opcodes/ChangeLog

   1 2019-07-30  Mel Chen <mel.chen@sifive.com>
   2
   3         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
   4         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
   5
   6         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
   7         fscsr.
   8
   9 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
  10
  11         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
  12         and MPY class instructions.
  13         (parse_option): Add nps400 option.
  14         (print_arc_disassembler_options): Add nps400 info.
  15
  16 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
  17
  18         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
  19         (bspop): Likewise.
  20         (modapp): Likewise.
  21         * arc-opc.c (RAD_CHK): Add.
  22         * arc-tbl.h: Regenerate.
  23
  24 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
  25
  26         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
  27         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
  28
  29 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
  30
  31         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
  32         instructions as UNPREDICTABLE.
  33
  34 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
  35
  36         * bpf-desc.c: Regenerated.
  37
  38 2019-07-17  Jan Beulich  <jbeulich@suse.com>
  39
  40         * i386-gen.c (static_assert): Define.
  41         (main): Use it.
  42         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
  43         (Opcode_Modifier_Num): ... this.
  44         (Mem): Delete.
  45
  46 2019-07-16  Jan Beulich  <jbeulich@suse.com>
  47
  48         * i386-gen.c (operand_types): Move RegMem ...
  49         (opcode_modifiers): ... here.
  50         * i386-opc.h (RegMem): Move to opcode modifer enum.
  51         (union i386_operand_type): Move regmem field ...
  52         (struct i386_opcode_modifier): ... here.
  53         * i386-opc.tbl (RegMem): Define.
  54         (mov, movq): Move RegMem on segment, control, debug, and test
  55         register flavors.
  56         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
  57         to non-SSE2AVX flavor.
  58         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
  59         Move RegMem on register only flavors. Drop IgnoreSize from
  60         legacy encoding flavors.
  61         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
  62         flavors.
  63         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
  64         register only flavors.
  65         (vmovd): Move RegMem and drop IgnoreSize on register only
  66         flavor. Change opcode and operand order to store form.
  67         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  68
  69 2019-07-16  Jan Beulich  <jbeulich@suse.com>
  70
  71         * i386-gen.c (operand_type_init, operand_types): Replace SReg
  72         entries.
  73         * i386-opc.h (SReg2, SReg3): Replace by ...
  74         (SReg): ... this.
  75         (union i386_operand_type): Replace sreg fields.
  76         * i386-opc.tbl (mov, ): Use SReg.
  77         (push, pop): Likewies. Drop i386 and x86-64 specific segment
  78         register flavors.
  79         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
  80         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  81
  82 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
  83
  84         * bpf-desc.c: Regenerate.
  85         * bpf-opc.c: Likewise.
  86         * bpf-opc.h: Likewise.
  87
  88 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
  89
  90         * bpf-desc.c: Regenerate.
  91         * bpf-opc.c: Likewise.
  92
  93 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
  94
  95         * arm-dis.c (print_insn_coprocessor): Rename index to
  96         index_operand.
  97
  98 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
  99
 100         * riscv-opc.c (riscv_insn_types): Add r4 type.
 101
 102         * riscv-opc.c (riscv_insn_types): Add b and j type.
 103
 104         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 105         format for sb type and correct s type.
 106
 107 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 108
 109         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 110         SVE FMOV alias of FCPY.
 111
 112 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 113
 114         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 115         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 116
 117 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 118
 119         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 120         registers in an instruction prefixed by MOVPRFX.
 121
 122 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 123
 124         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 125         sve_size_13 icode to account for variant behaviour of
 126         pmull{t,b}.
 127         * aarch64-dis-2.c: Regenerate.
 128         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 129         sve_size_13 icode to account for variant behaviour of
 130         pmull{t,b}.
 131         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 132         (OP_SVE_VVV_Q_D): Add new qualifier.
 133         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 134         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 135         AES and those not.
 136
 137 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 138
 139         * opcodes/i386-gen.c (operand_type_init): Remove
 140         OPERAND_TYPE_VEC_IMM4 entry.
 141         (operand_types): Remove Vec_Imm4.
 142         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 143         (union i386_operand_type): Remove vec_imm4.
 144         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 145         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 146
 147 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 148
 149         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 150         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 151         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 152         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 153         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 154         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 155         * i386-tbl.h: Re-generate.
 156
 157 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 158
 159         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 160         register operands.
 161         * i386-tbl.h: Re-generate.
 162
 163 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 164
 165         * i386-opc.tbl (C): New.
 166         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 167         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 168         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 169         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 170         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 171         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 172         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 173         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 174         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 175         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 176         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 177         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 178         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 179         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 180         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 181         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 182         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 183         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 184         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 185         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 186         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 187         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 188         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 189         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 190         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 191         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 192         flavors.
 193         * i386-tbl.h: Re-generate.
 194
 195 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 196
 197         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 198         register operands.
 199         * i386-tbl.h: Re-generate.
 200
 201 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 202
 203         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 204         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 205         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 206         * i386-tbl.h: Re-generate.
 207
 208 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 209
 210         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 211         Disp8MemShift from register only templates.
 212         * i386-tbl.h: Re-generate.
 213
 214 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 215
 216         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 217         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 218         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 219         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 220         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 221         EVEX_W_0F11_P_3_M_1): Delete.
 222         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 223         EVEX_W_0F11_P_3): New.
 224         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 225         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 226         MOD_EVEX_0F11_PREFIX_3 table entries.
 227         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 228         PREFIX_EVEX_0F11 table entries.
 229         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 230         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 231         EVEX_W_0F11_P_3_M_{0,1} table entries.
 232
 233 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 234
 235         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 236         Delete.
 237
 238 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 239
 240         PR binutils/24719
 241         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 242         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 243         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 244         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 245         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 246         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 247         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 248         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 249         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 250         PREFIX_EVEX_0F38C6_REG_6 entries.
 251         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 252         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 253         EVEX_W_0F38C7_R_6_P_2 entries.
 254         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 255         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 256         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 257         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 258         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 259         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 260         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 261
 262 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 263
 264         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 265         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 266         VEX_LEN_0F2D_P_3): Delete.
 267         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 268         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 269         (prefix_table): ... here.
 270
 271 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 272
 273         * i386-dis.c (Iq): Delete.
 274         (Id): New.
 275         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 276         TBM insns.
 277         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 278         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 279         (OP_E_memory): Also honor needindex when deciding whether an
 280         address size prefix needs printing.
 281         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 282
 283 2019-06-26  Jim Wilson  <jimw@sifive.com>
 284
 285         PR binutils/24739
 286         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 287         Set info->display_endian to info->endian_code.
 288
 289 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 290
 291         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 292         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 293         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 294         OPERAND_TYPE_ACC64 entries.
 295         * i386-init.h: Re-generate.
 296
 297 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 298
 299         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 300         Delete.
 301         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 302         of dqa_mode.
 303         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 304         entries here.
 305         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 306         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 307
 308 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 309
 310         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 311         variables.
 312
 313 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 314
 315         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 316         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 317         movnti.
 318         * i386-opc.tbl (movnti): Add IgnoreSize.
 319         * i386-tbl.h: Re-generate.
 320
 321 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 322
 323         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 324         * i386-tbl.h: Re-generate.
 325
 326 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 327
 328         * i386-dis-evex.h: Break into ...
 329         * i386-dis-evex-len.h: New file.
 330         * i386-dis-evex-mod.h: Likewise.
 331         * i386-dis-evex-prefix.h: Likewise.
 332         * i386-dis-evex-reg.h: Likewise.
 333         * i386-dis-evex-w.h: Likewise.
 334         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 335         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 336         i386-dis-evex-mod.h.
 337
 338 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 339
 340         PR binutils/24700
 341         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 342         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 343         EVEX_W_0F385B_P_2.
 344         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 345         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 346         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 347         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 348         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 349         EVEX_LEN_0F385B_P_2_W_1.
 350         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 351         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 352         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 353         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 354         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 355         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 356         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 357         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 358         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 359         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 360
 361 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 362
 363         PR binutils/24691
 364         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 365         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 366         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 367         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 368         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 369         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 370         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 371         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 372         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 373         EVEX_LEN_0F3A43_P_2_W_1.
 374         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 375         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 376         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 377         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 378         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 379         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 380         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 381         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 382         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 383         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 384         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 385         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 386
 387 2019-06-14  Nick Clifton  <nickc@redhat.com>
 388
 389         * po/fr.po; Updated French translation.
 390
 391 2019-06-13  Stafford Horne  <shorne@gmail.com>
 392
 393         * or1k-asm.c: Regenerated.
 394         * or1k-desc.c: Regenerated.
 395         * or1k-desc.h: Regenerated.
 396         * or1k-dis.c: Regenerated.
 397         * or1k-ibld.c: Regenerated.
 398         * or1k-opc.c: Regenerated.
 399         * or1k-opc.h: Regenerated.
 400         * or1k-opinst.c: Regenerated.
 401
 402 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 403
 404         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 405
 406 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 407
 408         PR binutils/24633
 409         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 410         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 411         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 412         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 413         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 414         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 415         EVEX_LEN_0F3A1B_P_2_W_1.
 416         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 417         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 418         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 419         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 420         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 421         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 422         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 423         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 424
 425 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 426
 427         PR binutils/24626
 428         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 429         EVEX.vvvv when disassembling VEX and EVEX instructions.
 430         (OP_VEX): Set vex.register_specifier to 0 after readding
 431         vex.register_specifier.
 432         (OP_Vex_2src_1): Likewise.
 433         (OP_Vex_2src_2): Likewise.
 434         (OP_LWP_E): Likewise.
 435         (OP_EX_Vex): Don't check vex.register_specifier.
 436         (OP_XMM_Vex): Likewise.
 437
 438 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 439             Lili Cui  <lili.cui@intel.com>
 440
 441         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 442         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 443         instructions.
 444         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 445         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 446         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 447         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 448         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 449         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 450         * i386-init.h: Regenerated.
 451         * i386-tbl.h: Likewise.
 452
 453 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 454             Lili Cui  <lili.cui@intel.com>
 455
 456         * doc/c-i386.texi: Document enqcmd.
 457         * testsuite/gas/i386/enqcmd-intel.d: New file.
 458         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 459         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 460         * testsuite/gas/i386/enqcmd.d: Likewise.
 461         * testsuite/gas/i386/enqcmd.s: Likewise.
 462         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 463         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 464         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 465         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 466         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 467         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 468         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 469         and x86-64-enqcmd.
 470
 471 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 472
 473         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 474
 475 2019-06-03  Alan Modra  <amodra@gmail.com>
 476
 477         * ppc-dis.c (prefix_opcd_indices): Correct size.
 478
 479 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 480
 481         PR gas/24625
 482         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 483         Disp8ShiftVL.
 484         * i386-tbl.h: Regenerated.
 485
 486 2019-05-24  Alan Modra  <amodra@gmail.com>
 487
 488         * po/POTFILES.in: Regenerate.
 489
 490 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 491             Alan Modra  <amodra@gmail.com>
 492
 493         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 494         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 495         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 496         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 497         XTOP>): Define and add entries.
 498         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 499         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 500         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 501         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 502
 503 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 504             Alan Modra  <amodra@gmail.com>
 505
 506         * ppc-dis.c (ppc_opts): Add "future" entry.
 507         (PREFIX_OPCD_SEGS): Define.
 508         (prefix_opcd_indices): New array.
 509         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 510         (lookup_prefix): New function.
 511         (print_insn_powerpc): Handle 64-bit prefix instructions.
 512         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 513         (PMRR, POWERXX): Define.
 514         (prefix_opcodes): New instruction table.
 515         (prefix_num_opcodes): New constant.
 516
 517 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 518
 519         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 520         * configure: Regenerated.
 521         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 522         and cpu/bpf.opc.
 523         (HFILES): Add bpf-desc.h and bpf-opc.h.
 524         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 525         bpf-ibld.c and bpf-opc.c.
 526         (BPF_DEPS): Define.
 527         * Makefile.in: Regenerated.
 528         * disassemble.c (ARCH_bpf): Define.
 529         (disassembler): Add case for bfd_arch_bpf.
 530         (disassemble_init_for_target): Likewise.
 531         (enum epbf_isa_attr): Define.
 532         * disassemble.h: extern print_insn_bpf.
 533         * bpf-asm.c: Generated.
 534         * bpf-opc.h: Likewise.
 535         * bpf-opc.c: Likewise.
 536         * bpf-ibld.c: Likewise.
 537         * bpf-dis.c: Likewise.
 538         * bpf-desc.h: Likewise.
 539         * bpf-desc.c: Likewise.
 540
 541 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 542
 543         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 544         and VMSR with the new operands.
 545
 546 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 547
 548         * arm-dis.c (enum mve_instructions): New enum
 549         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 550         and cneg.
 551         (mve_opcodes): New instructions as above.
 552         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 553         csneg and csel.
 554         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 555
 556 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 557
 558         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 559         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 560         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 561         uqshl, urshrl and urshr.
 562         (is_mve_okay_in_it): Add new instructions to TRUE list.
 563         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 564         (print_insn_mve): Updated to accept new %j,
 565         %<bitfield>m and %<bitfield>n patterns.
 566
 567 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 568
 569         * mips-opc.c (mips_builtin_opcodes): Change source register
 570         constraint for DAUI.
 571
 572 2019-05-20  Nick Clifton  <nickc@redhat.com>
 573
 574         * po/fr.po: Updated French translation.
 575
 576 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 577             Michael Collison <michael.collison@arm.com>
 578
 579         * arm-dis.c (thumb32_opcodes): Add new instructions.
 580         (enum mve_instructions): Likewise.
 581         (enum mve_undefined): Add new reasons.
 582         (is_mve_encoding_conflict): Handle new instructions.
 583         (is_mve_undefined): Likewise.
 584         (is_mve_unpredictable): Likewise.
 585         (print_mve_undefined): Likewise.
 586         (print_mve_size): Likewise.
 587
 588 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 589             Michael Collison <michael.collison@arm.com>
 590
 591         * arm-dis.c (thumb32_opcodes): Add new instructions.
 592         (enum mve_instructions): Likewise.
 593         (is_mve_encoding_conflict): Handle new instructions.
 594         (is_mve_undefined): Likewise.
 595         (is_mve_unpredictable): Likewise.
 596         (print_mve_size): Likewise.
 597
 598 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 599             Michael Collison <michael.collison@arm.com>
 600
 601         * arm-dis.c (thumb32_opcodes): Add new instructions.
 602         (enum mve_instructions): Likewise.
 603         (is_mve_encoding_conflict): Likewise.
 604         (is_mve_unpredictable): Likewise.
 605         (print_mve_size): Likewise.
 606
 607 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 608             Michael Collison <michael.collison@arm.com>
 609
 610         * arm-dis.c (thumb32_opcodes): Add new instructions.
 611         (enum mve_instructions): Likewise.
 612         (is_mve_encoding_conflict): Handle new instructions.
 613         (is_mve_undefined): Likewise.
 614         (is_mve_unpredictable): Likewise.
 615         (print_mve_size): Likewise.
 616
 617 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 618             Michael Collison <michael.collison@arm.com>
 619
 620         * arm-dis.c (thumb32_opcodes): Add new instructions.
 621         (enum mve_instructions): Likewise.
 622         (is_mve_encoding_conflict): Handle new instructions.
 623         (is_mve_undefined): Likewise.
 624         (is_mve_unpredictable): Likewise.
 625         (print_mve_size): Likewise.
 626         (print_insn_mve): Likewise.
 627
 628 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 629             Michael Collison <michael.collison@arm.com>
 630
 631         * arm-dis.c (thumb32_opcodes): Add new instructions.
 632         (print_insn_thumb32): Handle new instructions.
 633
 634 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 635             Michael Collison <michael.collison@arm.com>
 636
 637         * arm-dis.c (enum mve_instructions): Add new instructions.
 638         (enum mve_undefined): Add new reasons.
 639         (is_mve_encoding_conflict): Handle new instructions.
 640         (is_mve_undefined): Likewise.
 641         (is_mve_unpredictable): Likewise.
 642         (print_mve_undefined): Likewise.
 643         (print_mve_size): Likewise.
 644         (print_mve_shift_n): Likewise.
 645         (print_insn_mve): Likewise.
 646
 647 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 648             Michael Collison <michael.collison@arm.com>
 649
 650         * arm-dis.c (enum mve_instructions): Add new instructions.
 651         (is_mve_encoding_conflict): Handle new instructions.
 652         (is_mve_unpredictable): Likewise.
 653         (print_mve_rotate): Likewise.
 654         (print_mve_size): Likewise.
 655         (print_insn_mve): Likewise.
 656
 657 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 658             Michael Collison <michael.collison@arm.com>
 659
 660         * arm-dis.c (enum mve_instructions): Add new instructions.
 661         (is_mve_encoding_conflict): Handle new instructions.
 662         (is_mve_unpredictable): Likewise.
 663         (print_mve_size): Likewise.
 664         (print_insn_mve): Likewise.
 665
 666 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 667             Michael Collison <michael.collison@arm.com>
 668
 669         * arm-dis.c (enum mve_instructions): Add new instructions.
 670         (enum mve_undefined): Add new reasons.
 671         (is_mve_encoding_conflict): Handle new instructions.
 672         (is_mve_undefined): Likewise.
 673         (is_mve_unpredictable): Likewise.
 674         (print_mve_undefined): Likewise.
 675         (print_mve_size): Likewise.
 676         (print_insn_mve): Likewise.
 677
 678 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 679             Michael Collison <michael.collison@arm.com>
 680
 681         * arm-dis.c (enum mve_instructions): Add new instructions.
 682         (is_mve_encoding_conflict): Handle new instructions.
 683         (is_mve_undefined): Likewise.
 684         (is_mve_unpredictable): Likewise.
 685         (print_mve_size): Likewise.
 686         (print_insn_mve): Likewise.
 687
 688 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 689             Michael Collison <michael.collison@arm.com>
 690
 691         * arm-dis.c (enum mve_instructions): Add new instructions.
 692         (enum mve_unpredictable): Add new reasons.
 693         (enum mve_undefined): Likewise.
 694         (is_mve_okay_in_it): Handle new isntructions.
 695         (is_mve_encoding_conflict): Likewise.
 696         (is_mve_undefined): Likewise.
 697         (is_mve_unpredictable): Likewise.
 698         (print_mve_vmov_index): Likewise.
 699         (print_simd_imm8): Likewise.
 700         (print_mve_undefined): Likewise.
 701         (print_mve_unpredictable): Likewise.
 702         (print_mve_size): Likewise.
 703         (print_insn_mve): Likewise.
 704
 705 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 706             Michael Collison <michael.collison@arm.com>
 707
 708         * arm-dis.c (enum mve_instructions): Add new instructions.
 709         (enum mve_unpredictable): Add new reasons.
 710         (enum mve_undefined): Likewise.
 711         (is_mve_encoding_conflict): Handle new instructions.
 712         (is_mve_undefined): Likewise.
 713         (is_mve_unpredictable): Likewise.
 714         (print_mve_undefined): Likewise.
 715         (print_mve_unpredictable): Likewise.
 716         (print_mve_rounding_mode): Likewise.
 717         (print_mve_vcvt_size): Likewise.
 718         (print_mve_size): Likewise.
 719         (print_insn_mve): Likewise.
 720
 721 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 722             Michael Collison <michael.collison@arm.com>
 723
 724         * arm-dis.c (enum mve_instructions): Add new instructions.
 725         (enum mve_unpredictable): Add new reasons.
 726         (enum mve_undefined): Likewise.
 727         (is_mve_undefined): Handle new instructions.
 728         (is_mve_unpredictable): Likewise.
 729         (print_mve_undefined): Likewise.
 730         (print_mve_unpredictable): Likewise.
 731         (print_mve_size): Likewise.
 732         (print_insn_mve): Likewise.
 733
 734 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 735             Michael Collison <michael.collison@arm.com>
 736
 737         * arm-dis.c (enum mve_instructions): Add new instructions.
 738         (enum mve_undefined): Add new reasons.
 739         (insns): Add new instructions.
 740         (is_mve_encoding_conflict):
 741         (print_mve_vld_str_addr): New print function.
 742         (is_mve_undefined): Handle new instructions.
 743         (is_mve_unpredictable): Likewise.
 744         (print_mve_undefined): Likewise.
 745         (print_mve_size): Likewise.
 746         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 747         (print_insn_mve):  Handle new operands.
 748
 749 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 750             Michael Collison <michael.collison@arm.com>
 751
 752         * arm-dis.c (enum mve_instructions): Add new instructions.
 753         (enum mve_unpredictable): Add new reasons.
 754         (is_mve_encoding_conflict): Handle new instructions.
 755         (is_mve_unpredictable): Likewise.
 756         (mve_opcodes): Add new instructions.
 757         (print_mve_unpredictable): Handle new reasons.
 758         (print_mve_register_blocks): New print function.
 759         (print_mve_size): Handle new instructions.
 760         (print_insn_mve): Likewise.
 761
 762 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 763             Michael Collison <michael.collison@arm.com>
 764
 765         * arm-dis.c (enum mve_instructions): Add new instructions.
 766         (enum mve_unpredictable): Add new reasons.
 767         (enum mve_undefined): Likewise.
 768         (is_mve_encoding_conflict): Handle new instructions.
 769         (is_mve_undefined): Likewise.
 770         (is_mve_unpredictable): Likewise.
 771         (coprocessor_opcodes): Move NEON VDUP from here...
 772         (neon_opcodes): ... to here.
 773         (mve_opcodes): Add new instructions.
 774         (print_mve_undefined):  Handle new reasons.
 775         (print_mve_unpredictable): Likewise.
 776         (print_mve_size): Handle new instructions.
 777         (print_insn_neon): Handle vdup.
 778         (print_insn_mve): Handle new operands.
 779
 780 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 781             Michael Collison <michael.collison@arm.com>
 782
 783         * arm-dis.c (enum mve_instructions): Add new instructions.
 784         (enum mve_unpredictable): Add new values.
 785         (mve_opcodes): Add new instructions.
 786         (vec_condnames): New array with vector conditions.
 787         (mve_predicatenames): New array with predicate suffixes.
 788         (mve_vec_sizename): New array with vector sizes.
 789         (enum vpt_pred_state): New enum with vector predication states.
 790         (struct vpt_block): New struct type for vpt blocks.
 791         (vpt_block_state): Global struct to keep track of state.
 792         (mve_extract_pred_mask): New helper function.
 793         (num_instructions_vpt_block): Likewise.
 794         (mark_outside_vpt_block): Likewise.
 795         (mark_inside_vpt_block): Likewise.
 796         (invert_next_predicate_state): Likewise.
 797         (update_next_predicate_state): Likewise.
 798         (update_vpt_block_state): Likewise.
 799         (is_vpt_instruction): Likewise.
 800         (is_mve_encoding_conflict): Add entries for new instructions.
 801         (is_mve_unpredictable): Likewise.
 802         (print_mve_unpredictable): Handle new cases.
 803         (print_instruction_predicate): Likewise.
 804         (print_mve_size): New function.
 805         (print_vec_condition): New function.
 806         (print_insn_mve): Handle vpt blocks and new print operands.
 807
 808 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 809
 810         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 811         8, 14 and 15 for Armv8.1-M Mainline.
 812
 813 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 814             Michael Collison <michael.collison@arm.com>
 815
 816         * arm-dis.c (enum mve_instructions): New enum.
 817         (enum mve_unpredictable): Likewise.
 818         (enum mve_undefined): Likewise.
 819         (struct mopcode32): New struct.
 820         (is_mve_okay_in_it): New function.
 821         (is_mve_architecture): Likewise.
 822         (arm_decode_field): Likewise.
 823         (arm_decode_field_multiple): Likewise.
 824         (is_mve_encoding_conflict): Likewise.
 825         (is_mve_undefined): Likewise.
 826         (is_mve_unpredictable): Likewise.
 827         (print_mve_undefined): Likewise.
 828         (print_mve_unpredictable): Likewise.
 829         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 830         (print_insn_mve): New function.
 831         (print_insn_thumb32): Handle MVE architecture.
 832         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 833
 834 2019-05-10  Nick Clifton  <nickc@redhat.com>
 835
 836         PR 24538
 837         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 838         end of the table prematurely.
 839
 840 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 841
 842         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 843         macros for R6.
 844
 845 2019-05-11  Alan Modra  <amodra@gmail.com>
 846
 847         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 848         when -Mraw is in effect.
 849
 850 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 851
 852         * aarch64-dis-2.c: Regenerate.
 853         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 854         (OP_SVE_BBB): New variant set.
 855         (OP_SVE_DDDD): New variant set.
 856         (OP_SVE_HHH): New variant set.
 857         (OP_SVE_HHHU): New variant set.
 858         (OP_SVE_SSS): New variant set.
 859         (OP_SVE_SSSU): New variant set.
 860         (OP_SVE_SHH): New variant set.
 861         (OP_SVE_SBBU): New variant set.
 862         (OP_SVE_DSS): New variant set.
 863         (OP_SVE_DHHU): New variant set.
 864         (OP_SVE_VMV_HSD_BHS): New variant set.
 865         (OP_SVE_VVU_HSD_BHS): New variant set.
 866         (OP_SVE_VVVU_SD_BH): New variant set.
 867         (OP_SVE_VVVU_BHSD): New variant set.
 868         (OP_SVE_VVV_QHD_DBS): New variant set.
 869         (OP_SVE_VVV_HSD_BHS): New variant set.
 870         (OP_SVE_VVV_HSD_BHS2): New variant set.
 871         (OP_SVE_VVV_BHS_HSD): New variant set.
 872         (OP_SVE_VV_BHS_HSD): New variant set.
 873         (OP_SVE_VVV_SD): New variant set.
 874         (OP_SVE_VVU_BHS_HSD): New variant set.
 875         (OP_SVE_VZVV_SD): New variant set.
 876         (OP_SVE_VZVV_BH): New variant set.
 877         (OP_SVE_VZV_SD): New variant set.
 878         (aarch64_opcode_table): Add sve2 instructions.
 879
 880 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 881
 882         * aarch64-asm-2.c: Regenerated.
 883         * aarch64-dis-2.c: Regenerated.
 884         * aarch64-opc-2.c: Regenerated.
 885         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 886         for SVE_SHLIMM_UNPRED_22.
 887         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 888         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 889         operand.
 890
 891 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 892
 893         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 894         sve_size_tsz_bhs iclass encode.
 895         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 896         sve_size_tsz_bhs iclass decode.
 897
 898 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 899
 900         * aarch64-asm-2.c: Regenerated.
 901         * aarch64-dis-2.c: Regenerated.
 902         * aarch64-opc-2.c: Regenerated.
 903         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 904         for SVE_Zm4_11_INDEX.
 905         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 906         (fields): Handle SVE_i2h field.
 907         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 908         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 909
 910 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 911
 912         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 913         sve_shift_tsz_bhsd iclass encode.
 914         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 915         sve_shift_tsz_bhsd iclass decode.
 916
 917 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 918
 919         * aarch64-asm-2.c: Regenerated.
 920         * aarch64-dis-2.c: Regenerated.
 921         * aarch64-opc-2.c: Regenerated.
 922         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 923         (aarch64_encode_variant_using_iclass): Handle
 924         sve_shift_tsz_hsd iclass encode.
 925         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 926         sve_shift_tsz_hsd iclass decode.
 927         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 928         for SVE_SHRIMM_UNPRED_22.
 929         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 930         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 931         operand.
 932
 933 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 934
 935         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 936         sve_size_013 iclass encode.
 937         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 938         sve_size_013 iclass decode.
 939
 940 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 941
 942         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 943         sve_size_bh iclass encode.
 944         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 945         sve_size_bh iclass decode.
 946
 947 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 948
 949         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 950         sve_size_sd2 iclass encode.
 951         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 952         sve_size_sd2 iclass decode.
 953         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 954         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 955
 956 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 957
 958         * aarch64-asm-2.c: Regenerated.
 959         * aarch64-dis-2.c: Regenerated.
 960         * aarch64-opc-2.c: Regenerated.
 961         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 962         for SVE_ADDR_ZX.
 963         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 964         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 965
 966 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 967
 968         * aarch64-asm-2.c: Regenerated.
 969         * aarch64-dis-2.c: Regenerated.
 970         * aarch64-opc-2.c: Regenerated.
 971         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 972         for SVE_Zm3_11_INDEX.
 973         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 974         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 975         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 976         fields.
 977         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 978
 979 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 980
 981         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 982         sve_size_hsd2 iclass encode.
 983         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 984         sve_size_hsd2 iclass decode.
 985         * aarch64-opc.c (fields): Handle SVE_size field.
 986         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 987
 988 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 989
 990         * aarch64-asm-2.c: Regenerated.
 991         * aarch64-dis-2.c: Regenerated.
 992         * aarch64-opc-2.c: Regenerated.
 993         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 994         for SVE_IMM_ROT3.
 995         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 996         (fields): Handle SVE_rot3 field.
 997         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 998         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 999
1000 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1001
1002         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1003         instructions.
1004
1005 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1006
1007         * aarch64-tbl.h
1008         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1009         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1010         aarch64_feature_sve2bitperm): New feature sets.
1011         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1012         for feature set addresses.
1013         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1014         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1015
1016 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1017             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1018
1019         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1020         argument and set ASE_EVA_R6 appropriately.
1021         (set_default_mips_dis_options): Pass ISA to above.
1022         (parse_mips_dis_option): Likewise.
1023         * mips-opc.c (EVAR6): New macro.
1024         (mips_builtin_opcodes): Add llwpe, scwpe.
1025
1026 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1027
1028         * aarch64-asm-2.c: Regenerated.
1029         * aarch64-dis-2.c: Regenerated.
1030         * aarch64-opc-2.c: Regenerated.
1031         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1032         AARCH64_OPND_TME_UIMM16.
1033         (aarch64_print_operand): Likewise.
1034         * aarch64-tbl.h (QL_IMM_NIL): New.
1035         (TME): New.
1036         (_TME_INSN): New.
1037         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1038
1039 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1040
1041         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1042
1043 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1044             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1045
1046         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1047
1048 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1049
1050         * s12z-opc.h: Add extern "C" bracketing to help
1051         users who wish to use this interface in c++ code.
1052
1053 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1054
1055         * s12z-opc.c (bm_decode): Handle bit map operations with the
1056         "reserved0" mode.
1057
1058 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1059
1060         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1061         specifier.  Add entries for VLDR and VSTR of system registers.
1062         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1063         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1064         of %J and %K format specifier.
1065
1066 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1067
1068         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1069         Add new entries for VSCCLRM instruction.
1070         (print_insn_coprocessor): Handle new %C format control code.
1071
1072 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1073
1074         * arm-dis.c (enum isa): New enum.
1075         (struct sopcode32): New structure.
1076         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1077         set isa field of all current entries to ANY.
1078         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1079         Only match an entry if its isa field allows the current mode.
1080
1081 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1082
1083         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1084         CLRM.
1085         (print_insn_thumb32): Add logic to print %n CLRM register list.
1086
1087 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1088
1089         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1090         and %Q patterns.
1091
1092 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1093
1094         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1095         (print_insn_thumb32): Edit the switch case for %Z.
1096
1097 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1098
1099         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1100
1101 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1102
1103         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1104
1105 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1106
1107         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1108
1109 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1110
1111         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1112         Arm register with r13 and r15 unpredictable.
1113         (thumb32_opcodes): New instructions for bfx and bflx.
1114
1115 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1116
1117         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1118
1119 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1120
1121         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1122
1123 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1124
1125         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1126
1127 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1128
1129         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1130
1131 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1132
1133         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1134         "optr". ("operator" is a reserved word in c++).
1135
1136 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1137
1138         * aarch64-opc.c (aarch64_print_operand): Add case for
1139         AARCH64_OPND_Rt_SP.
1140         (verify_constraints): Likewise.
1141         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1142         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1143         to accept Rt|SP as first operand.
1144         (AARCH64_OPERANDS): Add new Rt_SP.
1145         * aarch64-asm-2.c: Regenerated.
1146         * aarch64-dis-2.c: Regenerated.
1147         * aarch64-opc-2.c: Regenerated.
1148
1149 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1150
1151         * aarch64-asm-2.c: Regenerated.
1152         * aarch64-dis-2.c: Likewise.
1153         * aarch64-opc-2.c: Likewise.
1154         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1155
1156 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1157
1158         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1159
1160 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1161
1162         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1163         * i386-init.h: Regenerated.
1164
1165 2019-04-07  Alan Modra  <amodra@gmail.com>
1166
1167         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1168         op_separator to control printing of spaces, comma and parens
1169         rather than need_comma, need_paren and spaces vars.
1170
1171 2019-04-07  Alan Modra  <amodra@gmail.com>
1172
1173         PR 24421
1174         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1175         (print_insn_neon, print_insn_arm): Likewise.
1176
1177 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1178
1179         * i386-dis-evex.h (evex_table): Updated to support BF16
1180         instructions.
1181         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1182         and EVEX_W_0F3872_P_3.
1183         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1184         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1185         * i386-opc.h (enum): Add CpuAVX512_BF16.
1186         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1187         * i386-opc.tbl: Add AVX512 BF16 instructions.
1188         * i386-init.h: Regenerated.
1189         * i386-tbl.h: Likewise.
1190
1191 2019-04-05  Alan Modra  <amodra@gmail.com>
1192
1193         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1194         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1195         to favour printing of "-" branch hint when using the "y" bit.
1196         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1197
1198 2019-04-05  Alan Modra  <amodra@gmail.com>
1199
1200         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1201         opcode until first operand is output.
1202
1203 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1204
1205         PR gas/24349
1206         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1207         (valid_bo_post_v2): Add support for 'at' branch hints.
1208         (insert_bo): Only error on branch on ctr.
1209         (get_bo_hint_mask): New function.
1210         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1211         for inserting 'at' branch hints.
1212         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1213         for extracting 'at' branch hints.
1214         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1215         (BOE): Delete operand.
1216         (BOM, BOP): New operands.
1217         (RM): Update value.
1218         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1219         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1220         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1221         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1222         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1223         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1224         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1225         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1226         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1227         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1228         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1229         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1230         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1231         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1232         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1233         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1234         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1235         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1236         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1237         bttarl+>: New extended mnemonics.
1238
1239 2019-03-28  Alan Modra  <amodra@gmail.com>
1240
1241         PR 24390
1242         * ppc-opc.c (BTF): Define.
1243         (powerpc_opcodes): Use for mtfsb*.
1244         * ppc-dis.c (print_insn_powerpc): Print fields with both
1245         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1246
1247 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1248
1249         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1250         (mapping_symbol_for_insn): Implement new algorithm.
1251         (print_insn): Remove duplicate code.
1252
1253 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1254
1255         * aarch64-dis.c (print_insn_aarch64):
1256         Implement override.
1257
1258 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1259
1260         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1261         order.
1262
1263 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1264
1265         * aarch64-dis.c (last_stop_offset): New.
1266         (print_insn_aarch64): Use stop_offset.
1267
1268 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1269
1270         PR gas/24359
1271         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1272         CPU_ANY_AVX2_FLAGS.
1273         * i386-init.h: Regenerated.
1274
1275 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1276
1277         PR gas/24348
1278         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1279         vmovdqu16, vmovdqu32 and vmovdqu64.
1280         * i386-tbl.h: Regenerated.
1281
1282 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1283
1284         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1285         from vstrszb, vstrszh, and vstrszf.
1286
1287 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1288
1289         * s390-opc.txt: Add instruction descriptions.
1290
1291 2019-02-08  Jim Wilson  <jimw@sifive.com>
1292
1293         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1294         <bne>: Likewise.
1295
1296 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1297
1298         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1299
1300 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1301
1302         PR binutils/23212
1303         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1304         * aarch64-opc.c (verify_elem_sd): New.
1305         (fields): Add FLD_sz entr.
1306         * aarch64-tbl.h (_SIMD_INSN): New.
1307         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1308         fmulx scalar and vector by element isns.
1309
1310 2019-02-07  Nick Clifton  <nickc@redhat.com>
1311
1312         * po/sv.po: Updated Swedish translation.
1313
1314 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1315
1316         * s390-mkopc.c (main): Accept arch13 as cpu string.
1317         * s390-opc.c: Add new instruction formats and instruction opcode
1318         masks.
1319         * s390-opc.txt: Add new arch13 instructions.
1320
1321 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1322
1323         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1324         (aarch64_opcode): Change encoding for stg, stzg
1325         st2g and st2zg.
1326         * aarch64-asm-2.c: Regenerated.
1327         * aarch64-dis-2.c: Regenerated.
1328         * aarch64-opc-2.c: Regenerated.
1329
1330 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1331
1332         * aarch64-asm-2.c: Regenerated.
1333         * aarch64-dis-2.c: Likewise.
1334         * aarch64-opc-2.c: Likewise.
1335         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1336
1337 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1338             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1339
1340         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1341         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1342         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1343         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1344         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1345         case for ldstgv_indexed.
1346         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1347         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1348         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1349         * aarch64-asm-2.c: Regenerated.
1350         * aarch64-dis-2.c: Regenerated.
1351         * aarch64-opc-2.c: Regenerated.
1352
1353 2019-01-23  Nick Clifton  <nickc@redhat.com>
1354
1355         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1356
1357 2019-01-21  Nick Clifton  <nickc@redhat.com>
1358
1359         * po/de.po: Updated German translation.
1360         * po/uk.po: Updated Ukranian translation.
1361
1362 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1363         * mips-dis.c (mips_arch_choices): Fix typo in
1364         gs464, gs464e and gs264e descriptors.
1365
1366 2019-01-19  Nick Clifton  <nickc@redhat.com>
1367
1368         * configure: Regenerate.
1369         * po/opcodes.pot: Regenerate.
1370
1371 2018-06-24  Nick Clifton  <nickc@redhat.com>
1372
1373         2.32 branch created.
1374
1375 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1376
1377         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1378         if it is null.
1379         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1380         zero.
1381
1382 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1383
1384         * configure: Regenerate.
1385
1386 2019-01-07  Alan Modra  <amodra@gmail.com>
1387
1388         * configure: Regenerate.
1389         * po/POTFILES.in: Regenerate.
1390
1391 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1392
1393         * s12z-opc.c: New file.
1394         * s12z-opc.h: New file.
1395         * s12z-dis.c: Removed all code not directly related to display
1396         of instructions.  Used the interface provided by the new files
1397         instead.
1398         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1399         * Makefile.in: Regenerate.
1400         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1401         * configure: Regenerate.
1402
1403 2019-01-01  Alan Modra  <amodra@gmail.com>
1404
1405         Update year range in copyright notice of all files.
1406
1407 For older changes see ChangeLog-2018
1408 \f
1409 Copyright (C) 2019 Free Software Foundation, Inc.
1410
1411 Copying and distribution of this file, with or without modification,
1412 are permitted in any medium without royalty provided the copyright
1413 notice and this notice are preserved.
1414
1415 Local Variables:
1416 mode: change-log
1417 left-margin: 8
1418 fill-column: 74
1419 version-control: never
1420 End: