opcodes/ChangeLog

   1 2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
   2
   3         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
   4         of MSR PAN immediate operand.
   5
   6 2015-11-16  Nick Clifton  <nickc@redhat.com>
   7
   8         * rx-dis.c (condition_names): Replace always and never with
   9         invalid, since the always/never conditions can never be legal.
  10
  11 2015-11-13  Tristan Gingold  <gingold@adacore.com>
  12
  13         * configure: Regenerate.
  14
  15 2015-11-11  Alan Modra  <amodra@gmail.com>
  16             Peter Bergner <bergner@vnet.ibm.com>
  17
  18         * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
  19         Add PPC_OPCODE_VSX3 to the vsx entry.
  20         (powerpc_init_dialect): Set default dialect to power9.
  21         * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
  22         insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
  23         extract_l1 insert_xtq6, extract_xtq6): New static functions.
  24         (insert_esync): Test for illegal L operand value.
  25         (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
  26         XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
  27         XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
  28         XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
  29         PPCVSX3): New defines.
  30         (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
  31         fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
  32         <mcrxr>: Use XBFRARB_MASK.
  33         <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
  34         bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
  35         cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
  36         cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
  37         lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
  38         lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
  39         modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
  40         rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
  41         stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
  42         subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
  43         vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
  44         vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
  45         vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
  46         vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
  47         vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
  48         vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
  49         vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
  50         xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
  51         xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
  52         xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
  53         xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
  54         xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
  55         xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
  56         xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
  57         xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
  58         xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
  59         xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
  60         xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
  61         xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
  62         xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
  63         <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
  64         <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
  65
  66 2015-11-02  Nick Clifton  <nickc@redhat.com>
  67
  68         * rx-decode.opc (rx_decode_opcode): Decode extra NOP
  69         instructions.
  70         * rx-decode.c: Regenerate.
  71
  72 2015-11-02  Nick Clifton  <nickc@redhat.com>
  73
  74         * rx-decode.opc (rx_disp): If the displacement is zero, set the
  75         type to RX_Operand_Zero_Indirect.
  76         * rx-decode.c: Regenerate.
  77         * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
  78
  79 2015-10-28  Yao Qi  <yao.qi@linaro.org>
  80
  81         * aarch64-dis.c (aarch64_decode_insn): Add one argument
  82         noaliases_p.  Update comments.  Pass noaliases_p rather than
  83         no_aliases to aarch64_opcode_decode.
  84         (print_insn_aarch64_word): Pass no_aliases to
  85         aarch64_decode_insn.
  86
  87 2015-10-27  Vinay  <Vinay.G@kpit.com>
  88
  89         PR binutils/19159
  90         * rl78-decode.opc (MOV): Added offset to DE register in index
  91         addressing mode.
  92         * rl78-decode.c: Regenerate.
  93
  94 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
  95
  96         PR binutils/19158
  97         * rl78-decode.opc: Add 's' print operator to instructions that
  98         access system registers.
  99         * rl78-decode.c: Regenerate.
 100         * rl78-dis.c (print_insn_rl78_common): Decode all system
 101         registers.
 102
 103 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 104
 105         PR binutils/19157
 106         * rl78-decode.opc: Add 'a' print operator to mov instructions
 107         using stack pointer plus index addressing.
 108         * rl78-decode.c: Regenerate.
 109
 110 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 111
 112         * s390-opc.c: Fix comment.
 113         * s390-opc.txt: Change instruction type for troo, trot, trto, and
 114         trtt to RRF_U0RER since the second parameter does not need to be a
 115         register pair.
 116
 117 2015-10-08  Nick Clifton  <nickc@redhat.com>
 118
 119         * arc-dis.c (print_insn_arc): Initiallise insn array.
 120
 121 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 122
 123         * aarch64-dis.c (aarch64_ext_sysins_op): Access field
 124         'name' rather than 'template'.
 125         * aarch64-opc.c (aarch64_print_operand): Likewise.
 126
 127 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
 128
 129         * arc-dis.c: Revamped file for ARC support
 130         * arc-dis.h: Likewise.
 131         * arc-ext.c: Likewise.
 132         * arc-ext.h: Likewise.
 133         * arc-opc.c: Likewise.
 134         * arc-fxi.h: New file.
 135         * arc-regs.h: Likewise.
 136         * arc-tbl.h: Likewise.
 137
 138 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 139
 140         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
 141         argument insn type to aarch64_insn.  Rename to ...
 142         (aarch64_decode_insn): ... it.
 143         (print_insn_aarch64_word): Caller updated.
 144
 145 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 146
 147         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
 148         (print_insn_aarch64_word): Caller updated.
 149
 150 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 151
 152         * s390-mkopc.c (main): Parse htm and vx flag.
 153         * s390-opc.txt: Mark instructions from the hardware transactional
 154         memory and vector facilities with the "htm"/"vx" flag.
 155
 156 2015-09-28  Nick Clifton  <nickc@redhat.com>
 157
 158         * po/de.po: Updated German translation.
 159
 160 2015-09-28  Tom Rix  <tom@bumblecow.com>
 161
 162         * ppc-opc.c (PPC500): Mark some opcodes as invalid
 163
 164 2015-09-23  Nick Clifton  <nickc@redhat.com>
 165
 166         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
 167         function.
 168         * tic30-dis.c (print_branch): Likewise.
 169         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
 170         value before left shifting.
 171         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
 172         * hppa-dis.c (print_insn_hppa): Likewise.
 173         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
 174         array.
 175         * msp430-dis.c (msp430_singleoperand): Likewise.
 176         (msp430_doubleoperand): Likewise.
 177         (print_insn_msp430): Likewise.
 178         * nds32-asm.c (parse_operand): Likewise.
 179         * sh-opc.h (MASK): Likewise.
 180         * v850-dis.c (get_operand_value): Likewise.
 181
 182 2015-09-22  Nick Clifton  <nickc@redhat.com>
 183
 184         * rx-decode.opc (bwl): Use RX_Bad_Size.
 185         (sbwl): Likewise.
 186         (ubwl): Likewise.  Rename to ubw.
 187         (uBWL): Rename to uBW.
 188         Replace all references to uBWL with uBW.
 189         * rx-decode.c: Regenerate.
 190         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
 191         (opsize_names): Likewise.
 192         (print_insn_rx): Detect and report RX_Bad_Size.
 193
 194 2015-09-22  Anton Blanchard  <anton@samba.org>
 195
 196         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
 197
 198 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 199
 200         * sparc-dis.c (print_insn_sparc): Handle the privileged register
 201         %pmcdper.
 202
 203 2015-08-24  Jan Stancek  <jstancek@redhat.com>
 204
 205         * i386-dis.c (print_insn): Fix decoding of three byte operands.
 206
 207 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
 208
 209         PR binutils/18257
 210         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
 211         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
 212         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 213         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 214         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 215         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 216         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 217         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 218         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 219         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 220         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 221         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 222         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 223         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 224         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 225         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 226         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 227         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 228         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 229         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 230         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 231         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 232         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 233         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 234         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 235         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 236         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 237         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 238         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 239         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 240         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 241         (vex_w_table): Replace terminals with MOD_TABLE entries for
 242         most of mask instructions.
 243
 244 2015-08-17  Alan Modra  <amodra@gmail.com>
 245
 246         * cgen.sh: Trim trailing space from cgen output.
 247         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 248         (print_dis_table): Likewise.
 249         * opc2c.c (dump_lines): Likewise.
 250         (orig_filename): Warning fix.
 251         * ia64-asmtab.c: Regenerate.
 252
 253 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 254
 255         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 256         and higher with ARM instruction set will now mark the 26-bit
 257         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 258         (arm_opcodes): Fix for unpredictable nop being recognized as a
 259         teq.
 260
 261 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 262
 263         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 264         based on 'or' is first.
 265         * mips-opc.c (mips_builtin_opcodes): Ditto.
 266
 267 2015-08-11  Nick Clifton  <nickc@redhat.com>
 268
 269         PR 18800
 270         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 271         instruction.
 272
 273 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 274
 275         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 276
 277 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 278
 279         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 280         * i386-init.h: Regenerated.
 281
 282 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 283
 284         PR binutils/13571
 285         * i386-dis.c (MOD_0FC3): New.
 286         (PREFIX_0FC3): Renamed to ...
 287         (PREFIX_MOD_0_0FC3): This.
 288         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 289         (prefix_table): Replace Ma with Ev on movntiS.
 290         (mod_table): Add MOD_0FC3.
 291
 292 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 293
 294         * configure: Regenerated.
 295
 296 2015-07-23  Alan Modra  <amodra@gmail.com>
 297
 298         PR 18708
 299         * i386-dis.c (get64): Avoid signed integer overflow.
 300
 301 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 302
 303         PR binutils/18631
 304         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 305         "EXEvexHalfBcstXmmq" for the second operand.
 306         (EVEX_W_0F79_P_2): Likewise.
 307         (EVEX_W_0F7A_P_2): Likewise.
 308         (EVEX_W_0F7B_P_2): Likewise.
 309
 310 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 311
 312         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 313         float bitfield format.
 314         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 315         quarter float bitfield format.
 316
 317 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 318
 319         * configure: Regenerated.
 320
 321 2015-07-03  Alan Modra  <amodra@gmail.com>
 322
 323         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 324         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 325         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 326
 327 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 328             Cesar Philippidis  <cesar@codesourcery.com>
 329
 330         * nios2-dis.c (nios2_extract_opcode): New.
 331         (nios2_disassembler_state): New.
 332         (nios2_find_opcode_hash): Use mach parameter to select correct
 333         disassembler state.
 334         (nios2_print_insn_arg): Extend to support new R2 argument letters
 335         and formats.
 336         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 337         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 338         (NIOS2_NUM_OPCODES): Rename to...
 339         (NIOS2_NUM_R1_OPCODES): This.
 340         (nios2_r2_opcodes): New.
 341         (NIOS2_NUM_R2_OPCODES): New.
 342         (nios2_num_r2_opcodes): New.
 343         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 344         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 345         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 346         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 347         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 348
 349 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 350
 351         * i386-dis.c (OP_Mwaitx): New.
 352         (rm_table): Add monitorx/mwaitx.
 353         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 354         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 355         (operand_type_init): Add CpuMWAITX.
 356         * i386-opc.h (CpuMWAITX): New.
 357         (i386_cpu_flags): Add cpumwaitx.
 358         * i386-opc.tbl: Add monitorx and mwaitx.
 359         * i386-init.h: Regenerated.
 360         * i386-tbl.h: Likewise.
 361
 362 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 363
 364         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 365         (insert_esync): New function.
 366         (LS, WC): Use insert_ls.
 367         (ESYNC): Use insert_esync.
 368
 369 2015-06-22  Nick Clifton  <nickc@redhat.com>
 370
 371         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 372         requested region lies beyond it.
 373         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 374         looking for 32-bit insns.
 375         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 376         data.
 377         * sh-dis.c (print_insn_sh): Likewise.
 378         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 379         blocks of instructions.
 380         * vax-dis.c (print_insn_vax): Check that the requested address
 381         does not clash with the stop_vma.
 382
 383 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 384
 385         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 386         * ppc-opc.c (FXM4): Add non-zero optional value.
 387         (TBR): Likewise.
 388         (SXL): Likewise.
 389         (insert_fxm): Handle new default operand value.
 390         (extract_fxm): Likewise.
 391         (insert_tbr): Likewise.
 392         (extract_tbr): Likewise.
 393
 394 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 395
 396         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 397
 398 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 399
 400         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 401
 402 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 403
 404         * ppc-opc.c: Add comment accidentally removed by old commit.
 405         (MTMSRD_L): Delete.
 406
 407 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 408
 409         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 410
 411 2015-06-04  Nick Clifton  <nickc@redhat.com>
 412
 413         PR 18474
 414         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 415
 416 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 417
 418         * arm-dis.c (arm_opcodes): Add "setpan".
 419         (thumb_opcodes): Add "setpan".
 420
 421 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 422
 423         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 424         macros.
 425
 426 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 427
 428         * aarch64-tbl.h (aarch64_feature_rdma): New.
 429         (RDMA): New.
 430         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 431         * aarch64-asm-2.c: Regenerate.
 432         * aarch64-dis-2.c: Regenerate.
 433         * aarch64-opc-2.c: Regenerate.
 434
 435 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 436
 437         * aarch64-tbl.h (aarch64_feature_lor): New.
 438         (LOR): New.
 439         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 440         "stllrb", "stllrh".
 441         * aarch64-asm-2.c: Regenerate.
 442         * aarch64-dis-2.c: Regenerate.
 443         * aarch64-opc-2.c: Regenerate.
 444
 445 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 446
 447         * aarch64-opc.c (F_ARCHEXT): New.
 448         (aarch64_sys_regs): Add "pan".
 449         (aarch64_sys_reg_supported_p): New.
 450         (aarch64_pstatefields): Add "pan".
 451         (aarch64_pstatefield_supported_p): New.
 452
 453 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 454
 455         * i386-tbl.h: Regenerate.
 456
 457 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 458
 459         * i386-dis.c (print_insn): Swap rounding mode specifier and
 460         general purpose register in Intel mode.
 461
 462 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 463
 464         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 465         * i386-tbl.h: Regenerate.
 466
 467 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 468
 469         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 470         * i386-init.h: Regenerated.
 471
 472 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 473
 474         PR binutis/18386
 475         * i386-dis.c: Add comments for '@'.
 476         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 477         (enum x86_64_isa): New.
 478         (isa64): Likewise.
 479         (print_i386_disassembler_options): Add amd64 and intel64.
 480         (print_insn): Handle amd64 and intel64.
 481         (putop): Handle '@'.
 482         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 483         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 484         * i386-opc.h (AMD64): New.
 485         (CpuIntel64): Likewise.
 486         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 487         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 488         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 489         * i386-init.h: Regenerated.
 490         * i386-tbl.h: Likewise.
 491
 492 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 493
 494         * ppc-opc.c (IH) New define.
 495         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 496         <tlbie>: Add RS operand for POWER7.
 497         <slbia>: Add IH operand for POWER6.
 498
 499 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 500
 501         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 502         direct branch.
 503         (jmp): Likewise.
 504         * i386-tbl.h: Regenerated.
 505
 506 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 507
 508         * configure.ac: Support bfd_iamcu_arch.
 509         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 510         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 511         CPU_IAMCU_COMPAT_FLAGS.
 512         (cpu_flags): Add CpuIAMCU.
 513         * i386-opc.h (CpuIAMCU): New.
 514         (i386_cpu_flags): Add cpuiamcu.
 515         * configure: Regenerated.
 516         * i386-init.h: Likewise.
 517         * i386-tbl.h: Likewise.
 518
 519 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 520
 521         PR binutis/18386
 522         * i386-dis.c (X86_64_E8): New.
 523         (X86_64_E9): Likewise.
 524         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 525         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 526         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 527         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 528         (putop): Handle '^'.
 529         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 530         REX_W.
 531
 532 2015-04-30  DJ Delorie  <dj@redhat.com>
 533
 534         * disassemble.c (disassembler): Choose suitable disassembler based
 535         on E_ABI.
 536         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 537         it to decode mul/div insns.
 538         * rl78-decode.c: Regenerate.
 539         * rl78-dis.c (print_insn_rl78): Rename to...
 540         (print_insn_rl78_common): ...this, take ISA parameter.
 541         (print_insn_rl78): New.
 542         (print_insn_rl78_g10): New.
 543         (print_insn_rl78_g13): New.
 544         (print_insn_rl78_g14): New.
 545         (rl78_get_disassembler): New.
 546
 547 2015-04-29  Nick Clifton  <nickc@redhat.com>
 548
 549         * po/fr.po: Updated French translation.
 550
 551 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 552
 553         * ppc-opc.c (DCBT_EO): New define.
 554         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 555         <lharx>: Likewise.
 556         <stbcx.>: Likewise.
 557         <sthcx.>: Likewise.
 558         <waitrsv>: Do not enable for POWER7 and later.
 559         <waitimpl>: Likewise.
 560         <dcbt>: Default to the two operand form of the instruction for all
 561         "old" cpus.  For "new" cpus, use the operand ordering that matches
 562         whether the cpu is server or embedded.
 563         <dcbtst>: Likewise.
 564
 565 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 566
 567         * s390-opc.c: New instruction type VV0UU2.
 568         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 569         and WFC.
 570
 571 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 572
 573         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 574         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 575         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 576         (vfpclasspd, vfpclassps): Add %XZ.
 577
 578 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 579
 580         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 581         (PREFIX_UD_REPZ): Likewise.
 582         (PREFIX_UD_REPNZ): Likewise.
 583         (PREFIX_UD_DATA): Likewise.
 584         (PREFIX_UD_ADDR): Likewise.
 585         (PREFIX_UD_LOCK): Likewise.
 586
 587 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 588
 589         * i386-dis.c (prefix_requirement): Removed.
 590         (print_insn): Don't set prefix_requirement.  Check
 591         dp->prefix_requirement instead of prefix_requirement.
 592
 593 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 594
 595         PR binutils/17898
 596         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 597         (PREFIX_MOD_0_0FC7_REG_6): This.
 598         (PREFIX_MOD_3_0FC7_REG_6): New.
 599         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 600         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 601         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 602         PREFIX_MOD_3_0FC7_REG_7.
 603         (mod_table): Replace PREFIX_0FC7_REG_6 with
 604         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 605         PREFIX_MOD_3_0FC7_REG_7.
 606
 607 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 608
 609         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 610         (PREFIX_MANDATORY_REPNZ): Likewise.
 611         (PREFIX_MANDATORY_DATA): Likewise.
 612         (PREFIX_MANDATORY_ADDR): Likewise.
 613         (PREFIX_MANDATORY_LOCK): Likewise.
 614         (PREFIX_MANDATORY): Likewise.
 615         (PREFIX_UD_SHIFT): Set to 8
 616         (PREFIX_UD_REPZ): Updated.
 617         (PREFIX_UD_REPNZ): Likewise.
 618         (PREFIX_UD_DATA): Likewise.
 619         (PREFIX_UD_ADDR): Likewise.
 620         (PREFIX_UD_LOCK): Likewise.
 621         (PREFIX_IGNORED_SHIFT): New.
 622         (PREFIX_IGNORED_REPZ): Likewise.
 623         (PREFIX_IGNORED_REPNZ): Likewise.
 624         (PREFIX_IGNORED_DATA): Likewise.
 625         (PREFIX_IGNORED_ADDR): Likewise.
 626         (PREFIX_IGNORED_LOCK): Likewise.
 627         (PREFIX_OPCODE): Likewise.
 628         (PREFIX_IGNORED): Likewise.
 629         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 630         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 631         (three_byte_table): Likewise.
 632         (mod_table): Likewise.
 633         (mandatory_prefix): Renamed to ...
 634         (prefix_requirement): This.
 635         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 636         Update PREFIX_90 entry.
 637         (get_valid_dis386): Check prefix_requirement to see if a prefix
 638         should be ignored.
 639         (print_insn): Replace mandatory_prefix with prefix_requirement.
 640
 641 2015-04-15  Renlin Li  <renlin.li@arm.com>
 642
 643         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 644         use it for ssat and ssat16.
 645         (print_insn_thumb32): Add handle case for 'D' control code.
 646
 647 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 648             H.J. Lu  <hongjiu.lu@intel.com>
 649
 650         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 651         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 652         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 653         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 654         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 655         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 656         Fill prefix_requirement field.
 657         (struct dis386): Add prefix_requirement field.
 658         (dis386): Fill prefix_requirement field.
 659         (dis386_twobyte): Ditto.
 660         (twobyte_has_mandatory_prefix_: Remove.
 661         (reg_table): Fill prefix_requirement field.
 662         (prefix_table): Ditto.
 663         (x86_64_table): Ditto.
 664         (three_byte_table): Ditto.
 665         (xop_table): Ditto.
 666         (vex_table): Ditto.
 667         (vex_len_table): Ditto.
 668         (vex_w_table): Ditto.
 669         (mod_table): Ditto.
 670         (bad_opcode): Ditto.
 671         (print_insn): Use prefix_requirement.
 672         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 673         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 674         (float_reg): Ditto.
 675
 676 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 677
 678         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 679
 680 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 681
 682         * Makefile.in: Regenerated.
 683
 684 2015-03-25  Anton Blanchard  <anton@samba.org>
 685
 686         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 687         powerpc_opcd_indices and vle_opcd_indices once.
 688
 689 2015-03-25  Anton Blanchard  <anton@samba.org>
 690
 691         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 692
 693 2015-03-24  Terry Guo  <terry.guo@arm.com>
 694
 695         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 696         (opcode16): Likewise.
 697         (coprocessor_opcodes): Replace bit with feature struct.
 698         (neon_opcodes): Likewise.
 699         (arm_opcodes): Likewise.
 700         (thumb_opcodes): Likewise.
 701         (thumb32_opcodes): Likewise.
 702         (print_insn_coprocessor): Likewise.
 703         (print_insn_arm): Likewise.
 704         (select_arm_features): Follow new feature struct.
 705
 706 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 707
 708         * i386-dis.c (rm_table): Add clzero.
 709         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 710         Add CPU_CLZERO_FLAGS.
 711         (cpu_flags): Add CpuCLZERO.
 712         * i386-opc.h: Add CpuCLZERO.
 713         * i386-opc.tbl: Add clzero.
 714         * i386-init.h: Re-generated.
 715         * i386-tbl.h: Re-generated.
 716
 717 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 718
 719         * mips-opc.c (decode_mips_operand): Fix constraint issues
 720         with u and y operands.
 721
 722 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 723
 724         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 725
 726 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 727
 728         * s390-opc.c: Add new IBM z13 instructions.
 729         * s390-opc.txt: Likewise.
 730
 731 2015-03-10  Renlin Li  <renlin.li@arm.com>
 732
 733         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 734         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 735         related alias.
 736         * aarch64-asm-2.c: Regenerate.
 737         * aarch64-dis-2.c: Likewise.
 738         * aarch64-opc-2.c: Likewise.
 739
 740 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 741
 742         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 743
 744 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 745
 746         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 747         arch_sh_up.
 748         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 749         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 750
 751 2015-02-23  Vinay  <Vinay.G@kpit.com>
 752
 753         * rl78-decode.opc (MOV): Added space between two operands for
 754         'mov' instruction in index addressing mode.
 755         * rl78-decode.c: Regenerate.
 756
 757 2015-02-19  Pedro Alves  <palves@redhat.com>
 758
 759         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 760
 761 2015-02-10  Pedro Alves  <palves@redhat.com>
 762             Tom Tromey  <tromey@redhat.com>
 763
 764         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 765         microblaze_and, microblaze_xor.
 766         * microblaze-opc.h (opcodes): Adjust.
 767
 768 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 769
 770         * Makefile.am: Add FT32 files.
 771         * configure.ac: Handle FT32.
 772         * disassemble.c (disassembler): Call print_insn_ft32.
 773         * ft32-dis.c: New file.
 774         * ft32-opc.c: New file.
 775         * Makefile.in: Regenerate.
 776         * configure: Regenerate.
 777         * po/POTFILES.in: Regenerate.
 778
 779 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 780
 781         * nds32-asm.c (keyword_sr): Add new system registers.
 782
 783 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 784
 785         * s390-dis.c (s390_extract_operand): Support vector register
 786         operands.
 787         (s390_print_insn_with_opcode): Support new operands types and add
 788         new handling of optional operands.
 789         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 790         and include opcode/s390.h instead.
 791         (struct op_struct): New field `flags'.
 792         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 793         (dumpTable): Dump flags.
 794         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 795         string.
 796         * s390-opc.c: Add new operands types, instruction formats, and
 797         instruction masks.
 798         (s390_opformats): Add new formats for .insn.
 799         * s390-opc.txt: Add new instructions.
 800
 801 2015-01-01  Alan Modra  <amodra@gmail.com>
 802
 803         Update year range in copyright notice of all files.
 804
 805 For older changes see ChangeLog-2014
 806 \f
 807 Copyright (C) 2015 Free Software Foundation, Inc.
 808
 809 Copying and distribution of this file, with or without modification,
 810 are permitted in any medium without royalty provided the copyright
 811 notice and this notice are preserved.
 812
 813 Local Variables:
 814 mode: change-log
 815 left-margin: 8
 816 fill-column: 74
 817 version-control: never
 818 End: