opcodes/ChangeLog

   1 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
   2
   3         * aarch64-asm-2.c: Regenerated.
   4         * aarch64-dis-2.c: Regenerated.
   5         * aarch64-opc-2.c: Regenerated.
   6         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
   7         for SVE_ADDR_ZX.
   8         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
   9         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
  10
  11 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  12
  13         * aarch64-asm-2.c: Regenerated.
  14         * aarch64-dis-2.c: Regenerated.
  15         * aarch64-opc-2.c: Regenerated.
  16         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
  17         for SVE_Zm3_11_INDEX.
  18         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
  19         (fields): Handle SVE_i3l and SVE_i3h2 fields.
  20         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
  21         fields.
  22         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
  23
  24 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  25
  26         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
  27         sve_size_hsd2 iclass encode.
  28         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
  29         sve_size_hsd2 iclass decode.
  30         * aarch64-opc.c (fields): Handle SVE_size field.
  31         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
  32
  33 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  34
  35         * aarch64-asm-2.c: Regenerated.
  36         * aarch64-dis-2.c: Regenerated.
  37         * aarch64-opc-2.c: Regenerated.
  38         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
  39         for SVE_IMM_ROT3.
  40         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
  41         (fields): Handle SVE_rot3 field.
  42         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
  43         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
  44
  45 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  46
  47         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
  48         instructions.
  49
  50 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  51
  52         * aarch64-tbl.h
  53         (aarch64_feature_sve2, aarch64_feature_sve2aes,
  54         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
  55         aarch64_feature_sve2bitperm): New feature sets.
  56         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
  57         for feature set addresses.
  58         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
  59         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
  60
  61 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
  62             Faraz Shahbazker  <fshahbazker@wavecomp.com>
  63
  64         * mips-dis.c (mips_calculate_combination_ases): Add ISA
  65         argument and set ASE_EVA_R6 appropriately.
  66         (set_default_mips_dis_options): Pass ISA to above.
  67         (parse_mips_dis_option): Likewise.
  68         * mips-opc.c (EVAR6): New macro.
  69         (mips_builtin_opcodes): Add llwpe, scwpe.
  70
  71 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
  72
  73         * aarch64-asm-2.c: Regenerated.
  74         * aarch64-dis-2.c: Regenerated.
  75         * aarch64-opc-2.c: Regenerated.
  76         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
  77         AARCH64_OPND_TME_UIMM16.
  78         (aarch64_print_operand): Likewise.
  79         * aarch64-tbl.h (QL_IMM_NIL): New.
  80         (TME): New.
  81         (_TME_INSN): New.
  82         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
  83
  84 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
  85
  86         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
  87
  88 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
  89             Faraz Shahbazker  <fshahbazker@wavecomp.com>
  90
  91         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
  92
  93 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
  94
  95         * s12z-opc.h: Add extern "C" bracketing to help
  96         users who wish to use this interface in c++ code.
  97
  98 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
  99
 100         * s12z-opc.c (bm_decode): Handle bit map operations with the
 101         "reserved0" mode.
 102
 103 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 104
 105         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 106         specifier.  Add entries for VLDR and VSTR of system registers.
 107         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 108         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 109         of %J and %K format specifier.
 110
 111 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 112
 113         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 114         Add new entries for VSCCLRM instruction.
 115         (print_insn_coprocessor): Handle new %C format control code.
 116
 117 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 118
 119         * arm-dis.c (enum isa): New enum.
 120         (struct sopcode32): New structure.
 121         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 122         set isa field of all current entries to ANY.
 123         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 124         Only match an entry if its isa field allows the current mode.
 125
 126 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 127
 128         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 129         CLRM.
 130         (print_insn_thumb32): Add logic to print %n CLRM register list.
 131
 132 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 133
 134         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 135         and %Q patterns.
 136
 137 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 138
 139         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 140         (print_insn_thumb32): Edit the switch case for %Z.
 141
 142 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 143
 144         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 145
 146 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 147
 148         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 149
 150 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 151
 152         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 153
 154 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 155
 156         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 157         Arm register with r13 and r15 unpredictable.
 158         (thumb32_opcodes): New instructions for bfx and bflx.
 159
 160 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 161
 162         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 163
 164 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 165
 166         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 167
 168 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 169
 170         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 171
 172 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 173
 174         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 175
 176 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 177
 178         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 179         "optr". ("operator" is a reserved word in c++).
 180
 181 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 182
 183         * aarch64-opc.c (aarch64_print_operand): Add case for
 184         AARCH64_OPND_Rt_SP.
 185         (verify_constraints): Likewise.
 186         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 187         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 188         to accept Rt|SP as first operand.
 189         (AARCH64_OPERANDS): Add new Rt_SP.
 190         * aarch64-asm-2.c: Regenerated.
 191         * aarch64-dis-2.c: Regenerated.
 192         * aarch64-opc-2.c: Regenerated.
 193
 194 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 195
 196         * aarch64-asm-2.c: Regenerated.
 197         * aarch64-dis-2.c: Likewise.
 198         * aarch64-opc-2.c: Likewise.
 199         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 200
 201 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 202
 203         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 204
 205 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 206
 207         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 208         * i386-init.h: Regenerated.
 209
 210 2019-04-07  Alan Modra  <amodra@gmail.com>
 211
 212         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 213         op_separator to control printing of spaces, comma and parens
 214         rather than need_comma, need_paren and spaces vars.
 215
 216 2019-04-07  Alan Modra  <amodra@gmail.com>
 217
 218         PR 24421
 219         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 220         (print_insn_neon, print_insn_arm): Likewise.
 221
 222 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 223
 224         * i386-dis-evex.h (evex_table): Updated to support BF16
 225         instructions.
 226         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 227         and EVEX_W_0F3872_P_3.
 228         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 229         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 230         * i386-opc.h (enum): Add CpuAVX512_BF16.
 231         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 232         * i386-opc.tbl: Add AVX512 BF16 instructions.
 233         * i386-init.h: Regenerated.
 234         * i386-tbl.h: Likewise.
 235
 236 2019-04-05  Alan Modra  <amodra@gmail.com>
 237
 238         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 239         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 240         to favour printing of "-" branch hint when using the "y" bit.
 241         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 242
 243 2019-04-05  Alan Modra  <amodra@gmail.com>
 244
 245         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 246         opcode until first operand is output.
 247
 248 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 249
 250         PR gas/24349
 251         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 252         (valid_bo_post_v2): Add support for 'at' branch hints.
 253         (insert_bo): Only error on branch on ctr.
 254         (get_bo_hint_mask): New function.
 255         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 256         for inserting 'at' branch hints.
 257         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 258         for extracting 'at' branch hints.
 259         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 260         (BOE): Delete operand.
 261         (BOM, BOP): New operands.
 262         (RM): Update value.
 263         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 264         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 265         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 266         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 267         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 268         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 269         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 270         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 271         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 272         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 273         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 274         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 275         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 276         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 277         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 278         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 279         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 280         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 281         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 282         bttarl+>: New extended mnemonics.
 283
 284 2019-03-28  Alan Modra  <amodra@gmail.com>
 285
 286         PR 24390
 287         * ppc-opc.c (BTF): Define.
 288         (powerpc_opcodes): Use for mtfsb*.
 289         * ppc-dis.c (print_insn_powerpc): Print fields with both
 290         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 291
 292 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 293
 294         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 295         (mapping_symbol_for_insn): Implement new algorithm.
 296         (print_insn): Remove duplicate code.
 297
 298 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 299
 300         * aarch64-dis.c (print_insn_aarch64):
 301         Implement override.
 302
 303 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 304
 305         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 306         order.
 307
 308 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 309
 310         * aarch64-dis.c (last_stop_offset): New.
 311         (print_insn_aarch64): Use stop_offset.
 312
 313 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 314
 315         PR gas/24359
 316         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 317         CPU_ANY_AVX2_FLAGS.
 318         * i386-init.h: Regenerated.
 319
 320 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 321
 322         PR gas/24348
 323         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 324         vmovdqu16, vmovdqu32 and vmovdqu64.
 325         * i386-tbl.h: Regenerated.
 326
 327 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 328
 329         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 330         from vstrszb, vstrszh, and vstrszf.
 331
 332 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 333
 334         * s390-opc.txt: Add instruction descriptions.
 335
 336 2019-02-08  Jim Wilson  <jimw@sifive.com>
 337
 338         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 339         <bne>: Likewise.
 340
 341 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 342
 343         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 344
 345 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 346
 347         PR binutils/23212
 348         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 349         * aarch64-opc.c (verify_elem_sd): New.
 350         (fields): Add FLD_sz entr.
 351         * aarch64-tbl.h (_SIMD_INSN): New.
 352         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 353         fmulx scalar and vector by element isns.
 354
 355 2019-02-07  Nick Clifton  <nickc@redhat.com>
 356
 357         * po/sv.po: Updated Swedish translation.
 358
 359 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 360
 361         * s390-mkopc.c (main): Accept arch13 as cpu string.
 362         * s390-opc.c: Add new instruction formats and instruction opcode
 363         masks.
 364         * s390-opc.txt: Add new arch13 instructions.
 365
 366 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 367
 368         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 369         (aarch64_opcode): Change encoding for stg, stzg
 370         st2g and st2zg.
 371         * aarch64-asm-2.c: Regenerated.
 372         * aarch64-dis-2.c: Regenerated.
 373         * aarch64-opc-2.c: Regenerated.
 374
 375 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 376
 377         * aarch64-asm-2.c: Regenerated.
 378         * aarch64-dis-2.c: Likewise.
 379         * aarch64-opc-2.c: Likewise.
 380         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 381
 382 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 383             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 384
 385         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 386         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 387         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 388         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 389         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 390         case for ldstgv_indexed.
 391         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 392         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 393         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 394         * aarch64-asm-2.c: Regenerated.
 395         * aarch64-dis-2.c: Regenerated.
 396         * aarch64-opc-2.c: Regenerated.
 397
 398 2019-01-23  Nick Clifton  <nickc@redhat.com>
 399
 400         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 401
 402 2019-01-21  Nick Clifton  <nickc@redhat.com>
 403
 404         * po/de.po: Updated German translation.
 405         * po/uk.po: Updated Ukranian translation.
 406
 407 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 408         * mips-dis.c (mips_arch_choices): Fix typo in
 409         gs464, gs464e and gs264e descriptors.
 410
 411 2019-01-19  Nick Clifton  <nickc@redhat.com>
 412
 413         * configure: Regenerate.
 414         * po/opcodes.pot: Regenerate.
 415
 416 2018-06-24  Nick Clifton  <nickc@redhat.com>
 417
 418         2.32 branch created.
 419
 420 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 421
 422         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 423         if it is null.
 424         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 425         zero.
 426
 427 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 428
 429         * configure: Regenerate.
 430
 431 2019-01-07  Alan Modra  <amodra@gmail.com>
 432
 433         * configure: Regenerate.
 434         * po/POTFILES.in: Regenerate.
 435
 436 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 437
 438         * s12z-opc.c: New file.
 439         * s12z-opc.h: New file.
 440         * s12z-dis.c: Removed all code not directly related to display
 441         of instructions.  Used the interface provided by the new files
 442         instead.
 443         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 444         * Makefile.in: Regenerate.
 445         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 446         * configure: Regenerate.
 447
 448 2019-01-01  Alan Modra  <amodra@gmail.com>
 449
 450         Update year range in copyright notice of all files.
 451
 452 For older changes see ChangeLog-2018
 453 \f
 454 Copyright (C) 2019 Free Software Foundation, Inc.
 455
 456 Copying and distribution of this file, with or without modification,
 457 are permitted in any medium without royalty provided the copyright
 458 notice and this notice are preserved.
 459
 460 Local Variables:
 461 mode: change-log
 462 left-margin: 8
 463 fill-column: 74
 464 version-control: never
 465 End: