opcodes/ChangeLog

   1 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
   2             Michael Collison <michael.collison@arm.com>
   3
   4         * arm-dis.c (enum mve_instructions): Add new instructions.
   5         (enum mve_unpredictable): Add new reasons.
   6         (enum mve_undefined): Likewise.
   7         (is_mve_okay_in_it): Handle new isntructions.
   8         (is_mve_encoding_conflict): Likewise.
   9         (is_mve_undefined): Likewise.
  10         (is_mve_unpredictable): Likewise.
  11         (print_mve_vmov_index): Likewise.
  12         (print_simd_imm8): Likewise.
  13         (print_mve_undefined): Likewise.
  14         (print_mve_unpredictable): Likewise.
  15         (print_mve_size): Likewise.
  16         (print_insn_mve): Likewise.
  17
  18 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  19             Michael Collison <michael.collison@arm.com>
  20
  21         * arm-dis.c (enum mve_instructions): Add new instructions.
  22         (enum mve_unpredictable): Add new reasons.
  23         (enum mve_undefined): Likewise.
  24         (is_mve_encoding_conflict): Handle new instructions.
  25         (is_mve_undefined): Likewise.
  26         (is_mve_unpredictable): Likewise.
  27         (print_mve_undefined): Likewise.
  28         (print_mve_unpredictable): Likewise.
  29         (print_mve_rounding_mode): Likewise.
  30         (print_mve_vcvt_size): Likewise.
  31         (print_mve_size): Likewise.
  32         (print_insn_mve): Likewise.
  33
  34 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  35             Michael Collison <michael.collison@arm.com>
  36
  37         * arm-dis.c (enum mve_instructions): Add new instructions.
  38         (enum mve_unpredictable): Add new reasons.
  39         (enum mve_undefined): Likewise.
  40         (is_mve_undefined): Handle new instructions.
  41         (is_mve_unpredictable): Likewise.
  42         (print_mve_undefined): Likewise.
  43         (print_mve_unpredictable): Likewise.
  44         (print_mve_size): Likewise.
  45         (print_insn_mve): Likewise.
  46
  47 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  48             Michael Collison <michael.collison@arm.com>
  49
  50         * arm-dis.c (enum mve_instructions): Add new instructions.
  51         (enum mve_undefined): Add new reasons.
  52         (insns): Add new instructions.
  53         (is_mve_encoding_conflict):
  54         (print_mve_vld_str_addr): New print function.
  55         (is_mve_undefined): Handle new instructions.
  56         (is_mve_unpredictable): Likewise.
  57         (print_mve_undefined): Likewise.
  58         (print_mve_size): Likewise.
  59         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
  60         (print_insn_mve):  Handle new operands.
  61
  62 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  63             Michael Collison <michael.collison@arm.com>
  64
  65         * arm-dis.c (enum mve_instructions): Add new instructions.
  66         (enum mve_unpredictable): Add new reasons.
  67         (is_mve_encoding_conflict): Handle new instructions.
  68         (is_mve_unpredictable): Likewise.
  69         (mve_opcodes): Add new instructions.
  70         (print_mve_unpredictable): Handle new reasons.
  71         (print_mve_register_blocks): New print function.
  72         (print_mve_size): Handle new instructions.
  73         (print_insn_mve): Likewise.
  74
  75 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  76             Michael Collison <michael.collison@arm.com>
  77
  78         * arm-dis.c (enum mve_instructions): Add new instructions.
  79         (enum mve_unpredictable): Add new reasons.
  80         (enum mve_undefined): Likewise.
  81         (is_mve_encoding_conflict): Handle new instructions.
  82         (is_mve_undefined): Likewise.
  83         (is_mve_unpredictable): Likewise.
  84         (coprocessor_opcodes): Move NEON VDUP from here...
  85         (neon_opcodes): ... to here.
  86         (mve_opcodes): Add new instructions.
  87         (print_mve_undefined):  Handle new reasons.
  88         (print_mve_unpredictable): Likewise.
  89         (print_mve_size): Handle new instructions.
  90         (print_insn_neon): Handle vdup.
  91         (print_insn_mve): Handle new operands.
  92
  93 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  94             Michael Collison <michael.collison@arm.com>
  95
  96         * arm-dis.c (enum mve_instructions): Add new instructions.
  97         (enum mve_unpredictable): Add new values.
  98         (mve_opcodes): Add new instructions.
  99         (vec_condnames): New array with vector conditions.
 100         (mve_predicatenames): New array with predicate suffixes.
 101         (mve_vec_sizename): New array with vector sizes.
 102         (enum vpt_pred_state): New enum with vector predication states.
 103         (struct vpt_block): New struct type for vpt blocks.
 104         (vpt_block_state): Global struct to keep track of state.
 105         (mve_extract_pred_mask): New helper function.
 106         (num_instructions_vpt_block): Likewise.
 107         (mark_outside_vpt_block): Likewise.
 108         (mark_inside_vpt_block): Likewise.
 109         (invert_next_predicate_state): Likewise.
 110         (update_next_predicate_state): Likewise.
 111         (update_vpt_block_state): Likewise.
 112         (is_vpt_instruction): Likewise.
 113         (is_mve_encoding_conflict): Add entries for new instructions.
 114         (is_mve_unpredictable): Likewise.
 115         (print_mve_unpredictable): Handle new cases.
 116         (print_instruction_predicate): Likewise.
 117         (print_mve_size): New function.
 118         (print_vec_condition): New function.
 119         (print_insn_mve): Handle vpt blocks and new print operands.
 120
 121 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 122
 123         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 124         8, 14 and 15 for Armv8.1-M Mainline.
 125
 126 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 127             Michael Collison <michael.collison@arm.com>
 128
 129         * arm-dis.c (enum mve_instructions): New enum.
 130         (enum mve_unpredictable): Likewise.
 131         (enum mve_undefined): Likewise.
 132         (struct mopcode32): New struct.
 133         (is_mve_okay_in_it): New function.
 134         (is_mve_architecture): Likewise.
 135         (arm_decode_field): Likewise.
 136         (arm_decode_field_multiple): Likewise.
 137         (is_mve_encoding_conflict): Likewise.
 138         (is_mve_undefined): Likewise.
 139         (is_mve_unpredictable): Likewise.
 140         (print_mve_undefined): Likewise.
 141         (print_mve_unpredictable): Likewise.
 142         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 143         (print_insn_mve): New function.
 144         (print_insn_thumb32): Handle MVE architecture.
 145         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 146
 147 2019-05-10  Nick Clifton  <nickc@redhat.com>
 148
 149         PR 24538
 150         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 151         end of the table prematurely.
 152
 153 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 154
 155         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 156         macros for R6.
 157
 158 2019-05-11  Alan Modra  <amodra@gmail.com>
 159
 160         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 161         when -Mraw is in effect.
 162
 163 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 164
 165         * aarch64-dis-2.c: Regenerate.
 166         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 167         (OP_SVE_BBB): New variant set.
 168         (OP_SVE_DDDD): New variant set.
 169         (OP_SVE_HHH): New variant set.
 170         (OP_SVE_HHHU): New variant set.
 171         (OP_SVE_SSS): New variant set.
 172         (OP_SVE_SSSU): New variant set.
 173         (OP_SVE_SHH): New variant set.
 174         (OP_SVE_SBBU): New variant set.
 175         (OP_SVE_DSS): New variant set.
 176         (OP_SVE_DHHU): New variant set.
 177         (OP_SVE_VMV_HSD_BHS): New variant set.
 178         (OP_SVE_VVU_HSD_BHS): New variant set.
 179         (OP_SVE_VVVU_SD_BH): New variant set.
 180         (OP_SVE_VVVU_BHSD): New variant set.
 181         (OP_SVE_VVV_QHD_DBS): New variant set.
 182         (OP_SVE_VVV_HSD_BHS): New variant set.
 183         (OP_SVE_VVV_HSD_BHS2): New variant set.
 184         (OP_SVE_VVV_BHS_HSD): New variant set.
 185         (OP_SVE_VV_BHS_HSD): New variant set.
 186         (OP_SVE_VVV_SD): New variant set.
 187         (OP_SVE_VVU_BHS_HSD): New variant set.
 188         (OP_SVE_VZVV_SD): New variant set.
 189         (OP_SVE_VZVV_BH): New variant set.
 190         (OP_SVE_VZV_SD): New variant set.
 191         (aarch64_opcode_table): Add sve2 instructions.
 192
 193 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 194
 195         * aarch64-asm-2.c: Regenerated.
 196         * aarch64-dis-2.c: Regenerated.
 197         * aarch64-opc-2.c: Regenerated.
 198         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 199         for SVE_SHLIMM_UNPRED_22.
 200         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 201         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 202         operand.
 203
 204 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 205
 206         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 207         sve_size_tsz_bhs iclass encode.
 208         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 209         sve_size_tsz_bhs iclass decode.
 210
 211 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 212
 213         * aarch64-asm-2.c: Regenerated.
 214         * aarch64-dis-2.c: Regenerated.
 215         * aarch64-opc-2.c: Regenerated.
 216         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 217         for SVE_Zm4_11_INDEX.
 218         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 219         (fields): Handle SVE_i2h field.
 220         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 221         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 222
 223 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 224
 225         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 226         sve_shift_tsz_bhsd iclass encode.
 227         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 228         sve_shift_tsz_bhsd iclass decode.
 229
 230 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 231
 232         * aarch64-asm-2.c: Regenerated.
 233         * aarch64-dis-2.c: Regenerated.
 234         * aarch64-opc-2.c: Regenerated.
 235         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 236         (aarch64_encode_variant_using_iclass): Handle
 237         sve_shift_tsz_hsd iclass encode.
 238         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 239         sve_shift_tsz_hsd iclass decode.
 240         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 241         for SVE_SHRIMM_UNPRED_22.
 242         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 243         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 244         operand.
 245
 246 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 247
 248         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 249         sve_size_013 iclass encode.
 250         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 251         sve_size_013 iclass decode.
 252
 253 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 254
 255         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 256         sve_size_bh iclass encode.
 257         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 258         sve_size_bh iclass decode.
 259
 260 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 261
 262         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 263         sve_size_sd2 iclass encode.
 264         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 265         sve_size_sd2 iclass decode.
 266         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 267         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 268
 269 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 270
 271         * aarch64-asm-2.c: Regenerated.
 272         * aarch64-dis-2.c: Regenerated.
 273         * aarch64-opc-2.c: Regenerated.
 274         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 275         for SVE_ADDR_ZX.
 276         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 277         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 278
 279 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 280
 281         * aarch64-asm-2.c: Regenerated.
 282         * aarch64-dis-2.c: Regenerated.
 283         * aarch64-opc-2.c: Regenerated.
 284         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 285         for SVE_Zm3_11_INDEX.
 286         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 287         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 288         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 289         fields.
 290         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 291
 292 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 293
 294         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 295         sve_size_hsd2 iclass encode.
 296         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 297         sve_size_hsd2 iclass decode.
 298         * aarch64-opc.c (fields): Handle SVE_size field.
 299         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 300
 301 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 302
 303         * aarch64-asm-2.c: Regenerated.
 304         * aarch64-dis-2.c: Regenerated.
 305         * aarch64-opc-2.c: Regenerated.
 306         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 307         for SVE_IMM_ROT3.
 308         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 309         (fields): Handle SVE_rot3 field.
 310         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 311         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 312
 313 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 314
 315         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 316         instructions.
 317
 318 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 319
 320         * aarch64-tbl.h
 321         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 322         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 323         aarch64_feature_sve2bitperm): New feature sets.
 324         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 325         for feature set addresses.
 326         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 327         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 328
 329 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 330             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 331
 332         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 333         argument and set ASE_EVA_R6 appropriately.
 334         (set_default_mips_dis_options): Pass ISA to above.
 335         (parse_mips_dis_option): Likewise.
 336         * mips-opc.c (EVAR6): New macro.
 337         (mips_builtin_opcodes): Add llwpe, scwpe.
 338
 339 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 340
 341         * aarch64-asm-2.c: Regenerated.
 342         * aarch64-dis-2.c: Regenerated.
 343         * aarch64-opc-2.c: Regenerated.
 344         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 345         AARCH64_OPND_TME_UIMM16.
 346         (aarch64_print_operand): Likewise.
 347         * aarch64-tbl.h (QL_IMM_NIL): New.
 348         (TME): New.
 349         (_TME_INSN): New.
 350         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 351
 352 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 353
 354         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 355
 356 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 357             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 358
 359         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 360
 361 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 362
 363         * s12z-opc.h: Add extern "C" bracketing to help
 364         users who wish to use this interface in c++ code.
 365
 366 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 367
 368         * s12z-opc.c (bm_decode): Handle bit map operations with the
 369         "reserved0" mode.
 370
 371 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 372
 373         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 374         specifier.  Add entries for VLDR and VSTR of system registers.
 375         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 376         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 377         of %J and %K format specifier.
 378
 379 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 380
 381         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 382         Add new entries for VSCCLRM instruction.
 383         (print_insn_coprocessor): Handle new %C format control code.
 384
 385 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 386
 387         * arm-dis.c (enum isa): New enum.
 388         (struct sopcode32): New structure.
 389         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 390         set isa field of all current entries to ANY.
 391         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 392         Only match an entry if its isa field allows the current mode.
 393
 394 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 395
 396         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 397         CLRM.
 398         (print_insn_thumb32): Add logic to print %n CLRM register list.
 399
 400 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 401
 402         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 403         and %Q patterns.
 404
 405 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 406
 407         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 408         (print_insn_thumb32): Edit the switch case for %Z.
 409
 410 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 411
 412         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 413
 414 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 415
 416         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 417
 418 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 419
 420         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 421
 422 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 423
 424         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 425         Arm register with r13 and r15 unpredictable.
 426         (thumb32_opcodes): New instructions for bfx and bflx.
 427
 428 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 429
 430         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 431
 432 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 433
 434         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 435
 436 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 437
 438         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 439
 440 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 441
 442         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 443
 444 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 445
 446         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 447         "optr". ("operator" is a reserved word in c++).
 448
 449 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 450
 451         * aarch64-opc.c (aarch64_print_operand): Add case for
 452         AARCH64_OPND_Rt_SP.
 453         (verify_constraints): Likewise.
 454         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 455         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 456         to accept Rt|SP as first operand.
 457         (AARCH64_OPERANDS): Add new Rt_SP.
 458         * aarch64-asm-2.c: Regenerated.
 459         * aarch64-dis-2.c: Regenerated.
 460         * aarch64-opc-2.c: Regenerated.
 461
 462 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 463
 464         * aarch64-asm-2.c: Regenerated.
 465         * aarch64-dis-2.c: Likewise.
 466         * aarch64-opc-2.c: Likewise.
 467         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 468
 469 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 470
 471         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 472
 473 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 474
 475         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 476         * i386-init.h: Regenerated.
 477
 478 2019-04-07  Alan Modra  <amodra@gmail.com>
 479
 480         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 481         op_separator to control printing of spaces, comma and parens
 482         rather than need_comma, need_paren and spaces vars.
 483
 484 2019-04-07  Alan Modra  <amodra@gmail.com>
 485
 486         PR 24421
 487         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 488         (print_insn_neon, print_insn_arm): Likewise.
 489
 490 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 491
 492         * i386-dis-evex.h (evex_table): Updated to support BF16
 493         instructions.
 494         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 495         and EVEX_W_0F3872_P_3.
 496         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 497         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 498         * i386-opc.h (enum): Add CpuAVX512_BF16.
 499         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 500         * i386-opc.tbl: Add AVX512 BF16 instructions.
 501         * i386-init.h: Regenerated.
 502         * i386-tbl.h: Likewise.
 503
 504 2019-04-05  Alan Modra  <amodra@gmail.com>
 505
 506         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 507         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 508         to favour printing of "-" branch hint when using the "y" bit.
 509         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 510
 511 2019-04-05  Alan Modra  <amodra@gmail.com>
 512
 513         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 514         opcode until first operand is output.
 515
 516 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 517
 518         PR gas/24349
 519         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 520         (valid_bo_post_v2): Add support for 'at' branch hints.
 521         (insert_bo): Only error on branch on ctr.
 522         (get_bo_hint_mask): New function.
 523         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 524         for inserting 'at' branch hints.
 525         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 526         for extracting 'at' branch hints.
 527         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 528         (BOE): Delete operand.
 529         (BOM, BOP): New operands.
 530         (RM): Update value.
 531         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 532         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 533         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 534         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 535         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 536         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 537         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 538         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 539         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 540         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 541         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 542         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 543         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 544         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 545         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 546         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 547         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 548         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 549         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 550         bttarl+>: New extended mnemonics.
 551
 552 2019-03-28  Alan Modra  <amodra@gmail.com>
 553
 554         PR 24390
 555         * ppc-opc.c (BTF): Define.
 556         (powerpc_opcodes): Use for mtfsb*.
 557         * ppc-dis.c (print_insn_powerpc): Print fields with both
 558         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 559
 560 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 561
 562         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 563         (mapping_symbol_for_insn): Implement new algorithm.
 564         (print_insn): Remove duplicate code.
 565
 566 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 567
 568         * aarch64-dis.c (print_insn_aarch64):
 569         Implement override.
 570
 571 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 572
 573         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 574         order.
 575
 576 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 577
 578         * aarch64-dis.c (last_stop_offset): New.
 579         (print_insn_aarch64): Use stop_offset.
 580
 581 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 582
 583         PR gas/24359
 584         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 585         CPU_ANY_AVX2_FLAGS.
 586         * i386-init.h: Regenerated.
 587
 588 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 589
 590         PR gas/24348
 591         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 592         vmovdqu16, vmovdqu32 and vmovdqu64.
 593         * i386-tbl.h: Regenerated.
 594
 595 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 596
 597         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 598         from vstrszb, vstrszh, and vstrszf.
 599
 600 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 601
 602         * s390-opc.txt: Add instruction descriptions.
 603
 604 2019-02-08  Jim Wilson  <jimw@sifive.com>
 605
 606         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 607         <bne>: Likewise.
 608
 609 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 610
 611         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 612
 613 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 614
 615         PR binutils/23212
 616         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 617         * aarch64-opc.c (verify_elem_sd): New.
 618         (fields): Add FLD_sz entr.
 619         * aarch64-tbl.h (_SIMD_INSN): New.
 620         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 621         fmulx scalar and vector by element isns.
 622
 623 2019-02-07  Nick Clifton  <nickc@redhat.com>
 624
 625         * po/sv.po: Updated Swedish translation.
 626
 627 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 628
 629         * s390-mkopc.c (main): Accept arch13 as cpu string.
 630         * s390-opc.c: Add new instruction formats and instruction opcode
 631         masks.
 632         * s390-opc.txt: Add new arch13 instructions.
 633
 634 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 635
 636         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 637         (aarch64_opcode): Change encoding for stg, stzg
 638         st2g and st2zg.
 639         * aarch64-asm-2.c: Regenerated.
 640         * aarch64-dis-2.c: Regenerated.
 641         * aarch64-opc-2.c: Regenerated.
 642
 643 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 644
 645         * aarch64-asm-2.c: Regenerated.
 646         * aarch64-dis-2.c: Likewise.
 647         * aarch64-opc-2.c: Likewise.
 648         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 649
 650 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 651             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 652
 653         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 654         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 655         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 656         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 657         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 658         case for ldstgv_indexed.
 659         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 660         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 661         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 662         * aarch64-asm-2.c: Regenerated.
 663         * aarch64-dis-2.c: Regenerated.
 664         * aarch64-opc-2.c: Regenerated.
 665
 666 2019-01-23  Nick Clifton  <nickc@redhat.com>
 667
 668         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 669
 670 2019-01-21  Nick Clifton  <nickc@redhat.com>
 671
 672         * po/de.po: Updated German translation.
 673         * po/uk.po: Updated Ukranian translation.
 674
 675 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 676         * mips-dis.c (mips_arch_choices): Fix typo in
 677         gs464, gs464e and gs264e descriptors.
 678
 679 2019-01-19  Nick Clifton  <nickc@redhat.com>
 680
 681         * configure: Regenerate.
 682         * po/opcodes.pot: Regenerate.
 683
 684 2018-06-24  Nick Clifton  <nickc@redhat.com>
 685
 686         2.32 branch created.
 687
 688 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 689
 690         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 691         if it is null.
 692         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 693         zero.
 694
 695 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 696
 697         * configure: Regenerate.
 698
 699 2019-01-07  Alan Modra  <amodra@gmail.com>
 700
 701         * configure: Regenerate.
 702         * po/POTFILES.in: Regenerate.
 703
 704 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 705
 706         * s12z-opc.c: New file.
 707         * s12z-opc.h: New file.
 708         * s12z-dis.c: Removed all code not directly related to display
 709         of instructions.  Used the interface provided by the new files
 710         instead.
 711         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 712         * Makefile.in: Regenerate.
 713         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 714         * configure: Regenerate.
 715
 716 2019-01-01  Alan Modra  <amodra@gmail.com>
 717
 718         Update year range in copyright notice of all files.
 719
 720 For older changes see ChangeLog-2018
 721 \f
 722 Copyright (C) 2019 Free Software Foundation, Inc.
 723
 724 Copying and distribution of this file, with or without modification,
 725 are permitted in any medium without royalty provided the copyright
 726 notice and this notice are preserved.
 727
 728 Local Variables:
 729 mode: change-log
 730 left-margin: 8
 731 fill-column: 74
 732 version-control: never
 733 End: