opcodes/ChangeLog

   1 2020-02-16  David Faust  <david.faust@oracle.com>
   2
   3         * bpf-desc.c: Regenerate.
   4         * bpf-desc.h: Likewise.
   5         * bpf-opc.c: Regenerate.
   6         * bpf-opc.h: Likewise.
   7
   8 2020-04-07  Lili Cui  <lili.cui@intel.com>
   9
  10         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
  11         (prefix_table): New instructions (see prefixes above).
  12         (rm_table): Likewise
  13         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
  14         CPU_ANY_TSXLDTRK_FLAGS.
  15         (cpu_flags): Add CpuTSXLDTRK.
  16         * i386-opc.h (enum): Add CpuTSXLDTRK.
  17         (i386_cpu_flags): Add cputsxldtrk.
  18         * i386-opc.tbl: Add XSUSPLDTRK insns.
  19         * i386-init.h: Regenerate.
  20         * i386-tbl.h: Likewise.
  21
  22 2020-04-02  Lili Cui  <lili.cui@intel.com>
  23
  24         * i386-dis.c (prefix_table): New instructions serialize.
  25         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
  26         CPU_ANY_SERIALIZE_FLAGS.
  27         (cpu_flags): Add CpuSERIALIZE.
  28         * i386-opc.h (enum): Add CpuSERIALIZE.
  29         (i386_cpu_flags): Add cpuserialize.
  30         * i386-opc.tbl: Add SERIALIZE insns.
  31         * i386-init.h: Regenerate.
  32         * i386-tbl.h: Likewise.
  33
  34 2020-03-26  Alan Modra  <amodra@gmail.com>
  35
  36         * disassemble.h (opcodes_assert): Declare.
  37         (OPCODES_ASSERT): Define.
  38         * disassemble.c: Don't include assert.h.  Include opintl.h.
  39         (opcodes_assert): New function.
  40         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
  41         (bfd_h8_disassemble): Reduce size of data array.  Correctly
  42         calculate maxlen.  Omit insn decoding when insn length exceeds
  43         maxlen.  Exit from nibble loop when looking for E, before
  44         accessing next data byte.  Move processing of E outside loop.
  45         Replace tests of maxlen in loop with assertions.
  46
  47 2020-03-26  Alan Modra  <amodra@gmail.com>
  48
  49         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
  50
  51 2020-03-25  Alan Modra  <amodra@gmail.com>
  52
  53         * z80-dis.c (suffix): Init mybuf.
  54
  55 2020-03-22  Alan Modra  <amodra@gmail.com>
  56
  57         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
  58         successflly read from section.
  59
  60 2020-03-22  Alan Modra  <amodra@gmail.com>
  61
  62         * arc-dis.c (find_format): Use ISO C string concatenation rather
  63         than line continuation within a string.  Don't access needs_limm
  64         before testing opcode != NULL.
  65
  66 2020-03-22  Alan Modra  <amodra@gmail.com>
  67
  68         * ns32k-dis.c (print_insn_arg): Update comment.
  69         (print_insn_ns32k): Reduce size of index_offset array, and
  70         initialize, passing -1 to print_insn_arg for args that are not
  71         an index.  Don't exit arg loop early.  Abort on bad arg number.
  72
  73 2020-03-22  Alan Modra  <amodra@gmail.com>
  74
  75         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
  76         * s12z-opc.c: Formatting.
  77         (operands_f): Return an int.
  78         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
  79         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
  80         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
  81         (exg_sex_discrim): Likewise.
  82         (create_immediate_operand, create_bitfield_operand),
  83         (create_register_operand_with_size, create_register_all_operand),
  84         (create_register_all16_operand, create_simple_memory_operand),
  85         (create_memory_operand, create_memory_auto_operand): Don't
  86         segfault on malloc failure.
  87         (z_ext24_decode): Return an int status, negative on fail, zero
  88         on success.
  89         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
  90         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
  91         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
  92         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
  93         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
  94         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
  95         (loop_primitive_decode, shift_decode, psh_pul_decode),
  96         (bit_field_decode): Similarly.
  97         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
  98         to return value, update callers.
  99         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 100         Don't segfault on NULL operand.
 101         (decode_operation): Return OP_INVALID on first fail.
 102         (decode_s12z): Check all reads, returning -1 on fail.
 103
 104 2020-03-20  Alan Modra  <amodra@gmail.com>
 105
 106         * metag-dis.c (print_insn_metag): Don't ignore status from
 107         read_memory_func.
 108
 109 2020-03-20  Alan Modra  <amodra@gmail.com>
 110
 111         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 112         Initialize parts of buffer not written when handling a possible
 113         2-byte insn at end of section.  Don't attempt decoding of such
 114         an insn by the 4-byte machinery.
 115
 116 2020-03-20  Alan Modra  <amodra@gmail.com>
 117
 118         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 119         partially filled buffer.  Prevent lookup of 4-byte insns when
 120         only VLE 2-byte insns are possible due to section size.  Print
 121         ".word" rather than ".long" for 2-byte leftovers.
 122
 123 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 124
 125         PR 25641
 126         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 127
 128 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 129
 130         * i386-dis.c (X86_64_0D): Rename to ...
 131         (X86_64_0E): ... this.
 132
 133 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 134
 135         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 136         * Makefile.in: Regenerated.
 137
 138 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 139
 140         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 141         3-operand pseudos.
 142         * i386-tbl.h: Re-generate.
 143
 144 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 145
 146         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 147         vprot*, vpsha*, and vpshl*.
 148         * i386-tbl.h: Re-generate.
 149
 150 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 151
 152         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 153         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 154         * i386-tbl.h: Re-generate.
 155
 156 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 157
 158         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 159         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 160         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 161         * i386-tbl.h: Re-generate.
 162
 163 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 164
 165         * i386-gen.c (struct template_arg, struct template_instance,
 166         struct template_param, struct template, templates,
 167         parse_template, expand_templates): New.
 168         (process_i386_opcodes): Various local variables moved to
 169         expand_templates. Call parse_template and expand_templates.
 170         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 171         * i386-tbl.h: Re-generate.
 172
 173 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 174
 175         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 176         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 177         register and memory source templates. Replace VexW= by VexW*
 178         where applicable.
 179         * i386-tbl.h: Re-generate.
 180
 181 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 182
 183         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 184         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 185         * i386-tbl.h: Re-generate.
 186
 187 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 188
 189         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 190         * i386-tbl.h: Re-generate.
 191
 192 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 193
 194         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 195         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 196         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 197         VexW0 on SSE2AVX variants.
 198         (vmovq): Drop NoRex64 from XMM/XMM variants.
 199         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 200         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 201         applicable use VexW0.
 202         * i386-tbl.h: Re-generate.
 203
 204 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 205
 206         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 207         * i386-opc.h (Rex64): Delete.
 208         (struct i386_opcode_modifier): Remove rex64 field.
 209         * i386-opc.tbl (crc32): Drop Rex64.
 210         Replace Rex64 with Size64 everywhere else.
 211         * i386-tbl.h: Re-generate.
 212
 213 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 214
 215         * i386-dis.c (OP_E_memory): Exclude recording of used address
 216         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 217         addressed memory operands for MPX insns.
 218
 219 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 220
 221         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 222         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 223         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 224         (ptwrite): Split into non-64-bit and 64-bit forms.
 225         * i386-tbl.h: Re-generate.
 226
 227 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 228
 229         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 230         template.
 231         * i386-tbl.h: Re-generate.
 232
 233 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 234
 235         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 236         (prefix_table): Move vmmcall here. Add vmgexit.
 237         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 238         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 239         (cpu_flags): Add CpuSEV_ES entry.
 240         * i386-opc.h (CpuSEV_ES): New.
 241         (union i386_cpu_flags): Add cpusev_es field.
 242         * i386-opc.tbl (vmgexit): New.
 243         * i386-init.h, i386-tbl.h: Re-generate.
 244
 245 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 246
 247         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 248         with MnemonicSize.
 249         * i386-opc.h (IGNORESIZE): New.
 250         (DEFAULTSIZE): Likewise.
 251         (IgnoreSize): Removed.
 252         (DefaultSize): Likewise.
 253         (MnemonicSize): New.
 254         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 255         mnemonicsize.
 256         * i386-opc.tbl (IgnoreSize): New.
 257         (DefaultSize): Likewise.
 258         * i386-tbl.h: Regenerated.
 259
 260 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 261
 262         PR 25627
 263         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 264         instructions.
 265
 266 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 267
 268         PR gas/25622
 269         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 270         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 271         * i386-tbl.h: Regenerated.
 272
 273 2020-02-26  Alan Modra  <amodra@gmail.com>
 274
 275         * aarch64-asm.c: Indent labels correctly.
 276         * aarch64-dis.c: Likewise.
 277         * aarch64-gen.c: Likewise.
 278         * aarch64-opc.c: Likewise.
 279         * alpha-dis.c: Likewise.
 280         * i386-dis.c: Likewise.
 281         * nds32-asm.c: Likewise.
 282         * nfp-dis.c: Likewise.
 283         * visium-dis.c: Likewise.
 284
 285 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 286
 287         * arc-regs.h (int_vector_base): Make it available for all ARC
 288         CPUs.
 289
 290 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 291
 292         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 293         changed.
 294
 295 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 296
 297         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 298         c.mv/c.li if rs1 is zero.
 299
 300 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 301
 302         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 303         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 304         CPU_POPCNT_FLAGS.
 305         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 306         * i386-opc.h (CpuABM): Removed.
 307         (CpuPOPCNT): New.
 308         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 309         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 310         popcnt.  Remove CpuABM from lzcnt.
 311         * i386-init.h: Regenerated.
 312         * i386-tbl.h: Likewise.
 313
 314 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 315
 316         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 317         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 318         VexW1 instead of open-coding them.
 319         * i386-tbl.h: Re-generate.
 320
 321 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 322
 323         * i386-opc.tbl (AddrPrefixOpReg): Define.
 324         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 325         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 326         templates. Drop NoRex64.
 327         * i386-tbl.h: Re-generate.
 328
 329 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 330
 331         PR gas/6518
 332         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 333         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 334         into Intel syntax instance (with Unpsecified) and AT&T one
 335         (without).
 336         (vcvtneps2bf16): Likewise, along with folding the two so far
 337         separate ones.
 338         * i386-tbl.h: Re-generate.
 339
 340 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 341
 342         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 343         CPU_ANY_SSE4A_FLAGS.
 344
 345 2020-02-17  Alan Modra  <amodra@gmail.com>
 346
 347         * i386-gen.c (cpu_flag_init): Correct last change.
 348
 349 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 350
 351         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 352         CPU_ANY_SSE4_FLAGS.
 353
 354 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 355
 356         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 357         (movzx): Likewise.
 358
 359 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 360
 361         PR gas/25438
 362         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 363         destination for Cpu64-only variant.
 364         (movzx): Fold patterns.
 365         * i386-tbl.h: Re-generate.
 366
 367 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 368
 369         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 370         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 371         CPU_ANY_SSE4_FLAGS entry.
 372         * i386-init.h: Re-generate.
 373
 374 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 375
 376         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 377         with Unspecified, making the present one AT&T syntax only.
 378         * i386-tbl.h: Re-generate.
 379
 380 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 381
 382         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 383         * i386-tbl.h: Re-generate.
 384
 385 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 386
 387         PR gas/24546
 388         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 389         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 390         Amd64 and Intel64 templates.
 391         (call, jmp): Likewise for far indirect variants. Dro
 392         Unspecified.
 393         * i386-tbl.h: Re-generate.
 394
 395 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 396
 397         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 398         * i386-opc.h (ShortForm): Delete.
 399         (struct i386_opcode_modifier): Remove shortform field.
 400         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 401         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 402         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 403         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 404         Drop ShortForm.
 405         * i386-tbl.h: Re-generate.
 406
 407 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 408
 409         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 410         fucompi): Drop ShortForm from operand-less templates.
 411         * i386-tbl.h: Re-generate.
 412
 413 2020-02-11  Alan Modra  <amodra@gmail.com>
 414
 415         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 416         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 417         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 418         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 419         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 420
 421 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 422
 423         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 424         (cde_opcodes): Add VCX* instructions.
 425
 426 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 427             Matthew Malcomson  <matthew.malcomson@arm.com>
 428
 429         * arm-dis.c (struct cdeopcode32): New.
 430         (CDE_OPCODE): New macro.
 431         (cde_opcodes): New disassembly table.
 432         (regnames): New option to table.
 433         (cde_coprocs): New global variable.
 434         (print_insn_cde): New
 435         (print_insn_thumb32): Use print_insn_cde.
 436         (parse_arm_disassembler_options): Parse coprocN args.
 437
 438 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 439
 440         PR gas/25516
 441         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 442         with ISA64.
 443         * i386-opc.h (AMD64): Removed.
 444         (Intel64): Likewose.
 445         (AMD64): New.
 446         (INTEL64): Likewise.
 447         (INTEL64ONLY): Likewise.
 448         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 449         * i386-opc.tbl (Amd64): New.
 450         (Intel64): Likewise.
 451         (Intel64Only): Likewise.
 452         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 453         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 454         * i386-tbl.h: Regenerated.
 455
 456 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 457
 458         PR 25469
 459         * z80-dis.c: Add support for GBZ80 opcodes.
 460
 461 2020-02-04  Alan Modra  <amodra@gmail.com>
 462
 463         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 464
 465 2020-02-03  Alan Modra  <amodra@gmail.com>
 466
 467         * m32c-ibld.c: Regenerate.
 468
 469 2020-02-01  Alan Modra  <amodra@gmail.com>
 470
 471         * frv-ibld.c: Regenerate.
 472
 473 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 474
 475         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 476         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 477         (OP_E_memory): Replace xmm_mdq_mode case label by
 478         vex_scalar_w_dq_mode one.
 479         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 480
 481 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 482
 483         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 484         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 485         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 486         (intel_operand_size): Drop vex_w_dq_mode case label.
 487
 488 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 489
 490         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 491         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 492
 493 2020-01-30  Alan Modra  <amodra@gmail.com>
 494
 495         * m32c-ibld.c: Regenerate.
 496
 497 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 498
 499         * bpf-opc.c: Regenerate.
 500
 501 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 502
 503         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 504         (dis386): Use them to replace C2/C3 table entries.
 505         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 506         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 507         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 508         * i386-tbl.h: Re-generate.
 509
 510 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 511
 512         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 513         forms.
 514         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 515         DefaultSize.
 516         * i386-tbl.h: Re-generate.
 517
 518 2020-01-30  Alan Modra  <amodra@gmail.com>
 519
 520         * tic4x-dis.c (tic4x_dp): Make unsigned.
 521
 522 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 523             Jan Beulich  <jbeulich@suse.com>
 524
 525         PR binutils/25445
 526         * i386-dis.c (MOVSXD_Fixup): New function.
 527         (movsxd_mode): New enum.
 528         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 529         (intel_operand_size): Handle movsxd_mode.
 530         (OP_E_register): Likewise.
 531         (OP_G): Likewise.
 532         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 533         register on movsxd.  Add movsxd with 16-bit destination register
 534         for AMD64 and Intel64 ISAs.
 535         * i386-tbl.h: Regenerated.
 536
 537 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 538
 539         PR 25403
 540         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 541         * aarch64-asm-2.c: Regenerate
 542         * aarch64-dis-2.c: Likewise.
 543         * aarch64-opc-2.c: Likewise.
 544
 545 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 546
 547         * i386-opc.tbl (sysret): Drop DefaultSize.
 548         * i386-tbl.h: Re-generate.
 549
 550 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 551
 552         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 553         Dword.
 554         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 555         * i386-tbl.h: Re-generate.
 556
 557 2020-01-20  Nick Clifton  <nickc@redhat.com>
 558
 559         * po/de.po: Updated German translation.
 560         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 561         * po/uk.po: Updated Ukranian translation.
 562
 563 2020-01-20  Alan Modra  <amodra@gmail.com>
 564
 565         * hppa-dis.c (fput_const): Remove useless cast.
 566
 567 2020-01-20  Alan Modra  <amodra@gmail.com>
 568
 569         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 570
 571 2020-01-18  Nick Clifton  <nickc@redhat.com>
 572
 573         * configure: Regenerate.
 574         * po/opcodes.pot: Regenerate.
 575
 576 2020-01-18  Nick Clifton  <nickc@redhat.com>
 577
 578         Binutils 2.34 branch created.
 579
 580 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 581
 582         * opintl.h: Fix spelling error (seperate).
 583
 584 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 585
 586         * i386-opc.tbl: Add {vex} pseudo prefix.
 587         * i386-tbl.h: Regenerated.
 588
 589 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 590
 591         PR 25376
 592         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 593         (neon_opcodes): Likewise.
 594         (select_arm_features): Make sure we enable MVE bits when selecting
 595         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 596         any architecture.
 597
 598 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 599
 600         * i386-opc.tbl: Drop stale comment from XOP section.
 601
 602 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 603
 604         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 605         (extractps): Add VexWIG to SSE2AVX forms.
 606         * i386-tbl.h: Re-generate.
 607
 608 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 609
 610         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 611         Size64 from and use VexW1 on SSE2AVX forms.
 612         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 613         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 614         * i386-tbl.h: Re-generate.
 615
 616 2020-01-15  Alan Modra  <amodra@gmail.com>
 617
 618         * tic4x-dis.c (tic4x_version): Make unsigned long.
 619         (optab, optab_special, registernames): New file scope vars.
 620         (tic4x_print_register): Set up registernames rather than
 621         malloc'd registertable.
 622         (tic4x_disassemble): Delete optable and optable_special.  Use
 623         optab and optab_special instead.  Throw away old optab,
 624         optab_special and registernames when info->mach changes.
 625
 626 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 627
 628         PR 25377
 629         * z80-dis.c (suffix): Use .db instruction to generate double
 630         prefix.
 631
 632 2020-01-14  Alan Modra  <amodra@gmail.com>
 633
 634         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 635         values to unsigned before shifting.
 636
 637 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 638
 639         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 640         flow instructions.
 641         (print_insn_thumb16, print_insn_thumb32): Likewise.
 642         (print_insn): Initialize the insn info.
 643         * i386-dis.c (print_insn): Initialize the insn info fields, and
 644         detect jumps.
 645
 646 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 647
 648         * arc-opc.c (C_NE): Make it required.
 649
 650 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 651
 652         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 653         reserved register name.
 654
 655 2020-01-13  Alan Modra  <amodra@gmail.com>
 656
 657         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 658         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 659
 660 2020-01-13  Alan Modra  <amodra@gmail.com>
 661
 662         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 663         result of wasm_read_leb128 in a uint64_t and check that bits
 664         are not lost when copying to other locals.  Use uint32_t for
 665         most locals.  Use PRId64 when printing int64_t.
 666
 667 2020-01-13  Alan Modra  <amodra@gmail.com>
 668
 669         * score-dis.c: Formatting.
 670         * score7-dis.c: Formatting.
 671
 672 2020-01-13  Alan Modra  <amodra@gmail.com>
 673
 674         * score-dis.c (print_insn_score48): Use unsigned variables for
 675         unsigned values.  Don't left shift negative values.
 676         (print_insn_score32): Likewise.
 677         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 678
 679 2020-01-13  Alan Modra  <amodra@gmail.com>
 680
 681         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 682
 683 2020-01-13  Alan Modra  <amodra@gmail.com>
 684
 685         * fr30-ibld.c: Regenerate.
 686
 687 2020-01-13  Alan Modra  <amodra@gmail.com>
 688
 689         * xgate-dis.c (print_insn): Don't left shift signed value.
 690         (ripBits): Formatting, use 1u.
 691
 692 2020-01-10  Alan Modra  <amodra@gmail.com>
 693
 694         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 695         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 696
 697 2020-01-10  Alan Modra  <amodra@gmail.com>
 698
 699         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 700         and XRREG value earlier to avoid a shift with negative exponent.
 701         * m10200-dis.c (disassemble): Similarly.
 702
 703 2020-01-09  Nick Clifton  <nickc@redhat.com>
 704
 705         PR 25224
 706         * z80-dis.c (ld_ii_ii): Use correct cast.
 707
 708 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 709
 710         PR 25224
 711         * z80-dis.c (ld_ii_ii): Use character constant when checking
 712         opcode byte value.
 713
 714 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 715
 716         * i386-dis.c (SEP_Fixup): New.
 717         (SEP): Define.
 718         (dis386_twobyte): Use it for sysenter/sysexit.
 719         (enum x86_64_isa): Change amd64 enumerator to value 1.
 720         (OP_J): Compare isa64 against intel64 instead of amd64.
 721         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 722         forms.
 723         * i386-tbl.h: Re-generate.
 724
 725 2020-01-08  Alan Modra  <amodra@gmail.com>
 726
 727         * z8k-dis.c: Include libiberty.h
 728         (instr_data_s): Make max_fetched unsigned.
 729         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 730         Don't exceed byte_info bounds.
 731         (output_instr): Make num_bytes unsigned.
 732         (unpack_instr): Likewise for nibl_count and loop.
 733         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 734         idx unsigned.
 735         * z8k-opc.h: Regenerate.
 736
 737 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 738
 739         * arc-tbl.h (llock): Use 'LLOCK' as class.
 740         (llockd): Likewise.
 741         (scond): Use 'SCOND' as class.
 742         (scondd): Likewise.
 743         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 744         (scondd): Likewise.
 745
 746 2020-01-06  Alan Modra  <amodra@gmail.com>
 747
 748         * m32c-ibld.c: Regenerate.
 749
 750 2020-01-06  Alan Modra  <amodra@gmail.com>
 751
 752         PR 25344
 753         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 754         Peek at next byte to prevent recursion on repeated prefix bytes.
 755         Ensure uninitialised "mybuf" is not accessed.
 756         (print_insn_z80): Don't zero n_fetch and n_used here,..
 757         (print_insn_z80_buf): ..do it here instead.
 758
 759 2020-01-04  Alan Modra  <amodra@gmail.com>
 760
 761         * m32r-ibld.c: Regenerate.
 762
 763 2020-01-04  Alan Modra  <amodra@gmail.com>
 764
 765         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 766
 767 2020-01-04  Alan Modra  <amodra@gmail.com>
 768
 769         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 770
 771 2020-01-04  Alan Modra  <amodra@gmail.com>
 772
 773         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 774
 775 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 776
 777         * aarch64-tbl.h (aarch64_opcode_table): Use
 778         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 779
 780 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 781
 782         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 783         forms of SUDOT and USDOT.
 784
 785 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 786
 787         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 788         uzip{1,2}.
 789         * opcodes/aarch64-dis-2.c: Re-generate.
 790
 791 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 792
 793         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 794         FMMLA encoding.
 795         * opcodes/aarch64-dis-2.c: Re-generate.
 796
 797 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 798
 799         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 800
 801 2020-01-01  Alan Modra  <amodra@gmail.com>
 802
 803         Update year range in copyright notice of all files.
 804
 805 For older changes see ChangeLog-2019
 806 \f
 807 Copyright (C) 2020 Free Software Foundation, Inc.
 808
 809 Copying and distribution of this file, with or without modification,
 810 are permitted in any medium without royalty provided the copyright
 811 notice and this notice are preserved.
 812
 813 Local Variables:
 814 mode: change-log
 815 left-margin: 8
 816 fill-column: 74
 817 version-control: never
 818 End: