opcodes/ChangeLog

   1 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
   2
   3         * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
   4         (prefix_table): Add clwb.
   5         * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
   6         (cpu_flags): Add CpuCLWB.
   7         * i386-opc.h (enum): Add CpuCLWB.
   8         (i386_cpu_flags): Add cpuclwb.
   9         * i386-opc.tbl: Add clwb.
  10         * i386-init.h: Regenerated.
  11         * i386-tbl.h: Likewise.
  12
  13 2014-11-06  Sandra Loosemore  <sandra@codesourcery.com>
  14
  15         * nios2-dis.c (nios2_find_opcode_hash): Add mach parameter.
  16         (nios2_disassemble): Adjust call to nios2_find_opcode_hash.
  17
  18 2014-11-03  Nick Clifton  <nickc@redhat.com>
  19
  20         * po/fi.po: Updated Finnish translation.
  21
  22 2014-10-31  Andrew Pinski  <apinski@cavium.com>
  23             Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
  24
  25         * mips-dis.c (mips_arch_choices): Add octeon3.
  26         * mips-opc.c (IOCT): Include INSN_OCTEON3.
  27         (IOCT2): Likewise.
  28         (IOCT3): New define.
  29         (IVIRT): New define.
  30         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
  31         tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
  32         IVIRT instructions.
  33         Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
  34         operand for IOCT3.
  35
  36 2014-10-29  Nick Clifton  <nickc@redhat.com>
  37
  38         * po/de.po: Updated German translation.
  39
  40 2014-10-23  Sandra Loosemore  <sandra@codesourcery.com>
  41
  42         * nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
  43         (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.  Use new
  44         MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers.  Add
  45         size and format initializers.  Merge 'b' arguments into 'j'.
  46         (NIOS2_NUM_OPCODES): Adjust definition.
  47         (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
  48         (nios2_opcodes): Adjust.
  49         (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
  50         * nios2-dis.c (INSNLEN): Update comment.
  51         (nios2_hash_init, nios2_hash): Delete.
  52         (OPCODE_HASH_SIZE): New.
  53         (nios2_r1_extract_opcode): New.
  54         (nios2_disassembler_state): New.
  55         (nios2_r1_disassembler_state): New.
  56         (nios2_init_opcode_hash): Add state parameter.  Adjust to use it.
  57         (nios2_find_opcode_hash): Use state object.
  58         (bad_opcode): New.
  59         (nios2_print_insn_arg): Add op parameter.  Use it to access
  60         format.  Remove 'b' case.
  61         (nios2_disassemble): Remove special case for nop.  Remove
  62         hard-coded instruction size.
  63
  64 2014-10-21  Jan Beulich  <jbeulich@suse.com>
  65
  66         * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
  67
  68 2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
  69
  70         * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
  71         entries.
  72         Annotate several instructions with the HWCAP2_VIS3B hwcap.
  73
  74 2014-10-15  Tristan Gingold  <gingold@adacore.com>
  75
  76         * configure: Regenerate.
  77
  78 2014-10-09  Jose E. Marchesi  &lt;jose.marchesi@oracle.com&gt;
  79
  80         * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
  81         `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
  82         Annotate table with HWCAP2 bits.
  83         Add instructions xmontmul, xmontsqr, xmpmul.
  84         (sparc-opcodes): Add the `mwait',  `wr r,r,%mwait', `wr
  85         r,i,%mwait' and `rd %mwait,r' instructions.
  86         Add rd/wr instructions for accessing the %mcdper ancillary state
  87         register.
  88         (sparc-opcodes): Add sparc5/vis4.0 instructions:
  89         subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
  90         fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
  91         fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
  92         fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
  93         fpsubus16, and faligndatai.
  94         * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
  95         ancillary state register to the table.
  96         (print_insn_sparc): Handle the %mcdper ancillary state register.
  97         (print_insn_sparc): Handle new operand type '}'.
  98
  99 2014-09-22  H.J. Lu  <hongjiu.lu@intel.com>
 100
 101         * i386-dis.c (MOD_0F20): Removed.
 102         (MOD_0F21): Likewise.
 103         (MOD_0F22): Likewise.
 104         (MOD_0F23): Likewise.
 105         (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
 106         MOD_0F23 with "movZ".
 107         (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
 108         (OP_R): Check mod/rm byte and call OP_E_register.
 109
 110 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 111
 112         * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
 113         keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
 114         keyword_aridxi): Add audio ISA extension.
 115         (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
 116         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
 117         keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
 118         for nds32-dis.c using.
 119         (build_opcode_syntax): Remove dead code.
 120         (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
 121         parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
 122         parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
 123         operand parser.
 124         * nds32-asm.h: Declare.
 125         * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
 126         decoding by switch.
 127
 128 2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
 129             Matthew Fortune  <matthew.fortune@imgtec.com>
 130
 131         * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
 132         mips64r6.
 133         (parse_mips_dis_option): Allow MSA and virtualization support for
 134         mips64r6.
 135         (mips_print_arg_state): Add fields dest_regno and seen_dest.
 136         (mips_seen_register): New function.
 137         (print_insn_arg): Refactored code to use mips_seen_register
 138         function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
 139         OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
 140         the register rather than aborting.
 141         (print_insn_args): Add length argument.  Add code to correctly
 142         calculate the instruction address for pc relative instructions.
 143         (validate_insn_args): New static function.
 144         (print_insn_mips): Prevent jalx disassembling for r6.  Use
 145         validate_insn_args.
 146         (print_insn_micromips): Use validate_insn_args.
 147         all the arguments are valid.
 148         * mips-formats.h (PREV_CHECK): New define.
 149         * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
 150         -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
 151         (RD_pc): New define.
 152         (FS): New define.
 153         (I37): New define.
 154         (I69): New define.
 155         (mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
 156         MIPS R6 instructions from MIPS R2 instructions.
 157
 158 2014-09-10  H.J. Lu  <hongjiu.lu@intel.com>
 159
 160         * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
 161         (putop): Handle "%LP".
 162
 163 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 164
 165         * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
 166         * aarch64-dis-2.c: Update auto-generated file.
 167
 168 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 169
 170         * aarch64-tbl.h (QL_R4NIL): New qualifiers.
 171         (aarch64_feature_lse): New feature added.
 172         (LSE): New Added.
 173         (aarch64_opcode_table): New LSE instructions added.  Improve
 174         descriptions for ldarb/ldarh/ldar.
 175         (aarch64_opcode_table): Describe PAIRREG.
 176         * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
 177         * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
 178         (aarch64_print_operand): Recognize PAIRREG.
 179         (operand_general_constraint_met_p): Check reg pair constraints for CASP
 180         instructions.
 181         * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
 182         (do_special_decoding): Recognize F_LSE_SZ.
 183         * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
 184
 185 2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
 186
 187         * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
 188         (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
 189         "sdbbp", "syscall" and "wait".
 190
 191 2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
 192             Maciej W. Rozycki  <macro@codesourcery.com>
 193
 194         * arm-dis.c (print_arm_address): Negate the GPR-relative offset
 195         returned if the U bit is set.
 196
 197 2014-08-21  Maciej W. Rozycki  <macro@codesourcery.com>
 198
 199         * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
 200         48-bit "li" encoding.
 201
 202 2014-08-19  Andreas Arnez  <arnez@linux.vnet.ibm.com>
 203
 204         * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
 205         (s390_print_insn_with_opcode, opcode_mask_more_specific): New
 206         static functions, code was moved from...
 207         (print_insn_s390): ...here.
 208         (s390_extract_operand): Adjust comment.  Change type of first
 209         parameter from 'unsigned char *' to 'const bfd_byte *'.
 210         (union operand_value): New.
 211         (s390_extract_operand): Change return type to union operand_value.
 212         Also avoid integer overflow in sign-extension.
 213         (s390_print_insn_with_opcode): Adjust to changed return value from
 214         s390_extract_operand().  Change "%i" printf format to "%u" for
 215         unsigned values.
 216         (init_disasm): Simplify initialization of opc_index[].  This also
 217         fixes an access after the last element of s390_opcodes[].
 218         (print_insn_s390): Simplify the opcode search loop.
 219         Check architecture mask against all searched opcodes, not just the
 220         first matching one.
 221         (s390_print_insn_with_opcode): Drop function pointer dereferences
 222         without effect.
 223         (print_insn_s390): Likewise.
 224         (s390_insn_length): Simplify formula for return value.
 225         (s390_print_insn_with_opcode): Avoid special handling for the
 226         separator before the first operand.  Use new local variable
 227         'flags' in place of 'operand->flags'.
 228
 229 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 230
 231         * bfin-dis.c (struct private): Change int's to bfd_boolean's.
 232         (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 233         decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
 234         Change assignment of 1 to priv->comment to TRUE.
 235         (print_insn_bfin): Change legal to a bfd_boolean.  Change
 236         assignment of 0/1 with priv comment and parallel and legal
 237         to FALSE/TRUE.
 238
 239 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 240
 241         * bfin-dis.c (OUT): Define.
 242         (decode_CC2stat_0): Declare new op_names array.
 243         Replace multiple if statements with a single one.
 244
 245 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 246
 247         * bfin-dis.c (struct private): Add iw0.
 248         (_print_insn_bfin): Assign iw0 to priv.iw0.
 249         (print_insn_bfin): Drop ifetch and use priv.iw0.
 250
 251 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 252
 253         * bfin-dis.c (comment, parallel): Move from global scope ...
 254         (struct private): ... to this new struct.
 255         (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
 256         decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
 257         decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
 258         decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 259         decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 260         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 261         decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
 262         print_insn_bfin): Declare private struct.  Use priv's comment and
 263         parallel members.
 264
 265 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 266
 267         * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
 268         (_print_insn_bfin): Add check for unaligned pc.
 269
 270 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 271
 272         * bfin-dis.c (ifetch): New function.
 273         (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
 274         -1 when it errors.
 275
 276 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 277
 278         * micromips-opc.c (COD): Rename throughout to...
 279         (CM): New define, update to use INSN_COPROC_MOVE.
 280         (LCD): Rename throughout to...
 281         (LC): New define, update to use INSN_LOAD_COPROC.
 282         * mips-opc.c: Likewise.
 283
 284 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 285
 286         * micromips-opc.c (COD, LCD) New macros.
 287         (cfc1, ctc1): Remove FP_S attribute.
 288         (dmfc1, mfc1, mfhc1): Add LCD attribute.
 289         (dmtc1, mtc1, mthc1): Add COD attribute.
 290         * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
 291
 292 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 293             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 294             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 295             Sergey Lega  <sergey.s.lega@intel.com>
 296             Anna Tikhonova  <anna.tikhonova@intel.com>
 297             Ilya Tocar  <ilya.tocar@intel.com>
 298             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 299             Ilya Verbin  <ilya.verbin@intel.com>
 300             Kirill Yukhin  <kirill.yukhin@intel.com>
 301             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 302
 303         * i386-dis-evex.h: Updated.
 304         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 305         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
 306         PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
 307         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
 308         PREFIX_EVEX_0F3A67.
 309         (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
 310         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
 311         (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 312         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
 313         EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
 314         EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
 315         EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
 316         EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
 317         EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
 318         (prefix_table): Add entries for new instructions.
 319         (vex_len_table): Ditto.
 320         (vex_w_table): Ditto.
 321         (OP_E_memory): Update xmmq_mode handling.
 322         * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
 323         (cpu_flags): Add CpuAVX512DQ.
 324         * i386-init.h: Regenerared.
 325         * i386-opc.h (CpuAVX512DQ): New.
 326         (i386_cpu_flags): Add cpuavx512dq.
 327         * i386-opc.tbl: Add AVX512DQ instructions.
 328         * i386-tbl.h: Regenerate.
 329
 330 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 331             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 332             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 333             Sergey Lega  <sergey.s.lega@intel.com>
 334             Anna Tikhonova  <anna.tikhonova@intel.com>
 335             Ilya Tocar  <ilya.tocar@intel.com>
 336             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 337             Ilya Verbin  <ilya.verbin@intel.com>
 338             Kirill Yukhin  <kirill.yukhin@intel.com>
 339             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 340
 341         * i386-dis-evex.h: Add new instructions (prefixes bellow).
 342         * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
 343         (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
 344         (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
 345         PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
 346         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 347         PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
 348         PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
 349         PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 350         PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
 351         PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 352         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
 353         PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
 354         PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 355         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
 356         PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
 357         PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
 358         PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
 359         PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
 360         PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
 361         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
 362         PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
 363         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
 364         (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
 365         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 366         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
 367         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
 368         VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
 369         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
 370         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 371         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
 372         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
 373         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
 374         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
 375         (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
 376         EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
 377         EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
 378         EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
 379         EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
 380         EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
 381         EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
 382         (prefix_table): Add entries for new instructions.
 383         (vex_table) : Ditto.
 384         (vex_len_table): Ditto.
 385         (vex_w_table): Ditto.
 386         (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
 387         mask_bd_mode handling.
 388         (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
 389         handling.
 390         (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
 391         handling.
 392         (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
 393         (OP_EX): Add dqw_swap_mode handling.
 394         (OP_VEX): Add mask_bd_mode handling.
 395         (OP_Mask): Add mask_bd_mode handling.
 396         * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
 397         (cpu_flags): Add CpuAVX512BW.
 398         * i386-init.h: Regenerated.
 399         * i386-opc.h (CpuAVX512BW): New.
 400         (i386_cpu_flags): Add cpuavx512bw.
 401         * i386-opc.tbl: Add AVX512BW instructions.
 402         * i386-tbl.h: Regenerate.
 403
 404 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 405             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 406             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 407             Sergey Lega  <sergey.s.lega@intel.com>
 408             Anna Tikhonova  <anna.tikhonova@intel.com>
 409             Ilya Tocar  <ilya.tocar@intel.com>
 410             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 411             Ilya Verbin  <ilya.verbin@intel.com>
 412             Kirill Yukhin  <kirill.yukhin@intel.com>
 413             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 414
 415         * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
 416         * i386-tbl.h: Regenerate.
 417
 418 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 419             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 420             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 421             Sergey Lega  <sergey.s.lega@intel.com>
 422             Anna Tikhonova  <anna.tikhonova@intel.com>
 423             Ilya Tocar  <ilya.tocar@intel.com>
 424             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 425             Ilya Verbin  <ilya.verbin@intel.com>
 426             Kirill Yukhin  <kirill.yukhin@intel.com>
 427             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 428
 429         * i386-dis.c (intel_operand_size): Support 128/256 length in
 430         vex_vsib_q_w_dq_mode.
 431         (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
 432         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
 433         (cpu_flags): Add CpuAVX512VL.
 434         * i386-init.h: Regenerated.
 435         * i386-opc.h (CpuAVX512VL): New.
 436         (i386_cpu_flags): Add cpuavx512vl.
 437         (BROADCAST_1TO4, BROADCAST_1TO2): Define.
 438         * i386-opc.tbl: Add AVX512VL instructions.
 439         * i386-tbl.h: Regenerate.
 440
 441 2014-07-20  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 442
 443         * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
 444         * or1k-opinst.c: Regenerate.
 445
 446 2014-07-08  Ilya Tocar  <ilya.tocar@intel.com>
 447
 448         * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
 449         (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
 450
 451 2014-07-04  Alan Modra  <amodra@gmail.com>
 452
 453         * configure.ac: Rename from configure.in.
 454         * Makefile.in: Regenerate.
 455         * config.in: Regenerate.
 456
 457 2014-07-04  Alan Modra  <amodra@gmail.com>
 458
 459         * configure.in: Include bfd/version.m4.
 460         (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
 461         (BFD_VERSION): Delete.
 462         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
 463         * configure: Regenerate.
 464         * Makefile.in: Regenerate.
 465
 466 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
 467             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
 468             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 469             Soundararajan  <Sounderarajan.D@atmel.com>
 470
 471         * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
 472         (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
 473         machine is not avrtiny.
 474
 475 2014-06-26  Philippe De Muyter <phdm@macqel.be>
 476
 477         * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
 478         constants.
 479
 480 2014-06-12  Alan Modra  <amodra@gmail.com>
 481
 482         * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
 483         * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
 484
 485 2014-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 486
 487         * i386-dis.c (fwait_prefix): New.
 488         (ckprefix): Set fwait_prefix.
 489         (print_insn): Properly print prefixes before fwait.
 490
 491 2014-06-07  Alan Modra  <amodra@gmail.com>
 492
 493         * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
 494
 495 2014-06-05  Joel Brobecker  <brobecker@adacore.com>
 496
 497         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
 498         bfd's development.sh.
 499         * Makefile.in, configure: Regenerate.
 500
 501 2014-06-03  Nick Clifton  <nickc@redhat.com>
 502
 503         * msp430-dis.c (msp430_doubleoperand): Use extension_word to
 504         decide when extended addressing is being used.
 505
 506 2014-06-02  Eric Botcazou  <ebotcazou@adacore.com>
 507
 508         * sparc-opc.c (cas): Disable for LEON.
 509         (casl): Likewise.
 510
 511 2014-05-20  Alan Modra  <amodra@gmail.com>
 512
 513         * m68k-dis.c: Don't include setjmp.h.
 514
 515 2014-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 516
 517         * i386-dis.c (ADDR16_PREFIX): Removed.
 518         (ADDR32_PREFIX): Likewise.
 519         (DATA16_PREFIX): Likewise.
 520         (DATA32_PREFIX): Likewise.
 521         (prefix_name): Updated.
 522         (print_insn): Simplify data and address size prefixes processing.
 523
 524 2014-05-08  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 525
 526         * or1k-desc.c: Regenerated.
 527         * or1k-desc.h: Likewise.
 528         * or1k-opc.c: Likewise.
 529         * or1k-opc.h: Likewise.
 530         * or1k-opinst.c: Likewise.
 531
 532 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 533
 534         * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
 535         (I34): New define.
 536         (I36): New define.
 537         (I66): New define.
 538         (I68): New define.
 539         * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
 540         mips64r5.
 541         (parse_mips_dis_option): Update MSA and virtualization support to
 542         allow mips64r3 and mips64r5.
 543
 544 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 545
 546         * mips-opc.c (G3): Remove I4.
 547
 548 2014-05-05  H.J. Lu  <hongjiu.lu@intel.com>
 549
 550         PR binutils/16893
 551         * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
 552         (end_codep): Likewise.
 553         (mandatory_prefix): Likewise.
 554         (active_seg_prefix): Likewise.
 555         (ckprefix): Set active_seg_prefix to the active segment register
 556         prefix.
 557         (seg_prefix): Removed.
 558         (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
 559         for prefix index.  Ignore the index if it is invalid and the
 560         mandatory prefix isn't required.
 561         (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
 562         mandatory.  Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
 563         in used_prefixes here.  Don't print unused prefixes.  Check
 564         active_seg_prefix for the active segment register prefix.
 565         Restore the DFLAG bit in sizeflag if the data size prefix is
 566         unused.  Check the unused mandatory PREFIX_XXX prefixes
 567         (append_seg): Only print the segment register which gets used.
 568         (OP_E_memory): Check active_seg_prefix for the segment register
 569         prefix.
 570         (OP_OFF): Likewise.
 571         (OP_OFF64): Likewise.
 572         (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
 573
 574 2014-05-02  H.J. Lu  <hongjiu.lu@intel.com>
 575
 576         PR binutils/16886
 577         * config.in: Regenerated.
 578         * configure: Likewise.
 579         * configure.in: Check if sigsetjmp is available.
 580         * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 581         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 582         (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
 583         * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 584         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 585         (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
 586         * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 587         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 588         (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
 589         * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
 590         (OPCODES_SIGSETJMP): Likewise.
 591         (OPCODES_SIGLONGJMP): Likewise.
 592         * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 593         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 594         (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
 595         * xtensa-dis.c (dis_private): Replace jmp_buf with
 596         OPCODES_SIGJMP_BUF.
 597         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 598         (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
 599         * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 600         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 601         (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
 602
 603 2014-05-01  H.J. Lu  <hongjiu.lu@intel.com>
 604
 605         PR binutils/16891
 606         * i386-dis.c (print_insn): Handle prefixes before fwait.
 607
 608 2014-04-26  Alan Modra  <amodra@gmail.com>
 609
 610         * po/POTFILES.in: Regenerate.
 611
 612 2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
 613
 614         * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 615         to allow the MIPS XPA ASE.
 616         (parse_mips_dis_option): Process the -Mxpa option.
 617         * mips-opc.c (XPA): New define.
 618         (mips_builtin_opcodes): Add MIPS XPA instructions and move the
 619         locations of the ctc0 and cfc0 instructions.
 620
 621 2014-04-22  Christian Svensson  <blue@cmd.nu>
 622
 623         * Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
 624         * configure.in: Likewise.
 625         * disassemble.c: Likewise.
 626         * or1k-asm.c: New file.
 627         * or1k-desc.c: New file.
 628         * or1k-desc.h: New file.
 629         * or1k-dis.c: New file.
 630         * or1k-ibld.c: New file.
 631         * or1k-opc.c: New file.
 632         * or1k-opc.h: New file.
 633         * or1k-opinst.c: New file.
 634         * Makefile.in: Regenerate.
 635         * configure: Regenerate.
 636         * openrisc-asm.c: Delete.
 637         * openrisc-desc.c: Delete.
 638         * openrisc-desc.h: Delete.
 639         * openrisc-dis.c: Delete.
 640         * openrisc-ibld.c: Delete.
 641         * openrisc-opc.c: Delete.
 642         * openrisc-opc.h: Delete.
 643         * or32-dis.c: Delete.
 644         * or32-opc.c: Delete.
 645
 646 2014-04-04  Ilya Tocar  <ilya.tocar@intel.com>
 647
 648         * i386-dis.c (rm_table): Add encls, enclu.
 649         * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
 650         (cpu_flags): Add CpuSE1.
 651         * i386-opc.h (enum): Add CpuSE1.
 652         (i386_cpu_flags): Add cpuse1.
 653         * i386-opc.tbl: Add encls, enclu.
 654         * i386-init.h: Regenerated.
 655         * i386-tbl.h: Likewise.
 656
 657 2014-04-02  Anthony Green  <green@moxielogic.com>
 658
 659         * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
 660         instructions, sex.b and sex.s.
 661
 662 2014-03-26  Jiong Wang  <jiong.wang@arm.com>
 663
 664         * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
 665         instructions.
 666
 667 2014-03-20  Ilya Tocar  <ilya.tocar@intel.com>
 668
 669         * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
 670         vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
 671         vscatterqps.
 672         * i386-tbl.h: Regenerate.
 673
 674 2014-03-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 675
 676         * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
 677         %hstick_enable added.
 678
 679 2014-03-19  Nick Clifton  <nickc@redhat.com>
 680
 681         * rx-decode.opc (bwl): Allow for bogus instructions with a size
 682         field of 3.
 683         (sbwl, ubwl, SCALE): Likewise.
 684         * rx-decode.c: Regenerate.
 685
 686 2014-03-12  Alan Modra  <amodra@gmail.com>
 687
 688         * Makefile.in: Regenerate.
 689
 690 2014-03-05  Alan Modra  <amodra@gmail.com>
 691
 692         Update copyright years.
 693
 694 2014-03-04  Heiher  <r@hev.cc>
 695
 696         * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
 697
 698 2014-03-04  Richard Sandiford  <rdsandiford@googlemail.com>
 699
 700         * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
 701         so that they come after the Loongson extensions.
 702
 703 2014-03-03  Alan Modra  <amodra@gmail.com>
 704
 705         * i386-gen.c (process_copyright): Emit copyright notice on one line.
 706
 707 2014-02-28  Alan Modra  <amodra@gmail.com>
 708
 709         * msp430-decode.c: Regenerate.
 710
 711 2014-02-27  Jiong Wang  <jiong.wang@arm.com>
 712
 713         * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
 714         FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
 715
 716 2014-02-27  Yufeng Zhang  <yufeng.zhang@arm.com>
 717
 718         * aarch64-opc.c (print_register_offset_address): Call
 719         get_int_reg_name to prepare the register name.
 720
 721 2014-02-25  Ilya Tocar  <ilya.tocar@intel.com>
 722
 723         * i386-opc.tbl: Remove wrong variant of vcvtps2ph
 724         * i386-tbl.h: Regenerate.
 725
 726 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 727
 728         * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
 729         (cpu_flags): Add CpuPREFETCHWT1.
 730         * i386-init.h: Regenerate.
 731         * i386-opc.h (CpuPREFETCHWT1): New.
 732         (i386_cpu_flags): Add cpuprefetchwt1.
 733         * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
 734         * i386-tbl.h: Regenerate.
 735
 736 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 737
 738         * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
 739         to CpuAVX512F.
 740         * i386-tbl.h: Regenerate.
 741
 742 2014-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 743
 744         * i386-gen.c (output_cpu_flags): Don't output trailing space.
 745         (output_opcode_modifier): Likewise.
 746         (output_operand_type): Likewise.
 747         * i386-init.h: Regenerated.
 748         * i386-tbl.h: Likewise.
 749
 750 2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>
 751
 752         * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
 753         MOD_0FC7_REG_5.
 754         (PREFIX enum): Add PREFIX_0FAE_REG_7.
 755         (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
 756         (prefix_table): Add clflusopt.
 757         (mod_table): Add xrstors, xsavec, xsaves.
 758         * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
 759         CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
 760         (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
 761         * i386-init.h: Regenerate.
 762         * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
 763         xsaves64, xsavec, xsavec64.
 764         * i386-tbl.h: Regenerate.
 765
 766 2014-02-10  Alan Modra  <amodra@gmail.com>
 767
 768         * po/POTFILES.in: Regenerate.
 769         * po/opcodes.pot: Regenerate.
 770
 771 2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
 772             Jan Beulich  <jbeulich@suse.com>
 773
 774         PR binutils/16490
 775         * i386-dis.c (OP_E_memory): Fix shift computation for
 776         vex_vsib_q_w_dq_mode.
 777
 778 2014-01-09  Bradley Nelson  <bradnelson@google.com>
 779             Roland McGrath  <mcgrathr@google.com>
 780
 781         * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
 782         last_rex_prefix is -1.
 783
 784 2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 785
 786         * i386-gen.c (process_copyright): Update copyright year to 2014.
 787
 788 2014-01-03  Maciej W. Rozycki  <macro@codesourcery.com>
 789
 790         * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
 791
 792 For older changes see ChangeLog-2013
 793 \f
 794 Copyright (C) 2014 Free Software Foundation, Inc.
 795
 796 Copying and distribution of this file, with or without modification,
 797 are permitted in any medium without royalty provided the copyright
 798 notice and this notice are preserved.
 799
 800 Local Variables:
 801 mode: change-log
 802 left-margin: 8
 803 fill-column: 74
 804 version-control: never
 805 End: