opcodes/ChangeLog

   1 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
   2
   3         * mips-opc.c (mips_builtin_opcodes): Change source register
   4         constraint for DAUI.
   5
   6 2019-05-20  Nick Clifton  <nickc@redhat.com>
   7
   8         * po/fr.po: Updated French translation.
   9
  10 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  11             Michael Collison <michael.collison@arm.com>
  12
  13         * arm-dis.c (thumb32_opcodes): Add new instructions.
  14         (enum mve_instructions): Likewise.
  15         (enum mve_undefined): Add new reasons.
  16         (is_mve_encoding_conflict): Handle new instructions.
  17         (is_mve_undefined): Likewise.
  18         (is_mve_unpredictable): Likewise.
  19         (print_mve_undefined): Likewise.
  20         (print_mve_size): Likewise.
  21
  22 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  23             Michael Collison <michael.collison@arm.com>
  24
  25         * arm-dis.c (thumb32_opcodes): Add new instructions.
  26         (enum mve_instructions): Likewise.
  27         (is_mve_encoding_conflict): Handle new instructions.
  28         (is_mve_undefined): Likewise.
  29         (is_mve_unpredictable): Likewise.
  30         (print_mve_size): Likewise.
  31
  32 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  33             Michael Collison <michael.collison@arm.com>
  34
  35         * arm-dis.c (thumb32_opcodes): Add new instructions.
  36         (enum mve_instructions): Likewise.
  37         (is_mve_encoding_conflict): Likewise.
  38         (is_mve_unpredictable): Likewise.
  39         (print_mve_size): Likewise.
  40
  41 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  42             Michael Collison <michael.collison@arm.com>
  43
  44         * arm-dis.c (thumb32_opcodes): Add new instructions.
  45         (enum mve_instructions): Likewise.
  46         (is_mve_encoding_conflict): Handle new instructions.
  47         (is_mve_undefined): Likewise.
  48         (is_mve_unpredictable): Likewise.
  49         (print_mve_size): Likewise.
  50
  51 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  52             Michael Collison <michael.collison@arm.com>
  53
  54         * arm-dis.c (thumb32_opcodes): Add new instructions.
  55         (enum mve_instructions): Likewise.
  56         (is_mve_encoding_conflict): Handle new instructions.
  57         (is_mve_undefined): Likewise.
  58         (is_mve_unpredictable): Likewise.
  59         (print_mve_size): Likewise.
  60         (print_insn_mve): Likewise.
  61
  62 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  63             Michael Collison <michael.collison@arm.com>
  64
  65         * arm-dis.c (thumb32_opcodes): Add new instructions.
  66         (print_insn_thumb32): Handle new instructions.
  67
  68 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  69             Michael Collison <michael.collison@arm.com>
  70
  71         * arm-dis.c (enum mve_instructions): Add new instructions.
  72         (enum mve_undefined): Add new reasons.
  73         (is_mve_encoding_conflict): Handle new instructions.
  74         (is_mve_undefined): Likewise.
  75         (is_mve_unpredictable): Likewise.
  76         (print_mve_undefined): Likewise.
  77         (print_mve_size): Likewise.
  78         (print_mve_shift_n): Likewise.
  79         (print_insn_mve): Likewise.
  80
  81 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  82             Michael Collison <michael.collison@arm.com>
  83
  84         * arm-dis.c (enum mve_instructions): Add new instructions.
  85         (is_mve_encoding_conflict): Handle new instructions.
  86         (is_mve_unpredictable): Likewise.
  87         (print_mve_rotate): Likewise.
  88         (print_mve_size): Likewise.
  89         (print_insn_mve): Likewise.
  90
  91 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  92             Michael Collison <michael.collison@arm.com>
  93
  94         * arm-dis.c (enum mve_instructions): Add new instructions.
  95         (is_mve_encoding_conflict): Handle new instructions.
  96         (is_mve_unpredictable): Likewise.
  97         (print_mve_size): Likewise.
  98         (print_insn_mve): Likewise.
  99
 100 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 101             Michael Collison <michael.collison@arm.com>
 102
 103         * arm-dis.c (enum mve_instructions): Add new instructions.
 104         (enum mve_undefined): Add new reasons.
 105         (is_mve_encoding_conflict): Handle new instructions.
 106         (is_mve_undefined): Likewise.
 107         (is_mve_unpredictable): Likewise.
 108         (print_mve_undefined): Likewise.
 109         (print_mve_size): Likewise.
 110         (print_insn_mve): Likewise.
 111
 112 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 113             Michael Collison <michael.collison@arm.com>
 114
 115         * arm-dis.c (enum mve_instructions): Add new instructions.
 116         (is_mve_encoding_conflict): Handle new instructions.
 117         (is_mve_undefined): Likewise.
 118         (is_mve_unpredictable): Likewise.
 119         (print_mve_size): Likewise.
 120         (print_insn_mve): Likewise.
 121
 122 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 123             Michael Collison <michael.collison@arm.com>
 124
 125         * arm-dis.c (enum mve_instructions): Add new instructions.
 126         (enum mve_unpredictable): Add new reasons.
 127         (enum mve_undefined): Likewise.
 128         (is_mve_okay_in_it): Handle new isntructions.
 129         (is_mve_encoding_conflict): Likewise.
 130         (is_mve_undefined): Likewise.
 131         (is_mve_unpredictable): Likewise.
 132         (print_mve_vmov_index): Likewise.
 133         (print_simd_imm8): Likewise.
 134         (print_mve_undefined): Likewise.
 135         (print_mve_unpredictable): Likewise.
 136         (print_mve_size): Likewise.
 137         (print_insn_mve): Likewise.
 138
 139 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 140             Michael Collison <michael.collison@arm.com>
 141
 142         * arm-dis.c (enum mve_instructions): Add new instructions.
 143         (enum mve_unpredictable): Add new reasons.
 144         (enum mve_undefined): Likewise.
 145         (is_mve_encoding_conflict): Handle new instructions.
 146         (is_mve_undefined): Likewise.
 147         (is_mve_unpredictable): Likewise.
 148         (print_mve_undefined): Likewise.
 149         (print_mve_unpredictable): Likewise.
 150         (print_mve_rounding_mode): Likewise.
 151         (print_mve_vcvt_size): Likewise.
 152         (print_mve_size): Likewise.
 153         (print_insn_mve): Likewise.
 154
 155 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 156             Michael Collison <michael.collison@arm.com>
 157
 158         * arm-dis.c (enum mve_instructions): Add new instructions.
 159         (enum mve_unpredictable): Add new reasons.
 160         (enum mve_undefined): Likewise.
 161         (is_mve_undefined): Handle new instructions.
 162         (is_mve_unpredictable): Likewise.
 163         (print_mve_undefined): Likewise.
 164         (print_mve_unpredictable): Likewise.
 165         (print_mve_size): Likewise.
 166         (print_insn_mve): Likewise.
 167
 168 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 169             Michael Collison <michael.collison@arm.com>
 170
 171         * arm-dis.c (enum mve_instructions): Add new instructions.
 172         (enum mve_undefined): Add new reasons.
 173         (insns): Add new instructions.
 174         (is_mve_encoding_conflict):
 175         (print_mve_vld_str_addr): New print function.
 176         (is_mve_undefined): Handle new instructions.
 177         (is_mve_unpredictable): Likewise.
 178         (print_mve_undefined): Likewise.
 179         (print_mve_size): Likewise.
 180         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 181         (print_insn_mve):  Handle new operands.
 182
 183 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 184             Michael Collison <michael.collison@arm.com>
 185
 186         * arm-dis.c (enum mve_instructions): Add new instructions.
 187         (enum mve_unpredictable): Add new reasons.
 188         (is_mve_encoding_conflict): Handle new instructions.
 189         (is_mve_unpredictable): Likewise.
 190         (mve_opcodes): Add new instructions.
 191         (print_mve_unpredictable): Handle new reasons.
 192         (print_mve_register_blocks): New print function.
 193         (print_mve_size): Handle new instructions.
 194         (print_insn_mve): Likewise.
 195
 196 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 197             Michael Collison <michael.collison@arm.com>
 198
 199         * arm-dis.c (enum mve_instructions): Add new instructions.
 200         (enum mve_unpredictable): Add new reasons.
 201         (enum mve_undefined): Likewise.
 202         (is_mve_encoding_conflict): Handle new instructions.
 203         (is_mve_undefined): Likewise.
 204         (is_mve_unpredictable): Likewise.
 205         (coprocessor_opcodes): Move NEON VDUP from here...
 206         (neon_opcodes): ... to here.
 207         (mve_opcodes): Add new instructions.
 208         (print_mve_undefined):  Handle new reasons.
 209         (print_mve_unpredictable): Likewise.
 210         (print_mve_size): Handle new instructions.
 211         (print_insn_neon): Handle vdup.
 212         (print_insn_mve): Handle new operands.
 213
 214 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 215             Michael Collison <michael.collison@arm.com>
 216
 217         * arm-dis.c (enum mve_instructions): Add new instructions.
 218         (enum mve_unpredictable): Add new values.
 219         (mve_opcodes): Add new instructions.
 220         (vec_condnames): New array with vector conditions.
 221         (mve_predicatenames): New array with predicate suffixes.
 222         (mve_vec_sizename): New array with vector sizes.
 223         (enum vpt_pred_state): New enum with vector predication states.
 224         (struct vpt_block): New struct type for vpt blocks.
 225         (vpt_block_state): Global struct to keep track of state.
 226         (mve_extract_pred_mask): New helper function.
 227         (num_instructions_vpt_block): Likewise.
 228         (mark_outside_vpt_block): Likewise.
 229         (mark_inside_vpt_block): Likewise.
 230         (invert_next_predicate_state): Likewise.
 231         (update_next_predicate_state): Likewise.
 232         (update_vpt_block_state): Likewise.
 233         (is_vpt_instruction): Likewise.
 234         (is_mve_encoding_conflict): Add entries for new instructions.
 235         (is_mve_unpredictable): Likewise.
 236         (print_mve_unpredictable): Handle new cases.
 237         (print_instruction_predicate): Likewise.
 238         (print_mve_size): New function.
 239         (print_vec_condition): New function.
 240         (print_insn_mve): Handle vpt blocks and new print operands.
 241
 242 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 243
 244         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 245         8, 14 and 15 for Armv8.1-M Mainline.
 246
 247 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 248             Michael Collison <michael.collison@arm.com>
 249
 250         * arm-dis.c (enum mve_instructions): New enum.
 251         (enum mve_unpredictable): Likewise.
 252         (enum mve_undefined): Likewise.
 253         (struct mopcode32): New struct.
 254         (is_mve_okay_in_it): New function.
 255         (is_mve_architecture): Likewise.
 256         (arm_decode_field): Likewise.
 257         (arm_decode_field_multiple): Likewise.
 258         (is_mve_encoding_conflict): Likewise.
 259         (is_mve_undefined): Likewise.
 260         (is_mve_unpredictable): Likewise.
 261         (print_mve_undefined): Likewise.
 262         (print_mve_unpredictable): Likewise.
 263         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 264         (print_insn_mve): New function.
 265         (print_insn_thumb32): Handle MVE architecture.
 266         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 267
 268 2019-05-10  Nick Clifton  <nickc@redhat.com>
 269
 270         PR 24538
 271         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 272         end of the table prematurely.
 273
 274 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 275
 276         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 277         macros for R6.
 278
 279 2019-05-11  Alan Modra  <amodra@gmail.com>
 280
 281         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 282         when -Mraw is in effect.
 283
 284 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 285
 286         * aarch64-dis-2.c: Regenerate.
 287         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 288         (OP_SVE_BBB): New variant set.
 289         (OP_SVE_DDDD): New variant set.
 290         (OP_SVE_HHH): New variant set.
 291         (OP_SVE_HHHU): New variant set.
 292         (OP_SVE_SSS): New variant set.
 293         (OP_SVE_SSSU): New variant set.
 294         (OP_SVE_SHH): New variant set.
 295         (OP_SVE_SBBU): New variant set.
 296         (OP_SVE_DSS): New variant set.
 297         (OP_SVE_DHHU): New variant set.
 298         (OP_SVE_VMV_HSD_BHS): New variant set.
 299         (OP_SVE_VVU_HSD_BHS): New variant set.
 300         (OP_SVE_VVVU_SD_BH): New variant set.
 301         (OP_SVE_VVVU_BHSD): New variant set.
 302         (OP_SVE_VVV_QHD_DBS): New variant set.
 303         (OP_SVE_VVV_HSD_BHS): New variant set.
 304         (OP_SVE_VVV_HSD_BHS2): New variant set.
 305         (OP_SVE_VVV_BHS_HSD): New variant set.
 306         (OP_SVE_VV_BHS_HSD): New variant set.
 307         (OP_SVE_VVV_SD): New variant set.
 308         (OP_SVE_VVU_BHS_HSD): New variant set.
 309         (OP_SVE_VZVV_SD): New variant set.
 310         (OP_SVE_VZVV_BH): New variant set.
 311         (OP_SVE_VZV_SD): New variant set.
 312         (aarch64_opcode_table): Add sve2 instructions.
 313
 314 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 315
 316         * aarch64-asm-2.c: Regenerated.
 317         * aarch64-dis-2.c: Regenerated.
 318         * aarch64-opc-2.c: Regenerated.
 319         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 320         for SVE_SHLIMM_UNPRED_22.
 321         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 322         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 323         operand.
 324
 325 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 326
 327         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 328         sve_size_tsz_bhs iclass encode.
 329         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 330         sve_size_tsz_bhs iclass decode.
 331
 332 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 333
 334         * aarch64-asm-2.c: Regenerated.
 335         * aarch64-dis-2.c: Regenerated.
 336         * aarch64-opc-2.c: Regenerated.
 337         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 338         for SVE_Zm4_11_INDEX.
 339         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 340         (fields): Handle SVE_i2h field.
 341         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 342         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 343
 344 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 345
 346         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 347         sve_shift_tsz_bhsd iclass encode.
 348         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 349         sve_shift_tsz_bhsd iclass decode.
 350
 351 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 352
 353         * aarch64-asm-2.c: Regenerated.
 354         * aarch64-dis-2.c: Regenerated.
 355         * aarch64-opc-2.c: Regenerated.
 356         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 357         (aarch64_encode_variant_using_iclass): Handle
 358         sve_shift_tsz_hsd iclass encode.
 359         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 360         sve_shift_tsz_hsd iclass decode.
 361         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 362         for SVE_SHRIMM_UNPRED_22.
 363         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 364         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 365         operand.
 366
 367 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 368
 369         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 370         sve_size_013 iclass encode.
 371         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 372         sve_size_013 iclass decode.
 373
 374 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 375
 376         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 377         sve_size_bh iclass encode.
 378         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 379         sve_size_bh iclass decode.
 380
 381 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 382
 383         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 384         sve_size_sd2 iclass encode.
 385         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 386         sve_size_sd2 iclass decode.
 387         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 388         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 389
 390 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 391
 392         * aarch64-asm-2.c: Regenerated.
 393         * aarch64-dis-2.c: Regenerated.
 394         * aarch64-opc-2.c: Regenerated.
 395         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 396         for SVE_ADDR_ZX.
 397         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 398         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 399
 400 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 401
 402         * aarch64-asm-2.c: Regenerated.
 403         * aarch64-dis-2.c: Regenerated.
 404         * aarch64-opc-2.c: Regenerated.
 405         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 406         for SVE_Zm3_11_INDEX.
 407         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 408         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 409         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 410         fields.
 411         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 412
 413 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 414
 415         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 416         sve_size_hsd2 iclass encode.
 417         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 418         sve_size_hsd2 iclass decode.
 419         * aarch64-opc.c (fields): Handle SVE_size field.
 420         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 421
 422 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 423
 424         * aarch64-asm-2.c: Regenerated.
 425         * aarch64-dis-2.c: Regenerated.
 426         * aarch64-opc-2.c: Regenerated.
 427         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 428         for SVE_IMM_ROT3.
 429         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 430         (fields): Handle SVE_rot3 field.
 431         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 432         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 433
 434 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 435
 436         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 437         instructions.
 438
 439 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 440
 441         * aarch64-tbl.h
 442         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 443         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 444         aarch64_feature_sve2bitperm): New feature sets.
 445         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 446         for feature set addresses.
 447         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 448         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 449
 450 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 451             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 452
 453         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 454         argument and set ASE_EVA_R6 appropriately.
 455         (set_default_mips_dis_options): Pass ISA to above.
 456         (parse_mips_dis_option): Likewise.
 457         * mips-opc.c (EVAR6): New macro.
 458         (mips_builtin_opcodes): Add llwpe, scwpe.
 459
 460 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 461
 462         * aarch64-asm-2.c: Regenerated.
 463         * aarch64-dis-2.c: Regenerated.
 464         * aarch64-opc-2.c: Regenerated.
 465         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 466         AARCH64_OPND_TME_UIMM16.
 467         (aarch64_print_operand): Likewise.
 468         * aarch64-tbl.h (QL_IMM_NIL): New.
 469         (TME): New.
 470         (_TME_INSN): New.
 471         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 472
 473 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 474
 475         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 476
 477 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 478             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 479
 480         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 481
 482 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 483
 484         * s12z-opc.h: Add extern "C" bracketing to help
 485         users who wish to use this interface in c++ code.
 486
 487 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 488
 489         * s12z-opc.c (bm_decode): Handle bit map operations with the
 490         "reserved0" mode.
 491
 492 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 493
 494         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 495         specifier.  Add entries for VLDR and VSTR of system registers.
 496         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 497         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 498         of %J and %K format specifier.
 499
 500 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 501
 502         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 503         Add new entries for VSCCLRM instruction.
 504         (print_insn_coprocessor): Handle new %C format control code.
 505
 506 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 507
 508         * arm-dis.c (enum isa): New enum.
 509         (struct sopcode32): New structure.
 510         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 511         set isa field of all current entries to ANY.
 512         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 513         Only match an entry if its isa field allows the current mode.
 514
 515 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 516
 517         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 518         CLRM.
 519         (print_insn_thumb32): Add logic to print %n CLRM register list.
 520
 521 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 522
 523         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 524         and %Q patterns.
 525
 526 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 527
 528         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 529         (print_insn_thumb32): Edit the switch case for %Z.
 530
 531 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 532
 533         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 534
 535 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 536
 537         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 538
 539 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 540
 541         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 542
 543 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 544
 545         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 546         Arm register with r13 and r15 unpredictable.
 547         (thumb32_opcodes): New instructions for bfx and bflx.
 548
 549 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 550
 551         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 552
 553 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 554
 555         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 556
 557 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 558
 559         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 560
 561 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 562
 563         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 564
 565 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 566
 567         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 568         "optr". ("operator" is a reserved word in c++).
 569
 570 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 571
 572         * aarch64-opc.c (aarch64_print_operand): Add case for
 573         AARCH64_OPND_Rt_SP.
 574         (verify_constraints): Likewise.
 575         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 576         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 577         to accept Rt|SP as first operand.
 578         (AARCH64_OPERANDS): Add new Rt_SP.
 579         * aarch64-asm-2.c: Regenerated.
 580         * aarch64-dis-2.c: Regenerated.
 581         * aarch64-opc-2.c: Regenerated.
 582
 583 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 584
 585         * aarch64-asm-2.c: Regenerated.
 586         * aarch64-dis-2.c: Likewise.
 587         * aarch64-opc-2.c: Likewise.
 588         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 589
 590 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 591
 592         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 593
 594 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 595
 596         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 597         * i386-init.h: Regenerated.
 598
 599 2019-04-07  Alan Modra  <amodra@gmail.com>
 600
 601         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 602         op_separator to control printing of spaces, comma and parens
 603         rather than need_comma, need_paren and spaces vars.
 604
 605 2019-04-07  Alan Modra  <amodra@gmail.com>
 606
 607         PR 24421
 608         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 609         (print_insn_neon, print_insn_arm): Likewise.
 610
 611 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 612
 613         * i386-dis-evex.h (evex_table): Updated to support BF16
 614         instructions.
 615         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 616         and EVEX_W_0F3872_P_3.
 617         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 618         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 619         * i386-opc.h (enum): Add CpuAVX512_BF16.
 620         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 621         * i386-opc.tbl: Add AVX512 BF16 instructions.
 622         * i386-init.h: Regenerated.
 623         * i386-tbl.h: Likewise.
 624
 625 2019-04-05  Alan Modra  <amodra@gmail.com>
 626
 627         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 628         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 629         to favour printing of "-" branch hint when using the "y" bit.
 630         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 631
 632 2019-04-05  Alan Modra  <amodra@gmail.com>
 633
 634         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 635         opcode until first operand is output.
 636
 637 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 638
 639         PR gas/24349
 640         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 641         (valid_bo_post_v2): Add support for 'at' branch hints.
 642         (insert_bo): Only error on branch on ctr.
 643         (get_bo_hint_mask): New function.
 644         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 645         for inserting 'at' branch hints.
 646         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 647         for extracting 'at' branch hints.
 648         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 649         (BOE): Delete operand.
 650         (BOM, BOP): New operands.
 651         (RM): Update value.
 652         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 653         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 654         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 655         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 656         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 657         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 658         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 659         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 660         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 661         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 662         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 663         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 664         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 665         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 666         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 667         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 668         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 669         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 670         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 671         bttarl+>: New extended mnemonics.
 672
 673 2019-03-28  Alan Modra  <amodra@gmail.com>
 674
 675         PR 24390
 676         * ppc-opc.c (BTF): Define.
 677         (powerpc_opcodes): Use for mtfsb*.
 678         * ppc-dis.c (print_insn_powerpc): Print fields with both
 679         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 680
 681 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 682
 683         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 684         (mapping_symbol_for_insn): Implement new algorithm.
 685         (print_insn): Remove duplicate code.
 686
 687 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 688
 689         * aarch64-dis.c (print_insn_aarch64):
 690         Implement override.
 691
 692 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 693
 694         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 695         order.
 696
 697 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 698
 699         * aarch64-dis.c (last_stop_offset): New.
 700         (print_insn_aarch64): Use stop_offset.
 701
 702 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 703
 704         PR gas/24359
 705         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 706         CPU_ANY_AVX2_FLAGS.
 707         * i386-init.h: Regenerated.
 708
 709 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 710
 711         PR gas/24348
 712         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 713         vmovdqu16, vmovdqu32 and vmovdqu64.
 714         * i386-tbl.h: Regenerated.
 715
 716 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 717
 718         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 719         from vstrszb, vstrszh, and vstrszf.
 720
 721 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 722
 723         * s390-opc.txt: Add instruction descriptions.
 724
 725 2019-02-08  Jim Wilson  <jimw@sifive.com>
 726
 727         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 728         <bne>: Likewise.
 729
 730 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 731
 732         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 733
 734 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 735
 736         PR binutils/23212
 737         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 738         * aarch64-opc.c (verify_elem_sd): New.
 739         (fields): Add FLD_sz entr.
 740         * aarch64-tbl.h (_SIMD_INSN): New.
 741         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 742         fmulx scalar and vector by element isns.
 743
 744 2019-02-07  Nick Clifton  <nickc@redhat.com>
 745
 746         * po/sv.po: Updated Swedish translation.
 747
 748 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 749
 750         * s390-mkopc.c (main): Accept arch13 as cpu string.
 751         * s390-opc.c: Add new instruction formats and instruction opcode
 752         masks.
 753         * s390-opc.txt: Add new arch13 instructions.
 754
 755 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 756
 757         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 758         (aarch64_opcode): Change encoding for stg, stzg
 759         st2g and st2zg.
 760         * aarch64-asm-2.c: Regenerated.
 761         * aarch64-dis-2.c: Regenerated.
 762         * aarch64-opc-2.c: Regenerated.
 763
 764 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 765
 766         * aarch64-asm-2.c: Regenerated.
 767         * aarch64-dis-2.c: Likewise.
 768         * aarch64-opc-2.c: Likewise.
 769         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 770
 771 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 772             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 773
 774         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 775         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 776         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 777         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 778         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 779         case for ldstgv_indexed.
 780         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 781         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 782         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 783         * aarch64-asm-2.c: Regenerated.
 784         * aarch64-dis-2.c: Regenerated.
 785         * aarch64-opc-2.c: Regenerated.
 786
 787 2019-01-23  Nick Clifton  <nickc@redhat.com>
 788
 789         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 790
 791 2019-01-21  Nick Clifton  <nickc@redhat.com>
 792
 793         * po/de.po: Updated German translation.
 794         * po/uk.po: Updated Ukranian translation.
 795
 796 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 797         * mips-dis.c (mips_arch_choices): Fix typo in
 798         gs464, gs464e and gs264e descriptors.
 799
 800 2019-01-19  Nick Clifton  <nickc@redhat.com>
 801
 802         * configure: Regenerate.
 803         * po/opcodes.pot: Regenerate.
 804
 805 2018-06-24  Nick Clifton  <nickc@redhat.com>
 806
 807         2.32 branch created.
 808
 809 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 810
 811         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 812         if it is null.
 813         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 814         zero.
 815
 816 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 817
 818         * configure: Regenerate.
 819
 820 2019-01-07  Alan Modra  <amodra@gmail.com>
 821
 822         * configure: Regenerate.
 823         * po/POTFILES.in: Regenerate.
 824
 825 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 826
 827         * s12z-opc.c: New file.
 828         * s12z-opc.h: New file.
 829         * s12z-dis.c: Removed all code not directly related to display
 830         of instructions.  Used the interface provided by the new files
 831         instead.
 832         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 833         * Makefile.in: Regenerate.
 834         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 835         * configure: Regenerate.
 836
 837 2019-01-01  Alan Modra  <amodra@gmail.com>
 838
 839         Update year range in copyright notice of all files.
 840
 841 For older changes see ChangeLog-2018
 842 \f
 843 Copyright (C) 2019 Free Software Foundation, Inc.
 844
 845 Copying and distribution of this file, with or without modification,
 846 are permitted in any medium without royalty provided the copyright
 847 notice and this notice are preserved.
 848
 849 Local Variables:
 850 mode: change-log
 851 left-margin: 8
 852 fill-column: 74
 853 version-control: never
 854 End: