opcodes/ChangeLog

   1 2010-09-28  Pierre Muller  <muller@ics.u-strasbg.fr>
   2
   3         * s390-mkopc.c (main): Change description array size to 80.
   4         Add maximum length of 79 to description parsing.
   5
   6 2010-09-27  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
   7
   8         * configure: Regenerate.
   9
  10 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  11
  12         * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
  13         (main): Recognize the new CPU string.
  14         * s390-opc.c: Add new instruction formats and masks.
  15         * s390-opc.txt: Add new z196 instructions.
  16
  17 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  18
  19         * s390-dis.c (print_insn_s390): Pick instruction with most
  20         specific mask.
  21         * s390-opc.c: Add unused bits to the insn mask.
  22         * s390-opc.txt: Reorder some instructions to prefer more recent
  23         versions.
  24
  25 2010-09-27  Tejas Belagod  <tejas.belagod@arm.com>
  26
  27         * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
  28         correction to unaligned PCs while printing comment.
  29
  30 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  31
  32         * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
  33         (thumb32_opcodes): Likewise.
  34         (banked_regname): New function.
  35         (print_insn_arm): Add Virtualization Extensions support.
  36         (print_insn_thumb32): Likewise.
  37
  38 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  39
  40         * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
  41         ARM state.
  42
  43 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  44
  45         * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
  46         (thumb32_opcodes): Likewise.
  47
  48 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  49
  50         * arm-dis.c (arm_opcodes): Add support for pldw.
  51         (thumb32_opcodes): Likewise.
  52
  53 2010-09-22  Robin Getz  <robin.getz@analog.com>
  54
  55         * bfin-dis.c (fmtconst): Cast address to 32bits.
  56
  57 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  58
  59         * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
  60
  61 2010-09-22  Robin Getz  <robin.getz@analog.com>
  62
  63         * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
  64         Reject P6/P7 to TESTSET.
  65         (decode_PushPopReg_0): Check for parallel insns.  Reject pushing
  66         SP onto the stack.
  67         (decode_PushPopMultiple_0): Check for parallel insns.  Make sure
  68         P/D fields match all the time.
  69         (decode_CCflag_0): Check for parallel insns.  Verify x/y fields
  70         are 0 for accumulator compares.
  71         (decode_CC2stat_0): Check for parallel insns.  Reject CC<op>CC.
  72         (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
  73         decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
  74         decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
  75         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
  76         decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
  77         insns.
  78         (decode_dagMODim_0): Verify br field for IREG ops.
  79         (decode_LDST_0): Reject preg load into same preg.
  80         (_print_insn_bfin): Handle returns for ILLEGAL decodes.
  81         (print_insn_bfin): Likewise.
  82
  83 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  84
  85         * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
  86
  87 2010-09-22  Robin Getz  <robin.getz@analog.com>
  88
  89         * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
  90
  91 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  92
  93         * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
  94
  95 2010-09-22  Robin Getz  <robin.getz@analog.com>
  96
  97         * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
  98         register values greater than 8.
  99         (IS_RESERVEDREG, allreg, mostreg): New helpers.
 100         (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
 101         (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
 102         (decode_CC2dreg_0): Check valid CC register number.
 103
 104 2010-09-22  Robin Getz  <robin.getz@analog.com>
 105
 106         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
 107
 108 2010-09-22  Robin Getz  <robin.getz@analog.com>
 109
 110         * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
 111         (reg_names): Likewise.
 112         (decode_statbits): Likewise; while reformatting to make manageable.
 113
 114 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 115
 116         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
 117         (decode_pseudoOChar_0): New function.
 118         (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
 119
 120 2010-09-22  Robin Getz  <robin.getz@analog.com>
 121
 122         * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
 123         LSHIFT instead of SHIFT.
 124
 125 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 126
 127         * bfin-dis.c (constant_formats): Constify the whole structure.
 128         (fmtconst): Add const to return value.
 129         (reg_names): Mark const.
 130         (decode_multfunc): Mark s0/s1 as const.
 131         (decode_macfunc): Mark a/sop as const.
 132
 133 2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
 134
 135         * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
 136
 137 2010-09-14  Maciej W. Rozycki  <macro@codesourcery.com>
 138
 139         * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
 140         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
 141
 142 2010-09-10  Pierre Muller  <muller@ics.u-strasbg.fr>
 143
 144         * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
 145         dlx_insn_type array.
 146
 147 2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>
 148
 149         PR binutils/11960
 150         * i386-dis.c (sIv): New.
 151         (dis386): Replace Iq with sIv on "pushT".
 152         (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
 153         (x86_64_table): Replace {T|}/{P|} with P.
 154         (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
 155         (OP_sI): Update v_mode.  Remove w_mode.
 156
 157 2010-08-27  Nathan Froyd  <froydnj@codesourcery.com>
 158
 159         * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
 160         on E500 and E500MC.
 161
 162 2010-08-17  H.J. Lu  <hongjiu.lu@intel.com>
 163
 164         * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
 165         prefetchw.
 166
 167 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 168
 169         * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
 170         to processor flags for PENTIUMPRO processors and later.
 171         * i386-opc.h (enum): Add CpuNop.
 172         (i386_cpu_flags): Add cpunop bit.
 173         * i386-opc.tbl: Change nop cpu_flags.
 174         * i386-init.h: Regenerated.
 175         * i386-tbl.h: Likewise.
 176
 177 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 178
 179         * i386-opc.h (enum): Fix typos in comments.
 180
 181 2010-08-06  Alan Modra  <amodra@gmail.com>
 182
 183         * disassemble.c: Formatting.
 184         (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
 185
 186 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 187
 188         * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
 189         * i386-tbl.h: Regenerated.
 190
 191 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 192
 193         * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
 194
 195         * i386-opc.tbl: Add ud1.  Remove Cpu686 from ud2/ud2a/ud2b.
 196         * i386-tbl.h: Regenerated.
 197
 198 2010-07-29  DJ Delorie  <dj@redhat.com>
 199
 200         * rx-decode.opc (SRR): New.
 201         (rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
 202         r0,r0) and NOP3 (max r0,r0) special cases.
 203         * rx-decode.c: Regenerate.
 204
 205 2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>
 206
 207         * i386-dis.c: Add 0F to VEX opcode enums.
 208
 209 2010-07-27  DJ Delorie  <dj@redhat.com>
 210
 211         * rx-decode.opc (store_flags): Remove, replace with F_* macros.
 212         (rx_decode_opcode): Likewise.
 213         * rx-decode.c: Regenerate.
 214
 215 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 216             Ina Pandit  <ina.pandit@kpitcummins.com>
 217
 218         * v850-dis.c (v850_sreg_names): Updated structure for system
 219         registers.
 220         (float_cc_names): new structure for condition codes.
 221         (print_value): Update the function that prints value.
 222         (get_operand_value): New function to get the operand value.
 223         (disassemble): Updated to handle the disassembly of instructions.
 224         (print_insn_v850): Updated function to print instruction for different
 225         families.
 226         * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
 227         extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
 228         extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
 229         insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
 230         extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
 231         extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
 232         extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
 233         insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
 234         (insert_d8_7, insert_d5_4, insert_i5div): Remove.
 235         (v850_operands): Update with the relocation name. Also update
 236         the instructions with specific set of processors.
 237
 238 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
 239
 240         * arm-dis.c (print_insn_arm): Add cases for printing more
 241         symbolic operands.
 242         (print_insn_thumb32): Likewise.
 243
 244 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 245
 246         * mips-dis.c (print_insn_mips): Correct branch instruction type
 247         determination.
 248
 249 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 250
 251         * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
 252         type and delay slot determination.
 253         (print_insn_mips16): Extend branch instruction type and delay
 254         slot determination to cover all instructions.
 255         * mips16-opc.c (BR): Remove macro.
 256         (UBR, CBR): New macros.
 257         (mips16_opcodes): Update branch annotation for "b", "beqz",
 258         "bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
 259         and "jrc".
 260
 261 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 262
 263         AVX Programming Reference (June, 2010)
 264         * i386-dis.c (mod_table): Replace rdrnd with rdrand.
 265         * i386-opc.tbl: Likewise.
 266         * i386-tbl.h: Regenerated.
 267
 268 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 269
 270         * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
 271
 272 2010-07-03  Andreas Schwab  <schwab@linux-m68k.org>
 273
 274         * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
 275         ppc_cpu_t before inverting.
 276         (ppc_parse_cpu): Likewise.
 277         (print_insn_powerpc): Likewise.
 278
 279 2010-07-03  Alan Modra  <amodra@gmail.com>
 280
 281         * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
 282         * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
 283         (PPC64, MFDEC2): Update.
 284         (NON32, NO371): Define.
 285         (powerpc_opcode): Update to not use old opcode flags, and avoid
 286         -m601 duplicates.
 287
 288 2010-07-03  DJ Delorie  <dj@delorie.com>
 289
 290         * m32c-ibld.c: Regenerate.
 291
 292 2010-07-03  Alan Modra  <amodra@gmail.com>
 293
 294         * ppc-opc.c (PWR2COM): Define.
 295         (PPCPWR2): Add PPC_OPCODE_COMMON.
 296         (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
 297         "fcirz", "fcirz." to -mcom opcodes.  Remove "mfsri", "dclst",
 298         "rac" from -mcom.
 299
 300 2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>
 301
 302         AVX Programming Reference (June, 2010)
 303         * i386-dis.c (PREFIX_0FAE_REG_0): New.
 304         (PREFIX_0FAE_REG_1): Likewise.
 305         (PREFIX_0FAE_REG_2): Likewise.
 306         (PREFIX_0FAE_REG_3): Likewise.
 307         (PREFIX_VEX_3813): Likewise.
 308         (PREFIX_VEX_3A1D): Likewise.
 309         (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 310         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
 311         PREFIX_VEX_3A1D.
 312         (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
 313         (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 314         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
 315
 316         * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
 317         CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
 318         (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
 319
 320         * i386-opc.h (CpuXsaveopt): New.
 321         (CpuFSGSBase): Likewise.
 322         (CpuRdRnd): Likewise.
 323         (CpuF16C): Likewise.
 324         (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
 325         cpuf16c.
 326
 327         * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
 328         wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 329         * i386-init.h: Regenerated.
 330         * i386-tbl.h: Likewise.
 331
 332 2010-07-01  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 333
 334         * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
 335         and mtocrf on EFS.
 336
 337 2010-06-29  Alan Modra  <amodra@gmail.com>
 338
 339         * maxq-dis.c: Delete file.
 340         * Makefile.am: Remove references to maxq.
 341         * configure.in: Likewise.
 342         * disassemble.c: Likewise.
 343         * Makefile.in: Regenerate.
 344         * configure: Regenerate.
 345         * po/POTFILES.in: Regenerate.
 346
 347 2010-06-29  Alan Modra  <amodra@gmail.com>
 348
 349         * mep-dis.c: Regenerate.
 350
 351 2010-06-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 352
 353         * arm-disc.c (parse_insn_neon):  Fix Neon alignment syntax.
 354
 355 2010-06-27  Alan Modra  <amodra@gmail.com>
 356
 357         * arc-dis.c (arc_sprintf): Delete set but unused variables.
 358         (decodeInstr): Likewise.
 359         * dlx-dis.c (print_insn_dlx): Likewise.
 360         * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
 361         * maxq-dis.c (check_move, print_insn): Likewise.
 362         * mep-dis.c (mep_examine_ivc2_insns): Likewise.
 363         * msp430-dis.c (msp430_branchinstr): Likewise.
 364         * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
 365         * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
 366         * sparc-dis.c (print_insn_sparc): Likewise.
 367         * fr30-asm.c: Regenerate.
 368         * frv-asm.c: Regenerate.
 369         * ip2k-asm.c: Regenerate.
 370         * iq2000-asm.c: Regenerate.
 371         * lm32-asm.c: Regenerate.
 372         * m32c-asm.c: Regenerate.
 373         * m32r-asm.c: Regenerate.
 374         * mep-asm.c: Regenerate.
 375         * mt-asm.c: Regenerate.
 376         * openrisc-asm.c: Regenerate.
 377         * xc16x-asm.c: Regenerate.
 378         * xstormy16-asm.c: Regenerate.
 379
 380 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 381
 382         PR gas/11673
 383         * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
 384
 385 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 386
 387         PR binutils/11676
 388         * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
 389
 390 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 391
 392         * ppc-dis.c (ppc_opts):  Remove PPC_OPCODE_E500MC from e500 and
 393         e500x2.  Add PPC_OPCODE_E500 to e500 and e500x2
 394         * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
 395         touch floating point regs and are enabled by COM, PPC or PPCCOM.
 396         Treat sync as msync on e500.  Treat eieio as mbar 1 on e500.
 397         Treat lwsync as msync on e500.
 398
 399 2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 400
 401         * arm-dis.c (thumb-opcodes): Add disassembly for movs.
 402
 403 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 404
 405         * arm-dis.c (print_insn_neon):  Ensure disassembly of Neon
 406         constants is the same on 32-bit and 64-bit hosts.
 407
 408 2010-05-27  Jason Duerstock  <jason.duerstock+binutils@gmail.com>
 409
 410         * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
 411         .short directives so that they can be reassembled.
 412
 413 2010-05-26  Catherine Moore <clm@codesourcery.com>
 414             David Ung  <davidu@mips.com>
 415
 416         * mips-opc.c: Change membership to I1 for instructions ssnop and
 417         ehb.
 418
 419 2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>
 420
 421         * i386-dis.c (sib): New.
 422         (get_sib): Likewise.
 423         (print_insn): Call get_sib.
 424         OP_E_memory): Use sib.
 425
 426 2010-05-26  Catherine Moore  <clm@codesoourcery.com>
 427
 428         * mips-dis.c (mips_arch): Remove INSN_MIPS16.
 429         * mips-opc.c (I16): Remove.
 430         (mips_builtin_op): Reclassify jalx.
 431
 432 2010-05-19  Alan Modra  <amodra@gmail.com>
 433
 434         * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
 435         divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
 436
 437 2010-05-13  Alan Modra  <amodra@gmail.com>
 438
 439         * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
 440
 441 2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 442
 443         * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
 444         format.
 445         (print_insn_thumb16): Add support for new %W format.
 446
 447 2010-05-07  Tristan Gingold  <gingold@adacore.com>
 448
 449         * Makefile.in: Regenerate with automake 1.11.1.
 450         * aclocal.m4: Ditto.
 451
 452 2010-05-05  Nick Clifton  <nickc@redhat.com>
 453
 454         * po/es.po: Updated Spanish translation.
 455
 456 2010-04-22  Nick Clifton  <nickc@redhat.com>
 457
 458         * po/opcodes.pot: Updated by the Translation project.
 459         * po/vi.po: Updated Vietnamese translation.
 460
 461 2010-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 462
 463         * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
 464         bits in opcode.
 465
 466 2010-04-09  Nick Clifton  <nickc@redhat.com>
 467
 468         * i386-dis.c (print_insn): Remove unused variable op.
 469         (OP_sI): Remove unused variable mask.
 470
 471 2010-04-07  Alan Modra  <amodra@gmail.com>
 472
 473         * configure: Regenerate.
 474
 475 2010-04-06  Peter Bergner  <bergner@vnet.ibm.com>
 476
 477         * ppc-opc.c (RBOPT): New define.
 478         ("dccci"): Enable for PPCA2.  Make operands optional.
 479         ("iccci"): Likewise.  Do not deprecate for PPC476.
 480
 481 2010-04-02  Masaki Muranaka  <monaka@monami-software.com>
 482
 483         * cr16-opc.c (cr16_instruction): Fix typo in comment.
 484
 485 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 486
 487         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
 488         * Makefile.in: Regenerate.
 489         * configure.in (bfd_tic6x_arch): New.
 490         * configure: Regenerate.
 491         * disassemble.c (ARCH_tic6x): Define if ARCH_all.
 492         (disassembler): Handle TI C6X.
 493         * tic6x-dis.c: New.
 494
 495 2010-03-24  Mike Frysinger  <vapier@gentoo.org>
 496
 497         * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
 498
 499 2010-03-23  Joseph Myers  <joseph@codesourcery.com>
 500
 501         * dis-buf.c (buffer_read_memory): Give error for reading just
 502         before the start of memory.
 503
 504 2010-03-22  Sebastian Pop  <sebastian.pop@amd.com>
 505             Quentin Neill <quentin.neill@amd.com>
 506
 507         * i386-dis.c (OP_LWP_I): Removed.
 508         (reg_table): Do not use OP_LWP_I, use Iq.
 509         (OP_LWPCB_E): Remove use of names16.
 510         (OP_LWP_E): Same.
 511         * i386-opc.tbl: Removed 16bit LWP insns.  32bit LWP insns
 512         should not set the Vex.length bit.
 513         * i386-tbl.h: Regenerated.
 514
 515 2010-02-25  Edmar Wienskoski  <edmar@freescale.com>
 516
 517         * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
 518
 519 2010-02-24  Nick Clifton  <nickc@redhat.com>
 520
 521         PR binutils/6773
 522         * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
 523         <prefix>asx.  Replace <prefix>subaddx with <prefix>sax.
 524         (thumb32_opcodes): Likewise.
 525
 526 2010-02-15  Nick Clifton  <nickc@redhat.com>
 527
 528         * po/vi.po: Updated Vietnamese translation.
 529
 530 2010-02-12  Doug Evans  <dje@sebabeach.org>
 531
 532         * lm32-opinst.c: Regenerate.
 533
 534 2010-02-11  Doug Evans  <dje@sebabeach.org>
 535
 536         * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
 537         (print_address): Delete CGEN_PRINT_ADDRESS.
 538         * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
 539         * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
 540         * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
 541         * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
 542
 543         * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
 544         * frv-desc.c, * frv-desc.h, * frv-opc.c,
 545         * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
 546         * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
 547         * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
 548         * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
 549         * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
 550         * mep-desc.c, * mep-desc.h, * mep-opc.c,
 551         * mt-desc.c, * mt-desc.h, * mt-opc.c,
 552         * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
 553         * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
 554         * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
 555
 556 2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 557
 558         * i386-dis.c: Update copyright.
 559         * i386-gen.c: Likewise.
 560         * i386-opc.h: Likewise.
 561         * i386-opc.tbl: Likewise.
 562
 563 2010-02-10  Quentin Neill  <quentin.neill@amd.com>
 564             Sebastian Pop  <sebastian.pop@amd.com>
 565
 566         * i386-dis.c (OP_EX_VexImmW): Reintroduced
 567         function to handle 5th imm8 operand.
 568         (PREFIX_VEX_3A48): Added.
 569         (PREFIX_VEX_3A49): Added.
 570         (VEX_W_3A48_P_2): Added.
 571         (VEX_W_3A49_P_2): Added.
 572         (prefix table): Added entries for PREFIX_VEX_3A48
 573         and PREFIX_VEX_3A49.
 574         (vex table): Added entries for VEX_W_3A48_P_2 and
 575         and VEX_W_3A49_P_2.
 576         * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
 577         for Vec_Imm4 operands.
 578         * i386-opc.h (enum): Added Vec_Imm4.
 579         (i386_operand_type): Added vec_imm4.
 580         * i386-opc.tbl: Add entries for vpermilp[ds].
 581         * i386-init.h: Regenerated.
 582         * i386-tbl.h: Regenerated.
 583
 584 2010-02-10  Richard Sandiford  <r.sandiford@uk.ibm.com>
 585
 586         * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
 587         and "pwr7".  Move "a2" into alphabetical order.
 588
 589 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 590
 591         * ppc-dis.c (ppc_opts): Add titan entry.
 592         * ppc-opc.c (TITAN, MULHW): Define.
 593         (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
 594
 595 2010-02-03  Quentin Neill  <quentin.neill@amd.com>
 596
 597         * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
 598         to CPU_BDVER1_FLAGS
 599         * i386-init.h: Regenerated.
 600
 601 2010-02-03  Anthony Green  <green@moxielogic.com>
 602
 603         * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
 604         0x0f, and make 0x00 an illegal instruction.
 605
 606 2010-01-29  Daniel Jacobowitz  <dan@codesourcery.com>
 607
 608         * opcodes/arm-dis.c (struct arm_private_data): New.
 609         (print_insn_coprocessor, print_insn_arm): Update to use struct
 610         arm_private_data.
 611         (is_mapping_symbol, get_map_sym_type): New functions.
 612         (get_sym_code_type): Check the symbol's section.  Do not check
 613         mapping symbols.
 614         (print_insn): Default to disassembling ARM mode code.  Check
 615         for mapping symbols separately from other symbols.  Use
 616         struct arm_private_data.
 617
 618 2010-01-28  H.J. Lu  <hongjiu.lu@intel.com>
 619
 620         * i386-dis.c (EXVexWdqScalar): New.
 621         (vex_scalar_w_dq_mode): Likewise.
 622         (prefix_table): Update entries for PREFIX_VEX_3899,
 623         PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
 624         PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
 625         PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
 626         PREFIX_VEX_38BD and PREFIX_VEX_38BF.
 627         (intel_operand_size): Handle vex_scalar_w_dq_mode.
 628         (OP_EX): Likewise.
 629
 630 2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 631
 632         * i386-dis.c (XMScalar): New.
 633         (EXdScalar): Likewise.
 634         (EXqScalar): Likewise.
 635         (EXqScalarS): Likewise.
 636         (VexScalar): Likewise.
 637         (EXdVexScalarS): Likewise.
 638         (EXqVexScalarS): Likewise.
 639         (XMVexScalar): Likewise.
 640         (scalar_mode): Likewise.
 641         (d_scalar_mode): Likewise.
 642         (d_scalar_swap_mode): Likewise.
 643         (q_scalar_mode): Likewise.
 644         (q_scalar_swap_mode): Likewise.
 645         (vex_scalar_mode): Likewise.
 646         (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
 647         VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
 648         VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
 649         VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
 650         VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
 651         VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
 652         VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
 653         VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
 654         VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
 655         VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
 656         (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
 657         VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
 658         VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
 659         VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
 660         VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
 661         VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
 662         VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
 663         VEX_W_7E_P_1, VEX_W_D6_P_2  VEX_W_C2_P_1, VEX_W_C2_P_3,
 664         VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
 665         (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
 666         q_scalar_mode, q_scalar_swap_mode.
 667         (OP_XMM): Handle scalar_mode.
 668         (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
 669         and q_scalar_swap_mode.
 670         (OP_VEX): Handle vex_scalar_mode.
 671
 672 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 673
 674         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 675
 676 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 677
 678         * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
 679
 680 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 681
 682         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 683
 684 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 685
 686         * i386-dis.c (Bad_Opcode): New.
 687         (bad_opcode): Likewise.
 688         (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
 689         (dis386_twobyte): Likewise.
 690         (reg_table): Likewise.
 691         (prefix_table): Likewise.
 692         (x86_64_table): Likewise.
 693         (vex_len_table): Likewise.
 694         (vex_w_table): Likewise.
 695         (mod_table): Likewise.
 696         (rm_table): Likewise.
 697         (float_reg): Likewise.
 698         (reg_table): Remove trailing "(bad)" entries.
 699         (prefix_table): Likewise.
 700         (x86_64_table): Likewise.
 701         (vex_len_table): Likewise.
 702         (vex_w_table): Likewise.
 703         (mod_table): Likewise.
 704         (rm_table): Likewise.
 705         (get_valid_dis386): Handle bytemode 0.
 706
 707 2010-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 708
 709         * i386-opc.h (VEXScalar): New.
 710
 711         * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
 712         instructions.
 713         * i386-tbl.h: Regenerated.
 714
 715 2010-01-21  H.J. Lu  <hongjiu.lu@intel.com>
 716
 717         * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
 718
 719         * i386-opc.tbl: Add xsave64 and xrstor64.
 720         * i386-tbl.h: Regenerated.
 721
 722 2010-01-20  Nick Clifton  <nickc@redhat.com>
 723
 724         PR 11170
 725         * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
 726         based post-indexed addressing.
 727
 728 2010-01-15  Sebastian Pop  <sebastian.pop@amd.com>
 729
 730         * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
 731         * i386-tbl.h: Regenerated.
 732
 733 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 734
 735         * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
 736         comments.
 737
 738 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 739
 740         * i386-dis.c (names_mm): New.
 741         (intel_names_mm): Likewise.
 742         (att_names_mm): Likewise.
 743         (names_xmm): Likewise.
 744         (intel_names_xmm): Likewise.
 745         (att_names_xmm): Likewise.
 746         (names_ymm): Likewise.
 747         (intel_names_ymm): Likewise.
 748         (att_names_ymm): Likewise.
 749         (print_insn): Set names_mm, names_xmm and names_ymm.
 750         (OP_MMX): Use names_mm, names_xmm and names_ymm.
 751         (OP_XMM): Likewise.
 752         (OP_EM): Likewise.
 753         (OP_EMC): Likewise.
 754         (OP_MXC): Likewise.
 755         (OP_EX): Likewise.
 756         (XMM_Fixup): Likewise.
 757         (OP_VEX): Likewise.
 758         (OP_EX_VexReg): Likewise.
 759         (OP_Vex_2src): Likewise.
 760         (OP_Vex_2src_1): Likewise.
 761         (OP_Vex_2src_2): Likewise.
 762         (OP_REG_VexI4): Likewise.
 763
 764 2010-01-13  H.J. Lu  <hongjiu.lu@intel.com>
 765
 766         * i386-dis.c (print_insn): Update comments.
 767
 768 2010-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 769
 770         * i386-dis.c (rex_original): Removed.
 771         (ckprefix): Remove rex_original.
 772         (print_insn): Update comments.
 773
 774 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 775
 776         * Makefile.in: Regenerate.
 777         * configure: Regenerate.
 778
 779 2010-01-07  Doug Evans  <dje@sebabeach.org>
 780
 781         * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
 782         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 783         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 784         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 785         * xstormy16-ibld.c: Regenerate.
 786
 787 2010-01-06  Quentin Neill  <quentin.neill@amd.com>
 788
 789         * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
 790         * i386-init.h: Regenerated.
 791
 792 2010-01-06  Daniel Gutson  <dgutson@codesourcery.com>
 793
 794         * arm-dis.c (print_insn): Fixed search for next symbol and data
 795         dumping condition, and the initial mapping symbol state.
 796
 797 2010-01-05  Doug Evans  <dje@sebabeach.org>
 798
 799         * cgen-ibld.in: #include "cgen/basic-modes.h".
 800         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 801         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 802         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 803         * xstormy16-ibld.c: Regenerate.
 804
 805 2010-01-04  Nick Clifton  <nickc@redhat.com>
 806
 807         PR 11123
 808         * arm-dis.c (print_insn_coprocessor): Initialise value.
 809
 810 2010-01-04  Edmar Wienskoski  <edmar@freescale.com>
 811
 812         * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
 813
 814 2010-01-02  Doug Evans  <dje@sebabeach.org>
 815
 816         * cgen-asm.in: Update copyright year.
 817         * cgen-dis.in: Update copyright year.
 818         * cgen-ibld.in: Update copyright year.
 819         * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
 820         * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
 821         * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
 822         * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
 823         * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
 824         * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
 825         * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
 826         * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
 827         * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
 828         * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
 829         * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
 830         * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
 831         * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
 832         * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
 833         * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
 834         * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
 835         * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
 836         * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
 837         * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
 838         * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
 839         * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
 840
 841 For older changes see ChangeLog-2009
 842 \f
 843 Local Variables:
 844 mode: change-log
 845 left-margin: 8
 846 fill-column: 74
 847 version-control: never
 848 End: