opcodes/ChangeLog

   1 2011-06-03  Quentin Neill  <quentin.neill@amd.com>
   2
   3         * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
   4         * i386-init.h: Regenerated.
   5
   6 2011-06-03  Nick Clifton  <nickc@redhat.com>
   7
   8         PR binutils/12752
   9         * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
  10         computing address offsets.
  11         (print_arm_address): Likewise.
  12         (print_insn_arm): Likewise.
  13         (print_insn_thumb16): Likewise.
  14         (print_insn_thumb32): Likewise.
  15
  16 2011-06-02  Jie Zhang <jie@codesourcery.com>
  17             Nathan Sidwell <nathan@codesourcery.com>
  18             Maciej Rozycki <macro@codesourcery.com>
  19
  20         * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
  21         as address offset.
  22         (print_arm_address): Likewise. Elide positive #0 appropriately.
  23         (print_insn_arm): Likewise.
  24
  25 2011-06-02  Nick Clifton  <nickc@redhat.com>
  26
  27         PR gas/12752
  28         * arm-dis.c (print_insn_thumb32): Do not sign extend  addresses
  29         passed to print_address_func.
  30
  31 2011-06-02  Nick Clifton  <nickc@redhat.com>
  32
  33         * arm-dis.c: Fix spelling mistakes.
  34         * op/opcodes.pot: Regenerate.
  35
  36 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  37
  38         * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
  39         S390_OPERAND_REG_PAIR.  Fix INSTR_RRF_0UFEF instruction type.
  40         * s390-opc.txt: Fix cxr instruction type.
  41
  42 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  43
  44         * s390-opc.c: Add new instruction types marking register pair
  45         operands.
  46         * s390-opc.txt: Match instructions having register pair operands
  47         to the new instruction types.
  48
  49 2011-05-19  Nick Clifton  <nickc@redhat.com>
  50
  51         * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
  52         operands.
  53
  54 2011-05-10  Quentin Neill  <quentin.neill@amd.com>
  55
  56         * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
  57         * i386-init.h: Regenerated.
  58
  59 2011-04-27  Nick Clifton  <nickc@redhat.com>
  60
  61         * po/da.po: Updated Danish translation.
  62
  63 2011-04-26  Anton Blanchard  <anton@samba.org>
  64
  65         * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
  66
  67 2011-04-21  DJ Delorie  <dj@redhat.com>
  68
  69         * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
  70         * rx-decode.c: Regenerate.
  71
  72 2011-04-20  H.J. Lu  <hongjiu.lu@intel.com>
  73
  74         * i386-init.h: Regenerated.
  75
  76 2011-04-19  Quentin Neill  <quentin.neill@amd.com>
  77
  78         * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
  79         from bdver1 flags.
  80
  81 2011-04-13  Nick Clifton  <nickc@redhat.com>
  82
  83         * v850-dis.c (disassemble): Always print a closing square brace if
  84         an opening square brace was printed.
  85
  86 2011-04-12  Nick Clifton  <nickc@redhat.com>
  87
  88         PR binutils/12534
  89         * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
  90         patterns.
  91         (print_insn_thumb32): Handle %L.
  92
  93 2011-04-11  Julian Brown  <julian@codesourcery.com>
  94
  95         * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
  96         (print_insn_thumb32): Add APSR bitmask support.
  97
  98 2011-04-07  Paul Carroll<pcarroll@codesourcery.com>
  99
 100         * arm-dis.c (print_insn): init vars moved into private_data structure.
 101
 102 2011-03-24  Mike Frysinger  <vapier@gentoo.org>
 103
 104         * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
 105
 106 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 107
 108         * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
 109         post-increment to support LPM Z+ instruction. Add support for 'E'
 110         constraint for DES instruction.
 111         (print_insn_avr): Adjust calls to avr_operand. Rename variable.
 112
 113 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 114
 115         * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
 116
 117 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 118
 119         * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
 120         Use branch types instead.
 121         (print_insn): Likewise.
 122
 123 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 124
 125         * mips-opc.c (mips_builtin_opcodes): Correct register use
 126         annotation of "alnv.ps".
 127
 128 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 129
 130         * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
 131
 132 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 133
 134         * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
 135
 136 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 137
 138         * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
 139
 140 2011-02-19  Mike Frysinger  <vapier@gentoo.org>
 141
 142         * bfin-dis.c (saved_state): Mark static.  Change a[01]x to ax[] and
 143         a[01]w to aw[].  Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
 144         av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
 145         exception, end_of_registers, msize, memory, bfd_mach.
 146         (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
 147         LB0REG, LC1REG, LT1REG, LB1REG): Delete
 148         (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
 149         (get_allreg): Change to new defines.  Fallback to abort().
 150
 151 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 152
 153         * bfin-dis.c: Add whitespace/parenthesis where needed.
 154
 155 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 156
 157         * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
 158         than 7.
 159
 160 2011-02-13  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 161
 162         * configure: Regenerate.
 163
 164 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 165
 166         * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
 167
 168 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 169
 170         * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1.  Output
 171         dregs only when P is set, and dregs_lo otherwise.
 172
 173 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 174
 175         * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
 176
 177 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 178
 179         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
 180
 181 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 182
 183         * bfin-dis.c (machine_registers): Delete REG_GP.
 184         (reg_names): Delete "GP".
 185         (decode_allregs): Change REG_GP to REG_LASTREG.
 186
 187 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 188
 189         * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
 190         M_IH, M_IU): Delete.
 191
 192 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 193
 194         * bfin-dis.c (reg_names): Add const.
 195         (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
 196         decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
 197         decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
 198         decode_counters, decode_allregs): Likewise.
 199
 200 2011-02-09  Michael Snyder  <msnyder@vmware.com>
 201
 202         * i386-dis.c (OP_J): Parenthesize expression to prevent
 203         truncated addresses.
 204         (print_insn): Fix indentation off-by-one.
 205
 206 2011-02-01  Nick Clifton  <nickc@redhat.com>
 207
 208         * po/da.po: Updated Danish translation.
 209
 210 2011-01-21  Dave Murphy  <davem@devkitpro.org>
 211
 212         * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
 213
 214 2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>
 215
 216         * i386-dis.c (sIbT): New.
 217         (b_T_mode): Likewise.
 218         (dis386): Replace sIb with sIbT on "pushT".
 219         (x86_64_table): Replace sIb with Ib on "aam" and "aad".
 220         (OP_sI): Handle b_T_mode.  Properly sign-extend byte.
 221
 222 2011-01-18  Jan Kratochvil  <jan.kratochvil@redhat.com>
 223
 224         * i386-init.h: Regenerated.
 225         * i386-tbl.h: Regenerated
 226
 227 2011-01-17  Quentin Neill  <quentin.neill@amd.com>
 228
 229         * i386-dis.c (REG_XOP_TBM_01): New.
 230         (REG_XOP_TBM_02): New.
 231         (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
 232         (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
 233         entries, and add bextr instruction.
 234
 235         * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
 236         (cpu_flags): Add CpuTBM.
 237
 238         * i386-opc.h (CpuTBM) New.
 239         (i386_cpu_flags): Add bit cputbm.
 240
 241         * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
 242         blcs, blsfill, blsic, t1mskc, and tzmsk.
 243
 244 2011-01-12  DJ Delorie  <dj@redhat.com>
 245
 246         * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
 247
 248 2011-01-11  Mingjie Xing  <mingjie.xing@gmail.com>
 249
 250         * mips-dis.c (print_insn_args): Adjust the value to print the real
 251         offset for "+c" argument.
 252
 253 2011-01-10  Nick Clifton  <nickc@redhat.com>
 254
 255         * po/da.po: Updated Danish translation.
 256
 257 2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>
 258
 259         * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
 260
 261 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 262
 263         * i386-dis.c (REG_VEX_38F3): New.
 264         (PREFIX_0FBC): Likewise.
 265         (PREFIX_VEX_38F2): Likewise.
 266         (PREFIX_VEX_38F3_REG_1): Likewise.
 267         (PREFIX_VEX_38F3_REG_2): Likewise.
 268         (PREFIX_VEX_38F3_REG_3): Likewise.
 269         (PREFIX_VEX_38F7): Likewise.
 270         (VEX_LEN_38F2_P_0): Likewise.
 271         (VEX_LEN_38F3_R_1_P_0): Likewise.
 272         (VEX_LEN_38F3_R_2_P_0): Likewise.
 273         (VEX_LEN_38F3_R_3_P_0): Likewise.
 274         (VEX_LEN_38F7_P_0): Likewise.
 275         (dis386_twobyte): Use PREFIX_0FBC.
 276         (reg_table): Add REG_VEX_38F3.
 277         (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
 278         PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
 279         PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
 280         (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
 281         PREFIX_VEX_38F7.
 282         (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
 283         VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
 284         VEX_LEN_38F7_P_0.
 285
 286         * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
 287         (cpu_flags): Add CpuBMI.
 288
 289         * i386-opc.h (CpuBMI): New.
 290         (i386_cpu_flags): Add cpubmi.
 291
 292         * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
 293         * i386-init.h: Regenerated.
 294         * i386-tbl.h: Likewise.
 295
 296 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 297
 298         * i386-dis.c (VexGdq): New.
 299         (OP_VEX): Handle dq_mode.
 300
 301 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 302
 303         * i386-gen.c (process_copyright): Update copyright to 2011.
 304
 305 For older changes see ChangeLog-2010
 306 \f
 307 Local Variables:
 308 mode: change-log
 309 left-margin: 8
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 311 version-control: never
 312 End: