opcodes/ChangeLog

   1 2019-10-28  Nick Clifton  <nickc@redhat.com>
   2
   3         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
   4         operand.
   5
   6 2019-10-25  Nick Clifton  <nickc@redhat.com>
   7
   8         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
   9         access to opcodes.op array element.
  10
  11 2019-10-23  Nick Clifton  <nickc@redhat.com>
  12
  13         * rx-dis.c (get_register_name): Fix spelling typo in error
  14         message.
  15         (get_condition_name, get_flag_name, get_double_register_name)
  16         (get_double_register_high_name, get_double_register_low_name)
  17         (get_double_control_register_name, get_double_condition_name)
  18         (get_opsize_name, get_size_name): Likewise.
  19
  20 2019-10-22  Nick Clifton  <nickc@redhat.com>
  21
  22         * rx-dis.c (get_size_name): New function.  Provides safe
  23         access to name array.
  24         (get_opsize_name): Likewise.
  25         (print_insn_rx): Use the accessor functions.
  26
  27 2019-10-16  Nick Clifton  <nickc@redhat.com>
  28
  29         * rx-dis.c (get_register_name): New function.  Provides safe
  30         access to name array.
  31         (get_condition_name, get_flag_name, get_double_register_name)
  32         (get_double_register_high_name, get_double_register_low_name)
  33         (get_double_control_register_name, get_double_condition_name):
  34         Likewise.
  35         (print_insn_rx): Use the accessor functions.
  36
  37 2019-10-09  Nick Clifton  <nickc@redhat.com>
  38
  39         PR 25041
  40         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
  41         instructions.
  42
  43 2019-10-07  Jan Beulich  <jbeulich@suse.com>
  44
  45         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
  46         (cmpsd): Likewise. Move EsSeg to other operand.
  47         * opcodes/i386-tbl.h: Re-generate.
  48
  49 2019-09-23  Alan Modra  <amodra@gmail.com>
  50
  51         * m68k-dis.c: Include cpu-m68k.h
  52
  53 2019-09-23  Alan Modra  <amodra@gmail.com>
  54
  55         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
  56         "elf/mips.h" earlier.
  57
  58 2018-09-20  Jan Beulich  <jbeulich@suse.com>
  59
  60         PR gas/25012
  61         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
  62         with SReg operand.
  63         * i386-tbl.h: Re-generate.
  64
  65 2019-09-18  Alan Modra  <amodra@gmail.com>
  66
  67         * arc-ext.c: Update throughout for bfd section macro changes.
  68
  69 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
  70
  71         * Makefile.in: Re-generate.
  72         * configure: Re-generate.
  73
  74 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
  75
  76         * riscv-opc.c (riscv_opcodes): Change subset field
  77         to insn_class field for all instructions.
  78         (riscv_insn_types): Likewise.
  79
  80 2019-09-16  Phil Blundell  <pb@pbcl.net>
  81
  82         * configure: Regenerated.
  83
  84 2019-09-10  Miod Vallat  <miod@online.fr>
  85
  86         PR 24982
  87         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
  88
  89 2019-09-09  Phil Blundell  <pb@pbcl.net>
  90
  91         binutils 2.33 branch created.
  92
  93 2019-09-03  Nick Clifton  <nickc@redhat.com>
  94
  95         PR 24961
  96         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
  97         greater than zero before indexing via (bufcnt -1).
  98
  99 2019-09-03  Nick Clifton  <nickc@redhat.com>
 100
 101         PR 24958
 102         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 103         (MAX_SPEC_REG_NAME_LEN): Define.
 104         (struct mmix_dis_info): Use defined constants for array lengths.
 105         (get_reg_name): New function.
 106         (get_sprec_reg_name): New function.
 107         (print_insn_mmix): Use new functions.
 108
 109 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 110
 111         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 112         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 113         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 114
 115 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 116
 117         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 118         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 119         (aarch64_sys_reg_supported_p): Update checks for the above.
 120
 121 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 122
 123         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 124         cases MVE_SQRSHRL and MVE_UQRSHLL.
 125         (print_insn_mve): Add case for specifier 'k' to check
 126         specific bit of the instruction.
 127
 128 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 129
 130         PR 24854
 131         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 132         encountering an unknown machine type.
 133         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 134         cases return -1 rather than calling abort.
 135
 136 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 137
 138         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 139         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 140         IgnoreSize.
 141         * i386-tbl.h: Re-generate.
 142
 143 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 144
 145         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 146         instructions.
 147
 148 2019-07-30  Mel Chen <mel.chen@sifive.com>
 149
 150         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 151         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 152
 153         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 154         fscsr.
 155
 156 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 157
 158         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 159         and MPY class instructions.
 160         (parse_option): Add nps400 option.
 161         (print_arc_disassembler_options): Add nps400 info.
 162
 163 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 164
 165         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 166         (bspop): Likewise.
 167         (modapp): Likewise.
 168         * arc-opc.c (RAD_CHK): Add.
 169         * arc-tbl.h: Regenerate.
 170
 171 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 172
 173         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 174         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 175
 176 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 177
 178         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 179         instructions as UNPREDICTABLE.
 180
 181 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 182
 183         * bpf-desc.c: Regenerated.
 184
 185 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 186
 187         * i386-gen.c (static_assert): Define.
 188         (main): Use it.
 189         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 190         (Opcode_Modifier_Num): ... this.
 191         (Mem): Delete.
 192
 193 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 194
 195         * i386-gen.c (operand_types): Move RegMem ...
 196         (opcode_modifiers): ... here.
 197         * i386-opc.h (RegMem): Move to opcode modifer enum.
 198         (union i386_operand_type): Move regmem field ...
 199         (struct i386_opcode_modifier): ... here.
 200         * i386-opc.tbl (RegMem): Define.
 201         (mov, movq): Move RegMem on segment, control, debug, and test
 202         register flavors.
 203         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 204         to non-SSE2AVX flavor.
 205         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 206         Move RegMem on register only flavors. Drop IgnoreSize from
 207         legacy encoding flavors.
 208         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 209         flavors.
 210         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 211         register only flavors.
 212         (vmovd): Move RegMem and drop IgnoreSize on register only
 213         flavor. Change opcode and operand order to store form.
 214         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 215
 216 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 217
 218         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 219         entries.
 220         * i386-opc.h (SReg2, SReg3): Replace by ...
 221         (SReg): ... this.
 222         (union i386_operand_type): Replace sreg fields.
 223         * i386-opc.tbl (mov, ): Use SReg.
 224         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 225         register flavors.
 226         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 227         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 228
 229 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 230
 231         * bpf-desc.c: Regenerate.
 232         * bpf-opc.c: Likewise.
 233         * bpf-opc.h: Likewise.
 234
 235 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 236
 237         * bpf-desc.c: Regenerate.
 238         * bpf-opc.c: Likewise.
 239
 240 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 241
 242         * arm-dis.c (print_insn_coprocessor): Rename index to
 243         index_operand.
 244
 245 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 246
 247         * riscv-opc.c (riscv_insn_types): Add r4 type.
 248
 249         * riscv-opc.c (riscv_insn_types): Add b and j type.
 250
 251         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 252         format for sb type and correct s type.
 253
 254 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 255
 256         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 257         SVE FMOV alias of FCPY.
 258
 259 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 260
 261         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 262         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 263
 264 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 265
 266         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 267         registers in an instruction prefixed by MOVPRFX.
 268
 269 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 270
 271         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 272         sve_size_13 icode to account for variant behaviour of
 273         pmull{t,b}.
 274         * aarch64-dis-2.c: Regenerate.
 275         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 276         sve_size_13 icode to account for variant behaviour of
 277         pmull{t,b}.
 278         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 279         (OP_SVE_VVV_Q_D): Add new qualifier.
 280         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 281         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 282         AES and those not.
 283
 284 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 285
 286         * opcodes/i386-gen.c (operand_type_init): Remove
 287         OPERAND_TYPE_VEC_IMM4 entry.
 288         (operand_types): Remove Vec_Imm4.
 289         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 290         (union i386_operand_type): Remove vec_imm4.
 291         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 292         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 293
 294 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 295
 296         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 297         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 298         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 299         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 300         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 301         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 302         * i386-tbl.h: Re-generate.
 303
 304 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 305
 306         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 307         register operands.
 308         * i386-tbl.h: Re-generate.
 309
 310 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 311
 312         * i386-opc.tbl (C): New.
 313         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 314         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 315         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 316         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 317         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 318         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 319         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 320         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 321         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 322         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 323         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 324         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 325         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 326         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 327         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 328         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 329         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 330         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 331         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 332         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 333         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 334         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 335         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 336         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 337         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 338         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 339         flavors.
 340         * i386-tbl.h: Re-generate.
 341
 342 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 343
 344         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 345         register operands.
 346         * i386-tbl.h: Re-generate.
 347
 348 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 349
 350         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 351         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 352         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 353         * i386-tbl.h: Re-generate.
 354
 355 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 356
 357         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 358         Disp8MemShift from register only templates.
 359         * i386-tbl.h: Re-generate.
 360
 361 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 362
 363         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 364         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 365         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 366         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 367         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 368         EVEX_W_0F11_P_3_M_1): Delete.
 369         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 370         EVEX_W_0F11_P_3): New.
 371         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 372         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 373         MOD_EVEX_0F11_PREFIX_3 table entries.
 374         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 375         PREFIX_EVEX_0F11 table entries.
 376         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 377         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 378         EVEX_W_0F11_P_3_M_{0,1} table entries.
 379
 380 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 381
 382         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 383         Delete.
 384
 385 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 386
 387         PR binutils/24719
 388         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 389         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 390         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 391         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 392         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 393         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 394         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 395         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 396         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 397         PREFIX_EVEX_0F38C6_REG_6 entries.
 398         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 399         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 400         EVEX_W_0F38C7_R_6_P_2 entries.
 401         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 402         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 403         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 404         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 405         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 406         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 407         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 408
 409 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 410
 411         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 412         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 413         VEX_LEN_0F2D_P_3): Delete.
 414         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 415         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 416         (prefix_table): ... here.
 417
 418 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 419
 420         * i386-dis.c (Iq): Delete.
 421         (Id): New.
 422         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 423         TBM insns.
 424         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 425         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 426         (OP_E_memory): Also honor needindex when deciding whether an
 427         address size prefix needs printing.
 428         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 429
 430 2019-06-26  Jim Wilson  <jimw@sifive.com>
 431
 432         PR binutils/24739
 433         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 434         Set info->display_endian to info->endian_code.
 435
 436 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 437
 438         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 439         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 440         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 441         OPERAND_TYPE_ACC64 entries.
 442         * i386-init.h: Re-generate.
 443
 444 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 445
 446         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 447         Delete.
 448         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 449         of dqa_mode.
 450         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 451         entries here.
 452         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 453         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 454
 455 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 456
 457         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 458         variables.
 459
 460 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 461
 462         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 463         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 464         movnti.
 465         * i386-opc.tbl (movnti): Add IgnoreSize.
 466         * i386-tbl.h: Re-generate.
 467
 468 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 469
 470         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 471         * i386-tbl.h: Re-generate.
 472
 473 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 474
 475         * i386-dis-evex.h: Break into ...
 476         * i386-dis-evex-len.h: New file.
 477         * i386-dis-evex-mod.h: Likewise.
 478         * i386-dis-evex-prefix.h: Likewise.
 479         * i386-dis-evex-reg.h: Likewise.
 480         * i386-dis-evex-w.h: Likewise.
 481         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 482         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 483         i386-dis-evex-mod.h.
 484
 485 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 486
 487         PR binutils/24700
 488         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 489         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 490         EVEX_W_0F385B_P_2.
 491         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 492         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 493         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 494         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 495         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 496         EVEX_LEN_0F385B_P_2_W_1.
 497         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 498         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 499         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 500         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 501         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 502         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 503         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 504         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 505         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 506         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 507
 508 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 509
 510         PR binutils/24691
 511         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 512         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 513         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 514         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 515         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 516         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 517         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 518         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 519         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 520         EVEX_LEN_0F3A43_P_2_W_1.
 521         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 522         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 523         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 524         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 525         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 526         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 527         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 528         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 529         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 530         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 531         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 532         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 533
 534 2019-06-14  Nick Clifton  <nickc@redhat.com>
 535
 536         * po/fr.po; Updated French translation.
 537
 538 2019-06-13  Stafford Horne  <shorne@gmail.com>
 539
 540         * or1k-asm.c: Regenerated.
 541         * or1k-desc.c: Regenerated.
 542         * or1k-desc.h: Regenerated.
 543         * or1k-dis.c: Regenerated.
 544         * or1k-ibld.c: Regenerated.
 545         * or1k-opc.c: Regenerated.
 546         * or1k-opc.h: Regenerated.
 547         * or1k-opinst.c: Regenerated.
 548
 549 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 550
 551         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 552
 553 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 554
 555         PR binutils/24633
 556         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 557         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 558         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 559         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 560         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 561         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 562         EVEX_LEN_0F3A1B_P_2_W_1.
 563         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 564         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 565         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 566         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 567         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 568         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 569         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 570         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 571
 572 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 573
 574         PR binutils/24626
 575         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 576         EVEX.vvvv when disassembling VEX and EVEX instructions.
 577         (OP_VEX): Set vex.register_specifier to 0 after readding
 578         vex.register_specifier.
 579         (OP_Vex_2src_1): Likewise.
 580         (OP_Vex_2src_2): Likewise.
 581         (OP_LWP_E): Likewise.
 582         (OP_EX_Vex): Don't check vex.register_specifier.
 583         (OP_XMM_Vex): Likewise.
 584
 585 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 586             Lili Cui  <lili.cui@intel.com>
 587
 588         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 589         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 590         instructions.
 591         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 592         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 593         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 594         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 595         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 596         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 597         * i386-init.h: Regenerated.
 598         * i386-tbl.h: Likewise.
 599
 600 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 601             Lili Cui  <lili.cui@intel.com>
 602
 603         * doc/c-i386.texi: Document enqcmd.
 604         * testsuite/gas/i386/enqcmd-intel.d: New file.
 605         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 606         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 607         * testsuite/gas/i386/enqcmd.d: Likewise.
 608         * testsuite/gas/i386/enqcmd.s: Likewise.
 609         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 610         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 611         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 612         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 613         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 614         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 615         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 616         and x86-64-enqcmd.
 617
 618 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 619
 620         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 621
 622 2019-06-03  Alan Modra  <amodra@gmail.com>
 623
 624         * ppc-dis.c (prefix_opcd_indices): Correct size.
 625
 626 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 627
 628         PR gas/24625
 629         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 630         Disp8ShiftVL.
 631         * i386-tbl.h: Regenerated.
 632
 633 2019-05-24  Alan Modra  <amodra@gmail.com>
 634
 635         * po/POTFILES.in: Regenerate.
 636
 637 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 638             Alan Modra  <amodra@gmail.com>
 639
 640         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 641         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 642         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 643         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 644         XTOP>): Define and add entries.
 645         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 646         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 647         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 648         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 649
 650 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 651             Alan Modra  <amodra@gmail.com>
 652
 653         * ppc-dis.c (ppc_opts): Add "future" entry.
 654         (PREFIX_OPCD_SEGS): Define.
 655         (prefix_opcd_indices): New array.
 656         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 657         (lookup_prefix): New function.
 658         (print_insn_powerpc): Handle 64-bit prefix instructions.
 659         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 660         (PMRR, POWERXX): Define.
 661         (prefix_opcodes): New instruction table.
 662         (prefix_num_opcodes): New constant.
 663
 664 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 665
 666         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 667         * configure: Regenerated.
 668         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 669         and cpu/bpf.opc.
 670         (HFILES): Add bpf-desc.h and bpf-opc.h.
 671         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 672         bpf-ibld.c and bpf-opc.c.
 673         (BPF_DEPS): Define.
 674         * Makefile.in: Regenerated.
 675         * disassemble.c (ARCH_bpf): Define.
 676         (disassembler): Add case for bfd_arch_bpf.
 677         (disassemble_init_for_target): Likewise.
 678         (enum epbf_isa_attr): Define.
 679         * disassemble.h: extern print_insn_bpf.
 680         * bpf-asm.c: Generated.
 681         * bpf-opc.h: Likewise.
 682         * bpf-opc.c: Likewise.
 683         * bpf-ibld.c: Likewise.
 684         * bpf-dis.c: Likewise.
 685         * bpf-desc.h: Likewise.
 686         * bpf-desc.c: Likewise.
 687
 688 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 689
 690         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 691         and VMSR with the new operands.
 692
 693 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 694
 695         * arm-dis.c (enum mve_instructions): New enum
 696         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 697         and cneg.
 698         (mve_opcodes): New instructions as above.
 699         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 700         csneg and csel.
 701         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 702
 703 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 704
 705         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 706         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 707         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 708         uqshl, urshrl and urshr.
 709         (is_mve_okay_in_it): Add new instructions to TRUE list.
 710         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 711         (print_insn_mve): Updated to accept new %j,
 712         %<bitfield>m and %<bitfield>n patterns.
 713
 714 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 715
 716         * mips-opc.c (mips_builtin_opcodes): Change source register
 717         constraint for DAUI.
 718
 719 2019-05-20  Nick Clifton  <nickc@redhat.com>
 720
 721         * po/fr.po: Updated French translation.
 722
 723 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 724             Michael Collison <michael.collison@arm.com>
 725
 726         * arm-dis.c (thumb32_opcodes): Add new instructions.
 727         (enum mve_instructions): Likewise.
 728         (enum mve_undefined): Add new reasons.
 729         (is_mve_encoding_conflict): Handle new instructions.
 730         (is_mve_undefined): Likewise.
 731         (is_mve_unpredictable): Likewise.
 732         (print_mve_undefined): Likewise.
 733         (print_mve_size): Likewise.
 734
 735 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 736             Michael Collison <michael.collison@arm.com>
 737
 738         * arm-dis.c (thumb32_opcodes): Add new instructions.
 739         (enum mve_instructions): Likewise.
 740         (is_mve_encoding_conflict): Handle new instructions.
 741         (is_mve_undefined): Likewise.
 742         (is_mve_unpredictable): Likewise.
 743         (print_mve_size): Likewise.
 744
 745 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 746             Michael Collison <michael.collison@arm.com>
 747
 748         * arm-dis.c (thumb32_opcodes): Add new instructions.
 749         (enum mve_instructions): Likewise.
 750         (is_mve_encoding_conflict): Likewise.
 751         (is_mve_unpredictable): Likewise.
 752         (print_mve_size): Likewise.
 753
 754 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 755             Michael Collison <michael.collison@arm.com>
 756
 757         * arm-dis.c (thumb32_opcodes): Add new instructions.
 758         (enum mve_instructions): Likewise.
 759         (is_mve_encoding_conflict): Handle new instructions.
 760         (is_mve_undefined): Likewise.
 761         (is_mve_unpredictable): Likewise.
 762         (print_mve_size): Likewise.
 763
 764 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 765             Michael Collison <michael.collison@arm.com>
 766
 767         * arm-dis.c (thumb32_opcodes): Add new instructions.
 768         (enum mve_instructions): Likewise.
 769         (is_mve_encoding_conflict): Handle new instructions.
 770         (is_mve_undefined): Likewise.
 771         (is_mve_unpredictable): Likewise.
 772         (print_mve_size): Likewise.
 773         (print_insn_mve): Likewise.
 774
 775 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 776             Michael Collison <michael.collison@arm.com>
 777
 778         * arm-dis.c (thumb32_opcodes): Add new instructions.
 779         (print_insn_thumb32): Handle new instructions.
 780
 781 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 782             Michael Collison <michael.collison@arm.com>
 783
 784         * arm-dis.c (enum mve_instructions): Add new instructions.
 785         (enum mve_undefined): Add new reasons.
 786         (is_mve_encoding_conflict): Handle new instructions.
 787         (is_mve_undefined): Likewise.
 788         (is_mve_unpredictable): Likewise.
 789         (print_mve_undefined): Likewise.
 790         (print_mve_size): Likewise.
 791         (print_mve_shift_n): Likewise.
 792         (print_insn_mve): Likewise.
 793
 794 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 795             Michael Collison <michael.collison@arm.com>
 796
 797         * arm-dis.c (enum mve_instructions): Add new instructions.
 798         (is_mve_encoding_conflict): Handle new instructions.
 799         (is_mve_unpredictable): Likewise.
 800         (print_mve_rotate): Likewise.
 801         (print_mve_size): Likewise.
 802         (print_insn_mve): Likewise.
 803
 804 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 805             Michael Collison <michael.collison@arm.com>
 806
 807         * arm-dis.c (enum mve_instructions): Add new instructions.
 808         (is_mve_encoding_conflict): Handle new instructions.
 809         (is_mve_unpredictable): Likewise.
 810         (print_mve_size): Likewise.
 811         (print_insn_mve): Likewise.
 812
 813 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 814             Michael Collison <michael.collison@arm.com>
 815
 816         * arm-dis.c (enum mve_instructions): Add new instructions.
 817         (enum mve_undefined): Add new reasons.
 818         (is_mve_encoding_conflict): Handle new instructions.
 819         (is_mve_undefined): Likewise.
 820         (is_mve_unpredictable): Likewise.
 821         (print_mve_undefined): Likewise.
 822         (print_mve_size): Likewise.
 823         (print_insn_mve): Likewise.
 824
 825 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 826             Michael Collison <michael.collison@arm.com>
 827
 828         * arm-dis.c (enum mve_instructions): Add new instructions.
 829         (is_mve_encoding_conflict): Handle new instructions.
 830         (is_mve_undefined): Likewise.
 831         (is_mve_unpredictable): Likewise.
 832         (print_mve_size): Likewise.
 833         (print_insn_mve): Likewise.
 834
 835 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 836             Michael Collison <michael.collison@arm.com>
 837
 838         * arm-dis.c (enum mve_instructions): Add new instructions.
 839         (enum mve_unpredictable): Add new reasons.
 840         (enum mve_undefined): Likewise.
 841         (is_mve_okay_in_it): Handle new isntructions.
 842         (is_mve_encoding_conflict): Likewise.
 843         (is_mve_undefined): Likewise.
 844         (is_mve_unpredictable): Likewise.
 845         (print_mve_vmov_index): Likewise.
 846         (print_simd_imm8): Likewise.
 847         (print_mve_undefined): Likewise.
 848         (print_mve_unpredictable): Likewise.
 849         (print_mve_size): Likewise.
 850         (print_insn_mve): Likewise.
 851
 852 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 853             Michael Collison <michael.collison@arm.com>
 854
 855         * arm-dis.c (enum mve_instructions): Add new instructions.
 856         (enum mve_unpredictable): Add new reasons.
 857         (enum mve_undefined): Likewise.
 858         (is_mve_encoding_conflict): Handle new instructions.
 859         (is_mve_undefined): Likewise.
 860         (is_mve_unpredictable): Likewise.
 861         (print_mve_undefined): Likewise.
 862         (print_mve_unpredictable): Likewise.
 863         (print_mve_rounding_mode): Likewise.
 864         (print_mve_vcvt_size): Likewise.
 865         (print_mve_size): Likewise.
 866         (print_insn_mve): Likewise.
 867
 868 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 869             Michael Collison <michael.collison@arm.com>
 870
 871         * arm-dis.c (enum mve_instructions): Add new instructions.
 872         (enum mve_unpredictable): Add new reasons.
 873         (enum mve_undefined): Likewise.
 874         (is_mve_undefined): Handle new instructions.
 875         (is_mve_unpredictable): Likewise.
 876         (print_mve_undefined): Likewise.
 877         (print_mve_unpredictable): Likewise.
 878         (print_mve_size): Likewise.
 879         (print_insn_mve): Likewise.
 880
 881 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 882             Michael Collison <michael.collison@arm.com>
 883
 884         * arm-dis.c (enum mve_instructions): Add new instructions.
 885         (enum mve_undefined): Add new reasons.
 886         (insns): Add new instructions.
 887         (is_mve_encoding_conflict):
 888         (print_mve_vld_str_addr): New print function.
 889         (is_mve_undefined): Handle new instructions.
 890         (is_mve_unpredictable): Likewise.
 891         (print_mve_undefined): Likewise.
 892         (print_mve_size): Likewise.
 893         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 894         (print_insn_mve):  Handle new operands.
 895
 896 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 897             Michael Collison <michael.collison@arm.com>
 898
 899         * arm-dis.c (enum mve_instructions): Add new instructions.
 900         (enum mve_unpredictable): Add new reasons.
 901         (is_mve_encoding_conflict): Handle new instructions.
 902         (is_mve_unpredictable): Likewise.
 903         (mve_opcodes): Add new instructions.
 904         (print_mve_unpredictable): Handle new reasons.
 905         (print_mve_register_blocks): New print function.
 906         (print_mve_size): Handle new instructions.
 907         (print_insn_mve): Likewise.
 908
 909 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 910             Michael Collison <michael.collison@arm.com>
 911
 912         * arm-dis.c (enum mve_instructions): Add new instructions.
 913         (enum mve_unpredictable): Add new reasons.
 914         (enum mve_undefined): Likewise.
 915         (is_mve_encoding_conflict): Handle new instructions.
 916         (is_mve_undefined): Likewise.
 917         (is_mve_unpredictable): Likewise.
 918         (coprocessor_opcodes): Move NEON VDUP from here...
 919         (neon_opcodes): ... to here.
 920         (mve_opcodes): Add new instructions.
 921         (print_mve_undefined):  Handle new reasons.
 922         (print_mve_unpredictable): Likewise.
 923         (print_mve_size): Handle new instructions.
 924         (print_insn_neon): Handle vdup.
 925         (print_insn_mve): Handle new operands.
 926
 927 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 928             Michael Collison <michael.collison@arm.com>
 929
 930         * arm-dis.c (enum mve_instructions): Add new instructions.
 931         (enum mve_unpredictable): Add new values.
 932         (mve_opcodes): Add new instructions.
 933         (vec_condnames): New array with vector conditions.
 934         (mve_predicatenames): New array with predicate suffixes.
 935         (mve_vec_sizename): New array with vector sizes.
 936         (enum vpt_pred_state): New enum with vector predication states.
 937         (struct vpt_block): New struct type for vpt blocks.
 938         (vpt_block_state): Global struct to keep track of state.
 939         (mve_extract_pred_mask): New helper function.
 940         (num_instructions_vpt_block): Likewise.
 941         (mark_outside_vpt_block): Likewise.
 942         (mark_inside_vpt_block): Likewise.
 943         (invert_next_predicate_state): Likewise.
 944         (update_next_predicate_state): Likewise.
 945         (update_vpt_block_state): Likewise.
 946         (is_vpt_instruction): Likewise.
 947         (is_mve_encoding_conflict): Add entries for new instructions.
 948         (is_mve_unpredictable): Likewise.
 949         (print_mve_unpredictable): Handle new cases.
 950         (print_instruction_predicate): Likewise.
 951         (print_mve_size): New function.
 952         (print_vec_condition): New function.
 953         (print_insn_mve): Handle vpt blocks and new print operands.
 954
 955 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 956
 957         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 958         8, 14 and 15 for Armv8.1-M Mainline.
 959
 960 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 961             Michael Collison <michael.collison@arm.com>
 962
 963         * arm-dis.c (enum mve_instructions): New enum.
 964         (enum mve_unpredictable): Likewise.
 965         (enum mve_undefined): Likewise.
 966         (struct mopcode32): New struct.
 967         (is_mve_okay_in_it): New function.
 968         (is_mve_architecture): Likewise.
 969         (arm_decode_field): Likewise.
 970         (arm_decode_field_multiple): Likewise.
 971         (is_mve_encoding_conflict): Likewise.
 972         (is_mve_undefined): Likewise.
 973         (is_mve_unpredictable): Likewise.
 974         (print_mve_undefined): Likewise.
 975         (print_mve_unpredictable): Likewise.
 976         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 977         (print_insn_mve): New function.
 978         (print_insn_thumb32): Handle MVE architecture.
 979         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 980
 981 2019-05-10  Nick Clifton  <nickc@redhat.com>
 982
 983         PR 24538
 984         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 985         end of the table prematurely.
 986
 987 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 988
 989         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 990         macros for R6.
 991
 992 2019-05-11  Alan Modra  <amodra@gmail.com>
 993
 994         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 995         when -Mraw is in effect.
 996
 997 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 998
 999         * aarch64-dis-2.c: Regenerate.
1000         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1001         (OP_SVE_BBB): New variant set.
1002         (OP_SVE_DDDD): New variant set.
1003         (OP_SVE_HHH): New variant set.
1004         (OP_SVE_HHHU): New variant set.
1005         (OP_SVE_SSS): New variant set.
1006         (OP_SVE_SSSU): New variant set.
1007         (OP_SVE_SHH): New variant set.
1008         (OP_SVE_SBBU): New variant set.
1009         (OP_SVE_DSS): New variant set.
1010         (OP_SVE_DHHU): New variant set.
1011         (OP_SVE_VMV_HSD_BHS): New variant set.
1012         (OP_SVE_VVU_HSD_BHS): New variant set.
1013         (OP_SVE_VVVU_SD_BH): New variant set.
1014         (OP_SVE_VVVU_BHSD): New variant set.
1015         (OP_SVE_VVV_QHD_DBS): New variant set.
1016         (OP_SVE_VVV_HSD_BHS): New variant set.
1017         (OP_SVE_VVV_HSD_BHS2): New variant set.
1018         (OP_SVE_VVV_BHS_HSD): New variant set.
1019         (OP_SVE_VV_BHS_HSD): New variant set.
1020         (OP_SVE_VVV_SD): New variant set.
1021         (OP_SVE_VVU_BHS_HSD): New variant set.
1022         (OP_SVE_VZVV_SD): New variant set.
1023         (OP_SVE_VZVV_BH): New variant set.
1024         (OP_SVE_VZV_SD): New variant set.
1025         (aarch64_opcode_table): Add sve2 instructions.
1026
1027 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1028
1029         * aarch64-asm-2.c: Regenerated.
1030         * aarch64-dis-2.c: Regenerated.
1031         * aarch64-opc-2.c: Regenerated.
1032         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1033         for SVE_SHLIMM_UNPRED_22.
1034         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1035         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1036         operand.
1037
1038 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1039
1040         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1041         sve_size_tsz_bhs iclass encode.
1042         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1043         sve_size_tsz_bhs iclass decode.
1044
1045 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1046
1047         * aarch64-asm-2.c: Regenerated.
1048         * aarch64-dis-2.c: Regenerated.
1049         * aarch64-opc-2.c: Regenerated.
1050         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1051         for SVE_Zm4_11_INDEX.
1052         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1053         (fields): Handle SVE_i2h field.
1054         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1055         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1056
1057 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1058
1059         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1060         sve_shift_tsz_bhsd iclass encode.
1061         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1062         sve_shift_tsz_bhsd iclass decode.
1063
1064 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1065
1066         * aarch64-asm-2.c: Regenerated.
1067         * aarch64-dis-2.c: Regenerated.
1068         * aarch64-opc-2.c: Regenerated.
1069         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1070         (aarch64_encode_variant_using_iclass): Handle
1071         sve_shift_tsz_hsd iclass encode.
1072         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1073         sve_shift_tsz_hsd iclass decode.
1074         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1075         for SVE_SHRIMM_UNPRED_22.
1076         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1077         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1078         operand.
1079
1080 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1081
1082         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1083         sve_size_013 iclass encode.
1084         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1085         sve_size_013 iclass decode.
1086
1087 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1088
1089         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1090         sve_size_bh iclass encode.
1091         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1092         sve_size_bh iclass decode.
1093
1094 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1095
1096         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1097         sve_size_sd2 iclass encode.
1098         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1099         sve_size_sd2 iclass decode.
1100         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1101         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1102
1103 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1104
1105         * aarch64-asm-2.c: Regenerated.
1106         * aarch64-dis-2.c: Regenerated.
1107         * aarch64-opc-2.c: Regenerated.
1108         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1109         for SVE_ADDR_ZX.
1110         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1111         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1112
1113 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1114
1115         * aarch64-asm-2.c: Regenerated.
1116         * aarch64-dis-2.c: Regenerated.
1117         * aarch64-opc-2.c: Regenerated.
1118         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1119         for SVE_Zm3_11_INDEX.
1120         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1121         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1122         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1123         fields.
1124         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1125
1126 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1127
1128         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1129         sve_size_hsd2 iclass encode.
1130         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1131         sve_size_hsd2 iclass decode.
1132         * aarch64-opc.c (fields): Handle SVE_size field.
1133         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1134
1135 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1136
1137         * aarch64-asm-2.c: Regenerated.
1138         * aarch64-dis-2.c: Regenerated.
1139         * aarch64-opc-2.c: Regenerated.
1140         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1141         for SVE_IMM_ROT3.
1142         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1143         (fields): Handle SVE_rot3 field.
1144         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1145         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1146
1147 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1148
1149         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1150         instructions.
1151
1152 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1153
1154         * aarch64-tbl.h
1155         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1156         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1157         aarch64_feature_sve2bitperm): New feature sets.
1158         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1159         for feature set addresses.
1160         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1161         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1162
1163 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1164             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1165
1166         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1167         argument and set ASE_EVA_R6 appropriately.
1168         (set_default_mips_dis_options): Pass ISA to above.
1169         (parse_mips_dis_option): Likewise.
1170         * mips-opc.c (EVAR6): New macro.
1171         (mips_builtin_opcodes): Add llwpe, scwpe.
1172
1173 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1174
1175         * aarch64-asm-2.c: Regenerated.
1176         * aarch64-dis-2.c: Regenerated.
1177         * aarch64-opc-2.c: Regenerated.
1178         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1179         AARCH64_OPND_TME_UIMM16.
1180         (aarch64_print_operand): Likewise.
1181         * aarch64-tbl.h (QL_IMM_NIL): New.
1182         (TME): New.
1183         (_TME_INSN): New.
1184         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1185
1186 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1187
1188         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1189
1190 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1191             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1192
1193         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1194
1195 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1196
1197         * s12z-opc.h: Add extern "C" bracketing to help
1198         users who wish to use this interface in c++ code.
1199
1200 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1201
1202         * s12z-opc.c (bm_decode): Handle bit map operations with the
1203         "reserved0" mode.
1204
1205 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1206
1207         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1208         specifier.  Add entries for VLDR and VSTR of system registers.
1209         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1210         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1211         of %J and %K format specifier.
1212
1213 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1214
1215         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1216         Add new entries for VSCCLRM instruction.
1217         (print_insn_coprocessor): Handle new %C format control code.
1218
1219 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1220
1221         * arm-dis.c (enum isa): New enum.
1222         (struct sopcode32): New structure.
1223         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1224         set isa field of all current entries to ANY.
1225         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1226         Only match an entry if its isa field allows the current mode.
1227
1228 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1229
1230         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1231         CLRM.
1232         (print_insn_thumb32): Add logic to print %n CLRM register list.
1233
1234 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1235
1236         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1237         and %Q patterns.
1238
1239 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1240
1241         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1242         (print_insn_thumb32): Edit the switch case for %Z.
1243
1244 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1245
1246         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1247
1248 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1249
1250         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1251
1252 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1253
1254         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1255
1256 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1257
1258         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1259         Arm register with r13 and r15 unpredictable.
1260         (thumb32_opcodes): New instructions for bfx and bflx.
1261
1262 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1263
1264         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1265
1266 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1267
1268         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1269
1270 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1271
1272         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1273
1274 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1275
1276         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1277
1278 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1279
1280         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1281         "optr". ("operator" is a reserved word in c++).
1282
1283 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1284
1285         * aarch64-opc.c (aarch64_print_operand): Add case for
1286         AARCH64_OPND_Rt_SP.
1287         (verify_constraints): Likewise.
1288         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1289         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1290         to accept Rt|SP as first operand.
1291         (AARCH64_OPERANDS): Add new Rt_SP.
1292         * aarch64-asm-2.c: Regenerated.
1293         * aarch64-dis-2.c: Regenerated.
1294         * aarch64-opc-2.c: Regenerated.
1295
1296 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1297
1298         * aarch64-asm-2.c: Regenerated.
1299         * aarch64-dis-2.c: Likewise.
1300         * aarch64-opc-2.c: Likewise.
1301         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1302
1303 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1304
1305         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1306
1307 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1308
1309         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1310         * i386-init.h: Regenerated.
1311
1312 2019-04-07  Alan Modra  <amodra@gmail.com>
1313
1314         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1315         op_separator to control printing of spaces, comma and parens
1316         rather than need_comma, need_paren and spaces vars.
1317
1318 2019-04-07  Alan Modra  <amodra@gmail.com>
1319
1320         PR 24421
1321         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1322         (print_insn_neon, print_insn_arm): Likewise.
1323
1324 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1325
1326         * i386-dis-evex.h (evex_table): Updated to support BF16
1327         instructions.
1328         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1329         and EVEX_W_0F3872_P_3.
1330         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1331         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1332         * i386-opc.h (enum): Add CpuAVX512_BF16.
1333         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1334         * i386-opc.tbl: Add AVX512 BF16 instructions.
1335         * i386-init.h: Regenerated.
1336         * i386-tbl.h: Likewise.
1337
1338 2019-04-05  Alan Modra  <amodra@gmail.com>
1339
1340         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1341         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1342         to favour printing of "-" branch hint when using the "y" bit.
1343         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1344
1345 2019-04-05  Alan Modra  <amodra@gmail.com>
1346
1347         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1348         opcode until first operand is output.
1349
1350 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1351
1352         PR gas/24349
1353         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1354         (valid_bo_post_v2): Add support for 'at' branch hints.
1355         (insert_bo): Only error on branch on ctr.
1356         (get_bo_hint_mask): New function.
1357         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1358         for inserting 'at' branch hints.
1359         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1360         for extracting 'at' branch hints.
1361         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1362         (BOE): Delete operand.
1363         (BOM, BOP): New operands.
1364         (RM): Update value.
1365         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1366         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1367         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1368         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1369         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1370         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1371         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1372         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1373         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1374         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1375         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1376         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1377         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1378         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1379         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1380         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1381         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1382         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1383         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1384         bttarl+>: New extended mnemonics.
1385
1386 2019-03-28  Alan Modra  <amodra@gmail.com>
1387
1388         PR 24390
1389         * ppc-opc.c (BTF): Define.
1390         (powerpc_opcodes): Use for mtfsb*.
1391         * ppc-dis.c (print_insn_powerpc): Print fields with both
1392         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1393
1394 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1395
1396         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1397         (mapping_symbol_for_insn): Implement new algorithm.
1398         (print_insn): Remove duplicate code.
1399
1400 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1401
1402         * aarch64-dis.c (print_insn_aarch64):
1403         Implement override.
1404
1405 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1406
1407         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1408         order.
1409
1410 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1411
1412         * aarch64-dis.c (last_stop_offset): New.
1413         (print_insn_aarch64): Use stop_offset.
1414
1415 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1416
1417         PR gas/24359
1418         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1419         CPU_ANY_AVX2_FLAGS.
1420         * i386-init.h: Regenerated.
1421
1422 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1423
1424         PR gas/24348
1425         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1426         vmovdqu16, vmovdqu32 and vmovdqu64.
1427         * i386-tbl.h: Regenerated.
1428
1429 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1430
1431         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1432         from vstrszb, vstrszh, and vstrszf.
1433
1434 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1435
1436         * s390-opc.txt: Add instruction descriptions.
1437
1438 2019-02-08  Jim Wilson  <jimw@sifive.com>
1439
1440         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1441         <bne>: Likewise.
1442
1443 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1444
1445         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1446
1447 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1448
1449         PR binutils/23212
1450         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1451         * aarch64-opc.c (verify_elem_sd): New.
1452         (fields): Add FLD_sz entr.
1453         * aarch64-tbl.h (_SIMD_INSN): New.
1454         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1455         fmulx scalar and vector by element isns.
1456
1457 2019-02-07  Nick Clifton  <nickc@redhat.com>
1458
1459         * po/sv.po: Updated Swedish translation.
1460
1461 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1462
1463         * s390-mkopc.c (main): Accept arch13 as cpu string.
1464         * s390-opc.c: Add new instruction formats and instruction opcode
1465         masks.
1466         * s390-opc.txt: Add new arch13 instructions.
1467
1468 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1469
1470         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1471         (aarch64_opcode): Change encoding for stg, stzg
1472         st2g and st2zg.
1473         * aarch64-asm-2.c: Regenerated.
1474         * aarch64-dis-2.c: Regenerated.
1475         * aarch64-opc-2.c: Regenerated.
1476
1477 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1478
1479         * aarch64-asm-2.c: Regenerated.
1480         * aarch64-dis-2.c: Likewise.
1481         * aarch64-opc-2.c: Likewise.
1482         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1483
1484 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1485             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1486
1487         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1488         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1489         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1490         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1491         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1492         case for ldstgv_indexed.
1493         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1494         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1495         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1496         * aarch64-asm-2.c: Regenerated.
1497         * aarch64-dis-2.c: Regenerated.
1498         * aarch64-opc-2.c: Regenerated.
1499
1500 2019-01-23  Nick Clifton  <nickc@redhat.com>
1501
1502         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1503
1504 2019-01-21  Nick Clifton  <nickc@redhat.com>
1505
1506         * po/de.po: Updated German translation.
1507         * po/uk.po: Updated Ukranian translation.
1508
1509 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1510         * mips-dis.c (mips_arch_choices): Fix typo in
1511         gs464, gs464e and gs264e descriptors.
1512
1513 2019-01-19  Nick Clifton  <nickc@redhat.com>
1514
1515         * configure: Regenerate.
1516         * po/opcodes.pot: Regenerate.
1517
1518 2018-06-24  Nick Clifton  <nickc@redhat.com>
1519
1520         2.32 branch created.
1521
1522 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1523
1524         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1525         if it is null.
1526         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1527         zero.
1528
1529 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1530
1531         * configure: Regenerate.
1532
1533 2019-01-07  Alan Modra  <amodra@gmail.com>
1534
1535         * configure: Regenerate.
1536         * po/POTFILES.in: Regenerate.
1537
1538 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1539
1540         * s12z-opc.c: New file.
1541         * s12z-opc.h: New file.
1542         * s12z-dis.c: Removed all code not directly related to display
1543         of instructions.  Used the interface provided by the new files
1544         instead.
1545         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1546         * Makefile.in: Regenerate.
1547         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1548         * configure: Regenerate.
1549
1550 2019-01-01  Alan Modra  <amodra@gmail.com>
1551
1552         Update year range in copyright notice of all files.
1553
1554 For older changes see ChangeLog-2018
1555 \f
1556 Copyright (C) 2019 Free Software Foundation, Inc.
1557
1558 Copying and distribution of this file, with or without modification,
1559 are permitted in any medium without royalty provided the copyright
1560 notice and this notice are preserved.
1561
1562 Local Variables:
1563 mode: change-log
1564 left-margin: 8
1565 fill-column: 74
1566 version-control: never
1567 End: