opcodes/ChangeLog

   1 2018-08-29  Martin Aberg  <maberg@gaisler.com>
   2
   3         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
   4         psr (PWRPSR) instruction.
   5
   6 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
   7
   8         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
   9
  10 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  11
  12         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
  13
  14 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  15
  16         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
  17         loongson3a as an alias of gs464 for compatibility.
  18         * mips-opc.c (mips_opcodes): Change Comments.
  19
  20 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  21
  22         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
  23         option.
  24         (print_mips_disassembler_options): Document -M loongson-ext.
  25         * mips-opc.c (LEXT2): New macro.
  26         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
  27
  28 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  29
  30          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
  31          descriptors.
  32          (parse_mips_ase_option): Handle -M loongson-ext option.
  33          (print_mips_disassembler_options): Document -M loongson-ext.
  34          * mips-opc.c (IL3A): Delete.
  35          * mips-opc.c (LEXT): New macro.
  36          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
  37          instructions.
  38
  39 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  40
  41         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
  42         descriptors.
  43         (parse_mips_ase_option): Handle -M loongson-cam option.
  44         (print_mips_disassembler_options): Document -M loongson-cam.
  45         * mips-opc.c (LCAM): New macro.
  46         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
  47         instructions.
  48
  49 2018-08-21  Alan Modra  <amodra@gmail.com>
  50
  51         * ppc-dis.c (operand_value_powerpc): Init "invalid".
  52         (skip_optional_operands): Count optional operands, and update
  53         ppc_optional_operand_value call.
  54         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
  55         (extract_vlensi): Likewise.
  56         (extract_fxm): Return default value for missing optional operand.
  57         (extract_ls, extract_raq, extract_tbr): Likewise.
  58         (insert_sxl, extract_sxl): New functions.
  59         (insert_esync, extract_esync): Remove Power9 handling and simplify.
  60         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
  61         flag and extra entry.
  62         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
  63         extract_sxl.
  64
  65 2018-08-20  Alan Modra  <amodra@gmail.com>
  66
  67         * sh-opc.h (MASK): Simplify.
  68
  69 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
  70
  71         * s12z-dis.c (bm_decode): Deal with cases where the mode is
  72         BM_RESERVED0 or BM_RESERVED1
  73         (bm_rel_decode, bm_n_bytes): Ditto.
  74
  75 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
  76
  77         * s12z.h: Delete.
  78
  79 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
  80
  81         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
  82         address with the addr32 prefix and without base nor index
  83         registers.
  84
  85 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
  86
  87         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
  88         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
  89         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
  90         (cpu_flags): Add CpuCMOV and CpuFXSR.
  91         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
  92         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
  93         * i386-init.h: Regenerated.
  94         * i386-tbl.h: Likewise.
  95
  96 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
  97
  98         * arc-regs.h: Update auxiliary registers.
  99
 100 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 101
 102         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 103         (RegIP, RegIZ): Define.
 104         * i386-reg.tbl: Adjust comments.
 105         (rip): Use Qword instead of BaseIndex. Use RegIP.
 106         (eip): Use Dword instead of BaseIndex. Use RegIP.
 107         (riz): Add Qword. Use RegIZ.
 108         (eiz): Add Dword. Use RegIZ.
 109         * i386-tbl.h: Re-generate.
 110
 111 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 112
 113         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 114         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 115         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 116         * i386-tbl.h: Re-generate.
 117
 118 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 119
 120         * i386-gen.c (operand_types): Remove Mem field.
 121         * i386-opc.h (union i386_operand_type): Remove mem field.
 122         * i386-init.h, i386-tbl.h: Re-generate.
 123
 124 2018-08-01  Alan Modra  <amodra@gmail.com>
 125
 126         * po/POTFILES.in: Regenerate.
 127
 128 2018-07-31  Nick Clifton  <nickc@redhat.com>
 129
 130         * po/sv.po: Updated Swedish translation.
 131
 132 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 133
 134         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 135         * i386-init.h, i386-tbl.h: Re-generate.
 136
 137 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 138
 139         * i386-opc.h (ZEROING_MASKING) Rename to ...
 140         (DYNAMIC_MASKING): ... this. Adjust comment.
 141         * i386-opc.tbl (MaskingMorZ): Define.
 142         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 143         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 144         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 145         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 146         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 147         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 148         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 149         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 150         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 151
 152 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 153
 154         * i386-opc.tbl: Use element rather than vector size for AVX512*
 155         scatter/gather insns.
 156         * i386-tbl.h: Re-generate.
 157
 158 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 159
 160         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 161         (cpu_flags): Drop CpuVREX.
 162         * i386-opc.h (CpuVREX): Delete.
 163         (union i386_cpu_flags): Remove cpuvrex.
 164         * i386-init.h, i386-tbl.h: Re-generate.
 165
 166 2018-07-30  Jim Wilson  <jimw@sifive.com>
 167
 168         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 169         fields.
 170         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 171
 172 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 173
 174         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 175         * Makefile.in: Regenerated.
 176         * configure.ac: Add C-SKY.
 177         * configure: Regenerated.
 178         * csky-dis.c: New file.
 179         * csky-opc.h: New file.
 180         * disassemble.c (ARCH_csky): Define.
 181         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 182         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 183
 184 2018-07-27  Alan Modra  <amodra@gmail.com>
 185
 186         * ppc-opc.c (insert_sprbat): Correct function parameter and
 187         return type.
 188         (extract_sprbat): Likewise, variable too.
 189
 190 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 191             Alan Modra  <amodra@gmail.com>
 192
 193         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 194         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 195         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 196         support disjointed BAT.
 197         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 198         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 199         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 200
 201 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 202             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 203
 204         * i386-gen.c (adjust_broadcast_modifier): New function.
 205         (process_i386_opcode_modifier): Add an argument for operands.
 206         Adjust the Broadcast value based on operands.
 207         (output_i386_opcode): Pass operand_types to
 208         process_i386_opcode_modifier.
 209         (process_i386_opcodes): Pass NULL as operands to
 210         process_i386_opcode_modifier.
 211         * i386-opc.h (BYTE_BROADCAST): New.
 212         (WORD_BROADCAST): Likewise.
 213         (DWORD_BROADCAST): Likewise.
 214         (QWORD_BROADCAST): Likewise.
 215         (i386_opcode_modifier): Expand broadcast to 3 bits.
 216         * i386-tbl.h: Regenerated.
 217
 218 2018-07-24  Alan Modra  <amodra@gmail.com>
 219
 220         PR 23430
 221         * or1k-desc.h: Regenerate.
 222
 223 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 224
 225         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 226         vcvtusi2ss, and vcvtusi2sd.
 227         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 228         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 229         * i386-tbl.h: Re-generate.
 230
 231 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 232
 233         * arc-opc.c (extract_w6): Fix extending the sign.
 234
 235 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 236
 237         * arc-tbl.h (vewt): Allow it for ARC EM family.
 238
 239 2018-07-23  Alan Modra  <amodra@gmail.com>
 240
 241         PR 23419
 242         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 243         opcode variants for mtspr/mfspr encodings.
 244
 245 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 246             Maciej W. Rozycki  <macro@mips.com>
 247
 248         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 249         loongson3a descriptors.
 250         (parse_mips_ase_option): Handle -M loongson-mmi option.
 251         (print_mips_disassembler_options): Document -M loongson-mmi.
 252         * mips-opc.c (LMMI): New macro.
 253         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 254         instructions.
 255
 256 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 257
 258         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 259         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 260         IgnoreSize and [XYZ]MMword where applicable.
 261         * i386-tbl.h: Re-generate.
 262
 263 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 264
 265         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 266         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 267         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 268         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 269         * i386-tbl.h: Re-generate.
 270
 271 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 272
 273         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 274         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 275         VPCLMULQDQ templates into their respective AVX512VL counterparts
 276         where possible, using Disp8ShiftVL and CheckRegSize instead of
 277         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 278         * i386-tbl.h: Re-generate.
 279
 280 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 281
 282         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 283         AVX512VL counterparts where possible, using Disp8ShiftVL and
 284         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 285         IgnoreSize) as appropriate.
 286         * i386-tbl.h: Re-generate.
 287
 288 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 289
 290         * i386-opc.tbl: Fold AVX512BW templates into their respective
 291         AVX512VL counterparts where possible, using Disp8ShiftVL and
 292         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 293         IgnoreSize) as appropriate.
 294         * i386-tbl.h: Re-generate.
 295
 296 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 297
 298         * i386-opc.tbl: Fold AVX512CD templates into their respective
 299         AVX512VL counterparts where possible, using Disp8ShiftVL and
 300         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 301         IgnoreSize) as appropriate.
 302         * i386-tbl.h: Re-generate.
 303
 304 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 305
 306         * i386-opc.h (DISP8_SHIFT_VL): New.
 307         * i386-opc.tbl (Disp8ShiftVL):  Define.
 308         (various): Fold AVX512VL templates into their respective
 309         AVX512F counterparts where possible, using Disp8ShiftVL and
 310         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 311         IgnoreSize) as appropriate.
 312         * i386-tbl.h: Re-generate.
 313
 314 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 315
 316         * Makefile.am: Change dependencies and rule for
 317         $(srcdir)/i386-init.h.
 318         * Makefile.in: Re-generate.
 319         * i386-gen.c (process_i386_opcodes): New local variable
 320         "marker". Drop opening of input file. Recognize marker and line
 321         number directives.
 322         * i386-opc.tbl (OPCODE_I386_H): Define.
 323         (i386-opc.h): Include it.
 324         (None): Undefine.
 325
 326 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 327
 328         PR gas/23418
 329         * i386-opc.h (Byte): Update comments.
 330         (Word): Likewise.
 331         (Dword): Likewise.
 332         (Fword): Likewise.
 333         (Qword): Likewise.
 334         (Tbyte): Likewise.
 335         (Xmmword): Likewise.
 336         (Ymmword): Likewise.
 337         (Zmmword): Likewise.
 338         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 339         vcvttps2uqq.
 340         * i386-tbl.h: Regenerated.
 341
 342 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 343
 344         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 345         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 346         * aarch64-asm-2.c: Regenerate.
 347         * aarch64-dis-2.c: Regenerate.
 348         * aarch64-opc-2.c: Regenerate.
 349
 350 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 351
 352         PR binutils/23192
 353         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 354         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 355         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 356         sqdmulh, sqrdmulh): Use Em16.
 357
 358 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 359
 360         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 361         csdb together with them.
 362         (thumb32_opcodes): Likewise.
 363
 364 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 365
 366         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 367         requiring 32-bit registers as operands 2 and 3. Improve
 368         comments.
 369         (mwait, mwaitx): Fold templates. Improve comments.
 370         OPERAND_TYPE_INOUTPORTREG.
 371         * i386-tbl.h: Re-generate.
 372
 373 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 374
 375         * i386-gen.c (operand_type_init): Remove
 376         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 377         OPERAND_TYPE_INOUTPORTREG.
 378         * i386-init.h: Re-generate.
 379
 380 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 381
 382         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 383         (wrssq, wrussq): Add Qword.
 384         * i386-tbl.h: Re-generate.
 385
 386 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 387
 388         * i386-opc.h: Rename OTMax to OTNum.
 389         (OTNumOfUints): Adjust calculation.
 390         (OTUnused): Directly alias to OTNum.
 391
 392 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 393
 394         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 395         `reg_xys'.
 396         (lea_reg_xys): Likewise.
 397         (print_insn_loop_primitive): Rename `reg' local variable to
 398         `reg_dxy'.
 399
 400 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 401
 402         PR binutils/23242
 403         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 404
 405 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 406
 407         PR binutils/23369
 408         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 409         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 410
 411 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 412
 413         PR tdep/8282
 414         * mips-dis.c (mips_option_arg_t): New enumeration.
 415         (mips_options): New variable.
 416         (disassembler_options_mips): New function.
 417         (print_mips_disassembler_options): Reimplement in terms of
 418         `disassembler_options_mips'.
 419         * arm-dis.c (disassembler_options_arm): Adapt to using the
 420         `disasm_options_and_args_t' structure.
 421         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 422         * s390-dis.c (disassembler_options_s390): Likewise.
 423
 424 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 425
 426         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 427         expected result.
 428         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 429         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 430         * testsuite/ld-arm/tls-longplt.d: Likewise.
 431
 432 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 433
 434         PR binutils/23192
 435         * aarch64-asm-2.c: Regenerate.
 436         * aarch64-dis-2.c: Likewise.
 437         * aarch64-opc-2.c: Likewise.
 438         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 439         * aarch64-opc.c (operand_general_constraint_met_p,
 440         aarch64_print_operand): Likewise.
 441         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 442         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 443         fmlal2, fmlsl2.
 444         (AARCH64_OPERANDS): Add Em2.
 445
 446 2018-06-26  Nick Clifton  <nickc@redhat.com>
 447
 448         * po/uk.po: Updated Ukranian translation.
 449         * po/de.po: Updated German translation.
 450         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 451
 452 2018-06-26  Nick Clifton  <nickc@redhat.com>
 453
 454         * nfp-dis.c: Fix spelling mistake.
 455
 456 2018-06-24  Nick Clifton  <nickc@redhat.com>
 457
 458         * configure: Regenerate.
 459         * po/opcodes.pot: Regenerate.
 460
 461 2018-06-24  Nick Clifton  <nickc@redhat.com>
 462
 463         2.31 branch created.
 464
 465 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 466
 467         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 468         * aarch64-asm-2.c: Regenerate.
 469         * aarch64-dis-2.c: Likewise.
 470
 471 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 472
 473         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 474         `-M ginv' option description.
 475
 476 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 477
 478         PR gas/23305
 479         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 480         la and lla.
 481
 482 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 483
 484         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 485         * configure.ac: Remove AC_PREREQ.
 486         * Makefile.in: Re-generate.
 487         * aclocal.m4: Re-generate.
 488         * configure: Re-generate.
 489
 490 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 491
 492         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 493         mips64r6 descriptors.
 494         (parse_mips_ase_option): Handle -Mginv option.
 495         (print_mips_disassembler_options): Document -Mginv.
 496         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 497         (GINV): New macro.
 498         (mips_opcodes): Define ginvi and ginvt.
 499
 500 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 501             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 502
 503         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 504         * mips-opc.c (CRC, CRC64): New macros.
 505         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 506         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 507         crc32cd for CRC64.
 508
 509 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 510
 511         PR 20319
 512         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 513         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 514
 515 2018-06-06  Alan Modra  <amodra@gmail.com>
 516
 517         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 518         setjmp.  Move init for some other vars later too.
 519
 520 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 521
 522         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 523         (dis_private): Add new fields for property section tracking.
 524         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 525         (xtensa_instruction_fits): New functions.
 526         (fetch_data): Bump minimal fetch size to 4.
 527         (print_insn_xtensa): Make struct dis_private static.
 528         Load and prepare property table on section change.
 529         Don't disassemble literals. Don't disassemble instructions that
 530         cross property table boundaries.
 531
 532 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 533
 534         * configure: Regenerated.
 535
 536 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 537
 538         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 539         * i386-tbl.h: Re-generate.
 540
 541 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 542
 543         * i386-opc.tbl (sldt, str): Add NoRex64.
 544         * i386-tbl.h: Re-generate.
 545
 546 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 547
 548         * i386-opc.tbl (invpcid): Add Oword.
 549         * i386-tbl.h: Re-generate.
 550
 551 2018-06-01  Alan Modra  <amodra@gmail.com>
 552
 553         * sysdep.h (_bfd_error_handler): Don't declare.
 554         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 555         * rl78-decode.opc: Likewise.
 556         * msp430-decode.c: Regenerate.
 557         * rl78-decode.c: Regenerate.
 558
 559 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 560
 561         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 562         * i386-init.h : Regenerated.
 563
 564 2018-05-25  Alan Modra  <amodra@gmail.com>
 565
 566         * Makefile.in: Regenerate.
 567         * po/POTFILES.in: Regenerate.
 568
 569 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 570
 571         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 572         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 573         (insert_bab, extract_bab, insert_btab, extract_btab,
 574         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 575         (BAT, BBA VBA RBS XB6S): Delete macros.
 576         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 577         (BB, BD, RBX, XC6): Update for new macros.
 578         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 579         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 580         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 581         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 582
 583 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 584
 585         * Makefile.am: Add support for s12z architecture.
 586         * configure.ac: Likewise.
 587         * disassemble.c: Likewise.
 588         * disassemble.h: Likewise.
 589         * Makefile.in: Regenerate.
 590         * configure: Regenerate.
 591         * s12z-dis.c: New file.
 592         * s12z.h: New file.
 593
 594 2018-05-18  Alan Modra  <amodra@gmail.com>
 595
 596         * nfp-dis.c: Don't #include libbfd.h.
 597         (init_nfp3200_priv): Use bfd_get_section_contents.
 598         (nit_nfp6000_mecsr_sec): Likewise.
 599
 600 2018-05-17  Nick Clifton  <nickc@redhat.com>
 601
 602         * po/zh_CN.po: Updated simplified Chinese translation.
 603
 604 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 605
 606         PR binutils/23109
 607         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 608         * aarch64-dis-2.c: Regenerate.
 609
 610 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 611
 612         PR binutils/21446
 613         * aarch64-asm.c (opintl.h): Include.
 614         (aarch64_ins_sysreg): Enforce read/write constraints.
 615         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 616         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 617         (F_REG_READ, F_REG_WRITE): New.
 618         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 619         AARCH64_OPND_SYSREG.
 620         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 621         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 622         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 623         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 624         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 625         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 626         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 627         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 628         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 629         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 630         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 631         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 632         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 633         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 634         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 635         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 636         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 637
 638 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 639
 640         PR binutils/21446
 641         * aarch64-dis.c (no_notes: New.
 642         (parse_aarch64_dis_option): Support notes.
 643         (aarch64_decode_insn, print_operands): Likewise.
 644         (print_aarch64_disassembler_options): Document notes.
 645         * aarch64-opc.c (aarch64_print_operand): Support notes.
 646
 647 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 648
 649         PR binutils/21446
 650         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 651         and take error struct.
 652         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 653         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 654         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 655         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 656         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 657         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 658         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 659         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 660         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 661         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 662         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 663         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 664         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 665         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 666         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 667         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 668         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 669         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 670         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 671         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 672         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 673         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 674         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 675         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 676         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 677         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 678         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 679         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 680         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 681         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 682         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 683         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 684         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 685         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 686         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 687         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 688         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 689         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 690         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 691         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 692         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 693         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 694         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 695         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 696         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 697         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 698         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 699         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 700         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 701         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 702         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 703         (determine_disassembling_preference, aarch64_decode_insn,
 704         print_insn_aarch64_word, print_insn_data): Take errors struct.
 705         (print_insn_aarch64): Use errors.
 706         * aarch64-asm-2.c: Regenerate.
 707         * aarch64-dis-2.c: Regenerate.
 708         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 709         boolean in aarch64_insert_operan.
 710         (print_operand_extractor): Likewise.
 711         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 712
 713 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 714
 715         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 716
 717 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 718
 719         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 720
 721 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 722
 723         * cr16-opc.c (cr16_instruction): Comment typo fix.
 724         * hppa-dis.c (print_insn_hppa): Likewise.
 725
 726 2018-05-08  Jim Wilson  <jimw@sifive.com>
 727
 728         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 729         (match_c_slli64, match_srxi_as_c_srxi): New.
 730         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 731         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 732         <c.slli, c.srli, c.srai>: Use match_s_slli.
 733         <c.slli64, c.srli64, c.srai64>: New.
 734
 735 2018-05-08  Alan Modra  <amodra@gmail.com>
 736
 737         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 738         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 739         partition opcode space for index lookup.
 740
 741 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 742
 743         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 744         <insn_length>: ...with this.  Update usage.
 745         Remove duplicate call to *info->memory_error_func.
 746
 747 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 748             H.J. Lu  <hongjiu.lu@intel.com>
 749
 750         * i386-dis.c (Gva): New.
 751         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 752         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 753         (prefix_table): New instructions (see prefix above).
 754         (mod_table): New instructions (see prefix above).
 755         (OP_G): Handle va_mode.
 756         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 757         CPU_MOVDIR64B_FLAGS.
 758         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 759         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 760         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 761         * i386-opc.tbl: Add movidir{i,64b}.
 762         * i386-init.h: Regenerated.
 763         * i386-tbl.h: Likewise.
 764
 765 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 766
 767         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 768         AddrPrefixOpReg.
 769         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 770         (AddrPrefixOpReg): This.
 771         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 772         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 773
 774 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 775
 776         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 777         (vle_num_opcodes): Likewise.
 778         (spe2_num_opcodes): Likewise.
 779         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 780         initialization loop.
 781         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 782         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 783         only once.
 784
 785 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 786
 787         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 788
 789 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 790
 791         Makefile.am: Added nfp-dis.c.
 792         configure.ac: Added bfd_nfp_arch.
 793         disassemble.h: Added print_insn_nfp prototype.
 794         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 795         nfp-dis.c: New, for NFP support.
 796         po/POTFILES.in: Added nfp-dis.c to the list.
 797         Makefile.in: Regenerate.
 798         configure: Regenerate.
 799
 800 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 801
 802         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 803         templates into their base ones.
 804         * i386-tlb.h: Re-generate.
 805
 806 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 807
 808         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 809         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 810         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 811         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 812         * i386-init.h: Re-generate.
 813
 814 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 815
 816         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 817         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 818         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 819         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 820         comment.
 821         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 822         and CpuRegMask.
 823         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 824         CpuRegMask: Delete.
 825         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 826         cpuregzmm, and cpuregmask.
 827         * i386-init.h: Re-generate.
 828         * i386-tbl.h: Re-generate.
 829
 830 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 831
 832         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 833         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 834         * i386-init.h: Re-generate.
 835
 836 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 837
 838         * i386-gen.c (VexImmExt): Delete.
 839         * i386-opc.h (VexImmExt, veximmext): Delete.
 840         * i386-opc.tbl: Drop all VexImmExt uses.
 841         * i386-tlb.h: Re-generate.
 842
 843 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 844
 845         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 846         register-only forms.
 847         * i386-tlb.h: Re-generate.
 848
 849 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 850
 851         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 852
 853 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 854
 855         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 856         PREFIX_0F1C.
 857         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 858         (cpu_flags): Add CpuCLDEMOTE.
 859         * i386-init.h: Regenerate.
 860         * i386-opc.h (enum): Add CpuCLDEMOTE,
 861         (i386_cpu_flags): Add cpucldemote.
 862         * i386-opc.tbl: Add cldemote.
 863         * i386-tbl.h: Regenerate.
 864
 865 2018-04-16  Alan Modra  <amodra@gmail.com>
 866
 867         * Makefile.am: Remove sh5 and sh64 support.
 868         * configure.ac: Likewise.
 869         * disassemble.c: Likewise.
 870         * disassemble.h: Likewise.
 871         * sh-dis.c: Likewise.
 872         * sh64-dis.c: Delete.
 873         * sh64-opc.c: Delete.
 874         * sh64-opc.h: Delete.
 875         * Makefile.in: Regenerate.
 876         * configure: Regenerate.
 877         * po/POTFILES.in: Regenerate.
 878
 879 2018-04-16  Alan Modra  <amodra@gmail.com>
 880
 881         * Makefile.am: Remove w65 support.
 882         * configure.ac: Likewise.
 883         * disassemble.c: Likewise.
 884         * disassemble.h: Likewise.
 885         * w65-dis.c: Delete.
 886         * w65-opc.h: Delete.
 887         * Makefile.in: Regenerate.
 888         * configure: Regenerate.
 889         * po/POTFILES.in: Regenerate.
 890
 891 2018-04-16  Alan Modra  <amodra@gmail.com>
 892
 893         * configure.ac: Remove we32k support.
 894         * configure: Regenerate.
 895
 896 2018-04-16  Alan Modra  <amodra@gmail.com>
 897
 898         * Makefile.am: Remove m88k support.
 899         * configure.ac: Likewise.
 900         * disassemble.c: Likewise.
 901         * disassemble.h: Likewise.
 902         * m88k-dis.c: Delete.
 903         * Makefile.in: Regenerate.
 904         * configure: Regenerate.
 905         * po/POTFILES.in: Regenerate.
 906
 907 2018-04-16  Alan Modra  <amodra@gmail.com>
 908
 909         * Makefile.am: Remove i370 support.
 910         * configure.ac: Likewise.
 911         * disassemble.c: Likewise.
 912         * disassemble.h: Likewise.
 913         * i370-dis.c: Delete.
 914         * i370-opc.c: Delete.
 915         * Makefile.in: Regenerate.
 916         * configure: Regenerate.
 917         * po/POTFILES.in: Regenerate.
 918
 919 2018-04-16  Alan Modra  <amodra@gmail.com>
 920
 921         * Makefile.am: Remove h8500 support.
 922         * configure.ac: Likewise.
 923         * disassemble.c: Likewise.
 924         * disassemble.h: Likewise.
 925         * h8500-dis.c: Delete.
 926         * h8500-opc.h: Delete.
 927         * Makefile.in: Regenerate.
 928         * configure: Regenerate.
 929         * po/POTFILES.in: Regenerate.
 930
 931 2018-04-16  Alan Modra  <amodra@gmail.com>
 932
 933         * configure.ac: Remove tahoe support.
 934         * configure: Regenerate.
 935
 936 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 937
 938         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 939         umwait.
 940         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 941         64-bit mode.
 942         * i386-tbl.h: Regenerated.
 943
 944 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 945
 946         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 947         PREFIX_MOD_1_0FAE_REG_6.
 948         (va_mode): New.
 949         (OP_E_register): Use va_mode.
 950         * i386-dis-evex.h (prefix_table):
 951         New instructions (see prefixes above).
 952         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 953         (cpu_flags): Likewise.
 954         * i386-opc.h (enum): Likewise.
 955         (i386_cpu_flags): Likewise.
 956         * i386-opc.tbl: Add umonitor, umwait, tpause.
 957         * i386-init.h: Regenerate.
 958         * i386-tbl.h: Likewise.
 959
 960 2018-04-11  Alan Modra  <amodra@gmail.com>
 961
 962         * opcodes/i860-dis.c: Delete.
 963         * opcodes/i960-dis.c: Delete.
 964         * Makefile.am: Remove i860 and i960 support.
 965         * configure.ac: Likewise.
 966         * disassemble.c: Likewise.
 967         * disassemble.h: Likewise.
 968         * Makefile.in: Regenerate.
 969         * configure: Regenerate.
 970         * po/POTFILES.in: Regenerate.
 971
 972 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 973
 974         PR binutils/23025
 975         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 976         to 0.
 977         (print_insn): Clear vex instead of vex.evex.
 978
 979 2018-04-04  Nick Clifton  <nickc@redhat.com>
 980
 981         * po/es.po: Updated Spanish translation.
 982
 983 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 984
 985         * i386-gen.c (opcode_modifiers): Delete VecESize.
 986         * i386-opc.h (VecESize): Delete.
 987         (struct i386_opcode_modifier): Delete vecesize.
 988         * i386-opc.tbl: Drop VecESize.
 989         * i386-tlb.h: Re-generate.
 990
 991 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 992
 993         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 994         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 995         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 996         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 997         * i386-tlb.h: Re-generate.
 998
 999 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1000
1001         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1002         Fold AVX512 forms
1003         * i386-tlb.h: Re-generate.
1004
1005 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1006
1007         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1008         (vex_len_table): Drop Y for vcvt*2si.
1009         (putop): Replace plain 'Y' handling by abort().
1010
1011 2018-03-28  Nick Clifton  <nickc@redhat.com>
1012
1013         PR 22988
1014         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1015         instructions with only a base address register.
1016         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1017         handle AARHC64_OPND_SVE_ADDR_R.
1018         (aarch64_print_operand): Likewise.
1019         * aarch64-asm-2.c: Regenerate.
1020         * aarch64_dis-2.c: Regenerate.
1021         * aarch64-opc-2.c: Regenerate.
1022
1023 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1024
1025         * i386-opc.tbl: Drop VecESize from register only insn forms and
1026         memory forms not allowing broadcast.
1027         * i386-tlb.h: Re-generate.
1028
1029 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1030
1031         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1032         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1033         sha256*): Drop Disp<N>.
1034
1035 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1036
1037         * i386-dis.c (EbndS, bnd_swap_mode): New.
1038         (prefix_table): Use EbndS.
1039         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1040         * i386-opc.tbl (bndmov): Move misplaced Load.
1041         * i386-tlb.h: Re-generate.
1042
1043 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1044
1045         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1046         templates allowing memory operands and folded ones for register
1047         only flavors.
1048         * i386-tlb.h: Re-generate.
1049
1050 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1051
1052         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1053         256-bit templates. Drop redundant leftover Disp<N>.
1054         * i386-tlb.h: Re-generate.
1055
1056 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1057
1058         * riscv-opc.c (riscv_insn_types): New.
1059
1060 2018-03-13  Nick Clifton  <nickc@redhat.com>
1061
1062         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1063
1064 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1065
1066         * i386-opc.tbl: Add Optimize to clr.
1067         * i386-tbl.h: Regenerated.
1068
1069 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1070
1071         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1072         * i386-opc.h (OldGcc): Removed.
1073         (i386_opcode_modifier): Remove oldgcc.
1074         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1075         instructions for old (<= 2.8.1) versions of gcc.
1076         * i386-tbl.h: Regenerated.
1077
1078 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1079
1080         * i386-opc.h (EVEXDYN): New.
1081         * i386-opc.tbl: Fold various AVX512VL templates.
1082         * i386-tlb.h: Re-generate.
1083
1084 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1085
1086         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1087         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1088         vpexpandd, vpexpandq): Fold AFX512VF templates.
1089         * i386-tlb.h: Re-generate.
1090
1091 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1092
1093         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1094         Fold 128- and 256-bit VEX-encoded templates.
1095         * i386-tlb.h: Re-generate.
1096
1097 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1098
1099         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1100         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1101         vpexpandd, vpexpandq): Fold AVX512F templates.
1102         * i386-tlb.h: Re-generate.
1103
1104 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1105
1106         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1107         64-bit templates. Drop Disp<N>.
1108         * i386-tlb.h: Re-generate.
1109
1110 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1111
1112         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1113         and 256-bit templates.
1114         * i386-tlb.h: Re-generate.
1115
1116 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1117
1118         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1119         * i386-tlb.h: Re-generate.
1120
1121 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1122
1123         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1124         Drop NoAVX.
1125         * i386-tlb.h: Re-generate.
1126
1127 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1128
1129         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1130         * i386-tlb.h: Re-generate.
1131
1132 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1133
1134         * i386-gen.c (opcode_modifiers): Delete FloatD.
1135         * i386-opc.h (FloatD): Delete.
1136         (struct i386_opcode_modifier): Delete floatd.
1137         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1138         FloatD by D.
1139         * i386-tlb.h: Re-generate.
1140
1141 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1142
1143         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1144
1145 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1146
1147         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1148         * i386-tlb.h: Re-generate.
1149
1150 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1151
1152         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1153         forms.
1154         * i386-tlb.h: Re-generate.
1155
1156 2018-03-07  Alan Modra  <amodra@gmail.com>
1157
1158         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1159         bfd_arch_rs6000.
1160         * disassemble.h (print_insn_rs6000): Delete.
1161         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1162         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1163         (print_insn_rs6000): Delete.
1164
1165 2018-03-03  Alan Modra  <amodra@gmail.com>
1166
1167         * sysdep.h (opcodes_error_handler): Define.
1168         (_bfd_error_handler): Declare.
1169         * Makefile.am: Remove stray #.
1170         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1171         EDIT" comment.
1172         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1173         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1174         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1175         opcodes_error_handler to print errors.  Standardize error messages.
1176         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1177         and include opintl.h.
1178         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1179         * i386-gen.c: Standardize error messages.
1180         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1181         * Makefile.in: Regenerate.
1182         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1183         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1184         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1185         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1186         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1187         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1188         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1189         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1190         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1191         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1192         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1193         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1194         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1195
1196 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1197
1198         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1199         vpsub[bwdq] instructions.
1200         * i386-tbl.h: Regenerated.
1201
1202 2018-03-01  Alan Modra  <amodra@gmail.com>
1203
1204         * configure.ac (ALL_LINGUAS): Sort.
1205         * configure: Regenerate.
1206
1207 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1208
1209         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1210         macro by assignements.
1211
1212 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1213
1214         PR gas/22871
1215         * i386-gen.c (opcode_modifiers): Add Optimize.
1216         * i386-opc.h (Optimize): New enum.
1217         (i386_opcode_modifier): Add optimize.
1218         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1219         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1220         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1221         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1222         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1223         vpxord and vpxorq.
1224         * i386-tbl.h: Regenerated.
1225
1226 2018-02-26  Alan Modra  <amodra@gmail.com>
1227
1228         * crx-dis.c (getregliststring): Allocate a large enough buffer
1229         to silence false positive gcc8 warning.
1230
1231 2018-02-22  Shea Levy <shea@shealevy.com>
1232
1233         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1234
1235 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1236
1237         * i386-opc.tbl: Add {rex},
1238         * i386-tbl.h: Regenerated.
1239
1240 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1241
1242         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1243         (mips16_opcodes): Replace `M' with `m' for "restore".
1244
1245 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1246
1247         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1248
1249 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1250
1251         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1252         variable to `function_index'.
1253
1254 2018-02-13  Nick Clifton  <nickc@redhat.com>
1255
1256         PR 22823
1257         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1258         about truncation of printing.
1259
1260 2018-02-12  Henry Wong <henry@stuffedcow.net>
1261
1262         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1263
1264 2018-02-05  Nick Clifton  <nickc@redhat.com>
1265
1266         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1267
1268 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1269
1270         * i386-dis.c (enum): Add pconfig.
1271         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1272         (cpu_flags): Add CpuPCONFIG.
1273         * i386-opc.h (enum): Add CpuPCONFIG.
1274         (i386_cpu_flags): Add cpupconfig.
1275         * i386-opc.tbl: Add PCONFIG instruction.
1276         * i386-init.h: Regenerate.
1277         * i386-tbl.h: Likewise.
1278
1279 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1280
1281         * i386-dis.c (enum): Add PREFIX_0F09.
1282         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1283         (cpu_flags): Add CpuWBNOINVD.
1284         * i386-opc.h (enum): Add CpuWBNOINVD.
1285         (i386_cpu_flags): Add cpuwbnoinvd.
1286         * i386-opc.tbl: Add WBNOINVD instruction.
1287         * i386-init.h: Regenerate.
1288         * i386-tbl.h: Likewise.
1289
1290 2018-01-17  Jim Wilson  <jimw@sifive.com>
1291
1292         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1293
1294 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1295
1296         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1297         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1298         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1299         (cpu_flags): Add CpuIBT, CpuSHSTK.
1300         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1301         (i386_cpu_flags): Add cpuibt, cpushstk.
1302         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1303         * i386-init.h: Regenerate.
1304         * i386-tbl.h: Likewise.
1305
1306 2018-01-16  Nick Clifton  <nickc@redhat.com>
1307
1308         * po/pt_BR.po: Updated Brazilian Portugese translation.
1309         * po/de.po: Updated German translation.
1310
1311 2018-01-15  Jim Wilson  <jimw@sifive.com>
1312
1313         * riscv-opc.c (match_c_nop): New.
1314         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1315
1316 2018-01-15  Nick Clifton  <nickc@redhat.com>
1317
1318         * po/uk.po: Updated Ukranian translation.
1319
1320 2018-01-13  Nick Clifton  <nickc@redhat.com>
1321
1322         * po/opcodes.pot: Regenerated.
1323
1324 2018-01-13  Nick Clifton  <nickc@redhat.com>
1325
1326         * configure: Regenerate.
1327
1328 2018-01-13  Nick Clifton  <nickc@redhat.com>
1329
1330         2.30 branch created.
1331
1332 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1333
1334         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1335         * i386-tbl.h: Regenerate.
1336
1337 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1338
1339         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1340         * i386-tbl.h: Re-generate.
1341
1342 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1343
1344         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1345         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1346         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1347         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1348         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1349         Disp8MemShift of AVX512VL forms.
1350         * i386-tbl.h: Re-generate.
1351
1352 2018-01-09  Jim Wilson  <jimw@sifive.com>
1353
1354         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1355         then the hi_addr value is zero.
1356
1357 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1358
1359         * arm-dis.c (arm_opcodes): Add csdb.
1360         (thumb32_opcodes): Add csdb.
1361
1362 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1363
1364         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1365         * aarch64-asm-2.c: Regenerate.
1366         * aarch64-dis-2.c: Regenerate.
1367         * aarch64-opc-2.c: Regenerate.
1368
1369 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1370
1371         PR gas/22681
1372         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1373         Remove AVX512 vmovd with 64-bit operands.
1374         * i386-tbl.h: Regenerated.
1375
1376 2018-01-05  Jim Wilson  <jimw@sifive.com>
1377
1378         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1379         jalr.
1380
1381 2018-01-03  Alan Modra  <amodra@gmail.com>
1382
1383         Update year range in copyright notice of all files.
1384
1385 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1386
1387         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1388         and OPERAND_TYPE_REGZMM entries.
1389
1390 For older changes see ChangeLog-2017
1391 \f
1392 Copyright (C) 2018 Free Software Foundation, Inc.
1393
1394 Copying and distribution of this file, with or without modification,
1395 are permitted in any medium without royalty provided the copyright
1396 notice and this notice are preserved.
1397
1398 Local Variables:
1399 mode: change-log
1400 left-margin: 8
1401 fill-column: 74
1402 version-control: never
1403 End: