opcodes/ChangeLog

   1 2010-10-15  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * bfin-dis.c (decode_dsp32alu_0): Call imm5d() for BYTEOP2M.
   4
   5 2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>
   6
   7         * i386-opc.tbl: Remove CheckRegSize from movq.
   8         * i386-tbl.h: Regenerated.
   9
  10 2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>
  11
  12         * i386-opc.tbl: Remove CheckRegSize from instructions with
  13         0, 1 or fixed operands.
  14         * i386-tbl.h: Regenerated.
  15
  16 2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>
  17
  18         * i386-gen.c (opcode_modifiers): Add CheckRegSize.
  19
  20         * i386-opc.h (CheckRegSize): New.
  21         (i386_opcode_modifier): Add checkregsize.
  22
  23         * i386-opc.tbl: Add CheckRegSize to instructions which
  24         require register size check.
  25         * i386-tbl.h: Regenerated.
  26
  27 2010-10-12  Andreas Schwab  <schwab@linux-m68k.org>
  28
  29         * m68k-opc.c (m68k_opcodes): Move fnop before fbf.
  30
  31 2010-10-11  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  32
  33         * s390-opc.c: Make the instruction masks for the load/store on
  34         condition instructions to cover the condition code mask as well.
  35         * s390-opc.txt: lgoc -> locg and stgoc -> stocg.
  36
  37 2010-10-11  Jan Kratochvil  <jan.kratochvil@redhat.com>
  38             Jiang Jilin  <freephp@gmail.com>
  39
  40         * Makefile.am (libopcodes_a_SOURCES): New as empty.
  41         * Makefile.in: Regenerate.
  42
  43 2010-10-09  Matt Rice  <ratmice@gmail.com>
  44
  45         * fr30-desc.h: Regenerate.
  46         * frv-desc.h: Regenerate.
  47         * ip2k-desc.h: Regenerate.
  48         * iq2000-desc.h: Regenerate.
  49         * lm32-desc.h: Regenerate.
  50         * m32c-desc.h: Regenerate.
  51         * m32r-desc.h: Regenerate.
  52         * mep-desc.h: Regenerate.
  53         * mep-opc.c: Regenerate.
  54         * mt-desc.h: Regenerate.
  55         * openrisc-desc.h: Regenerate.
  56         * xc16x-desc.h: Regenerate.
  57         * xstormy16-desc.h: Regenerate.
  58
  59 2010-10-08  Pierre Muller  <muller@ics.u-strasbg.fr>
  60
  61         Fix build with -DDEBUG=7
  62         * frv-opc.c: Regenerate.
  63         * or32-dis.c (DEBUG): Don't redefine.
  64         (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register):
  65         Adapt DEBUG code to some type changes throughout.
  66         * or32-opc.c (or32_extract): Likewise.
  67
  68 2010-10-07  Bernd Schmidt  <bernds@codesourcery.com>
  69
  70         * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
  71         in SPKERNEL instructions.
  72
  73 2010-10-02  H.J. Lu  <hongjiu.lu@intel.com>
  74
  75         PR binutils/12076
  76         * i386-dis.c (RMAL): Remove duplicate.
  77
  78 2010-09-30  Pierre Muller  <muller@ics.u-strasbg.fr>
  79
  80         * s390-mkopc.c (main): Exit with error 1 if sscanf fails
  81         to parse all 6 parameters.
  82
  83 2010-09-28  Pierre Muller  <muller@ics.u-strasbg.fr>
  84
  85         * s390-mkopc.c (main): Change description array size to 80.
  86         Add maximum length of 79 to description parsing.
  87
  88 2010-09-27  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
  89
  90         * configure: Regenerate.
  91
  92 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  93
  94         * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
  95         (main): Recognize the new CPU string.
  96         * s390-opc.c: Add new instruction formats and masks.
  97         * s390-opc.txt: Add new z196 instructions.
  98
  99 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 100
 101         * s390-dis.c (print_insn_s390): Pick instruction with most
 102         specific mask.
 103         * s390-opc.c: Add unused bits to the insn mask.
 104         * s390-opc.txt: Reorder some instructions to prefer more recent
 105         versions.
 106
 107 2010-09-27  Tejas Belagod  <tejas.belagod@arm.com>
 108
 109         * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
 110         correction to unaligned PCs while printing comment.
 111
 112 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 113
 114         * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
 115         (thumb32_opcodes): Likewise.
 116         (banked_regname): New function.
 117         (print_insn_arm): Add Virtualization Extensions support.
 118         (print_insn_thumb32): Likewise.
 119
 120 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 121
 122         * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
 123         ARM state.
 124
 125 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 126
 127         * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
 128         (thumb32_opcodes): Likewise.
 129
 130 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 131
 132         * arm-dis.c (arm_opcodes): Add support for pldw.
 133         (thumb32_opcodes): Likewise.
 134
 135 2010-09-22  Robin Getz  <robin.getz@analog.com>
 136
 137         * bfin-dis.c (fmtconst): Cast address to 32bits.
 138
 139 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 140
 141         * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
 142
 143 2010-09-22  Robin Getz  <robin.getz@analog.com>
 144
 145         * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
 146         Reject P6/P7 to TESTSET.
 147         (decode_PushPopReg_0): Check for parallel insns.  Reject pushing
 148         SP onto the stack.
 149         (decode_PushPopMultiple_0): Check for parallel insns.  Make sure
 150         P/D fields match all the time.
 151         (decode_CCflag_0): Check for parallel insns.  Verify x/y fields
 152         are 0 for accumulator compares.
 153         (decode_CC2stat_0): Check for parallel insns.  Reject CC<op>CC.
 154         (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
 155         decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
 156         decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 157         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 158         decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
 159         insns.
 160         (decode_dagMODim_0): Verify br field for IREG ops.
 161         (decode_LDST_0): Reject preg load into same preg.
 162         (_print_insn_bfin): Handle returns for ILLEGAL decodes.
 163         (print_insn_bfin): Likewise.
 164
 165 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 166
 167         * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
 168
 169 2010-09-22  Robin Getz  <robin.getz@analog.com>
 170
 171         * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
 172
 173 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 174
 175         * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
 176
 177 2010-09-22  Robin Getz  <robin.getz@analog.com>
 178
 179         * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
 180         register values greater than 8.
 181         (IS_RESERVEDREG, allreg, mostreg): New helpers.
 182         (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
 183         (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
 184         (decode_CC2dreg_0): Check valid CC register number.
 185
 186 2010-09-22  Robin Getz  <robin.getz@analog.com>
 187
 188         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
 189
 190 2010-09-22  Robin Getz  <robin.getz@analog.com>
 191
 192         * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
 193         (reg_names): Likewise.
 194         (decode_statbits): Likewise; while reformatting to make manageable.
 195
 196 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 197
 198         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
 199         (decode_pseudoOChar_0): New function.
 200         (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
 201
 202 2010-09-22  Robin Getz  <robin.getz@analog.com>
 203
 204         * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
 205         LSHIFT instead of SHIFT.
 206
 207 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 208
 209         * bfin-dis.c (constant_formats): Constify the whole structure.
 210         (fmtconst): Add const to return value.
 211         (reg_names): Mark const.
 212         (decode_multfunc): Mark s0/s1 as const.
 213         (decode_macfunc): Mark a/sop as const.
 214
 215 2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
 216
 217         * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
 218
 219 2010-09-14  Maciej W. Rozycki  <macro@codesourcery.com>
 220
 221         * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
 222         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
 223
 224 2010-09-10  Pierre Muller  <muller@ics.u-strasbg.fr>
 225
 226         * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
 227         dlx_insn_type array.
 228
 229 2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>
 230
 231         PR binutils/11960
 232         * i386-dis.c (sIv): New.
 233         (dis386): Replace Iq with sIv on "pushT".
 234         (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
 235         (x86_64_table): Replace {T|}/{P|} with P.
 236         (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
 237         (OP_sI): Update v_mode.  Remove w_mode.
 238
 239 2010-08-27  Nathan Froyd  <froydnj@codesourcery.com>
 240
 241         * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
 242         on E500 and E500MC.
 243
 244 2010-08-17  H.J. Lu  <hongjiu.lu@intel.com>
 245
 246         * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
 247         prefetchw.
 248
 249 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 250
 251         * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
 252         to processor flags for PENTIUMPRO processors and later.
 253         * i386-opc.h (enum): Add CpuNop.
 254         (i386_cpu_flags): Add cpunop bit.
 255         * i386-opc.tbl: Change nop cpu_flags.
 256         * i386-init.h: Regenerated.
 257         * i386-tbl.h: Likewise.
 258
 259 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 260
 261         * i386-opc.h (enum): Fix typos in comments.
 262
 263 2010-08-06  Alan Modra  <amodra@gmail.com>
 264
 265         * disassemble.c: Formatting.
 266         (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
 267
 268 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 269
 270         * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
 271         * i386-tbl.h: Regenerated.
 272
 273 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 274
 275         * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
 276
 277         * i386-opc.tbl: Add ud1.  Remove Cpu686 from ud2/ud2a/ud2b.
 278         * i386-tbl.h: Regenerated.
 279
 280 2010-07-29  DJ Delorie  <dj@redhat.com>
 281
 282         * rx-decode.opc (SRR): New.
 283         (rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
 284         r0,r0) and NOP3 (max r0,r0) special cases.
 285         * rx-decode.c: Regenerate.
 286
 287 2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>
 288
 289         * i386-dis.c: Add 0F to VEX opcode enums.
 290
 291 2010-07-27  DJ Delorie  <dj@redhat.com>
 292
 293         * rx-decode.opc (store_flags): Remove, replace with F_* macros.
 294         (rx_decode_opcode): Likewise.
 295         * rx-decode.c: Regenerate.
 296
 297 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 298             Ina Pandit  <ina.pandit@kpitcummins.com>
 299
 300         * v850-dis.c (v850_sreg_names): Updated structure for system
 301         registers.
 302         (float_cc_names): new structure for condition codes.
 303         (print_value): Update the function that prints value.
 304         (get_operand_value): New function to get the operand value.
 305         (disassemble): Updated to handle the disassembly of instructions.
 306         (print_insn_v850): Updated function to print instruction for different
 307         families.
 308         * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
 309         extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
 310         extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
 311         insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
 312         extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
 313         extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
 314         extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
 315         insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
 316         (insert_d8_7, insert_d5_4, insert_i5div): Remove.
 317         (v850_operands): Update with the relocation name. Also update
 318         the instructions with specific set of processors.
 319
 320 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
 321
 322         * arm-dis.c (print_insn_arm): Add cases for printing more
 323         symbolic operands.
 324         (print_insn_thumb32): Likewise.
 325
 326 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 327
 328         * mips-dis.c (print_insn_mips): Correct branch instruction type
 329         determination.
 330
 331 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 332
 333         * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
 334         type and delay slot determination.
 335         (print_insn_mips16): Extend branch instruction type and delay
 336         slot determination to cover all instructions.
 337         * mips16-opc.c (BR): Remove macro.
 338         (UBR, CBR): New macros.
 339         (mips16_opcodes): Update branch annotation for "b", "beqz",
 340         "bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
 341         and "jrc".
 342
 343 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 344
 345         AVX Programming Reference (June, 2010)
 346         * i386-dis.c (mod_table): Replace rdrnd with rdrand.
 347         * i386-opc.tbl: Likewise.
 348         * i386-tbl.h: Regenerated.
 349
 350 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 351
 352         * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
 353
 354 2010-07-03  Andreas Schwab  <schwab@linux-m68k.org>
 355
 356         * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
 357         ppc_cpu_t before inverting.
 358         (ppc_parse_cpu): Likewise.
 359         (print_insn_powerpc): Likewise.
 360
 361 2010-07-03  Alan Modra  <amodra@gmail.com>
 362
 363         * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
 364         * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
 365         (PPC64, MFDEC2): Update.
 366         (NON32, NO371): Define.
 367         (powerpc_opcode): Update to not use old opcode flags, and avoid
 368         -m601 duplicates.
 369
 370 2010-07-03  DJ Delorie  <dj@delorie.com>
 371
 372         * m32c-ibld.c: Regenerate.
 373
 374 2010-07-03  Alan Modra  <amodra@gmail.com>
 375
 376         * ppc-opc.c (PWR2COM): Define.
 377         (PPCPWR2): Add PPC_OPCODE_COMMON.
 378         (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
 379         "fcirz", "fcirz." to -mcom opcodes.  Remove "mfsri", "dclst",
 380         "rac" from -mcom.
 381
 382 2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>
 383
 384         AVX Programming Reference (June, 2010)
 385         * i386-dis.c (PREFIX_0FAE_REG_0): New.
 386         (PREFIX_0FAE_REG_1): Likewise.
 387         (PREFIX_0FAE_REG_2): Likewise.
 388         (PREFIX_0FAE_REG_3): Likewise.
 389         (PREFIX_VEX_3813): Likewise.
 390         (PREFIX_VEX_3A1D): Likewise.
 391         (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 392         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
 393         PREFIX_VEX_3A1D.
 394         (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
 395         (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 396         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
 397
 398         * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
 399         CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
 400         (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
 401
 402         * i386-opc.h (CpuXsaveopt): New.
 403         (CpuFSGSBase): Likewise.
 404         (CpuRdRnd): Likewise.
 405         (CpuF16C): Likewise.
 406         (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
 407         cpuf16c.
 408
 409         * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
 410         wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 411         * i386-init.h: Regenerated.
 412         * i386-tbl.h: Likewise.
 413
 414 2010-07-01  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 415
 416         * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
 417         and mtocrf on EFS.
 418
 419 2010-06-29  Alan Modra  <amodra@gmail.com>
 420
 421         * maxq-dis.c: Delete file.
 422         * Makefile.am: Remove references to maxq.
 423         * configure.in: Likewise.
 424         * disassemble.c: Likewise.
 425         * Makefile.in: Regenerate.
 426         * configure: Regenerate.
 427         * po/POTFILES.in: Regenerate.
 428
 429 2010-06-29  Alan Modra  <amodra@gmail.com>
 430
 431         * mep-dis.c: Regenerate.
 432
 433 2010-06-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 434
 435         * arm-disc.c (parse_insn_neon):  Fix Neon alignment syntax.
 436
 437 2010-06-27  Alan Modra  <amodra@gmail.com>
 438
 439         * arc-dis.c (arc_sprintf): Delete set but unused variables.
 440         (decodeInstr): Likewise.
 441         * dlx-dis.c (print_insn_dlx): Likewise.
 442         * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
 443         * maxq-dis.c (check_move, print_insn): Likewise.
 444         * mep-dis.c (mep_examine_ivc2_insns): Likewise.
 445         * msp430-dis.c (msp430_branchinstr): Likewise.
 446         * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
 447         * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
 448         * sparc-dis.c (print_insn_sparc): Likewise.
 449         * fr30-asm.c: Regenerate.
 450         * frv-asm.c: Regenerate.
 451         * ip2k-asm.c: Regenerate.
 452         * iq2000-asm.c: Regenerate.
 453         * lm32-asm.c: Regenerate.
 454         * m32c-asm.c: Regenerate.
 455         * m32r-asm.c: Regenerate.
 456         * mep-asm.c: Regenerate.
 457         * mt-asm.c: Regenerate.
 458         * openrisc-asm.c: Regenerate.
 459         * xc16x-asm.c: Regenerate.
 460         * xstormy16-asm.c: Regenerate.
 461
 462 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 463
 464         PR gas/11673
 465         * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
 466
 467 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 468
 469         PR binutils/11676
 470         * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
 471
 472 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 473
 474         * ppc-dis.c (ppc_opts):  Remove PPC_OPCODE_E500MC from e500 and
 475         e500x2.  Add PPC_OPCODE_E500 to e500 and e500x2
 476         * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
 477         touch floating point regs and are enabled by COM, PPC or PPCCOM.
 478         Treat sync as msync on e500.  Treat eieio as mbar 1 on e500.
 479         Treat lwsync as msync on e500.
 480
 481 2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 482
 483         * arm-dis.c (thumb-opcodes): Add disassembly for movs.
 484
 485 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 486
 487         * arm-dis.c (print_insn_neon):  Ensure disassembly of Neon
 488         constants is the same on 32-bit and 64-bit hosts.
 489
 490 2010-05-27  Jason Duerstock  <jason.duerstock+binutils@gmail.com>
 491
 492         * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
 493         .short directives so that they can be reassembled.
 494
 495 2010-05-26  Catherine Moore <clm@codesourcery.com>
 496             David Ung  <davidu@mips.com>
 497
 498         * mips-opc.c: Change membership to I1 for instructions ssnop and
 499         ehb.
 500
 501 2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>
 502
 503         * i386-dis.c (sib): New.
 504         (get_sib): Likewise.
 505         (print_insn): Call get_sib.
 506         OP_E_memory): Use sib.
 507
 508 2010-05-26  Catherine Moore  <clm@codesoourcery.com>
 509
 510         * mips-dis.c (mips_arch): Remove INSN_MIPS16.
 511         * mips-opc.c (I16): Remove.
 512         (mips_builtin_op): Reclassify jalx.
 513
 514 2010-05-19  Alan Modra  <amodra@gmail.com>
 515
 516         * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
 517         divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
 518
 519 2010-05-13  Alan Modra  <amodra@gmail.com>
 520
 521         * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
 522
 523 2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 524
 525         * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
 526         format.
 527         (print_insn_thumb16): Add support for new %W format.
 528
 529 2010-05-07  Tristan Gingold  <gingold@adacore.com>
 530
 531         * Makefile.in: Regenerate with automake 1.11.1.
 532         * aclocal.m4: Ditto.
 533
 534 2010-05-05  Nick Clifton  <nickc@redhat.com>
 535
 536         * po/es.po: Updated Spanish translation.
 537
 538 2010-04-22  Nick Clifton  <nickc@redhat.com>
 539
 540         * po/opcodes.pot: Updated by the Translation project.
 541         * po/vi.po: Updated Vietnamese translation.
 542
 543 2010-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 544
 545         * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
 546         bits in opcode.
 547
 548 2010-04-09  Nick Clifton  <nickc@redhat.com>
 549
 550         * i386-dis.c (print_insn): Remove unused variable op.
 551         (OP_sI): Remove unused variable mask.
 552
 553 2010-04-07  Alan Modra  <amodra@gmail.com>
 554
 555         * configure: Regenerate.
 556
 557 2010-04-06  Peter Bergner  <bergner@vnet.ibm.com>
 558
 559         * ppc-opc.c (RBOPT): New define.
 560         ("dccci"): Enable for PPCA2.  Make operands optional.
 561         ("iccci"): Likewise.  Do not deprecate for PPC476.
 562
 563 2010-04-02  Masaki Muranaka  <monaka@monami-software.com>
 564
 565         * cr16-opc.c (cr16_instruction): Fix typo in comment.
 566
 567 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 568
 569         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
 570         * Makefile.in: Regenerate.
 571         * configure.in (bfd_tic6x_arch): New.
 572         * configure: Regenerate.
 573         * disassemble.c (ARCH_tic6x): Define if ARCH_all.
 574         (disassembler): Handle TI C6X.
 575         * tic6x-dis.c: New.
 576
 577 2010-03-24  Mike Frysinger  <vapier@gentoo.org>
 578
 579         * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
 580
 581 2010-03-23  Joseph Myers  <joseph@codesourcery.com>
 582
 583         * dis-buf.c (buffer_read_memory): Give error for reading just
 584         before the start of memory.
 585
 586 2010-03-22  Sebastian Pop  <sebastian.pop@amd.com>
 587             Quentin Neill <quentin.neill@amd.com>
 588
 589         * i386-dis.c (OP_LWP_I): Removed.
 590         (reg_table): Do not use OP_LWP_I, use Iq.
 591         (OP_LWPCB_E): Remove use of names16.
 592         (OP_LWP_E): Same.
 593         * i386-opc.tbl: Removed 16bit LWP insns.  32bit LWP insns
 594         should not set the Vex.length bit.
 595         * i386-tbl.h: Regenerated.
 596
 597 2010-02-25  Edmar Wienskoski  <edmar@freescale.com>
 598
 599         * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
 600
 601 2010-02-24  Nick Clifton  <nickc@redhat.com>
 602
 603         PR binutils/6773
 604         * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
 605         <prefix>asx.  Replace <prefix>subaddx with <prefix>sax.
 606         (thumb32_opcodes): Likewise.
 607
 608 2010-02-15  Nick Clifton  <nickc@redhat.com>
 609
 610         * po/vi.po: Updated Vietnamese translation.
 611
 612 2010-02-12  Doug Evans  <dje@sebabeach.org>
 613
 614         * lm32-opinst.c: Regenerate.
 615
 616 2010-02-11  Doug Evans  <dje@sebabeach.org>
 617
 618         * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
 619         (print_address): Delete CGEN_PRINT_ADDRESS.
 620         * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
 621         * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
 622         * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
 623         * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
 624
 625         * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
 626         * frv-desc.c, * frv-desc.h, * frv-opc.c,
 627         * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
 628         * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
 629         * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
 630         * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
 631         * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
 632         * mep-desc.c, * mep-desc.h, * mep-opc.c,
 633         * mt-desc.c, * mt-desc.h, * mt-opc.c,
 634         * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
 635         * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
 636         * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
 637
 638 2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 639
 640         * i386-dis.c: Update copyright.
 641         * i386-gen.c: Likewise.
 642         * i386-opc.h: Likewise.
 643         * i386-opc.tbl: Likewise.
 644
 645 2010-02-10  Quentin Neill  <quentin.neill@amd.com>
 646             Sebastian Pop  <sebastian.pop@amd.com>
 647
 648         * i386-dis.c (OP_EX_VexImmW): Reintroduced
 649         function to handle 5th imm8 operand.
 650         (PREFIX_VEX_3A48): Added.
 651         (PREFIX_VEX_3A49): Added.
 652         (VEX_W_3A48_P_2): Added.
 653         (VEX_W_3A49_P_2): Added.
 654         (prefix table): Added entries for PREFIX_VEX_3A48
 655         and PREFIX_VEX_3A49.
 656         (vex table): Added entries for VEX_W_3A48_P_2 and
 657         and VEX_W_3A49_P_2.
 658         * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
 659         for Vec_Imm4 operands.
 660         * i386-opc.h (enum): Added Vec_Imm4.
 661         (i386_operand_type): Added vec_imm4.
 662         * i386-opc.tbl: Add entries for vpermilp[ds].
 663         * i386-init.h: Regenerated.
 664         * i386-tbl.h: Regenerated.
 665
 666 2010-02-10  Richard Sandiford  <r.sandiford@uk.ibm.com>
 667
 668         * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
 669         and "pwr7".  Move "a2" into alphabetical order.
 670
 671 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 672
 673         * ppc-dis.c (ppc_opts): Add titan entry.
 674         * ppc-opc.c (TITAN, MULHW): Define.
 675         (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
 676
 677 2010-02-03  Quentin Neill  <quentin.neill@amd.com>
 678
 679         * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
 680         to CPU_BDVER1_FLAGS
 681         * i386-init.h: Regenerated.
 682
 683 2010-02-03  Anthony Green  <green@moxielogic.com>
 684
 685         * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
 686         0x0f, and make 0x00 an illegal instruction.
 687
 688 2010-01-29  Daniel Jacobowitz  <dan@codesourcery.com>
 689
 690         * opcodes/arm-dis.c (struct arm_private_data): New.
 691         (print_insn_coprocessor, print_insn_arm): Update to use struct
 692         arm_private_data.
 693         (is_mapping_symbol, get_map_sym_type): New functions.
 694         (get_sym_code_type): Check the symbol's section.  Do not check
 695         mapping symbols.
 696         (print_insn): Default to disassembling ARM mode code.  Check
 697         for mapping symbols separately from other symbols.  Use
 698         struct arm_private_data.
 699
 700 2010-01-28  H.J. Lu  <hongjiu.lu@intel.com>
 701
 702         * i386-dis.c (EXVexWdqScalar): New.
 703         (vex_scalar_w_dq_mode): Likewise.
 704         (prefix_table): Update entries for PREFIX_VEX_3899,
 705         PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
 706         PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
 707         PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
 708         PREFIX_VEX_38BD and PREFIX_VEX_38BF.
 709         (intel_operand_size): Handle vex_scalar_w_dq_mode.
 710         (OP_EX): Likewise.
 711
 712 2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 713
 714         * i386-dis.c (XMScalar): New.
 715         (EXdScalar): Likewise.
 716         (EXqScalar): Likewise.
 717         (EXqScalarS): Likewise.
 718         (VexScalar): Likewise.
 719         (EXdVexScalarS): Likewise.
 720         (EXqVexScalarS): Likewise.
 721         (XMVexScalar): Likewise.
 722         (scalar_mode): Likewise.
 723         (d_scalar_mode): Likewise.
 724         (d_scalar_swap_mode): Likewise.
 725         (q_scalar_mode): Likewise.
 726         (q_scalar_swap_mode): Likewise.
 727         (vex_scalar_mode): Likewise.
 728         (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
 729         VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
 730         VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
 731         VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
 732         VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
 733         VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
 734         VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
 735         VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
 736         VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
 737         VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
 738         (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
 739         VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
 740         VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
 741         VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
 742         VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
 743         VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
 744         VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
 745         VEX_W_7E_P_1, VEX_W_D6_P_2  VEX_W_C2_P_1, VEX_W_C2_P_3,
 746         VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
 747         (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
 748         q_scalar_mode, q_scalar_swap_mode.
 749         (OP_XMM): Handle scalar_mode.
 750         (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
 751         and q_scalar_swap_mode.
 752         (OP_VEX): Handle vex_scalar_mode.
 753
 754 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 755
 756         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 757
 758 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 759
 760         * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
 761
 762 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 763
 764         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 765
 766 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 767
 768         * i386-dis.c (Bad_Opcode): New.
 769         (bad_opcode): Likewise.
 770         (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
 771         (dis386_twobyte): Likewise.
 772         (reg_table): Likewise.
 773         (prefix_table): Likewise.
 774         (x86_64_table): Likewise.
 775         (vex_len_table): Likewise.
 776         (vex_w_table): Likewise.
 777         (mod_table): Likewise.
 778         (rm_table): Likewise.
 779         (float_reg): Likewise.
 780         (reg_table): Remove trailing "(bad)" entries.
 781         (prefix_table): Likewise.
 782         (x86_64_table): Likewise.
 783         (vex_len_table): Likewise.
 784         (vex_w_table): Likewise.
 785         (mod_table): Likewise.
 786         (rm_table): Likewise.
 787         (get_valid_dis386): Handle bytemode 0.
 788
 789 2010-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 790
 791         * i386-opc.h (VEXScalar): New.
 792
 793         * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
 794         instructions.
 795         * i386-tbl.h: Regenerated.
 796
 797 2010-01-21  H.J. Lu  <hongjiu.lu@intel.com>
 798
 799         * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
 800
 801         * i386-opc.tbl: Add xsave64 and xrstor64.
 802         * i386-tbl.h: Regenerated.
 803
 804 2010-01-20  Nick Clifton  <nickc@redhat.com>
 805
 806         PR 11170
 807         * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
 808         based post-indexed addressing.
 809
 810 2010-01-15  Sebastian Pop  <sebastian.pop@amd.com>
 811
 812         * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
 813         * i386-tbl.h: Regenerated.
 814
 815 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 816
 817         * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
 818         comments.
 819
 820 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 821
 822         * i386-dis.c (names_mm): New.
 823         (intel_names_mm): Likewise.
 824         (att_names_mm): Likewise.
 825         (names_xmm): Likewise.
 826         (intel_names_xmm): Likewise.
 827         (att_names_xmm): Likewise.
 828         (names_ymm): Likewise.
 829         (intel_names_ymm): Likewise.
 830         (att_names_ymm): Likewise.
 831         (print_insn): Set names_mm, names_xmm and names_ymm.
 832         (OP_MMX): Use names_mm, names_xmm and names_ymm.
 833         (OP_XMM): Likewise.
 834         (OP_EM): Likewise.
 835         (OP_EMC): Likewise.
 836         (OP_MXC): Likewise.
 837         (OP_EX): Likewise.
 838         (XMM_Fixup): Likewise.
 839         (OP_VEX): Likewise.
 840         (OP_EX_VexReg): Likewise.
 841         (OP_Vex_2src): Likewise.
 842         (OP_Vex_2src_1): Likewise.
 843         (OP_Vex_2src_2): Likewise.
 844         (OP_REG_VexI4): Likewise.
 845
 846 2010-01-13  H.J. Lu  <hongjiu.lu@intel.com>
 847
 848         * i386-dis.c (print_insn): Update comments.
 849
 850 2010-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 851
 852         * i386-dis.c (rex_original): Removed.
 853         (ckprefix): Remove rex_original.
 854         (print_insn): Update comments.
 855
 856 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 857
 858         * Makefile.in: Regenerate.
 859         * configure: Regenerate.
 860
 861 2010-01-07  Doug Evans  <dje@sebabeach.org>
 862
 863         * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
 864         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 865         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 866         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 867         * xstormy16-ibld.c: Regenerate.
 868
 869 2010-01-06  Quentin Neill  <quentin.neill@amd.com>
 870
 871         * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
 872         * i386-init.h: Regenerated.
 873
 874 2010-01-06  Daniel Gutson  <dgutson@codesourcery.com>
 875
 876         * arm-dis.c (print_insn): Fixed search for next symbol and data
 877         dumping condition, and the initial mapping symbol state.
 878
 879 2010-01-05  Doug Evans  <dje@sebabeach.org>
 880
 881         * cgen-ibld.in: #include "cgen/basic-modes.h".
 882         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 883         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 884         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 885         * xstormy16-ibld.c: Regenerate.
 886
 887 2010-01-04  Nick Clifton  <nickc@redhat.com>
 888
 889         PR 11123
 890         * arm-dis.c (print_insn_coprocessor): Initialise value.
 891
 892 2010-01-04  Edmar Wienskoski  <edmar@freescale.com>
 893
 894         * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
 895
 896 2010-01-02  Doug Evans  <dje@sebabeach.org>
 897
 898         * cgen-asm.in: Update copyright year.
 899         * cgen-dis.in: Update copyright year.
 900         * cgen-ibld.in: Update copyright year.
 901         * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
 902         * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
 903         * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
 904         * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
 905         * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
 906         * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
 907         * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
 908         * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
 909         * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
 910         * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
 911         * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
 912         * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
 913         * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
 914         * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
 915         * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
 916         * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
 917         * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
 918         * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
 919         * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
 920         * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
 921         * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
 922
 923 For older changes see ChangeLog-2009
 924 \f
 925 Local Variables:
 926 mode: change-log
 927 left-margin: 8
 928 fill-column: 74
 929 version-control: never
 930 End: