opcodes/ChangeLog

   1 2010-09-30  Pierre Muller  <muller@ics.u-strasbg.fr>
   2
   3         * s390-mkopc.c (main): Exit with error 1 if sscanf fails
   4         to parse all 6 parameters.
   5
   6 2010-09-28  Pierre Muller  <muller@ics.u-strasbg.fr>
   7
   8         * s390-mkopc.c (main): Change description array size to 80.
   9         Add maximum length of 79 to description parsing.
  10
  11 2010-09-27  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
  12
  13         * configure: Regenerate.
  14
  15 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  16
  17         * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
  18         (main): Recognize the new CPU string.
  19         * s390-opc.c: Add new instruction formats and masks.
  20         * s390-opc.txt: Add new z196 instructions.
  21
  22 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  23
  24         * s390-dis.c (print_insn_s390): Pick instruction with most
  25         specific mask.
  26         * s390-opc.c: Add unused bits to the insn mask.
  27         * s390-opc.txt: Reorder some instructions to prefer more recent
  28         versions.
  29
  30 2010-09-27  Tejas Belagod  <tejas.belagod@arm.com>
  31
  32         * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
  33         correction to unaligned PCs while printing comment.
  34
  35 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  36
  37         * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
  38         (thumb32_opcodes): Likewise.
  39         (banked_regname): New function.
  40         (print_insn_arm): Add Virtualization Extensions support.
  41         (print_insn_thumb32): Likewise.
  42
  43 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  44
  45         * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
  46         ARM state.
  47
  48 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  49
  50         * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
  51         (thumb32_opcodes): Likewise.
  52
  53 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  54
  55         * arm-dis.c (arm_opcodes): Add support for pldw.
  56         (thumb32_opcodes): Likewise.
  57
  58 2010-09-22  Robin Getz  <robin.getz@analog.com>
  59
  60         * bfin-dis.c (fmtconst): Cast address to 32bits.
  61
  62 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  63
  64         * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
  65
  66 2010-09-22  Robin Getz  <robin.getz@analog.com>
  67
  68         * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
  69         Reject P6/P7 to TESTSET.
  70         (decode_PushPopReg_0): Check for parallel insns.  Reject pushing
  71         SP onto the stack.
  72         (decode_PushPopMultiple_0): Check for parallel insns.  Make sure
  73         P/D fields match all the time.
  74         (decode_CCflag_0): Check for parallel insns.  Verify x/y fields
  75         are 0 for accumulator compares.
  76         (decode_CC2stat_0): Check for parallel insns.  Reject CC<op>CC.
  77         (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
  78         decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
  79         decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
  80         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
  81         decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
  82         insns.
  83         (decode_dagMODim_0): Verify br field for IREG ops.
  84         (decode_LDST_0): Reject preg load into same preg.
  85         (_print_insn_bfin): Handle returns for ILLEGAL decodes.
  86         (print_insn_bfin): Likewise.
  87
  88 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  89
  90         * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
  91
  92 2010-09-22  Robin Getz  <robin.getz@analog.com>
  93
  94         * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
  95
  96 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  97
  98         * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
  99
 100 2010-09-22  Robin Getz  <robin.getz@analog.com>
 101
 102         * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
 103         register values greater than 8.
 104         (IS_RESERVEDREG, allreg, mostreg): New helpers.
 105         (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
 106         (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
 107         (decode_CC2dreg_0): Check valid CC register number.
 108
 109 2010-09-22  Robin Getz  <robin.getz@analog.com>
 110
 111         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
 112
 113 2010-09-22  Robin Getz  <robin.getz@analog.com>
 114
 115         * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
 116         (reg_names): Likewise.
 117         (decode_statbits): Likewise; while reformatting to make manageable.
 118
 119 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 120
 121         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
 122         (decode_pseudoOChar_0): New function.
 123         (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
 124
 125 2010-09-22  Robin Getz  <robin.getz@analog.com>
 126
 127         * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
 128         LSHIFT instead of SHIFT.
 129
 130 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 131
 132         * bfin-dis.c (constant_formats): Constify the whole structure.
 133         (fmtconst): Add const to return value.
 134         (reg_names): Mark const.
 135         (decode_multfunc): Mark s0/s1 as const.
 136         (decode_macfunc): Mark a/sop as const.
 137
 138 2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
 139
 140         * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
 141
 142 2010-09-14  Maciej W. Rozycki  <macro@codesourcery.com>
 143
 144         * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
 145         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
 146
 147 2010-09-10  Pierre Muller  <muller@ics.u-strasbg.fr>
 148
 149         * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
 150         dlx_insn_type array.
 151
 152 2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>
 153
 154         PR binutils/11960
 155         * i386-dis.c (sIv): New.
 156         (dis386): Replace Iq with sIv on "pushT".
 157         (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
 158         (x86_64_table): Replace {T|}/{P|} with P.
 159         (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
 160         (OP_sI): Update v_mode.  Remove w_mode.
 161
 162 2010-08-27  Nathan Froyd  <froydnj@codesourcery.com>
 163
 164         * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
 165         on E500 and E500MC.
 166
 167 2010-08-17  H.J. Lu  <hongjiu.lu@intel.com>
 168
 169         * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
 170         prefetchw.
 171
 172 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 173
 174         * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
 175         to processor flags for PENTIUMPRO processors and later.
 176         * i386-opc.h (enum): Add CpuNop.
 177         (i386_cpu_flags): Add cpunop bit.
 178         * i386-opc.tbl: Change nop cpu_flags.
 179         * i386-init.h: Regenerated.
 180         * i386-tbl.h: Likewise.
 181
 182 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 183
 184         * i386-opc.h (enum): Fix typos in comments.
 185
 186 2010-08-06  Alan Modra  <amodra@gmail.com>
 187
 188         * disassemble.c: Formatting.
 189         (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
 190
 191 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 192
 193         * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
 194         * i386-tbl.h: Regenerated.
 195
 196 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 197
 198         * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
 199
 200         * i386-opc.tbl: Add ud1.  Remove Cpu686 from ud2/ud2a/ud2b.
 201         * i386-tbl.h: Regenerated.
 202
 203 2010-07-29  DJ Delorie  <dj@redhat.com>
 204
 205         * rx-decode.opc (SRR): New.
 206         (rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
 207         r0,r0) and NOP3 (max r0,r0) special cases.
 208         * rx-decode.c: Regenerate.
 209
 210 2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>
 211
 212         * i386-dis.c: Add 0F to VEX opcode enums.
 213
 214 2010-07-27  DJ Delorie  <dj@redhat.com>
 215
 216         * rx-decode.opc (store_flags): Remove, replace with F_* macros.
 217         (rx_decode_opcode): Likewise.
 218         * rx-decode.c: Regenerate.
 219
 220 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 221             Ina Pandit  <ina.pandit@kpitcummins.com>
 222
 223         * v850-dis.c (v850_sreg_names): Updated structure for system
 224         registers.
 225         (float_cc_names): new structure for condition codes.
 226         (print_value): Update the function that prints value.
 227         (get_operand_value): New function to get the operand value.
 228         (disassemble): Updated to handle the disassembly of instructions.
 229         (print_insn_v850): Updated function to print instruction for different
 230         families.
 231         * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
 232         extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
 233         extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
 234         insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
 235         extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
 236         extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
 237         extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
 238         insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
 239         (insert_d8_7, insert_d5_4, insert_i5div): Remove.
 240         (v850_operands): Update with the relocation name. Also update
 241         the instructions with specific set of processors.
 242
 243 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
 244
 245         * arm-dis.c (print_insn_arm): Add cases for printing more
 246         symbolic operands.
 247         (print_insn_thumb32): Likewise.
 248
 249 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 250
 251         * mips-dis.c (print_insn_mips): Correct branch instruction type
 252         determination.
 253
 254 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 255
 256         * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
 257         type and delay slot determination.
 258         (print_insn_mips16): Extend branch instruction type and delay
 259         slot determination to cover all instructions.
 260         * mips16-opc.c (BR): Remove macro.
 261         (UBR, CBR): New macros.
 262         (mips16_opcodes): Update branch annotation for "b", "beqz",
 263         "bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
 264         and "jrc".
 265
 266 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 267
 268         AVX Programming Reference (June, 2010)
 269         * i386-dis.c (mod_table): Replace rdrnd with rdrand.
 270         * i386-opc.tbl: Likewise.
 271         * i386-tbl.h: Regenerated.
 272
 273 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 274
 275         * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
 276
 277 2010-07-03  Andreas Schwab  <schwab@linux-m68k.org>
 278
 279         * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
 280         ppc_cpu_t before inverting.
 281         (ppc_parse_cpu): Likewise.
 282         (print_insn_powerpc): Likewise.
 283
 284 2010-07-03  Alan Modra  <amodra@gmail.com>
 285
 286         * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
 287         * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
 288         (PPC64, MFDEC2): Update.
 289         (NON32, NO371): Define.
 290         (powerpc_opcode): Update to not use old opcode flags, and avoid
 291         -m601 duplicates.
 292
 293 2010-07-03  DJ Delorie  <dj@delorie.com>
 294
 295         * m32c-ibld.c: Regenerate.
 296
 297 2010-07-03  Alan Modra  <amodra@gmail.com>
 298
 299         * ppc-opc.c (PWR2COM): Define.
 300         (PPCPWR2): Add PPC_OPCODE_COMMON.
 301         (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
 302         "fcirz", "fcirz." to -mcom opcodes.  Remove "mfsri", "dclst",
 303         "rac" from -mcom.
 304
 305 2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>
 306
 307         AVX Programming Reference (June, 2010)
 308         * i386-dis.c (PREFIX_0FAE_REG_0): New.
 309         (PREFIX_0FAE_REG_1): Likewise.
 310         (PREFIX_0FAE_REG_2): Likewise.
 311         (PREFIX_0FAE_REG_3): Likewise.
 312         (PREFIX_VEX_3813): Likewise.
 313         (PREFIX_VEX_3A1D): Likewise.
 314         (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 315         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
 316         PREFIX_VEX_3A1D.
 317         (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
 318         (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 319         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
 320
 321         * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
 322         CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
 323         (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
 324
 325         * i386-opc.h (CpuXsaveopt): New.
 326         (CpuFSGSBase): Likewise.
 327         (CpuRdRnd): Likewise.
 328         (CpuF16C): Likewise.
 329         (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
 330         cpuf16c.
 331
 332         * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
 333         wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 334         * i386-init.h: Regenerated.
 335         * i386-tbl.h: Likewise.
 336
 337 2010-07-01  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 338
 339         * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
 340         and mtocrf on EFS.
 341
 342 2010-06-29  Alan Modra  <amodra@gmail.com>
 343
 344         * maxq-dis.c: Delete file.
 345         * Makefile.am: Remove references to maxq.
 346         * configure.in: Likewise.
 347         * disassemble.c: Likewise.
 348         * Makefile.in: Regenerate.
 349         * configure: Regenerate.
 350         * po/POTFILES.in: Regenerate.
 351
 352 2010-06-29  Alan Modra  <amodra@gmail.com>
 353
 354         * mep-dis.c: Regenerate.
 355
 356 2010-06-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 357
 358         * arm-disc.c (parse_insn_neon):  Fix Neon alignment syntax.
 359
 360 2010-06-27  Alan Modra  <amodra@gmail.com>
 361
 362         * arc-dis.c (arc_sprintf): Delete set but unused variables.
 363         (decodeInstr): Likewise.
 364         * dlx-dis.c (print_insn_dlx): Likewise.
 365         * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
 366         * maxq-dis.c (check_move, print_insn): Likewise.
 367         * mep-dis.c (mep_examine_ivc2_insns): Likewise.
 368         * msp430-dis.c (msp430_branchinstr): Likewise.
 369         * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
 370         * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
 371         * sparc-dis.c (print_insn_sparc): Likewise.
 372         * fr30-asm.c: Regenerate.
 373         * frv-asm.c: Regenerate.
 374         * ip2k-asm.c: Regenerate.
 375         * iq2000-asm.c: Regenerate.
 376         * lm32-asm.c: Regenerate.
 377         * m32c-asm.c: Regenerate.
 378         * m32r-asm.c: Regenerate.
 379         * mep-asm.c: Regenerate.
 380         * mt-asm.c: Regenerate.
 381         * openrisc-asm.c: Regenerate.
 382         * xc16x-asm.c: Regenerate.
 383         * xstormy16-asm.c: Regenerate.
 384
 385 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 386
 387         PR gas/11673
 388         * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
 389
 390 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 391
 392         PR binutils/11676
 393         * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
 394
 395 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 396
 397         * ppc-dis.c (ppc_opts):  Remove PPC_OPCODE_E500MC from e500 and
 398         e500x2.  Add PPC_OPCODE_E500 to e500 and e500x2
 399         * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
 400         touch floating point regs and are enabled by COM, PPC or PPCCOM.
 401         Treat sync as msync on e500.  Treat eieio as mbar 1 on e500.
 402         Treat lwsync as msync on e500.
 403
 404 2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 405
 406         * arm-dis.c (thumb-opcodes): Add disassembly for movs.
 407
 408 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 409
 410         * arm-dis.c (print_insn_neon):  Ensure disassembly of Neon
 411         constants is the same on 32-bit and 64-bit hosts.
 412
 413 2010-05-27  Jason Duerstock  <jason.duerstock+binutils@gmail.com>
 414
 415         * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
 416         .short directives so that they can be reassembled.
 417
 418 2010-05-26  Catherine Moore <clm@codesourcery.com>
 419             David Ung  <davidu@mips.com>
 420
 421         * mips-opc.c: Change membership to I1 for instructions ssnop and
 422         ehb.
 423
 424 2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>
 425
 426         * i386-dis.c (sib): New.
 427         (get_sib): Likewise.
 428         (print_insn): Call get_sib.
 429         OP_E_memory): Use sib.
 430
 431 2010-05-26  Catherine Moore  <clm@codesoourcery.com>
 432
 433         * mips-dis.c (mips_arch): Remove INSN_MIPS16.
 434         * mips-opc.c (I16): Remove.
 435         (mips_builtin_op): Reclassify jalx.
 436
 437 2010-05-19  Alan Modra  <amodra@gmail.com>
 438
 439         * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
 440         divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
 441
 442 2010-05-13  Alan Modra  <amodra@gmail.com>
 443
 444         * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
 445
 446 2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 447
 448         * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
 449         format.
 450         (print_insn_thumb16): Add support for new %W format.
 451
 452 2010-05-07  Tristan Gingold  <gingold@adacore.com>
 453
 454         * Makefile.in: Regenerate with automake 1.11.1.
 455         * aclocal.m4: Ditto.
 456
 457 2010-05-05  Nick Clifton  <nickc@redhat.com>
 458
 459         * po/es.po: Updated Spanish translation.
 460
 461 2010-04-22  Nick Clifton  <nickc@redhat.com>
 462
 463         * po/opcodes.pot: Updated by the Translation project.
 464         * po/vi.po: Updated Vietnamese translation.
 465
 466 2010-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 467
 468         * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
 469         bits in opcode.
 470
 471 2010-04-09  Nick Clifton  <nickc@redhat.com>
 472
 473         * i386-dis.c (print_insn): Remove unused variable op.
 474         (OP_sI): Remove unused variable mask.
 475
 476 2010-04-07  Alan Modra  <amodra@gmail.com>
 477
 478         * configure: Regenerate.
 479
 480 2010-04-06  Peter Bergner  <bergner@vnet.ibm.com>
 481
 482         * ppc-opc.c (RBOPT): New define.
 483         ("dccci"): Enable for PPCA2.  Make operands optional.
 484         ("iccci"): Likewise.  Do not deprecate for PPC476.
 485
 486 2010-04-02  Masaki Muranaka  <monaka@monami-software.com>
 487
 488         * cr16-opc.c (cr16_instruction): Fix typo in comment.
 489
 490 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 491
 492         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
 493         * Makefile.in: Regenerate.
 494         * configure.in (bfd_tic6x_arch): New.
 495         * configure: Regenerate.
 496         * disassemble.c (ARCH_tic6x): Define if ARCH_all.
 497         (disassembler): Handle TI C6X.
 498         * tic6x-dis.c: New.
 499
 500 2010-03-24  Mike Frysinger  <vapier@gentoo.org>
 501
 502         * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
 503
 504 2010-03-23  Joseph Myers  <joseph@codesourcery.com>
 505
 506         * dis-buf.c (buffer_read_memory): Give error for reading just
 507         before the start of memory.
 508
 509 2010-03-22  Sebastian Pop  <sebastian.pop@amd.com>
 510             Quentin Neill <quentin.neill@amd.com>
 511
 512         * i386-dis.c (OP_LWP_I): Removed.
 513         (reg_table): Do not use OP_LWP_I, use Iq.
 514         (OP_LWPCB_E): Remove use of names16.
 515         (OP_LWP_E): Same.
 516         * i386-opc.tbl: Removed 16bit LWP insns.  32bit LWP insns
 517         should not set the Vex.length bit.
 518         * i386-tbl.h: Regenerated.
 519
 520 2010-02-25  Edmar Wienskoski  <edmar@freescale.com>
 521
 522         * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
 523
 524 2010-02-24  Nick Clifton  <nickc@redhat.com>
 525
 526         PR binutils/6773
 527         * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
 528         <prefix>asx.  Replace <prefix>subaddx with <prefix>sax.
 529         (thumb32_opcodes): Likewise.
 530
 531 2010-02-15  Nick Clifton  <nickc@redhat.com>
 532
 533         * po/vi.po: Updated Vietnamese translation.
 534
 535 2010-02-12  Doug Evans  <dje@sebabeach.org>
 536
 537         * lm32-opinst.c: Regenerate.
 538
 539 2010-02-11  Doug Evans  <dje@sebabeach.org>
 540
 541         * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
 542         (print_address): Delete CGEN_PRINT_ADDRESS.
 543         * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
 544         * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
 545         * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
 546         * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
 547
 548         * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
 549         * frv-desc.c, * frv-desc.h, * frv-opc.c,
 550         * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
 551         * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
 552         * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
 553         * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
 554         * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
 555         * mep-desc.c, * mep-desc.h, * mep-opc.c,
 556         * mt-desc.c, * mt-desc.h, * mt-opc.c,
 557         * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
 558         * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
 559         * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
 560
 561 2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 562
 563         * i386-dis.c: Update copyright.
 564         * i386-gen.c: Likewise.
 565         * i386-opc.h: Likewise.
 566         * i386-opc.tbl: Likewise.
 567
 568 2010-02-10  Quentin Neill  <quentin.neill@amd.com>
 569             Sebastian Pop  <sebastian.pop@amd.com>
 570
 571         * i386-dis.c (OP_EX_VexImmW): Reintroduced
 572         function to handle 5th imm8 operand.
 573         (PREFIX_VEX_3A48): Added.
 574         (PREFIX_VEX_3A49): Added.
 575         (VEX_W_3A48_P_2): Added.
 576         (VEX_W_3A49_P_2): Added.
 577         (prefix table): Added entries for PREFIX_VEX_3A48
 578         and PREFIX_VEX_3A49.
 579         (vex table): Added entries for VEX_W_3A48_P_2 and
 580         and VEX_W_3A49_P_2.
 581         * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
 582         for Vec_Imm4 operands.
 583         * i386-opc.h (enum): Added Vec_Imm4.
 584         (i386_operand_type): Added vec_imm4.
 585         * i386-opc.tbl: Add entries for vpermilp[ds].
 586         * i386-init.h: Regenerated.
 587         * i386-tbl.h: Regenerated.
 588
 589 2010-02-10  Richard Sandiford  <r.sandiford@uk.ibm.com>
 590
 591         * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
 592         and "pwr7".  Move "a2" into alphabetical order.
 593
 594 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 595
 596         * ppc-dis.c (ppc_opts): Add titan entry.
 597         * ppc-opc.c (TITAN, MULHW): Define.
 598         (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
 599
 600 2010-02-03  Quentin Neill  <quentin.neill@amd.com>
 601
 602         * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
 603         to CPU_BDVER1_FLAGS
 604         * i386-init.h: Regenerated.
 605
 606 2010-02-03  Anthony Green  <green@moxielogic.com>
 607
 608         * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
 609         0x0f, and make 0x00 an illegal instruction.
 610
 611 2010-01-29  Daniel Jacobowitz  <dan@codesourcery.com>
 612
 613         * opcodes/arm-dis.c (struct arm_private_data): New.
 614         (print_insn_coprocessor, print_insn_arm): Update to use struct
 615         arm_private_data.
 616         (is_mapping_symbol, get_map_sym_type): New functions.
 617         (get_sym_code_type): Check the symbol's section.  Do not check
 618         mapping symbols.
 619         (print_insn): Default to disassembling ARM mode code.  Check
 620         for mapping symbols separately from other symbols.  Use
 621         struct arm_private_data.
 622
 623 2010-01-28  H.J. Lu  <hongjiu.lu@intel.com>
 624
 625         * i386-dis.c (EXVexWdqScalar): New.
 626         (vex_scalar_w_dq_mode): Likewise.
 627         (prefix_table): Update entries for PREFIX_VEX_3899,
 628         PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
 629         PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
 630         PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
 631         PREFIX_VEX_38BD and PREFIX_VEX_38BF.
 632         (intel_operand_size): Handle vex_scalar_w_dq_mode.
 633         (OP_EX): Likewise.
 634
 635 2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 636
 637         * i386-dis.c (XMScalar): New.
 638         (EXdScalar): Likewise.
 639         (EXqScalar): Likewise.
 640         (EXqScalarS): Likewise.
 641         (VexScalar): Likewise.
 642         (EXdVexScalarS): Likewise.
 643         (EXqVexScalarS): Likewise.
 644         (XMVexScalar): Likewise.
 645         (scalar_mode): Likewise.
 646         (d_scalar_mode): Likewise.
 647         (d_scalar_swap_mode): Likewise.
 648         (q_scalar_mode): Likewise.
 649         (q_scalar_swap_mode): Likewise.
 650         (vex_scalar_mode): Likewise.
 651         (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
 652         VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
 653         VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
 654         VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
 655         VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
 656         VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
 657         VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
 658         VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
 659         VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
 660         VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
 661         (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
 662         VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
 663         VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
 664         VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
 665         VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
 666         VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
 667         VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
 668         VEX_W_7E_P_1, VEX_W_D6_P_2  VEX_W_C2_P_1, VEX_W_C2_P_3,
 669         VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
 670         (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
 671         q_scalar_mode, q_scalar_swap_mode.
 672         (OP_XMM): Handle scalar_mode.
 673         (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
 674         and q_scalar_swap_mode.
 675         (OP_VEX): Handle vex_scalar_mode.
 676
 677 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 678
 679         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 680
 681 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 682
 683         * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
 684
 685 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 686
 687         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 688
 689 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 690
 691         * i386-dis.c (Bad_Opcode): New.
 692         (bad_opcode): Likewise.
 693         (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
 694         (dis386_twobyte): Likewise.
 695         (reg_table): Likewise.
 696         (prefix_table): Likewise.
 697         (x86_64_table): Likewise.
 698         (vex_len_table): Likewise.
 699         (vex_w_table): Likewise.
 700         (mod_table): Likewise.
 701         (rm_table): Likewise.
 702         (float_reg): Likewise.
 703         (reg_table): Remove trailing "(bad)" entries.
 704         (prefix_table): Likewise.
 705         (x86_64_table): Likewise.
 706         (vex_len_table): Likewise.
 707         (vex_w_table): Likewise.
 708         (mod_table): Likewise.
 709         (rm_table): Likewise.
 710         (get_valid_dis386): Handle bytemode 0.
 711
 712 2010-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 713
 714         * i386-opc.h (VEXScalar): New.
 715
 716         * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
 717         instructions.
 718         * i386-tbl.h: Regenerated.
 719
 720 2010-01-21  H.J. Lu  <hongjiu.lu@intel.com>
 721
 722         * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
 723
 724         * i386-opc.tbl: Add xsave64 and xrstor64.
 725         * i386-tbl.h: Regenerated.
 726
 727 2010-01-20  Nick Clifton  <nickc@redhat.com>
 728
 729         PR 11170
 730         * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
 731         based post-indexed addressing.
 732
 733 2010-01-15  Sebastian Pop  <sebastian.pop@amd.com>
 734
 735         * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
 736         * i386-tbl.h: Regenerated.
 737
 738 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 739
 740         * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
 741         comments.
 742
 743 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 744
 745         * i386-dis.c (names_mm): New.
 746         (intel_names_mm): Likewise.
 747         (att_names_mm): Likewise.
 748         (names_xmm): Likewise.
 749         (intel_names_xmm): Likewise.
 750         (att_names_xmm): Likewise.
 751         (names_ymm): Likewise.
 752         (intel_names_ymm): Likewise.
 753         (att_names_ymm): Likewise.
 754         (print_insn): Set names_mm, names_xmm and names_ymm.
 755         (OP_MMX): Use names_mm, names_xmm and names_ymm.
 756         (OP_XMM): Likewise.
 757         (OP_EM): Likewise.
 758         (OP_EMC): Likewise.
 759         (OP_MXC): Likewise.
 760         (OP_EX): Likewise.
 761         (XMM_Fixup): Likewise.
 762         (OP_VEX): Likewise.
 763         (OP_EX_VexReg): Likewise.
 764         (OP_Vex_2src): Likewise.
 765         (OP_Vex_2src_1): Likewise.
 766         (OP_Vex_2src_2): Likewise.
 767         (OP_REG_VexI4): Likewise.
 768
 769 2010-01-13  H.J. Lu  <hongjiu.lu@intel.com>
 770
 771         * i386-dis.c (print_insn): Update comments.
 772
 773 2010-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 774
 775         * i386-dis.c (rex_original): Removed.
 776         (ckprefix): Remove rex_original.
 777         (print_insn): Update comments.
 778
 779 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 780
 781         * Makefile.in: Regenerate.
 782         * configure: Regenerate.
 783
 784 2010-01-07  Doug Evans  <dje@sebabeach.org>
 785
 786         * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
 787         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 788         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 789         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 790         * xstormy16-ibld.c: Regenerate.
 791
 792 2010-01-06  Quentin Neill  <quentin.neill@amd.com>
 793
 794         * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
 795         * i386-init.h: Regenerated.
 796
 797 2010-01-06  Daniel Gutson  <dgutson@codesourcery.com>
 798
 799         * arm-dis.c (print_insn): Fixed search for next symbol and data
 800         dumping condition, and the initial mapping symbol state.
 801
 802 2010-01-05  Doug Evans  <dje@sebabeach.org>
 803
 804         * cgen-ibld.in: #include "cgen/basic-modes.h".
 805         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 806         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 807         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 808         * xstormy16-ibld.c: Regenerate.
 809
 810 2010-01-04  Nick Clifton  <nickc@redhat.com>
 811
 812         PR 11123
 813         * arm-dis.c (print_insn_coprocessor): Initialise value.
 814
 815 2010-01-04  Edmar Wienskoski  <edmar@freescale.com>
 816
 817         * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
 818
 819 2010-01-02  Doug Evans  <dje@sebabeach.org>
 820
 821         * cgen-asm.in: Update copyright year.
 822         * cgen-dis.in: Update copyright year.
 823         * cgen-ibld.in: Update copyright year.
 824         * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
 825         * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
 826         * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
 827         * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
 828         * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
 829         * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
 830         * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
 831         * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
 832         * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
 833         * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
 834         * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
 835         * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
 836         * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
 837         * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
 838         * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
 839         * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
 840         * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
 841         * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
 842         * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
 843         * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
 844         * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
 845
 846 For older changes see ChangeLog-2009
 847 \f
 848 Local Variables:
 849 mode: change-log
 850 left-margin: 8
 851 fill-column: 74
 852 version-control: never
 853 End: