opcodes/ChangeLog

   1 2017-11-09 Tamar Christina  <tamar.christina@arm.com>
   2
   3         * aarch64-tbl.h
   4         (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
   5         (aarch64_feature_sm4, aarch64_feature_sha3): New.
   6         (aarch64_feature_fp_16_v8_2): New.
   7         (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
   8         (V8_4_INSN, CRYPTO_V8_2_INSN): New.
   9         (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
  10
  11 2017-11-08  Tamar Christina  <tamar.christina@arm.com>
  12
  13         * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
  14         (aarch64_feature_sha2, aarch64_feature_aes): New.
  15         (SHA2, AES): New.
  16         (AES_INSN, SHA2_INSN): New.
  17         (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
  18         (sha1h, sha1su1, sha256su0, sha1c, sha1p,
  19          sha1m, sha1su0, sha256h, sha256h2, sha256su1):
  20         Change to SHA2_INS.
  21
  22 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
  23             Tamar Christina <tamar.christina@arm.com>
  24
  25         * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
  26         FP16 instructions, including vfmal.f16 and vfmsl.f16.
  27
  28 2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
  29
  30         * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
  31
  32 2017-11-07  Alan Modra  <amodra@gmail.com>
  33
  34         * opintl.h: Formatting, comment fixes.
  35         (gettext, ngettext): Redefine when ENABLE_NLS.
  36         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
  37         (_): Define using gettext.
  38         (textdomain, bindtextdomain): Use safer "do nothing".
  39
  40 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
  41
  42         * arc-dis.c (print_hex): New variable.
  43         (parse_option): Check for hex option.
  44         (print_insn_arc): Use hexadecimal representation for short
  45         immediate values when requested.
  46         (print_arc_disassembler_options): Add hex option to the list.
  47
  48 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
  49
  50         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
  51         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
  52         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
  53         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
  54         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
  55         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
  56         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
  57         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
  58         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
  59         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
  60         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
  61         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
  62         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
  63         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
  64         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
  65         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
  66         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
  67         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
  68         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
  69         Changed opcodes.
  70         (prealloc, prefetch*): Place them before ld instruction.
  71         * arc-opc.c (skip_this_opcode): Add ARITH class.
  72
  73 2017-10-25  Alan Modra  <amodra@gmail.com>
  74
  75         PR 22348
  76         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
  77         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
  78         (imm4flag, size_changed): Likewise.
  79         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
  80         (words, allWords, processing_argument_number): Likewise.
  81         (cst4flag, size_changed): Likewise.
  82         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
  83         (crx_cst4_maps): Rename from cst4_maps.
  84         (crx_no_op_insn): Rename from no_op_insn.
  85
  86 2017-10-24  Andrew Waterman  <andrew@sifive.com>
  87
  88         * riscv-opc.c (match_c_addi16sp) : New function.
  89         (match_c_addi4spn): New function.
  90         (match_c_lui): Don't allow 0-immediate encodings.
  91         (riscv_opcodes) <addi>: Use the above functions.
  92         <add>: Likewise.
  93         <c.addi4spn>: Likewise.
  94         <c.addi16sp>: Likewise.
  95
  96 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  97
  98         * i386-init.h: Regenerate
  99         * i386-tbl.h: Likewise
 100
 101 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 102
 103         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
 104         (enum): Add EVEX_W_0F3854_P_2.
 105         * i386-dis-evex.h (evex_table): Updated.
 106         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
 107         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 108         (cpu_flags): Add CpuAVX512_BITALG.
 109         * i386-opc.h (enum): Add CpuAVX512_BITALG.
 110         (i386_cpu_flags): Add cpuavx512_bitalg..
 111         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
 112         * i386-init.h: Regenerate.
 113         * i386-tbl.h: Likewise.
 114
 115 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 116
 117         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
 118         * i386-dis-evex.h (evex_table): Updated.
 119         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
 120         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 121         (cpu_flags): Add CpuAVX512_VNNI.
 122         * i386-opc.h (enum): Add CpuAVX512_VNNI.
 123         (i386_cpu_flags): Add cpuavx512_vnni.
 124         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
 125         * i386-init.h: Regenerate.
 126         * i386-tbl.h: Likewise.
 127
 128 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 129
 130         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 131         (enum): Remove VEX_LEN_0F3A44_P_2.
 132         (vex_len_table): Ditto.
 133         (enum): Remove VEX_W_0F3A44_P_2.
 134         (vew_w_table): Ditto.
 135         (prefix_table): Adjust instructions (see prefixes above).
 136         * i386-dis-evex.h (evex_table):
 137         Add new instructions (see prefixes above).
 138         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 139         (bitfield_cpu_flags): Ditto.
 140         * i386-opc.h (enum): Ditto.
 141         (i386_cpu_flags): Ditto.
 142         (CpuUnused): Comment out to avoid zero-width field problem.
 143         * i386-opc.tbl (vpclmulqdq): New instruction.
 144         * i386-init.h: Regenerate.
 145         * i386-tbl.h: Ditto.
 146
 147 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 148
 149         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 150         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 151         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 152         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 153         (vex_len_table): Ditto.
 154         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 155         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 156         (vew_w_table): Ditto.
 157         (prefix_table): Adjust instructions (see prefixes above).
 158         * i386-dis-evex.h (evex_table):
 159         Add new instructions (see prefixes above).
 160         * i386-gen.c (cpu_flag_init): Add VAES.
 161         (bitfield_cpu_flags): Ditto.
 162         * i386-opc.h (enum): Ditto.
 163         (i386_cpu_flags): Ditto.
 164         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 165         * i386-init.h: Regenerate.
 166         * i386-tbl.h: Ditto.
 167
 168 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 169
 170         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 171         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 172         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 173         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 174         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 175         (prefix_table): Updated (see prefixes above).
 176         (three_byte_table): Likewise.
 177         (vex_w_table): Likewise.
 178         * i386-dis-evex.h: Likewise.
 179         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 180         (cpu_flags): Add CpuGFNI.
 181         * i386-opc.h (enum): Add CpuGFNI.
 182         (i386_cpu_flags): Add cpugfni.
 183         * i386-opc.tbl: Add Intel GFNI instructions.
 184         * i386-init.h: Regenerate.
 185         * i386-tbl.h: Likewise.
 186
 187 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 188
 189         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 190         Define EXbScalar and EXwScalar for OP_EX.
 191         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 192         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 193         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 194         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 195         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 196         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 197         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 198         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 199         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 200         (OP_E_memory): Likewise.
 201         * i386-dis-evex.h: Updated.
 202         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 203         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 204         (cpu_flags): Add CpuAVX512_VBMI2.
 205         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 206         (i386_cpu_flags): Add cpuavx512_vbmi2.
 207         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 208         * i386-init.h: Regenerate.
 209         * i386-tbl.h: Likewise.
 210
 211 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 212
 213         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 214
 215 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 216
 217         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 218         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 219         K15. Add jmpix pattern.
 220
 221 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 222
 223         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 224
 225 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 226
 227         * s390-opc.c (INSTR_SI_RD): New macro.
 228         (INSTR_S_RD): Adjust example instruction.
 229         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 230         SI_RD.
 231
 232 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 233
 234         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 235         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 236         VLE multimple load/store instructions. Old e_ldm* variants are
 237         kept as aliases.
 238         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 239
 240 2017-09-27  Nick Clifton  <nickc@redhat.com>
 241
 242         PR 22179
 243         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 244         names for the fmv.x.s and fmv.s.x instructions respectively.
 245
 246 2017-09-26  do  <do@nerilex.org>
 247
 248         PR 22123
 249         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 250         be used on CPUs that have emacs support.
 251
 252 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 253
 254         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 255
 256 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 257
 258         * nds32-asm.c: Rename __BIT() to N32_BIT().
 259         * nds32-asm.h: Likewise.
 260         * nds32-dis.c: Likewise.
 261
 262 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 263
 264         * i386-dis.c (last_active_prefix): Removed.
 265         (ckprefix): Don't set last_active_prefix.
 266         (NOTRACK_Fixup): Don't check last_active_prefix.
 267
 268 2017-08-31  Nick Clifton  <nickc@redhat.com>
 269
 270         * po/fr.po: Updated French translation.
 271
 272 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 273
 274         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 275         fields.
 276
 277 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 278             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 279
 280         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 281         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 282         New entries efs2 and spe2.
 283         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 284         (SPE2_OPCD_SEGS): New macro.
 285         (spe2_opcd_indices): New.
 286         (disassemble_init_powerpc): Handle SPE2 opcodes.
 287         (lookup_spe2): New function.
 288         (print_insn_powerpc): call lookup_spe2.
 289         * ppc-opc.c (insert_evuimm1_ex0): New function.
 290         (extract_evuimm1_ex0): Likewise.
 291         (insert_evuimm_lt8): Likewise.
 292         (extract_evuimm_lt8): Likewise.
 293         (insert_off_spe2): Likewise.
 294         (extract_off_spe2): Likewise.
 295         (insert_Ddd): Likewise.
 296         (extract_Ddd): Likewise.
 297         (DD): New operand.
 298         (EVUIMM_LT8): Likewise.
 299         (EVUIMM_LT16): Adjust.
 300         (MMMM): New operand.
 301         (EVUIMM_1): Likewise.
 302         (EVUIMM_1_EX0): Likewise.
 303         (EVUIMM_2): Adjust.
 304         (NNN): New operand.
 305         (VX_OFF_SPE2): Likewise.
 306         (BBB): Likewise.
 307         (DDD): Likewise.
 308         (VX_MASK_DDD): New mask.
 309         (HH): New operand.
 310         (VX_RA_CONST): New macro.
 311         (VX_RA_CONST_MASK): Likewise.
 312         (VX_RB_CONST): Likewise.
 313         (VX_RB_CONST_MASK): Likewise.
 314         (VX_OFF_SPE2_MASK): Likewise.
 315         (VX_SPE_CRFD): Likewise.
 316         (VX_SPE_CRFD_MASK VX): Likewise.
 317         (VX_SPE2_CLR): Likewise.
 318         (VX_SPE2_CLR_MASK): Likewise.
 319         (VX_SPE2_SPLATB): Likewise.
 320         (VX_SPE2_SPLATB_MASK): Likewise.
 321         (VX_SPE2_OCTET): Likewise.
 322         (VX_SPE2_OCTET_MASK): Likewise.
 323         (VX_SPE2_DDHH): Likewise.
 324         (VX_SPE2_DDHH_MASK): Likewise.
 325         (VX_SPE2_HH): Likewise.
 326         (VX_SPE2_HH_MASK): Likewise.
 327         (VX_SPE2_EVMAR): Likewise.
 328         (VX_SPE2_EVMAR_MASK): Likewise.
 329         (PPCSPE2): Likewise.
 330         (PPCEFS2): Likewise.
 331         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 332         (powerpc_macros): Map old SPE instructions have new names
 333         with the same opcodes. Add SPE2 instructions which just are
 334         mapped to SPE2.
 335         (spe2_opcodes): Add SPE2 opcodes.
 336
 337 2017-08-23  Alan Modra  <amodra@gmail.com>
 338
 339         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 340         extract functions earlier, deleting forward declarations.
 341         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 342         RA_MASK.
 343
 344 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 345
 346         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 347
 348 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 349             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 350
 351         * ppc-opc.c (insert_evuimm2_ex0): New function.
 352         (extract_evuimm2_ex0): Likewise.
 353         (insert_evuimm4_ex0): Likewise.
 354         (extract_evuimm4_ex0): Likewise.
 355         (insert_evuimm8_ex0): Likewise.
 356         (extract_evuimm8_ex0): Likewise.
 357         (insert_evuimm_lt16): Likewise.
 358         (extract_evuimm_lt16): Likewise.
 359         (insert_rD_rS_even): Likewise.
 360         (extract_rD_rS_even): Likewise.
 361         (insert_off_lsp): Likewise.
 362         (extract_off_lsp): Likewise.
 363         (RD_EVEN): New operand.
 364         (RS_EVEN): Likewise.
 365         (RSQ): Adjust.
 366         (EVUIMM_LT16): New operand.
 367         (HTM_SI): Adjust.
 368         (EVUIMM_2_EX0): New operand.
 369         (EVUIMM_4): Adjust.
 370         (EVUIMM_4_EX0): New operand.
 371         (EVUIMM_8): Adjust.
 372         (EVUIMM_8_EX0): New operand.
 373         (WS): Adjust.
 374         (VX_OFF): New operand.
 375         (VX_LSP): New macro.
 376         (VX_LSP_MASK): Likewise.
 377         (VX_LSP_OFF_MASK): Likewise.
 378         (PPC_OPCODE_LSP): Likewise.
 379         (vle_opcodes): Add LSP opcodes.
 380         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 381
 382 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 383
 384         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 385         register operands in CRC instructions.
 386         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 387         comments.
 388
 389 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 390
 391         * disassemble.c (disassembler): Mark big and mach with
 392         ATTRIBUTE_UNUSED.
 393
 394 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 395
 396         * disassemble.c (disassembler): Remove arch/mach/endian
 397         assertions.
 398
 399 2017-07-25  Nick Clifton  <nickc@redhat.com>
 400
 401         PR 21739
 402         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 403         message.
 404         (insert_r0): Likewise.
 405         (insert_r1): Likewise.
 406         (insert_r2): Likewise.
 407         (insert_r3): Likewise.
 408         (insert_sp): Likewise.
 409         (insert_gp): Likewise.
 410         (insert_pcl): Likewise.
 411         (insert_blink): Likewise.
 412         (insert_ilink1): Likewise.
 413         (insert_ilink2): Likewise.
 414         (insert_ras): Likewise.
 415         (insert_rbs): Likewise.
 416         (insert_rcs): Likewise.
 417         (insert_simm3s): Likewise.
 418         (insert_rrange): Likewise.
 419         (insert_r13el): Likewise.
 420         (insert_fpel): Likewise.
 421         (insert_blinkel): Likewise.
 422         (insert_pclel): Likewise.
 423         (insert_nps_bitop_size_2b): Likewise.
 424         (insert_nps_imm_offset): Likewise.
 425         (insert_nps_imm_entry): Likewise.
 426         (insert_nps_size_16bit): Likewise.
 427         (insert_nps_##NAME##_pos): Likewise.
 428         (insert_nps_##NAME): Likewise.
 429         (insert_nps_bitop_ins_ext): Likewise.
 430         (insert_nps_##NAME): Likewise.
 431         (insert_nps_min_hofs): Likewise.
 432         (insert_nps_##NAME): Likewise.
 433         (insert_nps_rbdouble_64): Likewise.
 434         (insert_nps_misc_imm_offset): Likewise.
 435         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 436         option description.
 437
 438 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 439             Jiong Wang  <jiong.wang@arm.com>
 440
 441         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 442         correct the print.
 443         * aarch64-dis-2.c: Regenerated.
 444
 445 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 446
 447         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 448         table.
 449
 450 2017-07-20  Nick Clifton  <nickc@redhat.com>
 451
 452         * po/de.po: Updated German translation.
 453
 454 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 455
 456         * arc-regs.h (sec_stat): New aux register.
 457         (aux_kernel_sp): Likewise.
 458         (aux_sec_u_sp): Likewise.
 459         (aux_sec_k_sp): Likewise.
 460         (sec_vecbase_build): Likewise.
 461         (nsc_table_top): Likewise.
 462         (nsc_table_base): Likewise.
 463         (ersec_stat): Likewise.
 464         (aux_sec_except): Likewise.
 465
 466 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 467
 468         * arc-opc.c (extract_uimm12_20): New function.
 469         (UIMM12_20): New operand.
 470         (SIMM3_5_S): Adjust.
 471         * arc-tbl.h (sjli): Add new instruction.
 472
 473 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 474             John Eric Martin  <John.Martin@emmicro-us.com>
 475
 476         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 477         (UIMM3_23): Adjust accordingly.
 478         * arc-regs.h: Add/correct jli_base register.
 479         * arc-tbl.h (jli_s): Likewise.
 480
 481 2017-07-18  Nick Clifton  <nickc@redhat.com>
 482
 483         PR 21775
 484         * aarch64-opc.c: Fix spelling typos.
 485         * i386-dis.c: Likewise.
 486
 487 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 488
 489         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 490         max_addr_offset and octets variables to size_t.
 491
 492 2017-07-12  Alan Modra  <amodra@gmail.com>
 493
 494         * po/da.po: Update from translationproject.org/latest/opcodes/.
 495         * po/de.po: Likewise.
 496         * po/es.po: Likewise.
 497         * po/fi.po: Likewise.
 498         * po/fr.po: Likewise.
 499         * po/id.po: Likewise.
 500         * po/it.po: Likewise.
 501         * po/nl.po: Likewise.
 502         * po/pt_BR.po: Likewise.
 503         * po/ro.po: Likewise.
 504         * po/sv.po: Likewise.
 505         * po/tr.po: Likewise.
 506         * po/uk.po: Likewise.
 507         * po/vi.po: Likewise.
 508         * po/zh_CN.po: Likewise.
 509
 510 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 511             Alan Modra  <amodra@gmail.com>
 512
 513         * cgen.sh: Mark generated files read-only.
 514         * epiphany-asm.c: Regenerate.
 515         * epiphany-desc.c: Regenerate.
 516         * epiphany-desc.h: Regenerate.
 517         * epiphany-dis.c: Regenerate.
 518         * epiphany-ibld.c: Regenerate.
 519         * epiphany-opc.c: Regenerate.
 520         * epiphany-opc.h: Regenerate.
 521         * fr30-asm.c: Regenerate.
 522         * fr30-desc.c: Regenerate.
 523         * fr30-desc.h: Regenerate.
 524         * fr30-dis.c: Regenerate.
 525         * fr30-ibld.c: Regenerate.
 526         * fr30-opc.c: Regenerate.
 527         * fr30-opc.h: Regenerate.
 528         * frv-asm.c: Regenerate.
 529         * frv-desc.c: Regenerate.
 530         * frv-desc.h: Regenerate.
 531         * frv-dis.c: Regenerate.
 532         * frv-ibld.c: Regenerate.
 533         * frv-opc.c: Regenerate.
 534         * frv-opc.h: Regenerate.
 535         * ip2k-asm.c: Regenerate.
 536         * ip2k-desc.c: Regenerate.
 537         * ip2k-desc.h: Regenerate.
 538         * ip2k-dis.c: Regenerate.
 539         * ip2k-ibld.c: Regenerate.
 540         * ip2k-opc.c: Regenerate.
 541         * ip2k-opc.h: Regenerate.
 542         * iq2000-asm.c: Regenerate.
 543         * iq2000-desc.c: Regenerate.
 544         * iq2000-desc.h: Regenerate.
 545         * iq2000-dis.c: Regenerate.
 546         * iq2000-ibld.c: Regenerate.
 547         * iq2000-opc.c: Regenerate.
 548         * iq2000-opc.h: Regenerate.
 549         * lm32-asm.c: Regenerate.
 550         * lm32-desc.c: Regenerate.
 551         * lm32-desc.h: Regenerate.
 552         * lm32-dis.c: Regenerate.
 553         * lm32-ibld.c: Regenerate.
 554         * lm32-opc.c: Regenerate.
 555         * lm32-opc.h: Regenerate.
 556         * lm32-opinst.c: Regenerate.
 557         * m32c-asm.c: Regenerate.
 558         * m32c-desc.c: Regenerate.
 559         * m32c-desc.h: Regenerate.
 560         * m32c-dis.c: Regenerate.
 561         * m32c-ibld.c: Regenerate.
 562         * m32c-opc.c: Regenerate.
 563         * m32c-opc.h: Regenerate.
 564         * m32r-asm.c: Regenerate.
 565         * m32r-desc.c: Regenerate.
 566         * m32r-desc.h: Regenerate.
 567         * m32r-dis.c: Regenerate.
 568         * m32r-ibld.c: Regenerate.
 569         * m32r-opc.c: Regenerate.
 570         * m32r-opc.h: Regenerate.
 571         * m32r-opinst.c: Regenerate.
 572         * mep-asm.c: Regenerate.
 573         * mep-desc.c: Regenerate.
 574         * mep-desc.h: Regenerate.
 575         * mep-dis.c: Regenerate.
 576         * mep-ibld.c: Regenerate.
 577         * mep-opc.c: Regenerate.
 578         * mep-opc.h: Regenerate.
 579         * mt-asm.c: Regenerate.
 580         * mt-desc.c: Regenerate.
 581         * mt-desc.h: Regenerate.
 582         * mt-dis.c: Regenerate.
 583         * mt-ibld.c: Regenerate.
 584         * mt-opc.c: Regenerate.
 585         * mt-opc.h: Regenerate.
 586         * or1k-asm.c: Regenerate.
 587         * or1k-desc.c: Regenerate.
 588         * or1k-desc.h: Regenerate.
 589         * or1k-dis.c: Regenerate.
 590         * or1k-ibld.c: Regenerate.
 591         * or1k-opc.c: Regenerate.
 592         * or1k-opc.h: Regenerate.
 593         * or1k-opinst.c: Regenerate.
 594         * xc16x-asm.c: Regenerate.
 595         * xc16x-desc.c: Regenerate.
 596         * xc16x-desc.h: Regenerate.
 597         * xc16x-dis.c: Regenerate.
 598         * xc16x-ibld.c: Regenerate.
 599         * xc16x-opc.c: Regenerate.
 600         * xc16x-opc.h: Regenerate.
 601         * xstormy16-asm.c: Regenerate.
 602         * xstormy16-desc.c: Regenerate.
 603         * xstormy16-desc.h: Regenerate.
 604         * xstormy16-dis.c: Regenerate.
 605         * xstormy16-ibld.c: Regenerate.
 606         * xstormy16-opc.c: Regenerate.
 607         * xstormy16-opc.h: Regenerate.
 608
 609 2017-07-07  Alan Modra  <amodra@gmail.com>
 610
 611         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 612         * m32c-dis.c: Regenerate.
 613         * mep-dis.c: Regenerate.
 614
 615 2017-07-05  Borislav Petkov  <bp@suse.de>
 616
 617         * i386-dis.c: Enable ModRM.reg /6 aliases.
 618
 619 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 620
 621         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 622         with vmrs and vmsr.
 623
 624 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 625
 626         * configure: Regenerate.
 627
 628 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 629
 630         * po/opcodes.pot: Regenerate.
 631
 632 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 633
 634         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 635         entries to the MSA ASE instruction block.
 636
 637 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 638             Maciej W. Rozycki  <macro@imgtec.com>
 639
 640         * micromips-opc.c (XPA, XPAVZ): New macros.
 641         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 642         "mthgc0".
 643
 644 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 645             Maciej W. Rozycki  <macro@imgtec.com>
 646
 647         * micromips-opc.c (I36): New macro.
 648         (micromips_opcodes): Add "eretnc".
 649
 650 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 651             Andrew Bennett  <andrew.bennett@imgtec.com>
 652
 653         * mips-dis.c (mips_calculate_combination_ases): Handle the
 654         ASE_XPA_VIRT flag.
 655         (parse_mips_ase_option): New function.
 656         (parse_mips_dis_option): Factor out ASE option handling to the
 657         new function.  Call `mips_calculate_combination_ases'.
 658         * mips-opc.c (XPAVZ): New macro.
 659         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 660         "mfhgc0", "mthc0" and "mthgc0".
 661
 662 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 663
 664         * mips-dis.c (mips_calculate_combination_ases): New function.
 665         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 666         calculation to the new function.
 667         (set_default_mips_dis_options): Call the new function.
 668
 669 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 670
 671         * arc-dis.c (parse_disassembler_options): Use
 672         FOR_EACH_DISASSEMBLER_OPTION.
 673
 674 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 675
 676         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 677         disassembler option strings.
 678         (parse_cpu_option): Likewise.
 679
 680 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 681
 682         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 683         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 684         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 685         (aarch64_feature_dotprod, DOT_INSN): New.
 686         (udot, sdot): New.
 687         * aarch64-dis-2.c: Regenerated.
 688
 689 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 690
 691         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 692
 693 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 694             Matthew Fortune  <matthew.fortune@imgtec.com>
 695             Andrew Bennett  <andrew.bennett@imgtec.com>
 696
 697         * mips-formats.h (INT_BIAS): New macro.
 698         (INT_ADJ): Redefine in INT_BIAS terms.
 699         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 700         (mips_print_save_restore): New function.
 701         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 702         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 703         call.
 704         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 705         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 706         OP_SAVE_RESTORE_LIST handling, factored out from here.
 707         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 708         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 709         (mips_builtin_opcodes): Add "restore" and "save" entries.
 710         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 711         (IAMR2): New macro.
 712         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 713
 714 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 715
 716         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 717         alias; do not mark SLTI instruction as an alias.
 718
 719 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 720
 721         * i386-dis.c (RM_0FAE_REG_5): Removed.
 722         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 723         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 724         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 725         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 726         PREFIX_MOD_3_0F01_REG_5_RM_0.
 727         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 728         PREFIX_MOD_3_0FAE_REG_5.
 729         (mod_table): Update MOD_0FAE_REG_5.
 730         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 731         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 732         * i386-tbl.h: Regenerated.
 733
 734 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 735
 736         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 737         * i386-opc.tbl: Likewise.
 738         * i386-tbl.h: Regenerated.
 739
 740 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 741
 742         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 743         and "jmp{&|}".
 744         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 745         prefix.
 746
 747 2017-06-19  Nick Clifton  <nickc@redhat.com>
 748
 749         PR binutils/21614
 750         * score-dis.c (score_opcodes): Add sentinel.
 751
 752 2017-06-16  Alan Modra  <amodra@gmail.com>
 753
 754         * rx-decode.c: Regenerate.
 755
 756 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 757
 758         PR binutils/21594
 759         * i386-dis.c (OP_E_register): Check valid bnd register.
 760         (OP_G): Likewise.
 761
 762 2017-06-15  Nick Clifton  <nickc@redhat.com>
 763
 764         PR binutils/21595
 765         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 766         range value.
 767
 768 2017-06-15  Nick Clifton  <nickc@redhat.com>
 769
 770         PR binutils/21588
 771         * rl78-decode.opc (OP_BUF_LEN): Define.
 772         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 773         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 774         array.
 775         * rl78-decode.c: Regenerate.
 776
 777 2017-06-15  Nick Clifton  <nickc@redhat.com>
 778
 779         PR binutils/21586
 780         * bfin-dis.c (gregs): Clip index to prevent overflow.
 781         (regs): Likewise.
 782         (regs_lo): Likewise.
 783         (regs_hi): Likewise.
 784
 785 2017-06-14  Nick Clifton  <nickc@redhat.com>
 786
 787         PR binutils/21576
 788         * score7-dis.c (score_opcodes): Add sentinel.
 789
 790 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 791
 792         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 793         * arm-dis.c: Likewise.
 794         * ia64-dis.c: Likewise.
 795         * mips-dis.c: Likewise.
 796         * spu-dis.c: Likewise.
 797         * disassemble.h (print_insn_aarch64): New declaration, moved from
 798         include/dis-asm.h.
 799         (print_insn_big_arm, print_insn_big_mips): Likewise.
 800         (print_insn_i386, print_insn_ia64): Likewise.
 801         (print_insn_little_arm, print_insn_little_mips): Likewise.
 802
 803 2017-06-14  Nick Clifton  <nickc@redhat.com>
 804
 805         PR binutils/21587
 806         * rx-decode.opc: Include libiberty.h
 807         (GET_SCALE): New macro - validates access to SCALE array.
 808         (GET_PSCALE): New macro - validates access to PSCALE array.
 809         (DIs, SIs, S2Is, rx_disp): Use new macros.
 810         * rx-decode.c: Regenerate.
 811
 812 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 813
 814         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 815
 816 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 817
 818         * arc-dis.c (enforced_isa_mask): Declare.
 819         (cpu_types): Likewise.
 820         (parse_cpu_option): New function.
 821         (parse_disassembler_options): Use it.
 822         (print_insn_arc): Use enforced_isa_mask.
 823         (print_arc_disassembler_options): Document new options.
 824
 825 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 826
 827         * alpha-dis.c: Include disassemble.h, don't include
 828         dis-asm.h.
 829         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 830         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 831         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 832         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 833         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 834         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 835         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 836         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 837         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 838         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 839         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 840         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 841         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 842         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 843         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 844         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 845         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 846         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 847         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 848         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 849         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 850         * z80-dis.c, z8k-dis.c: Likewise.
 851         * disassemble.h: New file.
 852
 853 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 854
 855         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 856         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 857
 858 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 859
 860         * disassemble.c (disassembler): Add arguments a, big and mach.
 861         Use them.
 862
 863 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 864
 865         * i386-dis.c (NOTRACK_Fixup): New.
 866         (NOTRACK): Likewise.
 867         (NOTRACK_PREFIX): Likewise.
 868         (last_active_prefix): Likewise.
 869         (reg_table): Use NOTRACK on indirect call and jmp.
 870         (ckprefix): Set last_active_prefix.
 871         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 872         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 873         * i386-opc.h (NoTrackPrefixOk): New.
 874         (i386_opcode_modifier): Add notrackprefixok.
 875         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 876         Add notrack.
 877         * i386-tbl.h: Regenerated.
 878
 879 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 880
 881         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 882         (X_IMM2): Define.
 883         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 884         bfd_mach_sparc_v9m8.
 885         (print_insn_sparc): Handle new operand types.
 886         * sparc-opc.c (MASK_M8): Define.
 887         (v6): Add MASK_M8.
 888         (v6notlet): Likewise.
 889         (v7): Likewise.
 890         (v8): Likewise.
 891         (v9): Likewise.
 892         (v9a): Likewise.
 893         (v9b): Likewise.
 894         (v9c): Likewise.
 895         (v9d): Likewise.
 896         (v9e): Likewise.
 897         (v9v): Likewise.
 898         (v9m): Likewise.
 899         (v9andleon): Likewise.
 900         (m8): Define.
 901         (HWS_VM8): Define.
 902         (HWS2_VM8): Likewise.
 903         (sparc_opcode_archs): Add entry for "m8".
 904         (sparc_opcodes): Add OSA2017 and M8 instructions
 905         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 906         fpx{ll,ra,rl}64x,
 907         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 908         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 909         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 910         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 911         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 912         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 913         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 914         ASI_CORE_SELECT_COMMIT_NHT.
 915
 916 2017-05-18  Alan Modra  <amodra@gmail.com>
 917
 918         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 919         * aarch64-dis.c: Likewise.
 920         * aarch64-gen.c: Likewise.
 921         * aarch64-opc.c: Likewise.
 922
 923 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 924             Matthew Fortune  <matthew.fortune@imgtec.com>
 925
 926         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 927         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 928         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 929         (print_insn_arg) <OP_REG28>: Add handler.
 930         (validate_insn_args) <OP_REG28>: Handle.
 931         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 932         32-bit encoding and 9-bit immediates.
 933         (print_insn_mips16): Handle MIPS16 instructions that require
 934         32-bit encoding and MFC0/MTC0 operand decoding.
 935         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 936         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 937         (RD_C0, WR_C0, E2, E2MT): New macros.
 938         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 939         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 940         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 941         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 942         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 943         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 944         instructions, "swl", "swr", "sync" and its "sync_acquire",
 945         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 946         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 947         regular/extended entries for original MIPS16 ISA revision
 948         instructions whose extended forms are subdecoded in the MIPS16e2
 949         ISA revision: "li", "sll" and "srl".
 950
 951 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 952
 953         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 954         reference in CP0 move operand decoding.
 955
 956 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 957
 958         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 959         type to hexadecimal.
 960         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 961
 962 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 963
 964         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 965         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 966         "sync_rmb" and "sync_wmb" as aliases.
 967         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 968         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 969
 970 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 971
 972         * arc-dis.c (parse_option): Update quarkse_em option..
 973         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 974         QUARKSE1.
 975         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 976
 977 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 978
 979         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 980
 981 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 982
 983         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 984         register.
 985
 986 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 987
 988         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 989         and branches and not synthetic data instructions.
 990
 991 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 992
 993         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 994
 995 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 996
 997         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 998         * arc-opc.c (insert_r13el): New function.
 999         (R13_EL): Define.
1000         * arc-tbl.h: Add new enter/leave variants.
1001
1002 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1003
1004         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1005
1006 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1007
1008         * mips-dis.c (print_mips_disassembler_options): Add
1009         `no-aliases'.
1010
1011 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1012
1013         * mips16-opc.c (AL): New macro.
1014         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1015         of "ld" and "lw" as aliases.
1016
1017 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
1018
1019         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1020         arguments.
1021
1022 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
1023             Alan Modra  <amodra@gmail.com>
1024
1025         * ppc-opc.c (ELEV): Define.
1026         (vle_opcodes): Add se_rfgi and e_sc.
1027         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1028         for E200Z4.
1029
1030 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1031
1032         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1033
1034 2017-04-21  Nick Clifton  <nickc@redhat.com>
1035
1036         PR binutils/21380
1037         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1038         LD3R and LD4R.
1039
1040 2017-04-13  Alan Modra  <amodra@gmail.com>
1041
1042         * epiphany-desc.c: Regenerate.
1043         * fr30-desc.c: Regenerate.
1044         * frv-desc.c: Regenerate.
1045         * ip2k-desc.c: Regenerate.
1046         * iq2000-desc.c: Regenerate.
1047         * lm32-desc.c: Regenerate.
1048         * m32c-desc.c: Regenerate.
1049         * m32r-desc.c: Regenerate.
1050         * mep-desc.c: Regenerate.
1051         * mt-desc.c: Regenerate.
1052         * or1k-desc.c: Regenerate.
1053         * xc16x-desc.c: Regenerate.
1054         * xstormy16-desc.c: Regenerate.
1055
1056 2017-04-11  Alan Modra  <amodra@gmail.com>
1057
1058         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1059         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1060         PPC_OPCODE_TMR for e6500.
1061         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1062         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1063         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1064         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1065         (PPCHTM): Define as PPC_OPCODE_POWER8.
1066         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1067
1068 2017-04-10  Alan Modra  <amodra@gmail.com>
1069
1070         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1071         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1072         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1073         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1074
1075 2017-04-09  Pip Cet  <pipcet@gmail.com>
1076
1077         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1078         appropriate floating-point precision directly.
1079
1080 2017-04-07  Alan Modra  <amodra@gmail.com>
1081
1082         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1083         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1084         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1085         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1086         vector instructions with E6500 not PPCVEC2.
1087
1088 2017-04-06  Pip Cet  <pipcet@gmail.com>
1089
1090         * Makefile.am: Add wasm32-dis.c.
1091         * configure.ac: Add wasm32-dis.c to wasm32 target.
1092         * disassemble.c: Add wasm32 disassembler code.
1093         * wasm32-dis.c: New file.
1094         * Makefile.in: Regenerate.
1095         * configure: Regenerate.
1096         * po/POTFILES.in: Regenerate.
1097         * po/opcodes.pot: Regenerate.
1098
1099 2017-04-05  Pedro Alves  <palves@redhat.com>
1100
1101         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1102         * arm-dis.c (parse_arm_disassembler_options): Constify.
1103         * ppc-dis.c (powerpc_init_dialect): Constify local.
1104         * vax-dis.c (parse_disassembler_options): Constify.
1105
1106 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1107
1108         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1109         RISCV_GP_SYMBOL.
1110
1111 2017-03-30  Pip Cet  <pipcet@gmail.com>
1112
1113         * configure.ac: Add (empty) bfd_wasm32_arch target.
1114         * configure: Regenerate
1115         * po/opcodes.pot: Regenerate.
1116
1117 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1118
1119         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1120         OSA2015.
1121         * opcodes/sparc-opc.c (asi_table): New ASIs.
1122
1123 2017-03-29  Alan Modra  <amodra@gmail.com>
1124
1125         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1126         "raw" option.
1127         (lookup_powerpc): Don't special case -1 dialect.  Handle
1128         PPC_OPCODE_RAW.
1129         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1130         lookup_powerpc call, pass it on second.
1131
1132 2017-03-27  Alan Modra  <amodra@gmail.com>
1133
1134         PR 21303
1135         * ppc-dis.c (struct ppc_mopt): Comment.
1136         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1137
1138 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1139
1140         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1141         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1142         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1143         (insert_nps_misc_imm_offset): New function.
1144         (extract_nps_misc imm_offset): New function.
1145         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1146         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1147
1148 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1149
1150         * s390-mkopc.c (main): Remove vx2 check.
1151         * s390-opc.txt: Remove vx2 instruction flags.
1152
1153 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1154
1155         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1156         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1157         (insert_nps_imm_offset): New function.
1158         (extract_nps_imm_offset): New function.
1159         (insert_nps_imm_entry): New function.
1160         (extract_nps_imm_entry): New function.
1161
1162 2017-03-17  Alan Modra  <amodra@gmail.com>
1163
1164         PR 21248
1165         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1166         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1167         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1168
1169 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1170
1171         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1172         <c.andi>: Likewise.
1173         <c.addiw> Likewise.
1174
1175 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1176
1177         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1178
1179 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1180
1181         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1182         <srl> Likewise.
1183         <srai> Likewise.
1184         <sra> Likewise.
1185
1186 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1187
1188         * i386-gen.c (opcode_modifiers): Replace S with Load.
1189         * i386-opc.h (S): Removed.
1190         (Load): New.
1191         (i386_opcode_modifier): Replace s with load.
1192         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1193         and {evex}.  Replace S with Load.
1194         * i386-tbl.h: Regenerated.
1195
1196 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1197
1198         * i386-opc.tbl: Use CpuCET on rdsspq.
1199         * i386-tbl.h: Regenerated.
1200
1201 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1202
1203         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1204         <vsx>: Do not use PPC_OPCODE_VSX3;
1205
1206 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1207
1208         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1209
1210 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1211
1212         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1213         (MOD_0F1E_PREFIX_1): Likewise.
1214         (MOD_0F38F5_PREFIX_2): Likewise.
1215         (MOD_0F38F6_PREFIX_0): Likewise.
1216         (RM_0F1E_MOD_3_REG_7): Likewise.
1217         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1218         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1219         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1220         (PREFIX_0F1E): Likewise.
1221         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1222         (PREFIX_0F38F5): Likewise.
1223         (dis386_twobyte): Use PREFIX_0F1E.
1224         (reg_table): Add REG_0F1E_MOD_3.
1225         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1226         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1227         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1228         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1229         (three_byte_table): Use PREFIX_0F38F5.
1230         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1231         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1232         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1233         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1234         PREFIX_MOD_3_0F01_REG_5_RM_2.
1235         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1236         (cpu_flags): Add CpuCET.
1237         * i386-opc.h (CpuCET): New enum.
1238         (CpuUnused): Commented out.
1239         (i386_cpu_flags): Add cpucet.
1240         * i386-opc.tbl: Add Intel CET instructions.
1241         * i386-init.h: Regenerated.
1242         * i386-tbl.h: Likewise.
1243
1244 2017-03-06  Alan Modra  <amodra@gmail.com>
1245
1246         PR 21124
1247         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1248         (extract_raq, extract_ras, extract_rbx): New functions.
1249         (powerpc_operands): Use opposite corresponding insert function.
1250         (Q_MASK): Define.
1251         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1252         register restriction.
1253
1254 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1255
1256         * disassemble.c Include "safe-ctype.h".
1257         (disassemble_init_for_target): Handle s390 init.
1258         (remove_whitespace_and_extra_commas): New function.
1259         (disassembler_options_cmp): Likewise.
1260         * arm-dis.c: Include "libiberty.h".
1261         (NUM_ELEM): Delete.
1262         (regnames): Use long disassembler style names.
1263         Add force-thumb and no-force-thumb options.
1264         (NUM_ARM_REGNAMES): Rename from this...
1265         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1266         (get_arm_regname_num_options): Delete.
1267         (set_arm_regname_option): Likewise.
1268         (get_arm_regnames): Likewise.
1269         (parse_disassembler_options): Likewise.
1270         (parse_arm_disassembler_option): Rename from this...
1271         (parse_arm_disassembler_options): ...to this.  Make static.
1272         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1273         (print_insn): Use parse_arm_disassembler_options.
1274         (disassembler_options_arm): New function.
1275         (print_arm_disassembler_options): Handle updated regnames.
1276         * ppc-dis.c: Include "libiberty.h".
1277         (ppc_opts): Add "32" and "64" entries.
1278         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1279         (powerpc_init_dialect): Add break to switch statement.
1280         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1281         (disassembler_options_powerpc): New function.
1282         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1283         Remove printing of "32" and "64".
1284         * s390-dis.c: Include "libiberty.h".
1285         (init_flag): Remove unneeded variable.
1286         (struct s390_options_t): New structure type.
1287         (options): New structure.
1288         (init_disasm): Rename from this...
1289         (disassemble_init_s390): ...to this.  Add initializations for
1290         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1291         (print_insn_s390): Delete call to init_disasm.
1292         (disassembler_options_s390): New function.
1293         (print_s390_disassembler_options): Print using information from
1294         struct 'options'.
1295         * po/opcodes.pot: Regenerate.
1296
1297 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1298
1299         * i386-dis.c (PCMPESTR_Fixup): New.
1300         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1301         (prefix_table): Use PCMPESTR_Fixup.
1302         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1303         PCMPESTR_Fixup.
1304         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1305         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1306         Split 64-bit and non-64-bit variants.
1307         * opcodes/i386-tbl.h: Re-generate.
1308
1309 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1310
1311         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1312         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1313         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1314         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1315         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1316         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1317         (OP_SVE_V_HSD): New macros.
1318         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1319         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1320         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1321         (aarch64_opcode_table): Add new SVE instructions.
1322         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1323         for rotation operands.  Add new SVE operands.
1324         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1325         (ins_sve_quad_index): Likewise.
1326         (ins_imm_rotate): Split into...
1327         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1328         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1329         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1330         functions.
1331         (aarch64_ins_sve_addr_ri_s4): New function.
1332         (aarch64_ins_sve_quad_index): Likewise.
1333         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1334         * aarch64-asm-2.c: Regenerate.
1335         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1336         (ext_sve_quad_index): Likewise.
1337         (ext_imm_rotate): Split into...
1338         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1339         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1340         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1341         functions.
1342         (aarch64_ext_sve_addr_ri_s4): New function.
1343         (aarch64_ext_sve_quad_index): Likewise.
1344         (aarch64_ext_sve_index): Allow quad indices.
1345         (do_misc_decoding): Likewise.
1346         * aarch64-dis-2.c: Regenerate.
1347         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1348         aarch64_field_kinds.
1349         (OPD_F_OD_MASK): Widen by one bit.
1350         (OPD_F_NO_ZR): Bump accordingly.
1351         (get_operand_field_width): New function.
1352         * aarch64-opc.c (fields): Add new SVE fields.
1353         (operand_general_constraint_met_p): Handle new SVE operands.
1354         (aarch64_print_operand): Likewise.
1355         * aarch64-opc-2.c: Regenerate.
1356
1357 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1358
1359         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1360         (aarch64_feature_compnum): ...this.
1361         (SIMD_V8_3): Replace with...
1362         (COMPNUM): ...this.
1363         (CNUM_INSN): New macro.
1364         (aarch64_opcode_table): Use it for the complex number instructions.
1365
1366 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1367
1368         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1369
1370 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1371
1372         Add support for associating SPARC ASIs with an architecture level.
1373         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1374         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1375         decoding of SPARC ASIs.
1376
1377 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1378
1379         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1380         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1381
1382 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1383
1384         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1385         1 (instead of to itself). Correct typo.
1386
1387 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1388
1389         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1390         pseudoinstructions.
1391
1392 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1393
1394         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1395         (aarch64_sys_reg_supported_p): Handle them.
1396
1397 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1398
1399         * arc-opc.c (UIMM6_20R): Define.
1400         (SIMM12_20): Use above.
1401         (SIMM12_20R): Define.
1402         (SIMM3_5_S): Use above.
1403         (UIMM7_A32_11R_S): Define.
1404         (UIMM7_9_S): Use above.
1405         (UIMM3_13R_S): Define.
1406         (SIMM11_A32_7_S): Use above.
1407         (SIMM9_8R): Define.
1408         (UIMM10_A32_8_S): Use above.
1409         (UIMM8_8R_S): Define.
1410         (W6): Use above.
1411         (arc_relax_opcodes): Use all above defines.
1412
1413 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1414
1415         * arc-regs.h: Distinguish some of the registers different on
1416         ARC700 and HS38 cpus.
1417
1418 2017-02-14  Alan Modra  <amodra@gmail.com>
1419
1420         PR 21118
1421         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1422         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1423
1424 2017-02-11  Stafford Horne  <shorne@gmail.com>
1425             Alan Modra  <amodra@gmail.com>
1426
1427         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1428         Use insn_bytes_value and insn_int_value directly instead.  Don't
1429         free allocated memory until function exit.
1430
1431 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1432
1433         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1434
1435 2017-02-03  Nick Clifton  <nickc@redhat.com>
1436
1437         PR 21096
1438         * aarch64-opc.c (print_register_list): Ensure that the register
1439         list index will fir into the tb buffer.
1440         (print_register_offset_address): Likewise.
1441         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1442
1443 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1444
1445         PR 21056
1446         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1447         instructions when the previous fetch packet ends with a 32-bit
1448         instruction.
1449
1450 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1451
1452         * pru-opc.c: Remove vague reference to a future GDB port.
1453
1454 2017-01-20  Nick Clifton  <nickc@redhat.com>
1455
1456         * po/ga.po: Updated Irish translation.
1457
1458 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1459
1460         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1461
1462 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1463
1464         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1465         if FETCH_DATA returns 0.
1466         (m68k_scan_mask): Likewise.
1467         (print_insn_m68k): Update code to handle -1 return value.
1468
1469 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1470
1471         * m68k-dis.c (enum print_insn_arg_error): New.
1472         (NEXTBYTE): Replace -3 with
1473         PRINT_INSN_ARG_MEMORY_ERROR.
1474         (NEXTULONG): Likewise.
1475         (NEXTSINGLE): Likewise.
1476         (NEXTDOUBLE): Likewise.
1477         (NEXTDOUBLE): Likewise.
1478         (NEXTPACKED): Likewise.
1479         (FETCH_ARG): Likewise.
1480         (FETCH_DATA): Update comments.
1481         (print_insn_arg): Update comments. Replace magic numbers with
1482         enum.
1483         (match_insn_m68k): Likewise.
1484
1485 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1486
1487         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1488         * i386-dis-evex.h (evex_table): Updated.
1489         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1490         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1491         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1492         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1493         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1494         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1495         * i386-init.h: Regenerate.
1496         * i386-tbl.h: Ditto.
1497
1498 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1499
1500         * msp430-dis.c (msp430_singleoperand): Return -1 if
1501         msp430dis_opcode_signed returns false.
1502         (msp430_doubleoperand): Likewise.
1503         (msp430_branchinstr): Return -1 if
1504         msp430dis_opcode_unsigned returns false.
1505         (msp430x_calla_instr): Likewise.
1506         (print_insn_msp430): Likewise.
1507
1508 2017-01-05  Nick Clifton  <nickc@redhat.com>
1509
1510         PR 20946
1511         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1512         could not be matched.
1513         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1514         NULL.
1515
1516 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1517
1518         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1519         (aarch64_opcode_table): Use RCPC_INSN.
1520
1521 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1522
1523         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1524         extension.
1525         * riscv-opcodes/all-opcodes: Likewise.
1526
1527 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1528
1529         * riscv-dis.c (print_insn_args): Add fall through comment.
1530
1531 2017-01-03  Nick Clifton  <nickc@redhat.com>
1532
1533         * po/sr.po: New Serbian translation.
1534         * configure.ac (ALL_LINGUAS): Add sr.
1535         * configure: Regenerate.
1536
1537 2017-01-02  Alan Modra  <amodra@gmail.com>
1538
1539         * epiphany-desc.h: Regenerate.
1540         * epiphany-opc.h: Regenerate.
1541         * fr30-desc.h: Regenerate.
1542         * fr30-opc.h: Regenerate.
1543         * frv-desc.h: Regenerate.
1544         * frv-opc.h: Regenerate.
1545         * ip2k-desc.h: Regenerate.
1546         * ip2k-opc.h: Regenerate.
1547         * iq2000-desc.h: Regenerate.
1548         * iq2000-opc.h: Regenerate.
1549         * lm32-desc.h: Regenerate.
1550         * lm32-opc.h: Regenerate.
1551         * m32c-desc.h: Regenerate.
1552         * m32c-opc.h: Regenerate.
1553         * m32r-desc.h: Regenerate.
1554         * m32r-opc.h: Regenerate.
1555         * mep-desc.h: Regenerate.
1556         * mep-opc.h: Regenerate.
1557         * mt-desc.h: Regenerate.
1558         * mt-opc.h: Regenerate.
1559         * or1k-desc.h: Regenerate.
1560         * or1k-opc.h: Regenerate.
1561         * xc16x-desc.h: Regenerate.
1562         * xc16x-opc.h: Regenerate.
1563         * xstormy16-desc.h: Regenerate.
1564         * xstormy16-opc.h: Regenerate.
1565
1566 2017-01-02  Alan Modra  <amodra@gmail.com>
1567
1568         Update year range in copyright notice of all files.
1569
1570 For older changes see ChangeLog-2016
1571 \f
1572 Copyright (C) 2017 Free Software Foundation, Inc.
1573
1574 Copying and distribution of this file, with or without modification,
1575 are permitted in any medium without royalty provided the copyright
1576 notice and this notice are preserved.
1577
1578 Local Variables:
1579 mode: change-log
1580 left-margin: 8
1581 fill-column: 74
1582 version-control: never
1583 End: