opcodes/ChangeLog

   1 2006-11-09  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-dis.c (twobyte_uses_SSE_prefix): Renamed to ...
   4         (twobyte_uses_DATA_prefix): This.
   5         (twobyte_uses_REPNZ_prefix): New.
   6         (twobyte_uses_REPZ_prefix): Likewise.
   7         (threebyte_0x38_uses_DATA_prefix): Likewise.
   8         (threebyte_0x38_uses_REPNZ_prefix): Likewise.
   9         (threebyte_0x38_uses_REPZ_prefix): Likewise.
  10         (threebyte_0x3a_uses_DATA_prefix): Likewise.
  11         (threebyte_0x3a_uses_REPNZ_prefix): Likewise.
  12         (threebyte_0x3a_uses_REPZ_prefix): Likewise.
  13         (print_insn): Updated checking usages of DATA/REPNZ/REPZ
  14         prefixes.
  15
  16 2006-11-06  Troy Rollo  <troy@corvu.com.au>
  17
  18         * ppc-opc.c: Restore COM to mfcr wrongly removed 2003-07-04.
  19
  20 2006-11-01  Mei Ligang  <ligang@sunnorth.com.cn>
  21
  22         * score-opc.h (score_opcodes): Delete modifier '0x'.
  23
  24 2006-10-30  Paul Brook  <paul@codesourcery.com>
  25
  26         * arm-dis.c (last_is_thumb, last_mapping_sym, last_mapping_addr): New.
  27         (get_sym_code_type): New function.
  28         (print_insn): Search for mapping symbols.
  29
  30 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
  31
  32         * score-dis.c (print_insn): Correct the error code to print
  33         correct PCE instruction disassembly.
  34
  35 2006-10-26  Ben Elliston  <bje@au.ibm.com>
  36             Anton Blanchard  <anton@samba.org>
  37             Peter Bergner  <bergner@vnet.ibm.com>
  38
  39         * ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH,
  40         AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define.
  41         (POWER6): Define.
  42         (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.",
  43         "frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.".
  44         Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd",
  45         "mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr",
  46         "lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix",
  47         "stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul",
  48         "dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.",
  49         "dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc",
  50         "dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix",
  51         "dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.",
  52         "ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.",
  53         "denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.",
  54         "dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.",
  55         "drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.",
  56         "dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq",
  57         "dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.",
  58         "dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.",
  59         "dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq",
  60         "drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.",
  61         "diexq" and "diexq." opcodes.
  62
  63 2006-10-26  Daniel Jacobowitz  <dan@codesourcery.com>
  64
  65         * h8300-dis.c (bfd_h8_disassemble): Add missing consts.
  66
  67 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
  68             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
  69             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
  70             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
  71             Alan Modra  <amodra@bigpond.net.au>
  72
  73         * spu-dis.c: New file.
  74         * spu-opc.c: New file.
  75         * configure.in: Add SPU support.
  76         * disassemble.c: Likewise.
  77         * Makefile.am: Likewise.  Run "make dep-am".
  78         * Makefile.in: Regenerate.
  79         * configure: Regenerate.
  80         * po/POTFILES.in: Regenerate.
  81
  82 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
  83
  84         * ppc-opc.c (CELL): New define.
  85         (powerpc_opcodes): Enable hrfid for Cell.  Add ldbrx and stdbrx,
  86         cell specific instructions.  Add {st,l}x{r,l}{,l} cell specific
  87         VMX instructions.
  88         * ppc-dis.c (powerpc_dialect): Handle cell.
  89
  90 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  91
  92         * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
  93         amdfam10 architecture.
  94         (PREGRP37): NEW.
  95         (print_insn): Disallow REP prefix for POPCNT.
  96
  97 2006-10-20  Andrew Stubbs  <andrew.stubbs@st.com>
  98
  99         * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
 100         duplicating it.
 101
 102 2006-10-18  Dave Brolley  <brolley@redhat.com>
 103
 104         * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
 105         * configure: Regenerated.
 106
 107 2006-09-29  Alan Modra  <amodra@bigpond.net.au>
 108
 109         * po/POTFILES.in: Regenerate.
 110
 111 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 112             Joseph Myers  <joseph@codesourcery.com>
 113             Ian Lance Taylor  <ian@wasabisystems.com>
 114             Ben Elliston  <bje@wasabisystems.com>
 115
 116         * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
 117         only be used with the default multiply-add operation, so if N is
 118         set, don't bother printing X.  Add new iwmmxt instructions.
 119         (IWMMXT_INSN_COUNT): Update.
 120         (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
 121         with a 'c' suffix.
 122         (print_insn_coprocessor): Check for iWMMXt2.  Handle format
 123         specifiers 'r', 'i'.
 124
 125 2006-09-24  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 126
 127         PR binutils/3100
 128         * i386-dis.c (prefix_user_table): Fix the second operand of
 129         maskmovdqu instruction to allow only %xmm register instead of
 130         both %xmm register and memory.
 131
 132 2006-09-23  H.J. Lu  <hongjiu.lu@intel.com>
 133
 134         PR binutils/3235
 135         * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
 136         address size prefix.
 137
 138 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 139
 140         * score-dis.c: New file.
 141         * score-opc.h: New file.
 142         * Makefile.am: Add Score files.
 143         * Makefile.in: Regenerate.
 144         * configure.in: Add support for Score target.
 145         * configure: Regenerate.
 146         * disassemble.c: Add support for Score target.
 147
 148 2006-09-16  Nick Clifton  <nickc@redhat.com>
 149             Pedro Alves  <pedro_alves@portugalmail.pt>
 150
 151         * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
 152         macros defined in bfd.h.
 153         * cris-dis.c: Likewise.
 154         * h8300-dis.c: Likewise.
 155         * i386-dis.c: Likewise.
 156         * ia64-gen.c: Likewise.
 157         * mips-dis: Likewise.
 158
 159 2006-09-04  Paul Brook  <paul@codesourcery.com>
 160
 161         * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
 162
 163 2006-08-23  H.J. Lu  <hongjiu.lu@intel.com>
 164
 165         * i386-dis.c (three_byte_table): Expand to 256 elements.
 166
 167 2006-08-04  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 168
 169         PR binutils/3000
 170         * i386-dis.c (MXC,EMC): Define.
 171         (OP_MXC): New function to handle cvt* (convert instructions) between
 172         %xmm and %mm register correctly.
 173         (OP_EMC): ditto.
 174         (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
 175         instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
 176         with EMC/MXC.
 177
 178 2006-07-29  Richard Sandiford  <richard@codesourcery.com>
 179
 180         * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
 181         "fdaddl" entry.
 182
 183 2006-07-19  Paul Brook  <paul@codesourcery.com>
 184
 185         * armd-dis.c (arm_opcodes): Fix rbit opcode.
 186
 187 2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 188
 189         * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
 190         "sldt", "str" and "smsw".
 191
 192 2006-07-15  H.J. Lu  <hongjiu.lu@intel.com>
 193
 194         PR binutils/2829
 195         * i386-dis.c (GRP11_C6): NEW.
 196         (GRP11_C7): Likewise.
 197         (GRP12): Updated.
 198         (GRP13): Likewise.
 199         (GRP14): Likewise.
 200         (GRP15): Likewise.
 201         (GRP16): Likewise.
 202         (GRPAMD): Likewise.
 203         (GRPPADLCK1): Likewise.
 204         (GRPPADLCK2): Likewise.
 205         (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
 206         respectively.
 207         (grps): Add entries for GRP11_C6 and GRP11_C7.
 208
 209 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 210            Michael Meissner             <michael.meissner@amd.com>
 211
 212         * i386-dis.c (dis386): Add support for 4 operand instructions. Add
 213         support for amdfam10 SSE4a/ABM instructions. Modify all
 214         initializer macros to have additional arguments. Disallow REP
 215         prefix for non-string instructions.
 216         (print_insn): Ditto.
 217
 218 2006-07-05  Julian Brown  <julian@codesourcery.com>
 219
 220         * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
 221
 222 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 223
 224         * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
 225         (twobyte_has_modrm): Set 1 for 0x1f.
 226
 227 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 228
 229         * i386-dis.c (NOP_Fixup): Removed.
 230         (NOP_Fixup1): New.
 231         (NOP_Fixup2): Likewise.
 232         (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
 233
 234 2006-06-12  Julian Brown  <julian@codesourcery.com>
 235
 236         * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
 237         on 64-bit hosts.
 238
 239 2006-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 240
 241         * i386.c (GRP10): Renamed to ...
 242         (GRP12): This.
 243         (GRP11): Renamed to ...
 244         (GRP13): This.
 245         (GRP12): Renamed to ...
 246         (GRP14): This.
 247         (GRP13): Renamed to ...
 248         (GRP15): This.
 249         (GRP14): Renamed to ...
 250         (GRP16): This.
 251         (dis386_twobyte): Updated.
 252         (grps): Likewise.
 253
 254 2006-06-09  Nick Clifton  <nickc@redhat.com>
 255
 256         * po/fi.po: Updated Finnish translation.
 257
 258 2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
 259
 260         * po/Make-in (pdf, ps): New dummy targets.
 261
 262 2006-06-06  Paul Brook  <paul@codesourcery.com>
 263
 264         * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
 265         instructions.
 266         (neon_opcodes): Add conditional execution specifiers.
 267         (thumb_opcodes): Ditto.
 268         (thumb32_opcodes): Ditto.
 269         (arm_conditional): Change 0xe to "al" and add "" to end.
 270         (ifthen_state, ifthen_next_state, ifthen_address): New.
 271         (IFTHEN_COND): Define.
 272         (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
 273         (print_insn_arm): Change %c to use new values of arm_conditional.
 274         (print_insn_thumb16): Print thumb conditions.  Add %I.
 275         (print_insn_thumb32): Print thumb conditions.
 276         (find_ifthen_state): New function.
 277         (print_insn): Track IT block state.
 278
 279 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 280             Anton Blanchard  <anton@samba.org>
 281             Peter Bergner  <bergner@vnet.ibm.com>
 282
 283         * ppc-dis.c (powerpc_dialect): Handle power6 option.
 284         (print_ppc_disassembler_options): Mention power6.
 285
 286 2006-06-06  Thiemo Seufer  <ths@mips.com>
 287             Chao-ying Fu  <fu@mips.com>
 288
 289         * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
 290         * mips-opc.c: Add DSP64 instructions.
 291
 292 2006-06-06  Alan Modra  <amodra@bigpond.net.au>
 293
 294         * m68hc11-dis.c (print_insn): Warning fix.
 295
 296 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 297
 298         * po/Make-in (top_builddir): Define.
 299
 300 2006-06-05  Alan Modra  <amodra@bigpond.net.au>
 301
 302         * Makefile.am: Run "make dep-am".
 303         * Makefile.in: Regenerate.
 304         * config.in: Regenerate.
 305
 306 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 307
 308         * Makefile.am (INCLUDES): Use @INCINTL@.
 309         * acinclude.m4: Include new gettext macros.
 310         * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
 311         Remove local code for po/Makefile.
 312         * Makefile.in, aclocal.m4, configure: Regenerated.
 313
 314 2006-05-30  Nick Clifton  <nickc@redhat.com>
 315
 316         * po/es.po: Updated Spanish translation.
 317
 318 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 319
 320         * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
 321         and fmovem entries.  Put register list entries before immediate
 322         mask entries.  Use "l" rather than "L" in the fmovem entries.
 323         * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
 324         out from INFO.
 325         (m68k_scan_mask): New function, split out from...
 326         (print_insn_m68k): ...here.  If no architecture has been set,
 327         first try printing an m680x0 instruction, then try a Coldfire one.
 328
 329 2006-05-24  Nick Clifton  <nickc@redhat.com>
 330
 331         * po/ga.po: Updated Irish translation.
 332
 333 2006-05-22  Nick Clifton  <nickc@redhat.com>
 334
 335         * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
 336
 337 2006-05-22  Nick Clifton  <nickc@redhat.com>
 338
 339         * po/nl.po: Updated translation.
 340
 341 2006-05-18  Alan Modra  <amodra@bigpond.net.au>
 342
 343         * avr-dis.c: Formatting fix.
 344
 345 2006-05-14  Thiemo Seufer  <ths@mips.com>
 346
 347         * mips16-opc.c (I1, I32, I64): New shortcut defines.
 348         (mips16_opcodes): Change membership of instructions to their
 349         lowest baseline ISA.
 350
 351 2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 352
 353         * i386-dis.c (grps): Update sgdt/sidt for 64bit.
 354
 355 2006-05-05  Julian Brown  <julian@codesourcery.com>
 356
 357         * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
 358         vldm/vstm.
 359
 360 2006-05-05  Thiemo Seufer  <ths@mips.com>
 361             David Ung  <davidu@mips.com>
 362
 363         * mips-opc.c: Add macro for cache instruction.
 364
 365 2006-05-04  Thiemo Seufer  <ths@mips.com>
 366             Nigel Stephens  <nigel@mips.com>
 367             David Ung  <davidu@mips.com>
 368
 369         * mips-dis.c (mips_arch_choices): Add smartmips instruction
 370         decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
 371         2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
 372         MIPS64R2.
 373         * mips-opc.c: fix random typos in comments.
 374         (INSN_SMARTMIPS): New defines.
 375         (mips_builtin_opcodes): Add paired single support for MIPS32R2.
 376         Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
 377         flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
 378         FP_S and FP_D flags to denote single and double register
 379         accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
 380         Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
 381         for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
 382         variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
 383         release 2 ISAs.
 384         * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
 385
 386 2006-05-03  Thiemo Seufer  <ths@mips.com>
 387
 388         * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
 389
 390 2006-05-02  Thiemo Seufer  <ths@mips.com>
 391             Nigel Stephens  <nigel@mips.com>
 392             David Ung  <davidu@mips.com>
 393
 394         * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
 395         (print_mips16_insn_arg): Force mips16 to odd addresses.
 396
 397 2006-04-30  Thiemo Seufer  <ths@mips.com>
 398             David Ung  <davidu@mips.com>
 399
 400         * mips-opc.c (mips_builtin_opcodes): Add udi instructions
 401         "udi0" to "udi15".
 402         * mips-dis.c (print_insn_args): Adds udi argument handling.
 403
 404 2006-04-28  James E Wilson  <wilson@specifix.com>
 405
 406         * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
 407         error message.
 408
 409 2006-04-28  Thiemo Seufer  <ths@mips.com>
 410             David Ung  <davidu@mips.com>
 411             Nigel Stephens  <nigel@mips.com>
 412
 413         * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
 414         names.
 415
 416 2006-04-28  Thiemo Seufer  <ths@mips.com>
 417             Nigel Stephens  <nigel@mips.com>
 418             David Ung  <davidu@mips.com>
 419
 420         * mips-dis.c (print_insn_args): Add mips_opcode argument.
 421         (print_insn_mips):  Adjust print_insn_args call.
 422
 423 2006-04-28  Thiemo Seufer  <ths@mips.com>
 424             Nigel Stephens  <nigel@mips.com>
 425
 426         * mips-dis.c (print_insn_args): Print $fcc only for FP
 427         instructions, use $cc elsewise.
 428
 429 2006-04-28  Thiemo Seufer  <ths@mips.com>
 430             Nigel Stephens  <nigel@mips.com>
 431
 432         * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
 433         Map MIPS16 registers to O32 names.
 434         (print_mips16_insn_arg): Use mips16_reg_names.
 435
 436 2006-04-26  Julian Brown  <julian@codesourcery.com>
 437
 438         * arm-dis.c (print_insn_neon): Disassemble floating-point constant
 439         VMOV.
 440
 441 2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
 442             Julian Brown  <julian@codesourcery.com>
 443
 444         * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
 445         %<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
 446         Add unified load/store instruction names.
 447         (neon_opcode_table): New.
 448         (arm_opcodes): Expand meaning of %<bitfield>['`?].
 449         (arm_decode_bitfield): New.
 450         (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
 451         Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
 452         (print_insn_neon): New.
 453         (print_insn_arm): Adjust print_insn_coprocessor call. Call
 454         print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
 455         (print_insn_thumb32): Likewise.
 456
 457 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 458
 459         * Makefile.am: Run "make dep-am".
 460         * Makefile.in: Regenerate.
 461
 462 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 463
 464         * avr-dis.c (avr_operand): Warning fix.
 465
 466         * configure: Regenerate.
 467
 468 2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
 469
 470         * po/POTFILES.in: Regenerated.
 471
 472 2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>
 473
 474         PR binutils/2454
 475         * avr-dis.c (avr_operand): Arrange for a comment to appear before
 476         the symolic form of an address, so that the output of objdump -d
 477         can be reassembled.
 478
 479 2006-04-10  DJ Delorie  <dj@redhat.com>
 480
 481         * m32c-asm.c: Regenerate.
 482
 483 2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
 484
 485         * Makefile.am: Add install-html target.
 486         * Makefile.in: Regenerate.
 487
 488 2006-04-06  Nick Clifton  <nickc@redhat.com>
 489
 490         * po/vi/po: Updated Vietnamese translation.
 491
 492 2006-03-31  Paul Koning  <ni1d@arrl.net>
 493
 494         * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
 495
 496 2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 497
 498         * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
 499         logic to identify halfword shifts.
 500
 501 2006-03-16  Paul Brook  <paul@codesourcery.com>
 502
 503         * arm-dis.c (arm_opcodes): Rename swi to svc.
 504         (thumb_opcodes): Ditto.
 505
 506 2006-03-13  DJ Delorie  <dj@redhat.com>
 507
 508         * m32c-asm.c: Regenerate.
 509         * m32c-desc.c: Likewise.
 510         * m32c-desc.h: Likewise.
 511         * m32c-dis.c: Likewise.
 512         * m32c-ibld.c: Likewise.
 513         * m32c-opc.c: Likewise.
 514         * m32c-opc.h: Likewise.
 515
 516 2006-03-10  DJ Delorie  <dj@redhat.com>
 517
 518         * m32c-desc.c: Regenerate with mul.l, mulu.l.
 519         * m32c-opc.c: Likewise.
 520         * m32c-opc.h: Likewise.
 521
 522
 523 2006-03-09  Nick Clifton  <nickc@redhat.com>
 524
 525         * po/sv.po: Updated Swedish translation.
 526
 527 2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 528
 529         PR binutils/2428
 530         * i386-dis.c (REP_Fixup): New function.
 531         (AL): Remove duplicate.
 532         (Xbr): New.
 533         (Xvr): Likewise.
 534         (Ybr): Likewise.
 535         (Yvr): Likewise.
 536         (indirDXr): Likewise.
 537         (ALr): Likewise.
 538         (eAXr): Likewise.
 539         (dis386): Updated entries of ins, outs, movs, lods and stos.
 540
 541 2006-03-05  Nick Clifton  <nickc@redhat.com>
 542
 543         * cgen-ibld.in (insert_normal): Cope with attempts to insert a
 544         signed 32-bit value into an unsigned 32-bit field when the host is
 545         a 64-bit machine.
 546         * fr30-ibld.c: Regenerate.
 547         * frv-ibld.c: Regenerate.
 548         * ip2k-ibld.c: Regenerate.
 549         * iq2000-asm.c: Regenerate.
 550         * iq2000-ibld.c: Regenerate.
 551         * m32c-ibld.c: Regenerate.
 552         * m32r-ibld.c: Regenerate.
 553         * openrisc-ibld.c: Regenerate.
 554         * xc16x-ibld.c: Regenerate.
 555         * xstormy16-ibld.c: Regenerate.
 556
 557 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 558
 559         * xc16x-asm.c: Regenerate.
 560         * xc16x-dis.c: Regenerate.
 561
 562 2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 563
 564         * po/Make-in: Add html target.
 565
 566 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 567
 568         * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
 569         Intel Merom New Instructions.
 570         (THREE_BYTE_0): Likewise.
 571         (THREE_BYTE_1): Likewise.
 572         (three_byte_table): Likewise.
 573         (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
 574         THREE_BYTE_1 for entry 0x3a.
 575         (twobyte_has_modrm): Updated.
 576         (twobyte_uses_SSE_prefix): Likewise.
 577         (print_insn): Handle 3-byte opcodes used by Intel Merom New
 578         Instructions.
 579
 580 2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
 581
 582         * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
 583         (v9_hpriv_reg_names): New table.
 584         (print_insn_sparc): Allow values up to 16 for '?' and '!'.
 585         New cases '$' and '%' for read/write hyperprivileged register.
 586         * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
 587         window handling and rdhpr/wrhpr instructions.
 588
 589 2006-02-24  DJ Delorie  <dj@redhat.com>
 590
 591         * m32c-desc.c: Regenerate with linker relaxation attributes.
 592         * m32c-desc.h: Likewise.
 593         * m32c-dis.c: Likewise.
 594         * m32c-opc.c: Likewise.
 595
 596 2006-02-24  Paul Brook  <paul@codesourcery.com>
 597
 598         * arm-dis.c (arm_opcodes): Add V7 instructions.
 599         (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
 600         (print_arm_address): New function.
 601         (print_insn_arm): Use it.  Add 'P' and 'U' cases.
 602         (psr_name): New function.
 603         (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 604
 605 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 606
 607         * ia64-opc-i.c (bXc): New.
 608         (mXc): Likewise.
 609         (OpX2TaTbYaXcC): Likewise.
 610         (TF). Likewise.
 611         (TFCM). Likewise.
 612         (ia64_opcodes_i): Add instructions for tf.
 613
 614         * ia64-opc.h (IMMU5b): New.
 615
 616         * ia64-asmtab.c: Regenerated.
 617
 618 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 619
 620         * ia64-gen.c: Update copyright years.
 621         * ia64-opc-b.c: Likewise.
 622
 623 2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 624
 625         * ia64-gen.c (lookup_regindex): Handle ".vm".
 626         (print_dependency_table): Handle '\"'.
 627
 628         * ia64-ic.tbl: Updated from SDM 2.2.
 629         * ia64-raw.tbl: Likewise.
 630         * ia64-waw.tbl: Likewise.
 631         * ia64-asmtab.c: Regenerated.
 632
 633         * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 634
 635 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 636             Anil Paranjape   <anilp1@kpitcummins.com>
 637             Shilin Shakti    <shilins@kpitcummins.com>
 638
 639         * xc16x-desc.h: New file
 640         * xc16x-desc.c: New file
 641         * xc16x-opc.h: New file
 642         * xc16x-opc.c: New file
 643         * xc16x-ibld.c: New file
 644         * xc16x-asm.c: New file
 645         * xc16x-dis.c: New file
 646         * Makefile.am: Entries for xc16x
 647         * Makefile.in: Regenerate
 648         * cofigure.in: Add xc16x target information.
 649         * configure: Regenerate.
 650         * disassemble.c: Add xc16x target information.
 651
 652 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 653
 654         * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
 655         moves.
 656
 657 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 658
 659         * i386-dis.c ('Z'): Add a new macro.
 660         (dis386_twobyte): Use "movZ" for control register moves.
 661
 662 2006-02-10  Nick Clifton  <nickc@redhat.com>
 663
 664         * iq2000-asm.c: Regenerate.
 665
 666 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 667
 668         * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
 669
 670 2006-01-26  David Ung  <davidu@mips.com>
 671
 672         * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
 673         ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
 674         floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
 675         nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
 676         rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 677
 678 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 679
 680         * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
 681         ld_d_r, pref_xd_cb): Use signed char to hold data to be
 682         disassembled.
 683         * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
 684         buffer overflows when disassembling instructions like
 685         ld (ix+123),0x23
 686         * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
 687         operand, if the offset is negative.
 688
 689 2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>
 690
 691         * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
 692         unsigned char to hold data to be disassembled.
 693
 694 2006-01-17  Andreas Schwab  <schwab@suse.de>
 695
 696         PR binutils/1486
 697         * disassemble.c (disassemble_init_for_target): Set
 698         disassembler_needs_relocs for bfd_arch_arm.
 699
 700 2006-01-16  Paul Brook  <paul@codesourcery.com>
 701
 702         * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
 703         f?add?, and f?sub? instructions.
 704
 705 2006-01-16  Nick Clifton  <nickc@redhat.com>
 706
 707         * po/zh_CN.po: New Chinese (simplified) translation.
 708         * configure.in (ALL_LINGUAS): Add "zh_CH".
 709         * configure: Regenerate.
 710
 711 2006-01-05  Paul Brook  <paul@codesourcery.com>
 712
 713         * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 714
 715 2006-01-06  DJ Delorie  <dj@redhat.com>
 716
 717         * m32c-desc.c: Regenerate.
 718         * m32c-opc.c: Regenerate.
 719         * m32c-opc.h: Regenerate.
 720
 721 2006-01-03  DJ Delorie  <dj@redhat.com>
 722
 723         * cgen-ibld.in (extract_normal): Avoid memory range errors.
 724         * m32c-ibld.c: Regenerated.
 725
 726 For older changes see ChangeLog-2005
 727 \f
 728 Local Variables:
 729 mode: change-log
 730 left-margin: 8
 731 fill-column: 74
 732 version-control: never
 733 End: