opcodes/ChangeLog

   1 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
   2             Michael Collison <michael.collison@arm.com>
   3
   4         * arm-dis.c (enum mve_instructions): Add new instructions.
   5         (enum mve_unpredictable): Add new reasons.
   6         (enum mve_undefined): Likewise.
   7         (is_mve_undefined): Handle new instructions.
   8         (is_mve_unpredictable): Likewise.
   9         (print_mve_undefined): Likewise.
  10         (print_mve_unpredictable): Likewise.
  11         (print_mve_size): Likewise.
  12         (print_insn_mve): Likewise.
  13
  14 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  15             Michael Collison <michael.collison@arm.com>
  16
  17         * arm-dis.c (enum mve_instructions): Add new instructions.
  18         (enum mve_undefined): Add new reasons.
  19         (insns): Add new instructions.
  20         (is_mve_encoding_conflict):
  21         (print_mve_vld_str_addr): New print function.
  22         (is_mve_undefined): Handle new instructions.
  23         (is_mve_unpredictable): Likewise.
  24         (print_mve_undefined): Likewise.
  25         (print_mve_size): Likewise.
  26         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
  27         (print_insn_mve):  Handle new operands.
  28
  29 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  30             Michael Collison <michael.collison@arm.com>
  31
  32         * arm-dis.c (enum mve_instructions): Add new instructions.
  33         (enum mve_unpredictable): Add new reasons.
  34         (is_mve_encoding_conflict): Handle new instructions.
  35         (is_mve_unpredictable): Likewise.
  36         (mve_opcodes): Add new instructions.
  37         (print_mve_unpredictable): Handle new reasons.
  38         (print_mve_register_blocks): New print function.
  39         (print_mve_size): Handle new instructions.
  40         (print_insn_mve): Likewise.
  41
  42 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  43             Michael Collison <michael.collison@arm.com>
  44
  45         * arm-dis.c (enum mve_instructions): Add new instructions.
  46         (enum mve_unpredictable): Add new reasons.
  47         (enum mve_undefined): Likewise.
  48         (is_mve_encoding_conflict): Handle new instructions.
  49         (is_mve_undefined): Likewise.
  50         (is_mve_unpredictable): Likewise.
  51         (coprocessor_opcodes): Move NEON VDUP from here...
  52         (neon_opcodes): ... to here.
  53         (mve_opcodes): Add new instructions.
  54         (print_mve_undefined):  Handle new reasons.
  55         (print_mve_unpredictable): Likewise.
  56         (print_mve_size): Handle new instructions.
  57         (print_insn_neon): Handle vdup.
  58         (print_insn_mve): Handle new operands.
  59
  60 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  61             Michael Collison <michael.collison@arm.com>
  62
  63         * arm-dis.c (enum mve_instructions): Add new instructions.
  64         (enum mve_unpredictable): Add new values.
  65         (mve_opcodes): Add new instructions.
  66         (vec_condnames): New array with vector conditions.
  67         (mve_predicatenames): New array with predicate suffixes.
  68         (mve_vec_sizename): New array with vector sizes.
  69         (enum vpt_pred_state): New enum with vector predication states.
  70         (struct vpt_block): New struct type for vpt blocks.
  71         (vpt_block_state): Global struct to keep track of state.
  72         (mve_extract_pred_mask): New helper function.
  73         (num_instructions_vpt_block): Likewise.
  74         (mark_outside_vpt_block): Likewise.
  75         (mark_inside_vpt_block): Likewise.
  76         (invert_next_predicate_state): Likewise.
  77         (update_next_predicate_state): Likewise.
  78         (update_vpt_block_state): Likewise.
  79         (is_vpt_instruction): Likewise.
  80         (is_mve_encoding_conflict): Add entries for new instructions.
  81         (is_mve_unpredictable): Likewise.
  82         (print_mve_unpredictable): Handle new cases.
  83         (print_instruction_predicate): Likewise.
  84         (print_mve_size): New function.
  85         (print_vec_condition): New function.
  86         (print_insn_mve): Handle vpt blocks and new print operands.
  87
  88 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  89
  90         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
  91         8, 14 and 15 for Armv8.1-M Mainline.
  92
  93 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  94             Michael Collison <michael.collison@arm.com>
  95
  96         * arm-dis.c (enum mve_instructions): New enum.
  97         (enum mve_unpredictable): Likewise.
  98         (enum mve_undefined): Likewise.
  99         (struct mopcode32): New struct.
 100         (is_mve_okay_in_it): New function.
 101         (is_mve_architecture): Likewise.
 102         (arm_decode_field): Likewise.
 103         (arm_decode_field_multiple): Likewise.
 104         (is_mve_encoding_conflict): Likewise.
 105         (is_mve_undefined): Likewise.
 106         (is_mve_unpredictable): Likewise.
 107         (print_mve_undefined): Likewise.
 108         (print_mve_unpredictable): Likewise.
 109         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 110         (print_insn_mve): New function.
 111         (print_insn_thumb32): Handle MVE architecture.
 112         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 113
 114 2019-05-10  Nick Clifton  <nickc@redhat.com>
 115
 116         PR 24538
 117         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 118         end of the table prematurely.
 119
 120 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 121
 122         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 123         macros for R6.
 124
 125 2019-05-11  Alan Modra  <amodra@gmail.com>
 126
 127         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 128         when -Mraw is in effect.
 129
 130 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 131
 132         * aarch64-dis-2.c: Regenerate.
 133         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 134         (OP_SVE_BBB): New variant set.
 135         (OP_SVE_DDDD): New variant set.
 136         (OP_SVE_HHH): New variant set.
 137         (OP_SVE_HHHU): New variant set.
 138         (OP_SVE_SSS): New variant set.
 139         (OP_SVE_SSSU): New variant set.
 140         (OP_SVE_SHH): New variant set.
 141         (OP_SVE_SBBU): New variant set.
 142         (OP_SVE_DSS): New variant set.
 143         (OP_SVE_DHHU): New variant set.
 144         (OP_SVE_VMV_HSD_BHS): New variant set.
 145         (OP_SVE_VVU_HSD_BHS): New variant set.
 146         (OP_SVE_VVVU_SD_BH): New variant set.
 147         (OP_SVE_VVVU_BHSD): New variant set.
 148         (OP_SVE_VVV_QHD_DBS): New variant set.
 149         (OP_SVE_VVV_HSD_BHS): New variant set.
 150         (OP_SVE_VVV_HSD_BHS2): New variant set.
 151         (OP_SVE_VVV_BHS_HSD): New variant set.
 152         (OP_SVE_VV_BHS_HSD): New variant set.
 153         (OP_SVE_VVV_SD): New variant set.
 154         (OP_SVE_VVU_BHS_HSD): New variant set.
 155         (OP_SVE_VZVV_SD): New variant set.
 156         (OP_SVE_VZVV_BH): New variant set.
 157         (OP_SVE_VZV_SD): New variant set.
 158         (aarch64_opcode_table): Add sve2 instructions.
 159
 160 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 161
 162         * aarch64-asm-2.c: Regenerated.
 163         * aarch64-dis-2.c: Regenerated.
 164         * aarch64-opc-2.c: Regenerated.
 165         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 166         for SVE_SHLIMM_UNPRED_22.
 167         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 168         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 169         operand.
 170
 171 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 172
 173         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 174         sve_size_tsz_bhs iclass encode.
 175         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 176         sve_size_tsz_bhs iclass decode.
 177
 178 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 179
 180         * aarch64-asm-2.c: Regenerated.
 181         * aarch64-dis-2.c: Regenerated.
 182         * aarch64-opc-2.c: Regenerated.
 183         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 184         for SVE_Zm4_11_INDEX.
 185         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 186         (fields): Handle SVE_i2h field.
 187         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 188         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 189
 190 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 191
 192         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 193         sve_shift_tsz_bhsd iclass encode.
 194         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 195         sve_shift_tsz_bhsd iclass decode.
 196
 197 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 198
 199         * aarch64-asm-2.c: Regenerated.
 200         * aarch64-dis-2.c: Regenerated.
 201         * aarch64-opc-2.c: Regenerated.
 202         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 203         (aarch64_encode_variant_using_iclass): Handle
 204         sve_shift_tsz_hsd iclass encode.
 205         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 206         sve_shift_tsz_hsd iclass decode.
 207         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 208         for SVE_SHRIMM_UNPRED_22.
 209         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 210         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 211         operand.
 212
 213 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 214
 215         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 216         sve_size_013 iclass encode.
 217         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 218         sve_size_013 iclass decode.
 219
 220 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 221
 222         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 223         sve_size_bh iclass encode.
 224         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 225         sve_size_bh iclass decode.
 226
 227 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 228
 229         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 230         sve_size_sd2 iclass encode.
 231         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 232         sve_size_sd2 iclass decode.
 233         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 234         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 235
 236 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 237
 238         * aarch64-asm-2.c: Regenerated.
 239         * aarch64-dis-2.c: Regenerated.
 240         * aarch64-opc-2.c: Regenerated.
 241         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 242         for SVE_ADDR_ZX.
 243         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 244         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 245
 246 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 247
 248         * aarch64-asm-2.c: Regenerated.
 249         * aarch64-dis-2.c: Regenerated.
 250         * aarch64-opc-2.c: Regenerated.
 251         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 252         for SVE_Zm3_11_INDEX.
 253         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 254         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 255         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 256         fields.
 257         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 258
 259 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 260
 261         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 262         sve_size_hsd2 iclass encode.
 263         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 264         sve_size_hsd2 iclass decode.
 265         * aarch64-opc.c (fields): Handle SVE_size field.
 266         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 267
 268 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 269
 270         * aarch64-asm-2.c: Regenerated.
 271         * aarch64-dis-2.c: Regenerated.
 272         * aarch64-opc-2.c: Regenerated.
 273         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 274         for SVE_IMM_ROT3.
 275         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 276         (fields): Handle SVE_rot3 field.
 277         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 278         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 279
 280 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 281
 282         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 283         instructions.
 284
 285 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 286
 287         * aarch64-tbl.h
 288         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 289         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 290         aarch64_feature_sve2bitperm): New feature sets.
 291         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 292         for feature set addresses.
 293         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 294         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 295
 296 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 297             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 298
 299         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 300         argument and set ASE_EVA_R6 appropriately.
 301         (set_default_mips_dis_options): Pass ISA to above.
 302         (parse_mips_dis_option): Likewise.
 303         * mips-opc.c (EVAR6): New macro.
 304         (mips_builtin_opcodes): Add llwpe, scwpe.
 305
 306 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 307
 308         * aarch64-asm-2.c: Regenerated.
 309         * aarch64-dis-2.c: Regenerated.
 310         * aarch64-opc-2.c: Regenerated.
 311         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 312         AARCH64_OPND_TME_UIMM16.
 313         (aarch64_print_operand): Likewise.
 314         * aarch64-tbl.h (QL_IMM_NIL): New.
 315         (TME): New.
 316         (_TME_INSN): New.
 317         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 318
 319 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 320
 321         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 322
 323 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 324             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 325
 326         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 327
 328 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 329
 330         * s12z-opc.h: Add extern "C" bracketing to help
 331         users who wish to use this interface in c++ code.
 332
 333 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 334
 335         * s12z-opc.c (bm_decode): Handle bit map operations with the
 336         "reserved0" mode.
 337
 338 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 339
 340         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 341         specifier.  Add entries for VLDR and VSTR of system registers.
 342         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 343         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 344         of %J and %K format specifier.
 345
 346 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 347
 348         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 349         Add new entries for VSCCLRM instruction.
 350         (print_insn_coprocessor): Handle new %C format control code.
 351
 352 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 353
 354         * arm-dis.c (enum isa): New enum.
 355         (struct sopcode32): New structure.
 356         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 357         set isa field of all current entries to ANY.
 358         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 359         Only match an entry if its isa field allows the current mode.
 360
 361 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 362
 363         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 364         CLRM.
 365         (print_insn_thumb32): Add logic to print %n CLRM register list.
 366
 367 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 368
 369         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 370         and %Q patterns.
 371
 372 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 373
 374         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 375         (print_insn_thumb32): Edit the switch case for %Z.
 376
 377 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 378
 379         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 380
 381 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 382
 383         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 384
 385 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 386
 387         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 388
 389 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 390
 391         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 392         Arm register with r13 and r15 unpredictable.
 393         (thumb32_opcodes): New instructions for bfx and bflx.
 394
 395 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 396
 397         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 398
 399 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 400
 401         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 402
 403 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 404
 405         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 406
 407 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 408
 409         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 410
 411 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 412
 413         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 414         "optr". ("operator" is a reserved word in c++).
 415
 416 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 417
 418         * aarch64-opc.c (aarch64_print_operand): Add case for
 419         AARCH64_OPND_Rt_SP.
 420         (verify_constraints): Likewise.
 421         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 422         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 423         to accept Rt|SP as first operand.
 424         (AARCH64_OPERANDS): Add new Rt_SP.
 425         * aarch64-asm-2.c: Regenerated.
 426         * aarch64-dis-2.c: Regenerated.
 427         * aarch64-opc-2.c: Regenerated.
 428
 429 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 430
 431         * aarch64-asm-2.c: Regenerated.
 432         * aarch64-dis-2.c: Likewise.
 433         * aarch64-opc-2.c: Likewise.
 434         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 435
 436 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 437
 438         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 439
 440 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 441
 442         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 443         * i386-init.h: Regenerated.
 444
 445 2019-04-07  Alan Modra  <amodra@gmail.com>
 446
 447         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 448         op_separator to control printing of spaces, comma and parens
 449         rather than need_comma, need_paren and spaces vars.
 450
 451 2019-04-07  Alan Modra  <amodra@gmail.com>
 452
 453         PR 24421
 454         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 455         (print_insn_neon, print_insn_arm): Likewise.
 456
 457 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 458
 459         * i386-dis-evex.h (evex_table): Updated to support BF16
 460         instructions.
 461         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 462         and EVEX_W_0F3872_P_3.
 463         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 464         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 465         * i386-opc.h (enum): Add CpuAVX512_BF16.
 466         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 467         * i386-opc.tbl: Add AVX512 BF16 instructions.
 468         * i386-init.h: Regenerated.
 469         * i386-tbl.h: Likewise.
 470
 471 2019-04-05  Alan Modra  <amodra@gmail.com>
 472
 473         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 474         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 475         to favour printing of "-" branch hint when using the "y" bit.
 476         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 477
 478 2019-04-05  Alan Modra  <amodra@gmail.com>
 479
 480         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 481         opcode until first operand is output.
 482
 483 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 484
 485         PR gas/24349
 486         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 487         (valid_bo_post_v2): Add support for 'at' branch hints.
 488         (insert_bo): Only error on branch on ctr.
 489         (get_bo_hint_mask): New function.
 490         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 491         for inserting 'at' branch hints.
 492         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 493         for extracting 'at' branch hints.
 494         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 495         (BOE): Delete operand.
 496         (BOM, BOP): New operands.
 497         (RM): Update value.
 498         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 499         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 500         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 501         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 502         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 503         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 504         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 505         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 506         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 507         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 508         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 509         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 510         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 511         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 512         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 513         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 514         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 515         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 516         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 517         bttarl+>: New extended mnemonics.
 518
 519 2019-03-28  Alan Modra  <amodra@gmail.com>
 520
 521         PR 24390
 522         * ppc-opc.c (BTF): Define.
 523         (powerpc_opcodes): Use for mtfsb*.
 524         * ppc-dis.c (print_insn_powerpc): Print fields with both
 525         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 526
 527 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 528
 529         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 530         (mapping_symbol_for_insn): Implement new algorithm.
 531         (print_insn): Remove duplicate code.
 532
 533 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 534
 535         * aarch64-dis.c (print_insn_aarch64):
 536         Implement override.
 537
 538 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 539
 540         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 541         order.
 542
 543 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 544
 545         * aarch64-dis.c (last_stop_offset): New.
 546         (print_insn_aarch64): Use stop_offset.
 547
 548 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 549
 550         PR gas/24359
 551         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 552         CPU_ANY_AVX2_FLAGS.
 553         * i386-init.h: Regenerated.
 554
 555 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 556
 557         PR gas/24348
 558         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 559         vmovdqu16, vmovdqu32 and vmovdqu64.
 560         * i386-tbl.h: Regenerated.
 561
 562 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 563
 564         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 565         from vstrszb, vstrszh, and vstrszf.
 566
 567 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 568
 569         * s390-opc.txt: Add instruction descriptions.
 570
 571 2019-02-08  Jim Wilson  <jimw@sifive.com>
 572
 573         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 574         <bne>: Likewise.
 575
 576 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 577
 578         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 579
 580 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 581
 582         PR binutils/23212
 583         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 584         * aarch64-opc.c (verify_elem_sd): New.
 585         (fields): Add FLD_sz entr.
 586         * aarch64-tbl.h (_SIMD_INSN): New.
 587         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 588         fmulx scalar and vector by element isns.
 589
 590 2019-02-07  Nick Clifton  <nickc@redhat.com>
 591
 592         * po/sv.po: Updated Swedish translation.
 593
 594 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 595
 596         * s390-mkopc.c (main): Accept arch13 as cpu string.
 597         * s390-opc.c: Add new instruction formats and instruction opcode
 598         masks.
 599         * s390-opc.txt: Add new arch13 instructions.
 600
 601 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 602
 603         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 604         (aarch64_opcode): Change encoding for stg, stzg
 605         st2g and st2zg.
 606         * aarch64-asm-2.c: Regenerated.
 607         * aarch64-dis-2.c: Regenerated.
 608         * aarch64-opc-2.c: Regenerated.
 609
 610 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 611
 612         * aarch64-asm-2.c: Regenerated.
 613         * aarch64-dis-2.c: Likewise.
 614         * aarch64-opc-2.c: Likewise.
 615         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 616
 617 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 618             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 619
 620         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 621         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 622         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 623         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 624         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 625         case for ldstgv_indexed.
 626         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 627         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 628         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 629         * aarch64-asm-2.c: Regenerated.
 630         * aarch64-dis-2.c: Regenerated.
 631         * aarch64-opc-2.c: Regenerated.
 632
 633 2019-01-23  Nick Clifton  <nickc@redhat.com>
 634
 635         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 636
 637 2019-01-21  Nick Clifton  <nickc@redhat.com>
 638
 639         * po/de.po: Updated German translation.
 640         * po/uk.po: Updated Ukranian translation.
 641
 642 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 643         * mips-dis.c (mips_arch_choices): Fix typo in
 644         gs464, gs464e and gs264e descriptors.
 645
 646 2019-01-19  Nick Clifton  <nickc@redhat.com>
 647
 648         * configure: Regenerate.
 649         * po/opcodes.pot: Regenerate.
 650
 651 2018-06-24  Nick Clifton  <nickc@redhat.com>
 652
 653         2.32 branch created.
 654
 655 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 656
 657         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 658         if it is null.
 659         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 660         zero.
 661
 662 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 663
 664         * configure: Regenerate.
 665
 666 2019-01-07  Alan Modra  <amodra@gmail.com>
 667
 668         * configure: Regenerate.
 669         * po/POTFILES.in: Regenerate.
 670
 671 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 672
 673         * s12z-opc.c: New file.
 674         * s12z-opc.h: New file.
 675         * s12z-dis.c: Removed all code not directly related to display
 676         of instructions.  Used the interface provided by the new files
 677         instead.
 678         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 679         * Makefile.in: Regenerate.
 680         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 681         * configure: Regenerate.
 682
 683 2019-01-01  Alan Modra  <amodra@gmail.com>
 684
 685         Update year range in copyright notice of all files.
 686
 687 For older changes see ChangeLog-2018
 688 \f
 689 Copyright (C) 2019 Free Software Foundation, Inc.
 690
 691 Copying and distribution of this file, with or without modification,
 692 are permitted in any medium without royalty provided the copyright
 693 notice and this notice are preserved.
 694
 695 Local Variables:
 696 mode: change-log
 697 left-margin: 8
 698 fill-column: 74
 699 version-control: never
 700 End: