1 2017-11-09 Tamar Christina <tamar.christina@arm.com>
3 * aarch64-asm.h (ins_addr_offset): New.
4 * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
5 (aarch64_ins_addr_offset): New.
6 * aarch64-asm-2.c: Regenerate.
7 * aarch64-dis.h (ext_addr_offset): New.
8 * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
9 (aarch64_ext_addr_offset): New.
10 * aarch64-dis-2.c: Regenerate.
11 * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
12 FLD_imm4_2 and FLD_SM3_imm2.
13 * aarch64-opc.c (fields): Add FLD_imm6_2,
14 FLD_imm4_2 and FLD_SM3_imm2.
15 (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
16 (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
17 AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
18 * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
20 (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
22 2017-11-09 Tamar Christina <tamar.christina@arm.com>
25 (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
26 (aarch64_feature_sm4, aarch64_feature_sha3): New.
27 (aarch64_feature_fp_16_v8_2): New.
28 (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
29 (V8_4_INSN, CRYPTO_V8_2_INSN): New.
30 (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
32 2017-11-08 Tamar Christina <tamar.christina@arm.com>
34 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
35 (aarch64_feature_sha2, aarch64_feature_aes): New.
37 (AES_INSN, SHA2_INSN): New.
38 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
39 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
40 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
43 2017-11-08 Jiong Wang <jiong.wang@arm.com>
44 Tamar Christina <tamar.christina@arm.com>
46 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
47 FP16 instructions, including vfmal.f16 and vfmsl.f16.
49 2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
51 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
53 2017-11-07 Alan Modra <amodra@gmail.com>
55 * opintl.h: Formatting, comment fixes.
56 (gettext, ngettext): Redefine when ENABLE_NLS.
57 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
58 (_): Define using gettext.
59 (textdomain, bindtextdomain): Use safer "do nothing".
61 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
63 * arc-dis.c (print_hex): New variable.
64 (parse_option): Check for hex option.
65 (print_insn_arc): Use hexadecimal representation for short
66 immediate values when requested.
67 (print_arc_disassembler_options): Add hex option to the list.
69 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
71 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
72 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
73 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
74 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
75 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
76 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
77 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
78 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
79 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
80 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
81 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
82 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
83 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
84 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
85 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
86 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
87 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
88 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
89 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
91 (prealloc, prefetch*): Place them before ld instruction.
92 * arc-opc.c (skip_this_opcode): Add ARITH class.
94 2017-10-25 Alan Modra <amodra@gmail.com>
97 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
98 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
99 (imm4flag, size_changed): Likewise.
100 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
101 (words, allWords, processing_argument_number): Likewise.
102 (cst4flag, size_changed): Likewise.
103 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
104 (crx_cst4_maps): Rename from cst4_maps.
105 (crx_no_op_insn): Rename from no_op_insn.
107 2017-10-24 Andrew Waterman <andrew@sifive.com>
109 * riscv-opc.c (match_c_addi16sp) : New function.
110 (match_c_addi4spn): New function.
111 (match_c_lui): Don't allow 0-immediate encodings.
112 (riscv_opcodes) <addi>: Use the above functions.
114 <c.addi4spn>: Likewise.
115 <c.addi16sp>: Likewise.
117 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
119 * i386-init.h: Regenerate
120 * i386-tbl.h: Likewise
122 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
124 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
125 (enum): Add EVEX_W_0F3854_P_2.
126 * i386-dis-evex.h (evex_table): Updated.
127 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
128 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
129 (cpu_flags): Add CpuAVX512_BITALG.
130 * i386-opc.h (enum): Add CpuAVX512_BITALG.
131 (i386_cpu_flags): Add cpuavx512_bitalg..
132 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
133 * i386-init.h: Regenerate.
134 * i386-tbl.h: Likewise.
136 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
138 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
139 * i386-dis-evex.h (evex_table): Updated.
140 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
141 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
142 (cpu_flags): Add CpuAVX512_VNNI.
143 * i386-opc.h (enum): Add CpuAVX512_VNNI.
144 (i386_cpu_flags): Add cpuavx512_vnni.
145 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
146 * i386-init.h: Regenerate.
147 * i386-tbl.h: Likewise.
149 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
151 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
152 (enum): Remove VEX_LEN_0F3A44_P_2.
153 (vex_len_table): Ditto.
154 (enum): Remove VEX_W_0F3A44_P_2.
155 (vew_w_table): Ditto.
156 (prefix_table): Adjust instructions (see prefixes above).
157 * i386-dis-evex.h (evex_table):
158 Add new instructions (see prefixes above).
159 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
160 (bitfield_cpu_flags): Ditto.
161 * i386-opc.h (enum): Ditto.
162 (i386_cpu_flags): Ditto.
163 (CpuUnused): Comment out to avoid zero-width field problem.
164 * i386-opc.tbl (vpclmulqdq): New instruction.
165 * i386-init.h: Regenerate.
168 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
170 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
171 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
172 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
173 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
174 (vex_len_table): Ditto.
175 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
176 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
177 (vew_w_table): Ditto.
178 (prefix_table): Adjust instructions (see prefixes above).
179 * i386-dis-evex.h (evex_table):
180 Add new instructions (see prefixes above).
181 * i386-gen.c (cpu_flag_init): Add VAES.
182 (bitfield_cpu_flags): Ditto.
183 * i386-opc.h (enum): Ditto.
184 (i386_cpu_flags): Ditto.
185 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
186 * i386-init.h: Regenerate.
189 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
191 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
192 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
193 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
194 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
195 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
196 (prefix_table): Updated (see prefixes above).
197 (three_byte_table): Likewise.
198 (vex_w_table): Likewise.
199 * i386-dis-evex.h: Likewise.
200 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
201 (cpu_flags): Add CpuGFNI.
202 * i386-opc.h (enum): Add CpuGFNI.
203 (i386_cpu_flags): Add cpugfni.
204 * i386-opc.tbl: Add Intel GFNI instructions.
205 * i386-init.h: Regenerate.
206 * i386-tbl.h: Likewise.
208 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
210 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
211 Define EXbScalar and EXwScalar for OP_EX.
212 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
213 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
214 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
215 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
216 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
217 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
218 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
219 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
220 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
221 (OP_E_memory): Likewise.
222 * i386-dis-evex.h: Updated.
223 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
224 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
225 (cpu_flags): Add CpuAVX512_VBMI2.
226 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
227 (i386_cpu_flags): Add cpuavx512_vbmi2.
228 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
229 * i386-init.h: Regenerate.
230 * i386-tbl.h: Likewise.
232 2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
234 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
236 2017-10-12 James Bowman <james.bowman@ftdichip.com>
238 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
239 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
240 K15. Add jmpix pattern.
242 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
244 * s390-opc.txt (prno, tpei, irbm): New instructions added.
246 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
248 * s390-opc.c (INSTR_SI_RD): New macro.
249 (INSTR_S_RD): Adjust example instruction.
250 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
253 2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
255 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
256 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
257 VLE multimple load/store instructions. Old e_ldm* variants are
259 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
261 2017-09-27 Nick Clifton <nickc@redhat.com>
264 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
265 names for the fmv.x.s and fmv.s.x instructions respectively.
267 2017-09-26 do <do@nerilex.org>
270 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
271 be used on CPUs that have emacs support.
273 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
275 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
277 2017-09-09 Kamil Rytarowski <n54@gmx.com>
279 * nds32-asm.c: Rename __BIT() to N32_BIT().
280 * nds32-asm.h: Likewise.
281 * nds32-dis.c: Likewise.
283 2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
285 * i386-dis.c (last_active_prefix): Removed.
286 (ckprefix): Don't set last_active_prefix.
287 (NOTRACK_Fixup): Don't check last_active_prefix.
289 2017-08-31 Nick Clifton <nickc@redhat.com>
291 * po/fr.po: Updated French translation.
293 2017-08-31 James Bowman <james.bowman@ftdichip.com>
295 * ft32-dis.c (print_insn_ft32): Correct display of non-address
298 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
299 Edmar Wienskoski <edmar.wienskoski@nxp.com>
301 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
302 PPC_OPCODE_EFS2 flag to "e200z4" entry.
303 New entries efs2 and spe2.
304 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
305 (SPE2_OPCD_SEGS): New macro.
306 (spe2_opcd_indices): New.
307 (disassemble_init_powerpc): Handle SPE2 opcodes.
308 (lookup_spe2): New function.
309 (print_insn_powerpc): call lookup_spe2.
310 * ppc-opc.c (insert_evuimm1_ex0): New function.
311 (extract_evuimm1_ex0): Likewise.
312 (insert_evuimm_lt8): Likewise.
313 (extract_evuimm_lt8): Likewise.
314 (insert_off_spe2): Likewise.
315 (extract_off_spe2): Likewise.
316 (insert_Ddd): Likewise.
317 (extract_Ddd): Likewise.
319 (EVUIMM_LT8): Likewise.
320 (EVUIMM_LT16): Adjust.
322 (EVUIMM_1): Likewise.
323 (EVUIMM_1_EX0): Likewise.
326 (VX_OFF_SPE2): Likewise.
329 (VX_MASK_DDD): New mask.
331 (VX_RA_CONST): New macro.
332 (VX_RA_CONST_MASK): Likewise.
333 (VX_RB_CONST): Likewise.
334 (VX_RB_CONST_MASK): Likewise.
335 (VX_OFF_SPE2_MASK): Likewise.
336 (VX_SPE_CRFD): Likewise.
337 (VX_SPE_CRFD_MASK VX): Likewise.
338 (VX_SPE2_CLR): Likewise.
339 (VX_SPE2_CLR_MASK): Likewise.
340 (VX_SPE2_SPLATB): Likewise.
341 (VX_SPE2_SPLATB_MASK): Likewise.
342 (VX_SPE2_OCTET): Likewise.
343 (VX_SPE2_OCTET_MASK): Likewise.
344 (VX_SPE2_DDHH): Likewise.
345 (VX_SPE2_DDHH_MASK): Likewise.
346 (VX_SPE2_HH): Likewise.
347 (VX_SPE2_HH_MASK): Likewise.
348 (VX_SPE2_EVMAR): Likewise.
349 (VX_SPE2_EVMAR_MASK): Likewise.
352 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
353 (powerpc_macros): Map old SPE instructions have new names
354 with the same opcodes. Add SPE2 instructions which just are
356 (spe2_opcodes): Add SPE2 opcodes.
358 2017-08-23 Alan Modra <amodra@gmail.com>
360 * ppc-opc.c: Formatting and comment fixes. Move insert and
361 extract functions earlier, deleting forward declarations.
362 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
365 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
367 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
369 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
370 Edmar Wienskoski <edmar.wienskoski@nxp.com>
372 * ppc-opc.c (insert_evuimm2_ex0): New function.
373 (extract_evuimm2_ex0): Likewise.
374 (insert_evuimm4_ex0): Likewise.
375 (extract_evuimm4_ex0): Likewise.
376 (insert_evuimm8_ex0): Likewise.
377 (extract_evuimm8_ex0): Likewise.
378 (insert_evuimm_lt16): Likewise.
379 (extract_evuimm_lt16): Likewise.
380 (insert_rD_rS_even): Likewise.
381 (extract_rD_rS_even): Likewise.
382 (insert_off_lsp): Likewise.
383 (extract_off_lsp): Likewise.
384 (RD_EVEN): New operand.
387 (EVUIMM_LT16): New operand.
389 (EVUIMM_2_EX0): New operand.
391 (EVUIMM_4_EX0): New operand.
393 (EVUIMM_8_EX0): New operand.
395 (VX_OFF): New operand.
397 (VX_LSP_MASK): Likewise.
398 (VX_LSP_OFF_MASK): Likewise.
399 (PPC_OPCODE_LSP): Likewise.
400 (vle_opcodes): Add LSP opcodes.
401 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
403 2017-08-09 Jiong Wang <jiong.wang@arm.com>
405 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
406 register operands in CRC instructions.
407 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
410 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
412 * disassemble.c (disassembler): Mark big and mach with
415 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
417 * disassemble.c (disassembler): Remove arch/mach/endian
420 2017-07-25 Nick Clifton <nickc@redhat.com>
423 * arc-opc.c (insert_rhv2): Use lower case first letter in error
425 (insert_r0): Likewise.
426 (insert_r1): Likewise.
427 (insert_r2): Likewise.
428 (insert_r3): Likewise.
429 (insert_sp): Likewise.
430 (insert_gp): Likewise.
431 (insert_pcl): Likewise.
432 (insert_blink): Likewise.
433 (insert_ilink1): Likewise.
434 (insert_ilink2): Likewise.
435 (insert_ras): Likewise.
436 (insert_rbs): Likewise.
437 (insert_rcs): Likewise.
438 (insert_simm3s): Likewise.
439 (insert_rrange): Likewise.
440 (insert_r13el): Likewise.
441 (insert_fpel): Likewise.
442 (insert_blinkel): Likewise.
443 (insert_pclel): Likewise.
444 (insert_nps_bitop_size_2b): Likewise.
445 (insert_nps_imm_offset): Likewise.
446 (insert_nps_imm_entry): Likewise.
447 (insert_nps_size_16bit): Likewise.
448 (insert_nps_##NAME##_pos): Likewise.
449 (insert_nps_##NAME): Likewise.
450 (insert_nps_bitop_ins_ext): Likewise.
451 (insert_nps_##NAME): Likewise.
452 (insert_nps_min_hofs): Likewise.
453 (insert_nps_##NAME): Likewise.
454 (insert_nps_rbdouble_64): Likewise.
455 (insert_nps_misc_imm_offset): Likewise.
456 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
459 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
460 Jiong Wang <jiong.wang@arm.com>
462 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
464 * aarch64-dis-2.c: Regenerated.
466 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
468 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
471 2017-07-20 Nick Clifton <nickc@redhat.com>
473 * po/de.po: Updated German translation.
475 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
477 * arc-regs.h (sec_stat): New aux register.
478 (aux_kernel_sp): Likewise.
479 (aux_sec_u_sp): Likewise.
480 (aux_sec_k_sp): Likewise.
481 (sec_vecbase_build): Likewise.
482 (nsc_table_top): Likewise.
483 (nsc_table_base): Likewise.
484 (ersec_stat): Likewise.
485 (aux_sec_except): Likewise.
487 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
489 * arc-opc.c (extract_uimm12_20): New function.
490 (UIMM12_20): New operand.
492 * arc-tbl.h (sjli): Add new instruction.
494 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
495 John Eric Martin <John.Martin@emmicro-us.com>
497 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
498 (UIMM3_23): Adjust accordingly.
499 * arc-regs.h: Add/correct jli_base register.
500 * arc-tbl.h (jli_s): Likewise.
502 2017-07-18 Nick Clifton <nickc@redhat.com>
505 * aarch64-opc.c: Fix spelling typos.
506 * i386-dis.c: Likewise.
508 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
510 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
511 max_addr_offset and octets variables to size_t.
513 2017-07-12 Alan Modra <amodra@gmail.com>
515 * po/da.po: Update from translationproject.org/latest/opcodes/.
516 * po/de.po: Likewise.
517 * po/es.po: Likewise.
518 * po/fi.po: Likewise.
519 * po/fr.po: Likewise.
520 * po/id.po: Likewise.
521 * po/it.po: Likewise.
522 * po/nl.po: Likewise.
523 * po/pt_BR.po: Likewise.
524 * po/ro.po: Likewise.
525 * po/sv.po: Likewise.
526 * po/tr.po: Likewise.
527 * po/uk.po: Likewise.
528 * po/vi.po: Likewise.
529 * po/zh_CN.po: Likewise.
531 2017-07-11 Yao Qi <yao.qi@linaro.org>
532 Alan Modra <amodra@gmail.com>
534 * cgen.sh: Mark generated files read-only.
535 * epiphany-asm.c: Regenerate.
536 * epiphany-desc.c: Regenerate.
537 * epiphany-desc.h: Regenerate.
538 * epiphany-dis.c: Regenerate.
539 * epiphany-ibld.c: Regenerate.
540 * epiphany-opc.c: Regenerate.
541 * epiphany-opc.h: Regenerate.
542 * fr30-asm.c: Regenerate.
543 * fr30-desc.c: Regenerate.
544 * fr30-desc.h: Regenerate.
545 * fr30-dis.c: Regenerate.
546 * fr30-ibld.c: Regenerate.
547 * fr30-opc.c: Regenerate.
548 * fr30-opc.h: Regenerate.
549 * frv-asm.c: Regenerate.
550 * frv-desc.c: Regenerate.
551 * frv-desc.h: Regenerate.
552 * frv-dis.c: Regenerate.
553 * frv-ibld.c: Regenerate.
554 * frv-opc.c: Regenerate.
555 * frv-opc.h: Regenerate.
556 * ip2k-asm.c: Regenerate.
557 * ip2k-desc.c: Regenerate.
558 * ip2k-desc.h: Regenerate.
559 * ip2k-dis.c: Regenerate.
560 * ip2k-ibld.c: Regenerate.
561 * ip2k-opc.c: Regenerate.
562 * ip2k-opc.h: Regenerate.
563 * iq2000-asm.c: Regenerate.
564 * iq2000-desc.c: Regenerate.
565 * iq2000-desc.h: Regenerate.
566 * iq2000-dis.c: Regenerate.
567 * iq2000-ibld.c: Regenerate.
568 * iq2000-opc.c: Regenerate.
569 * iq2000-opc.h: Regenerate.
570 * lm32-asm.c: Regenerate.
571 * lm32-desc.c: Regenerate.
572 * lm32-desc.h: Regenerate.
573 * lm32-dis.c: Regenerate.
574 * lm32-ibld.c: Regenerate.
575 * lm32-opc.c: Regenerate.
576 * lm32-opc.h: Regenerate.
577 * lm32-opinst.c: Regenerate.
578 * m32c-asm.c: Regenerate.
579 * m32c-desc.c: Regenerate.
580 * m32c-desc.h: Regenerate.
581 * m32c-dis.c: Regenerate.
582 * m32c-ibld.c: Regenerate.
583 * m32c-opc.c: Regenerate.
584 * m32c-opc.h: Regenerate.
585 * m32r-asm.c: Regenerate.
586 * m32r-desc.c: Regenerate.
587 * m32r-desc.h: Regenerate.
588 * m32r-dis.c: Regenerate.
589 * m32r-ibld.c: Regenerate.
590 * m32r-opc.c: Regenerate.
591 * m32r-opc.h: Regenerate.
592 * m32r-opinst.c: Regenerate.
593 * mep-asm.c: Regenerate.
594 * mep-desc.c: Regenerate.
595 * mep-desc.h: Regenerate.
596 * mep-dis.c: Regenerate.
597 * mep-ibld.c: Regenerate.
598 * mep-opc.c: Regenerate.
599 * mep-opc.h: Regenerate.
600 * mt-asm.c: Regenerate.
601 * mt-desc.c: Regenerate.
602 * mt-desc.h: Regenerate.
603 * mt-dis.c: Regenerate.
604 * mt-ibld.c: Regenerate.
605 * mt-opc.c: Regenerate.
606 * mt-opc.h: Regenerate.
607 * or1k-asm.c: Regenerate.
608 * or1k-desc.c: Regenerate.
609 * or1k-desc.h: Regenerate.
610 * or1k-dis.c: Regenerate.
611 * or1k-ibld.c: Regenerate.
612 * or1k-opc.c: Regenerate.
613 * or1k-opc.h: Regenerate.
614 * or1k-opinst.c: Regenerate.
615 * xc16x-asm.c: Regenerate.
616 * xc16x-desc.c: Regenerate.
617 * xc16x-desc.h: Regenerate.
618 * xc16x-dis.c: Regenerate.
619 * xc16x-ibld.c: Regenerate.
620 * xc16x-opc.c: Regenerate.
621 * xc16x-opc.h: Regenerate.
622 * xstormy16-asm.c: Regenerate.
623 * xstormy16-desc.c: Regenerate.
624 * xstormy16-desc.h: Regenerate.
625 * xstormy16-dis.c: Regenerate.
626 * xstormy16-ibld.c: Regenerate.
627 * xstormy16-opc.c: Regenerate.
628 * xstormy16-opc.h: Regenerate.
630 2017-07-07 Alan Modra <amodra@gmail.com>
632 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
633 * m32c-dis.c: Regenerate.
634 * mep-dis.c: Regenerate.
636 2017-07-05 Borislav Petkov <bp@suse.de>
638 * i386-dis.c: Enable ModRM.reg /6 aliases.
640 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
642 * opcodes/arm-dis.c: Support MVFR2 in disassembly
645 2017-07-04 Tristan Gingold <gingold@adacore.com>
647 * configure: Regenerate.
649 2017-07-03 Tristan Gingold <gingold@adacore.com>
651 * po/opcodes.pot: Regenerate.
653 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
655 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
656 entries to the MSA ASE instruction block.
658 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
659 Maciej W. Rozycki <macro@imgtec.com>
661 * micromips-opc.c (XPA, XPAVZ): New macros.
662 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
665 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
666 Maciej W. Rozycki <macro@imgtec.com>
668 * micromips-opc.c (I36): New macro.
669 (micromips_opcodes): Add "eretnc".
671 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
672 Andrew Bennett <andrew.bennett@imgtec.com>
674 * mips-dis.c (mips_calculate_combination_ases): Handle the
676 (parse_mips_ase_option): New function.
677 (parse_mips_dis_option): Factor out ASE option handling to the
678 new function. Call `mips_calculate_combination_ases'.
679 * mips-opc.c (XPAVZ): New macro.
680 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
681 "mfhgc0", "mthc0" and "mthgc0".
683 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
685 * mips-dis.c (mips_calculate_combination_ases): New function.
686 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
687 calculation to the new function.
688 (set_default_mips_dis_options): Call the new function.
690 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
692 * arc-dis.c (parse_disassembler_options): Use
693 FOR_EACH_DISASSEMBLER_OPTION.
695 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
697 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
698 disassembler option strings.
699 (parse_cpu_option): Likewise.
701 2017-06-28 Tamar Christina <tamar.christina@arm.com>
703 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
704 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
705 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
706 (aarch64_feature_dotprod, DOT_INSN): New.
708 * aarch64-dis-2.c: Regenerated.
710 2017-06-28 Jiong Wang <jiong.wang@arm.com>
712 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
714 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
715 Matthew Fortune <matthew.fortune@imgtec.com>
716 Andrew Bennett <andrew.bennett@imgtec.com>
718 * mips-formats.h (INT_BIAS): New macro.
719 (INT_ADJ): Redefine in INT_BIAS terms.
720 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
721 (mips_print_save_restore): New function.
722 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
723 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
725 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
726 (print_mips16_insn_arg): Call `mips_print_save_restore' for
727 OP_SAVE_RESTORE_LIST handling, factored out from here.
728 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
729 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
730 (mips_builtin_opcodes): Add "restore" and "save" entries.
731 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
733 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
735 2017-06-23 Andrew Waterman <andrew@sifive.com>
737 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
738 alias; do not mark SLTI instruction as an alias.
740 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
742 * i386-dis.c (RM_0FAE_REG_5): Removed.
743 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
744 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
745 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
746 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
747 PREFIX_MOD_3_0F01_REG_5_RM_0.
748 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
749 PREFIX_MOD_3_0FAE_REG_5.
750 (mod_table): Update MOD_0FAE_REG_5.
751 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
752 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
753 * i386-tbl.h: Regenerated.
755 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
757 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
758 * i386-opc.tbl: Likewise.
759 * i386-tbl.h: Regenerated.
761 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
763 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
765 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
768 2017-06-19 Nick Clifton <nickc@redhat.com>
771 * score-dis.c (score_opcodes): Add sentinel.
773 2017-06-16 Alan Modra <amodra@gmail.com>
775 * rx-decode.c: Regenerate.
777 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
780 * i386-dis.c (OP_E_register): Check valid bnd register.
783 2017-06-15 Nick Clifton <nickc@redhat.com>
786 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
789 2017-06-15 Nick Clifton <nickc@redhat.com>
792 * rl78-decode.opc (OP_BUF_LEN): Define.
793 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
794 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
796 * rl78-decode.c: Regenerate.
798 2017-06-15 Nick Clifton <nickc@redhat.com>
801 * bfin-dis.c (gregs): Clip index to prevent overflow.
806 2017-06-14 Nick Clifton <nickc@redhat.com>
809 * score7-dis.c (score_opcodes): Add sentinel.
811 2017-06-14 Yao Qi <yao.qi@linaro.org>
813 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
814 * arm-dis.c: Likewise.
815 * ia64-dis.c: Likewise.
816 * mips-dis.c: Likewise.
817 * spu-dis.c: Likewise.
818 * disassemble.h (print_insn_aarch64): New declaration, moved from
820 (print_insn_big_arm, print_insn_big_mips): Likewise.
821 (print_insn_i386, print_insn_ia64): Likewise.
822 (print_insn_little_arm, print_insn_little_mips): Likewise.
824 2017-06-14 Nick Clifton <nickc@redhat.com>
827 * rx-decode.opc: Include libiberty.h
828 (GET_SCALE): New macro - validates access to SCALE array.
829 (GET_PSCALE): New macro - validates access to PSCALE array.
830 (DIs, SIs, S2Is, rx_disp): Use new macros.
831 * rx-decode.c: Regenerate.
833 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
835 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
837 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
839 * arc-dis.c (enforced_isa_mask): Declare.
840 (cpu_types): Likewise.
841 (parse_cpu_option): New function.
842 (parse_disassembler_options): Use it.
843 (print_insn_arc): Use enforced_isa_mask.
844 (print_arc_disassembler_options): Document new options.
846 2017-05-24 Yao Qi <yao.qi@linaro.org>
848 * alpha-dis.c: Include disassemble.h, don't include
850 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
851 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
852 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
853 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
854 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
855 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
856 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
857 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
858 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
859 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
860 * moxie-dis.c, msp430-dis.c, mt-dis.c:
861 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
862 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
863 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
864 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
865 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
866 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
867 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
868 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
869 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
870 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
871 * z80-dis.c, z8k-dis.c: Likewise.
872 * disassemble.h: New file.
874 2017-05-24 Yao Qi <yao.qi@linaro.org>
876 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
877 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
879 2017-05-24 Yao Qi <yao.qi@linaro.org>
881 * disassemble.c (disassembler): Add arguments a, big and mach.
884 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
886 * i386-dis.c (NOTRACK_Fixup): New.
888 (NOTRACK_PREFIX): Likewise.
889 (last_active_prefix): Likewise.
890 (reg_table): Use NOTRACK on indirect call and jmp.
891 (ckprefix): Set last_active_prefix.
892 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
893 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
894 * i386-opc.h (NoTrackPrefixOk): New.
895 (i386_opcode_modifier): Add notrackprefixok.
896 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
898 * i386-tbl.h: Regenerated.
900 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
902 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
904 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
906 (print_insn_sparc): Handle new operand types.
907 * sparc-opc.c (MASK_M8): Define.
909 (v6notlet): Likewise.
920 (v9andleon): Likewise.
923 (HWS2_VM8): Likewise.
924 (sparc_opcode_archs): Add entry for "m8".
925 (sparc_opcodes): Add OSA2017 and M8 instructions
926 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
928 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
929 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
930 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
931 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
932 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
933 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
934 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
935 ASI_CORE_SELECT_COMMIT_NHT.
937 2017-05-18 Alan Modra <amodra@gmail.com>
939 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
940 * aarch64-dis.c: Likewise.
941 * aarch64-gen.c: Likewise.
942 * aarch64-opc.c: Likewise.
944 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
945 Matthew Fortune <matthew.fortune@imgtec.com>
947 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
948 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
949 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
950 (print_insn_arg) <OP_REG28>: Add handler.
951 (validate_insn_args) <OP_REG28>: Handle.
952 (print_mips16_insn_arg): Handle MIPS16 instructions that require
953 32-bit encoding and 9-bit immediates.
954 (print_insn_mips16): Handle MIPS16 instructions that require
955 32-bit encoding and MFC0/MTC0 operand decoding.
956 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
957 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
958 (RD_C0, WR_C0, E2, E2MT): New macros.
959 (mips16_opcodes): Add entries for MIPS16e2 instructions:
960 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
961 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
962 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
963 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
964 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
965 instructions, "swl", "swr", "sync" and its "sync_acquire",
966 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
967 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
968 regular/extended entries for original MIPS16 ISA revision
969 instructions whose extended forms are subdecoded in the MIPS16e2
970 ISA revision: "li", "sll" and "srl".
972 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
974 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
975 reference in CP0 move operand decoding.
977 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
979 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
981 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
983 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
985 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
986 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
987 "sync_rmb" and "sync_wmb" as aliases.
988 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
989 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
991 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
993 * arc-dis.c (parse_option): Update quarkse_em option..
994 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
996 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
998 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
1000 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1002 2017-05-01 Michael Clark <michaeljclark@mac.com>
1004 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1007 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
1009 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1010 and branches and not synthetic data instructions.
1012 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
1014 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1016 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1018 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1019 * arc-opc.c (insert_r13el): New function.
1021 * arc-tbl.h: Add new enter/leave variants.
1023 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1025 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1027 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1029 * mips-dis.c (print_mips_disassembler_options): Add
1032 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1034 * mips16-opc.c (AL): New macro.
1035 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1036 of "ld" and "lw" as aliases.
1038 2017-04-24 Tamar Christina <tamar.christina@arm.com>
1040 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1043 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1044 Alan Modra <amodra@gmail.com>
1046 * ppc-opc.c (ELEV): Define.
1047 (vle_opcodes): Add se_rfgi and e_sc.
1048 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1051 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1053 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1055 2017-04-21 Nick Clifton <nickc@redhat.com>
1058 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1061 2017-04-13 Alan Modra <amodra@gmail.com>
1063 * epiphany-desc.c: Regenerate.
1064 * fr30-desc.c: Regenerate.
1065 * frv-desc.c: Regenerate.
1066 * ip2k-desc.c: Regenerate.
1067 * iq2000-desc.c: Regenerate.
1068 * lm32-desc.c: Regenerate.
1069 * m32c-desc.c: Regenerate.
1070 * m32r-desc.c: Regenerate.
1071 * mep-desc.c: Regenerate.
1072 * mt-desc.c: Regenerate.
1073 * or1k-desc.c: Regenerate.
1074 * xc16x-desc.c: Regenerate.
1075 * xstormy16-desc.c: Regenerate.
1077 2017-04-11 Alan Modra <amodra@gmail.com>
1079 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1080 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1081 PPC_OPCODE_TMR for e6500.
1082 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1083 (PPCVEC3): Define as PPC_OPCODE_POWER9.
1084 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1085 (PPCVSX3): Define as PPC_OPCODE_POWER9.
1086 (PPCHTM): Define as PPC_OPCODE_POWER8.
1087 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1089 2017-04-10 Alan Modra <amodra@gmail.com>
1091 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1092 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1093 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1094 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1096 2017-04-09 Pip Cet <pipcet@gmail.com>
1098 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1099 appropriate floating-point precision directly.
1101 2017-04-07 Alan Modra <amodra@gmail.com>
1103 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1104 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1105 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1106 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1107 vector instructions with E6500 not PPCVEC2.
1109 2017-04-06 Pip Cet <pipcet@gmail.com>
1111 * Makefile.am: Add wasm32-dis.c.
1112 * configure.ac: Add wasm32-dis.c to wasm32 target.
1113 * disassemble.c: Add wasm32 disassembler code.
1114 * wasm32-dis.c: New file.
1115 * Makefile.in: Regenerate.
1116 * configure: Regenerate.
1117 * po/POTFILES.in: Regenerate.
1118 * po/opcodes.pot: Regenerate.
1120 2017-04-05 Pedro Alves <palves@redhat.com>
1122 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1123 * arm-dis.c (parse_arm_disassembler_options): Constify.
1124 * ppc-dis.c (powerpc_init_dialect): Constify local.
1125 * vax-dis.c (parse_disassembler_options): Constify.
1127 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1129 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1132 2017-03-30 Pip Cet <pipcet@gmail.com>
1134 * configure.ac: Add (empty) bfd_wasm32_arch target.
1135 * configure: Regenerate
1136 * po/opcodes.pot: Regenerate.
1138 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1140 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1142 * opcodes/sparc-opc.c (asi_table): New ASIs.
1144 2017-03-29 Alan Modra <amodra@gmail.com>
1146 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1148 (lookup_powerpc): Don't special case -1 dialect. Handle
1150 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1151 lookup_powerpc call, pass it on second.
1153 2017-03-27 Alan Modra <amodra@gmail.com>
1156 * ppc-dis.c (struct ppc_mopt): Comment.
1157 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1159 2017-03-27 Rinat Zelig <rinat@mellanox.com>
1161 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1162 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1163 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1164 (insert_nps_misc_imm_offset): New function.
1165 (extract_nps_misc imm_offset): New function.
1166 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1167 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1169 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1171 * s390-mkopc.c (main): Remove vx2 check.
1172 * s390-opc.txt: Remove vx2 instruction flags.
1174 2017-03-21 Rinat Zelig <rinat@mellanox.com>
1176 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1177 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1178 (insert_nps_imm_offset): New function.
1179 (extract_nps_imm_offset): New function.
1180 (insert_nps_imm_entry): New function.
1181 (extract_nps_imm_entry): New function.
1183 2017-03-17 Alan Modra <amodra@gmail.com>
1186 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1187 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1188 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1190 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1192 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1196 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1198 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1200 2017-03-13 Andrew Waterman <andrew@sifive.com>
1202 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1207 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1209 * i386-gen.c (opcode_modifiers): Replace S with Load.
1210 * i386-opc.h (S): Removed.
1212 (i386_opcode_modifier): Replace s with load.
1213 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1214 and {evex}. Replace S with Load.
1215 * i386-tbl.h: Regenerated.
1217 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1219 * i386-opc.tbl: Use CpuCET on rdsspq.
1220 * i386-tbl.h: Regenerated.
1222 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1224 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1225 <vsx>: Do not use PPC_OPCODE_VSX3;
1227 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1229 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1231 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1233 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1234 (MOD_0F1E_PREFIX_1): Likewise.
1235 (MOD_0F38F5_PREFIX_2): Likewise.
1236 (MOD_0F38F6_PREFIX_0): Likewise.
1237 (RM_0F1E_MOD_3_REG_7): Likewise.
1238 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1239 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1240 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1241 (PREFIX_0F1E): Likewise.
1242 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1243 (PREFIX_0F38F5): Likewise.
1244 (dis386_twobyte): Use PREFIX_0F1E.
1245 (reg_table): Add REG_0F1E_MOD_3.
1246 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1247 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1248 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1249 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1250 (three_byte_table): Use PREFIX_0F38F5.
1251 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1252 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1253 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1254 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1255 PREFIX_MOD_3_0F01_REG_5_RM_2.
1256 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1257 (cpu_flags): Add CpuCET.
1258 * i386-opc.h (CpuCET): New enum.
1259 (CpuUnused): Commented out.
1260 (i386_cpu_flags): Add cpucet.
1261 * i386-opc.tbl: Add Intel CET instructions.
1262 * i386-init.h: Regenerated.
1263 * i386-tbl.h: Likewise.
1265 2017-03-06 Alan Modra <amodra@gmail.com>
1268 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1269 (extract_raq, extract_ras, extract_rbx): New functions.
1270 (powerpc_operands): Use opposite corresponding insert function.
1272 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1273 register restriction.
1275 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1277 * disassemble.c Include "safe-ctype.h".
1278 (disassemble_init_for_target): Handle s390 init.
1279 (remove_whitespace_and_extra_commas): New function.
1280 (disassembler_options_cmp): Likewise.
1281 * arm-dis.c: Include "libiberty.h".
1283 (regnames): Use long disassembler style names.
1284 Add force-thumb and no-force-thumb options.
1285 (NUM_ARM_REGNAMES): Rename from this...
1286 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1287 (get_arm_regname_num_options): Delete.
1288 (set_arm_regname_option): Likewise.
1289 (get_arm_regnames): Likewise.
1290 (parse_disassembler_options): Likewise.
1291 (parse_arm_disassembler_option): Rename from this...
1292 (parse_arm_disassembler_options): ...to this. Make static.
1293 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1294 (print_insn): Use parse_arm_disassembler_options.
1295 (disassembler_options_arm): New function.
1296 (print_arm_disassembler_options): Handle updated regnames.
1297 * ppc-dis.c: Include "libiberty.h".
1298 (ppc_opts): Add "32" and "64" entries.
1299 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1300 (powerpc_init_dialect): Add break to switch statement.
1301 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1302 (disassembler_options_powerpc): New function.
1303 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1304 Remove printing of "32" and "64".
1305 * s390-dis.c: Include "libiberty.h".
1306 (init_flag): Remove unneeded variable.
1307 (struct s390_options_t): New structure type.
1308 (options): New structure.
1309 (init_disasm): Rename from this...
1310 (disassemble_init_s390): ...to this. Add initializations for
1311 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1312 (print_insn_s390): Delete call to init_disasm.
1313 (disassembler_options_s390): New function.
1314 (print_s390_disassembler_options): Print using information from
1316 * po/opcodes.pot: Regenerate.
1318 2017-02-28 Jan Beulich <jbeulich@suse.com>
1320 * i386-dis.c (PCMPESTR_Fixup): New.
1321 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1322 (prefix_table): Use PCMPESTR_Fixup.
1323 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1325 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1326 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1327 Split 64-bit and non-64-bit variants.
1328 * opcodes/i386-tbl.h: Re-generate.
1330 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1332 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1333 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1334 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1335 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1336 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1337 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1338 (OP_SVE_V_HSD): New macros.
1339 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1340 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1341 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1342 (aarch64_opcode_table): Add new SVE instructions.
1343 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1344 for rotation operands. Add new SVE operands.
1345 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1346 (ins_sve_quad_index): Likewise.
1347 (ins_imm_rotate): Split into...
1348 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1349 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1350 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1352 (aarch64_ins_sve_addr_ri_s4): New function.
1353 (aarch64_ins_sve_quad_index): Likewise.
1354 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1355 * aarch64-asm-2.c: Regenerate.
1356 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1357 (ext_sve_quad_index): Likewise.
1358 (ext_imm_rotate): Split into...
1359 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1360 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1361 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1363 (aarch64_ext_sve_addr_ri_s4): New function.
1364 (aarch64_ext_sve_quad_index): Likewise.
1365 (aarch64_ext_sve_index): Allow quad indices.
1366 (do_misc_decoding): Likewise.
1367 * aarch64-dis-2.c: Regenerate.
1368 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1369 aarch64_field_kinds.
1370 (OPD_F_OD_MASK): Widen by one bit.
1371 (OPD_F_NO_ZR): Bump accordingly.
1372 (get_operand_field_width): New function.
1373 * aarch64-opc.c (fields): Add new SVE fields.
1374 (operand_general_constraint_met_p): Handle new SVE operands.
1375 (aarch64_print_operand): Likewise.
1376 * aarch64-opc-2.c: Regenerate.
1378 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1380 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1381 (aarch64_feature_compnum): ...this.
1382 (SIMD_V8_3): Replace with...
1384 (CNUM_INSN): New macro.
1385 (aarch64_opcode_table): Use it for the complex number instructions.
1387 2017-02-24 Jan Beulich <jbeulich@suse.com>
1389 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1391 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1393 Add support for associating SPARC ASIs with an architecture level.
1394 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1395 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1396 decoding of SPARC ASIs.
1398 2017-02-23 Jan Beulich <jbeulich@suse.com>
1400 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1401 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1403 2017-02-21 Jan Beulich <jbeulich@suse.com>
1405 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1406 1 (instead of to itself). Correct typo.
1408 2017-02-14 Andrew Waterman <andrew@sifive.com>
1410 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1413 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1415 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1416 (aarch64_sys_reg_supported_p): Handle them.
1418 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1420 * arc-opc.c (UIMM6_20R): Define.
1421 (SIMM12_20): Use above.
1422 (SIMM12_20R): Define.
1423 (SIMM3_5_S): Use above.
1424 (UIMM7_A32_11R_S): Define.
1425 (UIMM7_9_S): Use above.
1426 (UIMM3_13R_S): Define.
1427 (SIMM11_A32_7_S): Use above.
1429 (UIMM10_A32_8_S): Use above.
1430 (UIMM8_8R_S): Define.
1432 (arc_relax_opcodes): Use all above defines.
1434 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1436 * arc-regs.h: Distinguish some of the registers different on
1437 ARC700 and HS38 cpus.
1439 2017-02-14 Alan Modra <amodra@gmail.com>
1442 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1443 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1445 2017-02-11 Stafford Horne <shorne@gmail.com>
1446 Alan Modra <amodra@gmail.com>
1448 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1449 Use insn_bytes_value and insn_int_value directly instead. Don't
1450 free allocated memory until function exit.
1452 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1454 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1456 2017-02-03 Nick Clifton <nickc@redhat.com>
1459 * aarch64-opc.c (print_register_list): Ensure that the register
1460 list index will fir into the tb buffer.
1461 (print_register_offset_address): Likewise.
1462 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1464 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1467 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1468 instructions when the previous fetch packet ends with a 32-bit
1471 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1473 * pru-opc.c: Remove vague reference to a future GDB port.
1475 2017-01-20 Nick Clifton <nickc@redhat.com>
1477 * po/ga.po: Updated Irish translation.
1479 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1481 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1483 2017-01-13 Yao Qi <yao.qi@linaro.org>
1485 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1486 if FETCH_DATA returns 0.
1487 (m68k_scan_mask): Likewise.
1488 (print_insn_m68k): Update code to handle -1 return value.
1490 2017-01-13 Yao Qi <yao.qi@linaro.org>
1492 * m68k-dis.c (enum print_insn_arg_error): New.
1493 (NEXTBYTE): Replace -3 with
1494 PRINT_INSN_ARG_MEMORY_ERROR.
1495 (NEXTULONG): Likewise.
1496 (NEXTSINGLE): Likewise.
1497 (NEXTDOUBLE): Likewise.
1498 (NEXTDOUBLE): Likewise.
1499 (NEXTPACKED): Likewise.
1500 (FETCH_ARG): Likewise.
1501 (FETCH_DATA): Update comments.
1502 (print_insn_arg): Update comments. Replace magic numbers with
1504 (match_insn_m68k): Likewise.
1506 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1508 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1509 * i386-dis-evex.h (evex_table): Updated.
1510 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1511 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1512 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1513 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1514 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1515 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1516 * i386-init.h: Regenerate.
1517 * i386-tbl.h: Ditto.
1519 2017-01-12 Yao Qi <yao.qi@linaro.org>
1521 * msp430-dis.c (msp430_singleoperand): Return -1 if
1522 msp430dis_opcode_signed returns false.
1523 (msp430_doubleoperand): Likewise.
1524 (msp430_branchinstr): Return -1 if
1525 msp430dis_opcode_unsigned returns false.
1526 (msp430x_calla_instr): Likewise.
1527 (print_insn_msp430): Likewise.
1529 2017-01-05 Nick Clifton <nickc@redhat.com>
1532 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1533 could not be matched.
1534 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1537 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1539 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1540 (aarch64_opcode_table): Use RCPC_INSN.
1542 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1544 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1546 * riscv-opcodes/all-opcodes: Likewise.
1548 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1550 * riscv-dis.c (print_insn_args): Add fall through comment.
1552 2017-01-03 Nick Clifton <nickc@redhat.com>
1554 * po/sr.po: New Serbian translation.
1555 * configure.ac (ALL_LINGUAS): Add sr.
1556 * configure: Regenerate.
1558 2017-01-02 Alan Modra <amodra@gmail.com>
1560 * epiphany-desc.h: Regenerate.
1561 * epiphany-opc.h: Regenerate.
1562 * fr30-desc.h: Regenerate.
1563 * fr30-opc.h: Regenerate.
1564 * frv-desc.h: Regenerate.
1565 * frv-opc.h: Regenerate.
1566 * ip2k-desc.h: Regenerate.
1567 * ip2k-opc.h: Regenerate.
1568 * iq2000-desc.h: Regenerate.
1569 * iq2000-opc.h: Regenerate.
1570 * lm32-desc.h: Regenerate.
1571 * lm32-opc.h: Regenerate.
1572 * m32c-desc.h: Regenerate.
1573 * m32c-opc.h: Regenerate.
1574 * m32r-desc.h: Regenerate.
1575 * m32r-opc.h: Regenerate.
1576 * mep-desc.h: Regenerate.
1577 * mep-opc.h: Regenerate.
1578 * mt-desc.h: Regenerate.
1579 * mt-opc.h: Regenerate.
1580 * or1k-desc.h: Regenerate.
1581 * or1k-opc.h: Regenerate.
1582 * xc16x-desc.h: Regenerate.
1583 * xc16x-opc.h: Regenerate.
1584 * xstormy16-desc.h: Regenerate.
1585 * xstormy16-opc.h: Regenerate.
1587 2017-01-02 Alan Modra <amodra@gmail.com>
1589 Update year range in copyright notice of all files.
1591 For older changes see ChangeLog-2016
1593 Copyright (C) 2017 Free Software Foundation, Inc.
1595 Copying and distribution of this file, with or without modification,
1596 are permitted in any medium without royalty provided the copyright
1597 notice and this notice are preserved.
1603 version-control: never