1 2019-11-12 Jan Beulich <jbeulich@suse.com>
3 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
5 (operand_types): Remove EsSeg entry.
6 (main): Replace stale use of OTMax.
7 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
8 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
10 (OTUnused): Comment out.
11 (union i386_operand_type): Remove esseg field.
12 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
13 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
14 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
15 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
16 * i386-init.h, i386-tbl.h: Re-generate.
18 2019-11-12 Jan Beulich <jbeulich@suse.com>
20 * i386-gen.c (operand_instances): Add RegB entry.
21 * i386-opc.h (enum operand_instance): Add RegB.
22 * i386-opc.tbl (RegC, RegD, RegB): Define.
23 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
24 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
25 monitorx, mwaitx): Drop ImmExt and convert encodings
27 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
28 (edx, rdx): Add Instance=RegD.
29 (ebx, rbx): Add Instance=RegB.
30 * i386-tbl.h: Re-generate.
32 2019-11-12 Jan Beulich <jbeulich@suse.com>
34 * i386-gen.c (operand_type_init): Adjust
35 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
36 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
37 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
38 (operand_instances): New.
39 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
40 (output_operand_type): New parameter "instance". Process it.
41 (process_i386_operand_type): New local variable "instance".
42 (main): Adjust static assertions.
43 * i386-opc.h (INSTANCE_WIDTH): Define.
44 (enum operand_instance): New.
45 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
46 (union i386_operand_type): Replace acc, inoutportreg, and
47 shiftcount by instance.
48 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
49 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
51 * i386-init.h, i386-tbl.h: Re-generate.
53 2019-11-11 Jan Beulich <jbeulich@suse.com>
55 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
56 smaxp/sminp entries' "tied_operand" field to 2.
58 2019-11-11 Jan Beulich <jbeulich@suse.com>
60 * aarch64-opc.c (operand_general_constraint_met_p): Replace
61 "index" local variable by that of the already existing "num".
63 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
66 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
67 * i386-tbl.h: Regenerated.
69 2019-11-08 Jan Beulich <jbeulich@suse.com>
71 * i386-gen.c (operand_type_init): Add Class= to
72 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
73 OPERAND_TYPE_REGBND entry.
74 (operand_classes): Add RegMask and RegBND entries.
75 (operand_types): Drop RegMask and RegBND entry.
76 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
77 (RegMask, RegBND): Delete.
78 (union i386_operand_type): Remove regmask and regbnd fields.
79 * i386-opc.tbl (RegMask, RegBND): Define.
80 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
82 * i386-init.h, i386-tbl.h: Re-generate.
84 2019-11-08 Jan Beulich <jbeulich@suse.com>
86 * i386-gen.c (operand_type_init): Add Class= to
87 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
88 OPERAND_TYPE_REGZMM entries.
89 (operand_classes): Add RegMMX and RegSIMD entries.
90 (operand_types): Drop RegMMX and RegSIMD entries.
91 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
92 (RegMMX, RegSIMD): Delete.
93 (union i386_operand_type): Remove regmmx and regsimd fields.
94 * i386-opc.tbl (RegMMX): Define.
95 (RegXMM, RegYMM, RegZMM): Add Class=.
96 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
98 * i386-init.h, i386-tbl.h: Re-generate.
100 2019-11-08 Jan Beulich <jbeulich@suse.com>
102 * i386-gen.c (operand_type_init): Add Class= to
103 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
105 (operand_classes): Add RegCR, RegDR, and RegTR entries.
106 (operand_types): Drop Control, Debug, and Test entries.
107 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
108 (Control, Debug, Test): Delete.
109 (union i386_operand_type): Remove control, debug, and test
111 * i386-opc.tbl (Control, Debug, Test): Define.
112 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
113 Class=RegDR, and Test by Class=RegTR.
114 * i386-init.h, i386-tbl.h: Re-generate.
116 2019-11-08 Jan Beulich <jbeulich@suse.com>
118 * i386-gen.c (operand_type_init): Add Class= to
119 OPERAND_TYPE_SREG entry.
120 (operand_classes): Add SReg entry.
121 (operand_types): Drop SReg entry.
122 * i386-opc.h (enum operand_class): Add SReg.
124 (union i386_operand_type): Remove sreg field.
125 * i386-opc.tbl (SReg): Define.
126 * i386-reg.tbl: Replace SReg by Class=SReg.
127 * i386-init.h, i386-tbl.h: Re-generate.
129 2019-11-08 Jan Beulich <jbeulich@suse.com>
131 * i386-gen.c (operand_type_init): Add Class=. New
132 OPERAND_TYPE_ANYIMM entry.
133 (operand_classes): New.
134 (operand_types): Drop Reg entry.
135 (output_operand_type): New parameter "class". Process it.
136 (process_i386_operand_type): New local variable "class".
137 (main): Adjust static assertions.
138 * i386-opc.h (CLASS_WIDTH): Define.
139 (enum operand_class): New.
140 (Reg): Replace by Class. Adjust comment.
141 (union i386_operand_type): Replace reg by class.
142 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
144 * i386-reg.tbl: Replace Reg by Class=Reg.
145 * i386-init.h: Re-generate.
147 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
149 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
150 (aarch64_opcode_table): Add data gathering hint mnemonic.
151 * opcodes/aarch64-dis-2.c: Account for new instruction.
153 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
155 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
158 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
160 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
161 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
162 aarch64_feature_f64mm): New feature sets.
163 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
164 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
166 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
168 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
169 (OP_SVE_QQQ): New qualifier.
170 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
171 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
172 the movprfx constraint.
173 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
174 (aarch64_opcode_table): Define new instructions smmla,
175 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
177 * aarch64-opc.c (operand_general_constraint_met_p): Handle
178 AARCH64_OPND_SVE_ADDR_RI_S4x32.
179 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
180 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
181 Account for new instructions.
182 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
184 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
186 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
187 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
189 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
191 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
192 (neon_opcodes): Add bfloat SIMD instructions.
193 (print_insn_coprocessor): Add new control character %b to print
194 condition code without checking cp_num.
195 (print_insn_neon): Account for BFloat16 instructions that have no
196 special top-byte handling.
198 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
199 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
201 * arm-dis.c (print_insn_coprocessor,
202 print_insn_generic_coprocessor): Create wrapper functions around
203 the implementation of the print_insn_coprocessor control codes.
204 (print_insn_coprocessor_1): Original print_insn_coprocessor
205 function that now takes which array to look at as an argument.
206 (print_insn_arm): Use both print_insn_coprocessor and
207 print_insn_generic_coprocessor.
208 (print_insn_thumb32): As above.
210 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
211 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
213 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
214 in reglane special case.
215 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
216 aarch64_find_next_opcode): Account for new instructions.
217 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
218 in reglane special case.
219 * aarch64-opc.c (struct operand_qualifier_data): Add data for
220 new AARCH64_OPND_QLF_S_2H qualifier.
221 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
222 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
223 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
225 (BFLOAT_SVE, BFLOAT): New feature set macros.
226 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
228 (aarch64_opcode_table): Define new instructions bfdot,
229 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
232 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
233 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
235 * aarch64-tbl.h (ARMV8_6): New macro.
237 2019-11-07 Jan Beulich <jbeulich@suse.com>
239 * i386-dis.c (prefix_table): Add mcommit.
240 (rm_table): Add rdpru.
241 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
242 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
243 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
244 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
245 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
246 * i386-opc.tbl (mcommit, rdpru): New.
247 * i386-init.h, i386-tbl.h: Re-generate.
249 2019-11-07 Jan Beulich <jbeulich@suse.com>
251 * i386-dis.c (OP_Mwait): Drop local variable "names", use
253 (OP_Monitor): Drop local variable "op1_names", re-purpose
254 "names" for it instead, and replace former "names" uses by
257 2019-11-07 Jan Beulich <jbeulich@suse.com>
260 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
262 * opcodes/i386-tbl.h: Re-generate.
264 2019-11-05 Jan Beulich <jbeulich@suse.com>
266 * i386-dis.c (OP_Mwaitx): Delete.
267 (prefix_table): Use OP_Mwait for mwaitx entry.
268 (OP_Mwait): Also handle mwaitx.
270 2019-11-05 Jan Beulich <jbeulich@suse.com>
272 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
273 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
274 (prefix_table): Add respective entries.
275 (rm_table): Link to those entries.
277 2019-11-05 Jan Beulich <jbeulich@suse.com>
279 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
280 (REG_0F1C_P_0_MOD_0): ... this.
281 (REG_0F1E_MOD_3): Rename to ...
282 (REG_0F1E_P_1_MOD_3): ... this.
283 (RM_0F01_REG_5): Rename to ...
284 (RM_0F01_REG_5_MOD_3): ... this.
285 (RM_0F01_REG_7): Rename to ...
286 (RM_0F01_REG_7_MOD_3): ... this.
287 (RM_0F1E_MOD_3_REG_7): Rename to ...
288 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
289 (RM_0FAE_REG_6): Rename to ...
290 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
291 (RM_0FAE_REG_7): Rename to ...
292 (RM_0FAE_REG_7_MOD_3): ... this.
293 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
294 (PREFIX_0F01_REG_5_MOD_0): ... this.
295 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
296 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
297 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
298 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
299 (PREFIX_0FAE_REG_0): Rename to ...
300 (PREFIX_0FAE_REG_0_MOD_3): ... this.
301 (PREFIX_0FAE_REG_1): Rename to ...
302 (PREFIX_0FAE_REG_1_MOD_3): ... this.
303 (PREFIX_0FAE_REG_2): Rename to ...
304 (PREFIX_0FAE_REG_2_MOD_3): ... this.
305 (PREFIX_0FAE_REG_3): Rename to ...
306 (PREFIX_0FAE_REG_3_MOD_3): ... this.
307 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
308 (PREFIX_0FAE_REG_4_MOD_0): ... this.
309 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
310 (PREFIX_0FAE_REG_4_MOD_3): ... this.
311 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
312 (PREFIX_0FAE_REG_5_MOD_0): ... this.
313 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
314 (PREFIX_0FAE_REG_5_MOD_3): ... this.
315 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
316 (PREFIX_0FAE_REG_6_MOD_0): ... this.
317 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
318 (PREFIX_0FAE_REG_6_MOD_3): ... this.
319 (PREFIX_0FAE_REG_7): Rename to ...
320 (PREFIX_0FAE_REG_7_MOD_0): ... this.
321 (PREFIX_MOD_0_0FC3): Rename to ...
322 (PREFIX_0FC3_MOD_0): ... this.
323 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
324 (PREFIX_0FC7_REG_6_MOD_0): ... this.
325 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
326 (PREFIX_0FC7_REG_6_MOD_3): ... this.
327 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
328 (PREFIX_0FC7_REG_7_MOD_3): ... this.
329 (reg_table, prefix_table, mod_table, rm_table): Adjust
332 2019-11-04 Nick Clifton <nickc@redhat.com>
334 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
335 of a v850 system register. Move the v850_sreg_names array into
337 (get_v850_reg_name): Likewise for ordinary register names.
338 (get_v850_vreg_name): Likewise for vector register names.
339 (get_v850_cc_name): Likewise for condition codes.
340 * get_v850_float_cc_name): Likewise for floating point condition
342 (get_v850_cacheop_name): Likewise for cache-ops.
343 (get_v850_prefop_name): Likewise for pref-ops.
344 (disassemble): Use the new accessor functions.
346 2019-10-30 Delia Burduv <delia.burduv@arm.com>
348 * aarch64-opc.c (print_immediate_offset_address): Don't print the
349 immediate for the writeback form of ldraa/ldrab if it is 0.
350 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
351 * aarch64-opc-2.c: Regenerated.
353 2019-10-30 Jan Beulich <jbeulich@suse.com>
355 * i386-gen.c (operand_type_shorthands): Delete.
356 (operand_type_init): Expand previous shorthands.
357 (set_bitfield_from_shorthand): Rename back to ...
358 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
359 of operand_type_init[].
360 (set_bitfield): Adjust call to the above function.
361 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
362 RegXMM, RegYMM, RegZMM): Define.
363 * i386-reg.tbl: Expand prior shorthands.
365 2019-10-30 Jan Beulich <jbeulich@suse.com>
367 * i386-gen.c (output_i386_opcode): Change order of fields
369 * i386-opc.h (struct insn_template): Move operands field.
370 Convert extension_opcode field to unsigned short.
371 * i386-tbl.h: Re-generate.
373 2019-10-30 Jan Beulich <jbeulich@suse.com>
375 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
377 * i386-opc.h (W): Extend comment.
378 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
379 general purpose variants not allowing for byte operands.
380 * i386-tbl.h: Re-generate.
382 2019-10-29 Nick Clifton <nickc@redhat.com>
384 * tic30-dis.c (print_branch): Correct size of operand array.
386 2019-10-29 Nick Clifton <nickc@redhat.com>
388 * d30v-dis.c (print_insn): Check that operand index is valid
389 before attempting to access the operands array.
391 2019-10-29 Nick Clifton <nickc@redhat.com>
393 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
394 locating the bit to be tested.
396 2019-10-29 Nick Clifton <nickc@redhat.com>
398 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
400 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
401 (print_insn_s12z): Check for illegal size values.
403 2019-10-28 Nick Clifton <nickc@redhat.com>
405 * csky-dis.c (csky_chars_to_number): Check for a negative
406 count. Use an unsigned integer to construct the return value.
408 2019-10-28 Nick Clifton <nickc@redhat.com>
410 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
411 operand buffer. Set value to 15 not 13.
412 (get_register_operand): Use OPERAND_BUFFER_LEN.
413 (get_indirect_operand): Likewise.
414 (print_two_operand): Likewise.
415 (print_three_operand): Likewise.
416 (print_oar_insn): Likewise.
418 2019-10-28 Nick Clifton <nickc@redhat.com>
420 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
421 (bit_extract_simple): Likewise.
422 (bit_copy): Likewise.
423 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
424 index_offset array are not accessed.
426 2019-10-28 Nick Clifton <nickc@redhat.com>
428 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
431 2019-10-25 Nick Clifton <nickc@redhat.com>
433 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
434 access to opcodes.op array element.
436 2019-10-23 Nick Clifton <nickc@redhat.com>
438 * rx-dis.c (get_register_name): Fix spelling typo in error
440 (get_condition_name, get_flag_name, get_double_register_name)
441 (get_double_register_high_name, get_double_register_low_name)
442 (get_double_control_register_name, get_double_condition_name)
443 (get_opsize_name, get_size_name): Likewise.
445 2019-10-22 Nick Clifton <nickc@redhat.com>
447 * rx-dis.c (get_size_name): New function. Provides safe
448 access to name array.
449 (get_opsize_name): Likewise.
450 (print_insn_rx): Use the accessor functions.
452 2019-10-16 Nick Clifton <nickc@redhat.com>
454 * rx-dis.c (get_register_name): New function. Provides safe
455 access to name array.
456 (get_condition_name, get_flag_name, get_double_register_name)
457 (get_double_register_high_name, get_double_register_low_name)
458 (get_double_control_register_name, get_double_condition_name):
460 (print_insn_rx): Use the accessor functions.
462 2019-10-09 Nick Clifton <nickc@redhat.com>
465 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
468 2019-10-07 Jan Beulich <jbeulich@suse.com>
470 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
471 (cmpsd): Likewise. Move EsSeg to other operand.
472 * opcodes/i386-tbl.h: Re-generate.
474 2019-09-23 Alan Modra <amodra@gmail.com>
476 * m68k-dis.c: Include cpu-m68k.h
478 2019-09-23 Alan Modra <amodra@gmail.com>
480 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
481 "elf/mips.h" earlier.
483 2018-09-20 Jan Beulich <jbeulich@suse.com>
486 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
488 * i386-tbl.h: Re-generate.
490 2019-09-18 Alan Modra <amodra@gmail.com>
492 * arc-ext.c: Update throughout for bfd section macro changes.
494 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
496 * Makefile.in: Re-generate.
497 * configure: Re-generate.
499 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
501 * riscv-opc.c (riscv_opcodes): Change subset field
502 to insn_class field for all instructions.
503 (riscv_insn_types): Likewise.
505 2019-09-16 Phil Blundell <pb@pbcl.net>
507 * configure: Regenerated.
509 2019-09-10 Miod Vallat <miod@online.fr>
512 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
514 2019-09-09 Phil Blundell <pb@pbcl.net>
516 binutils 2.33 branch created.
518 2019-09-03 Nick Clifton <nickc@redhat.com>
521 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
522 greater than zero before indexing via (bufcnt -1).
524 2019-09-03 Nick Clifton <nickc@redhat.com>
527 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
528 (MAX_SPEC_REG_NAME_LEN): Define.
529 (struct mmix_dis_info): Use defined constants for array lengths.
530 (get_reg_name): New function.
531 (get_sprec_reg_name): New function.
532 (print_insn_mmix): Use new functions.
534 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
536 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
537 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
538 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
540 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
542 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
543 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
544 (aarch64_sys_reg_supported_p): Update checks for the above.
546 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
548 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
549 cases MVE_SQRSHRL and MVE_UQRSHLL.
550 (print_insn_mve): Add case for specifier 'k' to check
551 specific bit of the instruction.
553 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
556 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
557 encountering an unknown machine type.
558 (print_insn_arc): Handle arc_insn_length returning 0. In error
559 cases return -1 rather than calling abort.
561 2019-08-07 Jan Beulich <jbeulich@suse.com>
563 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
564 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
566 * i386-tbl.h: Re-generate.
568 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
570 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
573 2019-07-30 Mel Chen <mel.chen@sifive.com>
575 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
576 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
578 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
581 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
583 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
584 and MPY class instructions.
585 (parse_option): Add nps400 option.
586 (print_arc_disassembler_options): Add nps400 info.
588 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
590 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
593 * arc-opc.c (RAD_CHK): Add.
594 * arc-tbl.h: Regenerate.
596 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
598 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
599 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
601 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
603 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
604 instructions as UNPREDICTABLE.
606 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
608 * bpf-desc.c: Regenerated.
610 2019-07-17 Jan Beulich <jbeulich@suse.com>
612 * i386-gen.c (static_assert): Define.
614 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
615 (Opcode_Modifier_Num): ... this.
618 2019-07-16 Jan Beulich <jbeulich@suse.com>
620 * i386-gen.c (operand_types): Move RegMem ...
621 (opcode_modifiers): ... here.
622 * i386-opc.h (RegMem): Move to opcode modifer enum.
623 (union i386_operand_type): Move regmem field ...
624 (struct i386_opcode_modifier): ... here.
625 * i386-opc.tbl (RegMem): Define.
626 (mov, movq): Move RegMem on segment, control, debug, and test
628 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
629 to non-SSE2AVX flavor.
630 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
631 Move RegMem on register only flavors. Drop IgnoreSize from
632 legacy encoding flavors.
633 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
635 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
636 register only flavors.
637 (vmovd): Move RegMem and drop IgnoreSize on register only
638 flavor. Change opcode and operand order to store form.
639 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
641 2019-07-16 Jan Beulich <jbeulich@suse.com>
643 * i386-gen.c (operand_type_init, operand_types): Replace SReg
645 * i386-opc.h (SReg2, SReg3): Replace by ...
647 (union i386_operand_type): Replace sreg fields.
648 * i386-opc.tbl (mov, ): Use SReg.
649 (push, pop): Likewies. Drop i386 and x86-64 specific segment
651 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
652 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
654 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
656 * bpf-desc.c: Regenerate.
657 * bpf-opc.c: Likewise.
658 * bpf-opc.h: Likewise.
660 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
662 * bpf-desc.c: Regenerate.
663 * bpf-opc.c: Likewise.
665 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
667 * arm-dis.c (print_insn_coprocessor): Rename index to
670 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
672 * riscv-opc.c (riscv_insn_types): Add r4 type.
674 * riscv-opc.c (riscv_insn_types): Add b and j type.
676 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
677 format for sb type and correct s type.
679 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
681 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
682 SVE FMOV alias of FCPY.
684 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
686 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
687 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
689 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
691 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
692 registers in an instruction prefixed by MOVPRFX.
694 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
696 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
697 sve_size_13 icode to account for variant behaviour of
699 * aarch64-dis-2.c: Regenerate.
700 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
701 sve_size_13 icode to account for variant behaviour of
703 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
704 (OP_SVE_VVV_Q_D): Add new qualifier.
705 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
706 (struct aarch64_opcode): Split pmull{t,b} into those requiring
709 2019-07-01 Jan Beulich <jbeulich@suse.com>
711 * opcodes/i386-gen.c (operand_type_init): Remove
712 OPERAND_TYPE_VEC_IMM4 entry.
713 (operand_types): Remove Vec_Imm4.
714 * opcodes/i386-opc.h (Vec_Imm4): Delete.
715 (union i386_operand_type): Remove vec_imm4.
716 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
717 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
719 2019-07-01 Jan Beulich <jbeulich@suse.com>
721 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
722 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
723 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
724 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
725 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
726 monitorx, mwaitx): Drop ImmExt from operand-less forms.
727 * i386-tbl.h: Re-generate.
729 2019-07-01 Jan Beulich <jbeulich@suse.com>
731 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
733 * i386-tbl.h: Re-generate.
735 2019-07-01 Jan Beulich <jbeulich@suse.com>
737 * i386-opc.tbl (C): New.
738 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
739 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
740 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
741 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
742 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
743 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
744 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
745 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
746 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
747 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
748 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
749 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
750 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
751 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
752 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
753 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
754 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
755 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
756 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
757 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
758 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
759 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
760 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
761 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
762 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
763 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
765 * i386-tbl.h: Re-generate.
767 2019-07-01 Jan Beulich <jbeulich@suse.com>
769 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
771 * i386-tbl.h: Re-generate.
773 2019-07-01 Jan Beulich <jbeulich@suse.com>
775 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
776 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
777 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
778 * i386-tbl.h: Re-generate.
780 2019-07-01 Jan Beulich <jbeulich@suse.com>
782 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
783 Disp8MemShift from register only templates.
784 * i386-tbl.h: Re-generate.
786 2019-07-01 Jan Beulich <jbeulich@suse.com>
788 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
789 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
790 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
791 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
792 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
793 EVEX_W_0F11_P_3_M_1): Delete.
794 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
795 EVEX_W_0F11_P_3): New.
796 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
797 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
798 MOD_EVEX_0F11_PREFIX_3 table entries.
799 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
800 PREFIX_EVEX_0F11 table entries.
801 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
802 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
803 EVEX_W_0F11_P_3_M_{0,1} table entries.
805 2019-07-01 Jan Beulich <jbeulich@suse.com>
807 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
810 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
813 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
814 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
815 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
816 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
817 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
818 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
819 EVEX_LEN_0F38C7_R_6_P_2_W_1.
820 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
821 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
822 PREFIX_EVEX_0F38C6_REG_6 entries.
823 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
824 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
825 EVEX_W_0F38C7_R_6_P_2 entries.
826 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
827 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
828 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
829 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
830 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
831 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
832 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
834 2019-06-27 Jan Beulich <jbeulich@suse.com>
836 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
837 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
838 VEX_LEN_0F2D_P_3): Delete.
839 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
840 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
841 (prefix_table): ... here.
843 2019-06-27 Jan Beulich <jbeulich@suse.com>
845 * i386-dis.c (Iq): Delete.
847 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
849 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
850 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
851 (OP_E_memory): Also honor needindex when deciding whether an
852 address size prefix needs printing.
853 (OP_I): Remove handling of q_mode. Add handling of d_mode.
855 2019-06-26 Jim Wilson <jimw@sifive.com>
858 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
859 Set info->display_endian to info->endian_code.
861 2019-06-25 Jan Beulich <jbeulich@suse.com>
863 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
864 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
865 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
866 OPERAND_TYPE_ACC64 entries.
867 * i386-init.h: Re-generate.
869 2019-06-25 Jan Beulich <jbeulich@suse.com>
871 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
873 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
875 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
877 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
878 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
880 2019-06-25 Jan Beulich <jbeulich@suse.com>
882 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
885 2019-06-25 Jan Beulich <jbeulich@suse.com>
887 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
888 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
890 * i386-opc.tbl (movnti): Add IgnoreSize.
891 * i386-tbl.h: Re-generate.
893 2019-06-25 Jan Beulich <jbeulich@suse.com>
895 * i386-opc.tbl (and): Mark Imm8S form for optimization.
896 * i386-tbl.h: Re-generate.
898 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
900 * i386-dis-evex.h: Break into ...
901 * i386-dis-evex-len.h: New file.
902 * i386-dis-evex-mod.h: Likewise.
903 * i386-dis-evex-prefix.h: Likewise.
904 * i386-dis-evex-reg.h: Likewise.
905 * i386-dis-evex-w.h: Likewise.
906 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
907 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
910 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
913 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
914 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
916 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
917 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
918 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
919 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
920 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
921 EVEX_LEN_0F385B_P_2_W_1.
922 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
923 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
924 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
925 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
926 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
927 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
928 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
929 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
930 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
931 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
933 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
936 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
937 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
938 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
939 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
940 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
941 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
942 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
943 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
944 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
945 EVEX_LEN_0F3A43_P_2_W_1.
946 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
947 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
948 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
949 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
950 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
951 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
952 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
953 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
954 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
955 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
956 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
957 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
959 2019-06-14 Nick Clifton <nickc@redhat.com>
961 * po/fr.po; Updated French translation.
963 2019-06-13 Stafford Horne <shorne@gmail.com>
965 * or1k-asm.c: Regenerated.
966 * or1k-desc.c: Regenerated.
967 * or1k-desc.h: Regenerated.
968 * or1k-dis.c: Regenerated.
969 * or1k-ibld.c: Regenerated.
970 * or1k-opc.c: Regenerated.
971 * or1k-opc.h: Regenerated.
972 * or1k-opinst.c: Regenerated.
974 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
976 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
978 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
981 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
982 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
983 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
984 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
985 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
986 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
987 EVEX_LEN_0F3A1B_P_2_W_1.
988 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
989 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
990 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
991 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
992 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
993 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
994 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
995 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
997 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1000 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1001 EVEX.vvvv when disassembling VEX and EVEX instructions.
1002 (OP_VEX): Set vex.register_specifier to 0 after readding
1003 vex.register_specifier.
1004 (OP_Vex_2src_1): Likewise.
1005 (OP_Vex_2src_2): Likewise.
1006 (OP_LWP_E): Likewise.
1007 (OP_EX_Vex): Don't check vex.register_specifier.
1008 (OP_XMM_Vex): Likewise.
1010 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1011 Lili Cui <lili.cui@intel.com>
1013 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1014 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1016 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1017 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1018 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1019 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1020 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1021 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1022 * i386-init.h: Regenerated.
1023 * i386-tbl.h: Likewise.
1025 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1026 Lili Cui <lili.cui@intel.com>
1028 * doc/c-i386.texi: Document enqcmd.
1029 * testsuite/gas/i386/enqcmd-intel.d: New file.
1030 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1031 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1032 * testsuite/gas/i386/enqcmd.d: Likewise.
1033 * testsuite/gas/i386/enqcmd.s: Likewise.
1034 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1035 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1036 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1037 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1038 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1039 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1040 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1043 2019-06-04 Alan Hayward <alan.hayward@arm.com>
1045 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1047 2019-06-03 Alan Modra <amodra@gmail.com>
1049 * ppc-dis.c (prefix_opcd_indices): Correct size.
1051 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1054 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1056 * i386-tbl.h: Regenerated.
1058 2019-05-24 Alan Modra <amodra@gmail.com>
1060 * po/POTFILES.in: Regenerate.
1062 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1063 Alan Modra <amodra@gmail.com>
1065 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1066 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1067 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1068 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1069 XTOP>): Define and add entries.
1070 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1071 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1072 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1073 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1075 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1076 Alan Modra <amodra@gmail.com>
1078 * ppc-dis.c (ppc_opts): Add "future" entry.
1079 (PREFIX_OPCD_SEGS): Define.
1080 (prefix_opcd_indices): New array.
1081 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1082 (lookup_prefix): New function.
1083 (print_insn_powerpc): Handle 64-bit prefix instructions.
1084 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1085 (PMRR, POWERXX): Define.
1086 (prefix_opcodes): New instruction table.
1087 (prefix_num_opcodes): New constant.
1089 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1091 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1092 * configure: Regenerated.
1093 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1095 (HFILES): Add bpf-desc.h and bpf-opc.h.
1096 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1097 bpf-ibld.c and bpf-opc.c.
1099 * Makefile.in: Regenerated.
1100 * disassemble.c (ARCH_bpf): Define.
1101 (disassembler): Add case for bfd_arch_bpf.
1102 (disassemble_init_for_target): Likewise.
1103 (enum epbf_isa_attr): Define.
1104 * disassemble.h: extern print_insn_bpf.
1105 * bpf-asm.c: Generated.
1106 * bpf-opc.h: Likewise.
1107 * bpf-opc.c: Likewise.
1108 * bpf-ibld.c: Likewise.
1109 * bpf-dis.c: Likewise.
1110 * bpf-desc.h: Likewise.
1111 * bpf-desc.c: Likewise.
1113 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1115 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1116 and VMSR with the new operands.
1118 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1120 * arm-dis.c (enum mve_instructions): New enum
1121 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1123 (mve_opcodes): New instructions as above.
1124 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1126 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1128 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1130 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1131 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1132 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1133 uqshl, urshrl and urshr.
1134 (is_mve_okay_in_it): Add new instructions to TRUE list.
1135 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1136 (print_insn_mve): Updated to accept new %j,
1137 %<bitfield>m and %<bitfield>n patterns.
1139 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1141 * mips-opc.c (mips_builtin_opcodes): Change source register
1142 constraint for DAUI.
1144 2019-05-20 Nick Clifton <nickc@redhat.com>
1146 * po/fr.po: Updated French translation.
1148 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1149 Michael Collison <michael.collison@arm.com>
1151 * arm-dis.c (thumb32_opcodes): Add new instructions.
1152 (enum mve_instructions): Likewise.
1153 (enum mve_undefined): Add new reasons.
1154 (is_mve_encoding_conflict): Handle new instructions.
1155 (is_mve_undefined): Likewise.
1156 (is_mve_unpredictable): Likewise.
1157 (print_mve_undefined): Likewise.
1158 (print_mve_size): Likewise.
1160 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1161 Michael Collison <michael.collison@arm.com>
1163 * arm-dis.c (thumb32_opcodes): Add new instructions.
1164 (enum mve_instructions): Likewise.
1165 (is_mve_encoding_conflict): Handle new instructions.
1166 (is_mve_undefined): Likewise.
1167 (is_mve_unpredictable): Likewise.
1168 (print_mve_size): Likewise.
1170 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1171 Michael Collison <michael.collison@arm.com>
1173 * arm-dis.c (thumb32_opcodes): Add new instructions.
1174 (enum mve_instructions): Likewise.
1175 (is_mve_encoding_conflict): Likewise.
1176 (is_mve_unpredictable): Likewise.
1177 (print_mve_size): Likewise.
1179 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1180 Michael Collison <michael.collison@arm.com>
1182 * arm-dis.c (thumb32_opcodes): Add new instructions.
1183 (enum mve_instructions): Likewise.
1184 (is_mve_encoding_conflict): Handle new instructions.
1185 (is_mve_undefined): Likewise.
1186 (is_mve_unpredictable): Likewise.
1187 (print_mve_size): Likewise.
1189 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1190 Michael Collison <michael.collison@arm.com>
1192 * arm-dis.c (thumb32_opcodes): Add new instructions.
1193 (enum mve_instructions): Likewise.
1194 (is_mve_encoding_conflict): Handle new instructions.
1195 (is_mve_undefined): Likewise.
1196 (is_mve_unpredictable): Likewise.
1197 (print_mve_size): Likewise.
1198 (print_insn_mve): Likewise.
1200 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1201 Michael Collison <michael.collison@arm.com>
1203 * arm-dis.c (thumb32_opcodes): Add new instructions.
1204 (print_insn_thumb32): Handle new instructions.
1206 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1207 Michael Collison <michael.collison@arm.com>
1209 * arm-dis.c (enum mve_instructions): Add new instructions.
1210 (enum mve_undefined): Add new reasons.
1211 (is_mve_encoding_conflict): Handle new instructions.
1212 (is_mve_undefined): Likewise.
1213 (is_mve_unpredictable): Likewise.
1214 (print_mve_undefined): Likewise.
1215 (print_mve_size): Likewise.
1216 (print_mve_shift_n): Likewise.
1217 (print_insn_mve): Likewise.
1219 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1220 Michael Collison <michael.collison@arm.com>
1222 * arm-dis.c (enum mve_instructions): Add new instructions.
1223 (is_mve_encoding_conflict): Handle new instructions.
1224 (is_mve_unpredictable): Likewise.
1225 (print_mve_rotate): Likewise.
1226 (print_mve_size): Likewise.
1227 (print_insn_mve): Likewise.
1229 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1230 Michael Collison <michael.collison@arm.com>
1232 * arm-dis.c (enum mve_instructions): Add new instructions.
1233 (is_mve_encoding_conflict): Handle new instructions.
1234 (is_mve_unpredictable): Likewise.
1235 (print_mve_size): Likewise.
1236 (print_insn_mve): Likewise.
1238 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1239 Michael Collison <michael.collison@arm.com>
1241 * arm-dis.c (enum mve_instructions): Add new instructions.
1242 (enum mve_undefined): Add new reasons.
1243 (is_mve_encoding_conflict): Handle new instructions.
1244 (is_mve_undefined): Likewise.
1245 (is_mve_unpredictable): Likewise.
1246 (print_mve_undefined): Likewise.
1247 (print_mve_size): Likewise.
1248 (print_insn_mve): Likewise.
1250 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1251 Michael Collison <michael.collison@arm.com>
1253 * arm-dis.c (enum mve_instructions): Add new instructions.
1254 (is_mve_encoding_conflict): Handle new instructions.
1255 (is_mve_undefined): Likewise.
1256 (is_mve_unpredictable): Likewise.
1257 (print_mve_size): Likewise.
1258 (print_insn_mve): Likewise.
1260 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1261 Michael Collison <michael.collison@arm.com>
1263 * arm-dis.c (enum mve_instructions): Add new instructions.
1264 (enum mve_unpredictable): Add new reasons.
1265 (enum mve_undefined): Likewise.
1266 (is_mve_okay_in_it): Handle new isntructions.
1267 (is_mve_encoding_conflict): Likewise.
1268 (is_mve_undefined): Likewise.
1269 (is_mve_unpredictable): Likewise.
1270 (print_mve_vmov_index): Likewise.
1271 (print_simd_imm8): Likewise.
1272 (print_mve_undefined): Likewise.
1273 (print_mve_unpredictable): Likewise.
1274 (print_mve_size): Likewise.
1275 (print_insn_mve): Likewise.
1277 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1278 Michael Collison <michael.collison@arm.com>
1280 * arm-dis.c (enum mve_instructions): Add new instructions.
1281 (enum mve_unpredictable): Add new reasons.
1282 (enum mve_undefined): Likewise.
1283 (is_mve_encoding_conflict): Handle new instructions.
1284 (is_mve_undefined): Likewise.
1285 (is_mve_unpredictable): Likewise.
1286 (print_mve_undefined): Likewise.
1287 (print_mve_unpredictable): Likewise.
1288 (print_mve_rounding_mode): Likewise.
1289 (print_mve_vcvt_size): Likewise.
1290 (print_mve_size): Likewise.
1291 (print_insn_mve): Likewise.
1293 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1294 Michael Collison <michael.collison@arm.com>
1296 * arm-dis.c (enum mve_instructions): Add new instructions.
1297 (enum mve_unpredictable): Add new reasons.
1298 (enum mve_undefined): Likewise.
1299 (is_mve_undefined): Handle new instructions.
1300 (is_mve_unpredictable): Likewise.
1301 (print_mve_undefined): Likewise.
1302 (print_mve_unpredictable): Likewise.
1303 (print_mve_size): Likewise.
1304 (print_insn_mve): Likewise.
1306 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1307 Michael Collison <michael.collison@arm.com>
1309 * arm-dis.c (enum mve_instructions): Add new instructions.
1310 (enum mve_undefined): Add new reasons.
1311 (insns): Add new instructions.
1312 (is_mve_encoding_conflict):
1313 (print_mve_vld_str_addr): New print function.
1314 (is_mve_undefined): Handle new instructions.
1315 (is_mve_unpredictable): Likewise.
1316 (print_mve_undefined): Likewise.
1317 (print_mve_size): Likewise.
1318 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1319 (print_insn_mve): Handle new operands.
1321 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1322 Michael Collison <michael.collison@arm.com>
1324 * arm-dis.c (enum mve_instructions): Add new instructions.
1325 (enum mve_unpredictable): Add new reasons.
1326 (is_mve_encoding_conflict): Handle new instructions.
1327 (is_mve_unpredictable): Likewise.
1328 (mve_opcodes): Add new instructions.
1329 (print_mve_unpredictable): Handle new reasons.
1330 (print_mve_register_blocks): New print function.
1331 (print_mve_size): Handle new instructions.
1332 (print_insn_mve): Likewise.
1334 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1335 Michael Collison <michael.collison@arm.com>
1337 * arm-dis.c (enum mve_instructions): Add new instructions.
1338 (enum mve_unpredictable): Add new reasons.
1339 (enum mve_undefined): Likewise.
1340 (is_mve_encoding_conflict): Handle new instructions.
1341 (is_mve_undefined): Likewise.
1342 (is_mve_unpredictable): Likewise.
1343 (coprocessor_opcodes): Move NEON VDUP from here...
1344 (neon_opcodes): ... to here.
1345 (mve_opcodes): Add new instructions.
1346 (print_mve_undefined): Handle new reasons.
1347 (print_mve_unpredictable): Likewise.
1348 (print_mve_size): Handle new instructions.
1349 (print_insn_neon): Handle vdup.
1350 (print_insn_mve): Handle new operands.
1352 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1353 Michael Collison <michael.collison@arm.com>
1355 * arm-dis.c (enum mve_instructions): Add new instructions.
1356 (enum mve_unpredictable): Add new values.
1357 (mve_opcodes): Add new instructions.
1358 (vec_condnames): New array with vector conditions.
1359 (mve_predicatenames): New array with predicate suffixes.
1360 (mve_vec_sizename): New array with vector sizes.
1361 (enum vpt_pred_state): New enum with vector predication states.
1362 (struct vpt_block): New struct type for vpt blocks.
1363 (vpt_block_state): Global struct to keep track of state.
1364 (mve_extract_pred_mask): New helper function.
1365 (num_instructions_vpt_block): Likewise.
1366 (mark_outside_vpt_block): Likewise.
1367 (mark_inside_vpt_block): Likewise.
1368 (invert_next_predicate_state): Likewise.
1369 (update_next_predicate_state): Likewise.
1370 (update_vpt_block_state): Likewise.
1371 (is_vpt_instruction): Likewise.
1372 (is_mve_encoding_conflict): Add entries for new instructions.
1373 (is_mve_unpredictable): Likewise.
1374 (print_mve_unpredictable): Handle new cases.
1375 (print_instruction_predicate): Likewise.
1376 (print_mve_size): New function.
1377 (print_vec_condition): New function.
1378 (print_insn_mve): Handle vpt blocks and new print operands.
1380 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1382 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1383 8, 14 and 15 for Armv8.1-M Mainline.
1385 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1386 Michael Collison <michael.collison@arm.com>
1388 * arm-dis.c (enum mve_instructions): New enum.
1389 (enum mve_unpredictable): Likewise.
1390 (enum mve_undefined): Likewise.
1391 (struct mopcode32): New struct.
1392 (is_mve_okay_in_it): New function.
1393 (is_mve_architecture): Likewise.
1394 (arm_decode_field): Likewise.
1395 (arm_decode_field_multiple): Likewise.
1396 (is_mve_encoding_conflict): Likewise.
1397 (is_mve_undefined): Likewise.
1398 (is_mve_unpredictable): Likewise.
1399 (print_mve_undefined): Likewise.
1400 (print_mve_unpredictable): Likewise.
1401 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1402 (print_insn_mve): New function.
1403 (print_insn_thumb32): Handle MVE architecture.
1404 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1406 2019-05-10 Nick Clifton <nickc@redhat.com>
1409 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1410 end of the table prematurely.
1412 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1414 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1417 2019-05-11 Alan Modra <amodra@gmail.com>
1419 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1420 when -Mraw is in effect.
1422 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1424 * aarch64-dis-2.c: Regenerate.
1425 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1426 (OP_SVE_BBB): New variant set.
1427 (OP_SVE_DDDD): New variant set.
1428 (OP_SVE_HHH): New variant set.
1429 (OP_SVE_HHHU): New variant set.
1430 (OP_SVE_SSS): New variant set.
1431 (OP_SVE_SSSU): New variant set.
1432 (OP_SVE_SHH): New variant set.
1433 (OP_SVE_SBBU): New variant set.
1434 (OP_SVE_DSS): New variant set.
1435 (OP_SVE_DHHU): New variant set.
1436 (OP_SVE_VMV_HSD_BHS): New variant set.
1437 (OP_SVE_VVU_HSD_BHS): New variant set.
1438 (OP_SVE_VVVU_SD_BH): New variant set.
1439 (OP_SVE_VVVU_BHSD): New variant set.
1440 (OP_SVE_VVV_QHD_DBS): New variant set.
1441 (OP_SVE_VVV_HSD_BHS): New variant set.
1442 (OP_SVE_VVV_HSD_BHS2): New variant set.
1443 (OP_SVE_VVV_BHS_HSD): New variant set.
1444 (OP_SVE_VV_BHS_HSD): New variant set.
1445 (OP_SVE_VVV_SD): New variant set.
1446 (OP_SVE_VVU_BHS_HSD): New variant set.
1447 (OP_SVE_VZVV_SD): New variant set.
1448 (OP_SVE_VZVV_BH): New variant set.
1449 (OP_SVE_VZV_SD): New variant set.
1450 (aarch64_opcode_table): Add sve2 instructions.
1452 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1454 * aarch64-asm-2.c: Regenerated.
1455 * aarch64-dis-2.c: Regenerated.
1456 * aarch64-opc-2.c: Regenerated.
1457 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1458 for SVE_SHLIMM_UNPRED_22.
1459 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1460 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1463 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1465 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1466 sve_size_tsz_bhs iclass encode.
1467 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1468 sve_size_tsz_bhs iclass decode.
1470 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1472 * aarch64-asm-2.c: Regenerated.
1473 * aarch64-dis-2.c: Regenerated.
1474 * aarch64-opc-2.c: Regenerated.
1475 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1476 for SVE_Zm4_11_INDEX.
1477 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1478 (fields): Handle SVE_i2h field.
1479 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1480 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1482 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1484 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1485 sve_shift_tsz_bhsd iclass encode.
1486 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1487 sve_shift_tsz_bhsd iclass decode.
1489 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1491 * aarch64-asm-2.c: Regenerated.
1492 * aarch64-dis-2.c: Regenerated.
1493 * aarch64-opc-2.c: Regenerated.
1494 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1495 (aarch64_encode_variant_using_iclass): Handle
1496 sve_shift_tsz_hsd iclass encode.
1497 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1498 sve_shift_tsz_hsd iclass decode.
1499 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1500 for SVE_SHRIMM_UNPRED_22.
1501 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1502 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1505 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1507 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1508 sve_size_013 iclass encode.
1509 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1510 sve_size_013 iclass decode.
1512 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1514 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1515 sve_size_bh iclass encode.
1516 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1517 sve_size_bh iclass decode.
1519 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1521 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1522 sve_size_sd2 iclass encode.
1523 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1524 sve_size_sd2 iclass decode.
1525 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1526 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1528 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1530 * aarch64-asm-2.c: Regenerated.
1531 * aarch64-dis-2.c: Regenerated.
1532 * aarch64-opc-2.c: Regenerated.
1533 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1535 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1536 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1538 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1540 * aarch64-asm-2.c: Regenerated.
1541 * aarch64-dis-2.c: Regenerated.
1542 * aarch64-opc-2.c: Regenerated.
1543 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1544 for SVE_Zm3_11_INDEX.
1545 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1546 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1547 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1549 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1551 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1553 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1554 sve_size_hsd2 iclass encode.
1555 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1556 sve_size_hsd2 iclass decode.
1557 * aarch64-opc.c (fields): Handle SVE_size field.
1558 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1560 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1562 * aarch64-asm-2.c: Regenerated.
1563 * aarch64-dis-2.c: Regenerated.
1564 * aarch64-opc-2.c: Regenerated.
1565 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1567 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1568 (fields): Handle SVE_rot3 field.
1569 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1570 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1572 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1574 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1577 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1580 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1581 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1582 aarch64_feature_sve2bitperm): New feature sets.
1583 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1584 for feature set addresses.
1585 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1586 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1588 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1589 Faraz Shahbazker <fshahbazker@wavecomp.com>
1591 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1592 argument and set ASE_EVA_R6 appropriately.
1593 (set_default_mips_dis_options): Pass ISA to above.
1594 (parse_mips_dis_option): Likewise.
1595 * mips-opc.c (EVAR6): New macro.
1596 (mips_builtin_opcodes): Add llwpe, scwpe.
1598 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1600 * aarch64-asm-2.c: Regenerated.
1601 * aarch64-dis-2.c: Regenerated.
1602 * aarch64-opc-2.c: Regenerated.
1603 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1604 AARCH64_OPND_TME_UIMM16.
1605 (aarch64_print_operand): Likewise.
1606 * aarch64-tbl.h (QL_IMM_NIL): New.
1609 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1611 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1613 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1615 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1616 Faraz Shahbazker <fshahbazker@wavecomp.com>
1618 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1620 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1622 * s12z-opc.h: Add extern "C" bracketing to help
1623 users who wish to use this interface in c++ code.
1625 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1627 * s12z-opc.c (bm_decode): Handle bit map operations with the
1630 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1632 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1633 specifier. Add entries for VLDR and VSTR of system registers.
1634 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1635 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1636 of %J and %K format specifier.
1638 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1640 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1641 Add new entries for VSCCLRM instruction.
1642 (print_insn_coprocessor): Handle new %C format control code.
1644 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1646 * arm-dis.c (enum isa): New enum.
1647 (struct sopcode32): New structure.
1648 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1649 set isa field of all current entries to ANY.
1650 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1651 Only match an entry if its isa field allows the current mode.
1653 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1655 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1657 (print_insn_thumb32): Add logic to print %n CLRM register list.
1659 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1661 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1664 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1666 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1667 (print_insn_thumb32): Edit the switch case for %Z.
1669 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1671 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1673 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1675 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1677 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1679 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1681 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1683 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1684 Arm register with r13 and r15 unpredictable.
1685 (thumb32_opcodes): New instructions for bfx and bflx.
1687 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1689 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1691 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1693 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1695 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1697 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1699 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1701 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1703 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1705 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1706 "optr". ("operator" is a reserved word in c++).
1708 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1710 * aarch64-opc.c (aarch64_print_operand): Add case for
1712 (verify_constraints): Likewise.
1713 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1714 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1715 to accept Rt|SP as first operand.
1716 (AARCH64_OPERANDS): Add new Rt_SP.
1717 * aarch64-asm-2.c: Regenerated.
1718 * aarch64-dis-2.c: Regenerated.
1719 * aarch64-opc-2.c: Regenerated.
1721 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1723 * aarch64-asm-2.c: Regenerated.
1724 * aarch64-dis-2.c: Likewise.
1725 * aarch64-opc-2.c: Likewise.
1726 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1728 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1730 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1732 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1734 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1735 * i386-init.h: Regenerated.
1737 2019-04-07 Alan Modra <amodra@gmail.com>
1739 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1740 op_separator to control printing of spaces, comma and parens
1741 rather than need_comma, need_paren and spaces vars.
1743 2019-04-07 Alan Modra <amodra@gmail.com>
1746 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1747 (print_insn_neon, print_insn_arm): Likewise.
1749 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1751 * i386-dis-evex.h (evex_table): Updated to support BF16
1753 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1754 and EVEX_W_0F3872_P_3.
1755 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1756 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1757 * i386-opc.h (enum): Add CpuAVX512_BF16.
1758 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1759 * i386-opc.tbl: Add AVX512 BF16 instructions.
1760 * i386-init.h: Regenerated.
1761 * i386-tbl.h: Likewise.
1763 2019-04-05 Alan Modra <amodra@gmail.com>
1765 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1766 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1767 to favour printing of "-" branch hint when using the "y" bit.
1768 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1770 2019-04-05 Alan Modra <amodra@gmail.com>
1772 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1773 opcode until first operand is output.
1775 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1778 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1779 (valid_bo_post_v2): Add support for 'at' branch hints.
1780 (insert_bo): Only error on branch on ctr.
1781 (get_bo_hint_mask): New function.
1782 (insert_boe): Add new 'branch_taken' formal argument. Add support
1783 for inserting 'at' branch hints.
1784 (extract_boe): Add new 'branch_taken' formal argument. Add support
1785 for extracting 'at' branch hints.
1786 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1787 (BOE): Delete operand.
1788 (BOM, BOP): New operands.
1790 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1791 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1792 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1793 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1794 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1795 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1796 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1797 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1798 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1799 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1800 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1801 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1802 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1803 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1804 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1805 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1806 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1807 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1808 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1809 bttarl+>: New extended mnemonics.
1811 2019-03-28 Alan Modra <amodra@gmail.com>
1814 * ppc-opc.c (BTF): Define.
1815 (powerpc_opcodes): Use for mtfsb*.
1816 * ppc-dis.c (print_insn_powerpc): Print fields with both
1817 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1819 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1821 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1822 (mapping_symbol_for_insn): Implement new algorithm.
1823 (print_insn): Remove duplicate code.
1825 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1827 * aarch64-dis.c (print_insn_aarch64):
1830 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1832 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1835 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1837 * aarch64-dis.c (last_stop_offset): New.
1838 (print_insn_aarch64): Use stop_offset.
1840 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1843 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1845 * i386-init.h: Regenerated.
1847 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1850 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1851 vmovdqu16, vmovdqu32 and vmovdqu64.
1852 * i386-tbl.h: Regenerated.
1854 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1856 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1857 from vstrszb, vstrszh, and vstrszf.
1859 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1861 * s390-opc.txt: Add instruction descriptions.
1863 2019-02-08 Jim Wilson <jimw@sifive.com>
1865 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1868 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1870 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1872 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1875 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1876 * aarch64-opc.c (verify_elem_sd): New.
1877 (fields): Add FLD_sz entr.
1878 * aarch64-tbl.h (_SIMD_INSN): New.
1879 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1880 fmulx scalar and vector by element isns.
1882 2019-02-07 Nick Clifton <nickc@redhat.com>
1884 * po/sv.po: Updated Swedish translation.
1886 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1888 * s390-mkopc.c (main): Accept arch13 as cpu string.
1889 * s390-opc.c: Add new instruction formats and instruction opcode
1891 * s390-opc.txt: Add new arch13 instructions.
1893 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1895 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1896 (aarch64_opcode): Change encoding for stg, stzg
1898 * aarch64-asm-2.c: Regenerated.
1899 * aarch64-dis-2.c: Regenerated.
1900 * aarch64-opc-2.c: Regenerated.
1902 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1904 * aarch64-asm-2.c: Regenerated.
1905 * aarch64-dis-2.c: Likewise.
1906 * aarch64-opc-2.c: Likewise.
1907 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1909 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1910 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1912 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1913 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1914 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1915 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1916 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1917 case for ldstgv_indexed.
1918 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1919 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1920 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1921 * aarch64-asm-2.c: Regenerated.
1922 * aarch64-dis-2.c: Regenerated.
1923 * aarch64-opc-2.c: Regenerated.
1925 2019-01-23 Nick Clifton <nickc@redhat.com>
1927 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1929 2019-01-21 Nick Clifton <nickc@redhat.com>
1931 * po/de.po: Updated German translation.
1932 * po/uk.po: Updated Ukranian translation.
1934 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1935 * mips-dis.c (mips_arch_choices): Fix typo in
1936 gs464, gs464e and gs264e descriptors.
1938 2019-01-19 Nick Clifton <nickc@redhat.com>
1940 * configure: Regenerate.
1941 * po/opcodes.pot: Regenerate.
1943 2018-06-24 Nick Clifton <nickc@redhat.com>
1945 2.32 branch created.
1947 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1949 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1951 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1954 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1956 * configure: Regenerate.
1958 2019-01-07 Alan Modra <amodra@gmail.com>
1960 * configure: Regenerate.
1961 * po/POTFILES.in: Regenerate.
1963 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1965 * s12z-opc.c: New file.
1966 * s12z-opc.h: New file.
1967 * s12z-dis.c: Removed all code not directly related to display
1968 of instructions. Used the interface provided by the new files
1970 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1971 * Makefile.in: Regenerate.
1972 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1973 * configure: Regenerate.
1975 2019-01-01 Alan Modra <amodra@gmail.com>
1977 Update year range in copyright notice of all files.
1979 For older changes see ChangeLog-2018
1981 Copyright (C) 2019 Free Software Foundation, Inc.
1983 Copying and distribution of this file, with or without modification,
1984 are permitted in any medium without royalty provided the copyright
1985 notice and this notice are preserved.
1991 version-control: never