1 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2 Michael Collison <michael.collison@arm.com>
4 * arm-dis.c (thumb32_opcodes): Add new instructions.
5 (enum mve_instructions): Likewise.
6 (is_mve_encoding_conflict): Handle new instructions.
7 (is_mve_undefined): Likewise.
8 (is_mve_unpredictable): Likewise.
9 (print_mve_size): Likewise.
11 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
12 Michael Collison <michael.collison@arm.com>
14 * arm-dis.c (thumb32_opcodes): Add new instructions.
15 (enum mve_instructions): Likewise.
16 (is_mve_encoding_conflict): Likewise.
17 (is_mve_unpredictable): Likewise.
18 (print_mve_size): Likewise.
20 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
21 Michael Collison <michael.collison@arm.com>
23 * arm-dis.c (thumb32_opcodes): Add new instructions.
24 (enum mve_instructions): Likewise.
25 (is_mve_encoding_conflict): Handle new instructions.
26 (is_mve_undefined): Likewise.
27 (is_mve_unpredictable): Likewise.
28 (print_mve_size): Likewise.
30 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
31 Michael Collison <michael.collison@arm.com>
33 * arm-dis.c (thumb32_opcodes): Add new instructions.
34 (enum mve_instructions): Likewise.
35 (is_mve_encoding_conflict): Handle new instructions.
36 (is_mve_undefined): Likewise.
37 (is_mve_unpredictable): Likewise.
38 (print_mve_size): Likewise.
39 (print_insn_mve): Likewise.
41 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
42 Michael Collison <michael.collison@arm.com>
44 * arm-dis.c (thumb32_opcodes): Add new instructions.
45 (print_insn_thumb32): Handle new instructions.
47 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
48 Michael Collison <michael.collison@arm.com>
50 * arm-dis.c (enum mve_instructions): Add new instructions.
51 (enum mve_undefined): Add new reasons.
52 (is_mve_encoding_conflict): Handle new instructions.
53 (is_mve_undefined): Likewise.
54 (is_mve_unpredictable): Likewise.
55 (print_mve_undefined): Likewise.
56 (print_mve_size): Likewise.
57 (print_mve_shift_n): Likewise.
58 (print_insn_mve): Likewise.
60 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
61 Michael Collison <michael.collison@arm.com>
63 * arm-dis.c (enum mve_instructions): Add new instructions.
64 (is_mve_encoding_conflict): Handle new instructions.
65 (is_mve_unpredictable): Likewise.
66 (print_mve_rotate): Likewise.
67 (print_mve_size): Likewise.
68 (print_insn_mve): Likewise.
70 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
71 Michael Collison <michael.collison@arm.com>
73 * arm-dis.c (enum mve_instructions): Add new instructions.
74 (is_mve_encoding_conflict): Handle new instructions.
75 (is_mve_unpredictable): Likewise.
76 (print_mve_size): Likewise.
77 (print_insn_mve): Likewise.
79 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
80 Michael Collison <michael.collison@arm.com>
82 * arm-dis.c (enum mve_instructions): Add new instructions.
83 (enum mve_undefined): Add new reasons.
84 (is_mve_encoding_conflict): Handle new instructions.
85 (is_mve_undefined): Likewise.
86 (is_mve_unpredictable): Likewise.
87 (print_mve_undefined): Likewise.
88 (print_mve_size): Likewise.
89 (print_insn_mve): Likewise.
91 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
92 Michael Collison <michael.collison@arm.com>
94 * arm-dis.c (enum mve_instructions): Add new instructions.
95 (is_mve_encoding_conflict): Handle new instructions.
96 (is_mve_undefined): Likewise.
97 (is_mve_unpredictable): Likewise.
98 (print_mve_size): Likewise.
99 (print_insn_mve): Likewise.
101 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
102 Michael Collison <michael.collison@arm.com>
104 * arm-dis.c (enum mve_instructions): Add new instructions.
105 (enum mve_unpredictable): Add new reasons.
106 (enum mve_undefined): Likewise.
107 (is_mve_okay_in_it): Handle new isntructions.
108 (is_mve_encoding_conflict): Likewise.
109 (is_mve_undefined): Likewise.
110 (is_mve_unpredictable): Likewise.
111 (print_mve_vmov_index): Likewise.
112 (print_simd_imm8): Likewise.
113 (print_mve_undefined): Likewise.
114 (print_mve_unpredictable): Likewise.
115 (print_mve_size): Likewise.
116 (print_insn_mve): Likewise.
118 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
119 Michael Collison <michael.collison@arm.com>
121 * arm-dis.c (enum mve_instructions): Add new instructions.
122 (enum mve_unpredictable): Add new reasons.
123 (enum mve_undefined): Likewise.
124 (is_mve_encoding_conflict): Handle new instructions.
125 (is_mve_undefined): Likewise.
126 (is_mve_unpredictable): Likewise.
127 (print_mve_undefined): Likewise.
128 (print_mve_unpredictable): Likewise.
129 (print_mve_rounding_mode): Likewise.
130 (print_mve_vcvt_size): Likewise.
131 (print_mve_size): Likewise.
132 (print_insn_mve): Likewise.
134 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
135 Michael Collison <michael.collison@arm.com>
137 * arm-dis.c (enum mve_instructions): Add new instructions.
138 (enum mve_unpredictable): Add new reasons.
139 (enum mve_undefined): Likewise.
140 (is_mve_undefined): Handle new instructions.
141 (is_mve_unpredictable): Likewise.
142 (print_mve_undefined): Likewise.
143 (print_mve_unpredictable): Likewise.
144 (print_mve_size): Likewise.
145 (print_insn_mve): Likewise.
147 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
148 Michael Collison <michael.collison@arm.com>
150 * arm-dis.c (enum mve_instructions): Add new instructions.
151 (enum mve_undefined): Add new reasons.
152 (insns): Add new instructions.
153 (is_mve_encoding_conflict):
154 (print_mve_vld_str_addr): New print function.
155 (is_mve_undefined): Handle new instructions.
156 (is_mve_unpredictable): Likewise.
157 (print_mve_undefined): Likewise.
158 (print_mve_size): Likewise.
159 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
160 (print_insn_mve): Handle new operands.
162 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
163 Michael Collison <michael.collison@arm.com>
165 * arm-dis.c (enum mve_instructions): Add new instructions.
166 (enum mve_unpredictable): Add new reasons.
167 (is_mve_encoding_conflict): Handle new instructions.
168 (is_mve_unpredictable): Likewise.
169 (mve_opcodes): Add new instructions.
170 (print_mve_unpredictable): Handle new reasons.
171 (print_mve_register_blocks): New print function.
172 (print_mve_size): Handle new instructions.
173 (print_insn_mve): Likewise.
175 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
176 Michael Collison <michael.collison@arm.com>
178 * arm-dis.c (enum mve_instructions): Add new instructions.
179 (enum mve_unpredictable): Add new reasons.
180 (enum mve_undefined): Likewise.
181 (is_mve_encoding_conflict): Handle new instructions.
182 (is_mve_undefined): Likewise.
183 (is_mve_unpredictable): Likewise.
184 (coprocessor_opcodes): Move NEON VDUP from here...
185 (neon_opcodes): ... to here.
186 (mve_opcodes): Add new instructions.
187 (print_mve_undefined): Handle new reasons.
188 (print_mve_unpredictable): Likewise.
189 (print_mve_size): Handle new instructions.
190 (print_insn_neon): Handle vdup.
191 (print_insn_mve): Handle new operands.
193 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
194 Michael Collison <michael.collison@arm.com>
196 * arm-dis.c (enum mve_instructions): Add new instructions.
197 (enum mve_unpredictable): Add new values.
198 (mve_opcodes): Add new instructions.
199 (vec_condnames): New array with vector conditions.
200 (mve_predicatenames): New array with predicate suffixes.
201 (mve_vec_sizename): New array with vector sizes.
202 (enum vpt_pred_state): New enum with vector predication states.
203 (struct vpt_block): New struct type for vpt blocks.
204 (vpt_block_state): Global struct to keep track of state.
205 (mve_extract_pred_mask): New helper function.
206 (num_instructions_vpt_block): Likewise.
207 (mark_outside_vpt_block): Likewise.
208 (mark_inside_vpt_block): Likewise.
209 (invert_next_predicate_state): Likewise.
210 (update_next_predicate_state): Likewise.
211 (update_vpt_block_state): Likewise.
212 (is_vpt_instruction): Likewise.
213 (is_mve_encoding_conflict): Add entries for new instructions.
214 (is_mve_unpredictable): Likewise.
215 (print_mve_unpredictable): Handle new cases.
216 (print_instruction_predicate): Likewise.
217 (print_mve_size): New function.
218 (print_vec_condition): New function.
219 (print_insn_mve): Handle vpt blocks and new print operands.
221 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
223 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
224 8, 14 and 15 for Armv8.1-M Mainline.
226 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
227 Michael Collison <michael.collison@arm.com>
229 * arm-dis.c (enum mve_instructions): New enum.
230 (enum mve_unpredictable): Likewise.
231 (enum mve_undefined): Likewise.
232 (struct mopcode32): New struct.
233 (is_mve_okay_in_it): New function.
234 (is_mve_architecture): Likewise.
235 (arm_decode_field): Likewise.
236 (arm_decode_field_multiple): Likewise.
237 (is_mve_encoding_conflict): Likewise.
238 (is_mve_undefined): Likewise.
239 (is_mve_unpredictable): Likewise.
240 (print_mve_undefined): Likewise.
241 (print_mve_unpredictable): Likewise.
242 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
243 (print_insn_mve): New function.
244 (print_insn_thumb32): Handle MVE architecture.
245 (select_arm_features): Force thumb for Armv8.1-m Mainline.
247 2019-05-10 Nick Clifton <nickc@redhat.com>
250 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
251 end of the table prematurely.
253 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
255 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
258 2019-05-11 Alan Modra <amodra@gmail.com>
260 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
261 when -Mraw is in effect.
263 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
265 * aarch64-dis-2.c: Regenerate.
266 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
267 (OP_SVE_BBB): New variant set.
268 (OP_SVE_DDDD): New variant set.
269 (OP_SVE_HHH): New variant set.
270 (OP_SVE_HHHU): New variant set.
271 (OP_SVE_SSS): New variant set.
272 (OP_SVE_SSSU): New variant set.
273 (OP_SVE_SHH): New variant set.
274 (OP_SVE_SBBU): New variant set.
275 (OP_SVE_DSS): New variant set.
276 (OP_SVE_DHHU): New variant set.
277 (OP_SVE_VMV_HSD_BHS): New variant set.
278 (OP_SVE_VVU_HSD_BHS): New variant set.
279 (OP_SVE_VVVU_SD_BH): New variant set.
280 (OP_SVE_VVVU_BHSD): New variant set.
281 (OP_SVE_VVV_QHD_DBS): New variant set.
282 (OP_SVE_VVV_HSD_BHS): New variant set.
283 (OP_SVE_VVV_HSD_BHS2): New variant set.
284 (OP_SVE_VVV_BHS_HSD): New variant set.
285 (OP_SVE_VV_BHS_HSD): New variant set.
286 (OP_SVE_VVV_SD): New variant set.
287 (OP_SVE_VVU_BHS_HSD): New variant set.
288 (OP_SVE_VZVV_SD): New variant set.
289 (OP_SVE_VZVV_BH): New variant set.
290 (OP_SVE_VZV_SD): New variant set.
291 (aarch64_opcode_table): Add sve2 instructions.
293 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
295 * aarch64-asm-2.c: Regenerated.
296 * aarch64-dis-2.c: Regenerated.
297 * aarch64-opc-2.c: Regenerated.
298 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
299 for SVE_SHLIMM_UNPRED_22.
300 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
301 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
304 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
306 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
307 sve_size_tsz_bhs iclass encode.
308 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
309 sve_size_tsz_bhs iclass decode.
311 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
313 * aarch64-asm-2.c: Regenerated.
314 * aarch64-dis-2.c: Regenerated.
315 * aarch64-opc-2.c: Regenerated.
316 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
317 for SVE_Zm4_11_INDEX.
318 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
319 (fields): Handle SVE_i2h field.
320 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
321 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
323 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
325 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
326 sve_shift_tsz_bhsd iclass encode.
327 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
328 sve_shift_tsz_bhsd iclass decode.
330 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
332 * aarch64-asm-2.c: Regenerated.
333 * aarch64-dis-2.c: Regenerated.
334 * aarch64-opc-2.c: Regenerated.
335 * aarch64-asm.c (aarch64_ins_sve_shrimm):
336 (aarch64_encode_variant_using_iclass): Handle
337 sve_shift_tsz_hsd iclass encode.
338 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
339 sve_shift_tsz_hsd iclass decode.
340 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
341 for SVE_SHRIMM_UNPRED_22.
342 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
343 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
346 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
348 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
349 sve_size_013 iclass encode.
350 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
351 sve_size_013 iclass decode.
353 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
355 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
356 sve_size_bh iclass encode.
357 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
358 sve_size_bh iclass decode.
360 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
362 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
363 sve_size_sd2 iclass encode.
364 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
365 sve_size_sd2 iclass decode.
366 * aarch64-opc.c (fields): Handle SVE_sz2 field.
367 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
369 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
371 * aarch64-asm-2.c: Regenerated.
372 * aarch64-dis-2.c: Regenerated.
373 * aarch64-opc-2.c: Regenerated.
374 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
376 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
377 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
379 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
381 * aarch64-asm-2.c: Regenerated.
382 * aarch64-dis-2.c: Regenerated.
383 * aarch64-opc-2.c: Regenerated.
384 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
385 for SVE_Zm3_11_INDEX.
386 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
387 (fields): Handle SVE_i3l and SVE_i3h2 fields.
388 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
390 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
392 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
394 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
395 sve_size_hsd2 iclass encode.
396 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
397 sve_size_hsd2 iclass decode.
398 * aarch64-opc.c (fields): Handle SVE_size field.
399 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
401 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
403 * aarch64-asm-2.c: Regenerated.
404 * aarch64-dis-2.c: Regenerated.
405 * aarch64-opc-2.c: Regenerated.
406 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
408 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
409 (fields): Handle SVE_rot3 field.
410 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
411 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
413 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
415 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
418 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
421 (aarch64_feature_sve2, aarch64_feature_sve2aes,
422 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
423 aarch64_feature_sve2bitperm): New feature sets.
424 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
425 for feature set addresses.
426 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
427 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
429 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
430 Faraz Shahbazker <fshahbazker@wavecomp.com>
432 * mips-dis.c (mips_calculate_combination_ases): Add ISA
433 argument and set ASE_EVA_R6 appropriately.
434 (set_default_mips_dis_options): Pass ISA to above.
435 (parse_mips_dis_option): Likewise.
436 * mips-opc.c (EVAR6): New macro.
437 (mips_builtin_opcodes): Add llwpe, scwpe.
439 2019-05-01 Sudakshina Das <sudi.das@arm.com>
441 * aarch64-asm-2.c: Regenerated.
442 * aarch64-dis-2.c: Regenerated.
443 * aarch64-opc-2.c: Regenerated.
444 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
445 AARCH64_OPND_TME_UIMM16.
446 (aarch64_print_operand): Likewise.
447 * aarch64-tbl.h (QL_IMM_NIL): New.
450 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
452 2019-04-29 John Darrington <john@darrington.wattle.id.au>
454 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
456 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
457 Faraz Shahbazker <fshahbazker@wavecomp.com>
459 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
461 2019-04-24 John Darrington <john@darrington.wattle.id.au>
463 * s12z-opc.h: Add extern "C" bracketing to help
464 users who wish to use this interface in c++ code.
466 2019-04-24 John Darrington <john@darrington.wattle.id.au>
468 * s12z-opc.c (bm_decode): Handle bit map operations with the
471 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
473 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
474 specifier. Add entries for VLDR and VSTR of system registers.
475 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
476 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
477 of %J and %K format specifier.
479 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
481 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
482 Add new entries for VSCCLRM instruction.
483 (print_insn_coprocessor): Handle new %C format control code.
485 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
487 * arm-dis.c (enum isa): New enum.
488 (struct sopcode32): New structure.
489 (coprocessor_opcodes): change type of entries to struct sopcode32 and
490 set isa field of all current entries to ANY.
491 (print_insn_coprocessor): Change type of insn to struct sopcode32.
492 Only match an entry if its isa field allows the current mode.
494 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
496 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
498 (print_insn_thumb32): Add logic to print %n CLRM register list.
500 2019-04-15 Sudakshina Das <sudi.das@arm.com>
502 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
505 2019-04-15 Sudakshina Das <sudi.das@arm.com>
507 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
508 (print_insn_thumb32): Edit the switch case for %Z.
510 2019-04-15 Sudakshina Das <sudi.das@arm.com>
512 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
514 2019-04-15 Sudakshina Das <sudi.das@arm.com>
516 * arm-dis.c (thumb32_opcodes): New instruction bfl.
518 2019-04-15 Sudakshina Das <sudi.das@arm.com>
520 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
522 2019-04-15 Sudakshina Das <sudi.das@arm.com>
524 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
525 Arm register with r13 and r15 unpredictable.
526 (thumb32_opcodes): New instructions for bfx and bflx.
528 2019-04-15 Sudakshina Das <sudi.das@arm.com>
530 * arm-dis.c (thumb32_opcodes): New instructions for bf.
532 2019-04-15 Sudakshina Das <sudi.das@arm.com>
534 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
536 2019-04-15 Sudakshina Das <sudi.das@arm.com>
538 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
540 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
542 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
544 2019-04-12 John Darrington <john@darrington.wattle.id.au>
546 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
547 "optr". ("operator" is a reserved word in c++).
549 2019-04-11 Sudakshina Das <sudi.das@arm.com>
551 * aarch64-opc.c (aarch64_print_operand): Add case for
553 (verify_constraints): Likewise.
554 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
555 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
556 to accept Rt|SP as first operand.
557 (AARCH64_OPERANDS): Add new Rt_SP.
558 * aarch64-asm-2.c: Regenerated.
559 * aarch64-dis-2.c: Regenerated.
560 * aarch64-opc-2.c: Regenerated.
562 2019-04-11 Sudakshina Das <sudi.das@arm.com>
564 * aarch64-asm-2.c: Regenerated.
565 * aarch64-dis-2.c: Likewise.
566 * aarch64-opc-2.c: Likewise.
567 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
569 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
571 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
573 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
575 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
576 * i386-init.h: Regenerated.
578 2019-04-07 Alan Modra <amodra@gmail.com>
580 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
581 op_separator to control printing of spaces, comma and parens
582 rather than need_comma, need_paren and spaces vars.
584 2019-04-07 Alan Modra <amodra@gmail.com>
587 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
588 (print_insn_neon, print_insn_arm): Likewise.
590 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
592 * i386-dis-evex.h (evex_table): Updated to support BF16
594 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
595 and EVEX_W_0F3872_P_3.
596 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
597 (cpu_flags): Add bitfield for CpuAVX512_BF16.
598 * i386-opc.h (enum): Add CpuAVX512_BF16.
599 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
600 * i386-opc.tbl: Add AVX512 BF16 instructions.
601 * i386-init.h: Regenerated.
602 * i386-tbl.h: Likewise.
604 2019-04-05 Alan Modra <amodra@gmail.com>
606 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
607 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
608 to favour printing of "-" branch hint when using the "y" bit.
609 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
611 2019-04-05 Alan Modra <amodra@gmail.com>
613 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
614 opcode until first operand is output.
616 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
619 * ppc-opc.c (valid_bo_pre_v2): Add comments.
620 (valid_bo_post_v2): Add support for 'at' branch hints.
621 (insert_bo): Only error on branch on ctr.
622 (get_bo_hint_mask): New function.
623 (insert_boe): Add new 'branch_taken' formal argument. Add support
624 for inserting 'at' branch hints.
625 (extract_boe): Add new 'branch_taken' formal argument. Add support
626 for extracting 'at' branch hints.
627 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
628 (BOE): Delete operand.
629 (BOM, BOP): New operands.
631 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
632 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
633 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
634 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
635 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
636 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
637 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
638 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
639 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
640 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
641 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
642 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
643 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
644 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
645 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
646 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
647 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
648 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
649 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
650 bttarl+>: New extended mnemonics.
652 2019-03-28 Alan Modra <amodra@gmail.com>
655 * ppc-opc.c (BTF): Define.
656 (powerpc_opcodes): Use for mtfsb*.
657 * ppc-dis.c (print_insn_powerpc): Print fields with both
658 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
660 2019-03-25 Tamar Christina <tamar.christina@arm.com>
662 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
663 (mapping_symbol_for_insn): Implement new algorithm.
664 (print_insn): Remove duplicate code.
666 2019-03-25 Tamar Christina <tamar.christina@arm.com>
668 * aarch64-dis.c (print_insn_aarch64):
671 2019-03-25 Tamar Christina <tamar.christina@arm.com>
673 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
676 2019-03-25 Tamar Christina <tamar.christina@arm.com>
678 * aarch64-dis.c (last_stop_offset): New.
679 (print_insn_aarch64): Use stop_offset.
681 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
684 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
686 * i386-init.h: Regenerated.
688 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
691 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
692 vmovdqu16, vmovdqu32 and vmovdqu64.
693 * i386-tbl.h: Regenerated.
695 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
697 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
698 from vstrszb, vstrszh, and vstrszf.
700 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
702 * s390-opc.txt: Add instruction descriptions.
704 2019-02-08 Jim Wilson <jimw@sifive.com>
706 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
709 2019-02-07 Tamar Christina <tamar.christina@arm.com>
711 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
713 2019-02-07 Tamar Christina <tamar.christina@arm.com>
716 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
717 * aarch64-opc.c (verify_elem_sd): New.
718 (fields): Add FLD_sz entr.
719 * aarch64-tbl.h (_SIMD_INSN): New.
720 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
721 fmulx scalar and vector by element isns.
723 2019-02-07 Nick Clifton <nickc@redhat.com>
725 * po/sv.po: Updated Swedish translation.
727 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
729 * s390-mkopc.c (main): Accept arch13 as cpu string.
730 * s390-opc.c: Add new instruction formats and instruction opcode
732 * s390-opc.txt: Add new arch13 instructions.
734 2019-01-25 Sudakshina Das <sudi.das@arm.com>
736 * aarch64-tbl.h (QL_LDST_AT): Update macro.
737 (aarch64_opcode): Change encoding for stg, stzg
739 * aarch64-asm-2.c: Regenerated.
740 * aarch64-dis-2.c: Regenerated.
741 * aarch64-opc-2.c: Regenerated.
743 2019-01-25 Sudakshina Das <sudi.das@arm.com>
745 * aarch64-asm-2.c: Regenerated.
746 * aarch64-dis-2.c: Likewise.
747 * aarch64-opc-2.c: Likewise.
748 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
750 2019-01-25 Sudakshina Das <sudi.das@arm.com>
751 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
753 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
754 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
755 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
756 * aarch64-dis.h (ext_addr_simple_2): Likewise.
757 * aarch64-opc.c (operand_general_constraint_met_p): Remove
758 case for ldstgv_indexed.
759 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
760 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
761 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
762 * aarch64-asm-2.c: Regenerated.
763 * aarch64-dis-2.c: Regenerated.
764 * aarch64-opc-2.c: Regenerated.
766 2019-01-23 Nick Clifton <nickc@redhat.com>
768 * po/pt_BR.po: Updated Brazilian Portuguese translation.
770 2019-01-21 Nick Clifton <nickc@redhat.com>
772 * po/de.po: Updated German translation.
773 * po/uk.po: Updated Ukranian translation.
775 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
776 * mips-dis.c (mips_arch_choices): Fix typo in
777 gs464, gs464e and gs264e descriptors.
779 2019-01-19 Nick Clifton <nickc@redhat.com>
781 * configure: Regenerate.
782 * po/opcodes.pot: Regenerate.
784 2018-06-24 Nick Clifton <nickc@redhat.com>
788 2019-01-09 John Darrington <john@darrington.wattle.id.au>
790 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
792 -dis.c (opr_emit_disassembly): Do not omit an index if it is
795 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
797 * configure: Regenerate.
799 2019-01-07 Alan Modra <amodra@gmail.com>
801 * configure: Regenerate.
802 * po/POTFILES.in: Regenerate.
804 2019-01-03 John Darrington <john@darrington.wattle.id.au>
806 * s12z-opc.c: New file.
807 * s12z-opc.h: New file.
808 * s12z-dis.c: Removed all code not directly related to display
809 of instructions. Used the interface provided by the new files
811 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
812 * Makefile.in: Regenerate.
813 * configure.ac (bfd_s12z_arch): Correct the dependencies.
814 * configure: Regenerate.
816 2019-01-01 Alan Modra <amodra@gmail.com>
818 Update year range in copyright notice of all files.
820 For older changes see ChangeLog-2018
822 Copyright (C) 2019 Free Software Foundation, Inc.
824 Copying and distribution of this file, with or without modification,
825 are permitted in any medium without royalty provided the copyright
826 notice and this notice are preserved.
832 version-control: never