Updated translations for various binutils components.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
1 2015-04-29 Nick Clifton <nickc@redhat.com>
2
3 * po/fr.po: Updated French translation.
4
5 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
6
7 * ppc-opc.c (DCBT_EO): New define.
8 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
9 <lharx>: Likewise.
10 <stbcx.>: Likewise.
11 <sthcx.>: Likewise.
12 <waitrsv>: Do not enable for POWER7 and later.
13 <waitimpl>: Likewise.
14 <dcbt>: Default to the two operand form of the instruction for all
15 "old" cpus. For "new" cpus, use the operand ordering that matches
16 whether the cpu is server or embedded.
17 <dcbtst>: Likewise.
18
19 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
20
21 * s390-opc.c: New instruction type VV0UU2.
22 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
23 and WFC.
24
25 2015-04-23 Jan Beulich <jbeulich@suse.com>
26
27 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
28 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
29 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
30 (vfpclasspd, vfpclassps): Add %XZ.
31
32 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
33
34 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
35 (PREFIX_UD_REPZ): Likewise.
36 (PREFIX_UD_REPNZ): Likewise.
37 (PREFIX_UD_DATA): Likewise.
38 (PREFIX_UD_ADDR): Likewise.
39 (PREFIX_UD_LOCK): Likewise.
40
41 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
42
43 * i386-dis.c (prefix_requirement): Removed.
44 (print_insn): Don't set prefix_requirement. Check
45 dp->prefix_requirement instead of prefix_requirement.
46
47 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
48
49 PR binutils/17898
50 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
51 (PREFIX_MOD_0_0FC7_REG_6): This.
52 (PREFIX_MOD_3_0FC7_REG_6): New.
53 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
54 (prefix_table): Replace PREFIX_0FC7_REG_6 with
55 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
56 PREFIX_MOD_3_0FC7_REG_7.
57 (mod_table): Replace PREFIX_0FC7_REG_6 with
58 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
59 PREFIX_MOD_3_0FC7_REG_7.
60
61 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
62
63 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
64 (PREFIX_MANDATORY_REPNZ): Likewise.
65 (PREFIX_MANDATORY_DATA): Likewise.
66 (PREFIX_MANDATORY_ADDR): Likewise.
67 (PREFIX_MANDATORY_LOCK): Likewise.
68 (PREFIX_MANDATORY): Likewise.
69 (PREFIX_UD_SHIFT): Set to 8
70 (PREFIX_UD_REPZ): Updated.
71 (PREFIX_UD_REPNZ): Likewise.
72 (PREFIX_UD_DATA): Likewise.
73 (PREFIX_UD_ADDR): Likewise.
74 (PREFIX_UD_LOCK): Likewise.
75 (PREFIX_IGNORED_SHIFT): New.
76 (PREFIX_IGNORED_REPZ): Likewise.
77 (PREFIX_IGNORED_REPNZ): Likewise.
78 (PREFIX_IGNORED_DATA): Likewise.
79 (PREFIX_IGNORED_ADDR): Likewise.
80 (PREFIX_IGNORED_LOCK): Likewise.
81 (PREFIX_OPCODE): Likewise.
82 (PREFIX_IGNORED): Likewise.
83 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
84 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
85 (three_byte_table): Likewise.
86 (mod_table): Likewise.
87 (mandatory_prefix): Renamed to ...
88 (prefix_requirement): This.
89 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
90 Update PREFIX_90 entry.
91 (get_valid_dis386): Check prefix_requirement to see if a prefix
92 should be ignored.
93 (print_insn): Replace mandatory_prefix with prefix_requirement.
94
95 2015-04-15 Renlin Li <renlin.li@arm.com>
96
97 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
98 use it for ssat and ssat16.
99 (print_insn_thumb32): Add handle case for 'D' control code.
100
101 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
102 H.J. Lu <hongjiu.lu@intel.com>
103
104 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
105 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
106 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
107 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
108 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
109 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
110 Fill prefix_requirement field.
111 (struct dis386): Add prefix_requirement field.
112 (dis386): Fill prefix_requirement field.
113 (dis386_twobyte): Ditto.
114 (twobyte_has_mandatory_prefix_: Remove.
115 (reg_table): Fill prefix_requirement field.
116 (prefix_table): Ditto.
117 (x86_64_table): Ditto.
118 (three_byte_table): Ditto.
119 (xop_table): Ditto.
120 (vex_table): Ditto.
121 (vex_len_table): Ditto.
122 (vex_w_table): Ditto.
123 (mod_table): Ditto.
124 (bad_opcode): Ditto.
125 (print_insn): Use prefix_requirement.
126 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
127 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
128 (float_reg): Ditto.
129
130 2015-03-30 Mike Frysinger <vapier@gentoo.org>
131
132 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
133
134 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
135
136 * Makefile.in: Regenerated.
137
138 2015-03-25 Anton Blanchard <anton@samba.org>
139
140 * ppc-dis.c (disassemble_init_powerpc): Only initialise
141 powerpc_opcd_indices and vle_opcd_indices once.
142
143 2015-03-25 Anton Blanchard <anton@samba.org>
144
145 * ppc-opc.c (powerpc_opcodes): Add slbfee.
146
147 2015-03-24 Terry Guo <terry.guo@arm.com>
148
149 * arm-dis.c (opcode32): Updated to use new arm feature struct.
150 (opcode16): Likewise.
151 (coprocessor_opcodes): Replace bit with feature struct.
152 (neon_opcodes): Likewise.
153 (arm_opcodes): Likewise.
154 (thumb_opcodes): Likewise.
155 (thumb32_opcodes): Likewise.
156 (print_insn_coprocessor): Likewise.
157 (print_insn_arm): Likewise.
158 (select_arm_features): Follow new feature struct.
159
160 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
161
162 * i386-dis.c (rm_table): Add clzero.
163 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
164 Add CPU_CLZERO_FLAGS.
165 (cpu_flags): Add CpuCLZERO.
166 * i386-opc.h: Add CpuCLZERO.
167 * i386-opc.tbl: Add clzero.
168 * i386-init.h: Re-generated.
169 * i386-tbl.h: Re-generated.
170
171 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
172
173 * mips-opc.c (decode_mips_operand): Fix constraint issues
174 with u and y operands.
175
176 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
177
178 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
179
180 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
181
182 * s390-opc.c: Add new IBM z13 instructions.
183 * s390-opc.txt: Likewise.
184
185 2015-03-10 Renlin Li <renlin.li@arm.com>
186
187 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
188 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
189 related alias.
190 * aarch64-asm-2.c: Regenerate.
191 * aarch64-dis-2.c: Likewise.
192 * aarch64-opc-2.c: Likewise.
193
194 2015-03-03 Jiong Wang <jiong.wang@arm.com>
195
196 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
197
198 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
199
200 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
201 arch_sh_up.
202 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
203 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
204
205 2015-02-23 Vinay <Vinay.G@kpit.com>
206
207 * rl78-decode.opc (MOV): Added space between two operands for
208 'mov' instruction in index addressing mode.
209 * rl78-decode.c: Regenerate.
210
211 2015-02-19 Pedro Alves <palves@redhat.com>
212
213 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
214
215 2015-02-10 Pedro Alves <palves@redhat.com>
216 Tom Tromey <tromey@redhat.com>
217
218 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
219 microblaze_and, microblaze_xor.
220 * microblaze-opc.h (opcodes): Adjust.
221
222 2015-01-28 James Bowman <james.bowman@ftdichip.com>
223
224 * Makefile.am: Add FT32 files.
225 * configure.ac: Handle FT32.
226 * disassemble.c (disassembler): Call print_insn_ft32.
227 * ft32-dis.c: New file.
228 * ft32-opc.c: New file.
229 * Makefile.in: Regenerate.
230 * configure: Regenerate.
231 * po/POTFILES.in: Regenerate.
232
233 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
234
235 * nds32-asm.c (keyword_sr): Add new system registers.
236
237 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
238
239 * s390-dis.c (s390_extract_operand): Support vector register
240 operands.
241 (s390_print_insn_with_opcode): Support new operands types and add
242 new handling of optional operands.
243 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
244 and include opcode/s390.h instead.
245 (struct op_struct): New field `flags'.
246 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
247 (dumpTable): Dump flags.
248 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
249 string.
250 * s390-opc.c: Add new operands types, instruction formats, and
251 instruction masks.
252 (s390_opformats): Add new formats for .insn.
253 * s390-opc.txt: Add new instructions.
254
255 2015-01-01 Alan Modra <amodra@gmail.com>
256
257 Update year range in copyright notice of all files.
258
259 For older changes see ChangeLog-2014
260 \f
261 Copyright (C) 2015 Free Software Foundation, Inc.
262
263 Copying and distribution of this file, with or without modification,
264 are permitted in any medium without royalty provided the copyright
265 notice and this notice are preserved.
266
267 Local Variables:
268 mode: change-log
269 left-margin: 8
270 fill-column: 74
271 version-control: never
272 End:
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