1 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
3 * s390-opc.c (J12_12, J24_24): New macros.
4 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
5 (MASK_MII_UPI): Rename to MASK_MII_UPP.
6 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
8 2013-07-04 Alan Modra <amodra@gmail.com>
10 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
12 2013-06-26 Nick Clifton <nickc@redhat.com>
14 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
15 field when checking for type 2 nop.
16 * rx-decode.c: Regenerate.
18 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
20 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
23 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
25 * mips-dis.c (is_mips16_plt_tail): New function.
26 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
28 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
30 2013-06-21 DJ Delorie <dj@redhat.com>
32 * msp430-decode.opc: New.
33 * msp430-decode.c: New/generated.
34 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
35 (MAINTAINER_CLEANFILES): Likewise.
36 Add rule to build msp430-decode.c frommsp430decode.opc
37 using the opc2c program.
38 * Makefile.in: Regenerate.
39 * configure.in: Add msp430-decode.lo to msp430 architecture files.
40 * configure: Regenerate.
42 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
44 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
45 (SYMTAB_AVAILABLE): Removed.
46 (#include "elf/aarch64.h): Ditto.
48 2013-06-17 Catherine Moore <clm@codesourcery.com>
49 Maciej W. Rozycki <macro@codesourcery.com>
50 Chao-Ying Fu <fu@mips.com>
52 * micromips-opc.c (EVA): Define.
54 (micromips_opcodes): Add EVA opcodes.
55 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
56 (print_insn_args): Handle EVA offsets.
57 (print_insn_micromips): Likewise.
58 * mips-opc.c (EVA): Define.
60 (mips_builtin_opcodes): Add EVA opcodes.
62 2013-06-17 Alan Modra <amodra@gmail.com>
64 * Makefile.am (mips-opc.lo): Add rules to create automatic
65 dependency files. Pass archdefs.
66 (micromips-opc.lo, mips16-opc.lo): Likewise.
67 * Makefile.in: Regenerate.
69 2013-06-14 DJ Delorie <dj@redhat.com>
71 * rx-decode.opc (rx_decode_opcode): Bit operations on
72 registers are 32-bit operations, not 8-bit operations.
73 * rx-decode.c: Regenerate.
75 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
77 * micromips-opc.c (IVIRT): New define.
78 (IVIRT64): New define.
79 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
80 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
82 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
83 dmtgc0 to print cp0 names.
85 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
87 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
90 2013-06-08 Catherine Moore <clm@codesourcery.com>
91 Richard Sandiford <rdsandiford@googlemail.com>
93 * micromips-opc.c (D32, D33, MC): Update definitions.
94 (micromips_opcodes): Initialize ase field.
95 * mips-dis.c (mips_arch_choice): Add ase field.
96 (mips_arch_choices): Initialize ase field.
97 (set_default_mips_dis_options): Declare and setup mips_ase.
98 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
99 MT32, MC): Update definitions.
100 (mips_builtin_opcodes): Initialize ase field.
102 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
104 * s390-opc.txt (flogr): Require a register pair destination.
106 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
108 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
111 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
113 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
115 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
117 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
118 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
119 XLS_MASK, PPCVSX2): New defines.
120 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
121 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
122 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
123 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
124 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
125 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
126 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
127 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
128 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
129 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
130 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
131 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
132 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
133 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
134 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
135 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
136 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
137 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
138 <lxvx, stxvx>: New extended mnemonics.
140 2013-05-17 Alan Modra <amodra@gmail.com>
142 * ia64-raw.tbl: Replace non-ASCII char.
143 * ia64-waw.tbl: Likewise.
144 * ia64-asmtab.c: Regenerate.
146 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
148 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
149 * i386-init.h: Regenerated.
151 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
153 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
154 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
155 check from [0, 255] to [-128, 255].
157 2013-05-09 Andrew Pinski <apinski@cavium.com>
159 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
160 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
161 (parse_mips_dis_option): Handle the virt option.
162 (print_insn_args): Handle "+J".
163 (print_mips_disassembler_options): Print out message about virt64.
164 * mips-opc.c (IVIRT): New define.
165 (IVIRT64): New define.
166 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
167 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
168 Move rfe to the bottom as it conflicts with tlbgp.
170 2013-05-09 Alan Modra <amodra@gmail.com>
172 * ppc-opc.c (extract_vlesi): Properly sign extend.
173 (extract_vlensi): Likewise. Comment reason for setting invalid.
175 2013-05-02 Nick Clifton <nickc@redhat.com>
177 * msp430-dis.c: Add support for MSP430X instructions.
179 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
181 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
184 2013-04-17 Wei-chen Wang <cole945@gmail.com>
187 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
189 (hash_insns_list): Likewise.
191 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
193 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
196 2013-04-08 Jan Beulich <jbeulich@suse.com>
198 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
199 * i386-tbl.h: Re-generate.
201 2013-04-06 David S. Miller <davem@davemloft.net>
203 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
204 of an opcode, prefer the one with F_PREFERRED set.
205 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
206 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
207 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
208 mark existing mnenomics as aliases. Add "cc" suffix to edge
209 instructions generating condition codes, mark existing mnenomics
210 as aliases. Add "fp" prefix to VIS compare instructions, mark
211 existing mnenomics as aliases.
213 2013-04-03 Nick Clifton <nickc@redhat.com>
215 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
216 destination address by subtracting the operand from the current
218 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
219 a positive value in the insn.
220 (extract_u16_loop): Do not negate the returned value.
221 (D16_LOOP): Add V850_INVERSE_PCREL flag.
223 (ceilf.sw): Remove duplicate entry.
224 (cvtf.hs): New entry.
230 (maddf.s): Restrict to E3V5 architectures.
232 (nmaddf.s): Likewise.
233 (nmsubf.s): Likewise.
235 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
237 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
239 (print_insn): Pass sizeflag to get_sib.
241 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
244 * tic6x-dis.c: Add support for displaying 16-bit insns.
246 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
249 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
250 individual msb and lsb halves in src1 & src2 fields. Discard the
251 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
252 follow what Ti SDK does in that case as any value in the src1
253 field yields the same output with SDK disassembler.
255 2013-03-12 Michael Eager <eager@eagercon.com>
257 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
259 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
261 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
263 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
265 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
267 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
269 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
271 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
273 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
274 (thumb32_opcodes): Likewise.
275 (print_insn_thumb32): Handle 'S' control char.
277 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
279 * lm32-desc.c: Regenerate.
281 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
283 * i386-reg.tbl (riz): Add RegRex64.
284 * i386-tbl.h: Regenerated.
286 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
288 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
289 (aarch64_feature_crc): New static.
291 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
292 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
293 * aarch64-asm-2.c: Re-generate.
294 * aarch64-dis-2.c: Ditto.
295 * aarch64-opc-2.c: Ditto.
297 2013-02-27 Alan Modra <amodra@gmail.com>
299 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
300 * rl78-decode.c: Regenerate.
302 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
304 * rl78-decode.opc: Fix encoding of DIVWU insn.
305 * rl78-decode.c: Regenerate.
307 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
310 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
312 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
313 (cpu_flags): Add CpuSMAP.
315 * i386-opc.h (CpuSMAP): New.
316 (i386_cpu_flags): Add cpusmap.
318 * i386-opc.tbl: Add clac and stac.
320 * i386-init.h: Regenerated.
321 * i386-tbl.h: Likewise.
323 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
325 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
326 which also makes the disassembler output be in little
327 endian like it should be.
329 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
331 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
333 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
335 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
337 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
338 section disassembled.
340 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
342 * arm-dis.c: Update strht pattern.
344 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
346 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
347 single-float. Disable ll, lld, sc and scd for EE. Disable the
348 trunc.w.s macro for EE.
350 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
351 Andrew Jenner <andrew@codesourcery.com>
353 Based on patches from Altera Corporation.
355 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
357 * Makefile.in: Regenerated.
358 * configure.in: Add case for bfd_nios2_arch.
359 * configure: Regenerated.
360 * disassemble.c (ARCH_nios2): Define.
361 (disassembler): Add case for bfd_arch_nios2.
362 * nios2-dis.c: New file.
363 * nios2-opc.c: New file.
365 2013-02-04 Alan Modra <amodra@gmail.com>
367 * po/POTFILES.in: Regenerate.
368 * rl78-decode.c: Regenerate.
369 * rx-decode.c: Regenerate.
371 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
373 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
374 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
375 * aarch64-asm.c (convert_xtl_to_shll): New function.
376 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
377 calling convert_xtl_to_shll.
378 * aarch64-dis.c (convert_shll_to_xtl): New function.
379 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
380 calling convert_shll_to_xtl.
381 * aarch64-gen.c: Update copyright year.
382 * aarch64-asm-2.c: Re-generate.
383 * aarch64-dis-2.c: Re-generate.
384 * aarch64-opc-2.c: Re-generate.
386 2013-01-24 Nick Clifton <nickc@redhat.com>
388 * v850-dis.c: Add support for e3v5 architecture.
389 * v850-opc.c: Likewise.
391 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
393 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
394 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
395 * aarch64-opc.c (operand_general_constraint_met_p): For
396 AARCH64_MOD_LSL, move the range check on the shift amount before the
397 alignment check; change to call set_sft_amount_out_of_range_error
398 instead of set_imm_out_of_range_error.
399 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
400 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
401 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
404 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
406 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
408 * i386-init.h: Regenerated.
409 * i386-tbl.h: Likewise.
411 2013-01-15 Nick Clifton <nickc@redhat.com>
413 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
415 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
417 2013-01-14 Will Newton <will.newton@imgtec.com>
419 * metag-dis.c (REG_WIDTH): Increase to 64.
421 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
423 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
424 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
425 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
427 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
428 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
429 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
430 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
432 2013-01-10 Will Newton <will.newton@imgtec.com>
434 * Makefile.am: Add Meta.
435 * configure.in: Add Meta.
436 * disassemble.c: Add Meta support.
437 * metag-dis.c: New file.
438 * Makefile.in: Regenerate.
439 * configure: Regenerate.
441 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
443 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
444 (match_opcode): Rename to cr16_match_opcode.
446 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
448 * mips-dis.c: Add names for CP0 registers of r5900.
449 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
450 instructions sq and lq.
451 Add support for MIPS r5900 CPU.
452 Add support for 128 bit MMI (Multimedia Instructions).
453 Add support for EE instructions (Emotion Engine).
454 Disable unsupported floating point instructions (64 bit and
455 undefined compare operations).
456 Enable instructions of MIPS ISA IV which are supported by r5900.
457 Disable 64 bit co processor instructions.
458 Disable 64 bit multiplication and division instructions.
459 Disable instructions for co-processor 2 and 3, because these are
460 not supported (preparation for later VU0 support (Vector Unit)).
461 Disable cvt.w.s because this behaves like trunc.w.s and the
462 correct execution can't be ensured on r5900.
463 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
464 will confuse less developers and compilers.
466 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
468 * aarch64-opc.c (aarch64_print_operand): Change to print
469 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
471 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
472 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
475 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
477 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
478 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
480 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
482 * i386-gen.c (process_copyright): Update copyright year to 2013.
484 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
486 * cr16-dis.c (match_opcode,make_instruction): Remove static
488 (dwordU,wordU): Moved typedefs to opcode/cr16.h
489 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
491 For older changes see ChangeLog-2012
493 Copyright (C) 2013 Free Software Foundation, Inc.
495 Copying and distribution of this file, with or without modification,
496 are permitted in any medium without royalty provided the copyright
497 notice and this notice are preserved.
503 version-control: never