opcodes/ChangeLog

   1 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
   2
   3         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
   4         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
   5         xor3>: Delete mnemonics.
   6         <cp_abort>: Rename mnemonic from ...
   7         <cpabort>: ...to this.
   8         <setb>: Change to a X form instruction.
   9         <sync>: Change to 1 operand form.
  10         <copy>: Delete mnemonic.
  11         <copy_first>: Rename mnemonic from ...
  12         <copy>: ...to this.
  13         <paste, paste.>: Delete mnemonics.
  14         <paste_last>: Rename mnemonic from ...
  15         <paste.>: ...to this.
  16
  17 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  18
  19         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
  20
  21 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
  22
  23         * s390-mkopc.c (main): Support alternate arch strings.
  24
  25 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
  26
  27         * s390-opc.txt: Fix kmctr instruction type.
  28
  29 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
  30
  31         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
  32         * i386-init.h: Regenerated.
  33
  34 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
  35
  36         * opcodes/arc-dis.c (print_insn_arc): Changed.
  37
  38 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
  39
  40         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
  41         camellia_fl.
  42
  43 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  44
  45         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
  46         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
  47         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
  48
  49 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
  50
  51         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
  52         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
  53         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
  54         PREFIX_MOD_3_0FAE_REG_4.
  55         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
  56         PREFIX_MOD_3_0FAE_REG_4.
  57         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
  58         (cpu_flags): Add CpuPTWRITE.
  59         * i386-opc.h (CpuPTWRITE): New.
  60         (i386_cpu_flags): Add cpuptwrite.
  61         * i386-opc.tbl: Add ptwrite instruction.
  62         * i386-init.h: Regenerated.
  63         * i386-tbl.h: Likewise.
  64
  65 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  66
  67         * arc-dis.h: Wrap around in extern "C".
  68
  69 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  70
  71         * aarch64-tbl.h (V8_2_INSN): New macro.
  72         (aarch64_opcode_table): Use it.
  73
  74 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  75
  76         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
  77         CORE_INSN, __FP_INSN and SIMD_INSN.
  78
  79 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  80
  81         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
  82         (aarch64_opcode_table): Update uses accordingly.
  83
  84 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
  85         Kwok Cheung Yeung  <kcy@codesourcery.com>
  86
  87         opcodes/
  88         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
  89         'e_cmplwi' to 'e_cmpli' instead.
  90         (OPVUPRT, OPVUPRT_MASK): Define.
  91         (powerpc_opcodes): Add E200Z4 insns.
  92         (vle_opcodes): Add context save/restore insns.
  93
  94 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
  95
  96         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
  97         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
  98         "j".
  99
 100 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 101
 102         * arc-nps400-tbl.h: Change block comments to GNU format.
 103         * arc-dis.c: Add new globals addrtypenames,
 104         addrtypenames_max, and addtypeunknown.
 105         (get_addrtype): New function.
 106         (print_insn_arc): Print colons and address types when
 107         required.
 108         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 109         define insert and extract functions for all address types.
 110         (arc_operands): Add operands for colon and all address
 111         types.
 112         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 113         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 114         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 115         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 116         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 117         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 118
 119 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 120
 121         * configure: Regenerated.
 122
 123 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 124
 125         * arc-dis.c (skipclass): New structure.
 126         (decodelist): New variable.
 127         (is_compatible_p): New function.
 128         (new_element): Likewise.
 129         (skip_class_p): Likewise.
 130         (find_format_from_table): Use skip_class_p function.
 131         (find_format): Decode first the extension instructions.
 132         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 133         e_flags.
 134         (parse_option): New function.
 135         (parse_disassembler_options): Likewise.
 136         (print_arc_disassembler_options): Likewise.
 137         (print_insn_arc): Use parse_disassembler_options function.  Proper
 138         select ARCv2 cpu variant.
 139         * disassemble.c (disassembler_usage): Add ARC disassembler
 140         options.
 141
 142 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 143
 144         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 145         annotation from the "nal" entry and reorder it beyond "bltzal".
 146
 147 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 148
 149         * sparc-opc.c (ldtxa): New macro.
 150         (sparc_opcodes): Use the macro defined above to add entries for
 151         the LDTXA instructions.
 152         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 153         instruction.
 154
 155 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 156
 157         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 158         and "jmpc".
 159
 160 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 161
 162         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 163         (movzb): Adjust to cover all permitted suffixes.
 164         (movzw): New.
 165         * i386-tbl.h: Re-generate.
 166
 167 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 168
 169         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 170         (lgdt): Remove Tbyte from non-64-bit variant.
 171         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 172         xsaves64, xsavec64): Remove Disp16.
 173         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 174         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 175         64-bit variants.
 176         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 177         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 178         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 179         64-bit variants.
 180         * i386-tbl.h: Re-generate.
 181
 182 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 183
 184         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 185         * i386-tbl.h: Re-generate.
 186
 187 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 188
 189         * arm-dis.c (print_insn): Fix typo in comment.
 190
 191 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 192
 193         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 194         range of ldst_elemlist operands.
 195         (print_register_list): Use PRIi64 to print the index.
 196         (aarch64_print_operand): Likewise.
 197
 198 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 199
 200         * mcore-opc.h: Remove sentinal.
 201         * mcore-dis.c (print_insn_mcore): Adjust.
 202
 203 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 204
 205         * arc-opc.c: Correct description of availability of NPS400
 206         features.
 207
 208 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 209
 210         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 211         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 212         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 213         xor3>: New mnemonics.
 214         <setb>: Change to a VX form instruction.
 215         (insert_sh6): Add support for rldixor.
 216         (extract_sh6): Likewise.
 217
 218 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 219
 220         * arc-ext.h: Wrap in extern C.
 221
 222 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 223
 224         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 225         Use same method for determining instruction length on ARC700 and
 226         NPS-400.
 227         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 228         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 229         with the NPS400 subclass.
 230         * arc-opc.c: Likewise.
 231
 232 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 233
 234         * sparc-opc.c (rdasr): New macro.
 235         (wrasr): Likewise.
 236         (rdpr): Likewise.
 237         (wrpr): Likewise.
 238         (rdhpr): Likewise.
 239         (wrhpr): Likewise.
 240         (sparc_opcodes): Use the macros above to fix and expand the
 241         definition of read/write instructions from/to
 242         asr/privileged/hyperprivileged instructions.
 243         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 244         %hva_mask_nz.  Prefer softint_set and softint_clear over
 245         set_softint and clear_softint.
 246         (print_insn_sparc): Support %ver in Rd.
 247
 248 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 249
 250         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 251         architecture according to the hardware capabilities they require.
 252
 253 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 254
 255         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 256         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 257         bfd_mach_sparc_v9{c,d,e,v,m}.
 258         * sparc-opc.c (MASK_V9C): Define.
 259         (MASK_V9D): Likewise.
 260         (MASK_V9E): Likewise.
 261         (MASK_V9V): Likewise.
 262         (MASK_V9M): Likewise.
 263         (v6): Add MASK_V9{C,D,E,V,M}.
 264         (v6notlet): Likewise.
 265         (v7): Likewise.
 266         (v8): Likewise.
 267         (v9): Likewise.
 268         (v9andleon): Likewise.
 269         (v9a): Likewise.
 270         (v9b): Likewise.
 271         (v9c): Define.
 272         (v9d): Likewise.
 273         (v9e): Likewise.
 274         (v9v): Likewise.
 275         (v9m): Likewise.
 276         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 277
 278 2016-06-15  Nick Clifton  <nickc@redhat.com>
 279
 280         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 281         constants to match expected behaviour.
 282         (nds32_parse_opcode): Likewise.  Also for whitespace.
 283
 284 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 285
 286         * arc-opc.c (extract_rhv1): Extract value from insn.
 287
 288 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 289
 290         * arc-nps400-tbl.h: Add ldbit instruction.
 291         * arc-opc.c: Add flag classes required for ldbit.
 292
 293 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 294
 295         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 296         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 297         support the above instructions.
 298
 299 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 300
 301         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 302         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 303         csma, cbba, zncv, and hofs.
 304         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 305         support the above instructions.
 306
 307 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 308
 309         * arc-nps400-tbl.h: Add andab and orab instructions.
 310
 311 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 312
 313         * arc-nps400-tbl.h: Add addl-like instructions.
 314
 315 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 316
 317         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 318
 319 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 320
 321         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 322         instructions.
 323
 324 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 325
 326         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 327         variable.
 328         (init_disasm): Handle new command line option "insnlength".
 329         (print_s390_disassembler_options): Mention new option in help
 330         output.
 331         (print_insn_s390): Use the encoded insn length when dumping
 332         unknown instructions.
 333
 334 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 335
 336         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 337          to the address and set as symbol address for LDS/ STS immediate operands.
 338
 339 2016-06-07  Alan Modra  <amodra@gmail.com>
 340
 341         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 342         cpu for "vle" to e500.
 343         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 344         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 345         (PPCNONE): Delete, substitute throughout.
 346         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 347         except for major opcode 4 and 31.
 348         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 349
 350 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 351
 352         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 353         ARM_EXT_RAS in relevant entries.
 354
 355 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 356
 357         PR binutils/20196
 358         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 359         opcodes for E6500.
 360
 361 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 362
 363         PR binutis/18386
 364         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 365         (indir_v_mode): New.
 366         Add comments for '&'.
 367         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 368         (putop): Handle '&'.
 369         (intel_operand_size): Handle indir_v_mode.
 370         (OP_E_register): Likewise.
 371         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 372         64-bit indirect call/jmp for AMD64.
 373         * i386-tbl.h: Regenerated
 374
 375 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 376
 377         * arc-dis.c (struct arc_operand_iterator): New structure.
 378         (find_format_from_table): All the old content from find_format,
 379         with some minor adjustments, and parameter renaming.
 380         (find_format_long_instructions): New function.
 381         (find_format): Rewritten.
 382         (arc_insn_length): Add LSB parameter.
 383         (extract_operand_value): New function.
 384         (operand_iterator_next): New function.
 385         (print_insn_arc): Use new functions to find opcode, and iterator
 386         over operands.
 387         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 388         (extract_nps_3bit_dst_short): New function.
 389         (insert_nps_3bit_src2_short): New function.
 390         (extract_nps_3bit_src2_short): New function.
 391         (insert_nps_bitop1_size): New function.
 392         (extract_nps_bitop1_size): New function.
 393         (insert_nps_bitop2_size): New function.
 394         (extract_nps_bitop2_size): New function.
 395         (insert_nps_bitop_mod4_msb): New function.
 396         (extract_nps_bitop_mod4_msb): New function.
 397         (insert_nps_bitop_mod4_lsb): New function.
 398         (extract_nps_bitop_mod4_lsb): New function.
 399         (insert_nps_bitop_dst_pos3_pos4): New function.
 400         (extract_nps_bitop_dst_pos3_pos4): New function.
 401         (insert_nps_bitop_ins_ext): New function.
 402         (extract_nps_bitop_ins_ext): New function.
 403         (arc_operands): Add new operands.
 404         (arc_long_opcodes): New global array.
 405         (arc_num_long_opcodes): New global.
 406         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 407
 408 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 409
 410         * nds32-asm.h: Add extern "C".
 411         * sh-opc.h: Likewise.
 412
 413 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 414
 415         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 416         0,b,limm to the rflt instruction.
 417
 418 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 419
 420         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 421         constant.
 422
 423 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 424
 425         PR gas/20145
 426         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 427         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 428         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 429         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 430         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 431         * i386-init.h: Regenerated.
 432
 433 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 434
 435         PR gas/20145
 436         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 437         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 438         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 439         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 440         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 441         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 442         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 443         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 444         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 445         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 446         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 447         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 448         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 449         CpuRegMask for AVX512.
 450         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 451         and CpuRegMask.
 452         (set_bitfield_from_cpu_flag_init): New function.
 453         (set_bitfield): Remove const on f.  Call
 454         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 455         * i386-opc.h (CpuRegMMX): New.
 456         (CpuRegXMM): Likewise.
 457         (CpuRegYMM): Likewise.
 458         (CpuRegZMM): Likewise.
 459         (CpuRegMask): Likewise.
 460         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 461         and cpuregmask.
 462         * i386-init.h: Regenerated.
 463         * i386-tbl.h: Likewise.
 464
 465 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 466
 467         PR gas/20154
 468         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 469         (opcode_modifiers): Add AMD64 and Intel64.
 470         (main): Properly verify CpuMax.
 471         * i386-opc.h (CpuAMD64): Removed.
 472         (CpuIntel64): Likewise.
 473         (CpuMax): Set to CpuNo64.
 474         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 475         (AMD64): New.
 476         (Intel64): Likewise.
 477         (i386_opcode_modifier): Add amd64 and intel64.
 478         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 479         on call and jmp.
 480         * i386-init.h: Regenerated.
 481         * i386-tbl.h: Likewise.
 482
 483 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 484
 485         PR gas/20154
 486         * i386-gen.c (main): Fail if CpuMax is incorrect.
 487         * i386-opc.h (CpuMax): Set to CpuIntel64.
 488         * i386-tbl.h: Regenerated.
 489
 490 2016-05-27  Nick Clifton  <nickc@redhat.com>
 491
 492         PR target/20150
 493         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 494         (msp430dis_opcode_unsigned): New function.
 495         (msp430dis_opcode_signed): New function.
 496         (msp430_singleoperand): Use the new opcode reading functions.
 497         Only disassenmble bytes if they were successfully read.
 498         (msp430_doubleoperand): Likewise.
 499         (msp430_branchinstr): Likewise.
 500         (msp430x_callx_instr): Likewise.
 501         (print_insn_msp430): Check that it is safe to read bytes before
 502         attempting disassembly.  Use the new opcode reading functions.
 503
 504 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 505
 506         * ppc-opc.c (CY): New define.  Document it.
 507         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 508
 509 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 510
 511         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 512         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 513         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 514         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 515         CPU_ANY_AVX_FLAGS.
 516         * i386-init.h: Regenerated.
 517
 518 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 519
 520         PR gas/20141
 521         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 522         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 523         * i386-init.h: Regenerated.
 524
 525 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 526
 527         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 528         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 529         * i386-init.h: Regenerated.
 530
 531 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 532
 533         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 534         information.
 535         (print_insn_arc): Set insn_type information.
 536         * arc-opc.c (C_CC): Add F_CLASS_COND.
 537         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 538         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 539         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 540         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 541         (brne, brne_s, jeq_s, jne_s): Likewise.
 542
 543 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 544
 545         * arc-tbl.h (neg): New instruction variant.
 546
 547 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 548
 549         * arc-dis.c (find_format, find_format, get_auxreg)
 550         (print_insn_arc): Changed.
 551         * arc-ext.h (INSERT_XOP): Likewise.
 552
 553 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 554
 555         * tic54x-dis.c (sprint_mmr): Adjust.
 556         * tic54x-opc.c: Likewise.
 557
 558 2016-05-19  Alan Modra  <amodra@gmail.com>
 559
 560         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 561
 562 2016-05-19  Alan Modra  <amodra@gmail.com>
 563
 564         * ppc-opc.c: Formatting.
 565         (NSISIGNOPT): Define.
 566         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 567
 568 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 569
 570         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 571         replacing references to `micromips_ase' throughout.
 572         (_print_insn_mips): Don't use file-level microMIPS annotation to
 573         determine the disassembly mode with the symbol table.
 574
 575 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 576
 577         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 578
 579 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 580
 581         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 582         mips64r6.
 583         * mips-opc.c (D34): New macro.
 584         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 585
 586 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 587
 588         * i386-dis.c (prefix_table): Add RDPID instruction.
 589         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 590         (cpu_flags): Add RDPID bitfield.
 591         * i386-opc.h (enum): Add RDPID element.
 592         (i386_cpu_flags): Add RDPID field.
 593         * i386-opc.tbl: Add RDPID instruction.
 594         * i386-init.h: Regenerate.
 595         * i386-tbl.h: Regenerate.
 596
 597 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 598
 599         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 600         branch type of a symbol.
 601         (print_insn): Likewise.
 602
 603 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 604
 605         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 606         Mainline Security Extensions instructions.
 607         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 608         Extensions instructions.
 609         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 610         instructions.
 611         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 612         special registers.
 613
 614 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 615
 616         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 617
 618 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 619
 620         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 621         (arcExtMap_genOpcode): Likewise.
 622         * arc-opc.c (arg_32bit_rc): Define new variable.
 623         (arg_32bit_u6): Likewise.
 624         (arg_32bit_limm): Likewise.
 625
 626 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 627
 628         * aarch64-gen.c (VERIFIER): Define.
 629         * aarch64-opc.c (VERIFIER): Define.
 630         (verify_ldpsw): Use static linkage.
 631         * aarch64-opc.h (verify_ldpsw): Remove.
 632         * aarch64-tbl.h: Use VERIFIER for verifiers.
 633
 634 2016-04-28  Nick Clifton  <nickc@redhat.com>
 635
 636         PR target/19722
 637         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 638         * aarch64-opc.c (verify_ldpsw): New function.
 639         * aarch64-opc.h (verify_ldpsw): New prototype.
 640         * aarch64-tbl.h: Add initialiser for verifier field.
 641         (LDPSW): Set verifier to verify_ldpsw.
 642
 643 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 644
 645         PR binutils/19983
 646         PR binutils/19984
 647         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 648         smaller than address size.
 649
 650 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 651
 652         * alpha-dis.c: Regenerate.
 653         * crx-dis.c: Likewise.
 654         * disassemble.c: Likewise.
 655         * epiphany-opc.c: Likewise.
 656         * fr30-opc.c: Likewise.
 657         * frv-opc.c: Likewise.
 658         * ip2k-opc.c: Likewise.
 659         * iq2000-opc.c: Likewise.
 660         * lm32-opc.c: Likewise.
 661         * lm32-opinst.c: Likewise.
 662         * m32c-opc.c: Likewise.
 663         * m32r-opc.c: Likewise.
 664         * m32r-opinst.c: Likewise.
 665         * mep-opc.c: Likewise.
 666         * mt-opc.c: Likewise.
 667         * or1k-opc.c: Likewise.
 668         * or1k-opinst.c: Likewise.
 669         * tic80-opc.c: Likewise.
 670         * xc16x-opc.c: Likewise.
 671         * xstormy16-opc.c: Likewise.
 672
 673 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 674
 675         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 676         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 677         calcsd, and calcxd instructions.
 678         * arc-opc.c (insert_nps_bitop_size): Delete.
 679         (extract_nps_bitop_size): Delete.
 680         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 681         (extract_nps_qcmp_m3): Define.
 682         (extract_nps_qcmp_m2): Define.
 683         (extract_nps_qcmp_m1): Define.
 684         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 685         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 686         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 687         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 688         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 689         NPS_QCMP_M3.
 690
 691 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 692
 693         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 694
 695 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 696
 697         * Makefile.in: Regenerated with automake 1.11.6.
 698         * aclocal.m4: Likewise.
 699
 700 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 701
 702         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 703         instructions.
 704         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 705         (extract_nps_cmem_uimm16): New function.
 706         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 707
 708 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 709
 710         * arc-dis.c (arc_insn_length): New function.
 711         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 712         (find_format): Change insnLen parameter to unsigned.
 713
 714 2016-04-13  Nick Clifton  <nickc@redhat.com>
 715
 716         PR target/19937
 717         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 718         the LD.B and LD.BU instructions.
 719
 720 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 721
 722         * arc-dis.c (find_format): Check for extension flags.
 723         (print_flags): New function.
 724         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 725         .extAuxRegister.
 726         * arc-ext.c (arcExtMap_coreRegName): Use
 727         LAST_EXTENSION_CORE_REGISTER.
 728         (arcExtMap_coreReadWrite): Likewise.
 729         (dump_ARC_extmap): Update printing.
 730         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 731         (arc_aux_regs): Add cpu field.
 732         * arc-regs.h: Add cpu field, lower case name aux registers.
 733
 734 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 735
 736         * arc-tbl.h: Add rtsc, sleep with no arguments.
 737
 738 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 739
 740         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 741         Initialize.
 742         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 743         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 744         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 745         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 746         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 747         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 748         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 749         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 750         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 751         (arc_opcode arc_opcodes): Null terminate the array.
 752         (arc_num_opcodes): Remove.
 753         * arc-ext.h (INSERT_XOP): Define.
 754         (extInstruction_t): Likewise.
 755         (arcExtMap_instName): Delete.
 756         (arcExtMap_insn): New function.
 757         (arcExtMap_genOpcode): Likewise.
 758         * arc-ext.c (ExtInstruction): Remove.
 759         (create_map): Zero initialize instruction fields.
 760         (arcExtMap_instName): Remove.
 761         (arcExtMap_insn): New function.
 762         (dump_ARC_extmap): More info while debuging.
 763         (arcExtMap_genOpcode): New function.
 764         * arc-dis.c (find_format): New function.
 765         (print_insn_arc): Use find_format.
 766         (arc_get_disassembler): Enable dump_ARC_extmap only when
 767         debugging.
 768
 769 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 770
 771         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 772         instruction bits out.
 773
 774 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 775
 776         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 777         * arc-opc.c (arc_flag_operands): Add new flags.
 778         (arc_flag_classes): Add new classes.
 779
 780 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 781
 782         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 783
 784 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 785
 786         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 787         encode1, rflt, crc16, and crc32 instructions.
 788         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 789         (arc_flag_classes): Add C_NPS_R.
 790         (insert_nps_bitop_size_2b): New function.
 791         (extract_nps_bitop_size_2b): Likewise.
 792         (insert_nps_bitop_uimm8): Likewise.
 793         (extract_nps_bitop_uimm8): Likewise.
 794         (arc_operands): Add new operand entries.
 795
 796 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 797
 798         * arc-regs.h: Add a new subclass field.  Add double assist
 799         accumulator register values.
 800         * arc-tbl.h: Use DPA subclass to mark the double assist
 801         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 802         * arc-opc.c (RSP): Define instead of SP.
 803         (arc_aux_regs): Add the subclass field.
 804
 805 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 806
 807         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 808
 809 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 810
 811         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 812         NPS_R_SRC1.
 813
 814 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 815
 816         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 817         issues.  No functional changes.
 818
 819 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 820
 821         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 822         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 823         (RTT): Remove duplicate.
 824         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 825         (PCT_CONFIG*): Remove.
 826         (D1L, D1H, D2H, D2L): Define.
 827
 828 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 829
 830         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 831
 832 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 833
 834         * arc-tbl.h (invld07): Remove.
 835         * arc-ext-tbl.h: New file.
 836         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 837         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 838
 839 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 840
 841         Fix -Wstack-usage warnings.
 842         * aarch64-dis.c (print_operands): Substitute size.
 843         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 844
 845 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 846
 847         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 848         to get a proper diagnostic when an invalid ASR register is used.
 849
 850 2016-03-22  Nick Clifton  <nickc@redhat.com>
 851
 852         * configure: Regenerate.
 853
 854 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 855
 856         * arc-nps400-tbl.h: New file.
 857         * arc-opc.c: Add top level comment.
 858         (insert_nps_3bit_dst): New function.
 859         (extract_nps_3bit_dst): New function.
 860         (insert_nps_3bit_src2): New function.
 861         (extract_nps_3bit_src2): New function.
 862         (insert_nps_bitop_size): New function.
 863         (extract_nps_bitop_size): New function.
 864         (arc_flag_operands): Add nps400 entries.
 865         (arc_flag_classes): Add nps400 entries.
 866         (arc_operands): Add nps400 entries.
 867         (arc_opcodes): Add nps400 include.
 868
 869 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 870
 871         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 872         the new class enum values.
 873
 874 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 875
 876         * arc-dis.c (print_insn_arc): Handle nps400.
 877
 878 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 879
 880         * arc-opc.c (BASE): Delete.
 881
 882 2016-03-18  Nick Clifton  <nickc@redhat.com>
 883
 884         PR target/19721
 885         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 886         of MOV insn that aliases an ORR insn.
 887
 888 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 889
 890         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 891
 892 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 893
 894         * mcore-opc.h: Add const qualifiers.
 895         * microblaze-opc.h (struct op_code_struct): Likewise.
 896         * sh-opc.h: Likewise.
 897         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 898         (tic4x_print_op): Likewise.
 899
 900 2016-03-02  Alan Modra  <amodra@gmail.com>
 901
 902         * or1k-desc.h: Regenerate.
 903         * fr30-ibld.c: Regenerate.
 904         * rl78-decode.c: Regenerate.
 905
 906 2016-03-01  Nick Clifton  <nickc@redhat.com>
 907
 908         PR target/19747
 909         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 910
 911 2016-02-24  Renlin Li  <renlin.li@arm.com>
 912
 913         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 914         (print_insn_coprocessor): Support fp16 instructions.
 915
 916 2016-02-24  Renlin Li  <renlin.li@arm.com>
 917
 918         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 919         vminnm, vrint(mpna).
 920
 921 2016-02-24  Renlin Li  <renlin.li@arm.com>
 922
 923         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 924         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 925
 926 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 927
 928         * i386-dis.c (print_insn): Parenthesize expression to prevent
 929         truncated addresses.
 930         (OP_J): Likewise.
 931
 932 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 933             Janek van Oirschot  <jvanoirs@synopsys.com>
 934
 935         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 936         variable.
 937
 938 2016-02-04  Nick Clifton  <nickc@redhat.com>
 939
 940         PR target/19561
 941         * msp430-dis.c (print_insn_msp430): Add a special case for
 942         decoding an RRC instruction with the ZC bit set in the extension
 943         word.
 944
 945 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 946
 947         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 948         * epiphany-ibld.c: Regenerate.
 949         * fr30-ibld.c: Regenerate.
 950         * frv-ibld.c: Regenerate.
 951         * ip2k-ibld.c: Regenerate.
 952         * iq2000-ibld.c: Regenerate.
 953         * lm32-ibld.c: Regenerate.
 954         * m32c-ibld.c: Regenerate.
 955         * m32r-ibld.c: Regenerate.
 956         * mep-ibld.c: Regenerate.
 957         * mt-ibld.c: Regenerate.
 958         * or1k-ibld.c: Regenerate.
 959         * xc16x-ibld.c: Regenerate.
 960         * xstormy16-ibld.c: Regenerate.
 961
 962 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 963
 964         * epiphany-dis.c: Regenerated from latest cpu files.
 965
 966 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 967
 968         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 969         test bit.
 970
 971 2016-01-25  Renlin Li  <renlin.li@arm.com>
 972
 973         * arm-dis.c (mapping_symbol_for_insn): New function.
 974         (find_ifthen_state): Call mapping_symbol_for_insn().
 975
 976 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 977
 978         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 979         of MSR UAO immediate operand.
 980
 981 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 982
 983         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 984         instruction support.
 985
 986 2016-01-17  Alan Modra  <amodra@gmail.com>
 987
 988         * configure: Regenerate.
 989
 990 2016-01-14  Nick Clifton  <nickc@redhat.com>
 991
 992         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 993         instructions that can support stack pointer operations.
 994         * rl78-decode.c: Regenerate.
 995         * rl78-dis.c: Fix display of stack pointer in MOVW based
 996         instructions.
 997
 998 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 999
1000         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1001         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1002         erxtatus_el1 and erxaddr_el1.
1003
1004 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1005
1006         * arm-dis.c (arm_opcodes): Add "esb".
1007         (thumb_opcodes): Likewise.
1008
1009 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1010
1011         * ppc-opc.c <xscmpnedp>: Delete.
1012         <xvcmpnedp>: Likewise.
1013         <xvcmpnedp.>: Likewise.
1014         <xvcmpnesp>: Likewise.
1015         <xvcmpnesp.>: Likewise.
1016
1017 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1018
1019         PR gas/13050
1020         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1021         addition to ISA_A.
1022
1023 2016-01-01  Alan Modra  <amodra@gmail.com>
1024
1025         Update year range in copyright notice of all files.
1026
1027 For older changes see ChangeLog-2015
1028 \f
1029 Copyright (C) 2016 Free Software Foundation, Inc.
1030
1031 Copying and distribution of this file, with or without modification,
1032 are permitted in any medium without royalty provided the copyright
1033 notice and this notice are preserved.
1034
1035 Local Variables:
1036 mode: change-log
1037 left-margin: 8
1038 fill-column: 74
1039 version-control: never
1040 End: