opcodes/ChangeLog

   1 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
   2
   3         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
   4
   5 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
   6
   7         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
   8         * arc-opc.c (insert_r13el): New function.
   9         (R13_EL): Define.
  10         * arc-tbl.h: Add new enter/leave variants.
  11
  12 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
  13
  14         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
  15
  16 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
  17
  18         * mips-dis.c (print_mips_disassembler_options): Add
  19         `no-aliases'.
  20
  21 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
  22
  23         * mips16-opc.c (AL): New macro.
  24         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
  25         of "ld" and "lw" as aliases.
  26
  27 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
  28
  29         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
  30         arguments.
  31
  32 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
  33             Alan Modra  <amodra@gmail.com>
  34
  35         * ppc-opc.c (ELEV): Define.
  36         (vle_opcodes): Add se_rfgi and e_sc.
  37         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
  38         for E200Z4.
  39
  40 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
  41
  42         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
  43
  44 2017-04-21  Nick Clifton  <nickc@redhat.com>
  45
  46         PR binutils/21380
  47         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
  48         LD3R and LD4R.
  49
  50 2017-04-13  Alan Modra  <amodra@gmail.com>
  51
  52         * epiphany-desc.c: Regenerate.
  53         * fr30-desc.c: Regenerate.
  54         * frv-desc.c: Regenerate.
  55         * ip2k-desc.c: Regenerate.
  56         * iq2000-desc.c: Regenerate.
  57         * lm32-desc.c: Regenerate.
  58         * m32c-desc.c: Regenerate.
  59         * m32r-desc.c: Regenerate.
  60         * mep-desc.c: Regenerate.
  61         * mt-desc.c: Regenerate.
  62         * or1k-desc.c: Regenerate.
  63         * xc16x-desc.c: Regenerate.
  64         * xstormy16-desc.c: Regenerate.
  65
  66 2017-04-11  Alan Modra  <amodra@gmail.com>
  67
  68         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
  69         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
  70         PPC_OPCODE_TMR for e6500.
  71         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
  72         (PPCVEC3): Define as PPC_OPCODE_POWER9.
  73         (PPCVSX2): Define as PPC_OPCODE_POWER8.
  74         (PPCVSX3): Define as PPC_OPCODE_POWER9.
  75         (PPCHTM): Define as PPC_OPCODE_POWER8.
  76         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
  77
  78 2017-04-10  Alan Modra  <amodra@gmail.com>
  79
  80         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
  81         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
  82         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
  83         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
  84
  85 2017-04-09  Pip Cet  <pipcet@gmail.com>
  86
  87         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
  88         appropriate floating-point precision directly.
  89
  90 2017-04-07  Alan Modra  <amodra@gmail.com>
  91
  92         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
  93         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
  94         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
  95         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
  96         vector instructions with E6500 not PPCVEC2.
  97
  98 2017-04-06  Pip Cet  <pipcet@gmail.com>
  99
 100         * Makefile.am: Add wasm32-dis.c.
 101         * configure.ac: Add wasm32-dis.c to wasm32 target.
 102         * disassemble.c: Add wasm32 disassembler code.
 103         * wasm32-dis.c: New file.
 104         * Makefile.in: Regenerate.
 105         * configure: Regenerate.
 106         * po/POTFILES.in: Regenerate.
 107         * po/opcodes.pot: Regenerate.
 108
 109 2017-04-05  Pedro Alves  <palves@redhat.com>
 110
 111         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 112         * arm-dis.c (parse_arm_disassembler_options): Constify.
 113         * ppc-dis.c (powerpc_init_dialect): Constify local.
 114         * vax-dis.c (parse_disassembler_options): Constify.
 115
 116 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 117
 118         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 119         RISCV_GP_SYMBOL.
 120
 121 2017-03-30  Pip Cet  <pipcet@gmail.com>
 122
 123         * configure.ac: Add (empty) bfd_wasm32_arch target.
 124         * configure: Regenerate
 125         * po/opcodes.pot: Regenerate.
 126
 127 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 128
 129         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 130         OSA2015.
 131         * opcodes/sparc-opc.c (asi_table): New ASIs.
 132
 133 2017-03-29  Alan Modra  <amodra@gmail.com>
 134
 135         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 136         "raw" option.
 137         (lookup_powerpc): Don't special case -1 dialect.  Handle
 138         PPC_OPCODE_RAW.
 139         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 140         lookup_powerpc call, pass it on second.
 141
 142 2017-03-27  Alan Modra  <amodra@gmail.com>
 143
 144         PR 21303
 145         * ppc-dis.c (struct ppc_mopt): Comment.
 146         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 147
 148 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 149
 150         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 151         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 152         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 153         (insert_nps_misc_imm_offset): New function.
 154         (extract_nps_misc imm_offset): New function.
 155         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 156         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 157
 158 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 159
 160         * s390-mkopc.c (main): Remove vx2 check.
 161         * s390-opc.txt: Remove vx2 instruction flags.
 162
 163 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 164
 165         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 166         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 167         (insert_nps_imm_offset): New function.
 168         (extract_nps_imm_offset): New function.
 169         (insert_nps_imm_entry): New function.
 170         (extract_nps_imm_entry): New function.
 171
 172 2017-03-17  Alan Modra  <amodra@gmail.com>
 173
 174         PR 21248
 175         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 176         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 177         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 178
 179 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 180
 181         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 182         <c.andi>: Likewise.
 183         <c.addiw> Likewise.
 184
 185 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 186
 187         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 188
 189 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 190
 191         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 192         <srl> Likewise.
 193         <srai> Likewise.
 194         <sra> Likewise.
 195
 196 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 197
 198         * i386-gen.c (opcode_modifiers): Replace S with Load.
 199         * i386-opc.h (S): Removed.
 200         (Load): New.
 201         (i386_opcode_modifier): Replace s with load.
 202         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 203         and {evex}.  Replace S with Load.
 204         * i386-tbl.h: Regenerated.
 205
 206 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 207
 208         * i386-opc.tbl: Use CpuCET on rdsspq.
 209         * i386-tbl.h: Regenerated.
 210
 211 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 212
 213         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 214         <vsx>: Do not use PPC_OPCODE_VSX3;
 215
 216 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 217
 218         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 219
 220 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 221
 222         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 223         (MOD_0F1E_PREFIX_1): Likewise.
 224         (MOD_0F38F5_PREFIX_2): Likewise.
 225         (MOD_0F38F6_PREFIX_0): Likewise.
 226         (RM_0F1E_MOD_3_REG_7): Likewise.
 227         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 228         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 229         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 230         (PREFIX_0F1E): Likewise.
 231         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 232         (PREFIX_0F38F5): Likewise.
 233         (dis386_twobyte): Use PREFIX_0F1E.
 234         (reg_table): Add REG_0F1E_MOD_3.
 235         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 236         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 237         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 238         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 239         (three_byte_table): Use PREFIX_0F38F5.
 240         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 241         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 242         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 243         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 244         PREFIX_MOD_3_0F01_REG_5_RM_2.
 245         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 246         (cpu_flags): Add CpuCET.
 247         * i386-opc.h (CpuCET): New enum.
 248         (CpuUnused): Commented out.
 249         (i386_cpu_flags): Add cpucet.
 250         * i386-opc.tbl: Add Intel CET instructions.
 251         * i386-init.h: Regenerated.
 252         * i386-tbl.h: Likewise.
 253
 254 2017-03-06  Alan Modra  <amodra@gmail.com>
 255
 256         PR 21124
 257         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 258         (extract_raq, extract_ras, extract_rbx): New functions.
 259         (powerpc_operands): Use opposite corresponding insert function.
 260         (Q_MASK): Define.
 261         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 262         register restriction.
 263
 264 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 265
 266         * disassemble.c Include "safe-ctype.h".
 267         (disassemble_init_for_target): Handle s390 init.
 268         (remove_whitespace_and_extra_commas): New function.
 269         (disassembler_options_cmp): Likewise.
 270         * arm-dis.c: Include "libiberty.h".
 271         (NUM_ELEM): Delete.
 272         (regnames): Use long disassembler style names.
 273         Add force-thumb and no-force-thumb options.
 274         (NUM_ARM_REGNAMES): Rename from this...
 275         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 276         (get_arm_regname_num_options): Delete.
 277         (set_arm_regname_option): Likewise.
 278         (get_arm_regnames): Likewise.
 279         (parse_disassembler_options): Likewise.
 280         (parse_arm_disassembler_option): Rename from this...
 281         (parse_arm_disassembler_options): ...to this.  Make static.
 282         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 283         (print_insn): Use parse_arm_disassembler_options.
 284         (disassembler_options_arm): New function.
 285         (print_arm_disassembler_options): Handle updated regnames.
 286         * ppc-dis.c: Include "libiberty.h".
 287         (ppc_opts): Add "32" and "64" entries.
 288         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 289         (powerpc_init_dialect): Add break to switch statement.
 290         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 291         (disassembler_options_powerpc): New function.
 292         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 293         Remove printing of "32" and "64".
 294         * s390-dis.c: Include "libiberty.h".
 295         (init_flag): Remove unneeded variable.
 296         (struct s390_options_t): New structure type.
 297         (options): New structure.
 298         (init_disasm): Rename from this...
 299         (disassemble_init_s390): ...to this.  Add initializations for
 300         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 301         (print_insn_s390): Delete call to init_disasm.
 302         (disassembler_options_s390): New function.
 303         (print_s390_disassembler_options): Print using information from
 304         struct 'options'.
 305         * po/opcodes.pot: Regenerate.
 306
 307 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 308
 309         * i386-dis.c (PCMPESTR_Fixup): New.
 310         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 311         (prefix_table): Use PCMPESTR_Fixup.
 312         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 313         PCMPESTR_Fixup.
 314         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 315         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 316         Split 64-bit and non-64-bit variants.
 317         * opcodes/i386-tbl.h: Re-generate.
 318
 319 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 320
 321         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 322         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 323         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 324         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 325         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 326         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 327         (OP_SVE_V_HSD): New macros.
 328         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 329         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 330         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 331         (aarch64_opcode_table): Add new SVE instructions.
 332         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 333         for rotation operands.  Add new SVE operands.
 334         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 335         (ins_sve_quad_index): Likewise.
 336         (ins_imm_rotate): Split into...
 337         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 338         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 339         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 340         functions.
 341         (aarch64_ins_sve_addr_ri_s4): New function.
 342         (aarch64_ins_sve_quad_index): Likewise.
 343         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 344         * aarch64-asm-2.c: Regenerate.
 345         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 346         (ext_sve_quad_index): Likewise.
 347         (ext_imm_rotate): Split into...
 348         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 349         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 350         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 351         functions.
 352         (aarch64_ext_sve_addr_ri_s4): New function.
 353         (aarch64_ext_sve_quad_index): Likewise.
 354         (aarch64_ext_sve_index): Allow quad indices.
 355         (do_misc_decoding): Likewise.
 356         * aarch64-dis-2.c: Regenerate.
 357         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 358         aarch64_field_kinds.
 359         (OPD_F_OD_MASK): Widen by one bit.
 360         (OPD_F_NO_ZR): Bump accordingly.
 361         (get_operand_field_width): New function.
 362         * aarch64-opc.c (fields): Add new SVE fields.
 363         (operand_general_constraint_met_p): Handle new SVE operands.
 364         (aarch64_print_operand): Likewise.
 365         * aarch64-opc-2.c: Regenerate.
 366
 367 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 368
 369         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 370         (aarch64_feature_compnum): ...this.
 371         (SIMD_V8_3): Replace with...
 372         (COMPNUM): ...this.
 373         (CNUM_INSN): New macro.
 374         (aarch64_opcode_table): Use it for the complex number instructions.
 375
 376 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 377
 378         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 379
 380 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 381
 382         Add support for associating SPARC ASIs with an architecture level.
 383         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 384         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 385         decoding of SPARC ASIs.
 386
 387 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 388
 389         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 390         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 391
 392 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 393
 394         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 395         1 (instead of to itself). Correct typo.
 396
 397 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 398
 399         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 400         pseudoinstructions.
 401
 402 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 403
 404         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 405         (aarch64_sys_reg_supported_p): Handle them.
 406
 407 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 408
 409         * arc-opc.c (UIMM6_20R): Define.
 410         (SIMM12_20): Use above.
 411         (SIMM12_20R): Define.
 412         (SIMM3_5_S): Use above.
 413         (UIMM7_A32_11R_S): Define.
 414         (UIMM7_9_S): Use above.
 415         (UIMM3_13R_S): Define.
 416         (SIMM11_A32_7_S): Use above.
 417         (SIMM9_8R): Define.
 418         (UIMM10_A32_8_S): Use above.
 419         (UIMM8_8R_S): Define.
 420         (W6): Use above.
 421         (arc_relax_opcodes): Use all above defines.
 422
 423 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 424
 425         * arc-regs.h: Distinguish some of the registers different on
 426         ARC700 and HS38 cpus.
 427
 428 2017-02-14  Alan Modra  <amodra@gmail.com>
 429
 430         PR 21118
 431         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 432         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 433
 434 2017-02-11  Stafford Horne  <shorne@gmail.com>
 435             Alan Modra  <amodra@gmail.com>
 436
 437         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 438         Use insn_bytes_value and insn_int_value directly instead.  Don't
 439         free allocated memory until function exit.
 440
 441 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 442
 443         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 444
 445 2017-02-03  Nick Clifton  <nickc@redhat.com>
 446
 447         PR 21096
 448         * aarch64-opc.c (print_register_list): Ensure that the register
 449         list index will fir into the tb buffer.
 450         (print_register_offset_address): Likewise.
 451         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 452
 453 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 454
 455         PR 21056
 456         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 457         instructions when the previous fetch packet ends with a 32-bit
 458         instruction.
 459
 460 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 461
 462         * pru-opc.c: Remove vague reference to a future GDB port.
 463
 464 2017-01-20  Nick Clifton  <nickc@redhat.com>
 465
 466         * po/ga.po: Updated Irish translation.
 467
 468 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 469
 470         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 471
 472 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 473
 474         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 475         if FETCH_DATA returns 0.
 476         (m68k_scan_mask): Likewise.
 477         (print_insn_m68k): Update code to handle -1 return value.
 478
 479 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 480
 481         * m68k-dis.c (enum print_insn_arg_error): New.
 482         (NEXTBYTE): Replace -3 with
 483         PRINT_INSN_ARG_MEMORY_ERROR.
 484         (NEXTULONG): Likewise.
 485         (NEXTSINGLE): Likewise.
 486         (NEXTDOUBLE): Likewise.
 487         (NEXTDOUBLE): Likewise.
 488         (NEXTPACKED): Likewise.
 489         (FETCH_ARG): Likewise.
 490         (FETCH_DATA): Update comments.
 491         (print_insn_arg): Update comments. Replace magic numbers with
 492         enum.
 493         (match_insn_m68k): Likewise.
 494
 495 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 496
 497         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 498         * i386-dis-evex.h (evex_table): Updated.
 499         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 500         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 501         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 502         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 503         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 504         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 505         * i386-init.h: Regenerate.
 506         * i386-tbl.h: Ditto.
 507
 508 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 509
 510         * msp430-dis.c (msp430_singleoperand): Return -1 if
 511         msp430dis_opcode_signed returns false.
 512         (msp430_doubleoperand): Likewise.
 513         (msp430_branchinstr): Return -1 if
 514         msp430dis_opcode_unsigned returns false.
 515         (msp430x_calla_instr): Likewise.
 516         (print_insn_msp430): Likewise.
 517
 518 2017-01-05  Nick Clifton  <nickc@redhat.com>
 519
 520         PR 20946
 521         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 522         could not be matched.
 523         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 524         NULL.
 525
 526 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 527
 528         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 529         (aarch64_opcode_table): Use RCPC_INSN.
 530
 531 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 532
 533         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 534         extension.
 535         * riscv-opcodes/all-opcodes: Likewise.
 536
 537 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 538
 539         * riscv-dis.c (print_insn_args): Add fall through comment.
 540
 541 2017-01-03  Nick Clifton  <nickc@redhat.com>
 542
 543         * po/sr.po: New Serbian translation.
 544         * configure.ac (ALL_LINGUAS): Add sr.
 545         * configure: Regenerate.
 546
 547 2017-01-02  Alan Modra  <amodra@gmail.com>
 548
 549         * epiphany-desc.h: Regenerate.
 550         * epiphany-opc.h: Regenerate.
 551         * fr30-desc.h: Regenerate.
 552         * fr30-opc.h: Regenerate.
 553         * frv-desc.h: Regenerate.
 554         * frv-opc.h: Regenerate.
 555         * ip2k-desc.h: Regenerate.
 556         * ip2k-opc.h: Regenerate.
 557         * iq2000-desc.h: Regenerate.
 558         * iq2000-opc.h: Regenerate.
 559         * lm32-desc.h: Regenerate.
 560         * lm32-opc.h: Regenerate.
 561         * m32c-desc.h: Regenerate.
 562         * m32c-opc.h: Regenerate.
 563         * m32r-desc.h: Regenerate.
 564         * m32r-opc.h: Regenerate.
 565         * mep-desc.h: Regenerate.
 566         * mep-opc.h: Regenerate.
 567         * mt-desc.h: Regenerate.
 568         * mt-opc.h: Regenerate.
 569         * or1k-desc.h: Regenerate.
 570         * or1k-opc.h: Regenerate.
 571         * xc16x-desc.h: Regenerate.
 572         * xc16x-opc.h: Regenerate.
 573         * xstormy16-desc.h: Regenerate.
 574         * xstormy16-opc.h: Regenerate.
 575
 576 2017-01-02  Alan Modra  <amodra@gmail.com>
 577
 578         Update year range in copyright notice of all files.
 579
 580 For older changes see ChangeLog-2016
 581 \f
 582 Copyright (C) 2017 Free Software Foundation, Inc.
 583
 584 Copying and distribution of this file, with or without modification,
 585 are permitted in any medium without royalty provided the copyright
 586 notice and this notice are preserved.
 587
 588 Local Variables:
 589 mode: change-log
 590 left-margin: 8
 591 fill-column: 74
 592 version-control: never
 593 End: