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[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.
[deliverable/binutils-gdb.git] / opcodes / aarch64-asm.c
1 /* aarch64-asm.c -- AArch64 assembler support.
2 Copyright (C) 2012-2019 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21 #include "sysdep.h"
22 #include <stdarg.h>
23 #include "libiberty.h"
24 #include "aarch64-asm.h"
25 #include "opintl.h"
26
27 /* Utilities. */
28
29 /* The unnamed arguments consist of the number of fields and information about
30 these fields where the VALUE will be inserted into CODE. MASK can be zero or
31 the base mask of the opcode.
32
33 N.B. the fields are required to be in such an order than the least signficant
34 field for VALUE comes the first, e.g. the <index> in
35 SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
36 is encoded in H:L:M in some cases, the fields H:L:M should be passed in
37 the order of M, L, H. */
38
39 static inline void
40 insert_fields (aarch64_insn *code, aarch64_insn value, aarch64_insn mask, ...)
41 {
42 uint32_t num;
43 const aarch64_field *field;
44 enum aarch64_field_kind kind;
45 va_list va;
46
47 va_start (va, mask);
48 num = va_arg (va, uint32_t);
49 assert (num <= 5);
50 while (num--)
51 {
52 kind = va_arg (va, enum aarch64_field_kind);
53 field = &fields[kind];
54 insert_field (kind, code, value, mask);
55 value >>= field->width;
56 }
57 va_end (va);
58 }
59
60 /* Insert a raw field value VALUE into all fields in SELF->fields.
61 The least significant bit goes in the final field. */
62
63 static void
64 insert_all_fields (const aarch64_operand *self, aarch64_insn *code,
65 aarch64_insn value)
66 {
67 unsigned int i;
68 enum aarch64_field_kind kind;
69
70 for (i = ARRAY_SIZE (self->fields); i-- > 0; )
71 if (self->fields[i] != FLD_NIL)
72 {
73 kind = self->fields[i];
74 insert_field (kind, code, value, 0);
75 value >>= fields[kind].width;
76 }
77 }
78
79 /* Operand inserters. */
80
81 /* Insert register number. */
82 bfd_boolean
83 aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info,
84 aarch64_insn *code,
85 const aarch64_inst *inst ATTRIBUTE_UNUSED,
86 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
87 {
88 insert_field (self->fields[0], code, info->reg.regno, 0);
89 return TRUE;
90 }
91
92 /* Insert register number, index and/or other data for SIMD register element
93 operand, e.g. the last source operand in
94 SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
95 bfd_boolean
96 aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
97 aarch64_insn *code, const aarch64_inst *inst,
98 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
99 {
100 /* regno */
101 insert_field (self->fields[0], code, info->reglane.regno, inst->opcode->mask);
102 /* index and/or type */
103 if (inst->opcode->iclass == asisdone || inst->opcode->iclass == asimdins)
104 {
105 int pos = info->qualifier - AARCH64_OPND_QLF_S_B;
106 if (info->type == AARCH64_OPND_En
107 && inst->opcode->operands[0] == AARCH64_OPND_Ed)
108 {
109 /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */
110 assert (info->idx == 1); /* Vn */
111 aarch64_insn value = info->reglane.index << pos;
112 insert_field (FLD_imm4, code, value, 0);
113 }
114 else
115 {
116 /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>].
117 imm5<3:0> <V>
118 0000 RESERVED
119 xxx1 B
120 xx10 H
121 x100 S
122 1000 D */
123 aarch64_insn value = ((info->reglane.index << 1) | 1) << pos;
124 insert_field (FLD_imm5, code, value, 0);
125 }
126 }
127 else if (inst->opcode->iclass == dotproduct)
128 {
129 unsigned reglane_index = info->reglane.index;
130 switch (info->qualifier)
131 {
132 case AARCH64_OPND_QLF_S_4B:
133 /* L:H */
134 assert (reglane_index < 4);
135 insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);
136 break;
137 default:
138 assert (0);
139 }
140 }
141 else if (inst->opcode->iclass == cryptosm3)
142 {
143 /* index for e.g. SM3TT2A <Vd>.4S, <Vn>.4S, <Vm>S[<imm2>]. */
144 unsigned reglane_index = info->reglane.index;
145 assert (reglane_index < 4);
146 insert_field (FLD_SM3_imm2, code, reglane_index, 0);
147 }
148 else
149 {
150 /* index for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
151 or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
152 unsigned reglane_index = info->reglane.index;
153
154 if (inst->opcode->op == OP_FCMLA_ELEM)
155 /* Complex operand takes two elements. */
156 reglane_index *= 2;
157
158 switch (info->qualifier)
159 {
160 case AARCH64_OPND_QLF_S_H:
161 /* H:L:M */
162 assert (reglane_index < 8);
163 insert_fields (code, reglane_index, 0, 3, FLD_M, FLD_L, FLD_H);
164 break;
165 case AARCH64_OPND_QLF_S_S:
166 /* H:L */
167 assert (reglane_index < 4);
168 insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);
169 break;
170 case AARCH64_OPND_QLF_S_D:
171 /* H */
172 assert (reglane_index < 2);
173 insert_field (FLD_H, code, reglane_index, 0);
174 break;
175 default:
176 assert (0);
177 }
178 }
179 return TRUE;
180 }
181
182 /* Insert regno and len field of a register list operand, e.g. Vn in TBL. */
183 bfd_boolean
184 aarch64_ins_reglist (const aarch64_operand *self, const aarch64_opnd_info *info,
185 aarch64_insn *code,
186 const aarch64_inst *inst ATTRIBUTE_UNUSED,
187 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
188 {
189 /* R */
190 insert_field (self->fields[0], code, info->reglist.first_regno, 0);
191 /* len */
192 insert_field (FLD_len, code, info->reglist.num_regs - 1, 0);
193 return TRUE;
194 }
195
196 /* Insert Rt and opcode fields for a register list operand, e.g. Vt
197 in AdvSIMD load/store instructions. */
198 bfd_boolean
199 aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
200 const aarch64_opnd_info *info, aarch64_insn *code,
201 const aarch64_inst *inst,
202 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
203 {
204 aarch64_insn value = 0;
205 /* Number of elements in each structure to be loaded/stored. */
206 unsigned num = get_opcode_dependent_value (inst->opcode);
207
208 /* Rt */
209 insert_field (FLD_Rt, code, info->reglist.first_regno, 0);
210 /* opcode */
211 switch (num)
212 {
213 case 1:
214 switch (info->reglist.num_regs)
215 {
216 case 1: value = 0x7; break;
217 case 2: value = 0xa; break;
218 case 3: value = 0x6; break;
219 case 4: value = 0x2; break;
220 default: assert (0);
221 }
222 break;
223 case 2:
224 value = info->reglist.num_regs == 4 ? 0x3 : 0x8;
225 break;
226 case 3:
227 value = 0x4;
228 break;
229 case 4:
230 value = 0x0;
231 break;
232 default:
233 assert (0);
234 }
235 insert_field (FLD_opcode, code, value, 0);
236
237 return TRUE;
238 }
239
240 /* Insert Rt and S fields for a register list operand, e.g. Vt in AdvSIMD load
241 single structure to all lanes instructions. */
242 bfd_boolean
243 aarch64_ins_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
244 const aarch64_opnd_info *info, aarch64_insn *code,
245 const aarch64_inst *inst,
246 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
247 {
248 aarch64_insn value;
249 /* The opcode dependent area stores the number of elements in
250 each structure to be loaded/stored. */
251 int is_ld1r = get_opcode_dependent_value (inst->opcode) == 1;
252
253 /* Rt */
254 insert_field (FLD_Rt, code, info->reglist.first_regno, 0);
255 /* S */
256 value = (aarch64_insn) 0;
257 if (is_ld1r && info->reglist.num_regs == 2)
258 /* OP_LD1R does not have alternating variant, but have "two consecutive"
259 instead. */
260 value = (aarch64_insn) 1;
261 insert_field (FLD_S, code, value, 0);
262
263 return TRUE;
264 }
265
266 /* Insert Q, opcode<2:1>, S, size and Rt fields for a register element list
267 operand e.g. Vt in AdvSIMD load/store single element instructions. */
268 bfd_boolean
269 aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
270 const aarch64_opnd_info *info, aarch64_insn *code,
271 const aarch64_inst *inst ATTRIBUTE_UNUSED,
272 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
273 {
274 aarch64_field field = {0, 0};
275 aarch64_insn QSsize = 0; /* fields Q:S:size. */
276 aarch64_insn opcodeh2 = 0; /* opcode<2:1> */
277
278 assert (info->reglist.has_index);
279
280 /* Rt */
281 insert_field (FLD_Rt, code, info->reglist.first_regno, 0);
282 /* Encode the index, opcode<2:1> and size. */
283 switch (info->qualifier)
284 {
285 case AARCH64_OPND_QLF_S_B:
286 /* Index encoded in "Q:S:size". */
287 QSsize = info->reglist.index;
288 opcodeh2 = 0x0;
289 break;
290 case AARCH64_OPND_QLF_S_H:
291 /* Index encoded in "Q:S:size<1>". */
292 QSsize = info->reglist.index << 1;
293 opcodeh2 = 0x1;
294 break;
295 case AARCH64_OPND_QLF_S_S:
296 /* Index encoded in "Q:S". */
297 QSsize = info->reglist.index << 2;
298 opcodeh2 = 0x2;
299 break;
300 case AARCH64_OPND_QLF_S_D:
301 /* Index encoded in "Q". */
302 QSsize = info->reglist.index << 3 | 0x1;
303 opcodeh2 = 0x2;
304 break;
305 default:
306 assert (0);
307 }
308 insert_fields (code, QSsize, 0, 3, FLD_vldst_size, FLD_S, FLD_Q);
309 gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field);
310 insert_field_2 (&field, code, opcodeh2, 0);
311
312 return TRUE;
313 }
314
315 /* Insert fields immh:immb and/or Q for e.g. the shift immediate in
316 SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
317 or SSHR <V><d>, <V><n>, #<shift>. */
318 bfd_boolean
319 aarch64_ins_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
320 const aarch64_opnd_info *info,
321 aarch64_insn *code, const aarch64_inst *inst,
322 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
323 {
324 unsigned val = aarch64_get_qualifier_standard_value (info->qualifier);
325 aarch64_insn Q, imm;
326
327 if (inst->opcode->iclass == asimdshf)
328 {
329 /* Q
330 immh Q <T>
331 0000 x SEE AdvSIMD modified immediate
332 0001 0 8B
333 0001 1 16B
334 001x 0 4H
335 001x 1 8H
336 01xx 0 2S
337 01xx 1 4S
338 1xxx 0 RESERVED
339 1xxx 1 2D */
340 Q = (val & 0x1) ? 1 : 0;
341 insert_field (FLD_Q, code, Q, inst->opcode->mask);
342 val >>= 1;
343 }
344
345 assert (info->type == AARCH64_OPND_IMM_VLSR
346 || info->type == AARCH64_OPND_IMM_VLSL);
347
348 if (info->type == AARCH64_OPND_IMM_VLSR)
349 /* immh:immb
350 immh <shift>
351 0000 SEE AdvSIMD modified immediate
352 0001 (16-UInt(immh:immb))
353 001x (32-UInt(immh:immb))
354 01xx (64-UInt(immh:immb))
355 1xxx (128-UInt(immh:immb)) */
356 imm = (16 << (unsigned)val) - info->imm.value;
357 else
358 /* immh:immb
359 immh <shift>
360 0000 SEE AdvSIMD modified immediate
361 0001 (UInt(immh:immb)-8)
362 001x (UInt(immh:immb)-16)
363 01xx (UInt(immh:immb)-32)
364 1xxx (UInt(immh:immb)-64) */
365 imm = info->imm.value + (8 << (unsigned)val);
366 insert_fields (code, imm, 0, 2, FLD_immb, FLD_immh);
367
368 return TRUE;
369 }
370
371 /* Insert fields for e.g. the immediate operands in
372 BFM <Wd>, <Wn>, #<immr>, #<imms>. */
373 bfd_boolean
374 aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info,
375 aarch64_insn *code,
376 const aarch64_inst *inst ATTRIBUTE_UNUSED,
377 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
378 {
379 int64_t imm;
380
381 imm = info->imm.value;
382 if (operand_need_shift_by_two (self))
383 imm >>= 2;
384 if (operand_need_shift_by_four (self))
385 imm >>= 4;
386 insert_all_fields (self, code, imm);
387 return TRUE;
388 }
389
390 /* Insert immediate and its shift amount for e.g. the last operand in
391 MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
392 bfd_boolean
393 aarch64_ins_imm_half (const aarch64_operand *self, const aarch64_opnd_info *info,
394 aarch64_insn *code, const aarch64_inst *inst,
395 aarch64_operand_error *errors)
396 {
397 /* imm16 */
398 aarch64_ins_imm (self, info, code, inst, errors);
399 /* hw */
400 insert_field (FLD_hw, code, info->shifter.amount >> 4, 0);
401 return TRUE;
402 }
403
404 /* Insert cmode and "a:b:c:d:e:f:g:h" fields for e.g. the last operand in
405 MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
406 bfd_boolean
407 aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
408 const aarch64_opnd_info *info,
409 aarch64_insn *code,
410 const aarch64_inst *inst ATTRIBUTE_UNUSED,
411 aarch64_operand_error *errors
412 ATTRIBUTE_UNUSED)
413 {
414 enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier;
415 uint64_t imm = info->imm.value;
416 enum aarch64_modifier_kind kind = info->shifter.kind;
417 int amount = info->shifter.amount;
418 aarch64_field field = {0, 0};
419
420 /* a:b:c:d:e:f:g:h */
421 if (!info->imm.is_fp && aarch64_get_qualifier_esize (opnd0_qualifier) == 8)
422 {
423 /* Either MOVI <Dd>, #<imm>
424 or MOVI <Vd>.2D, #<imm>.
425 <imm> is a 64-bit immediate
426 "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
427 encoded in "a:b:c:d:e:f:g:h". */
428 imm = aarch64_shrink_expanded_imm8 (imm);
429 assert ((int)imm >= 0);
430 }
431 insert_fields (code, imm, 0, 2, FLD_defgh, FLD_abc);
432
433 if (kind == AARCH64_MOD_NONE)
434 return TRUE;
435
436 /* shift amount partially in cmode */
437 assert (kind == AARCH64_MOD_LSL || kind == AARCH64_MOD_MSL);
438 if (kind == AARCH64_MOD_LSL)
439 {
440 /* AARCH64_MOD_LSL: shift zeros. */
441 int esize = aarch64_get_qualifier_esize (opnd0_qualifier);
442 assert (esize == 4 || esize == 2 || esize == 1);
443 /* For 8-bit move immediate, the optional LSL #0 does not require
444 encoding. */
445 if (esize == 1)
446 return TRUE;
447 amount >>= 3;
448 if (esize == 4)
449 gen_sub_field (FLD_cmode, 1, 2, &field); /* per word */
450 else
451 gen_sub_field (FLD_cmode, 1, 1, &field); /* per halfword */
452 }
453 else
454 {
455 /* AARCH64_MOD_MSL: shift ones. */
456 amount >>= 4;
457 gen_sub_field (FLD_cmode, 0, 1, &field); /* per word */
458 }
459 insert_field_2 (&field, code, amount, 0);
460
461 return TRUE;
462 }
463
464 /* Insert fields for an 8-bit floating-point immediate. */
465 bfd_boolean
466 aarch64_ins_fpimm (const aarch64_operand *self, const aarch64_opnd_info *info,
467 aarch64_insn *code,
468 const aarch64_inst *inst ATTRIBUTE_UNUSED,
469 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
470 {
471 insert_all_fields (self, code, info->imm.value);
472 return TRUE;
473 }
474
475 /* Insert 1-bit rotation immediate (#90 or #270). */
476 bfd_boolean
477 aarch64_ins_imm_rotate1 (const aarch64_operand *self,
478 const aarch64_opnd_info *info,
479 aarch64_insn *code, const aarch64_inst *inst,
480 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
481 {
482 uint64_t rot = (info->imm.value - 90) / 180;
483 assert (rot < 2U);
484 insert_field (self->fields[0], code, rot, inst->opcode->mask);
485 return TRUE;
486 }
487
488 /* Insert 2-bit rotation immediate (#0, #90, #180 or #270). */
489 bfd_boolean
490 aarch64_ins_imm_rotate2 (const aarch64_operand *self,
491 const aarch64_opnd_info *info,
492 aarch64_insn *code, const aarch64_inst *inst,
493 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
494 {
495 uint64_t rot = info->imm.value / 90;
496 assert (rot < 4U);
497 insert_field (self->fields[0], code, rot, inst->opcode->mask);
498 return TRUE;
499 }
500
501 /* Insert #<fbits> for the immediate operand in fp fix-point instructions,
502 e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
503 bfd_boolean
504 aarch64_ins_fbits (const aarch64_operand *self, const aarch64_opnd_info *info,
505 aarch64_insn *code,
506 const aarch64_inst *inst ATTRIBUTE_UNUSED,
507 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
508 {
509 insert_field (self->fields[0], code, 64 - info->imm.value, 0);
510 return TRUE;
511 }
512
513 /* Insert arithmetic immediate for e.g. the last operand in
514 SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
515 bfd_boolean
516 aarch64_ins_aimm (const aarch64_operand *self, const aarch64_opnd_info *info,
517 aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED,
518 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
519 {
520 /* shift */
521 aarch64_insn value = info->shifter.amount ? 1 : 0;
522 insert_field (self->fields[0], code, value, 0);
523 /* imm12 (unsigned) */
524 insert_field (self->fields[1], code, info->imm.value, 0);
525 return TRUE;
526 }
527
528 /* Common routine shared by aarch64_ins{,_inv}_limm. INVERT_P says whether
529 the operand should be inverted before encoding. */
530 static bfd_boolean
531 aarch64_ins_limm_1 (const aarch64_operand *self,
532 const aarch64_opnd_info *info, aarch64_insn *code,
533 const aarch64_inst *inst, bfd_boolean invert_p,
534 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
535 {
536 aarch64_insn value;
537 uint64_t imm = info->imm.value;
538 int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
539
540 if (invert_p)
541 imm = ~imm;
542 /* The constraint check should have guaranteed this wouldn't happen. */
543 assert (aarch64_logical_immediate_p (imm, esize, &value));
544
545 insert_fields (code, value, 0, 3, self->fields[2], self->fields[1],
546 self->fields[0]);
547 return TRUE;
548 }
549
550 /* Insert logical/bitmask immediate for e.g. the last operand in
551 ORR <Wd|WSP>, <Wn>, #<imm>. */
552 bfd_boolean
553 aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info,
554 aarch64_insn *code, const aarch64_inst *inst,
555 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
556 {
557 return aarch64_ins_limm_1 (self, info, code, inst,
558 inst->opcode->op == OP_BIC, errors);
559 }
560
561 /* Insert a logical/bitmask immediate for the BIC alias of AND (etc.). */
562 bfd_boolean
563 aarch64_ins_inv_limm (const aarch64_operand *self,
564 const aarch64_opnd_info *info, aarch64_insn *code,
565 const aarch64_inst *inst,
566 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
567 {
568 return aarch64_ins_limm_1 (self, info, code, inst, TRUE, errors);
569 }
570
571 /* Encode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
572 or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
573 bfd_boolean
574 aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info,
575 aarch64_insn *code, const aarch64_inst *inst,
576 aarch64_operand_error *errors)
577 {
578 aarch64_insn value = 0;
579
580 assert (info->idx == 0);
581
582 /* Rt */
583 aarch64_ins_regno (self, info, code, inst, errors);
584 if (inst->opcode->iclass == ldstpair_indexed
585 || inst->opcode->iclass == ldstnapair_offs
586 || inst->opcode->iclass == ldstpair_off
587 || inst->opcode->iclass == loadlit)
588 {
589 /* size */
590 switch (info->qualifier)
591 {
592 case AARCH64_OPND_QLF_S_S: value = 0; break;
593 case AARCH64_OPND_QLF_S_D: value = 1; break;
594 case AARCH64_OPND_QLF_S_Q: value = 2; break;
595 default: assert (0);
596 }
597 insert_field (FLD_ldst_size, code, value, 0);
598 }
599 else
600 {
601 /* opc[1]:size */
602 value = aarch64_get_qualifier_standard_value (info->qualifier);
603 insert_fields (code, value, 0, 2, FLD_ldst_size, FLD_opc1);
604 }
605
606 return TRUE;
607 }
608
609 /* Encode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
610 bfd_boolean
611 aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
612 const aarch64_opnd_info *info, aarch64_insn *code,
613 const aarch64_inst *inst ATTRIBUTE_UNUSED,
614 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
615 {
616 /* Rn */
617 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
618 return TRUE;
619 }
620
621 /* Encode the address operand for e.g.
622 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
623 bfd_boolean
624 aarch64_ins_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
625 const aarch64_opnd_info *info, aarch64_insn *code,
626 const aarch64_inst *inst ATTRIBUTE_UNUSED,
627 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
628 {
629 aarch64_insn S;
630 enum aarch64_modifier_kind kind = info->shifter.kind;
631
632 /* Rn */
633 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
634 /* Rm */
635 insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
636 /* option */
637 if (kind == AARCH64_MOD_LSL)
638 kind = AARCH64_MOD_UXTX; /* Trick to enable the table-driven. */
639 insert_field (FLD_option, code, aarch64_get_operand_modifier_value (kind), 0);
640 /* S */
641 if (info->qualifier != AARCH64_OPND_QLF_S_B)
642 S = info->shifter.amount != 0;
643 else
644 /* For STR <Bt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}},
645 S <amount>
646 0 [absent]
647 1 #0
648 Must be #0 if <extend> is explicitly LSL. */
649 S = info->shifter.operator_present && info->shifter.amount_present;
650 insert_field (FLD_S, code, S, 0);
651
652 return TRUE;
653 }
654
655 /* Encode the address operand for e.g.
656 stlur <Xt>, [<Xn|SP>{, <amount>}]. */
657 bfd_boolean
658 aarch64_ins_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
659 const aarch64_opnd_info *info, aarch64_insn *code,
660 const aarch64_inst *inst ATTRIBUTE_UNUSED,
661 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
662 {
663 /* Rn */
664 insert_field (self->fields[0], code, info->addr.base_regno, 0);
665
666 /* simm9 */
667 int imm = info->addr.offset.imm;
668 insert_field (self->fields[1], code, imm, 0);
669
670 /* writeback */
671 if (info->addr.writeback)
672 {
673 assert (info->addr.preind == 1 && info->addr.postind == 0);
674 insert_field (self->fields[2], code, 1, 0);
675 }
676 return TRUE;
677 }
678
679 /* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>, #<simm>]!. */
680 bfd_boolean
681 aarch64_ins_addr_simm (const aarch64_operand *self,
682 const aarch64_opnd_info *info,
683 aarch64_insn *code,
684 const aarch64_inst *inst ATTRIBUTE_UNUSED,
685 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
686 {
687 int imm;
688
689 /* Rn */
690 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
691 /* simm (imm9 or imm7) */
692 imm = info->addr.offset.imm;
693 if (self->fields[0] == FLD_imm7
694 || info->qualifier == AARCH64_OPND_QLF_imm_tag)
695 /* scaled immediate in ld/st pair instructions.. */
696 imm >>= get_logsz (aarch64_get_qualifier_esize (info->qualifier));
697 insert_field (self->fields[0], code, imm, 0);
698 /* pre/post- index */
699 if (info->addr.writeback)
700 {
701 assert (inst->opcode->iclass != ldst_unscaled
702 && inst->opcode->iclass != ldstnapair_offs
703 && inst->opcode->iclass != ldstpair_off
704 && inst->opcode->iclass != ldst_unpriv);
705 assert (info->addr.preind != info->addr.postind);
706 if (info->addr.preind)
707 insert_field (self->fields[1], code, 1, 0);
708 }
709
710 return TRUE;
711 }
712
713 /* Encode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */
714 bfd_boolean
715 aarch64_ins_addr_simm10 (const aarch64_operand *self,
716 const aarch64_opnd_info *info,
717 aarch64_insn *code,
718 const aarch64_inst *inst ATTRIBUTE_UNUSED,
719 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
720 {
721 int imm;
722
723 /* Rn */
724 insert_field (self->fields[0], code, info->addr.base_regno, 0);
725 /* simm10 */
726 imm = info->addr.offset.imm >> 3;
727 insert_field (self->fields[1], code, imm >> 9, 0);
728 insert_field (self->fields[2], code, imm, 0);
729 /* writeback */
730 if (info->addr.writeback)
731 {
732 assert (info->addr.preind == 1 && info->addr.postind == 0);
733 insert_field (self->fields[3], code, 1, 0);
734 }
735 return TRUE;
736 }
737
738 /* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]. */
739 bfd_boolean
740 aarch64_ins_addr_uimm12 (const aarch64_operand *self,
741 const aarch64_opnd_info *info,
742 aarch64_insn *code,
743 const aarch64_inst *inst ATTRIBUTE_UNUSED,
744 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
745 {
746 int shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
747
748 /* Rn */
749 insert_field (self->fields[0], code, info->addr.base_regno, 0);
750 /* uimm12 */
751 insert_field (self->fields[1], code,info->addr.offset.imm >> shift, 0);
752 return TRUE;
753 }
754
755 /* Encode the address operand for e.g.
756 LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
757 bfd_boolean
758 aarch64_ins_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
759 const aarch64_opnd_info *info, aarch64_insn *code,
760 const aarch64_inst *inst ATTRIBUTE_UNUSED,
761 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
762 {
763 /* Rn */
764 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
765 /* Rm | #<amount> */
766 if (info->addr.offset.is_reg)
767 insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
768 else
769 insert_field (FLD_Rm, code, 0x1f, 0);
770 return TRUE;
771 }
772
773 /* Encode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
774 bfd_boolean
775 aarch64_ins_cond (const aarch64_operand *self ATTRIBUTE_UNUSED,
776 const aarch64_opnd_info *info, aarch64_insn *code,
777 const aarch64_inst *inst ATTRIBUTE_UNUSED,
778 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
779 {
780 /* cond */
781 insert_field (FLD_cond, code, info->cond->value, 0);
782 return TRUE;
783 }
784
785 /* Encode the system register operand for e.g. MRS <Xt>, <systemreg>. */
786 bfd_boolean
787 aarch64_ins_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
788 const aarch64_opnd_info *info, aarch64_insn *code,
789 const aarch64_inst *inst,
790 aarch64_operand_error *detail ATTRIBUTE_UNUSED)
791 {
792 /* If a system instruction check if we have any restrictions on which
793 registers it can use. */
794 if (inst->opcode->iclass == ic_system)
795 {
796 uint64_t opcode_flags
797 = inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE);
798 uint32_t sysreg_flags
799 = info->sysreg.flags & (F_REG_READ | F_REG_WRITE);
800
801 /* Check to see if it's read-only, else check if it's write only.
802 if it's both or unspecified don't care. */
803 if (opcode_flags == F_SYS_READ
804 && sysreg_flags
805 && sysreg_flags != F_REG_READ)
806 {
807 detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
808 detail->error = _("specified register cannot be read from");
809 detail->index = info->idx;
810 detail->non_fatal = TRUE;
811 }
812 else if (opcode_flags == F_SYS_WRITE
813 && sysreg_flags
814 && sysreg_flags != F_REG_WRITE)
815 {
816 detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
817 detail->error = _("specified register cannot be written to");
818 detail->index = info->idx;
819 detail->non_fatal = TRUE;
820 }
821 }
822 /* op0:op1:CRn:CRm:op2 */
823 insert_fields (code, info->sysreg.value, inst->opcode->mask, 5,
824 FLD_op2, FLD_CRm, FLD_CRn, FLD_op1, FLD_op0);
825 return TRUE;
826 }
827
828 /* Encode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
829 bfd_boolean
830 aarch64_ins_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
831 const aarch64_opnd_info *info, aarch64_insn *code,
832 const aarch64_inst *inst ATTRIBUTE_UNUSED,
833 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
834 {
835 /* op1:op2 */
836 insert_fields (code, info->pstatefield, inst->opcode->mask, 2,
837 FLD_op2, FLD_op1);
838 return TRUE;
839 }
840
841 /* Encode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
842 bfd_boolean
843 aarch64_ins_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
844 const aarch64_opnd_info *info, aarch64_insn *code,
845 const aarch64_inst *inst ATTRIBUTE_UNUSED,
846 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
847 {
848 /* op1:CRn:CRm:op2 */
849 insert_fields (code, info->sysins_op->value, inst->opcode->mask, 4,
850 FLD_op2, FLD_CRm, FLD_CRn, FLD_op1);
851 return TRUE;
852 }
853
854 /* Encode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
855
856 bfd_boolean
857 aarch64_ins_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
858 const aarch64_opnd_info *info, aarch64_insn *code,
859 const aarch64_inst *inst ATTRIBUTE_UNUSED,
860 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
861 {
862 /* CRm */
863 insert_field (FLD_CRm, code, info->barrier->value, 0);
864 return TRUE;
865 }
866
867 /* Encode the prefetch operation option operand for e.g.
868 PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
869
870 bfd_boolean
871 aarch64_ins_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
872 const aarch64_opnd_info *info, aarch64_insn *code,
873 const aarch64_inst *inst ATTRIBUTE_UNUSED,
874 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
875 {
876 /* prfop in Rt */
877 insert_field (FLD_Rt, code, info->prfop->value, 0);
878 return TRUE;
879 }
880
881 /* Encode the hint number for instructions that alias HINT but take an
882 operand. */
883
884 bfd_boolean
885 aarch64_ins_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
886 const aarch64_opnd_info *info, aarch64_insn *code,
887 const aarch64_inst *inst ATTRIBUTE_UNUSED,
888 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
889 {
890 /* CRm:op2. */
891 insert_fields (code, info->hint_option->value, 0, 2, FLD_op2, FLD_CRm);
892 return TRUE;
893 }
894
895 /* Encode the extended register operand for e.g.
896 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
897 bfd_boolean
898 aarch64_ins_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
899 const aarch64_opnd_info *info, aarch64_insn *code,
900 const aarch64_inst *inst ATTRIBUTE_UNUSED,
901 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
902 {
903 enum aarch64_modifier_kind kind;
904
905 /* Rm */
906 insert_field (FLD_Rm, code, info->reg.regno, 0);
907 /* option */
908 kind = info->shifter.kind;
909 if (kind == AARCH64_MOD_LSL)
910 kind = info->qualifier == AARCH64_OPND_QLF_W
911 ? AARCH64_MOD_UXTW : AARCH64_MOD_UXTX;
912 insert_field (FLD_option, code, aarch64_get_operand_modifier_value (kind), 0);
913 /* imm3 */
914 insert_field (FLD_imm3, code, info->shifter.amount, 0);
915
916 return TRUE;
917 }
918
919 /* Encode the shifted register operand for e.g.
920 SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
921 bfd_boolean
922 aarch64_ins_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
923 const aarch64_opnd_info *info, aarch64_insn *code,
924 const aarch64_inst *inst ATTRIBUTE_UNUSED,
925 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
926 {
927 /* Rm */
928 insert_field (FLD_Rm, code, info->reg.regno, 0);
929 /* shift */
930 insert_field (FLD_shift, code,
931 aarch64_get_operand_modifier_value (info->shifter.kind), 0);
932 /* imm6 */
933 insert_field (FLD_imm6, code, info->shifter.amount, 0);
934
935 return TRUE;
936 }
937
938 /* Encode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
939 where <simm4> is a 4-bit signed value and where <factor> is 1 plus
940 SELF's operand-dependent value. fields[0] specifies the field that
941 holds <base>. <simm4> is encoded in the SVE_imm4 field. */
942 bfd_boolean
943 aarch64_ins_sve_addr_ri_s4xvl (const aarch64_operand *self,
944 const aarch64_opnd_info *info,
945 aarch64_insn *code,
946 const aarch64_inst *inst ATTRIBUTE_UNUSED,
947 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
948 {
949 int factor = 1 + get_operand_specific_data (self);
950 insert_field (self->fields[0], code, info->addr.base_regno, 0);
951 insert_field (FLD_SVE_imm4, code, info->addr.offset.imm / factor, 0);
952 return TRUE;
953 }
954
955 /* Encode an SVE address [<base>, #<simm6>*<factor>, MUL VL],
956 where <simm6> is a 6-bit signed value and where <factor> is 1 plus
957 SELF's operand-dependent value. fields[0] specifies the field that
958 holds <base>. <simm6> is encoded in the SVE_imm6 field. */
959 bfd_boolean
960 aarch64_ins_sve_addr_ri_s6xvl (const aarch64_operand *self,
961 const aarch64_opnd_info *info,
962 aarch64_insn *code,
963 const aarch64_inst *inst ATTRIBUTE_UNUSED,
964 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
965 {
966 int factor = 1 + get_operand_specific_data (self);
967 insert_field (self->fields[0], code, info->addr.base_regno, 0);
968 insert_field (FLD_SVE_imm6, code, info->addr.offset.imm / factor, 0);
969 return TRUE;
970 }
971
972 /* Encode an SVE address [<base>, #<simm9>*<factor>, MUL VL],
973 where <simm9> is a 9-bit signed value and where <factor> is 1 plus
974 SELF's operand-dependent value. fields[0] specifies the field that
975 holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6
976 and imm3 fields, with imm3 being the less-significant part. */
977 bfd_boolean
978 aarch64_ins_sve_addr_ri_s9xvl (const aarch64_operand *self,
979 const aarch64_opnd_info *info,
980 aarch64_insn *code,
981 const aarch64_inst *inst ATTRIBUTE_UNUSED,
982 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
983 {
984 int factor = 1 + get_operand_specific_data (self);
985 insert_field (self->fields[0], code, info->addr.base_regno, 0);
986 insert_fields (code, info->addr.offset.imm / factor, 0,
987 2, FLD_imm3, FLD_SVE_imm6);
988 return TRUE;
989 }
990
991 /* Encode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4>
992 is a 4-bit signed number and where <shift> is SELF's operand-dependent
993 value. fields[0] specifies the base register field. */
994 bfd_boolean
995 aarch64_ins_sve_addr_ri_s4 (const aarch64_operand *self,
996 const aarch64_opnd_info *info, aarch64_insn *code,
997 const aarch64_inst *inst ATTRIBUTE_UNUSED,
998 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
999 {
1000 int factor = 1 << get_operand_specific_data (self);
1001 insert_field (self->fields[0], code, info->addr.base_regno, 0);
1002 insert_field (FLD_SVE_imm4, code, info->addr.offset.imm / factor, 0);
1003 return TRUE;
1004 }
1005
1006 /* Encode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
1007 is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
1008 value. fields[0] specifies the base register field. */
1009 bfd_boolean
1010 aarch64_ins_sve_addr_ri_u6 (const aarch64_operand *self,
1011 const aarch64_opnd_info *info, aarch64_insn *code,
1012 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1013 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1014 {
1015 int factor = 1 << get_operand_specific_data (self);
1016 insert_field (self->fields[0], code, info->addr.base_regno, 0);
1017 insert_field (FLD_SVE_imm6, code, info->addr.offset.imm / factor, 0);
1018 return TRUE;
1019 }
1020
1021 /* Encode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift>
1022 is SELF's operand-dependent value. fields[0] specifies the base
1023 register field and fields[1] specifies the offset register field. */
1024 bfd_boolean
1025 aarch64_ins_sve_addr_rr_lsl (const aarch64_operand *self,
1026 const aarch64_opnd_info *info, aarch64_insn *code,
1027 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1028 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1029 {
1030 insert_field (self->fields[0], code, info->addr.base_regno, 0);
1031 insert_field (self->fields[1], code, info->addr.offset.regno, 0);
1032 return TRUE;
1033 }
1034
1035 /* Encode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where
1036 <shift> is SELF's operand-dependent value. fields[0] specifies the
1037 base register field, fields[1] specifies the offset register field and
1038 fields[2] is a single-bit field that selects SXTW over UXTW. */
1039 bfd_boolean
1040 aarch64_ins_sve_addr_rz_xtw (const aarch64_operand *self,
1041 const aarch64_opnd_info *info, aarch64_insn *code,
1042 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1043 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1044 {
1045 insert_field (self->fields[0], code, info->addr.base_regno, 0);
1046 insert_field (self->fields[1], code, info->addr.offset.regno, 0);
1047 if (info->shifter.kind == AARCH64_MOD_UXTW)
1048 insert_field (self->fields[2], code, 0, 0);
1049 else
1050 insert_field (self->fields[2], code, 1, 0);
1051 return TRUE;
1052 }
1053
1054 /* Encode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a
1055 5-bit unsigned number and where <shift> is SELF's operand-dependent value.
1056 fields[0] specifies the base register field. */
1057 bfd_boolean
1058 aarch64_ins_sve_addr_zi_u5 (const aarch64_operand *self,
1059 const aarch64_opnd_info *info, aarch64_insn *code,
1060 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1061 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1062 {
1063 int factor = 1 << get_operand_specific_data (self);
1064 insert_field (self->fields[0], code, info->addr.base_regno, 0);
1065 insert_field (FLD_imm5, code, info->addr.offset.imm / factor, 0);
1066 return TRUE;
1067 }
1068
1069 /* Encode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}],
1070 where <modifier> is fixed by the instruction and where <msz> is a
1071 2-bit unsigned number. fields[0] specifies the base register field
1072 and fields[1] specifies the offset register field. */
1073 static bfd_boolean
1074 aarch64_ext_sve_addr_zz (const aarch64_operand *self,
1075 const aarch64_opnd_info *info, aarch64_insn *code,
1076 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1077 {
1078 insert_field (self->fields[0], code, info->addr.base_regno, 0);
1079 insert_field (self->fields[1], code, info->addr.offset.regno, 0);
1080 insert_field (FLD_SVE_msz, code, info->shifter.amount, 0);
1081 return TRUE;
1082 }
1083
1084 /* Encode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where
1085 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1086 field and fields[1] specifies the offset register field. */
1087 bfd_boolean
1088 aarch64_ins_sve_addr_zz_lsl (const aarch64_operand *self,
1089 const aarch64_opnd_info *info, aarch64_insn *code,
1090 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1091 aarch64_operand_error *errors)
1092 {
1093 return aarch64_ext_sve_addr_zz (self, info, code, errors);
1094 }
1095
1096 /* Encode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where
1097 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1098 field and fields[1] specifies the offset register field. */
1099 bfd_boolean
1100 aarch64_ins_sve_addr_zz_sxtw (const aarch64_operand *self,
1101 const aarch64_opnd_info *info,
1102 aarch64_insn *code,
1103 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1104 aarch64_operand_error *errors)
1105 {
1106 return aarch64_ext_sve_addr_zz (self, info, code, errors);
1107 }
1108
1109 /* Encode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where
1110 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1111 field and fields[1] specifies the offset register field. */
1112 bfd_boolean
1113 aarch64_ins_sve_addr_zz_uxtw (const aarch64_operand *self,
1114 const aarch64_opnd_info *info,
1115 aarch64_insn *code,
1116 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1117 aarch64_operand_error *errors)
1118 {
1119 return aarch64_ext_sve_addr_zz (self, info, code, errors);
1120 }
1121
1122 /* Encode an SVE ADD/SUB immediate. */
1123 bfd_boolean
1124 aarch64_ins_sve_aimm (const aarch64_operand *self,
1125 const aarch64_opnd_info *info, aarch64_insn *code,
1126 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1127 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1128 {
1129 if (info->shifter.amount == 8)
1130 insert_all_fields (self, code, (info->imm.value & 0xff) | 256);
1131 else if (info->imm.value != 0 && (info->imm.value & 0xff) == 0)
1132 insert_all_fields (self, code, ((info->imm.value / 256) & 0xff) | 256);
1133 else
1134 insert_all_fields (self, code, info->imm.value & 0xff);
1135 return TRUE;
1136 }
1137
1138 /* Encode an SVE CPY/DUP immediate. */
1139 bfd_boolean
1140 aarch64_ins_sve_asimm (const aarch64_operand *self,
1141 const aarch64_opnd_info *info, aarch64_insn *code,
1142 const aarch64_inst *inst,
1143 aarch64_operand_error *errors)
1144 {
1145 return aarch64_ins_sve_aimm (self, info, code, inst, errors);
1146 }
1147
1148 /* Encode Zn[MM], where MM has a 7-bit triangular encoding. The fields
1149 array specifies which field to use for Zn. MM is encoded in the
1150 concatenation of imm5 and SVE_tszh, with imm5 being the less
1151 significant part. */
1152 bfd_boolean
1153 aarch64_ins_sve_index (const aarch64_operand *self,
1154 const aarch64_opnd_info *info, aarch64_insn *code,
1155 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1156 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1157 {
1158 unsigned int esize = aarch64_get_qualifier_esize (info->qualifier);
1159 insert_field (self->fields[0], code, info->reglane.regno, 0);
1160 insert_fields (code, (info->reglane.index * 2 + 1) * esize, 0,
1161 2, FLD_imm5, FLD_SVE_tszh);
1162 return TRUE;
1163 }
1164
1165 /* Encode a logical/bitmask immediate for the MOV alias of SVE DUPM. */
1166 bfd_boolean
1167 aarch64_ins_sve_limm_mov (const aarch64_operand *self,
1168 const aarch64_opnd_info *info, aarch64_insn *code,
1169 const aarch64_inst *inst,
1170 aarch64_operand_error *errors)
1171 {
1172 return aarch64_ins_limm (self, info, code, inst, errors);
1173 }
1174
1175 /* Encode Zn[MM], where Zn occupies the least-significant part of the field
1176 and where MM occupies the most-significant part. The operand-dependent
1177 value specifies the number of bits in Zn. */
1178 bfd_boolean
1179 aarch64_ins_sve_quad_index (const aarch64_operand *self,
1180 const aarch64_opnd_info *info, aarch64_insn *code,
1181 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1182 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1183 {
1184 unsigned int reg_bits = get_operand_specific_data (self);
1185 assert (info->reglane.regno < (1U << reg_bits));
1186 unsigned int val = (info->reglane.index << reg_bits) + info->reglane.regno;
1187 insert_all_fields (self, code, val);
1188 return TRUE;
1189 }
1190
1191 /* Encode {Zn.<T> - Zm.<T>}. The fields array specifies which field
1192 to use for Zn. */
1193 bfd_boolean
1194 aarch64_ins_sve_reglist (const aarch64_operand *self,
1195 const aarch64_opnd_info *info, aarch64_insn *code,
1196 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1197 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1198 {
1199 insert_field (self->fields[0], code, info->reglist.first_regno, 0);
1200 return TRUE;
1201 }
1202
1203 /* Encode <pattern>{, MUL #<amount>}. The fields array specifies which
1204 fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
1205 field. */
1206 bfd_boolean
1207 aarch64_ins_sve_scale (const aarch64_operand *self,
1208 const aarch64_opnd_info *info, aarch64_insn *code,
1209 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1210 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1211 {
1212 insert_all_fields (self, code, info->imm.value);
1213 insert_field (FLD_SVE_imm4, code, info->shifter.amount - 1, 0);
1214 return TRUE;
1215 }
1216
1217 /* Encode an SVE shift left immediate. */
1218 bfd_boolean
1219 aarch64_ins_sve_shlimm (const aarch64_operand *self,
1220 const aarch64_opnd_info *info, aarch64_insn *code,
1221 const aarch64_inst *inst,
1222 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1223 {
1224 const aarch64_opnd_info *prev_operand;
1225 unsigned int esize;
1226
1227 assert (info->idx > 0);
1228 prev_operand = &inst->operands[info->idx - 1];
1229 esize = aarch64_get_qualifier_esize (prev_operand->qualifier);
1230 insert_all_fields (self, code, 8 * esize + info->imm.value);
1231 return TRUE;
1232 }
1233
1234 /* Encode an SVE shift right immediate. */
1235 bfd_boolean
1236 aarch64_ins_sve_shrimm (const aarch64_operand *self,
1237 const aarch64_opnd_info *info, aarch64_insn *code,
1238 const aarch64_inst *inst,
1239 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1240 {
1241 const aarch64_opnd_info *prev_operand;
1242 unsigned int esize;
1243
1244 unsigned int opnd_backshift = get_operand_specific_data (self);
1245 assert (info->idx >= (int)opnd_backshift);
1246 prev_operand = &inst->operands[info->idx - opnd_backshift];
1247 esize = aarch64_get_qualifier_esize (prev_operand->qualifier);
1248 insert_all_fields (self, code, 16 * esize - info->imm.value);
1249 return TRUE;
1250 }
1251
1252 /* Encode a single-bit immediate that selects between #0.5 and #1.0.
1253 The fields array specifies which field to use. */
1254 bfd_boolean
1255 aarch64_ins_sve_float_half_one (const aarch64_operand *self,
1256 const aarch64_opnd_info *info,
1257 aarch64_insn *code,
1258 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1259 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1260 {
1261 if (info->imm.value == 0x3f000000)
1262 insert_field (self->fields[0], code, 0, 0);
1263 else
1264 insert_field (self->fields[0], code, 1, 0);
1265 return TRUE;
1266 }
1267
1268 /* Encode a single-bit immediate that selects between #0.5 and #2.0.
1269 The fields array specifies which field to use. */
1270 bfd_boolean
1271 aarch64_ins_sve_float_half_two (const aarch64_operand *self,
1272 const aarch64_opnd_info *info,
1273 aarch64_insn *code,
1274 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1275 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1276 {
1277 if (info->imm.value == 0x3f000000)
1278 insert_field (self->fields[0], code, 0, 0);
1279 else
1280 insert_field (self->fields[0], code, 1, 0);
1281 return TRUE;
1282 }
1283
1284 /* Encode a single-bit immediate that selects between #0.0 and #1.0.
1285 The fields array specifies which field to use. */
1286 bfd_boolean
1287 aarch64_ins_sve_float_zero_one (const aarch64_operand *self,
1288 const aarch64_opnd_info *info,
1289 aarch64_insn *code,
1290 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1291 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1292 {
1293 if (info->imm.value == 0)
1294 insert_field (self->fields[0], code, 0, 0);
1295 else
1296 insert_field (self->fields[0], code, 1, 0);
1297 return TRUE;
1298 }
1299
1300 /* Miscellaneous encoding functions. */
1301
1302 /* Encode size[0], i.e. bit 22, for
1303 e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1304
1305 static void
1306 encode_asimd_fcvt (aarch64_inst *inst)
1307 {
1308 aarch64_insn value;
1309 aarch64_field field = {0, 0};
1310 enum aarch64_opnd_qualifier qualifier;
1311
1312 switch (inst->opcode->op)
1313 {
1314 case OP_FCVTN:
1315 case OP_FCVTN2:
1316 /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1317 qualifier = inst->operands[1].qualifier;
1318 break;
1319 case OP_FCVTL:
1320 case OP_FCVTL2:
1321 /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
1322 qualifier = inst->operands[0].qualifier;
1323 break;
1324 default:
1325 assert (0);
1326 }
1327 assert (qualifier == AARCH64_OPND_QLF_V_4S
1328 || qualifier == AARCH64_OPND_QLF_V_2D);
1329 value = (qualifier == AARCH64_OPND_QLF_V_4S) ? 0 : 1;
1330 gen_sub_field (FLD_size, 0, 1, &field);
1331 insert_field_2 (&field, &inst->value, value, 0);
1332 }
1333
1334 /* Encode size[0], i.e. bit 22, for
1335 e.g. FCVTXN <Vb><d>, <Va><n>. */
1336
1337 static void
1338 encode_asisd_fcvtxn (aarch64_inst *inst)
1339 {
1340 aarch64_insn val = 1;
1341 aarch64_field field = {0, 0};
1342 assert (inst->operands[0].qualifier == AARCH64_OPND_QLF_S_S);
1343 gen_sub_field (FLD_size, 0, 1, &field);
1344 insert_field_2 (&field, &inst->value, val, 0);
1345 }
1346
1347 /* Encode the 'opc' field for e.g. FCVT <Dd>, <Sn>. */
1348 static void
1349 encode_fcvt (aarch64_inst *inst)
1350 {
1351 aarch64_insn val;
1352 const aarch64_field field = {15, 2};
1353
1354 /* opc dstsize */
1355 switch (inst->operands[0].qualifier)
1356 {
1357 case AARCH64_OPND_QLF_S_S: val = 0; break;
1358 case AARCH64_OPND_QLF_S_D: val = 1; break;
1359 case AARCH64_OPND_QLF_S_H: val = 3; break;
1360 default: abort ();
1361 }
1362 insert_field_2 (&field, &inst->value, val, 0);
1363
1364 return;
1365 }
1366
1367 /* Return the index in qualifiers_list that INST is using. Should only
1368 be called once the qualifiers are known to be valid. */
1369
1370 static int
1371 aarch64_get_variant (struct aarch64_inst *inst)
1372 {
1373 int i, nops, variant;
1374
1375 nops = aarch64_num_of_operands (inst->opcode);
1376 for (variant = 0; variant < AARCH64_MAX_QLF_SEQ_NUM; ++variant)
1377 {
1378 for (i = 0; i < nops; ++i)
1379 if (inst->opcode->qualifiers_list[variant][i]
1380 != inst->operands[i].qualifier)
1381 break;
1382 if (i == nops)
1383 return variant;
1384 }
1385 abort ();
1386 }
1387
1388 /* Do miscellaneous encodings that are not common enough to be driven by
1389 flags. */
1390
1391 static void
1392 do_misc_encoding (aarch64_inst *inst)
1393 {
1394 unsigned int value;
1395
1396 switch (inst->opcode->op)
1397 {
1398 case OP_FCVT:
1399 encode_fcvt (inst);
1400 break;
1401 case OP_FCVTN:
1402 case OP_FCVTN2:
1403 case OP_FCVTL:
1404 case OP_FCVTL2:
1405 encode_asimd_fcvt (inst);
1406 break;
1407 case OP_FCVTXN_S:
1408 encode_asisd_fcvtxn (inst);
1409 break;
1410 case OP_MOV_P_P:
1411 case OP_MOVS_P_P:
1412 /* Copy Pn to Pm and Pg. */
1413 value = extract_field (FLD_SVE_Pn, inst->value, 0);
1414 insert_field (FLD_SVE_Pm, &inst->value, value, 0);
1415 insert_field (FLD_SVE_Pg4_10, &inst->value, value, 0);
1416 break;
1417 case OP_MOV_Z_P_Z:
1418 /* Copy Zd to Zm. */
1419 value = extract_field (FLD_SVE_Zd, inst->value, 0);
1420 insert_field (FLD_SVE_Zm_16, &inst->value, value, 0);
1421 break;
1422 case OP_MOV_Z_V:
1423 /* Fill in the zero immediate. */
1424 insert_fields (&inst->value, 1 << aarch64_get_variant (inst), 0,
1425 2, FLD_imm5, FLD_SVE_tszh);
1426 break;
1427 case OP_MOV_Z_Z:
1428 /* Copy Zn to Zm. */
1429 value = extract_field (FLD_SVE_Zn, inst->value, 0);
1430 insert_field (FLD_SVE_Zm_16, &inst->value, value, 0);
1431 break;
1432 case OP_MOV_Z_Zi:
1433 break;
1434 case OP_MOVM_P_P_P:
1435 /* Copy Pd to Pm. */
1436 value = extract_field (FLD_SVE_Pd, inst->value, 0);
1437 insert_field (FLD_SVE_Pm, &inst->value, value, 0);
1438 break;
1439 case OP_MOVZS_P_P_P:
1440 case OP_MOVZ_P_P_P:
1441 /* Copy Pn to Pm. */
1442 value = extract_field (FLD_SVE_Pn, inst->value, 0);
1443 insert_field (FLD_SVE_Pm, &inst->value, value, 0);
1444 break;
1445 case OP_NOTS_P_P_P_Z:
1446 case OP_NOT_P_P_P_Z:
1447 /* Copy Pg to Pm. */
1448 value = extract_field (FLD_SVE_Pg4_10, inst->value, 0);
1449 insert_field (FLD_SVE_Pm, &inst->value, value, 0);
1450 break;
1451 default: break;
1452 }
1453 }
1454
1455 /* Encode the 'size' and 'Q' field for e.g. SHADD. */
1456 static void
1457 encode_sizeq (aarch64_inst *inst)
1458 {
1459 aarch64_insn sizeq;
1460 enum aarch64_field_kind kind;
1461 int idx;
1462
1463 /* Get the index of the operand whose information we are going to use
1464 to encode the size and Q fields.
1465 This is deduced from the possible valid qualifier lists. */
1466 idx = aarch64_select_operand_for_sizeq_field_coding (inst->opcode);
1467 DEBUG_TRACE ("idx: %d; qualifier: %s", idx,
1468 aarch64_get_qualifier_name (inst->operands[idx].qualifier));
1469 sizeq = aarch64_get_qualifier_standard_value (inst->operands[idx].qualifier);
1470 /* Q */
1471 insert_field (FLD_Q, &inst->value, sizeq & 0x1, inst->opcode->mask);
1472 /* size */
1473 if (inst->opcode->iclass == asisdlse
1474 || inst->opcode->iclass == asisdlsep
1475 || inst->opcode->iclass == asisdlso
1476 || inst->opcode->iclass == asisdlsop)
1477 kind = FLD_vldst_size;
1478 else
1479 kind = FLD_size;
1480 insert_field (kind, &inst->value, (sizeq >> 1) & 0x3, inst->opcode->mask);
1481 }
1482
1483 /* Opcodes that have fields shared by multiple operands are usually flagged
1484 with flags. In this function, we detect such flags and use the
1485 information in one of the related operands to do the encoding. The 'one'
1486 operand is not any operand but one of the operands that has the enough
1487 information for such an encoding. */
1488
1489 static void
1490 do_special_encoding (struct aarch64_inst *inst)
1491 {
1492 int idx;
1493 aarch64_insn value = 0;
1494
1495 DEBUG_TRACE ("enter with coding 0x%x", (uint32_t) inst->value);
1496
1497 /* Condition for truly conditional executed instructions, e.g. b.cond. */
1498 if (inst->opcode->flags & F_COND)
1499 {
1500 insert_field (FLD_cond2, &inst->value, inst->cond->value, 0);
1501 }
1502 if (inst->opcode->flags & F_SF)
1503 {
1504 idx = select_operand_for_sf_field_coding (inst->opcode);
1505 value = (inst->operands[idx].qualifier == AARCH64_OPND_QLF_X
1506 || inst->operands[idx].qualifier == AARCH64_OPND_QLF_SP)
1507 ? 1 : 0;
1508 insert_field (FLD_sf, &inst->value, value, 0);
1509 if (inst->opcode->flags & F_N)
1510 insert_field (FLD_N, &inst->value, value, inst->opcode->mask);
1511 }
1512 if (inst->opcode->flags & F_LSE_SZ)
1513 {
1514 idx = select_operand_for_sf_field_coding (inst->opcode);
1515 value = (inst->operands[idx].qualifier == AARCH64_OPND_QLF_X
1516 || inst->operands[idx].qualifier == AARCH64_OPND_QLF_SP)
1517 ? 1 : 0;
1518 insert_field (FLD_lse_sz, &inst->value, value, 0);
1519 }
1520 if (inst->opcode->flags & F_SIZEQ)
1521 encode_sizeq (inst);
1522 if (inst->opcode->flags & F_FPTYPE)
1523 {
1524 idx = select_operand_for_fptype_field_coding (inst->opcode);
1525 switch (inst->operands[idx].qualifier)
1526 {
1527 case AARCH64_OPND_QLF_S_S: value = 0; break;
1528 case AARCH64_OPND_QLF_S_D: value = 1; break;
1529 case AARCH64_OPND_QLF_S_H: value = 3; break;
1530 default: assert (0);
1531 }
1532 insert_field (FLD_type, &inst->value, value, 0);
1533 }
1534 if (inst->opcode->flags & F_SSIZE)
1535 {
1536 enum aarch64_opnd_qualifier qualifier;
1537 idx = select_operand_for_scalar_size_field_coding (inst->opcode);
1538 qualifier = inst->operands[idx].qualifier;
1539 assert (qualifier >= AARCH64_OPND_QLF_S_B
1540 && qualifier <= AARCH64_OPND_QLF_S_Q);
1541 value = aarch64_get_qualifier_standard_value (qualifier);
1542 insert_field (FLD_size, &inst->value, value, inst->opcode->mask);
1543 }
1544 if (inst->opcode->flags & F_T)
1545 {
1546 int num; /* num of consecutive '0's on the right side of imm5<3:0>. */
1547 aarch64_field field = {0, 0};
1548 enum aarch64_opnd_qualifier qualifier;
1549
1550 idx = 0;
1551 qualifier = inst->operands[idx].qualifier;
1552 assert (aarch64_get_operand_class (inst->opcode->operands[0])
1553 == AARCH64_OPND_CLASS_SIMD_REG
1554 && qualifier >= AARCH64_OPND_QLF_V_8B
1555 && qualifier <= AARCH64_OPND_QLF_V_2D);
1556 /* imm5<3:0> q <t>
1557 0000 x reserved
1558 xxx1 0 8b
1559 xxx1 1 16b
1560 xx10 0 4h
1561 xx10 1 8h
1562 x100 0 2s
1563 x100 1 4s
1564 1000 0 reserved
1565 1000 1 2d */
1566 value = aarch64_get_qualifier_standard_value (qualifier);
1567 insert_field (FLD_Q, &inst->value, value & 0x1, inst->opcode->mask);
1568 num = (int) value >> 1;
1569 assert (num >= 0 && num <= 3);
1570 gen_sub_field (FLD_imm5, 0, num + 1, &field);
1571 insert_field_2 (&field, &inst->value, 1 << num, inst->opcode->mask);
1572 }
1573 if (inst->opcode->flags & F_GPRSIZE_IN_Q)
1574 {
1575 /* Use Rt to encode in the case of e.g.
1576 STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
1577 enum aarch64_opnd_qualifier qualifier;
1578 idx = aarch64_operand_index (inst->opcode->operands, AARCH64_OPND_Rt);
1579 if (idx == -1)
1580 /* Otherwise use the result operand, which has to be a integer
1581 register. */
1582 idx = 0;
1583 assert (idx == 0 || idx == 1);
1584 assert (aarch64_get_operand_class (inst->opcode->operands[idx])
1585 == AARCH64_OPND_CLASS_INT_REG);
1586 qualifier = inst->operands[idx].qualifier;
1587 insert_field (FLD_Q, &inst->value,
1588 aarch64_get_qualifier_standard_value (qualifier), 0);
1589 }
1590 if (inst->opcode->flags & F_LDS_SIZE)
1591 {
1592 /* e.g. LDRSB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1593 enum aarch64_opnd_qualifier qualifier;
1594 aarch64_field field = {0, 0};
1595 assert (aarch64_get_operand_class (inst->opcode->operands[0])
1596 == AARCH64_OPND_CLASS_INT_REG);
1597 gen_sub_field (FLD_opc, 0, 1, &field);
1598 qualifier = inst->operands[0].qualifier;
1599 insert_field_2 (&field, &inst->value,
1600 1 - aarch64_get_qualifier_standard_value (qualifier), 0);
1601 }
1602 /* Miscellaneous encoding as the last step. */
1603 if (inst->opcode->flags & F_MISC)
1604 do_misc_encoding (inst);
1605
1606 DEBUG_TRACE ("exit with coding 0x%x", (uint32_t) inst->value);
1607 }
1608
1609 /* Some instructions (including all SVE ones) use the instruction class
1610 to describe how a qualifiers_list index is represented in the instruction
1611 encoding. If INST is such an instruction, encode the chosen qualifier
1612 variant. */
1613
1614 static void
1615 aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
1616 {
1617 int variant = 0;
1618 switch (inst->opcode->iclass)
1619 {
1620 case sve_cpy:
1621 insert_fields (&inst->value, aarch64_get_variant (inst),
1622 0, 2, FLD_SVE_M_14, FLD_size);
1623 break;
1624
1625 case sve_index:
1626 case sve_shift_pred:
1627 case sve_shift_unpred:
1628 case sve_shift_tsz_hsd:
1629 /* For indices and shift amounts, the variant is encoded as
1630 part of the immediate. */
1631 break;
1632
1633 case sve_limm:
1634 /* For sve_limm, the .B, .H, and .S forms are just a convenience
1635 and depend on the immediate. They don't have a separate
1636 encoding. */
1637 break;
1638
1639 case sve_misc:
1640 /* sve_misc instructions have only a single variant. */
1641 break;
1642
1643 case sve_movprfx:
1644 insert_fields (&inst->value, aarch64_get_variant (inst),
1645 0, 2, FLD_SVE_M_16, FLD_size);
1646 break;
1647
1648 case sve_pred_zm:
1649 insert_field (FLD_SVE_M_4, &inst->value, aarch64_get_variant (inst), 0);
1650 break;
1651
1652 case sve_size_bhs:
1653 case sve_size_bhsd:
1654 insert_field (FLD_size, &inst->value, aarch64_get_variant (inst), 0);
1655 break;
1656
1657 case sve_size_hsd:
1658 insert_field (FLD_size, &inst->value, aarch64_get_variant (inst) + 1, 0);
1659 break;
1660
1661 case sve_size_bh:
1662 case sve_size_sd:
1663 insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0);
1664 break;
1665
1666 case sve_size_sd2:
1667 insert_field (FLD_SVE_sz2, &inst->value, aarch64_get_variant (inst), 0);
1668 break;
1669
1670 case sve_size_hsd2:
1671 insert_field (FLD_SVE_size, &inst->value,
1672 aarch64_get_variant (inst) + 1, 0);
1673 break;
1674
1675 case sve_size_013:
1676 variant = aarch64_get_variant (inst);
1677 if (variant == 2)
1678 variant = 3;
1679 insert_field (FLD_size, &inst->value, variant, 0);
1680 break;
1681
1682 default:
1683 break;
1684 }
1685 }
1686
1687 /* Converters converting an alias opcode instruction to its real form. */
1688
1689 /* ROR <Wd>, <Ws>, #<shift>
1690 is equivalent to:
1691 EXTR <Wd>, <Ws>, <Ws>, #<shift>. */
1692 static void
1693 convert_ror_to_extr (aarch64_inst *inst)
1694 {
1695 copy_operand_info (inst, 3, 2);
1696 copy_operand_info (inst, 2, 1);
1697 }
1698
1699 /* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
1700 is equivalent to:
1701 USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */
1702 static void
1703 convert_xtl_to_shll (aarch64_inst *inst)
1704 {
1705 inst->operands[2].qualifier = inst->operands[1].qualifier;
1706 inst->operands[2].imm.value = 0;
1707 }
1708
1709 /* Convert
1710 LSR <Xd>, <Xn>, #<shift>
1711 to
1712 UBFM <Xd>, <Xn>, #<shift>, #63. */
1713 static void
1714 convert_sr_to_bfm (aarch64_inst *inst)
1715 {
1716 inst->operands[3].imm.value =
1717 inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63;
1718 }
1719
1720 /* Convert MOV to ORR. */
1721 static void
1722 convert_mov_to_orr (aarch64_inst *inst)
1723 {
1724 /* MOV <Vd>.<T>, <Vn>.<T>
1725 is equivalent to:
1726 ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>. */
1727 copy_operand_info (inst, 2, 1);
1728 }
1729
1730 /* When <imms> >= <immr>, the instruction written:
1731 SBFX <Xd>, <Xn>, #<lsb>, #<width>
1732 is equivalent to:
1733 SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1). */
1734
1735 static void
1736 convert_bfx_to_bfm (aarch64_inst *inst)
1737 {
1738 int64_t lsb, width;
1739
1740 /* Convert the operand. */
1741 lsb = inst->operands[2].imm.value;
1742 width = inst->operands[3].imm.value;
1743 inst->operands[2].imm.value = lsb;
1744 inst->operands[3].imm.value = lsb + width - 1;
1745 }
1746
1747 /* When <imms> < <immr>, the instruction written:
1748 SBFIZ <Xd>, <Xn>, #<lsb>, #<width>
1749 is equivalent to:
1750 SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1). */
1751
1752 static void
1753 convert_bfi_to_bfm (aarch64_inst *inst)
1754 {
1755 int64_t lsb, width;
1756
1757 /* Convert the operand. */
1758 lsb = inst->operands[2].imm.value;
1759 width = inst->operands[3].imm.value;
1760 if (inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31)
1761 {
1762 inst->operands[2].imm.value = (32 - lsb) & 0x1f;
1763 inst->operands[3].imm.value = width - 1;
1764 }
1765 else
1766 {
1767 inst->operands[2].imm.value = (64 - lsb) & 0x3f;
1768 inst->operands[3].imm.value = width - 1;
1769 }
1770 }
1771
1772 /* The instruction written:
1773 BFC <Xd>, #<lsb>, #<width>
1774 is equivalent to:
1775 BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1). */
1776
1777 static void
1778 convert_bfc_to_bfm (aarch64_inst *inst)
1779 {
1780 int64_t lsb, width;
1781
1782 /* Insert XZR. */
1783 copy_operand_info (inst, 3, 2);
1784 copy_operand_info (inst, 2, 1);
1785 copy_operand_info (inst, 1, 0);
1786 inst->operands[1].reg.regno = 0x1f;
1787
1788 /* Convert the immediate operand. */
1789 lsb = inst->operands[2].imm.value;
1790 width = inst->operands[3].imm.value;
1791 if (inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31)
1792 {
1793 inst->operands[2].imm.value = (32 - lsb) & 0x1f;
1794 inst->operands[3].imm.value = width - 1;
1795 }
1796 else
1797 {
1798 inst->operands[2].imm.value = (64 - lsb) & 0x3f;
1799 inst->operands[3].imm.value = width - 1;
1800 }
1801 }
1802
1803 /* The instruction written:
1804 LSL <Xd>, <Xn>, #<shift>
1805 is equivalent to:
1806 UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */
1807
1808 static void
1809 convert_lsl_to_ubfm (aarch64_inst *inst)
1810 {
1811 int64_t shift = inst->operands[2].imm.value;
1812
1813 if (inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31)
1814 {
1815 inst->operands[2].imm.value = (32 - shift) & 0x1f;
1816 inst->operands[3].imm.value = 31 - shift;
1817 }
1818 else
1819 {
1820 inst->operands[2].imm.value = (64 - shift) & 0x3f;
1821 inst->operands[3].imm.value = 63 - shift;
1822 }
1823 }
1824
1825 /* CINC <Wd>, <Wn>, <cond>
1826 is equivalent to:
1827 CSINC <Wd>, <Wn>, <Wn>, invert(<cond>). */
1828
1829 static void
1830 convert_to_csel (aarch64_inst *inst)
1831 {
1832 copy_operand_info (inst, 3, 2);
1833 copy_operand_info (inst, 2, 1);
1834 inst->operands[3].cond = get_inverted_cond (inst->operands[3].cond);
1835 }
1836
1837 /* CSET <Wd>, <cond>
1838 is equivalent to:
1839 CSINC <Wd>, WZR, WZR, invert(<cond>). */
1840
1841 static void
1842 convert_cset_to_csinc (aarch64_inst *inst)
1843 {
1844 copy_operand_info (inst, 3, 1);
1845 copy_operand_info (inst, 2, 0);
1846 copy_operand_info (inst, 1, 0);
1847 inst->operands[1].reg.regno = 0x1f;
1848 inst->operands[2].reg.regno = 0x1f;
1849 inst->operands[3].cond = get_inverted_cond (inst->operands[3].cond);
1850 }
1851
1852 /* MOV <Wd>, #<imm>
1853 is equivalent to:
1854 MOVZ <Wd>, #<imm16>, LSL #<shift>. */
1855
1856 static void
1857 convert_mov_to_movewide (aarch64_inst *inst)
1858 {
1859 int is32;
1860 uint32_t shift_amount;
1861 uint64_t value;
1862
1863 switch (inst->opcode->op)
1864 {
1865 case OP_MOV_IMM_WIDE:
1866 value = inst->operands[1].imm.value;
1867 break;
1868 case OP_MOV_IMM_WIDEN:
1869 value = ~inst->operands[1].imm.value;
1870 break;
1871 default:
1872 assert (0);
1873 }
1874 inst->operands[1].type = AARCH64_OPND_HALF;
1875 is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
1876 if (! aarch64_wide_constant_p (value, is32, &shift_amount))
1877 /* The constraint check should have guaranteed this wouldn't happen. */
1878 assert (0);
1879 value >>= shift_amount;
1880 value &= 0xffff;
1881 inst->operands[1].imm.value = value;
1882 inst->operands[1].shifter.kind = AARCH64_MOD_LSL;
1883 inst->operands[1].shifter.amount = shift_amount;
1884 }
1885
1886 /* MOV <Wd>, #<imm>
1887 is equivalent to:
1888 ORR <Wd>, WZR, #<imm>. */
1889
1890 static void
1891 convert_mov_to_movebitmask (aarch64_inst *inst)
1892 {
1893 copy_operand_info (inst, 2, 1);
1894 inst->operands[1].reg.regno = 0x1f;
1895 inst->operands[1].skip = 0;
1896 }
1897
1898 /* Some alias opcodes are assembled by being converted to their real-form. */
1899
1900 static void
1901 convert_to_real (aarch64_inst *inst, const aarch64_opcode *real)
1902 {
1903 const aarch64_opcode *alias = inst->opcode;
1904
1905 if ((alias->flags & F_CONV) == 0)
1906 goto convert_to_real_return;
1907
1908 switch (alias->op)
1909 {
1910 case OP_ASR_IMM:
1911 case OP_LSR_IMM:
1912 convert_sr_to_bfm (inst);
1913 break;
1914 case OP_LSL_IMM:
1915 convert_lsl_to_ubfm (inst);
1916 break;
1917 case OP_CINC:
1918 case OP_CINV:
1919 case OP_CNEG:
1920 convert_to_csel (inst);
1921 break;
1922 case OP_CSET:
1923 case OP_CSETM:
1924 convert_cset_to_csinc (inst);
1925 break;
1926 case OP_UBFX:
1927 case OP_BFXIL:
1928 case OP_SBFX:
1929 convert_bfx_to_bfm (inst);
1930 break;
1931 case OP_SBFIZ:
1932 case OP_BFI:
1933 case OP_UBFIZ:
1934 convert_bfi_to_bfm (inst);
1935 break;
1936 case OP_BFC:
1937 convert_bfc_to_bfm (inst);
1938 break;
1939 case OP_MOV_V:
1940 convert_mov_to_orr (inst);
1941 break;
1942 case OP_MOV_IMM_WIDE:
1943 case OP_MOV_IMM_WIDEN:
1944 convert_mov_to_movewide (inst);
1945 break;
1946 case OP_MOV_IMM_LOG:
1947 convert_mov_to_movebitmask (inst);
1948 break;
1949 case OP_ROR_IMM:
1950 convert_ror_to_extr (inst);
1951 break;
1952 case OP_SXTL:
1953 case OP_SXTL2:
1954 case OP_UXTL:
1955 case OP_UXTL2:
1956 convert_xtl_to_shll (inst);
1957 break;
1958 default:
1959 break;
1960 }
1961
1962 convert_to_real_return:
1963 aarch64_replace_opcode (inst, real);
1964 }
1965
1966 /* Encode *INST_ORI of the opcode code OPCODE.
1967 Return the encoded result in *CODE and if QLF_SEQ is not NULL, return the
1968 matched operand qualifier sequence in *QLF_SEQ. */
1969
1970 bfd_boolean
1971 aarch64_opcode_encode (const aarch64_opcode *opcode,
1972 const aarch64_inst *inst_ori, aarch64_insn *code,
1973 aarch64_opnd_qualifier_t *qlf_seq,
1974 aarch64_operand_error *mismatch_detail,
1975 aarch64_instr_sequence* insn_sequence)
1976 {
1977 int i;
1978 const aarch64_opcode *aliased;
1979 aarch64_inst copy, *inst;
1980
1981 DEBUG_TRACE ("enter with %s", opcode->name);
1982
1983 /* Create a copy of *INST_ORI, so that we can do any change we want. */
1984 copy = *inst_ori;
1985 inst = &copy;
1986
1987 assert (inst->opcode == NULL || inst->opcode == opcode);
1988 if (inst->opcode == NULL)
1989 inst->opcode = opcode;
1990
1991 /* Constrain the operands.
1992 After passing this, the encoding is guaranteed to succeed. */
1993 if (aarch64_match_operands_constraint (inst, mismatch_detail) == 0)
1994 {
1995 DEBUG_TRACE ("FAIL since operand constraint not met");
1996 return 0;
1997 }
1998
1999 /* Get the base value.
2000 Note: this has to be before the aliasing handling below in order to
2001 get the base value from the alias opcode before we move on to the
2002 aliased opcode for encoding. */
2003 inst->value = opcode->opcode;
2004
2005 /* No need to do anything else if the opcode does not have any operand. */
2006 if (aarch64_num_of_operands (opcode) == 0)
2007 goto encoding_exit;
2008
2009 /* Assign operand indexes and check types. Also put the matched
2010 operand qualifiers in *QLF_SEQ to return. */
2011 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2012 {
2013 assert (opcode->operands[i] == inst->operands[i].type);
2014 inst->operands[i].idx = i;
2015 if (qlf_seq != NULL)
2016 *qlf_seq = inst->operands[i].qualifier;
2017 }
2018
2019 aliased = aarch64_find_real_opcode (opcode);
2020 /* If the opcode is an alias and it does not ask for direct encoding by
2021 itself, the instruction will be transformed to the form of real opcode
2022 and the encoding will be carried out using the rules for the aliased
2023 opcode. */
2024 if (aliased != NULL && (opcode->flags & F_CONV))
2025 {
2026 DEBUG_TRACE ("real opcode '%s' has been found for the alias %s",
2027 aliased->name, opcode->name);
2028 /* Convert the operands to the form of the real opcode. */
2029 convert_to_real (inst, aliased);
2030 opcode = aliased;
2031 }
2032
2033 aarch64_opnd_info *info = inst->operands;
2034
2035 /* Call the inserter of each operand. */
2036 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++info)
2037 {
2038 const aarch64_operand *opnd;
2039 enum aarch64_opnd type = opcode->operands[i];
2040 if (type == AARCH64_OPND_NIL)
2041 break;
2042 if (info->skip)
2043 {
2044 DEBUG_TRACE ("skip the incomplete operand %d", i);
2045 continue;
2046 }
2047 opnd = &aarch64_operands[type];
2048 if (operand_has_inserter (opnd)
2049 && !aarch64_insert_operand (opnd, info, &inst->value, inst,
2050 mismatch_detail))
2051 return FALSE;
2052 }
2053
2054 /* Call opcode encoders indicated by flags. */
2055 if (opcode_has_special_coder (opcode))
2056 do_special_encoding (inst);
2057
2058 /* Possibly use the instruction class to encode the chosen qualifier
2059 variant. */
2060 aarch64_encode_variant_using_iclass (inst);
2061
2062 /* Run a verifier if the instruction has one set. */
2063 if (opcode->verifier)
2064 {
2065 enum err_type result = opcode->verifier (inst, *code, 0, TRUE,
2066 mismatch_detail, insn_sequence);
2067 switch (result)
2068 {
2069 case ERR_UND:
2070 case ERR_UNP:
2071 case ERR_NYI:
2072 return FALSE;
2073 default:
2074 break;
2075 }
2076 }
2077
2078 /* Always run constrain verifiers, this is needed because constrains need to
2079 maintain a global state. Regardless if the instruction has the flag set
2080 or not. */
2081 enum err_type result = verify_constraints (inst, *code, 0, TRUE,
2082 mismatch_detail, insn_sequence);
2083 switch (result)
2084 {
2085 case ERR_UND:
2086 case ERR_UNP:
2087 case ERR_NYI:
2088 return FALSE;
2089 default:
2090 break;
2091 }
2092
2093
2094 encoding_exit:
2095 DEBUG_TRACE ("exit with %s", opcode->name);
2096
2097 *code = inst->value;
2098
2099 return TRUE;
2100 }
GDB Binutils - Deliverables
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