1 /* aarch64-dis.c -- AArch64 disassembler.
2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
22 #include "bfd_stdint.h"
23 #include "disassemble.h"
24 #include "libiberty.h"
26 #include "aarch64-dis.h"
36 /* Cached mapping symbol state. */
43 static enum map_type last_type
;
44 static int last_mapping_sym
= -1;
45 static bfd_vma last_mapping_addr
= 0;
48 static int no_aliases
= 0; /* If set disassemble as most general inst. */
52 set_default_aarch64_dis_options (struct disassemble_info
*info ATTRIBUTE_UNUSED
)
57 parse_aarch64_dis_option (const char *option
, unsigned int len ATTRIBUTE_UNUSED
)
59 /* Try to match options that are simple flags */
60 if (CONST_STRNEQ (option
, "no-aliases"))
66 if (CONST_STRNEQ (option
, "aliases"))
73 if (CONST_STRNEQ (option
, "debug_dump"))
78 #endif /* DEBUG_AARCH64 */
81 fprintf (stderr
, _("Unrecognised disassembler option: %s\n"), option
);
85 parse_aarch64_dis_options (const char *options
)
87 const char *option_end
;
92 while (*options
!= '\0')
94 /* Skip empty options. */
101 /* We know that *options is neither NUL or a comma. */
102 option_end
= options
+ 1;
103 while (*option_end
!= ',' && *option_end
!= '\0')
106 parse_aarch64_dis_option (options
, option_end
- options
);
108 /* Go on to the next one. If option_end points to a comma, it
109 will be skipped above. */
110 options
= option_end
;
114 /* Functions doing the instruction disassembling. */
116 /* The unnamed arguments consist of the number of fields and information about
117 these fields where the VALUE will be extracted from CODE and returned.
118 MASK can be zero or the base mask of the opcode.
120 N.B. the fields are required to be in such an order than the most signficant
121 field for VALUE comes the first, e.g. the <index> in
122 SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
123 is encoded in H:L:M in some cases, the fields H:L:M should be passed in
124 the order of H, L, M. */
127 extract_fields (aarch64_insn code
, aarch64_insn mask
, ...)
130 const aarch64_field
*field
;
131 enum aarch64_field_kind kind
;
135 num
= va_arg (va
, uint32_t);
137 aarch64_insn value
= 0x0;
140 kind
= va_arg (va
, enum aarch64_field_kind
);
141 field
= &fields
[kind
];
142 value
<<= field
->width
;
143 value
|= extract_field (kind
, code
, mask
);
148 /* Extract the value of all fields in SELF->fields from instruction CODE.
149 The least significant bit comes from the final field. */
152 extract_all_fields (const aarch64_operand
*self
, aarch64_insn code
)
156 enum aarch64_field_kind kind
;
159 for (i
= 0; i
< ARRAY_SIZE (self
->fields
) && self
->fields
[i
] != FLD_NIL
; ++i
)
161 kind
= self
->fields
[i
];
162 value
<<= fields
[kind
].width
;
163 value
|= extract_field (kind
, code
, 0);
168 /* Sign-extend bit I of VALUE. */
169 static inline int32_t
170 sign_extend (aarch64_insn value
, unsigned i
)
172 uint32_t ret
= value
;
175 if ((value
>> i
) & 0x1)
177 uint32_t val
= (uint32_t)(-1) << i
;
180 return (int32_t) ret
;
183 /* N.B. the following inline helpfer functions create a dependency on the
184 order of operand qualifier enumerators. */
186 /* Given VALUE, return qualifier for a general purpose register. */
187 static inline enum aarch64_opnd_qualifier
188 get_greg_qualifier_from_value (aarch64_insn value
)
190 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_W
+ value
;
192 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
196 /* Given VALUE, return qualifier for a vector register. This does not support
197 decoding instructions that accept the 2H vector type. */
199 static inline enum aarch64_opnd_qualifier
200 get_vreg_qualifier_from_value (aarch64_insn value
)
202 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_V_8B
+ value
;
204 /* Instructions using vector type 2H should not call this function. Skip over
206 if (qualifier
>= AARCH64_OPND_QLF_V_2H
)
210 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
214 /* Given VALUE, return qualifier for an FP or AdvSIMD scalar register. */
215 static inline enum aarch64_opnd_qualifier
216 get_sreg_qualifier_from_value (aarch64_insn value
)
218 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_S_B
+ value
;
221 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
225 /* Given the instruction in *INST which is probably half way through the
226 decoding and our caller wants to know the expected qualifier for operand
227 I. Return such a qualifier if we can establish it; otherwise return
228 AARCH64_OPND_QLF_NIL. */
230 static aarch64_opnd_qualifier_t
231 get_expected_qualifier (const aarch64_inst
*inst
, int i
)
233 aarch64_opnd_qualifier_seq_t qualifiers
;
234 /* Should not be called if the qualifier is known. */
235 assert (inst
->operands
[i
].qualifier
== AARCH64_OPND_QLF_NIL
);
236 if (aarch64_find_best_match (inst
, inst
->opcode
->qualifiers_list
,
238 return qualifiers
[i
];
240 return AARCH64_OPND_QLF_NIL
;
243 /* Operand extractors. */
246 aarch64_ext_regno (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
247 const aarch64_insn code
,
248 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
250 info
->reg
.regno
= extract_field (self
->fields
[0], code
, 0);
255 aarch64_ext_regno_pair (const aarch64_operand
*self ATTRIBUTE_UNUSED
, aarch64_opnd_info
*info
,
256 const aarch64_insn code ATTRIBUTE_UNUSED
,
257 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
259 assert (info
->idx
== 1
261 info
->reg
.regno
= inst
->operands
[info
->idx
- 1].reg
.regno
+ 1;
265 /* e.g. IC <ic_op>{, <Xt>}. */
267 aarch64_ext_regrt_sysins (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
268 const aarch64_insn code
,
269 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
271 info
->reg
.regno
= extract_field (self
->fields
[0], code
, 0);
272 assert (info
->idx
== 1
273 && (aarch64_get_operand_class (inst
->operands
[0].type
)
274 == AARCH64_OPND_CLASS_SYSTEM
));
275 /* This will make the constraint checking happy and more importantly will
276 help the disassembler determine whether this operand is optional or
278 info
->present
= aarch64_sys_ins_reg_has_xt (inst
->operands
[0].sysins_op
);
283 /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
285 aarch64_ext_reglane (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
286 const aarch64_insn code
,
287 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
290 info
->reglane
.regno
= extract_field (self
->fields
[0], code
,
293 /* Index and/or type. */
294 if (inst
->opcode
->iclass
== asisdone
295 || inst
->opcode
->iclass
== asimdins
)
297 if (info
->type
== AARCH64_OPND_En
298 && inst
->opcode
->operands
[0] == AARCH64_OPND_Ed
)
301 /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */
302 assert (info
->idx
== 1); /* Vn */
303 aarch64_insn value
= extract_field (FLD_imm4
, code
, 0);
304 /* Depend on AARCH64_OPND_Ed to determine the qualifier. */
305 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
306 shift
= get_logsz (aarch64_get_qualifier_esize (info
->qualifier
));
307 info
->reglane
.index
= value
>> shift
;
311 /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>].
319 aarch64_insn value
= extract_field (FLD_imm5
, code
, 0);
320 while (++pos
<= 3 && (value
& 0x1) == 0)
324 info
->qualifier
= get_sreg_qualifier_from_value (pos
);
325 info
->reglane
.index
= (unsigned) (value
>> 1);
330 /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
331 or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
333 /* Need information in other operand(s) to help decoding. */
334 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
335 switch (info
->qualifier
)
337 case AARCH64_OPND_QLF_S_H
:
339 info
->reglane
.index
= extract_fields (code
, 0, 3, FLD_H
, FLD_L
,
341 info
->reglane
.regno
&= 0xf;
343 case AARCH64_OPND_QLF_S_S
:
345 info
->reglane
.index
= extract_fields (code
, 0, 2, FLD_H
, FLD_L
);
347 case AARCH64_OPND_QLF_S_D
:
349 info
->reglane
.index
= extract_field (FLD_H
, code
, 0);
355 if (inst
->opcode
->op
== OP_FCMLA_ELEM
)
357 /* Complex operand takes two elements. */
358 if (info
->reglane
.index
& 1)
360 info
->reglane
.index
/= 2;
368 aarch64_ext_reglist (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
369 const aarch64_insn code
,
370 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
373 info
->reglist
.first_regno
= extract_field (self
->fields
[0], code
, 0);
375 info
->reglist
.num_regs
= extract_field (FLD_len
, code
, 0) + 1;
379 /* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions. */
381 aarch64_ext_ldst_reglist (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
382 aarch64_opnd_info
*info
, const aarch64_insn code
,
383 const aarch64_inst
*inst
)
386 /* Number of elements in each structure to be loaded/stored. */
387 unsigned expected_num
= get_opcode_dependent_value (inst
->opcode
);
391 unsigned is_reserved
;
393 unsigned num_elements
;
409 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
411 value
= extract_field (FLD_opcode
, code
, 0);
412 /* PR 21595: Check for a bogus value. */
413 if (value
>= ARRAY_SIZE (data
))
415 if (expected_num
!= data
[value
].num_elements
|| data
[value
].is_reserved
)
417 info
->reglist
.num_regs
= data
[value
].num_regs
;
422 /* Decode Rt and S fields of Vt in AdvSIMD load single structure to all
423 lanes instructions. */
425 aarch64_ext_ldst_reglist_r (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
426 aarch64_opnd_info
*info
, const aarch64_insn code
,
427 const aarch64_inst
*inst
)
432 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
434 value
= extract_field (FLD_S
, code
, 0);
436 /* Number of registers is equal to the number of elements in
437 each structure to be loaded/stored. */
438 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
439 assert (info
->reglist
.num_regs
>= 1 && info
->reglist
.num_regs
<= 4);
441 /* Except when it is LD1R. */
442 if (info
->reglist
.num_regs
== 1 && value
== (aarch64_insn
) 1)
443 info
->reglist
.num_regs
= 2;
448 /* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD
449 load/store single element instructions. */
451 aarch64_ext_ldst_elemlist (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
452 aarch64_opnd_info
*info
, const aarch64_insn code
,
453 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
455 aarch64_field field
= {0, 0};
456 aarch64_insn QSsize
; /* fields Q:S:size. */
457 aarch64_insn opcodeh2
; /* opcode<2:1> */
460 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
462 /* Decode the index, opcode<2:1> and size. */
463 gen_sub_field (FLD_asisdlso_opcode
, 1, 2, &field
);
464 opcodeh2
= extract_field_2 (&field
, code
, 0);
465 QSsize
= extract_fields (code
, 0, 3, FLD_Q
, FLD_S
, FLD_vldst_size
);
469 info
->qualifier
= AARCH64_OPND_QLF_S_B
;
470 /* Index encoded in "Q:S:size". */
471 info
->reglist
.index
= QSsize
;
477 info
->qualifier
= AARCH64_OPND_QLF_S_H
;
478 /* Index encoded in "Q:S:size<1>". */
479 info
->reglist
.index
= QSsize
>> 1;
482 if ((QSsize
>> 1) & 0x1)
485 if ((QSsize
& 0x1) == 0)
487 info
->qualifier
= AARCH64_OPND_QLF_S_S
;
488 /* Index encoded in "Q:S". */
489 info
->reglist
.index
= QSsize
>> 2;
493 if (extract_field (FLD_S
, code
, 0))
496 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
497 /* Index encoded in "Q". */
498 info
->reglist
.index
= QSsize
>> 3;
505 info
->reglist
.has_index
= 1;
506 info
->reglist
.num_regs
= 0;
507 /* Number of registers is equal to the number of elements in
508 each structure to be loaded/stored. */
509 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
510 assert (info
->reglist
.num_regs
>= 1 && info
->reglist
.num_regs
<= 4);
515 /* Decode fields immh:immb and/or Q for e.g.
516 SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
517 or SSHR <V><d>, <V><n>, #<shift>. */
520 aarch64_ext_advsimd_imm_shift (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
521 aarch64_opnd_info
*info
, const aarch64_insn code
,
522 const aarch64_inst
*inst
)
525 aarch64_insn Q
, imm
, immh
;
526 enum aarch64_insn_class iclass
= inst
->opcode
->iclass
;
528 immh
= extract_field (FLD_immh
, code
, 0);
531 imm
= extract_fields (code
, 0, 2, FLD_immh
, FLD_immb
);
533 /* Get highest set bit in immh. */
534 while (--pos
>= 0 && (immh
& 0x8) == 0)
537 assert ((iclass
== asimdshf
|| iclass
== asisdshf
)
538 && (info
->type
== AARCH64_OPND_IMM_VLSR
539 || info
->type
== AARCH64_OPND_IMM_VLSL
));
541 if (iclass
== asimdshf
)
543 Q
= extract_field (FLD_Q
, code
, 0);
545 0000 x SEE AdvSIMD modified immediate
555 get_vreg_qualifier_from_value ((pos
<< 1) | (int) Q
);
558 info
->qualifier
= get_sreg_qualifier_from_value (pos
);
560 if (info
->type
== AARCH64_OPND_IMM_VLSR
)
562 0000 SEE AdvSIMD modified immediate
563 0001 (16-UInt(immh:immb))
564 001x (32-UInt(immh:immb))
565 01xx (64-UInt(immh:immb))
566 1xxx (128-UInt(immh:immb)) */
567 info
->imm
.value
= (16 << pos
) - imm
;
571 0000 SEE AdvSIMD modified immediate
572 0001 (UInt(immh:immb)-8)
573 001x (UInt(immh:immb)-16)
574 01xx (UInt(immh:immb)-32)
575 1xxx (UInt(immh:immb)-64) */
576 info
->imm
.value
= imm
- (8 << pos
);
581 /* Decode shift immediate for e.g. sshr (imm). */
583 aarch64_ext_shll_imm (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
584 aarch64_opnd_info
*info
, const aarch64_insn code
,
585 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
589 val
= extract_field (FLD_size
, code
, 0);
592 case 0: imm
= 8; break;
593 case 1: imm
= 16; break;
594 case 2: imm
= 32; break;
597 info
->imm
.value
= imm
;
601 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
602 value in the field(s) will be extracted as unsigned immediate value. */
604 aarch64_ext_imm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
605 const aarch64_insn code
,
606 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
610 imm
= extract_all_fields (self
, code
);
612 if (operand_need_sign_extension (self
))
613 imm
= sign_extend (imm
, get_operand_fields_width (self
) - 1);
615 if (operand_need_shift_by_two (self
))
618 if (info
->type
== AARCH64_OPND_ADDR_ADRP
)
621 info
->imm
.value
= imm
;
625 /* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
627 aarch64_ext_imm_half (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
628 const aarch64_insn code
,
629 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
631 aarch64_ext_imm (self
, info
, code
, inst
);
632 info
->shifter
.kind
= AARCH64_MOD_LSL
;
633 info
->shifter
.amount
= extract_field (FLD_hw
, code
, 0) << 4;
637 /* Decode cmode and "a:b:c:d:e:f:g:h" for e.g.
638 MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
640 aarch64_ext_advsimd_imm_modified (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
641 aarch64_opnd_info
*info
,
642 const aarch64_insn code
,
643 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
646 enum aarch64_opnd_qualifier opnd0_qualifier
= inst
->operands
[0].qualifier
;
647 aarch64_field field
= {0, 0};
649 assert (info
->idx
== 1);
651 if (info
->type
== AARCH64_OPND_SIMD_FPIMM
)
654 /* a:b:c:d:e:f:g:h */
655 imm
= extract_fields (code
, 0, 2, FLD_abc
, FLD_defgh
);
656 if (!info
->imm
.is_fp
&& aarch64_get_qualifier_esize (opnd0_qualifier
) == 8)
658 /* Either MOVI <Dd>, #<imm>
659 or MOVI <Vd>.2D, #<imm>.
660 <imm> is a 64-bit immediate
661 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh',
662 encoded in "a:b:c:d:e:f:g:h". */
664 unsigned abcdefgh
= imm
;
665 for (imm
= 0ull, i
= 0; i
< 8; i
++)
666 if (((abcdefgh
>> i
) & 0x1) != 0)
667 imm
|= 0xffull
<< (8 * i
);
669 info
->imm
.value
= imm
;
672 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
673 switch (info
->qualifier
)
675 case AARCH64_OPND_QLF_NIL
:
677 info
->shifter
.kind
= AARCH64_MOD_NONE
;
679 case AARCH64_OPND_QLF_LSL
:
681 info
->shifter
.kind
= AARCH64_MOD_LSL
;
682 switch (aarch64_get_qualifier_esize (opnd0_qualifier
))
684 case 4: gen_sub_field (FLD_cmode
, 1, 2, &field
); break; /* per word */
685 case 2: gen_sub_field (FLD_cmode
, 1, 1, &field
); break; /* per half */
686 case 1: gen_sub_field (FLD_cmode
, 1, 0, &field
); break; /* per byte */
687 default: assert (0); return 0;
689 /* 00: 0; 01: 8; 10:16; 11:24. */
690 info
->shifter
.amount
= extract_field_2 (&field
, code
, 0) << 3;
692 case AARCH64_OPND_QLF_MSL
:
694 info
->shifter
.kind
= AARCH64_MOD_MSL
;
695 gen_sub_field (FLD_cmode
, 0, 1, &field
); /* per word */
696 info
->shifter
.amount
= extract_field_2 (&field
, code
, 0) ? 16 : 8;
706 /* Decode an 8-bit floating-point immediate. */
708 aarch64_ext_fpimm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
709 const aarch64_insn code
,
710 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
712 info
->imm
.value
= extract_all_fields (self
, code
);
717 /* Decode a 1-bit rotate immediate (#90 or #270). */
719 aarch64_ext_imm_rotate1 (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
720 const aarch64_insn code
,
721 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
723 uint64_t rot
= extract_field (self
->fields
[0], code
, 0);
725 info
->imm
.value
= rot
* 180 + 90;
729 /* Decode a 2-bit rotate immediate (#0, #90, #180 or #270). */
731 aarch64_ext_imm_rotate2 (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
732 const aarch64_insn code
,
733 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
735 uint64_t rot
= extract_field (self
->fields
[0], code
, 0);
737 info
->imm
.value
= rot
* 90;
741 /* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
743 aarch64_ext_fbits (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
744 aarch64_opnd_info
*info
, const aarch64_insn code
,
745 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
747 info
->imm
.value
= 64- extract_field (FLD_scale
, code
, 0);
751 /* Decode arithmetic immediate for e.g.
752 SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
754 aarch64_ext_aimm (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
755 aarch64_opnd_info
*info
, const aarch64_insn code
,
756 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
760 info
->shifter
.kind
= AARCH64_MOD_LSL
;
762 value
= extract_field (FLD_shift
, code
, 0);
765 info
->shifter
.amount
= value
? 12 : 0;
766 /* imm12 (unsigned) */
767 info
->imm
.value
= extract_field (FLD_imm12
, code
, 0);
772 /* Return true if VALUE is a valid logical immediate encoding, storing the
773 decoded value in *RESULT if so. ESIZE is the number of bytes in the
774 decoded immediate. */
776 decode_limm (uint32_t esize
, aarch64_insn value
, int64_t *result
)
782 /* value is N:immr:imms. */
784 R
= (value
>> 6) & 0x3f;
785 N
= (value
>> 12) & 0x1;
787 /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
788 (in other words, right rotated by R), then replicated. */
792 mask
= 0xffffffffffffffffull
;
798 case 0x00 ... 0x1f: /* 0xxxxx */ simd_size
= 32; break;
799 case 0x20 ... 0x2f: /* 10xxxx */ simd_size
= 16; S
&= 0xf; break;
800 case 0x30 ... 0x37: /* 110xxx */ simd_size
= 8; S
&= 0x7; break;
801 case 0x38 ... 0x3b: /* 1110xx */ simd_size
= 4; S
&= 0x3; break;
802 case 0x3c ... 0x3d: /* 11110x */ simd_size
= 2; S
&= 0x1; break;
805 mask
= (1ull << simd_size
) - 1;
806 /* Top bits are IGNORED. */
810 if (simd_size
> esize
* 8)
813 /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */
814 if (S
== simd_size
- 1)
816 /* S+1 consecutive bits to 1. */
817 /* NOTE: S can't be 63 due to detection above. */
818 imm
= (1ull << (S
+ 1)) - 1;
819 /* Rotate to the left by simd_size - R. */
821 imm
= ((imm
<< (simd_size
- R
)) & mask
) | (imm
>> R
);
822 /* Replicate the value according to SIMD size. */
825 case 2: imm
= (imm
<< 2) | imm
;
827 case 4: imm
= (imm
<< 4) | imm
;
829 case 8: imm
= (imm
<< 8) | imm
;
831 case 16: imm
= (imm
<< 16) | imm
;
833 case 32: imm
= (imm
<< 32) | imm
;
836 default: assert (0); return 0;
839 *result
= imm
& ~((uint64_t) -1 << (esize
* 4) << (esize
* 4));
844 /* Decode a logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */
846 aarch64_ext_limm (const aarch64_operand
*self
,
847 aarch64_opnd_info
*info
, const aarch64_insn code
,
848 const aarch64_inst
*inst
)
853 value
= extract_fields (code
, 0, 3, self
->fields
[0], self
->fields
[1],
855 esize
= aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
);
856 return decode_limm (esize
, value
, &info
->imm
.value
);
859 /* Decode a logical immediate for the BIC alias of AND (etc.). */
861 aarch64_ext_inv_limm (const aarch64_operand
*self
,
862 aarch64_opnd_info
*info
, const aarch64_insn code
,
863 const aarch64_inst
*inst
)
865 if (!aarch64_ext_limm (self
, info
, code
, inst
))
867 info
->imm
.value
= ~info
->imm
.value
;
871 /* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
872 or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
874 aarch64_ext_ft (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
875 aarch64_opnd_info
*info
,
876 const aarch64_insn code
, const aarch64_inst
*inst
)
881 info
->reg
.regno
= extract_field (FLD_Rt
, code
, 0);
884 value
= extract_field (FLD_ldst_size
, code
, 0);
885 if (inst
->opcode
->iclass
== ldstpair_indexed
886 || inst
->opcode
->iclass
== ldstnapair_offs
887 || inst
->opcode
->iclass
== ldstpair_off
888 || inst
->opcode
->iclass
== loadlit
)
890 enum aarch64_opnd_qualifier qualifier
;
893 case 0: qualifier
= AARCH64_OPND_QLF_S_S
; break;
894 case 1: qualifier
= AARCH64_OPND_QLF_S_D
; break;
895 case 2: qualifier
= AARCH64_OPND_QLF_S_Q
; break;
898 info
->qualifier
= qualifier
;
903 value
= extract_fields (code
, 0, 2, FLD_opc1
, FLD_ldst_size
);
906 info
->qualifier
= get_sreg_qualifier_from_value (value
);
912 /* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
914 aarch64_ext_addr_simple (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
915 aarch64_opnd_info
*info
,
917 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
920 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
924 /* Decode the address operand for e.g.
925 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
927 aarch64_ext_addr_regoff (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
928 aarch64_opnd_info
*info
,
929 aarch64_insn code
, const aarch64_inst
*inst
)
931 aarch64_insn S
, value
;
934 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
936 info
->addr
.offset
.regno
= extract_field (FLD_Rm
, code
, 0);
938 value
= extract_field (FLD_option
, code
, 0);
940 aarch64_get_operand_modifier_from_value (value
, TRUE
/* extend_p */);
941 /* Fix-up the shifter kind; although the table-driven approach is
942 efficient, it is slightly inflexible, thus needing this fix-up. */
943 if (info
->shifter
.kind
== AARCH64_MOD_UXTX
)
944 info
->shifter
.kind
= AARCH64_MOD_LSL
;
946 S
= extract_field (FLD_S
, code
, 0);
949 info
->shifter
.amount
= 0;
950 info
->shifter
.amount_present
= 0;
955 /* Need information in other operand(s) to help achieve the decoding
957 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
958 /* Get the size of the data element that is accessed, which may be
959 different from that of the source register size, e.g. in strb/ldrb. */
960 size
= aarch64_get_qualifier_esize (info
->qualifier
);
961 info
->shifter
.amount
= get_logsz (size
);
962 info
->shifter
.amount_present
= 1;
968 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>. */
970 aarch64_ext_addr_simm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
971 aarch64_insn code
, const aarch64_inst
*inst
)
974 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
977 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
978 /* simm (imm9 or imm7) */
979 imm
= extract_field (self
->fields
[0], code
, 0);
980 info
->addr
.offset
.imm
= sign_extend (imm
, fields
[self
->fields
[0]].width
- 1);
981 if (self
->fields
[0] == FLD_imm7
)
982 /* scaled immediate in ld/st pair instructions. */
983 info
->addr
.offset
.imm
*= aarch64_get_qualifier_esize (info
->qualifier
);
985 if (inst
->opcode
->iclass
== ldst_unscaled
986 || inst
->opcode
->iclass
== ldstnapair_offs
987 || inst
->opcode
->iclass
== ldstpair_off
988 || inst
->opcode
->iclass
== ldst_unpriv
)
989 info
->addr
.writeback
= 0;
992 /* pre/post- index */
993 info
->addr
.writeback
= 1;
994 if (extract_field (self
->fields
[1], code
, 0) == 1)
995 info
->addr
.preind
= 1;
997 info
->addr
.postind
= 1;
1003 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}]. */
1005 aarch64_ext_addr_uimm12 (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
1007 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1010 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
1011 shift
= get_logsz (aarch64_get_qualifier_esize (info
->qualifier
));
1013 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1015 info
->addr
.offset
.imm
= extract_field (self
->fields
[1], code
, 0) << shift
;
1019 /* Decode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */
1021 aarch64_ext_addr_simm10 (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
1023 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1027 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
1029 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1031 imm
= extract_fields (code
, 0, 2, self
->fields
[1], self
->fields
[2]);
1032 info
->addr
.offset
.imm
= sign_extend (imm
, 9) << 3;
1033 if (extract_field (self
->fields
[3], code
, 0) == 1) {
1034 info
->addr
.writeback
= 1;
1035 info
->addr
.preind
= 1;
1040 /* Decode the address operand for e.g.
1041 LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
1043 aarch64_ext_simd_addr_post (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1044 aarch64_opnd_info
*info
,
1045 aarch64_insn code
, const aarch64_inst
*inst
)
1047 /* The opcode dependent area stores the number of elements in
1048 each structure to be loaded/stored. */
1049 int is_ld1r
= get_opcode_dependent_value (inst
->opcode
) == 1;
1052 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
1053 /* Rm | #<amount> */
1054 info
->addr
.offset
.regno
= extract_field (FLD_Rm
, code
, 0);
1055 if (info
->addr
.offset
.regno
== 31)
1057 if (inst
->opcode
->operands
[0] == AARCH64_OPND_LVt_AL
)
1058 /* Special handling of loading single structure to all lane. */
1059 info
->addr
.offset
.imm
= (is_ld1r
? 1
1060 : inst
->operands
[0].reglist
.num_regs
)
1061 * aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
);
1063 info
->addr
.offset
.imm
= inst
->operands
[0].reglist
.num_regs
1064 * aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
)
1065 * aarch64_get_qualifier_nelem (inst
->operands
[0].qualifier
);
1068 info
->addr
.offset
.is_reg
= 1;
1069 info
->addr
.writeback
= 1;
1074 /* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
1076 aarch64_ext_cond (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1077 aarch64_opnd_info
*info
,
1078 aarch64_insn code
, const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1082 value
= extract_field (FLD_cond
, code
, 0);
1083 info
->cond
= get_cond_from_value (value
);
1087 /* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */
1089 aarch64_ext_sysreg (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1090 aarch64_opnd_info
*info
,
1092 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1094 /* op0:op1:CRn:CRm:op2 */
1095 info
->sysreg
= extract_fields (code
, 0, 5, FLD_op0
, FLD_op1
, FLD_CRn
,
1100 /* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
1102 aarch64_ext_pstatefield (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1103 aarch64_opnd_info
*info
, aarch64_insn code
,
1104 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1108 info
->pstatefield
= extract_fields (code
, 0, 2, FLD_op1
, FLD_op2
);
1109 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
1110 if (aarch64_pstatefields
[i
].value
== (aarch64_insn
)info
->pstatefield
)
1112 /* Reserved value in <pstatefield>. */
1116 /* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
1118 aarch64_ext_sysins_op (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1119 aarch64_opnd_info
*info
,
1121 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1125 const aarch64_sys_ins_reg
*sysins_ops
;
1126 /* op0:op1:CRn:CRm:op2 */
1127 value
= extract_fields (code
, 0, 5,
1128 FLD_op0
, FLD_op1
, FLD_CRn
,
1133 case AARCH64_OPND_SYSREG_AT
: sysins_ops
= aarch64_sys_regs_at
; break;
1134 case AARCH64_OPND_SYSREG_DC
: sysins_ops
= aarch64_sys_regs_dc
; break;
1135 case AARCH64_OPND_SYSREG_IC
: sysins_ops
= aarch64_sys_regs_ic
; break;
1136 case AARCH64_OPND_SYSREG_TLBI
: sysins_ops
= aarch64_sys_regs_tlbi
; break;
1137 default: assert (0); return 0;
1140 for (i
= 0; sysins_ops
[i
].name
!= NULL
; ++i
)
1141 if (sysins_ops
[i
].value
== value
)
1143 info
->sysins_op
= sysins_ops
+ i
;
1144 DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
1145 info
->sysins_op
->name
,
1146 (unsigned)info
->sysins_op
->value
,
1147 aarch64_sys_ins_reg_has_xt (info
->sysins_op
), i
);
1154 /* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
1157 aarch64_ext_barrier (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1158 aarch64_opnd_info
*info
,
1160 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1163 info
->barrier
= aarch64_barrier_options
+ extract_field (FLD_CRm
, code
, 0);
1167 /* Decode the prefetch operation option operand for e.g.
1168 PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
1171 aarch64_ext_prfop (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1172 aarch64_opnd_info
*info
,
1173 aarch64_insn code
, const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1176 info
->prfop
= aarch64_prfops
+ extract_field (FLD_Rt
, code
, 0);
1180 /* Decode the hint number for an alias taking an operand. Set info->hint_option
1181 to the matching name/value pair in aarch64_hint_options. */
1184 aarch64_ext_hint (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1185 aarch64_opnd_info
*info
,
1187 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1190 unsigned hint_number
;
1193 hint_number
= extract_fields (code
, 0, 2, FLD_CRm
, FLD_op2
);
1195 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
1197 if (hint_number
== aarch64_hint_options
[i
].value
)
1199 info
->hint_option
= &(aarch64_hint_options
[i
]);
1207 /* Decode the extended register operand for e.g.
1208 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1210 aarch64_ext_reg_extended (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1211 aarch64_opnd_info
*info
,
1213 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1218 info
->reg
.regno
= extract_field (FLD_Rm
, code
, 0);
1220 value
= extract_field (FLD_option
, code
, 0);
1221 info
->shifter
.kind
=
1222 aarch64_get_operand_modifier_from_value (value
, TRUE
/* extend_p */);
1224 info
->shifter
.amount
= extract_field (FLD_imm3
, code
, 0);
1226 /* This makes the constraint checking happy. */
1227 info
->shifter
.operator_present
= 1;
1229 /* Assume inst->operands[0].qualifier has been resolved. */
1230 assert (inst
->operands
[0].qualifier
!= AARCH64_OPND_QLF_NIL
);
1231 info
->qualifier
= AARCH64_OPND_QLF_W
;
1232 if (inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_X
1233 && (info
->shifter
.kind
== AARCH64_MOD_UXTX
1234 || info
->shifter
.kind
== AARCH64_MOD_SXTX
))
1235 info
->qualifier
= AARCH64_OPND_QLF_X
;
1240 /* Decode the shifted register operand for e.g.
1241 SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
1243 aarch64_ext_reg_shifted (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1244 aarch64_opnd_info
*info
,
1246 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1251 info
->reg
.regno
= extract_field (FLD_Rm
, code
, 0);
1253 value
= extract_field (FLD_shift
, code
, 0);
1254 info
->shifter
.kind
=
1255 aarch64_get_operand_modifier_from_value (value
, FALSE
/* extend_p */);
1256 if (info
->shifter
.kind
== AARCH64_MOD_ROR
1257 && inst
->opcode
->iclass
!= log_shift
)
1258 /* ROR is not available for the shifted register operand in arithmetic
1262 info
->shifter
.amount
= extract_field (FLD_imm6
, code
, 0);
1264 /* This makes the constraint checking happy. */
1265 info
->shifter
.operator_present
= 1;
1270 /* Decode an SVE address [<base>, #<offset>*<factor>, MUL VL],
1271 where <offset> is given by the OFFSET parameter and where <factor> is
1272 1 plus SELF's operand-dependent value. fields[0] specifies the field
1273 that holds <base>. */
1275 aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand
*self
,
1276 aarch64_opnd_info
*info
, aarch64_insn code
,
1279 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1280 info
->addr
.offset
.imm
= offset
* (1 + get_operand_specific_data (self
));
1281 info
->addr
.offset
.is_reg
= FALSE
;
1282 info
->addr
.writeback
= FALSE
;
1283 info
->addr
.preind
= TRUE
;
1285 info
->shifter
.kind
= AARCH64_MOD_MUL_VL
;
1286 info
->shifter
.amount
= 1;
1287 info
->shifter
.operator_present
= (info
->addr
.offset
.imm
!= 0);
1288 info
->shifter
.amount_present
= FALSE
;
1292 /* Decode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
1293 where <simm4> is a 4-bit signed value and where <factor> is 1 plus
1294 SELF's operand-dependent value. fields[0] specifies the field that
1295 holds <base>. <simm4> is encoded in the SVE_imm4 field. */
1297 aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand
*self
,
1298 aarch64_opnd_info
*info
, aarch64_insn code
,
1299 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1303 offset
= extract_field (FLD_SVE_imm4
, code
, 0);
1304 offset
= ((offset
+ 8) & 15) - 8;
1305 return aarch64_ext_sve_addr_reg_mul_vl (self
, info
, code
, offset
);
1308 /* Decode an SVE address [<base>, #<simm6>*<factor>, MUL VL],
1309 where <simm6> is a 6-bit signed value and where <factor> is 1 plus
1310 SELF's operand-dependent value. fields[0] specifies the field that
1311 holds <base>. <simm6> is encoded in the SVE_imm6 field. */
1313 aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand
*self
,
1314 aarch64_opnd_info
*info
, aarch64_insn code
,
1315 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1319 offset
= extract_field (FLD_SVE_imm6
, code
, 0);
1320 offset
= (((offset
+ 32) & 63) - 32);
1321 return aarch64_ext_sve_addr_reg_mul_vl (self
, info
, code
, offset
);
1324 /* Decode an SVE address [<base>, #<simm9>*<factor>, MUL VL],
1325 where <simm9> is a 9-bit signed value and where <factor> is 1 plus
1326 SELF's operand-dependent value. fields[0] specifies the field that
1327 holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6
1328 and imm3 fields, with imm3 being the less-significant part. */
1330 aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand
*self
,
1331 aarch64_opnd_info
*info
,
1333 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1337 offset
= extract_fields (code
, 0, 2, FLD_SVE_imm6
, FLD_imm3
);
1338 offset
= (((offset
+ 256) & 511) - 256);
1339 return aarch64_ext_sve_addr_reg_mul_vl (self
, info
, code
, offset
);
1342 /* Decode an SVE address [<base>, #<offset> << <shift>], where <offset>
1343 is given by the OFFSET parameter and where <shift> is SELF's operand-
1344 dependent value. fields[0] specifies the base register field <base>. */
1346 aarch64_ext_sve_addr_reg_imm (const aarch64_operand
*self
,
1347 aarch64_opnd_info
*info
, aarch64_insn code
,
1350 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1351 info
->addr
.offset
.imm
= offset
* (1 << get_operand_specific_data (self
));
1352 info
->addr
.offset
.is_reg
= FALSE
;
1353 info
->addr
.writeback
= FALSE
;
1354 info
->addr
.preind
= TRUE
;
1355 info
->shifter
.operator_present
= FALSE
;
1356 info
->shifter
.amount_present
= FALSE
;
1360 /* Decode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4>
1361 is a 4-bit signed number and where <shift> is SELF's operand-dependent
1362 value. fields[0] specifies the base register field. */
1364 aarch64_ext_sve_addr_ri_s4 (const aarch64_operand
*self
,
1365 aarch64_opnd_info
*info
, aarch64_insn code
,
1366 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1368 int offset
= sign_extend (extract_field (FLD_SVE_imm4
, code
, 0), 3);
1369 return aarch64_ext_sve_addr_reg_imm (self
, info
, code
, offset
);
1372 /* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
1373 is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
1374 value. fields[0] specifies the base register field. */
1376 aarch64_ext_sve_addr_ri_u6 (const aarch64_operand
*self
,
1377 aarch64_opnd_info
*info
, aarch64_insn code
,
1378 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1380 int offset
= extract_field (FLD_SVE_imm6
, code
, 0);
1381 return aarch64_ext_sve_addr_reg_imm (self
, info
, code
, offset
);
1384 /* Decode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift>
1385 is SELF's operand-dependent value. fields[0] specifies the base
1386 register field and fields[1] specifies the offset register field. */
1388 aarch64_ext_sve_addr_rr_lsl (const aarch64_operand
*self
,
1389 aarch64_opnd_info
*info
, aarch64_insn code
,
1390 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1394 index_regno
= extract_field (self
->fields
[1], code
, 0);
1395 if (index_regno
== 31 && (self
->flags
& OPD_F_NO_ZR
) != 0)
1398 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1399 info
->addr
.offset
.regno
= index_regno
;
1400 info
->addr
.offset
.is_reg
= TRUE
;
1401 info
->addr
.writeback
= FALSE
;
1402 info
->addr
.preind
= TRUE
;
1403 info
->shifter
.kind
= AARCH64_MOD_LSL
;
1404 info
->shifter
.amount
= get_operand_specific_data (self
);
1405 info
->shifter
.operator_present
= (info
->shifter
.amount
!= 0);
1406 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1410 /* Decode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where
1411 <shift> is SELF's operand-dependent value. fields[0] specifies the
1412 base register field, fields[1] specifies the offset register field and
1413 fields[2] is a single-bit field that selects SXTW over UXTW. */
1415 aarch64_ext_sve_addr_rz_xtw (const aarch64_operand
*self
,
1416 aarch64_opnd_info
*info
, aarch64_insn code
,
1417 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1419 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1420 info
->addr
.offset
.regno
= extract_field (self
->fields
[1], code
, 0);
1421 info
->addr
.offset
.is_reg
= TRUE
;
1422 info
->addr
.writeback
= FALSE
;
1423 info
->addr
.preind
= TRUE
;
1424 if (extract_field (self
->fields
[2], code
, 0))
1425 info
->shifter
.kind
= AARCH64_MOD_SXTW
;
1427 info
->shifter
.kind
= AARCH64_MOD_UXTW
;
1428 info
->shifter
.amount
= get_operand_specific_data (self
);
1429 info
->shifter
.operator_present
= TRUE
;
1430 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1434 /* Decode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a
1435 5-bit unsigned number and where <shift> is SELF's operand-dependent value.
1436 fields[0] specifies the base register field. */
1438 aarch64_ext_sve_addr_zi_u5 (const aarch64_operand
*self
,
1439 aarch64_opnd_info
*info
, aarch64_insn code
,
1440 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1442 int offset
= extract_field (FLD_imm5
, code
, 0);
1443 return aarch64_ext_sve_addr_reg_imm (self
, info
, code
, offset
);
1446 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}],
1447 where <modifier> is given by KIND and where <msz> is a 2-bit unsigned
1448 number. fields[0] specifies the base register field and fields[1]
1449 specifies the offset register field. */
1451 aarch64_ext_sve_addr_zz (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
1452 aarch64_insn code
, enum aarch64_modifier_kind kind
)
1454 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1455 info
->addr
.offset
.regno
= extract_field (self
->fields
[1], code
, 0);
1456 info
->addr
.offset
.is_reg
= TRUE
;
1457 info
->addr
.writeback
= FALSE
;
1458 info
->addr
.preind
= TRUE
;
1459 info
->shifter
.kind
= kind
;
1460 info
->shifter
.amount
= extract_field (FLD_SVE_msz
, code
, 0);
1461 info
->shifter
.operator_present
= (kind
!= AARCH64_MOD_LSL
1462 || info
->shifter
.amount
!= 0);
1463 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1467 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where
1468 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1469 field and fields[1] specifies the offset register field. */
1471 aarch64_ext_sve_addr_zz_lsl (const aarch64_operand
*self
,
1472 aarch64_opnd_info
*info
, aarch64_insn code
,
1473 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1475 return aarch64_ext_sve_addr_zz (self
, info
, code
, AARCH64_MOD_LSL
);
1478 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where
1479 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1480 field and fields[1] specifies the offset register field. */
1482 aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand
*self
,
1483 aarch64_opnd_info
*info
, aarch64_insn code
,
1484 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1486 return aarch64_ext_sve_addr_zz (self
, info
, code
, AARCH64_MOD_SXTW
);
1489 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where
1490 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1491 field and fields[1] specifies the offset register field. */
1493 aarch64_ext_sve_addr_zz_uxtw (const aarch64_operand
*self
,
1494 aarch64_opnd_info
*info
, aarch64_insn code
,
1495 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1497 return aarch64_ext_sve_addr_zz (self
, info
, code
, AARCH64_MOD_UXTW
);
1500 /* Finish decoding an SVE arithmetic immediate, given that INFO already
1501 has the raw field value and that the low 8 bits decode to VALUE. */
1503 decode_sve_aimm (aarch64_opnd_info
*info
, int64_t value
)
1505 info
->shifter
.kind
= AARCH64_MOD_LSL
;
1506 info
->shifter
.amount
= 0;
1507 if (info
->imm
.value
& 0x100)
1510 /* Decode 0x100 as #0, LSL #8. */
1511 info
->shifter
.amount
= 8;
1515 info
->shifter
.operator_present
= (info
->shifter
.amount
!= 0);
1516 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1517 info
->imm
.value
= value
;
1521 /* Decode an SVE ADD/SUB immediate. */
1523 aarch64_ext_sve_aimm (const aarch64_operand
*self
,
1524 aarch64_opnd_info
*info
, const aarch64_insn code
,
1525 const aarch64_inst
*inst
)
1527 return (aarch64_ext_imm (self
, info
, code
, inst
)
1528 && decode_sve_aimm (info
, (uint8_t) info
->imm
.value
));
1531 /* Decode an SVE CPY/DUP immediate. */
1533 aarch64_ext_sve_asimm (const aarch64_operand
*self
,
1534 aarch64_opnd_info
*info
, const aarch64_insn code
,
1535 const aarch64_inst
*inst
)
1537 return (aarch64_ext_imm (self
, info
, code
, inst
)
1538 && decode_sve_aimm (info
, (int8_t) info
->imm
.value
));
1541 /* Decode a single-bit immediate that selects between #0.5 and #1.0.
1542 The fields array specifies which field to use. */
1544 aarch64_ext_sve_float_half_one (const aarch64_operand
*self
,
1545 aarch64_opnd_info
*info
, aarch64_insn code
,
1546 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1548 if (extract_field (self
->fields
[0], code
, 0))
1549 info
->imm
.value
= 0x3f800000;
1551 info
->imm
.value
= 0x3f000000;
1552 info
->imm
.is_fp
= TRUE
;
1556 /* Decode a single-bit immediate that selects between #0.5 and #2.0.
1557 The fields array specifies which field to use. */
1559 aarch64_ext_sve_float_half_two (const aarch64_operand
*self
,
1560 aarch64_opnd_info
*info
, aarch64_insn code
,
1561 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1563 if (extract_field (self
->fields
[0], code
, 0))
1564 info
->imm
.value
= 0x40000000;
1566 info
->imm
.value
= 0x3f000000;
1567 info
->imm
.is_fp
= TRUE
;
1571 /* Decode a single-bit immediate that selects between #0.0 and #1.0.
1572 The fields array specifies which field to use. */
1574 aarch64_ext_sve_float_zero_one (const aarch64_operand
*self
,
1575 aarch64_opnd_info
*info
, aarch64_insn code
,
1576 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1578 if (extract_field (self
->fields
[0], code
, 0))
1579 info
->imm
.value
= 0x3f800000;
1581 info
->imm
.value
= 0x0;
1582 info
->imm
.is_fp
= TRUE
;
1586 /* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields
1587 array specifies which field to use for Zn. MM is encoded in the
1588 concatenation of imm5 and SVE_tszh, with imm5 being the less
1589 significant part. */
1591 aarch64_ext_sve_index (const aarch64_operand
*self
,
1592 aarch64_opnd_info
*info
, aarch64_insn code
,
1593 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1597 info
->reglane
.regno
= extract_field (self
->fields
[0], code
, 0);
1598 val
= extract_fields (code
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
1599 if ((val
& 31) == 0)
1601 while ((val
& 1) == 0)
1603 info
->reglane
.index
= val
/ 2;
1607 /* Decode a logical immediate for the MOV alias of SVE DUPM. */
1609 aarch64_ext_sve_limm_mov (const aarch64_operand
*self
,
1610 aarch64_opnd_info
*info
, const aarch64_insn code
,
1611 const aarch64_inst
*inst
)
1613 int esize
= aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
);
1614 return (aarch64_ext_limm (self
, info
, code
, inst
)
1615 && aarch64_sve_dupm_mov_immediate_p (info
->imm
.value
, esize
));
1618 /* Decode Zn[MM], where Zn occupies the least-significant part of the field
1619 and where MM occupies the most-significant part. The operand-dependent
1620 value specifies the number of bits in Zn. */
1622 aarch64_ext_sve_quad_index (const aarch64_operand
*self
,
1623 aarch64_opnd_info
*info
, aarch64_insn code
,
1624 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1626 unsigned int reg_bits
= get_operand_specific_data (self
);
1627 unsigned int val
= extract_all_fields (self
, code
);
1628 info
->reglane
.regno
= val
& ((1 << reg_bits
) - 1);
1629 info
->reglane
.index
= val
>> reg_bits
;
1633 /* Decode {Zn.<T> - Zm.<T>}. The fields array specifies which field
1634 to use for Zn. The opcode-dependent value specifies the number
1635 of registers in the list. */
1637 aarch64_ext_sve_reglist (const aarch64_operand
*self
,
1638 aarch64_opnd_info
*info
, aarch64_insn code
,
1639 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1641 info
->reglist
.first_regno
= extract_field (self
->fields
[0], code
, 0);
1642 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
1646 /* Decode <pattern>{, MUL #<amount>}. The fields array specifies which
1647 fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
1650 aarch64_ext_sve_scale (const aarch64_operand
*self
,
1651 aarch64_opnd_info
*info
, aarch64_insn code
,
1652 const aarch64_inst
*inst
)
1656 if (!aarch64_ext_imm (self
, info
, code
, inst
))
1658 val
= extract_field (FLD_SVE_imm4
, code
, 0);
1659 info
->shifter
.kind
= AARCH64_MOD_MUL
;
1660 info
->shifter
.amount
= val
+ 1;
1661 info
->shifter
.operator_present
= (val
!= 0);
1662 info
->shifter
.amount_present
= (val
!= 0);
1666 /* Return the top set bit in VALUE, which is expected to be relatively
1669 get_top_bit (uint64_t value
)
1671 while ((value
& -value
) != value
)
1672 value
-= value
& -value
;
1676 /* Decode an SVE shift-left immediate. */
1678 aarch64_ext_sve_shlimm (const aarch64_operand
*self
,
1679 aarch64_opnd_info
*info
, const aarch64_insn code
,
1680 const aarch64_inst
*inst
)
1682 if (!aarch64_ext_imm (self
, info
, code
, inst
)
1683 || info
->imm
.value
== 0)
1686 info
->imm
.value
-= get_top_bit (info
->imm
.value
);
1690 /* Decode an SVE shift-right immediate. */
1692 aarch64_ext_sve_shrimm (const aarch64_operand
*self
,
1693 aarch64_opnd_info
*info
, const aarch64_insn code
,
1694 const aarch64_inst
*inst
)
1696 if (!aarch64_ext_imm (self
, info
, code
, inst
)
1697 || info
->imm
.value
== 0)
1700 info
->imm
.value
= get_top_bit (info
->imm
.value
) * 2 - info
->imm
.value
;
1704 /* Bitfields that are commonly used to encode certain operands' information
1705 may be partially used as part of the base opcode in some instructions.
1706 For example, the bit 1 of the field 'size' in
1707 FCVTXN <Vb><d>, <Va><n>
1708 is actually part of the base opcode, while only size<0> is available
1709 for encoding the register type. Another example is the AdvSIMD
1710 instruction ORR (register), in which the field 'size' is also used for
1711 the base opcode, leaving only the field 'Q' available to encode the
1712 vector register arrangement specifier '8B' or '16B'.
1714 This function tries to deduce the qualifier from the value of partially
1715 constrained field(s). Given the VALUE of such a field or fields, the
1716 qualifiers CANDIDATES and the MASK (indicating which bits are valid for
1717 operand encoding), the function returns the matching qualifier or
1718 AARCH64_OPND_QLF_NIL if nothing matches.
1720 N.B. CANDIDATES is a group of possible qualifiers that are valid for
1721 one operand; it has a maximum of AARCH64_MAX_QLF_SEQ_NUM qualifiers and
1722 may end with AARCH64_OPND_QLF_NIL. */
1724 static enum aarch64_opnd_qualifier
1725 get_qualifier_from_partial_encoding (aarch64_insn value
,
1726 const enum aarch64_opnd_qualifier
* \
1731 DEBUG_TRACE ("enter with value: %d, mask: %d", (int)value
, (int)mask
);
1732 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1734 aarch64_insn standard_value
;
1735 if (candidates
[i
] == AARCH64_OPND_QLF_NIL
)
1737 standard_value
= aarch64_get_qualifier_standard_value (candidates
[i
]);
1738 if ((standard_value
& mask
) == (value
& mask
))
1739 return candidates
[i
];
1741 return AARCH64_OPND_QLF_NIL
;
1744 /* Given a list of qualifier sequences, return all possible valid qualifiers
1745 for operand IDX in QUALIFIERS.
1746 Assume QUALIFIERS is an array whose length is large enough. */
1749 get_operand_possible_qualifiers (int idx
,
1750 const aarch64_opnd_qualifier_seq_t
*list
,
1751 enum aarch64_opnd_qualifier
*qualifiers
)
1754 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1755 if ((qualifiers
[i
] = list
[i
][idx
]) == AARCH64_OPND_QLF_NIL
)
1759 /* Decode the size Q field for e.g. SHADD.
1760 We tag one operand with the qualifer according to the code;
1761 whether the qualifier is valid for this opcode or not, it is the
1762 duty of the semantic checking. */
1765 decode_sizeq (aarch64_inst
*inst
)
1768 enum aarch64_opnd_qualifier qualifier
;
1770 aarch64_insn value
, mask
;
1771 enum aarch64_field_kind fld_sz
;
1772 enum aarch64_opnd_qualifier candidates
[AARCH64_MAX_QLF_SEQ_NUM
];
1774 if (inst
->opcode
->iclass
== asisdlse
1775 || inst
->opcode
->iclass
== asisdlsep
1776 || inst
->opcode
->iclass
== asisdlso
1777 || inst
->opcode
->iclass
== asisdlsop
)
1778 fld_sz
= FLD_vldst_size
;
1783 value
= extract_fields (code
, inst
->opcode
->mask
, 2, fld_sz
, FLD_Q
);
1784 /* Obtain the info that which bits of fields Q and size are actually
1785 available for operand encoding. Opcodes like FMAXNM and FMLA have
1786 size[1] unavailable. */
1787 mask
= extract_fields (~inst
->opcode
->mask
, 0, 2, fld_sz
, FLD_Q
);
1789 /* The index of the operand we are going to tag a qualifier and the qualifer
1790 itself are reasoned from the value of the size and Q fields and the
1791 possible valid qualifier lists. */
1792 idx
= aarch64_select_operand_for_sizeq_field_coding (inst
->opcode
);
1793 DEBUG_TRACE ("key idx: %d", idx
);
1795 /* For most related instruciton, size:Q are fully available for operand
1799 inst
->operands
[idx
].qualifier
= get_vreg_qualifier_from_value (value
);
1803 get_operand_possible_qualifiers (idx
, inst
->opcode
->qualifiers_list
,
1805 #ifdef DEBUG_AARCH64
1809 for (i
= 0; candidates
[i
] != AARCH64_OPND_QLF_NIL
1810 && i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1811 DEBUG_TRACE ("qualifier %d: %s", i
,
1812 aarch64_get_qualifier_name(candidates
[i
]));
1813 DEBUG_TRACE ("%d, %d", (int)value
, (int)mask
);
1815 #endif /* DEBUG_AARCH64 */
1817 qualifier
= get_qualifier_from_partial_encoding (value
, candidates
, mask
);
1819 if (qualifier
== AARCH64_OPND_QLF_NIL
)
1822 inst
->operands
[idx
].qualifier
= qualifier
;
1826 /* Decode size[0]:Q, i.e. bit 22 and bit 30, for
1827 e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1830 decode_asimd_fcvt (aarch64_inst
*inst
)
1832 aarch64_field field
= {0, 0};
1834 enum aarch64_opnd_qualifier qualifier
;
1836 gen_sub_field (FLD_size
, 0, 1, &field
);
1837 value
= extract_field_2 (&field
, inst
->value
, 0);
1838 qualifier
= value
== 0 ? AARCH64_OPND_QLF_V_4S
1839 : AARCH64_OPND_QLF_V_2D
;
1840 switch (inst
->opcode
->op
)
1844 /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1845 inst
->operands
[1].qualifier
= qualifier
;
1849 /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
1850 inst
->operands
[0].qualifier
= qualifier
;
1860 /* Decode size[0], i.e. bit 22, for
1861 e.g. FCVTXN <Vb><d>, <Va><n>. */
1864 decode_asisd_fcvtxn (aarch64_inst
*inst
)
1866 aarch64_field field
= {0, 0};
1867 gen_sub_field (FLD_size
, 0, 1, &field
);
1868 if (!extract_field_2 (&field
, inst
->value
, 0))
1870 inst
->operands
[0].qualifier
= AARCH64_OPND_QLF_S_S
;
1874 /* Decode the 'opc' field for e.g. FCVT <Dd>, <Sn>. */
1876 decode_fcvt (aarch64_inst
*inst
)
1878 enum aarch64_opnd_qualifier qualifier
;
1880 const aarch64_field field
= {15, 2};
1883 value
= extract_field_2 (&field
, inst
->value
, 0);
1886 case 0: qualifier
= AARCH64_OPND_QLF_S_S
; break;
1887 case 1: qualifier
= AARCH64_OPND_QLF_S_D
; break;
1888 case 3: qualifier
= AARCH64_OPND_QLF_S_H
; break;
1891 inst
->operands
[0].qualifier
= qualifier
;
1896 /* Do miscellaneous decodings that are not common enough to be driven by
1900 do_misc_decoding (aarch64_inst
*inst
)
1903 switch (inst
->opcode
->op
)
1906 return decode_fcvt (inst
);
1912 return decode_asimd_fcvt (inst
);
1915 return decode_asisd_fcvtxn (inst
);
1919 value
= extract_field (FLD_SVE_Pn
, inst
->value
, 0);
1920 return (value
== extract_field (FLD_SVE_Pm
, inst
->value
, 0)
1921 && value
== extract_field (FLD_SVE_Pg4_10
, inst
->value
, 0));
1924 return (extract_field (FLD_SVE_Zd
, inst
->value
, 0)
1925 == extract_field (FLD_SVE_Zm_16
, inst
->value
, 0));
1928 /* Index must be zero. */
1929 value
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
1930 return value
> 0 && value
<= 16 && value
== (value
& -value
);
1933 return (extract_field (FLD_SVE_Zn
, inst
->value
, 0)
1934 == extract_field (FLD_SVE_Zm_16
, inst
->value
, 0));
1937 /* Index must be nonzero. */
1938 value
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
1939 return value
> 0 && value
!= (value
& -value
);
1942 return (extract_field (FLD_SVE_Pd
, inst
->value
, 0)
1943 == extract_field (FLD_SVE_Pm
, inst
->value
, 0));
1945 case OP_MOVZS_P_P_P
:
1947 return (extract_field (FLD_SVE_Pn
, inst
->value
, 0)
1948 == extract_field (FLD_SVE_Pm
, inst
->value
, 0));
1950 case OP_NOTS_P_P_P_Z
:
1951 case OP_NOT_P_P_P_Z
:
1952 return (extract_field (FLD_SVE_Pm
, inst
->value
, 0)
1953 == extract_field (FLD_SVE_Pg4_10
, inst
->value
, 0));
1960 /* Opcodes that have fields shared by multiple operands are usually flagged
1961 with flags. In this function, we detect such flags, decode the related
1962 field(s) and store the information in one of the related operands. The
1963 'one' operand is not any operand but one of the operands that can
1964 accommadate all the information that has been decoded. */
1967 do_special_decoding (aarch64_inst
*inst
)
1971 /* Condition for truly conditional executed instructions, e.g. b.cond. */
1972 if (inst
->opcode
->flags
& F_COND
)
1974 value
= extract_field (FLD_cond2
, inst
->value
, 0);
1975 inst
->cond
= get_cond_from_value (value
);
1978 if (inst
->opcode
->flags
& F_SF
)
1980 idx
= select_operand_for_sf_field_coding (inst
->opcode
);
1981 value
= extract_field (FLD_sf
, inst
->value
, 0);
1982 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
1983 if ((inst
->opcode
->flags
& F_N
)
1984 && extract_field (FLD_N
, inst
->value
, 0) != value
)
1988 if (inst
->opcode
->flags
& F_LSE_SZ
)
1990 idx
= select_operand_for_sf_field_coding (inst
->opcode
);
1991 value
= extract_field (FLD_lse_sz
, inst
->value
, 0);
1992 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
1994 /* size:Q fields. */
1995 if (inst
->opcode
->flags
& F_SIZEQ
)
1996 return decode_sizeq (inst
);
1998 if (inst
->opcode
->flags
& F_FPTYPE
)
2000 idx
= select_operand_for_fptype_field_coding (inst
->opcode
);
2001 value
= extract_field (FLD_type
, inst
->value
, 0);
2004 case 0: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_S
; break;
2005 case 1: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_D
; break;
2006 case 3: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_H
; break;
2011 if (inst
->opcode
->flags
& F_SSIZE
)
2013 /* N.B. some opcodes like FCMGT <V><d>, <V><n>, #0 have the size[1] as part
2014 of the base opcode. */
2016 enum aarch64_opnd_qualifier candidates
[AARCH64_MAX_QLF_SEQ_NUM
];
2017 idx
= select_operand_for_scalar_size_field_coding (inst
->opcode
);
2018 value
= extract_field (FLD_size
, inst
->value
, inst
->opcode
->mask
);
2019 mask
= extract_field (FLD_size
, ~inst
->opcode
->mask
, 0);
2020 /* For most related instruciton, the 'size' field is fully available for
2021 operand encoding. */
2023 inst
->operands
[idx
].qualifier
= get_sreg_qualifier_from_value (value
);
2026 get_operand_possible_qualifiers (idx
, inst
->opcode
->qualifiers_list
,
2028 inst
->operands
[idx
].qualifier
2029 = get_qualifier_from_partial_encoding (value
, candidates
, mask
);
2033 if (inst
->opcode
->flags
& F_T
)
2035 /* Num of consecutive '0's on the right side of imm5<3:0>. */
2038 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
2039 == AARCH64_OPND_CLASS_SIMD_REG
);
2050 val
= extract_field (FLD_imm5
, inst
->value
, 0);
2051 while ((val
& 0x1) == 0 && ++num
<= 3)
2055 Q
= (unsigned) extract_field (FLD_Q
, inst
->value
, inst
->opcode
->mask
);
2056 inst
->operands
[0].qualifier
=
2057 get_vreg_qualifier_from_value ((num
<< 1) | Q
);
2060 if (inst
->opcode
->flags
& F_GPRSIZE_IN_Q
)
2062 /* Use Rt to encode in the case of e.g.
2063 STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
2064 idx
= aarch64_operand_index (inst
->opcode
->operands
, AARCH64_OPND_Rt
);
2067 /* Otherwise use the result operand, which has to be a integer
2069 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
2070 == AARCH64_OPND_CLASS_INT_REG
);
2073 assert (idx
== 0 || idx
== 1);
2074 value
= extract_field (FLD_Q
, inst
->value
, 0);
2075 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
2078 if (inst
->opcode
->flags
& F_LDS_SIZE
)
2080 aarch64_field field
= {0, 0};
2081 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
2082 == AARCH64_OPND_CLASS_INT_REG
);
2083 gen_sub_field (FLD_opc
, 0, 1, &field
);
2084 value
= extract_field_2 (&field
, inst
->value
, 0);
2085 inst
->operands
[0].qualifier
2086 = value
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
2089 /* Miscellaneous decoding; done as the last step. */
2090 if (inst
->opcode
->flags
& F_MISC
)
2091 return do_misc_decoding (inst
);
2096 /* Converters converting a real opcode instruction to its alias form. */
2098 /* ROR <Wd>, <Ws>, #<shift>
2100 EXTR <Wd>, <Ws>, <Ws>, #<shift>. */
2102 convert_extr_to_ror (aarch64_inst
*inst
)
2104 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
)
2106 copy_operand_info (inst
, 2, 3);
2107 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2113 /* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
2115 USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */
2117 convert_shll_to_xtl (aarch64_inst
*inst
)
2119 if (inst
->operands
[2].imm
.value
== 0)
2121 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2128 UBFM <Xd>, <Xn>, #<shift>, #63.
2130 LSR <Xd>, <Xn>, #<shift>. */
2132 convert_bfm_to_sr (aarch64_inst
*inst
)
2136 imms
= inst
->operands
[3].imm
.value
;
2137 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 31 : 63;
2140 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2147 /* Convert MOV to ORR. */
2149 convert_orr_to_mov (aarch64_inst
*inst
)
2151 /* MOV <Vd>.<T>, <Vn>.<T>
2153 ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>. */
2154 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
)
2156 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2162 /* When <imms> >= <immr>, the instruction written:
2163 SBFX <Xd>, <Xn>, #<lsb>, #<width>
2165 SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1). */
2168 convert_bfm_to_bfx (aarch64_inst
*inst
)
2172 immr
= inst
->operands
[2].imm
.value
;
2173 imms
= inst
->operands
[3].imm
.value
;
2177 inst
->operands
[2].imm
.value
= lsb
;
2178 inst
->operands
[3].imm
.value
= imms
+ 1 - lsb
;
2179 /* The two opcodes have different qualifiers for
2180 the immediate operands; reset to help the checking. */
2181 reset_operand_qualifier (inst
, 2);
2182 reset_operand_qualifier (inst
, 3);
2189 /* When <imms> < <immr>, the instruction written:
2190 SBFIZ <Xd>, <Xn>, #<lsb>, #<width>
2192 SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1). */
2195 convert_bfm_to_bfi (aarch64_inst
*inst
)
2197 int64_t immr
, imms
, val
;
2199 immr
= inst
->operands
[2].imm
.value
;
2200 imms
= inst
->operands
[3].imm
.value
;
2201 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 32 : 64;
2204 inst
->operands
[2].imm
.value
= (val
- immr
) & (val
- 1);
2205 inst
->operands
[3].imm
.value
= imms
+ 1;
2206 /* The two opcodes have different qualifiers for
2207 the immediate operands; reset to help the checking. */
2208 reset_operand_qualifier (inst
, 2);
2209 reset_operand_qualifier (inst
, 3);
2216 /* The instruction written:
2217 BFC <Xd>, #<lsb>, #<width>
2219 BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1). */
2222 convert_bfm_to_bfc (aarch64_inst
*inst
)
2224 int64_t immr
, imms
, val
;
2226 /* Should have been assured by the base opcode value. */
2227 assert (inst
->operands
[1].reg
.regno
== 0x1f);
2229 immr
= inst
->operands
[2].imm
.value
;
2230 imms
= inst
->operands
[3].imm
.value
;
2231 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 32 : 64;
2234 /* Drop XZR from the second operand. */
2235 copy_operand_info (inst
, 1, 2);
2236 copy_operand_info (inst
, 2, 3);
2237 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2239 /* Recalculate the immediates. */
2240 inst
->operands
[1].imm
.value
= (val
- immr
) & (val
- 1);
2241 inst
->operands
[2].imm
.value
= imms
+ 1;
2243 /* The two opcodes have different qualifiers for the operands; reset to
2244 help the checking. */
2245 reset_operand_qualifier (inst
, 1);
2246 reset_operand_qualifier (inst
, 2);
2247 reset_operand_qualifier (inst
, 3);
2255 /* The instruction written:
2256 LSL <Xd>, <Xn>, #<shift>
2258 UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */
2261 convert_ubfm_to_lsl (aarch64_inst
*inst
)
2263 int64_t immr
= inst
->operands
[2].imm
.value
;
2264 int64_t imms
= inst
->operands
[3].imm
.value
;
2266 = inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 31 : 63;
2268 if ((immr
== 0 && imms
== val
) || immr
== imms
+ 1)
2270 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2271 inst
->operands
[2].imm
.value
= val
- imms
;
2278 /* CINC <Wd>, <Wn>, <cond>
2280 CSINC <Wd>, <Wn>, <Wn>, invert(<cond>)
2281 where <cond> is not AL or NV. */
2284 convert_from_csel (aarch64_inst
*inst
)
2286 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
2287 && (inst
->operands
[3].cond
->value
& 0xe) != 0xe)
2289 copy_operand_info (inst
, 2, 3);
2290 inst
->operands
[2].cond
= get_inverted_cond (inst
->operands
[3].cond
);
2291 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2297 /* CSET <Wd>, <cond>
2299 CSINC <Wd>, WZR, WZR, invert(<cond>)
2300 where <cond> is not AL or NV. */
2303 convert_csinc_to_cset (aarch64_inst
*inst
)
2305 if (inst
->operands
[1].reg
.regno
== 0x1f
2306 && inst
->operands
[2].reg
.regno
== 0x1f
2307 && (inst
->operands
[3].cond
->value
& 0xe) != 0xe)
2309 copy_operand_info (inst
, 1, 3);
2310 inst
->operands
[1].cond
= get_inverted_cond (inst
->operands
[3].cond
);
2311 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2312 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2320 MOVZ <Wd>, #<imm16>, LSL #<shift>.
2322 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
2323 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
2324 or where a MOVN has an immediate that could be encoded by MOVZ, or where
2325 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
2326 machine-instruction mnemonic must be used. */
2329 convert_movewide_to_mov (aarch64_inst
*inst
)
2331 uint64_t value
= inst
->operands
[1].imm
.value
;
2332 /* MOVZ/MOVN #0 have a shift amount other than LSL #0. */
2333 if (value
== 0 && inst
->operands
[1].shifter
.amount
!= 0)
2335 inst
->operands
[1].type
= AARCH64_OPND_IMM_MOV
;
2336 inst
->operands
[1].shifter
.kind
= AARCH64_MOD_NONE
;
2337 value
<<= inst
->operands
[1].shifter
.amount
;
2338 /* As an alias convertor, it has to be clear that the INST->OPCODE
2339 is the opcode of the real instruction. */
2340 if (inst
->opcode
->op
== OP_MOVN
)
2342 int is32
= inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_W
;
2344 /* A MOVN has an immediate that could be encoded by MOVZ. */
2345 if (aarch64_wide_constant_p (value
, is32
, NULL
))
2348 inst
->operands
[1].imm
.value
= value
;
2349 inst
->operands
[1].shifter
.amount
= 0;
2355 ORR <Wd>, WZR, #<imm>.
2357 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
2358 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
2359 or where a MOVN has an immediate that could be encoded by MOVZ, or where
2360 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
2361 machine-instruction mnemonic must be used. */
2364 convert_movebitmask_to_mov (aarch64_inst
*inst
)
2369 /* Should have been assured by the base opcode value. */
2370 assert (inst
->operands
[1].reg
.regno
== 0x1f);
2371 copy_operand_info (inst
, 1, 2);
2372 is32
= inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_W
;
2373 inst
->operands
[1].type
= AARCH64_OPND_IMM_MOV
;
2374 value
= inst
->operands
[1].imm
.value
;
2375 /* ORR has an immediate that could be generated by a MOVZ or MOVN
2377 if (inst
->operands
[0].reg
.regno
!= 0x1f
2378 && (aarch64_wide_constant_p (value
, is32
, NULL
)
2379 || aarch64_wide_constant_p (~value
, is32
, NULL
)))
2382 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2386 /* Some alias opcodes are disassembled by being converted from their real-form.
2387 N.B. INST->OPCODE is the real opcode rather than the alias. */
2390 convert_to_alias (aarch64_inst
*inst
, const aarch64_opcode
*alias
)
2396 return convert_bfm_to_sr (inst
);
2398 return convert_ubfm_to_lsl (inst
);
2402 return convert_from_csel (inst
);
2405 return convert_csinc_to_cset (inst
);
2409 return convert_bfm_to_bfx (inst
);
2413 return convert_bfm_to_bfi (inst
);
2415 return convert_bfm_to_bfc (inst
);
2417 return convert_orr_to_mov (inst
);
2418 case OP_MOV_IMM_WIDE
:
2419 case OP_MOV_IMM_WIDEN
:
2420 return convert_movewide_to_mov (inst
);
2421 case OP_MOV_IMM_LOG
:
2422 return convert_movebitmask_to_mov (inst
);
2424 return convert_extr_to_ror (inst
);
2429 return convert_shll_to_xtl (inst
);
2435 static int aarch64_opcode_decode (const aarch64_opcode
*, const aarch64_insn
,
2436 aarch64_inst
*, int);
2438 /* Given the instruction information in *INST, check if the instruction has
2439 any alias form that can be used to represent *INST. If the answer is yes,
2440 update *INST to be in the form of the determined alias. */
2442 /* In the opcode description table, the following flags are used in opcode
2443 entries to help establish the relations between the real and alias opcodes:
2445 F_ALIAS: opcode is an alias
2446 F_HAS_ALIAS: opcode has alias(es)
2449 F_P3: Disassembly preference priority 1-3 (the larger the
2450 higher). If nothing is specified, it is the priority
2451 0 by default, i.e. the lowest priority.
2453 Although the relation between the machine and the alias instructions are not
2454 explicitly described, it can be easily determined from the base opcode
2455 values, masks and the flags F_ALIAS and F_HAS_ALIAS in their opcode
2456 description entries:
2458 The mask of an alias opcode must be equal to or a super-set (i.e. more
2459 constrained) of that of the aliased opcode; so is the base opcode value.
2461 if (opcode_has_alias (real) && alias_opcode_p (opcode)
2462 && (opcode->mask & real->mask) == real->mask
2463 && (real->mask & opcode->opcode) == (real->mask & real->opcode))
2464 then OPCODE is an alias of, and only of, the REAL instruction
2466 The alias relationship is forced flat-structured to keep related algorithm
2467 simple; an opcode entry cannot be flagged with both F_ALIAS and F_HAS_ALIAS.
2469 During the disassembling, the decoding decision tree (in
2470 opcodes/aarch64-dis-2.c) always returns an machine instruction opcode entry;
2471 if the decoding of such a machine instruction succeeds (and -Mno-aliases is
2472 not specified), the disassembler will check whether there is any alias
2473 instruction exists for this real instruction. If there is, the disassembler
2474 will try to disassemble the 32-bit binary again using the alias's rule, or
2475 try to convert the IR to the form of the alias. In the case of the multiple
2476 aliases, the aliases are tried one by one from the highest priority
2477 (currently the flag F_P3) to the lowest priority (no priority flag), and the
2478 first succeeds first adopted.
2480 You may ask why there is a need for the conversion of IR from one form to
2481 another in handling certain aliases. This is because on one hand it avoids
2482 adding more operand code to handle unusual encoding/decoding; on other
2483 hand, during the disassembling, the conversion is an effective approach to
2484 check the condition of an alias (as an alias may be adopted only if certain
2485 conditions are met).
2487 In order to speed up the alias opcode lookup, aarch64-gen has preprocessed
2488 aarch64_opcode_table and generated aarch64_find_alias_opcode and
2489 aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help. */
2492 determine_disassembling_preference (struct aarch64_inst
*inst
)
2494 const aarch64_opcode
*opcode
;
2495 const aarch64_opcode
*alias
;
2497 opcode
= inst
->opcode
;
2499 /* This opcode does not have an alias, so use itself. */
2500 if (!opcode_has_alias (opcode
))
2503 alias
= aarch64_find_alias_opcode (opcode
);
2506 #ifdef DEBUG_AARCH64
2509 const aarch64_opcode
*tmp
= alias
;
2510 printf ("#### LIST orderd: ");
2513 printf ("%s, ", tmp
->name
);
2514 tmp
= aarch64_find_next_alias_opcode (tmp
);
2518 #endif /* DEBUG_AARCH64 */
2520 for (; alias
; alias
= aarch64_find_next_alias_opcode (alias
))
2522 DEBUG_TRACE ("try %s", alias
->name
);
2523 assert (alias_opcode_p (alias
) || opcode_has_alias (opcode
));
2525 /* An alias can be a pseudo opcode which will never be used in the
2526 disassembly, e.g. BIC logical immediate is such a pseudo opcode
2528 if (pseudo_opcode_p (alias
))
2530 DEBUG_TRACE ("skip pseudo %s", alias
->name
);
2534 if ((inst
->value
& alias
->mask
) != alias
->opcode
)
2536 DEBUG_TRACE ("skip %s as base opcode not match", alias
->name
);
2539 /* No need to do any complicated transformation on operands, if the alias
2540 opcode does not have any operand. */
2541 if (aarch64_num_of_operands (alias
) == 0 && alias
->opcode
== inst
->value
)
2543 DEBUG_TRACE ("succeed with 0-operand opcode %s", alias
->name
);
2544 aarch64_replace_opcode (inst
, alias
);
2547 if (alias
->flags
& F_CONV
)
2550 memcpy (©
, inst
, sizeof (aarch64_inst
));
2551 /* ALIAS is the preference as long as the instruction can be
2552 successfully converted to the form of ALIAS. */
2553 if (convert_to_alias (©
, alias
) == 1)
2555 aarch64_replace_opcode (©
, alias
);
2556 assert (aarch64_match_operands_constraint (©
, NULL
));
2557 DEBUG_TRACE ("succeed with %s via conversion", alias
->name
);
2558 memcpy (inst
, ©
, sizeof (aarch64_inst
));
2564 /* Directly decode the alias opcode. */
2566 memset (&temp
, '\0', sizeof (aarch64_inst
));
2567 if (aarch64_opcode_decode (alias
, inst
->value
, &temp
, 1) == 1)
2569 DEBUG_TRACE ("succeed with %s via direct decoding", alias
->name
);
2570 memcpy (inst
, &temp
, sizeof (aarch64_inst
));
2577 /* Some instructions (including all SVE ones) use the instruction class
2578 to describe how a qualifiers_list index is represented in the instruction
2579 encoding. If INST is such an instruction, decode the appropriate fields
2580 and fill in the operand qualifiers accordingly. Return true if no
2581 problems are found. */
2584 aarch64_decode_variant_using_iclass (aarch64_inst
*inst
)
2589 switch (inst
->opcode
->iclass
)
2592 variant
= extract_fields (inst
->value
, 0, 2, FLD_size
, FLD_SVE_M_14
);
2596 i
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
2599 while ((i
& 1) == 0)
2607 /* Pick the smallest applicable element size. */
2608 if ((inst
->value
& 0x20600) == 0x600)
2610 else if ((inst
->value
& 0x20400) == 0x400)
2612 else if ((inst
->value
& 0x20000) == 0)
2619 /* sve_misc instructions have only a single variant. */
2623 variant
= extract_fields (inst
->value
, 0, 2, FLD_size
, FLD_SVE_M_16
);
2627 variant
= extract_field (FLD_SVE_M_4
, inst
->value
, 0);
2630 case sve_shift_pred
:
2631 i
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_SVE_tszl_8
);
2642 case sve_shift_unpred
:
2643 i
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_SVE_tszl_19
);
2647 variant
= extract_field (FLD_size
, inst
->value
, 0);
2653 variant
= extract_field (FLD_size
, inst
->value
, 0);
2657 i
= extract_field (FLD_size
, inst
->value
, 0);
2664 variant
= extract_field (FLD_SVE_sz
, inst
->value
, 0);
2668 /* No mapping between instruction class and qualifiers. */
2672 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2673 inst
->operands
[i
].qualifier
= inst
->opcode
->qualifiers_list
[variant
][i
];
2676 /* Decode the CODE according to OPCODE; fill INST. Return 0 if the decoding
2677 fails, which meanes that CODE is not an instruction of OPCODE; otherwise
2680 If OPCODE has alias(es) and NOALIASES_P is 0, an alias opcode may be
2681 determined and used to disassemble CODE; this is done just before the
2685 aarch64_opcode_decode (const aarch64_opcode
*opcode
, const aarch64_insn code
,
2686 aarch64_inst
*inst
, int noaliases_p
)
2690 DEBUG_TRACE ("enter with %s", opcode
->name
);
2692 assert (opcode
&& inst
);
2694 /* Check the base opcode. */
2695 if ((code
& opcode
->mask
) != (opcode
->opcode
& opcode
->mask
))
2697 DEBUG_TRACE ("base opcode match FAIL");
2702 memset (inst
, '\0', sizeof (aarch64_inst
));
2704 inst
->opcode
= opcode
;
2707 /* Assign operand codes and indexes. */
2708 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2710 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
)
2712 inst
->operands
[i
].type
= opcode
->operands
[i
];
2713 inst
->operands
[i
].idx
= i
;
2716 /* Call the opcode decoder indicated by flags. */
2717 if (opcode_has_special_coder (opcode
) && do_special_decoding (inst
) == 0)
2719 DEBUG_TRACE ("opcode flag-based decoder FAIL");
2723 /* Possibly use the instruction class to determine the correct
2725 if (!aarch64_decode_variant_using_iclass (inst
))
2727 DEBUG_TRACE ("iclass-based decoder FAIL");
2731 /* Call operand decoders. */
2732 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2734 const aarch64_operand
*opnd
;
2735 enum aarch64_opnd type
;
2737 type
= opcode
->operands
[i
];
2738 if (type
== AARCH64_OPND_NIL
)
2740 opnd
= &aarch64_operands
[type
];
2741 if (operand_has_extractor (opnd
)
2742 && (! aarch64_extract_operand (opnd
, &inst
->operands
[i
], code
, inst
)))
2744 DEBUG_TRACE ("operand decoder FAIL at operand %d", i
);
2749 /* If the opcode has a verifier, then check it now. */
2750 if (opcode
->verifier
&& ! opcode
->verifier (opcode
, code
))
2752 DEBUG_TRACE ("operand verifier FAIL");
2756 /* Match the qualifiers. */
2757 if (aarch64_match_operands_constraint (inst
, NULL
) == 1)
2759 /* Arriving here, the CODE has been determined as a valid instruction
2760 of OPCODE and *INST has been filled with information of this OPCODE
2761 instruction. Before the return, check if the instruction has any
2762 alias and should be disassembled in the form of its alias instead.
2763 If the answer is yes, *INST will be updated. */
2765 determine_disassembling_preference (inst
);
2766 DEBUG_TRACE ("SUCCESS");
2771 DEBUG_TRACE ("constraint matching FAIL");
2778 /* This does some user-friendly fix-up to *INST. It is currently focus on
2779 the adjustment of qualifiers to help the printed instruction
2780 recognized/understood more easily. */
2783 user_friendly_fixup (aarch64_inst
*inst
)
2785 switch (inst
->opcode
->iclass
)
2788 /* TBNZ Xn|Wn, #uimm6, label
2789 Test and Branch Not Zero: conditionally jumps to label if bit number
2790 uimm6 in register Xn is not zero. The bit number implies the width of
2791 the register, which may be written and should be disassembled as Wn if
2792 uimm is less than 32. Limited to a branch offset range of +/- 32KiB.
2794 if (inst
->operands
[1].imm
.value
< 32)
2795 inst
->operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
2801 /* Decode INSN and fill in *INST the instruction information. An alias
2802 opcode may be filled in *INSN if NOALIASES_P is FALSE. Return zero on
2806 aarch64_decode_insn (aarch64_insn insn
, aarch64_inst
*inst
,
2807 bfd_boolean noaliases_p
)
2809 const aarch64_opcode
*opcode
= aarch64_opcode_lookup (insn
);
2811 #ifdef DEBUG_AARCH64
2814 const aarch64_opcode
*tmp
= opcode
;
2816 DEBUG_TRACE ("opcode lookup:");
2819 aarch64_verbose (" %s", tmp
->name
);
2820 tmp
= aarch64_find_next_opcode (tmp
);
2823 #endif /* DEBUG_AARCH64 */
2825 /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot
2826 distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same
2827 opcode field and value, apart from the difference that one of them has an
2828 extra field as part of the opcode, but such a field is used for operand
2829 encoding in other opcode(s) ('immh' in the case of the example). */
2830 while (opcode
!= NULL
)
2832 /* But only one opcode can be decoded successfully for, as the
2833 decoding routine will check the constraint carefully. */
2834 if (aarch64_opcode_decode (opcode
, insn
, inst
, noaliases_p
) == 1)
2836 opcode
= aarch64_find_next_opcode (opcode
);
2842 /* Print operands. */
2845 print_operands (bfd_vma pc
, const aarch64_opcode
*opcode
,
2846 const aarch64_opnd_info
*opnds
, struct disassemble_info
*info
)
2848 int i
, pcrel_p
, num_printed
;
2849 for (i
= 0, num_printed
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2852 /* We regard the opcode operand info more, however we also look into
2853 the inst->operands to support the disassembling of the optional
2855 The two operand code should be the same in all cases, apart from
2856 when the operand can be optional. */
2857 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
2858 || opnds
[i
].type
== AARCH64_OPND_NIL
)
2861 /* Generate the operand string in STR. */
2862 aarch64_print_operand (str
, sizeof (str
), pc
, opcode
, opnds
, i
, &pcrel_p
,
2865 /* Print the delimiter (taking account of omitted operand(s)). */
2867 (*info
->fprintf_func
) (info
->stream
, "%s",
2868 num_printed
++ == 0 ? "\t" : ", ");
2870 /* Print the operand. */
2872 (*info
->print_address_func
) (info
->target
, info
);
2874 (*info
->fprintf_func
) (info
->stream
, "%s", str
);
2878 /* Set NAME to a copy of INST's mnemonic with the "." suffix removed. */
2881 remove_dot_suffix (char *name
, const aarch64_inst
*inst
)
2886 ptr
= strchr (inst
->opcode
->name
, '.');
2887 assert (ptr
&& inst
->cond
);
2888 len
= ptr
- inst
->opcode
->name
;
2890 strncpy (name
, inst
->opcode
->name
, len
);
2894 /* Print the instruction mnemonic name. */
2897 print_mnemonic_name (const aarch64_inst
*inst
, struct disassemble_info
*info
)
2899 if (inst
->opcode
->flags
& F_COND
)
2901 /* For instructions that are truly conditionally executed, e.g. b.cond,
2902 prepare the full mnemonic name with the corresponding condition
2906 remove_dot_suffix (name
, inst
);
2907 (*info
->fprintf_func
) (info
->stream
, "%s.%s", name
, inst
->cond
->names
[0]);
2910 (*info
->fprintf_func
) (info
->stream
, "%s", inst
->opcode
->name
);
2913 /* Decide whether we need to print a comment after the operands of
2914 instruction INST. */
2917 print_comment (const aarch64_inst
*inst
, struct disassemble_info
*info
)
2919 if (inst
->opcode
->flags
& F_COND
)
2922 unsigned int i
, num_conds
;
2924 remove_dot_suffix (name
, inst
);
2925 num_conds
= ARRAY_SIZE (inst
->cond
->names
);
2926 for (i
= 1; i
< num_conds
&& inst
->cond
->names
[i
]; ++i
)
2927 (*info
->fprintf_func
) (info
->stream
, "%s %s.%s",
2928 i
== 1 ? " //" : ",",
2929 name
, inst
->cond
->names
[i
]);
2933 /* Print the instruction according to *INST. */
2936 print_aarch64_insn (bfd_vma pc
, const aarch64_inst
*inst
,
2937 struct disassemble_info
*info
)
2939 print_mnemonic_name (inst
, info
);
2940 print_operands (pc
, inst
->opcode
, inst
->operands
, info
);
2941 print_comment (inst
, info
);
2944 /* Entry-point of the instruction disassembler and printer. */
2947 print_insn_aarch64_word (bfd_vma pc
,
2949 struct disassemble_info
*info
)
2951 static const char *err_msg
[6] =
2954 [-ERR_UND
] = "undefined",
2955 [-ERR_UNP
] = "unpredictable",
2962 info
->insn_info_valid
= 1;
2963 info
->branch_delay_insns
= 0;
2964 info
->data_size
= 0;
2968 if (info
->flags
& INSN_HAS_RELOC
)
2969 /* If the instruction has a reloc associated with it, then
2970 the offset field in the instruction will actually be the
2971 addend for the reloc. (If we are using REL type relocs).
2972 In such cases, we can ignore the pc when computing
2973 addresses, since the addend is not currently pc-relative. */
2976 ret
= aarch64_decode_insn (word
, &inst
, no_aliases
);
2978 if (((word
>> 21) & 0x3ff) == 1)
2980 /* RESERVED for ALES. */
2981 assert (ret
!= ERR_OK
);
2990 /* Handle undefined instructions. */
2991 info
->insn_type
= dis_noninsn
;
2992 (*info
->fprintf_func
) (info
->stream
,".inst\t0x%08x ; %s",
2993 word
, err_msg
[-ret
]);
2996 user_friendly_fixup (&inst
);
2997 print_aarch64_insn (pc
, &inst
, info
);
3004 /* Disallow mapping symbols ($x, $d etc) from
3005 being displayed in symbol relative addresses. */
3008 aarch64_symbol_is_valid (asymbol
* sym
,
3009 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
3016 name
= bfd_asymbol_name (sym
);
3020 || (name
[1] != 'x' && name
[1] != 'd')
3021 || (name
[2] != '\0' && name
[2] != '.'));
3024 /* Print data bytes on INFO->STREAM. */
3027 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
3029 struct disassemble_info
*info
)
3031 switch (info
->bytes_per_chunk
)
3034 info
->fprintf_func (info
->stream
, ".byte\t0x%02x", word
);
3037 info
->fprintf_func (info
->stream
, ".short\t0x%04x", word
);
3040 info
->fprintf_func (info
->stream
, ".word\t0x%08x", word
);
3047 /* Try to infer the code or data type from a symbol.
3048 Returns nonzero if *MAP_TYPE was set. */
3051 get_sym_code_type (struct disassemble_info
*info
, int n
,
3052 enum map_type
*map_type
)
3054 elf_symbol_type
*es
;
3058 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
3059 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
3061 /* If the symbol has function type then use that. */
3062 if (type
== STT_FUNC
)
3064 *map_type
= MAP_INSN
;
3068 /* Check for mapping symbols. */
3069 name
= bfd_asymbol_name(info
->symtab
[n
]);
3071 && (name
[1] == 'x' || name
[1] == 'd')
3072 && (name
[2] == '\0' || name
[2] == '.'))
3074 *map_type
= (name
[1] == 'x' ? MAP_INSN
: MAP_DATA
);
3081 /* Entry-point of the AArch64 disassembler. */
3084 print_insn_aarch64 (bfd_vma pc
,
3085 struct disassemble_info
*info
)
3087 bfd_byte buffer
[INSNLEN
];
3089 void (*printer
) (bfd_vma
, uint32_t, struct disassemble_info
*);
3090 bfd_boolean found
= FALSE
;
3091 unsigned int size
= 4;
3094 if (info
->disassembler_options
)
3096 set_default_aarch64_dis_options (info
);
3098 parse_aarch64_dis_options (info
->disassembler_options
);
3100 /* To avoid repeated parsing of these options, we remove them here. */
3101 info
->disassembler_options
= NULL
;
3104 /* Aarch64 instructions are always little-endian */
3105 info
->endian_code
= BFD_ENDIAN_LITTLE
;
3107 /* First check the full symtab for a mapping symbol, even if there
3108 are no usable non-mapping symbols for this address. */
3109 if (info
->symtab_size
!= 0
3110 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
3112 enum map_type type
= MAP_INSN
;
3117 if (pc
<= last_mapping_addr
)
3118 last_mapping_sym
= -1;
3120 /* Start scanning at the start of the function, or wherever
3121 we finished last time. */
3122 n
= info
->symtab_pos
+ 1;
3123 if (n
< last_mapping_sym
)
3124 n
= last_mapping_sym
;
3126 /* Scan up to the location being disassembled. */
3127 for (; n
< info
->symtab_size
; n
++)
3129 addr
= bfd_asymbol_value (info
->symtab
[n
]);
3132 if ((info
->section
== NULL
3133 || info
->section
== info
->symtab
[n
]->section
)
3134 && get_sym_code_type (info
, n
, &type
))
3143 n
= info
->symtab_pos
;
3144 if (n
< last_mapping_sym
)
3145 n
= last_mapping_sym
;
3147 /* No mapping symbol found at this address. Look backwards
3148 for a preceeding one. */
3151 if (get_sym_code_type (info
, n
, &type
))
3160 last_mapping_sym
= last_sym
;
3163 /* Look a little bit ahead to see if we should print out
3164 less than four bytes of data. If there's a symbol,
3165 mapping or otherwise, after two bytes then don't
3167 if (last_type
== MAP_DATA
)
3169 size
= 4 - (pc
& 3);
3170 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
3172 addr
= bfd_asymbol_value (info
->symtab
[n
]);
3175 if (addr
- pc
< size
)
3180 /* If the next symbol is after three bytes, we need to
3181 print only part of the data, so that we can use either
3184 size
= (pc
& 1) ? 1 : 2;
3188 if (last_type
== MAP_DATA
)
3190 /* size was set above. */
3191 info
->bytes_per_chunk
= size
;
3192 info
->display_endian
= info
->endian
;
3193 printer
= print_insn_data
;
3197 info
->bytes_per_chunk
= size
= INSNLEN
;
3198 info
->display_endian
= info
->endian_code
;
3199 printer
= print_insn_aarch64_word
;
3202 status
= (*info
->read_memory_func
) (pc
, buffer
, size
, info
);
3205 (*info
->memory_error_func
) (status
, pc
, info
);
3209 data
= bfd_get_bits (buffer
, size
* 8,
3210 info
->display_endian
== BFD_ENDIAN_BIG
);
3212 (*printer
) (pc
, data
, info
);
3218 print_aarch64_disassembler_options (FILE *stream
)
3220 fprintf (stream
, _("\n\
3221 The following AARCH64 specific disassembler options are supported for use\n\
3222 with the -M switch (multiple options should be separated by commas):\n"));
3224 fprintf (stream
, _("\n\
3225 no-aliases Don't print instruction aliases.\n"));
3227 fprintf (stream
, _("\n\
3228 aliases Do print instruction aliases.\n"));
3230 #ifdef DEBUG_AARCH64
3231 fprintf (stream
, _("\n\
3232 debug_dump Temp switch for debug trace.\n"));
3233 #endif /* DEBUG_AARCH64 */
3235 fprintf (stream
, _("\n"));