1 /* aarch64-opc.c -- AArch64 opcode support.
2 Copyright (C) 2009-2019 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
30 #include "libiberty.h"
32 #include "aarch64-opc.h"
35 int debug_dump
= FALSE
;
36 #endif /* DEBUG_AARCH64 */
38 /* The enumeration strings associated with each value of a 5-bit SVE
39 pattern operand. A null entry indicates a reserved meaning. */
40 const char *const aarch64_sve_pattern_array
[32] = {
79 /* The enumeration strings associated with each value of a 4-bit SVE
80 prefetch operand. A null entry indicates a reserved meaning. */
81 const char *const aarch64_sve_prfop_array
[16] = {
102 /* Helper functions to determine which operand to be used to encode/decode
103 the size:Q fields for AdvSIMD instructions. */
105 static inline bfd_boolean
106 vector_qualifier_p (enum aarch64_opnd_qualifier qualifier
)
108 return ((qualifier
>= AARCH64_OPND_QLF_V_8B
109 && qualifier
<= AARCH64_OPND_QLF_V_1Q
) ? TRUE
113 static inline bfd_boolean
114 fp_qualifier_p (enum aarch64_opnd_qualifier qualifier
)
116 return ((qualifier
>= AARCH64_OPND_QLF_S_B
117 && qualifier
<= AARCH64_OPND_QLF_S_Q
) ? TRUE
127 DP_VECTOR_ACROSS_LANES
,
130 static const char significant_operand_index
[] =
132 0, /* DP_UNKNOWN, by default using operand 0. */
133 0, /* DP_VECTOR_3SAME */
134 1, /* DP_VECTOR_LONG */
135 2, /* DP_VECTOR_WIDE */
136 1, /* DP_VECTOR_ACROSS_LANES */
139 /* Given a sequence of qualifiers in QUALIFIERS, determine and return
141 N.B. QUALIFIERS is a possible sequence of qualifiers each of which
142 corresponds to one of a sequence of operands. */
144 static enum data_pattern
145 get_data_pattern (const aarch64_opnd_qualifier_seq_t qualifiers
)
147 if (vector_qualifier_p (qualifiers
[0]) == TRUE
)
149 /* e.g. v.4s, v.4s, v.4s
150 or v.4h, v.4h, v.h[3]. */
151 if (qualifiers
[0] == qualifiers
[1]
152 && vector_qualifier_p (qualifiers
[2]) == TRUE
153 && (aarch64_get_qualifier_esize (qualifiers
[0])
154 == aarch64_get_qualifier_esize (qualifiers
[1]))
155 && (aarch64_get_qualifier_esize (qualifiers
[0])
156 == aarch64_get_qualifier_esize (qualifiers
[2])))
157 return DP_VECTOR_3SAME
;
158 /* e.g. v.8h, v.8b, v.8b.
159 or v.4s, v.4h, v.h[2].
161 if (vector_qualifier_p (qualifiers
[1]) == TRUE
162 && aarch64_get_qualifier_esize (qualifiers
[0]) != 0
163 && (aarch64_get_qualifier_esize (qualifiers
[0])
164 == aarch64_get_qualifier_esize (qualifiers
[1]) << 1))
165 return DP_VECTOR_LONG
;
166 /* e.g. v.8h, v.8h, v.8b. */
167 if (qualifiers
[0] == qualifiers
[1]
168 && vector_qualifier_p (qualifiers
[2]) == TRUE
169 && aarch64_get_qualifier_esize (qualifiers
[0]) != 0
170 && (aarch64_get_qualifier_esize (qualifiers
[0])
171 == aarch64_get_qualifier_esize (qualifiers
[2]) << 1)
172 && (aarch64_get_qualifier_esize (qualifiers
[0])
173 == aarch64_get_qualifier_esize (qualifiers
[1])))
174 return DP_VECTOR_WIDE
;
176 else if (fp_qualifier_p (qualifiers
[0]) == TRUE
)
178 /* e.g. SADDLV <V><d>, <Vn>.<T>. */
179 if (vector_qualifier_p (qualifiers
[1]) == TRUE
180 && qualifiers
[2] == AARCH64_OPND_QLF_NIL
)
181 return DP_VECTOR_ACROSS_LANES
;
187 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
188 the AdvSIMD instructions. */
189 /* N.B. it is possible to do some optimization that doesn't call
190 get_data_pattern each time when we need to select an operand. We can
191 either buffer the caculated the result or statically generate the data,
192 however, it is not obvious that the optimization will bring significant
196 aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode
*opcode
)
199 significant_operand_index
[get_data_pattern (opcode
->qualifiers_list
[0])];
202 const aarch64_field fields
[] =
205 { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
206 { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
207 { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
208 { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
209 { 5, 19 }, /* imm19: e.g. in CBZ. */
210 { 5, 19 }, /* immhi: e.g. in ADRP. */
211 { 29, 2 }, /* immlo: e.g. in ADRP. */
212 { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
213 { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
214 { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
215 { 30, 1 }, /* Q: in most AdvSIMD instructions. */
216 { 0, 5 }, /* Rt: in load/store instructions. */
217 { 0, 5 }, /* Rd: in many integer instructions. */
218 { 5, 5 }, /* Rn: in many integer instructions. */
219 { 10, 5 }, /* Rt2: in load/store pair instructions. */
220 { 10, 5 }, /* Ra: in fp instructions. */
221 { 5, 3 }, /* op2: in the system instructions. */
222 { 8, 4 }, /* CRm: in the system instructions. */
223 { 12, 4 }, /* CRn: in the system instructions. */
224 { 16, 3 }, /* op1: in the system instructions. */
225 { 19, 2 }, /* op0: in the system instructions. */
226 { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
227 { 12, 4 }, /* cond: condition flags as a source operand. */
228 { 12, 4 }, /* opcode: in advsimd load/store instructions. */
229 { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
230 { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
231 { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
232 { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
233 { 16, 5 }, /* Rs: in load/store exclusive instructions. */
234 { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
235 { 12, 1 }, /* S: in load/store reg offset instructions. */
236 { 21, 2 }, /* hw: in move wide constant instructions. */
237 { 22, 2 }, /* opc: in load/store reg offset instructions. */
238 { 23, 1 }, /* opc1: in load/store reg offset instructions. */
239 { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
240 { 22, 2 }, /* type: floating point type field in fp data inst. */
241 { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
242 { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */
243 { 15, 6 }, /* imm6_2: in rmif instructions. */
244 { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
245 { 0, 4 }, /* imm4_2: in rmif instructions. */
246 { 10, 4 }, /* imm4_3: in adddg/subg instructions. */
247 { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
248 { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
249 { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
250 { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
251 { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
252 { 5, 14 }, /* imm14: in test bit and branch instructions. */
253 { 5, 16 }, /* imm16: in exception instructions. */
254 { 0, 26 }, /* imm26: in unconditional branch instructions. */
255 { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
256 { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
257 { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
258 { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
259 { 22, 1 }, /* S: in LDRAA and LDRAB instructions. */
260 { 22, 1 }, /* N: in logical (immediate) instructions. */
261 { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
262 { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
263 { 31, 1 }, /* sf: in integer data processing instructions. */
264 { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */
265 { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
266 { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
267 { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
268 { 31, 1 }, /* b5: in the test bit and branch instructions. */
269 { 19, 5 }, /* b40: in the test bit and branch instructions. */
270 { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
271 { 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
272 { 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
273 { 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
274 { 17, 1 }, /* SVE_N: SVE equivalent of N. */
275 { 0, 4 }, /* SVE_Pd: p0-p15, bits [3,0]. */
276 { 10, 3 }, /* SVE_Pg3: p0-p7, bits [12,10]. */
277 { 5, 4 }, /* SVE_Pg4_5: p0-p15, bits [8,5]. */
278 { 10, 4 }, /* SVE_Pg4_10: p0-p15, bits [13,10]. */
279 { 16, 4 }, /* SVE_Pg4_16: p0-p15, bits [19,16]. */
280 { 16, 4 }, /* SVE_Pm: p0-p15, bits [19,16]. */
281 { 5, 4 }, /* SVE_Pn: p0-p15, bits [8,5]. */
282 { 0, 4 }, /* SVE_Pt: p0-p15, bits [3,0]. */
283 { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
284 { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
285 { 0, 5 }, /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */
286 { 5, 5 }, /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */
287 { 5, 5 }, /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */
288 { 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
289 { 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
290 { 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
291 { 5, 5 }, /* SVE_Zm_5: SVE vector register, bits [9,5]. */
292 { 16, 5 }, /* SVE_Zm_16: SVE vector register, bits [20,16]. */
293 { 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
294 { 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
295 { 5, 1 }, /* SVE_i1: single-bit immediate. */
296 { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
297 { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
298 { 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
299 { 20, 1 }, /* SVE_i2h: high bit of 2bit immediate, bits. */
300 { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
301 { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
302 { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
303 { 16, 5 }, /* SVE_imm5b: secondary 5-bit immediate field. */
304 { 16, 6 }, /* SVE_imm6: 6-bit immediate field. */
305 { 14, 7 }, /* SVE_imm7: 7-bit immediate field. */
306 { 5, 8 }, /* SVE_imm8: 8-bit immediate field. */
307 { 5, 9 }, /* SVE_imm9: 9-bit immediate field. */
308 { 11, 6 }, /* SVE_immr: SVE equivalent of immr. */
309 { 5, 6 }, /* SVE_imms: SVE equivalent of imms. */
310 { 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
311 { 5, 5 }, /* SVE_pattern: vector pattern enumeration. */
312 { 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
313 { 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
314 { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
315 { 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
316 { 22, 1 }, /* SVE_sz: 1-bit element size select. */
317 { 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */
318 { 30, 1 }, /* SVE_sz2: 1-bit element size select. */
319 { 16, 4 }, /* SVE_tsz: triangular size select. */
320 { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
321 { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */
322 { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
323 { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
324 { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
325 { 11, 2 }, /* rotate1: FCMLA immediate rotate. */
326 { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
327 { 12, 1 }, /* rotate3: FCADD immediate rotate. */
328 { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
329 { 22, 1 }, /* sz: 1-bit element size select. */
332 enum aarch64_operand_class
333 aarch64_get_operand_class (enum aarch64_opnd type
)
335 return aarch64_operands
[type
].op_class
;
339 aarch64_get_operand_name (enum aarch64_opnd type
)
341 return aarch64_operands
[type
].name
;
344 /* Get operand description string.
345 This is usually for the diagnosis purpose. */
347 aarch64_get_operand_desc (enum aarch64_opnd type
)
349 return aarch64_operands
[type
].desc
;
352 /* Table of all conditional affixes. */
353 const aarch64_cond aarch64_conds
[16] =
355 {{"eq", "none"}, 0x0},
356 {{"ne", "any"}, 0x1},
357 {{"cs", "hs", "nlast"}, 0x2},
358 {{"cc", "lo", "ul", "last"}, 0x3},
359 {{"mi", "first"}, 0x4},
360 {{"pl", "nfrst"}, 0x5},
363 {{"hi", "pmore"}, 0x8},
364 {{"ls", "plast"}, 0x9},
365 {{"ge", "tcont"}, 0xa},
366 {{"lt", "tstop"}, 0xb},
374 get_cond_from_value (aarch64_insn value
)
377 return &aarch64_conds
[(unsigned int) value
];
381 get_inverted_cond (const aarch64_cond
*cond
)
383 return &aarch64_conds
[cond
->value
^ 0x1];
386 /* Table describing the operand extension/shifting operators; indexed by
387 enum aarch64_modifier_kind.
389 The value column provides the most common values for encoding modifiers,
390 which enables table-driven encoding/decoding for the modifiers. */
391 const struct aarch64_name_value_pair aarch64_operand_modifiers
[] =
412 enum aarch64_modifier_kind
413 aarch64_get_operand_modifier (const struct aarch64_name_value_pair
*desc
)
415 return desc
- aarch64_operand_modifiers
;
419 aarch64_get_operand_modifier_value (enum aarch64_modifier_kind kind
)
421 return aarch64_operand_modifiers
[kind
].value
;
424 enum aarch64_modifier_kind
425 aarch64_get_operand_modifier_from_value (aarch64_insn value
,
426 bfd_boolean extend_p
)
428 if (extend_p
== TRUE
)
429 return AARCH64_MOD_UXTB
+ value
;
431 return AARCH64_MOD_LSL
- value
;
435 aarch64_extend_operator_p (enum aarch64_modifier_kind kind
)
437 return (kind
> AARCH64_MOD_LSL
&& kind
<= AARCH64_MOD_SXTX
)
441 static inline bfd_boolean
442 aarch64_shift_operator_p (enum aarch64_modifier_kind kind
)
444 return (kind
>= AARCH64_MOD_ROR
&& kind
<= AARCH64_MOD_LSL
)
448 const struct aarch64_name_value_pair aarch64_barrier_options
[16] =
468 /* Table describing the operands supported by the aliases of the HINT
471 The name column is the operand that is accepted for the alias. The value
472 column is the hint number of the alias. The list of operands is terminated
473 by NULL in the name column. */
475 const struct aarch64_name_value_pair aarch64_hint_options
[] =
477 /* BTI. This is also the F_DEFAULT entry for AARCH64_OPND_BTI_TARGET. */
478 { " ", HINT_ENCODE (HINT_OPD_F_NOPRINT
, 0x20) },
479 { "csync", HINT_OPD_CSYNC
}, /* PSB CSYNC. */
480 { "c", HINT_OPD_C
}, /* BTI C. */
481 { "j", HINT_OPD_J
}, /* BTI J. */
482 { "jc", HINT_OPD_JC
}, /* BTI JC. */
483 { NULL
, HINT_OPD_NULL
},
486 /* op -> op: load = 0 instruction = 1 store = 2
488 t -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1 */
489 #define B(op,l,t) (((op) << 3) | (((l) - 1) << 1) | (t))
490 const struct aarch64_name_value_pair aarch64_prfops
[32] =
492 { "pldl1keep", B(0, 1, 0) },
493 { "pldl1strm", B(0, 1, 1) },
494 { "pldl2keep", B(0, 2, 0) },
495 { "pldl2strm", B(0, 2, 1) },
496 { "pldl3keep", B(0, 3, 0) },
497 { "pldl3strm", B(0, 3, 1) },
500 { "plil1keep", B(1, 1, 0) },
501 { "plil1strm", B(1, 1, 1) },
502 { "plil2keep", B(1, 2, 0) },
503 { "plil2strm", B(1, 2, 1) },
504 { "plil3keep", B(1, 3, 0) },
505 { "plil3strm", B(1, 3, 1) },
508 { "pstl1keep", B(2, 1, 0) },
509 { "pstl1strm", B(2, 1, 1) },
510 { "pstl2keep", B(2, 2, 0) },
511 { "pstl2strm", B(2, 2, 1) },
512 { "pstl3keep", B(2, 3, 0) },
513 { "pstl3strm", B(2, 3, 1) },
527 /* Utilities on value constraint. */
530 value_in_range_p (int64_t value
, int low
, int high
)
532 return (value
>= low
&& value
<= high
) ? 1 : 0;
535 /* Return true if VALUE is a multiple of ALIGN. */
537 value_aligned_p (int64_t value
, int align
)
539 return (value
% align
) == 0;
542 /* A signed value fits in a field. */
544 value_fit_signed_field_p (int64_t value
, unsigned width
)
547 if (width
< sizeof (value
) * 8)
549 int64_t lim
= (int64_t)1 << (width
- 1);
550 if (value
>= -lim
&& value
< lim
)
556 /* An unsigned value fits in a field. */
558 value_fit_unsigned_field_p (int64_t value
, unsigned width
)
561 if (width
< sizeof (value
) * 8)
563 int64_t lim
= (int64_t)1 << width
;
564 if (value
>= 0 && value
< lim
)
570 /* Return 1 if OPERAND is SP or WSP. */
572 aarch64_stack_pointer_p (const aarch64_opnd_info
*operand
)
574 return ((aarch64_get_operand_class (operand
->type
)
575 == AARCH64_OPND_CLASS_INT_REG
)
576 && operand_maybe_stack_pointer (aarch64_operands
+ operand
->type
)
577 && operand
->reg
.regno
== 31);
580 /* Return 1 if OPERAND is XZR or WZP. */
582 aarch64_zero_register_p (const aarch64_opnd_info
*operand
)
584 return ((aarch64_get_operand_class (operand
->type
)
585 == AARCH64_OPND_CLASS_INT_REG
)
586 && !operand_maybe_stack_pointer (aarch64_operands
+ operand
->type
)
587 && operand
->reg
.regno
== 31);
590 /* Return true if the operand *OPERAND that has the operand code
591 OPERAND->TYPE and been qualified by OPERAND->QUALIFIER can be also
592 qualified by the qualifier TARGET. */
595 operand_also_qualified_p (const struct aarch64_opnd_info
*operand
,
596 aarch64_opnd_qualifier_t target
)
598 switch (operand
->qualifier
)
600 case AARCH64_OPND_QLF_W
:
601 if (target
== AARCH64_OPND_QLF_WSP
&& aarch64_stack_pointer_p (operand
))
604 case AARCH64_OPND_QLF_X
:
605 if (target
== AARCH64_OPND_QLF_SP
&& aarch64_stack_pointer_p (operand
))
608 case AARCH64_OPND_QLF_WSP
:
609 if (target
== AARCH64_OPND_QLF_W
610 && operand_maybe_stack_pointer (aarch64_operands
+ operand
->type
))
613 case AARCH64_OPND_QLF_SP
:
614 if (target
== AARCH64_OPND_QLF_X
615 && operand_maybe_stack_pointer (aarch64_operands
+ operand
->type
))
625 /* Given qualifier sequence list QSEQ_LIST and the known qualifier KNOWN_QLF
626 for operand KNOWN_IDX, return the expected qualifier for operand IDX.
628 Return NIL if more than one expected qualifiers are found. */
630 aarch64_opnd_qualifier_t
631 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t
*qseq_list
,
633 const aarch64_opnd_qualifier_t known_qlf
,
640 When the known qualifier is NIL, we have to assume that there is only
641 one qualifier sequence in the *QSEQ_LIST and return the corresponding
642 qualifier directly. One scenario is that for instruction
643 PRFM <prfop>, [<Xn|SP>, #:lo12:<symbol>]
644 which has only one possible valid qualifier sequence
646 the caller may pass NIL in KNOWN_QLF to obtain S_D so that it can
647 determine the correct relocation type (i.e. LDST64_LO12) for PRFM.
649 Because the qualifier NIL has dual roles in the qualifier sequence:
650 it can mean no qualifier for the operand, or the qualifer sequence is
651 not in use (when all qualifiers in the sequence are NILs), we have to
652 handle this special case here. */
653 if (known_qlf
== AARCH64_OPND_NIL
)
655 assert (qseq_list
[0][known_idx
] == AARCH64_OPND_NIL
);
656 return qseq_list
[0][idx
];
659 for (i
= 0, saved_i
= -1; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
661 if (qseq_list
[i
][known_idx
] == known_qlf
)
664 /* More than one sequences are found to have KNOWN_QLF at
666 return AARCH64_OPND_NIL
;
671 return qseq_list
[saved_i
][idx
];
674 enum operand_qualifier_kind
682 /* Operand qualifier description. */
683 struct operand_qualifier_data
685 /* The usage of the three data fields depends on the qualifier kind. */
692 enum operand_qualifier_kind kind
;
695 /* Indexed by the operand qualifier enumerators. */
696 struct operand_qualifier_data aarch64_opnd_qualifiers
[] =
698 {0, 0, 0, "NIL", OQK_NIL
},
700 /* Operand variant qualifiers.
702 element size, number of elements and common value for encoding. */
704 {4, 1, 0x0, "w", OQK_OPD_VARIANT
},
705 {8, 1, 0x1, "x", OQK_OPD_VARIANT
},
706 {4, 1, 0x0, "wsp", OQK_OPD_VARIANT
},
707 {8, 1, 0x1, "sp", OQK_OPD_VARIANT
},
709 {1, 1, 0x0, "b", OQK_OPD_VARIANT
},
710 {2, 1, 0x1, "h", OQK_OPD_VARIANT
},
711 {4, 1, 0x2, "s", OQK_OPD_VARIANT
},
712 {8, 1, 0x3, "d", OQK_OPD_VARIANT
},
713 {16, 1, 0x4, "q", OQK_OPD_VARIANT
},
714 {4, 1, 0x0, "4b", OQK_OPD_VARIANT
},
716 {1, 4, 0x0, "4b", OQK_OPD_VARIANT
},
717 {1, 8, 0x0, "8b", OQK_OPD_VARIANT
},
718 {1, 16, 0x1, "16b", OQK_OPD_VARIANT
},
719 {2, 2, 0x0, "2h", OQK_OPD_VARIANT
},
720 {2, 4, 0x2, "4h", OQK_OPD_VARIANT
},
721 {2, 8, 0x3, "8h", OQK_OPD_VARIANT
},
722 {4, 2, 0x4, "2s", OQK_OPD_VARIANT
},
723 {4, 4, 0x5, "4s", OQK_OPD_VARIANT
},
724 {8, 1, 0x6, "1d", OQK_OPD_VARIANT
},
725 {8, 2, 0x7, "2d", OQK_OPD_VARIANT
},
726 {16, 1, 0x8, "1q", OQK_OPD_VARIANT
},
728 {0, 0, 0, "z", OQK_OPD_VARIANT
},
729 {0, 0, 0, "m", OQK_OPD_VARIANT
},
731 /* Qualifier for scaled immediate for Tag granule (stg,st2g,etc). */
732 {16, 0, 0, "tag", OQK_OPD_VARIANT
},
734 /* Qualifiers constraining the value range.
736 Lower bound, higher bound, unused. */
738 {0, 15, 0, "CR", OQK_VALUE_IN_RANGE
},
739 {0, 7, 0, "imm_0_7" , OQK_VALUE_IN_RANGE
},
740 {0, 15, 0, "imm_0_15", OQK_VALUE_IN_RANGE
},
741 {0, 31, 0, "imm_0_31", OQK_VALUE_IN_RANGE
},
742 {0, 63, 0, "imm_0_63", OQK_VALUE_IN_RANGE
},
743 {1, 32, 0, "imm_1_32", OQK_VALUE_IN_RANGE
},
744 {1, 64, 0, "imm_1_64", OQK_VALUE_IN_RANGE
},
746 /* Qualifiers for miscellaneous purpose.
748 unused, unused and unused. */
753 {0, 0, 0, "retrieving", 0},
756 static inline bfd_boolean
757 operand_variant_qualifier_p (aarch64_opnd_qualifier_t qualifier
)
759 return (aarch64_opnd_qualifiers
[qualifier
].kind
== OQK_OPD_VARIANT
)
763 static inline bfd_boolean
764 qualifier_value_in_range_constraint_p (aarch64_opnd_qualifier_t qualifier
)
766 return (aarch64_opnd_qualifiers
[qualifier
].kind
== OQK_VALUE_IN_RANGE
)
771 aarch64_get_qualifier_name (aarch64_opnd_qualifier_t qualifier
)
773 return aarch64_opnd_qualifiers
[qualifier
].desc
;
776 /* Given an operand qualifier, return the expected data element size
777 of a qualified operand. */
779 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t qualifier
)
781 assert (operand_variant_qualifier_p (qualifier
) == TRUE
);
782 return aarch64_opnd_qualifiers
[qualifier
].data0
;
786 aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t qualifier
)
788 assert (operand_variant_qualifier_p (qualifier
) == TRUE
);
789 return aarch64_opnd_qualifiers
[qualifier
].data1
;
793 aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t qualifier
)
795 assert (operand_variant_qualifier_p (qualifier
) == TRUE
);
796 return aarch64_opnd_qualifiers
[qualifier
].data2
;
800 get_lower_bound (aarch64_opnd_qualifier_t qualifier
)
802 assert (qualifier_value_in_range_constraint_p (qualifier
) == TRUE
);
803 return aarch64_opnd_qualifiers
[qualifier
].data0
;
807 get_upper_bound (aarch64_opnd_qualifier_t qualifier
)
809 assert (qualifier_value_in_range_constraint_p (qualifier
) == TRUE
);
810 return aarch64_opnd_qualifiers
[qualifier
].data1
;
815 aarch64_verbose (const char *str
, ...)
826 dump_qualifier_sequence (const aarch64_opnd_qualifier_t
*qualifier
)
830 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
, ++qualifier
)
831 printf ("%s,", aarch64_get_qualifier_name (*qualifier
));
836 dump_match_qualifiers (const struct aarch64_opnd_info
*opnd
,
837 const aarch64_opnd_qualifier_t
*qualifier
)
840 aarch64_opnd_qualifier_t curr
[AARCH64_MAX_OPND_NUM
];
842 aarch64_verbose ("dump_match_qualifiers:");
843 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
844 curr
[i
] = opnd
[i
].qualifier
;
845 dump_qualifier_sequence (curr
);
846 aarch64_verbose ("against");
847 dump_qualifier_sequence (qualifier
);
849 #endif /* DEBUG_AARCH64 */
851 /* This function checks if the given instruction INSN is a destructive
852 instruction based on the usage of the registers. It does not recognize
853 unary destructive instructions. */
855 aarch64_is_destructive_by_operands (const aarch64_opcode
*opcode
)
858 const enum aarch64_opnd
*opnds
= opcode
->operands
;
860 if (opnds
[0] == AARCH64_OPND_NIL
)
863 while (opnds
[++i
] != AARCH64_OPND_NIL
)
864 if (opnds
[i
] == opnds
[0])
870 /* TODO improve this, we can have an extra field at the runtime to
871 store the number of operands rather than calculating it every time. */
874 aarch64_num_of_operands (const aarch64_opcode
*opcode
)
877 const enum aarch64_opnd
*opnds
= opcode
->operands
;
878 while (opnds
[i
++] != AARCH64_OPND_NIL
)
881 assert (i
>= 0 && i
<= AARCH64_MAX_OPND_NUM
);
885 /* Find the best matched qualifier sequence in *QUALIFIERS_LIST for INST.
886 If succeeds, fill the found sequence in *RET, return 1; otherwise return 0.
888 N.B. on the entry, it is very likely that only some operands in *INST
889 have had their qualifiers been established.
891 If STOP_AT is not -1, the function will only try to match
892 the qualifier sequence for operands before and including the operand
893 of index STOP_AT; and on success *RET will only be filled with the first
894 (STOP_AT+1) qualifiers.
896 A couple examples of the matching algorithm:
904 Apart from serving the main encoding routine, this can also be called
905 during or after the operand decoding. */
908 aarch64_find_best_match (const aarch64_inst
*inst
,
909 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
,
910 int stop_at
, aarch64_opnd_qualifier_t
*ret
)
914 const aarch64_opnd_qualifier_t
*qualifiers
;
916 num_opnds
= aarch64_num_of_operands (inst
->opcode
);
919 DEBUG_TRACE ("SUCCEED: no operand");
923 if (stop_at
< 0 || stop_at
>= num_opnds
)
924 stop_at
= num_opnds
- 1;
926 /* For each pattern. */
927 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
930 qualifiers
= *qualifiers_list
;
932 /* Start as positive. */
935 DEBUG_TRACE ("%d", i
);
938 dump_match_qualifiers (inst
->operands
, qualifiers
);
941 /* Most opcodes has much fewer patterns in the list.
942 First NIL qualifier indicates the end in the list. */
943 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
945 DEBUG_TRACE_IF (i
== 0, "SUCCEED: empty qualifier list");
951 for (j
= 0; j
< num_opnds
&& j
<= stop_at
; ++j
, ++qualifiers
)
953 if (inst
->operands
[j
].qualifier
== AARCH64_OPND_QLF_NIL
)
955 /* Either the operand does not have qualifier, or the qualifier
956 for the operand needs to be deduced from the qualifier
958 In the latter case, any constraint checking related with
959 the obtained qualifier should be done later in
960 operand_general_constraint_met_p. */
963 else if (*qualifiers
!= inst
->operands
[j
].qualifier
)
965 /* Unless the target qualifier can also qualify the operand
966 (which has already had a non-nil qualifier), non-equal
967 qualifiers are generally un-matched. */
968 if (operand_also_qualified_p (inst
->operands
+ j
, *qualifiers
))
977 continue; /* Equal qualifiers are certainly matched. */
980 /* Qualifiers established. */
987 /* Fill the result in *RET. */
989 qualifiers
= *qualifiers_list
;
991 DEBUG_TRACE ("complete qualifiers using list %d", i
);
994 dump_qualifier_sequence (qualifiers
);
997 for (j
= 0; j
<= stop_at
; ++j
, ++qualifiers
)
998 ret
[j
] = *qualifiers
;
999 for (; j
< AARCH64_MAX_OPND_NUM
; ++j
)
1000 ret
[j
] = AARCH64_OPND_QLF_NIL
;
1002 DEBUG_TRACE ("SUCCESS");
1006 DEBUG_TRACE ("FAIL");
1010 /* Operand qualifier matching and resolving.
1012 Return 1 if the operand qualifier(s) in *INST match one of the qualifier
1013 sequences in INST->OPCODE->qualifiers_list; otherwise return 0.
1015 if UPDATE_P == TRUE, update the qualifier(s) in *INST after the matching
1019 match_operands_qualifier (aarch64_inst
*inst
, bfd_boolean update_p
)
1022 aarch64_opnd_qualifier_seq_t qualifiers
;
1024 if (!aarch64_find_best_match (inst
, inst
->opcode
->qualifiers_list
, -1,
1027 DEBUG_TRACE ("matching FAIL");
1031 if (inst
->opcode
->flags
& F_STRICT
)
1033 /* Require an exact qualifier match, even for NIL qualifiers. */
1034 nops
= aarch64_num_of_operands (inst
->opcode
);
1035 for (i
= 0; i
< nops
; ++i
)
1036 if (inst
->operands
[i
].qualifier
!= qualifiers
[i
])
1040 /* Update the qualifiers. */
1041 if (update_p
== TRUE
)
1042 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
1044 if (inst
->opcode
->operands
[i
] == AARCH64_OPND_NIL
)
1046 DEBUG_TRACE_IF (inst
->operands
[i
].qualifier
!= qualifiers
[i
],
1047 "update %s with %s for operand %d",
1048 aarch64_get_qualifier_name (inst
->operands
[i
].qualifier
),
1049 aarch64_get_qualifier_name (qualifiers
[i
]), i
);
1050 inst
->operands
[i
].qualifier
= qualifiers
[i
];
1053 DEBUG_TRACE ("matching SUCCESS");
1057 /* Return TRUE if VALUE is a wide constant that can be moved into a general
1060 IS32 indicates whether value is a 32-bit immediate or not.
1061 If SHIFT_AMOUNT is not NULL, on the return of TRUE, the logical left shift
1062 amount will be returned in *SHIFT_AMOUNT. */
1065 aarch64_wide_constant_p (int64_t value
, int is32
, unsigned int *shift_amount
)
1069 DEBUG_TRACE ("enter with 0x%" PRIx64
"(%" PRIi64
")", value
, value
);
1073 /* Allow all zeros or all ones in top 32-bits, so that
1074 32-bit constant expressions like ~0x80000000 are
1076 uint64_t ext
= value
;
1077 if (ext
>> 32 != 0 && ext
>> 32 != (uint64_t) 0xffffffff)
1078 /* Immediate out of range. */
1080 value
&= (int64_t) 0xffffffff;
1083 /* first, try movz then movn */
1085 if ((value
& ((int64_t) 0xffff << 0)) == value
)
1087 else if ((value
& ((int64_t) 0xffff << 16)) == value
)
1089 else if (!is32
&& (value
& ((int64_t) 0xffff << 32)) == value
)
1091 else if (!is32
&& (value
& ((int64_t) 0xffff << 48)) == value
)
1096 DEBUG_TRACE ("exit FALSE with 0x%" PRIx64
"(%" PRIi64
")", value
, value
);
1100 if (shift_amount
!= NULL
)
1101 *shift_amount
= amount
;
1103 DEBUG_TRACE ("exit TRUE with amount %d", amount
);
1108 /* Build the accepted values for immediate logical SIMD instructions.
1110 The standard encodings of the immediate value are:
1111 N imms immr SIMD size R S
1112 1 ssssss rrrrrr 64 UInt(rrrrrr) UInt(ssssss)
1113 0 0sssss 0rrrrr 32 UInt(rrrrr) UInt(sssss)
1114 0 10ssss 00rrrr 16 UInt(rrrr) UInt(ssss)
1115 0 110sss 000rrr 8 UInt(rrr) UInt(sss)
1116 0 1110ss 0000rr 4 UInt(rr) UInt(ss)
1117 0 11110s 00000r 2 UInt(r) UInt(s)
1118 where all-ones value of S is reserved.
1120 Let's call E the SIMD size.
1122 The immediate value is: S+1 bits '1' rotated to the right by R.
1124 The total of valid encodings is 64*63 + 32*31 + ... + 2*1 = 5334
1125 (remember S != E - 1). */
1127 #define TOTAL_IMM_NB 5334
1132 aarch64_insn encoding
;
1133 } simd_imm_encoding
;
1135 static simd_imm_encoding simd_immediates
[TOTAL_IMM_NB
];
1138 simd_imm_encoding_cmp(const void *i1
, const void *i2
)
1140 const simd_imm_encoding
*imm1
= (const simd_imm_encoding
*)i1
;
1141 const simd_imm_encoding
*imm2
= (const simd_imm_encoding
*)i2
;
1143 if (imm1
->imm
< imm2
->imm
)
1145 if (imm1
->imm
> imm2
->imm
)
1150 /* immediate bitfield standard encoding
1151 imm13<12> imm13<5:0> imm13<11:6> SIMD size R S
1152 1 ssssss rrrrrr 64 rrrrrr ssssss
1153 0 0sssss 0rrrrr 32 rrrrr sssss
1154 0 10ssss 00rrrr 16 rrrr ssss
1155 0 110sss 000rrr 8 rrr sss
1156 0 1110ss 0000rr 4 rr ss
1157 0 11110s 00000r 2 r s */
1159 encode_immediate_bitfield (int is64
, uint32_t s
, uint32_t r
)
1161 return (is64
<< 12) | (r
<< 6) | s
;
1165 build_immediate_table (void)
1167 uint32_t log_e
, e
, s
, r
, s_mask
;
1173 for (log_e
= 1; log_e
<= 6; log_e
++)
1175 /* Get element size. */
1180 mask
= 0xffffffffffffffffull
;
1186 mask
= (1ull << e
) - 1;
1188 1 ((1 << 4) - 1) << 2 = 111100
1189 2 ((1 << 3) - 1) << 3 = 111000
1190 3 ((1 << 2) - 1) << 4 = 110000
1191 4 ((1 << 1) - 1) << 5 = 100000
1192 5 ((1 << 0) - 1) << 6 = 000000 */
1193 s_mask
= ((1u << (5 - log_e
)) - 1) << (log_e
+ 1);
1195 for (s
= 0; s
< e
- 1; s
++)
1196 for (r
= 0; r
< e
; r
++)
1198 /* s+1 consecutive bits to 1 (s < 63) */
1199 imm
= (1ull << (s
+ 1)) - 1;
1200 /* rotate right by r */
1202 imm
= (imm
>> r
) | ((imm
<< (e
- r
)) & mask
);
1203 /* replicate the constant depending on SIMD size */
1206 case 1: imm
= (imm
<< 2) | imm
;
1208 case 2: imm
= (imm
<< 4) | imm
;
1210 case 3: imm
= (imm
<< 8) | imm
;
1212 case 4: imm
= (imm
<< 16) | imm
;
1214 case 5: imm
= (imm
<< 32) | imm
;
1219 simd_immediates
[nb_imms
].imm
= imm
;
1220 simd_immediates
[nb_imms
].encoding
=
1221 encode_immediate_bitfield(is64
, s
| s_mask
, r
);
1225 assert (nb_imms
== TOTAL_IMM_NB
);
1226 qsort(simd_immediates
, nb_imms
,
1227 sizeof(simd_immediates
[0]), simd_imm_encoding_cmp
);
1230 /* Return TRUE if VALUE is a valid logical immediate, i.e. bitmask, that can
1231 be accepted by logical (immediate) instructions
1232 e.g. ORR <Xd|SP>, <Xn>, #<imm>.
1234 ESIZE is the number of bytes in the decoded immediate value.
1235 If ENCODING is not NULL, on the return of TRUE, the standard encoding for
1236 VALUE will be returned in *ENCODING. */
1239 aarch64_logical_immediate_p (uint64_t value
, int esize
, aarch64_insn
*encoding
)
1241 simd_imm_encoding imm_enc
;
1242 const simd_imm_encoding
*imm_encoding
;
1243 static bfd_boolean initialized
= FALSE
;
1247 DEBUG_TRACE ("enter with 0x%" PRIx64
"(%" PRIi64
"), esize: %d", value
,
1252 build_immediate_table ();
1256 /* Allow all zeros or all ones in top bits, so that
1257 constant expressions like ~1 are permitted. */
1258 upper
= (uint64_t) -1 << (esize
* 4) << (esize
* 4);
1259 if ((value
& ~upper
) != value
&& (value
| upper
) != value
)
1262 /* Replicate to a full 64-bit value. */
1264 for (i
= esize
* 8; i
< 64; i
*= 2)
1265 value
|= (value
<< i
);
1267 imm_enc
.imm
= value
;
1268 imm_encoding
= (const simd_imm_encoding
*)
1269 bsearch(&imm_enc
, simd_immediates
, TOTAL_IMM_NB
,
1270 sizeof(simd_immediates
[0]), simd_imm_encoding_cmp
);
1271 if (imm_encoding
== NULL
)
1273 DEBUG_TRACE ("exit with FALSE");
1276 if (encoding
!= NULL
)
1277 *encoding
= imm_encoding
->encoding
;
1278 DEBUG_TRACE ("exit with TRUE");
1282 /* If 64-bit immediate IMM is in the format of
1283 "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
1284 where a, b, c, d, e, f, g and h are independently 0 or 1, return an integer
1285 of value "abcdefgh". Otherwise return -1. */
1287 aarch64_shrink_expanded_imm8 (uint64_t imm
)
1293 for (i
= 0; i
< 8; i
++)
1295 byte
= (imm
>> (8 * i
)) & 0xff;
1298 else if (byte
!= 0x00)
1304 /* Utility inline functions for operand_general_constraint_met_p. */
1307 set_error (aarch64_operand_error
*mismatch_detail
,
1308 enum aarch64_operand_error_kind kind
, int idx
,
1311 if (mismatch_detail
== NULL
)
1313 mismatch_detail
->kind
= kind
;
1314 mismatch_detail
->index
= idx
;
1315 mismatch_detail
->error
= error
;
1319 set_syntax_error (aarch64_operand_error
*mismatch_detail
, int idx
,
1322 if (mismatch_detail
== NULL
)
1324 set_error (mismatch_detail
, AARCH64_OPDE_SYNTAX_ERROR
, idx
, error
);
1328 set_out_of_range_error (aarch64_operand_error
*mismatch_detail
,
1329 int idx
, int lower_bound
, int upper_bound
,
1332 if (mismatch_detail
== NULL
)
1334 set_error (mismatch_detail
, AARCH64_OPDE_OUT_OF_RANGE
, idx
, error
);
1335 mismatch_detail
->data
[0] = lower_bound
;
1336 mismatch_detail
->data
[1] = upper_bound
;
1340 set_imm_out_of_range_error (aarch64_operand_error
*mismatch_detail
,
1341 int idx
, int lower_bound
, int upper_bound
)
1343 if (mismatch_detail
== NULL
)
1345 set_out_of_range_error (mismatch_detail
, idx
, lower_bound
, upper_bound
,
1346 _("immediate value"));
1350 set_offset_out_of_range_error (aarch64_operand_error
*mismatch_detail
,
1351 int idx
, int lower_bound
, int upper_bound
)
1353 if (mismatch_detail
== NULL
)
1355 set_out_of_range_error (mismatch_detail
, idx
, lower_bound
, upper_bound
,
1356 _("immediate offset"));
1360 set_regno_out_of_range_error (aarch64_operand_error
*mismatch_detail
,
1361 int idx
, int lower_bound
, int upper_bound
)
1363 if (mismatch_detail
== NULL
)
1365 set_out_of_range_error (mismatch_detail
, idx
, lower_bound
, upper_bound
,
1366 _("register number"));
1370 set_elem_idx_out_of_range_error (aarch64_operand_error
*mismatch_detail
,
1371 int idx
, int lower_bound
, int upper_bound
)
1373 if (mismatch_detail
== NULL
)
1375 set_out_of_range_error (mismatch_detail
, idx
, lower_bound
, upper_bound
,
1376 _("register element index"));
1380 set_sft_amount_out_of_range_error (aarch64_operand_error
*mismatch_detail
,
1381 int idx
, int lower_bound
, int upper_bound
)
1383 if (mismatch_detail
== NULL
)
1385 set_out_of_range_error (mismatch_detail
, idx
, lower_bound
, upper_bound
,
1389 /* Report that the MUL modifier in operand IDX should be in the range
1390 [LOWER_BOUND, UPPER_BOUND]. */
1392 set_multiplier_out_of_range_error (aarch64_operand_error
*mismatch_detail
,
1393 int idx
, int lower_bound
, int upper_bound
)
1395 if (mismatch_detail
== NULL
)
1397 set_out_of_range_error (mismatch_detail
, idx
, lower_bound
, upper_bound
,
1402 set_unaligned_error (aarch64_operand_error
*mismatch_detail
, int idx
,
1405 if (mismatch_detail
== NULL
)
1407 set_error (mismatch_detail
, AARCH64_OPDE_UNALIGNED
, idx
, NULL
);
1408 mismatch_detail
->data
[0] = alignment
;
1412 set_reg_list_error (aarch64_operand_error
*mismatch_detail
, int idx
,
1415 if (mismatch_detail
== NULL
)
1417 set_error (mismatch_detail
, AARCH64_OPDE_REG_LIST
, idx
, NULL
);
1418 mismatch_detail
->data
[0] = expected_num
;
1422 set_other_error (aarch64_operand_error
*mismatch_detail
, int idx
,
1425 if (mismatch_detail
== NULL
)
1427 set_error (mismatch_detail
, AARCH64_OPDE_OTHER_ERROR
, idx
, error
);
1430 /* General constraint checking based on operand code.
1432 Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
1433 as the IDXth operand of opcode OPCODE. Otherwise return 0.
1435 This function has to be called after the qualifiers for all operands
1438 Mismatching error message is returned in *MISMATCH_DETAIL upon request,
1439 i.e. when MISMATCH_DETAIL is non-NULL. This avoids the generation
1440 of error message during the disassembling where error message is not
1441 wanted. We avoid the dynamic construction of strings of error messages
1442 here (i.e. in libopcodes), as it is costly and complicated; instead, we
1443 use a combination of error code, static string and some integer data to
1444 represent an error. */
1447 operand_general_constraint_met_p (const aarch64_opnd_info
*opnds
, int idx
,
1448 enum aarch64_opnd type
,
1449 const aarch64_opcode
*opcode
,
1450 aarch64_operand_error
*mismatch_detail
)
1452 unsigned num
, modifiers
, shift
;
1454 int64_t imm
, min_value
, max_value
;
1455 uint64_t uvalue
, mask
;
1456 const aarch64_opnd_info
*opnd
= opnds
+ idx
;
1457 aarch64_opnd_qualifier_t qualifier
= opnd
->qualifier
;
1459 assert (opcode
->operands
[idx
] == opnd
->type
&& opnd
->type
== type
);
1461 switch (aarch64_operands
[type
].op_class
)
1463 case AARCH64_OPND_CLASS_INT_REG
:
1464 /* Check pair reg constraints for cas* instructions. */
1465 if (type
== AARCH64_OPND_PAIRREG
)
1467 assert (idx
== 1 || idx
== 3);
1468 if (opnds
[idx
- 1].reg
.regno
% 2 != 0)
1470 set_syntax_error (mismatch_detail
, idx
- 1,
1471 _("reg pair must start from even reg"));
1474 if (opnds
[idx
].reg
.regno
!= opnds
[idx
- 1].reg
.regno
+ 1)
1476 set_syntax_error (mismatch_detail
, idx
,
1477 _("reg pair must be contiguous"));
1483 /* <Xt> may be optional in some IC and TLBI instructions. */
1484 if (type
== AARCH64_OPND_Rt_SYS
)
1486 assert (idx
== 1 && (aarch64_get_operand_class (opnds
[0].type
)
1487 == AARCH64_OPND_CLASS_SYSTEM
));
1488 if (opnds
[1].present
1489 && !aarch64_sys_ins_reg_has_xt (opnds
[0].sysins_op
))
1491 set_other_error (mismatch_detail
, idx
, _("extraneous register"));
1494 if (!opnds
[1].present
1495 && aarch64_sys_ins_reg_has_xt (opnds
[0].sysins_op
))
1497 set_other_error (mismatch_detail
, idx
, _("missing register"));
1503 case AARCH64_OPND_QLF_WSP
:
1504 case AARCH64_OPND_QLF_SP
:
1505 if (!aarch64_stack_pointer_p (opnd
))
1507 set_other_error (mismatch_detail
, idx
,
1508 _("stack pointer register expected"));
1517 case AARCH64_OPND_CLASS_SVE_REG
:
1520 case AARCH64_OPND_SVE_Zm3_INDEX
:
1521 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
1522 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
1523 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
1524 case AARCH64_OPND_SVE_Zm4_INDEX
:
1525 size
= get_operand_fields_width (get_operand_from_code (type
));
1526 shift
= get_operand_specific_data (&aarch64_operands
[type
]);
1527 mask
= (1 << shift
) - 1;
1528 if (opnd
->reg
.regno
> mask
)
1530 assert (mask
== 7 || mask
== 15);
1531 set_other_error (mismatch_detail
, idx
,
1533 ? _("z0-z15 expected")
1534 : _("z0-z7 expected"));
1537 mask
= (1 << (size
- shift
)) - 1;
1538 if (!value_in_range_p (opnd
->reglane
.index
, 0, mask
))
1540 set_elem_idx_out_of_range_error (mismatch_detail
, idx
, 0, mask
);
1545 case AARCH64_OPND_SVE_Zn_INDEX
:
1546 size
= aarch64_get_qualifier_esize (opnd
->qualifier
);
1547 if (!value_in_range_p (opnd
->reglane
.index
, 0, 64 / size
- 1))
1549 set_elem_idx_out_of_range_error (mismatch_detail
, idx
,
1555 case AARCH64_OPND_SVE_ZnxN
:
1556 case AARCH64_OPND_SVE_ZtxN
:
1557 if (opnd
->reglist
.num_regs
!= get_opcode_dependent_value (opcode
))
1559 set_other_error (mismatch_detail
, idx
,
1560 _("invalid register list"));
1570 case AARCH64_OPND_CLASS_PRED_REG
:
1571 if (opnd
->reg
.regno
>= 8
1572 && get_operand_fields_width (get_operand_from_code (type
)) == 3)
1574 set_other_error (mismatch_detail
, idx
, _("p0-p7 expected"));
1579 case AARCH64_OPND_CLASS_COND
:
1580 if (type
== AARCH64_OPND_COND1
1581 && (opnds
[idx
].cond
->value
& 0xe) == 0xe)
1583 /* Not allow AL or NV. */
1584 set_syntax_error (mismatch_detail
, idx
, NULL
);
1588 case AARCH64_OPND_CLASS_ADDRESS
:
1589 /* Check writeback. */
1590 switch (opcode
->iclass
)
1594 case ldstnapair_offs
:
1597 if (opnd
->addr
.writeback
== 1)
1599 set_syntax_error (mismatch_detail
, idx
,
1600 _("unexpected address writeback"));
1605 if (opnd
->addr
.writeback
== 1 && opnd
->addr
.preind
!= 1)
1607 set_syntax_error (mismatch_detail
, idx
,
1608 _("unexpected address writeback"));
1613 case ldstpair_indexed
:
1616 if (opnd
->addr
.writeback
== 0)
1618 set_syntax_error (mismatch_detail
, idx
,
1619 _("address writeback expected"));
1624 assert (opnd
->addr
.writeback
== 0);
1629 case AARCH64_OPND_ADDR_SIMM7
:
1630 /* Scaled signed 7 bits immediate offset. */
1631 /* Get the size of the data element that is accessed, which may be
1632 different from that of the source register size,
1633 e.g. in strb/ldrb. */
1634 size
= aarch64_get_qualifier_esize (opnd
->qualifier
);
1635 if (!value_in_range_p (opnd
->addr
.offset
.imm
, -64 * size
, 63 * size
))
1637 set_offset_out_of_range_error (mismatch_detail
, idx
,
1638 -64 * size
, 63 * size
);
1641 if (!value_aligned_p (opnd
->addr
.offset
.imm
, size
))
1643 set_unaligned_error (mismatch_detail
, idx
, size
);
1647 case AARCH64_OPND_ADDR_OFFSET
:
1648 case AARCH64_OPND_ADDR_SIMM9
:
1649 /* Unscaled signed 9 bits immediate offset. */
1650 if (!value_in_range_p (opnd
->addr
.offset
.imm
, -256, 255))
1652 set_offset_out_of_range_error (mismatch_detail
, idx
, -256, 255);
1657 case AARCH64_OPND_ADDR_SIMM9_2
:
1658 /* Unscaled signed 9 bits immediate offset, which has to be negative
1660 size
= aarch64_get_qualifier_esize (qualifier
);
1661 if ((value_in_range_p (opnd
->addr
.offset
.imm
, 0, 255)
1662 && !value_aligned_p (opnd
->addr
.offset
.imm
, size
))
1663 || value_in_range_p (opnd
->addr
.offset
.imm
, -256, -1))
1665 set_other_error (mismatch_detail
, idx
,
1666 _("negative or unaligned offset expected"));
1669 case AARCH64_OPND_ADDR_SIMM10
:
1670 /* Scaled signed 10 bits immediate offset. */
1671 if (!value_in_range_p (opnd
->addr
.offset
.imm
, -4096, 4088))
1673 set_offset_out_of_range_error (mismatch_detail
, idx
, -4096, 4088);
1676 if (!value_aligned_p (opnd
->addr
.offset
.imm
, 8))
1678 set_unaligned_error (mismatch_detail
, idx
, 8);
1683 case AARCH64_OPND_ADDR_SIMM11
:
1684 /* Signed 11 bits immediate offset (multiple of 16). */
1685 if (!value_in_range_p (opnd
->addr
.offset
.imm
, -1024, 1008))
1687 set_offset_out_of_range_error (mismatch_detail
, idx
, -1024, 1008);
1691 if (!value_aligned_p (opnd
->addr
.offset
.imm
, 16))
1693 set_unaligned_error (mismatch_detail
, idx
, 16);
1698 case AARCH64_OPND_ADDR_SIMM13
:
1699 /* Signed 13 bits immediate offset (multiple of 16). */
1700 if (!value_in_range_p (opnd
->addr
.offset
.imm
, -4096, 4080))
1702 set_offset_out_of_range_error (mismatch_detail
, idx
, -4096, 4080);
1706 if (!value_aligned_p (opnd
->addr
.offset
.imm
, 16))
1708 set_unaligned_error (mismatch_detail
, idx
, 16);
1713 case AARCH64_OPND_SIMD_ADDR_POST
:
1714 /* AdvSIMD load/store multiple structures, post-index. */
1716 if (opnd
->addr
.offset
.is_reg
)
1718 if (value_in_range_p (opnd
->addr
.offset
.regno
, 0, 30))
1722 set_other_error (mismatch_detail
, idx
,
1723 _("invalid register offset"));
1729 const aarch64_opnd_info
*prev
= &opnds
[idx
-1];
1730 unsigned num_bytes
; /* total number of bytes transferred. */
1731 /* The opcode dependent area stores the number of elements in
1732 each structure to be loaded/stored. */
1733 int is_ld1r
= get_opcode_dependent_value (opcode
) == 1;
1734 if (opcode
->operands
[0] == AARCH64_OPND_LVt_AL
)
1735 /* Special handling of loading single structure to all lane. */
1736 num_bytes
= (is_ld1r
? 1 : prev
->reglist
.num_regs
)
1737 * aarch64_get_qualifier_esize (prev
->qualifier
);
1739 num_bytes
= prev
->reglist
.num_regs
1740 * aarch64_get_qualifier_esize (prev
->qualifier
)
1741 * aarch64_get_qualifier_nelem (prev
->qualifier
);
1742 if ((int) num_bytes
!= opnd
->addr
.offset
.imm
)
1744 set_other_error (mismatch_detail
, idx
,
1745 _("invalid post-increment amount"));
1751 case AARCH64_OPND_ADDR_REGOFF
:
1752 /* Get the size of the data element that is accessed, which may be
1753 different from that of the source register size,
1754 e.g. in strb/ldrb. */
1755 size
= aarch64_get_qualifier_esize (opnd
->qualifier
);
1756 /* It is either no shift or shift by the binary logarithm of SIZE. */
1757 if (opnd
->shifter
.amount
!= 0
1758 && opnd
->shifter
.amount
!= (int)get_logsz (size
))
1760 set_other_error (mismatch_detail
, idx
,
1761 _("invalid shift amount"));
1764 /* Only UXTW, LSL, SXTW and SXTX are the accepted extending
1766 switch (opnd
->shifter
.kind
)
1768 case AARCH64_MOD_UXTW
:
1769 case AARCH64_MOD_LSL
:
1770 case AARCH64_MOD_SXTW
:
1771 case AARCH64_MOD_SXTX
: break;
1773 set_other_error (mismatch_detail
, idx
,
1774 _("invalid extend/shift operator"));
1779 case AARCH64_OPND_ADDR_UIMM12
:
1780 imm
= opnd
->addr
.offset
.imm
;
1781 /* Get the size of the data element that is accessed, which may be
1782 different from that of the source register size,
1783 e.g. in strb/ldrb. */
1784 size
= aarch64_get_qualifier_esize (qualifier
);
1785 if (!value_in_range_p (opnd
->addr
.offset
.imm
, 0, 4095 * size
))
1787 set_offset_out_of_range_error (mismatch_detail
, idx
,
1791 if (!value_aligned_p (opnd
->addr
.offset
.imm
, size
))
1793 set_unaligned_error (mismatch_detail
, idx
, size
);
1798 case AARCH64_OPND_ADDR_PCREL14
:
1799 case AARCH64_OPND_ADDR_PCREL19
:
1800 case AARCH64_OPND_ADDR_PCREL21
:
1801 case AARCH64_OPND_ADDR_PCREL26
:
1802 imm
= opnd
->imm
.value
;
1803 if (operand_need_shift_by_two (get_operand_from_code (type
)))
1805 /* The offset value in a PC-relative branch instruction is alway
1806 4-byte aligned and is encoded without the lowest 2 bits. */
1807 if (!value_aligned_p (imm
, 4))
1809 set_unaligned_error (mismatch_detail
, idx
, 4);
1812 /* Right shift by 2 so that we can carry out the following check
1816 size
= get_operand_fields_width (get_operand_from_code (type
));
1817 if (!value_fit_signed_field_p (imm
, size
))
1819 set_other_error (mismatch_detail
, idx
,
1820 _("immediate out of range"));
1825 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
1826 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
1827 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
1828 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
1832 assert (!opnd
->addr
.offset
.is_reg
);
1833 assert (opnd
->addr
.preind
);
1834 num
= 1 + get_operand_specific_data (&aarch64_operands
[type
]);
1837 if ((opnd
->addr
.offset
.imm
!= 0 && !opnd
->shifter
.operator_present
)
1838 || (opnd
->shifter
.operator_present
1839 && opnd
->shifter
.kind
!= AARCH64_MOD_MUL_VL
))
1841 set_other_error (mismatch_detail
, idx
,
1842 _("invalid addressing mode"));
1845 if (!value_in_range_p (opnd
->addr
.offset
.imm
, min_value
, max_value
))
1847 set_offset_out_of_range_error (mismatch_detail
, idx
,
1848 min_value
, max_value
);
1851 if (!value_aligned_p (opnd
->addr
.offset
.imm
, num
))
1853 set_unaligned_error (mismatch_detail
, idx
, num
);
1858 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
1861 goto sve_imm_offset_vl
;
1863 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
1866 goto sve_imm_offset_vl
;
1868 case AARCH64_OPND_SVE_ADDR_RI_U6
:
1869 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
1870 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
1871 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
1875 assert (!opnd
->addr
.offset
.is_reg
);
1876 assert (opnd
->addr
.preind
);
1877 num
= 1 << get_operand_specific_data (&aarch64_operands
[type
]);
1880 if (opnd
->shifter
.operator_present
1881 || opnd
->shifter
.amount_present
)
1883 set_other_error (mismatch_detail
, idx
,
1884 _("invalid addressing mode"));
1887 if (!value_in_range_p (opnd
->addr
.offset
.imm
, min_value
, max_value
))
1889 set_offset_out_of_range_error (mismatch_detail
, idx
,
1890 min_value
, max_value
);
1893 if (!value_aligned_p (opnd
->addr
.offset
.imm
, num
))
1895 set_unaligned_error (mismatch_detail
, idx
, num
);
1900 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
1903 goto sve_imm_offset
;
1905 case AARCH64_OPND_SVE_ADDR_ZX
:
1906 /* Everything is already ensured by parse_operands or
1907 aarch64_ext_sve_addr_rr_lsl (because this is a very specific
1909 assert (opnd
->addr
.offset
.is_reg
);
1910 assert (opnd
->addr
.preind
);
1911 assert ((aarch64_operands
[type
].flags
& OPD_F_NO_ZR
) == 0);
1912 assert (opnd
->shifter
.kind
== AARCH64_MOD_LSL
);
1913 assert (opnd
->shifter
.operator_present
== 0);
1916 case AARCH64_OPND_SVE_ADDR_R
:
1917 case AARCH64_OPND_SVE_ADDR_RR
:
1918 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
1919 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
1920 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
1921 case AARCH64_OPND_SVE_ADDR_RX
:
1922 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
1923 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
1924 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
1925 case AARCH64_OPND_SVE_ADDR_RZ
:
1926 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
1927 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
1928 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
1929 modifiers
= 1 << AARCH64_MOD_LSL
;
1931 assert (opnd
->addr
.offset
.is_reg
);
1932 assert (opnd
->addr
.preind
);
1933 if ((aarch64_operands
[type
].flags
& OPD_F_NO_ZR
) != 0
1934 && opnd
->addr
.offset
.regno
== 31)
1936 set_other_error (mismatch_detail
, idx
,
1937 _("index register xzr is not allowed"));
1940 if (((1 << opnd
->shifter
.kind
) & modifiers
) == 0
1941 || (opnd
->shifter
.amount
1942 != get_operand_specific_data (&aarch64_operands
[type
])))
1944 set_other_error (mismatch_detail
, idx
,
1945 _("invalid addressing mode"));
1950 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
1951 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
1952 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
1953 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
1954 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
1955 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
1956 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
1957 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
1958 modifiers
= (1 << AARCH64_MOD_SXTW
) | (1 << AARCH64_MOD_UXTW
);
1959 goto sve_rr_operand
;
1961 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
1962 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
1963 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
1964 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
1967 goto sve_imm_offset
;
1969 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
1970 modifiers
= 1 << AARCH64_MOD_LSL
;
1972 assert (opnd
->addr
.offset
.is_reg
);
1973 assert (opnd
->addr
.preind
);
1974 if (((1 << opnd
->shifter
.kind
) & modifiers
) == 0
1975 || opnd
->shifter
.amount
< 0
1976 || opnd
->shifter
.amount
> 3)
1978 set_other_error (mismatch_detail
, idx
,
1979 _("invalid addressing mode"));
1984 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
1985 modifiers
= (1 << AARCH64_MOD_SXTW
);
1986 goto sve_zz_operand
;
1988 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
1989 modifiers
= 1 << AARCH64_MOD_UXTW
;
1990 goto sve_zz_operand
;
1997 case AARCH64_OPND_CLASS_SIMD_REGLIST
:
1998 if (type
== AARCH64_OPND_LEt
)
2000 /* Get the upper bound for the element index. */
2001 num
= 16 / aarch64_get_qualifier_esize (qualifier
) - 1;
2002 if (!value_in_range_p (opnd
->reglist
.index
, 0, num
))
2004 set_elem_idx_out_of_range_error (mismatch_detail
, idx
, 0, num
);
2008 /* The opcode dependent area stores the number of elements in
2009 each structure to be loaded/stored. */
2010 num
= get_opcode_dependent_value (opcode
);
2013 case AARCH64_OPND_LVt
:
2014 assert (num
>= 1 && num
<= 4);
2015 /* Unless LD1/ST1, the number of registers should be equal to that
2016 of the structure elements. */
2017 if (num
!= 1 && opnd
->reglist
.num_regs
!= num
)
2019 set_reg_list_error (mismatch_detail
, idx
, num
);
2023 case AARCH64_OPND_LVt_AL
:
2024 case AARCH64_OPND_LEt
:
2025 assert (num
>= 1 && num
<= 4);
2026 /* The number of registers should be equal to that of the structure
2028 if (opnd
->reglist
.num_regs
!= num
)
2030 set_reg_list_error (mismatch_detail
, idx
, num
);
2039 case AARCH64_OPND_CLASS_IMMEDIATE
:
2040 /* Constraint check on immediate operand. */
2041 imm
= opnd
->imm
.value
;
2042 /* E.g. imm_0_31 constrains value to be 0..31. */
2043 if (qualifier_value_in_range_constraint_p (qualifier
)
2044 && !value_in_range_p (imm
, get_lower_bound (qualifier
),
2045 get_upper_bound (qualifier
)))
2047 set_imm_out_of_range_error (mismatch_detail
, idx
,
2048 get_lower_bound (qualifier
),
2049 get_upper_bound (qualifier
));
2055 case AARCH64_OPND_AIMM
:
2056 if (opnd
->shifter
.kind
!= AARCH64_MOD_LSL
)
2058 set_other_error (mismatch_detail
, idx
,
2059 _("invalid shift operator"));
2062 if (opnd
->shifter
.amount
!= 0 && opnd
->shifter
.amount
!= 12)
2064 set_other_error (mismatch_detail
, idx
,
2065 _("shift amount must be 0 or 12"));
2068 if (!value_fit_unsigned_field_p (opnd
->imm
.value
, 12))
2070 set_other_error (mismatch_detail
, idx
,
2071 _("immediate out of range"));
2076 case AARCH64_OPND_HALF
:
2077 assert (idx
== 1 && opnds
[0].type
== AARCH64_OPND_Rd
);
2078 if (opnd
->shifter
.kind
!= AARCH64_MOD_LSL
)
2080 set_other_error (mismatch_detail
, idx
,
2081 _("invalid shift operator"));
2084 size
= aarch64_get_qualifier_esize (opnds
[0].qualifier
);
2085 if (!value_aligned_p (opnd
->shifter
.amount
, 16))
2087 set_other_error (mismatch_detail
, idx
,
2088 _("shift amount must be a multiple of 16"));
2091 if (!value_in_range_p (opnd
->shifter
.amount
, 0, size
* 8 - 16))
2093 set_sft_amount_out_of_range_error (mismatch_detail
, idx
,
2097 if (opnd
->imm
.value
< 0)
2099 set_other_error (mismatch_detail
, idx
,
2100 _("negative immediate value not allowed"));
2103 if (!value_fit_unsigned_field_p (opnd
->imm
.value
, 16))
2105 set_other_error (mismatch_detail
, idx
,
2106 _("immediate out of range"));
2111 case AARCH64_OPND_IMM_MOV
:
2113 int esize
= aarch64_get_qualifier_esize (opnds
[0].qualifier
);
2114 imm
= opnd
->imm
.value
;
2118 case OP_MOV_IMM_WIDEN
:
2121 case OP_MOV_IMM_WIDE
:
2122 if (!aarch64_wide_constant_p (imm
, esize
== 4, NULL
))
2124 set_other_error (mismatch_detail
, idx
,
2125 _("immediate out of range"));
2129 case OP_MOV_IMM_LOG
:
2130 if (!aarch64_logical_immediate_p (imm
, esize
, NULL
))
2132 set_other_error (mismatch_detail
, idx
,
2133 _("immediate out of range"));
2144 case AARCH64_OPND_NZCV
:
2145 case AARCH64_OPND_CCMP_IMM
:
2146 case AARCH64_OPND_EXCEPTION
:
2147 case AARCH64_OPND_TME_UIMM16
:
2148 case AARCH64_OPND_UIMM4
:
2149 case AARCH64_OPND_UIMM4_ADDG
:
2150 case AARCH64_OPND_UIMM7
:
2151 case AARCH64_OPND_UIMM3_OP1
:
2152 case AARCH64_OPND_UIMM3_OP2
:
2153 case AARCH64_OPND_SVE_UIMM3
:
2154 case AARCH64_OPND_SVE_UIMM7
:
2155 case AARCH64_OPND_SVE_UIMM8
:
2156 case AARCH64_OPND_SVE_UIMM8_53
:
2157 size
= get_operand_fields_width (get_operand_from_code (type
));
2159 if (!value_fit_unsigned_field_p (opnd
->imm
.value
, size
))
2161 set_imm_out_of_range_error (mismatch_detail
, idx
, 0,
2167 case AARCH64_OPND_UIMM10
:
2168 /* Scaled unsigned 10 bits immediate offset. */
2169 if (!value_in_range_p (opnd
->imm
.value
, 0, 1008))
2171 set_imm_out_of_range_error (mismatch_detail
, idx
, 0, 1008);
2175 if (!value_aligned_p (opnd
->imm
.value
, 16))
2177 set_unaligned_error (mismatch_detail
, idx
, 16);
2182 case AARCH64_OPND_SIMM5
:
2183 case AARCH64_OPND_SVE_SIMM5
:
2184 case AARCH64_OPND_SVE_SIMM5B
:
2185 case AARCH64_OPND_SVE_SIMM6
:
2186 case AARCH64_OPND_SVE_SIMM8
:
2187 size
= get_operand_fields_width (get_operand_from_code (type
));
2189 if (!value_fit_signed_field_p (opnd
->imm
.value
, size
))
2191 set_imm_out_of_range_error (mismatch_detail
, idx
,
2193 (1 << (size
- 1)) - 1);
2198 case AARCH64_OPND_WIDTH
:
2199 assert (idx
> 1 && opnds
[idx
-1].type
== AARCH64_OPND_IMM
2200 && opnds
[0].type
== AARCH64_OPND_Rd
);
2201 size
= get_upper_bound (qualifier
);
2202 if (opnd
->imm
.value
+ opnds
[idx
-1].imm
.value
> size
)
2203 /* lsb+width <= reg.size */
2205 set_imm_out_of_range_error (mismatch_detail
, idx
, 1,
2206 size
- opnds
[idx
-1].imm
.value
);
2211 case AARCH64_OPND_LIMM
:
2212 case AARCH64_OPND_SVE_LIMM
:
2214 int esize
= aarch64_get_qualifier_esize (opnds
[0].qualifier
);
2215 uint64_t uimm
= opnd
->imm
.value
;
2216 if (opcode
->op
== OP_BIC
)
2218 if (!aarch64_logical_immediate_p (uimm
, esize
, NULL
))
2220 set_other_error (mismatch_detail
, idx
,
2221 _("immediate out of range"));
2227 case AARCH64_OPND_IMM0
:
2228 case AARCH64_OPND_FPIMM0
:
2229 if (opnd
->imm
.value
!= 0)
2231 set_other_error (mismatch_detail
, idx
,
2232 _("immediate zero expected"));
2237 case AARCH64_OPND_IMM_ROT1
:
2238 case AARCH64_OPND_IMM_ROT2
:
2239 case AARCH64_OPND_SVE_IMM_ROT2
:
2240 if (opnd
->imm
.value
!= 0
2241 && opnd
->imm
.value
!= 90
2242 && opnd
->imm
.value
!= 180
2243 && opnd
->imm
.value
!= 270)
2245 set_other_error (mismatch_detail
, idx
,
2246 _("rotate expected to be 0, 90, 180 or 270"));
2251 case AARCH64_OPND_IMM_ROT3
:
2252 case AARCH64_OPND_SVE_IMM_ROT1
:
2253 case AARCH64_OPND_SVE_IMM_ROT3
:
2254 if (opnd
->imm
.value
!= 90 && opnd
->imm
.value
!= 270)
2256 set_other_error (mismatch_detail
, idx
,
2257 _("rotate expected to be 90 or 270"));
2262 case AARCH64_OPND_SHLL_IMM
:
2264 size
= 8 * aarch64_get_qualifier_esize (opnds
[idx
- 1].qualifier
);
2265 if (opnd
->imm
.value
!= size
)
2267 set_other_error (mismatch_detail
, idx
,
2268 _("invalid shift amount"));
2273 case AARCH64_OPND_IMM_VLSL
:
2274 size
= aarch64_get_qualifier_esize (qualifier
);
2275 if (!value_in_range_p (opnd
->imm
.value
, 0, size
* 8 - 1))
2277 set_imm_out_of_range_error (mismatch_detail
, idx
, 0,
2283 case AARCH64_OPND_IMM_VLSR
:
2284 size
= aarch64_get_qualifier_esize (qualifier
);
2285 if (!value_in_range_p (opnd
->imm
.value
, 1, size
* 8))
2287 set_imm_out_of_range_error (mismatch_detail
, idx
, 1, size
* 8);
2292 case AARCH64_OPND_SIMD_IMM
:
2293 case AARCH64_OPND_SIMD_IMM_SFT
:
2294 /* Qualifier check. */
2297 case AARCH64_OPND_QLF_LSL
:
2298 if (opnd
->shifter
.kind
!= AARCH64_MOD_LSL
)
2300 set_other_error (mismatch_detail
, idx
,
2301 _("invalid shift operator"));
2305 case AARCH64_OPND_QLF_MSL
:
2306 if (opnd
->shifter
.kind
!= AARCH64_MOD_MSL
)
2308 set_other_error (mismatch_detail
, idx
,
2309 _("invalid shift operator"));
2313 case AARCH64_OPND_QLF_NIL
:
2314 if (opnd
->shifter
.kind
!= AARCH64_MOD_NONE
)
2316 set_other_error (mismatch_detail
, idx
,
2317 _("shift is not permitted"));
2325 /* Is the immediate valid? */
2327 if (aarch64_get_qualifier_esize (opnds
[0].qualifier
) != 8)
2329 /* uimm8 or simm8 */
2330 if (!value_in_range_p (opnd
->imm
.value
, -128, 255))
2332 set_imm_out_of_range_error (mismatch_detail
, idx
, -128, 255);
2336 else if (aarch64_shrink_expanded_imm8 (opnd
->imm
.value
) < 0)
2339 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeee
2340 ffffffffgggggggghhhhhhhh'. */
2341 set_other_error (mismatch_detail
, idx
,
2342 _("invalid value for immediate"));
2345 /* Is the shift amount valid? */
2346 switch (opnd
->shifter
.kind
)
2348 case AARCH64_MOD_LSL
:
2349 size
= aarch64_get_qualifier_esize (opnds
[0].qualifier
);
2350 if (!value_in_range_p (opnd
->shifter
.amount
, 0, (size
- 1) * 8))
2352 set_sft_amount_out_of_range_error (mismatch_detail
, idx
, 0,
2356 if (!value_aligned_p (opnd
->shifter
.amount
, 8))
2358 set_unaligned_error (mismatch_detail
, idx
, 8);
2362 case AARCH64_MOD_MSL
:
2363 /* Only 8 and 16 are valid shift amount. */
2364 if (opnd
->shifter
.amount
!= 8 && opnd
->shifter
.amount
!= 16)
2366 set_other_error (mismatch_detail
, idx
,
2367 _("shift amount must be 0 or 16"));
2372 if (opnd
->shifter
.kind
!= AARCH64_MOD_NONE
)
2374 set_other_error (mismatch_detail
, idx
,
2375 _("invalid shift operator"));
2382 case AARCH64_OPND_FPIMM
:
2383 case AARCH64_OPND_SIMD_FPIMM
:
2384 case AARCH64_OPND_SVE_FPIMM8
:
2385 if (opnd
->imm
.is_fp
== 0)
2387 set_other_error (mismatch_detail
, idx
,
2388 _("floating-point immediate expected"));
2391 /* The value is expected to be an 8-bit floating-point constant with
2392 sign, 3-bit exponent and normalized 4 bits of precision, encoded
2393 in "a:b:c:d:e:f:g:h" or FLD_imm8 (depending on the type of the
2395 if (!value_in_range_p (opnd
->imm
.value
, 0, 255))
2397 set_other_error (mismatch_detail
, idx
,
2398 _("immediate out of range"));
2401 if (opnd
->shifter
.kind
!= AARCH64_MOD_NONE
)
2403 set_other_error (mismatch_detail
, idx
,
2404 _("invalid shift operator"));
2409 case AARCH64_OPND_SVE_AIMM
:
2412 assert (opnd
->shifter
.kind
== AARCH64_MOD_LSL
);
2413 size
= aarch64_get_qualifier_esize (opnds
[0].qualifier
);
2414 mask
= ~((uint64_t) -1 << (size
* 4) << (size
* 4));
2415 uvalue
= opnd
->imm
.value
;
2416 shift
= opnd
->shifter
.amount
;
2421 set_other_error (mismatch_detail
, idx
,
2422 _("no shift amount allowed for"
2423 " 8-bit constants"));
2429 if (shift
!= 0 && shift
!= 8)
2431 set_other_error (mismatch_detail
, idx
,
2432 _("shift amount must be 0 or 8"));
2435 if (shift
== 0 && (uvalue
& 0xff) == 0)
2438 uvalue
= (int64_t) uvalue
/ 256;
2442 if ((uvalue
& mask
) != uvalue
&& (uvalue
| ~mask
) != uvalue
)
2444 set_other_error (mismatch_detail
, idx
,
2445 _("immediate too big for element size"));
2448 uvalue
= (uvalue
- min_value
) & mask
;
2451 set_other_error (mismatch_detail
, idx
,
2452 _("invalid arithmetic immediate"));
2457 case AARCH64_OPND_SVE_ASIMM
:
2461 case AARCH64_OPND_SVE_I1_HALF_ONE
:
2462 assert (opnd
->imm
.is_fp
);
2463 if (opnd
->imm
.value
!= 0x3f000000 && opnd
->imm
.value
!= 0x3f800000)
2465 set_other_error (mismatch_detail
, idx
,
2466 _("floating-point value must be 0.5 or 1.0"));
2471 case AARCH64_OPND_SVE_I1_HALF_TWO
:
2472 assert (opnd
->imm
.is_fp
);
2473 if (opnd
->imm
.value
!= 0x3f000000 && opnd
->imm
.value
!= 0x40000000)
2475 set_other_error (mismatch_detail
, idx
,
2476 _("floating-point value must be 0.5 or 2.0"));
2481 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
2482 assert (opnd
->imm
.is_fp
);
2483 if (opnd
->imm
.value
!= 0 && opnd
->imm
.value
!= 0x3f800000)
2485 set_other_error (mismatch_detail
, idx
,
2486 _("floating-point value must be 0.0 or 1.0"));
2491 case AARCH64_OPND_SVE_INV_LIMM
:
2493 int esize
= aarch64_get_qualifier_esize (opnds
[0].qualifier
);
2494 uint64_t uimm
= ~opnd
->imm
.value
;
2495 if (!aarch64_logical_immediate_p (uimm
, esize
, NULL
))
2497 set_other_error (mismatch_detail
, idx
,
2498 _("immediate out of range"));
2504 case AARCH64_OPND_SVE_LIMM_MOV
:
2506 int esize
= aarch64_get_qualifier_esize (opnds
[0].qualifier
);
2507 uint64_t uimm
= opnd
->imm
.value
;
2508 if (!aarch64_logical_immediate_p (uimm
, esize
, NULL
))
2510 set_other_error (mismatch_detail
, idx
,
2511 _("immediate out of range"));
2514 if (!aarch64_sve_dupm_mov_immediate_p (uimm
, esize
))
2516 set_other_error (mismatch_detail
, idx
,
2517 _("invalid replicated MOV immediate"));
2523 case AARCH64_OPND_SVE_PATTERN_SCALED
:
2524 assert (opnd
->shifter
.kind
== AARCH64_MOD_MUL
);
2525 if (!value_in_range_p (opnd
->shifter
.amount
, 1, 16))
2527 set_multiplier_out_of_range_error (mismatch_detail
, idx
, 1, 16);
2532 case AARCH64_OPND_SVE_SHLIMM_PRED
:
2533 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
2534 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
2535 size
= aarch64_get_qualifier_esize (opnds
[idx
- 1].qualifier
);
2536 if (!value_in_range_p (opnd
->imm
.value
, 0, 8 * size
- 1))
2538 set_imm_out_of_range_error (mismatch_detail
, idx
,
2544 case AARCH64_OPND_SVE_SHRIMM_PRED
:
2545 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
2546 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
2548 unsigned int index
=
2549 (type
== AARCH64_OPND_SVE_SHRIMM_UNPRED_22
) ? 2 : 1;
2550 size
= aarch64_get_qualifier_esize (opnds
[idx
- index
].qualifier
);
2551 if (!value_in_range_p (opnd
->imm
.value
, 1, 8 * size
))
2553 set_imm_out_of_range_error (mismatch_detail
, idx
, 1, 8*size
);
2564 case AARCH64_OPND_CLASS_SYSTEM
:
2567 case AARCH64_OPND_PSTATEFIELD
:
2568 assert (idx
== 0 && opnds
[1].type
== AARCH64_OPND_UIMM4
);
2572 The immediate must be #0 or #1. */
2573 if ((opnd
->pstatefield
== 0x03 /* UAO. */
2574 || opnd
->pstatefield
== 0x04 /* PAN. */
2575 || opnd
->pstatefield
== 0x19 /* SSBS. */
2576 || opnd
->pstatefield
== 0x1a) /* DIT. */
2577 && opnds
[1].imm
.value
> 1)
2579 set_imm_out_of_range_error (mismatch_detail
, idx
, 0, 1);
2582 /* MSR SPSel, #uimm4
2583 Uses uimm4 as a control value to select the stack pointer: if
2584 bit 0 is set it selects the current exception level's stack
2585 pointer, if bit 0 is clear it selects shared EL0 stack pointer.
2586 Bits 1 to 3 of uimm4 are reserved and should be zero. */
2587 if (opnd
->pstatefield
== 0x05 /* spsel */ && opnds
[1].imm
.value
> 1)
2589 set_imm_out_of_range_error (mismatch_detail
, idx
, 0, 1);
2598 case AARCH64_OPND_CLASS_SIMD_ELEMENT
:
2599 /* Get the upper bound for the element index. */
2600 if (opcode
->op
== OP_FCMLA_ELEM
)
2601 /* FCMLA index range depends on the vector size of other operands
2602 and is halfed because complex numbers take two elements. */
2603 num
= aarch64_get_qualifier_nelem (opnds
[0].qualifier
)
2604 * aarch64_get_qualifier_esize (opnds
[0].qualifier
) / 2;
2607 num
= num
/ aarch64_get_qualifier_esize (qualifier
) - 1;
2608 assert (aarch64_get_qualifier_nelem (qualifier
) == 1);
2610 /* Index out-of-range. */
2611 if (!value_in_range_p (opnd
->reglane
.index
, 0, num
))
2613 set_elem_idx_out_of_range_error (mismatch_detail
, idx
, 0, num
);
2616 /* SMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].
2617 <Vm> Is the vector register (V0-V31) or (V0-V15), whose
2618 number is encoded in "size:M:Rm":
2624 if (type
== AARCH64_OPND_Em16
&& qualifier
== AARCH64_OPND_QLF_S_H
2625 && !value_in_range_p (opnd
->reglane
.regno
, 0, 15))
2627 set_regno_out_of_range_error (mismatch_detail
, idx
, 0, 15);
2632 case AARCH64_OPND_CLASS_MODIFIED_REG
:
2633 assert (idx
== 1 || idx
== 2);
2636 case AARCH64_OPND_Rm_EXT
:
2637 if (!aarch64_extend_operator_p (opnd
->shifter
.kind
)
2638 && opnd
->shifter
.kind
!= AARCH64_MOD_LSL
)
2640 set_other_error (mismatch_detail
, idx
,
2641 _("extend operator expected"));
2644 /* It is not optional unless at least one of "Rd" or "Rn" is '11111'
2645 (i.e. SP), in which case it defaults to LSL. The LSL alias is
2646 only valid when "Rd" or "Rn" is '11111', and is preferred in that
2648 if (!aarch64_stack_pointer_p (opnds
+ 0)
2649 && (idx
!= 2 || !aarch64_stack_pointer_p (opnds
+ 1)))
2651 if (!opnd
->shifter
.operator_present
)
2653 set_other_error (mismatch_detail
, idx
,
2654 _("missing extend operator"));
2657 else if (opnd
->shifter
.kind
== AARCH64_MOD_LSL
)
2659 set_other_error (mismatch_detail
, idx
,
2660 _("'LSL' operator not allowed"));
2664 assert (opnd
->shifter
.operator_present
/* Default to LSL. */
2665 || opnd
->shifter
.kind
== AARCH64_MOD_LSL
);
2666 if (!value_in_range_p (opnd
->shifter
.amount
, 0, 4))
2668 set_sft_amount_out_of_range_error (mismatch_detail
, idx
, 0, 4);
2671 /* In the 64-bit form, the final register operand is written as Wm
2672 for all but the (possibly omitted) UXTX/LSL and SXTX
2674 N.B. GAS allows X register to be used with any operator as a
2675 programming convenience. */
2676 if (qualifier
== AARCH64_OPND_QLF_X
2677 && opnd
->shifter
.kind
!= AARCH64_MOD_LSL
2678 && opnd
->shifter
.kind
!= AARCH64_MOD_UXTX
2679 && opnd
->shifter
.kind
!= AARCH64_MOD_SXTX
)
2681 set_other_error (mismatch_detail
, idx
, _("W register expected"));
2686 case AARCH64_OPND_Rm_SFT
:
2687 /* ROR is not available to the shifted register operand in
2688 arithmetic instructions. */
2689 if (!aarch64_shift_operator_p (opnd
->shifter
.kind
))
2691 set_other_error (mismatch_detail
, idx
,
2692 _("shift operator expected"));
2695 if (opnd
->shifter
.kind
== AARCH64_MOD_ROR
2696 && opcode
->iclass
!= log_shift
)
2698 set_other_error (mismatch_detail
, idx
,
2699 _("'ROR' operator not allowed"));
2702 num
= qualifier
== AARCH64_OPND_QLF_W
? 31 : 63;
2703 if (!value_in_range_p (opnd
->shifter
.amount
, 0, num
))
2705 set_sft_amount_out_of_range_error (mismatch_detail
, idx
, 0, num
);
2722 /* Main entrypoint for the operand constraint checking.
2724 Return 1 if operands of *INST meet the constraint applied by the operand
2725 codes and operand qualifiers; otherwise return 0 and if MISMATCH_DETAIL is
2726 not NULL, return the detail of the error in *MISMATCH_DETAIL. N.B. when
2727 adding more constraint checking, make sure MISMATCH_DETAIL->KIND is set
2728 with a proper error kind rather than AARCH64_OPDE_NIL (GAS asserts non-NIL
2729 error kind when it is notified that an instruction does not pass the check).
2731 Un-determined operand qualifiers may get established during the process. */
2734 aarch64_match_operands_constraint (aarch64_inst
*inst
,
2735 aarch64_operand_error
*mismatch_detail
)
2739 DEBUG_TRACE ("enter");
2741 /* Check for cases where a source register needs to be the same as the
2742 destination register. Do this before matching qualifiers since if
2743 an instruction has both invalid tying and invalid qualifiers,
2744 the error about qualifiers would suggest several alternative
2745 instructions that also have invalid tying. */
2746 i
= inst
->opcode
->tied_operand
;
2747 if (i
> 0 && (inst
->operands
[0].reg
.regno
!= inst
->operands
[i
].reg
.regno
))
2749 if (mismatch_detail
)
2751 mismatch_detail
->kind
= AARCH64_OPDE_UNTIED_OPERAND
;
2752 mismatch_detail
->index
= i
;
2753 mismatch_detail
->error
= NULL
;
2758 /* Match operands' qualifier.
2759 *INST has already had qualifier establish for some, if not all, of
2760 its operands; we need to find out whether these established
2761 qualifiers match one of the qualifier sequence in
2762 INST->OPCODE->QUALIFIERS_LIST. If yes, we will assign each operand
2763 with the corresponding qualifier in such a sequence.
2764 Only basic operand constraint checking is done here; the more thorough
2765 constraint checking will carried out by operand_general_constraint_met_p,
2766 which has be to called after this in order to get all of the operands'
2767 qualifiers established. */
2768 if (match_operands_qualifier (inst
, TRUE
/* update_p */) == 0)
2770 DEBUG_TRACE ("FAIL on operand qualifier matching");
2771 if (mismatch_detail
)
2773 /* Return an error type to indicate that it is the qualifier
2774 matching failure; we don't care about which operand as there
2775 are enough information in the opcode table to reproduce it. */
2776 mismatch_detail
->kind
= AARCH64_OPDE_INVALID_VARIANT
;
2777 mismatch_detail
->index
= -1;
2778 mismatch_detail
->error
= NULL
;
2783 /* Match operands' constraint. */
2784 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2786 enum aarch64_opnd type
= inst
->opcode
->operands
[i
];
2787 if (type
== AARCH64_OPND_NIL
)
2789 if (inst
->operands
[i
].skip
)
2791 DEBUG_TRACE ("skip the incomplete operand %d", i
);
2794 if (operand_general_constraint_met_p (inst
->operands
, i
, type
,
2795 inst
->opcode
, mismatch_detail
) == 0)
2797 DEBUG_TRACE ("FAIL on operand %d", i
);
2802 DEBUG_TRACE ("PASS");
2807 /* Replace INST->OPCODE with OPCODE and return the replaced OPCODE.
2808 Also updates the TYPE of each INST->OPERANDS with the corresponding
2809 value of OPCODE->OPERANDS.
2811 Note that some operand qualifiers may need to be manually cleared by
2812 the caller before it further calls the aarch64_opcode_encode; by
2813 doing this, it helps the qualifier matching facilities work
2816 const aarch64_opcode
*
2817 aarch64_replace_opcode (aarch64_inst
*inst
, const aarch64_opcode
*opcode
)
2820 const aarch64_opcode
*old
= inst
->opcode
;
2822 inst
->opcode
= opcode
;
2824 /* Update the operand types. */
2825 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2827 inst
->operands
[i
].type
= opcode
->operands
[i
];
2828 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
)
2832 DEBUG_TRACE ("replace %s with %s", old
->name
, opcode
->name
);
2838 aarch64_operand_index (const enum aarch64_opnd
*operands
, enum aarch64_opnd operand
)
2841 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2842 if (operands
[i
] == operand
)
2844 else if (operands
[i
] == AARCH64_OPND_NIL
)
2849 /* R0...R30, followed by FOR31. */
2850 #define BANK(R, FOR31) \
2851 { R (0), R (1), R (2), R (3), R (4), R (5), R (6), R (7), \
2852 R (8), R (9), R (10), R (11), R (12), R (13), R (14), R (15), \
2853 R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), \
2854 R (24), R (25), R (26), R (27), R (28), R (29), R (30), FOR31 }
2855 /* [0][0] 32-bit integer regs with sp Wn
2856 [0][1] 64-bit integer regs with sp Xn sf=1
2857 [1][0] 32-bit integer regs with #0 Wn
2858 [1][1] 64-bit integer regs with #0 Xn sf=1 */
2859 static const char *int_reg
[2][2][32] = {
2860 #define R32(X) "w" #X
2861 #define R64(X) "x" #X
2862 { BANK (R32
, "wsp"), BANK (R64
, "sp") },
2863 { BANK (R32
, "wzr"), BANK (R64
, "xzr") }
2868 /* Names of the SVE vector registers, first with .S suffixes,
2869 then with .D suffixes. */
2871 static const char *sve_reg
[2][32] = {
2872 #define ZS(X) "z" #X ".s"
2873 #define ZD(X) "z" #X ".d"
2874 BANK (ZS
, ZS (31)), BANK (ZD
, ZD (31))
2880 /* Return the integer register name.
2881 if SP_REG_P is not 0, R31 is an SP reg, other R31 is the zero reg. */
2883 static inline const char *
2884 get_int_reg_name (int regno
, aarch64_opnd_qualifier_t qualifier
, int sp_reg_p
)
2886 const int has_zr
= sp_reg_p
? 0 : 1;
2887 const int is_64
= aarch64_get_qualifier_esize (qualifier
) == 4 ? 0 : 1;
2888 return int_reg
[has_zr
][is_64
][regno
];
2891 /* Like get_int_reg_name, but IS_64 is always 1. */
2893 static inline const char *
2894 get_64bit_int_reg_name (int regno
, int sp_reg_p
)
2896 const int has_zr
= sp_reg_p
? 0 : 1;
2897 return int_reg
[has_zr
][1][regno
];
2900 /* Get the name of the integer offset register in OPND, using the shift type
2901 to decide whether it's a word or doubleword. */
2903 static inline const char *
2904 get_offset_int_reg_name (const aarch64_opnd_info
*opnd
)
2906 switch (opnd
->shifter
.kind
)
2908 case AARCH64_MOD_UXTW
:
2909 case AARCH64_MOD_SXTW
:
2910 return get_int_reg_name (opnd
->addr
.offset
.regno
, AARCH64_OPND_QLF_W
, 0);
2912 case AARCH64_MOD_LSL
:
2913 case AARCH64_MOD_SXTX
:
2914 return get_int_reg_name (opnd
->addr
.offset
.regno
, AARCH64_OPND_QLF_X
, 0);
2921 /* Get the name of the SVE vector offset register in OPND, using the operand
2922 qualifier to decide whether the suffix should be .S or .D. */
2924 static inline const char *
2925 get_addr_sve_reg_name (int regno
, aarch64_opnd_qualifier_t qualifier
)
2927 assert (qualifier
== AARCH64_OPND_QLF_S_S
2928 || qualifier
== AARCH64_OPND_QLF_S_D
);
2929 return sve_reg
[qualifier
== AARCH64_OPND_QLF_S_D
][regno
];
2932 /* Types for expanding an encoded 8-bit value to a floating-point value. */
2952 /* IMM8 is an 8-bit floating-point constant with sign, 3-bit exponent and
2953 normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h" or FLD_imm8
2954 (depending on the type of the instruction). IMM8 will be expanded to a
2955 single-precision floating-point value (SIZE == 4) or a double-precision
2956 floating-point value (SIZE == 8). A half-precision floating-point value
2957 (SIZE == 2) is expanded to a single-precision floating-point value. The
2958 expanded value is returned. */
2961 expand_fp_imm (int size
, uint32_t imm8
)
2964 uint32_t imm8_7
, imm8_6_0
, imm8_6
, imm8_6_repl4
;
2966 imm8_7
= (imm8
>> 7) & 0x01; /* imm8<7> */
2967 imm8_6_0
= imm8
& 0x7f; /* imm8<6:0> */
2968 imm8_6
= imm8_6_0
>> 6; /* imm8<6> */
2969 imm8_6_repl4
= (imm8_6
<< 3) | (imm8_6
<< 2)
2970 | (imm8_6
<< 1) | imm8_6
; /* Replicate(imm8<6>,4) */
2973 imm
= (imm8_7
<< (63-32)) /* imm8<7> */
2974 | ((imm8_6
^ 1) << (62-32)) /* NOT(imm8<6) */
2975 | (imm8_6_repl4
<< (58-32)) | (imm8_6
<< (57-32))
2976 | (imm8_6
<< (56-32)) | (imm8_6
<< (55-32)) /* Replicate(imm8<6>,7) */
2977 | (imm8_6_0
<< (48-32)); /* imm8<6>:imm8<5:0> */
2980 else if (size
== 4 || size
== 2)
2982 imm
= (imm8_7
<< 31) /* imm8<7> */
2983 | ((imm8_6
^ 1) << 30) /* NOT(imm8<6>) */
2984 | (imm8_6_repl4
<< 26) /* Replicate(imm8<6>,4) */
2985 | (imm8_6_0
<< 19); /* imm8<6>:imm8<5:0> */
2989 /* An unsupported size. */
2996 /* Produce the string representation of the register list operand *OPND
2997 in the buffer pointed by BUF of size SIZE. PREFIX is the part of
2998 the register name that comes before the register number, such as "v". */
3000 print_register_list (char *buf
, size_t size
, const aarch64_opnd_info
*opnd
,
3003 const int num_regs
= opnd
->reglist
.num_regs
;
3004 const int first_reg
= opnd
->reglist
.first_regno
;
3005 const int last_reg
= (first_reg
+ num_regs
- 1) & 0x1f;
3006 const char *qlf_name
= aarch64_get_qualifier_name (opnd
->qualifier
);
3007 char tb
[8]; /* Temporary buffer. */
3009 assert (opnd
->type
!= AARCH64_OPND_LEt
|| opnd
->reglist
.has_index
);
3010 assert (num_regs
>= 1 && num_regs
<= 4);
3012 /* Prepare the index if any. */
3013 if (opnd
->reglist
.has_index
)
3014 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3015 snprintf (tb
, 8, "[%" PRIi64
"]", (opnd
->reglist
.index
% 100));
3019 /* The hyphenated form is preferred for disassembly if there are
3020 more than two registers in the list, and the register numbers
3021 are monotonically increasing in increments of one. */
3022 if (num_regs
> 2 && last_reg
> first_reg
)
3023 snprintf (buf
, size
, "{%s%d.%s-%s%d.%s}%s", prefix
, first_reg
, qlf_name
,
3024 prefix
, last_reg
, qlf_name
, tb
);
3027 const int reg0
= first_reg
;
3028 const int reg1
= (first_reg
+ 1) & 0x1f;
3029 const int reg2
= (first_reg
+ 2) & 0x1f;
3030 const int reg3
= (first_reg
+ 3) & 0x1f;
3035 snprintf (buf
, size
, "{%s%d.%s}%s", prefix
, reg0
, qlf_name
, tb
);
3038 snprintf (buf
, size
, "{%s%d.%s, %s%d.%s}%s", prefix
, reg0
, qlf_name
,
3039 prefix
, reg1
, qlf_name
, tb
);
3042 snprintf (buf
, size
, "{%s%d.%s, %s%d.%s, %s%d.%s}%s",
3043 prefix
, reg0
, qlf_name
, prefix
, reg1
, qlf_name
,
3044 prefix
, reg2
, qlf_name
, tb
);
3047 snprintf (buf
, size
, "{%s%d.%s, %s%d.%s, %s%d.%s, %s%d.%s}%s",
3048 prefix
, reg0
, qlf_name
, prefix
, reg1
, qlf_name
,
3049 prefix
, reg2
, qlf_name
, prefix
, reg3
, qlf_name
, tb
);
3055 /* Print the register+immediate address in OPND to BUF, which has SIZE
3056 characters. BASE is the name of the base register. */
3059 print_immediate_offset_address (char *buf
, size_t size
,
3060 const aarch64_opnd_info
*opnd
,
3063 if (opnd
->addr
.writeback
)
3065 if (opnd
->addr
.preind
)
3067 if (opnd
->type
== AARCH64_OPND_ADDR_SIMM10
&& !opnd
->addr
.offset
.imm
)
3068 snprintf (buf
, size
, "[%s]!", base
);
3070 snprintf (buf
, size
, "[%s, #%d]!", base
, opnd
->addr
.offset
.imm
);
3073 snprintf (buf
, size
, "[%s], #%d", base
, opnd
->addr
.offset
.imm
);
3077 if (opnd
->shifter
.operator_present
)
3079 assert (opnd
->shifter
.kind
== AARCH64_MOD_MUL_VL
);
3080 snprintf (buf
, size
, "[%s, #%d, mul vl]",
3081 base
, opnd
->addr
.offset
.imm
);
3083 else if (opnd
->addr
.offset
.imm
)
3084 snprintf (buf
, size
, "[%s, #%d]", base
, opnd
->addr
.offset
.imm
);
3086 snprintf (buf
, size
, "[%s]", base
);
3090 /* Produce the string representation of the register offset address operand
3091 *OPND in the buffer pointed by BUF of size SIZE. BASE and OFFSET are
3092 the names of the base and offset registers. */
3094 print_register_offset_address (char *buf
, size_t size
,
3095 const aarch64_opnd_info
*opnd
,
3096 const char *base
, const char *offset
)
3098 char tb
[16]; /* Temporary buffer. */
3099 bfd_boolean print_extend_p
= TRUE
;
3100 bfd_boolean print_amount_p
= TRUE
;
3101 const char *shift_name
= aarch64_operand_modifiers
[opnd
->shifter
.kind
].name
;
3103 if (!opnd
->shifter
.amount
&& (opnd
->qualifier
!= AARCH64_OPND_QLF_S_B
3104 || !opnd
->shifter
.amount_present
))
3106 /* Not print the shift/extend amount when the amount is zero and
3107 when it is not the special case of 8-bit load/store instruction. */
3108 print_amount_p
= FALSE
;
3109 /* Likewise, no need to print the shift operator LSL in such a
3111 if (opnd
->shifter
.kind
== AARCH64_MOD_LSL
)
3112 print_extend_p
= FALSE
;
3115 /* Prepare for the extend/shift. */
3119 snprintf (tb
, sizeof (tb
), ", %s #%" PRIi64
, shift_name
,
3120 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3121 (opnd
->shifter
.amount
% 100));
3123 snprintf (tb
, sizeof (tb
), ", %s", shift_name
);
3128 snprintf (buf
, size
, "[%s, %s%s]", base
, offset
, tb
);
3131 /* Generate the string representation of the operand OPNDS[IDX] for OPCODE
3132 in *BUF. The caller should pass in the maximum size of *BUF in SIZE.
3133 PC, PCREL_P and ADDRESS are used to pass in and return information about
3134 the PC-relative address calculation, where the PC value is passed in
3135 PC. If the operand is pc-relative related, *PCREL_P (if PCREL_P non-NULL)
3136 will return 1 and *ADDRESS (if ADDRESS non-NULL) will return the
3137 calculated address; otherwise, *PCREL_P (if PCREL_P non-NULL) returns 0.
3139 The function serves both the disassembler and the assembler diagnostics
3140 issuer, which is the reason why it lives in this file. */
3143 aarch64_print_operand (char *buf
, size_t size
, bfd_vma pc
,
3144 const aarch64_opcode
*opcode
,
3145 const aarch64_opnd_info
*opnds
, int idx
, int *pcrel_p
,
3146 bfd_vma
*address
, char** notes
)
3148 unsigned int i
, num_conds
;
3149 const char *name
= NULL
;
3150 const aarch64_opnd_info
*opnd
= opnds
+ idx
;
3151 enum aarch64_modifier_kind kind
;
3152 uint64_t addr
, enum_value
;
3160 case AARCH64_OPND_Rd
:
3161 case AARCH64_OPND_Rn
:
3162 case AARCH64_OPND_Rm
:
3163 case AARCH64_OPND_Rt
:
3164 case AARCH64_OPND_Rt2
:
3165 case AARCH64_OPND_Rs
:
3166 case AARCH64_OPND_Ra
:
3167 case AARCH64_OPND_Rt_SYS
:
3168 case AARCH64_OPND_PAIRREG
:
3169 case AARCH64_OPND_SVE_Rm
:
3170 /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
3171 the <ic_op>, therefore we use opnd->present to override the
3172 generic optional-ness information. */
3173 if (opnd
->type
== AARCH64_OPND_Rt_SYS
)
3178 /* Omit the operand, e.g. RET. */
3179 else if (optional_operand_p (opcode
, idx
)
3181 == get_optional_operand_default_value (opcode
)))
3183 assert (opnd
->qualifier
== AARCH64_OPND_QLF_W
3184 || opnd
->qualifier
== AARCH64_OPND_QLF_X
);
3185 snprintf (buf
, size
, "%s",
3186 get_int_reg_name (opnd
->reg
.regno
, opnd
->qualifier
, 0));
3189 case AARCH64_OPND_Rd_SP
:
3190 case AARCH64_OPND_Rn_SP
:
3191 case AARCH64_OPND_Rt_SP
:
3192 case AARCH64_OPND_SVE_Rn_SP
:
3193 case AARCH64_OPND_Rm_SP
:
3194 assert (opnd
->qualifier
== AARCH64_OPND_QLF_W
3195 || opnd
->qualifier
== AARCH64_OPND_QLF_WSP
3196 || opnd
->qualifier
== AARCH64_OPND_QLF_X
3197 || opnd
->qualifier
== AARCH64_OPND_QLF_SP
);
3198 snprintf (buf
, size
, "%s",
3199 get_int_reg_name (opnd
->reg
.regno
, opnd
->qualifier
, 1));
3202 case AARCH64_OPND_Rm_EXT
:
3203 kind
= opnd
->shifter
.kind
;
3204 assert (idx
== 1 || idx
== 2);
3205 if ((aarch64_stack_pointer_p (opnds
)
3206 || (idx
== 2 && aarch64_stack_pointer_p (opnds
+ 1)))
3207 && ((opnd
->qualifier
== AARCH64_OPND_QLF_W
3208 && opnds
[0].qualifier
== AARCH64_OPND_QLF_W
3209 && kind
== AARCH64_MOD_UXTW
)
3210 || (opnd
->qualifier
== AARCH64_OPND_QLF_X
3211 && kind
== AARCH64_MOD_UXTX
)))
3213 /* 'LSL' is the preferred form in this case. */
3214 kind
= AARCH64_MOD_LSL
;
3215 if (opnd
->shifter
.amount
== 0)
3217 /* Shifter omitted. */
3218 snprintf (buf
, size
, "%s",
3219 get_int_reg_name (opnd
->reg
.regno
, opnd
->qualifier
, 0));
3223 if (opnd
->shifter
.amount
)
3224 snprintf (buf
, size
, "%s, %s #%" PRIi64
,
3225 get_int_reg_name (opnd
->reg
.regno
, opnd
->qualifier
, 0),
3226 aarch64_operand_modifiers
[kind
].name
,
3227 opnd
->shifter
.amount
);
3229 snprintf (buf
, size
, "%s, %s",
3230 get_int_reg_name (opnd
->reg
.regno
, opnd
->qualifier
, 0),
3231 aarch64_operand_modifiers
[kind
].name
);
3234 case AARCH64_OPND_Rm_SFT
:
3235 assert (opnd
->qualifier
== AARCH64_OPND_QLF_W
3236 || opnd
->qualifier
== AARCH64_OPND_QLF_X
);
3237 if (opnd
->shifter
.amount
== 0 && opnd
->shifter
.kind
== AARCH64_MOD_LSL
)
3238 snprintf (buf
, size
, "%s",
3239 get_int_reg_name (opnd
->reg
.regno
, opnd
->qualifier
, 0));
3241 snprintf (buf
, size
, "%s, %s #%" PRIi64
,
3242 get_int_reg_name (opnd
->reg
.regno
, opnd
->qualifier
, 0),
3243 aarch64_operand_modifiers
[opnd
->shifter
.kind
].name
,
3244 opnd
->shifter
.amount
);
3247 case AARCH64_OPND_Fd
:
3248 case AARCH64_OPND_Fn
:
3249 case AARCH64_OPND_Fm
:
3250 case AARCH64_OPND_Fa
:
3251 case AARCH64_OPND_Ft
:
3252 case AARCH64_OPND_Ft2
:
3253 case AARCH64_OPND_Sd
:
3254 case AARCH64_OPND_Sn
:
3255 case AARCH64_OPND_Sm
:
3256 case AARCH64_OPND_SVE_VZn
:
3257 case AARCH64_OPND_SVE_Vd
:
3258 case AARCH64_OPND_SVE_Vm
:
3259 case AARCH64_OPND_SVE_Vn
:
3260 snprintf (buf
, size
, "%s%d", aarch64_get_qualifier_name (opnd
->qualifier
),
3264 case AARCH64_OPND_Va
:
3265 case AARCH64_OPND_Vd
:
3266 case AARCH64_OPND_Vn
:
3267 case AARCH64_OPND_Vm
:
3268 snprintf (buf
, size
, "v%d.%s", opnd
->reg
.regno
,
3269 aarch64_get_qualifier_name (opnd
->qualifier
));
3272 case AARCH64_OPND_Ed
:
3273 case AARCH64_OPND_En
:
3274 case AARCH64_OPND_Em
:
3275 case AARCH64_OPND_Em16
:
3276 case AARCH64_OPND_SM3_IMM2
:
3277 snprintf (buf
, size
, "v%d.%s[%" PRIi64
"]", opnd
->reglane
.regno
,
3278 aarch64_get_qualifier_name (opnd
->qualifier
),
3279 opnd
->reglane
.index
);
3282 case AARCH64_OPND_VdD1
:
3283 case AARCH64_OPND_VnD1
:
3284 snprintf (buf
, size
, "v%d.d[1]", opnd
->reg
.regno
);
3287 case AARCH64_OPND_LVn
:
3288 case AARCH64_OPND_LVt
:
3289 case AARCH64_OPND_LVt_AL
:
3290 case AARCH64_OPND_LEt
:
3291 print_register_list (buf
, size
, opnd
, "v");
3294 case AARCH64_OPND_SVE_Pd
:
3295 case AARCH64_OPND_SVE_Pg3
:
3296 case AARCH64_OPND_SVE_Pg4_5
:
3297 case AARCH64_OPND_SVE_Pg4_10
:
3298 case AARCH64_OPND_SVE_Pg4_16
:
3299 case AARCH64_OPND_SVE_Pm
:
3300 case AARCH64_OPND_SVE_Pn
:
3301 case AARCH64_OPND_SVE_Pt
:
3302 if (opnd
->qualifier
== AARCH64_OPND_QLF_NIL
)
3303 snprintf (buf
, size
, "p%d", opnd
->reg
.regno
);
3304 else if (opnd
->qualifier
== AARCH64_OPND_QLF_P_Z
3305 || opnd
->qualifier
== AARCH64_OPND_QLF_P_M
)
3306 snprintf (buf
, size
, "p%d/%s", opnd
->reg
.regno
,
3307 aarch64_get_qualifier_name (opnd
->qualifier
));
3309 snprintf (buf
, size
, "p%d.%s", opnd
->reg
.regno
,
3310 aarch64_get_qualifier_name (opnd
->qualifier
));
3313 case AARCH64_OPND_SVE_Za_5
:
3314 case AARCH64_OPND_SVE_Za_16
:
3315 case AARCH64_OPND_SVE_Zd
:
3316 case AARCH64_OPND_SVE_Zm_5
:
3317 case AARCH64_OPND_SVE_Zm_16
:
3318 case AARCH64_OPND_SVE_Zn
:
3319 case AARCH64_OPND_SVE_Zt
:
3320 if (opnd
->qualifier
== AARCH64_OPND_QLF_NIL
)
3321 snprintf (buf
, size
, "z%d", opnd
->reg
.regno
);
3323 snprintf (buf
, size
, "z%d.%s", opnd
->reg
.regno
,
3324 aarch64_get_qualifier_name (opnd
->qualifier
));
3327 case AARCH64_OPND_SVE_ZnxN
:
3328 case AARCH64_OPND_SVE_ZtxN
:
3329 print_register_list (buf
, size
, opnd
, "z");
3332 case AARCH64_OPND_SVE_Zm3_INDEX
:
3333 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
3334 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
3335 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
3336 case AARCH64_OPND_SVE_Zm4_INDEX
:
3337 case AARCH64_OPND_SVE_Zn_INDEX
:
3338 snprintf (buf
, size
, "z%d.%s[%" PRIi64
"]", opnd
->reglane
.regno
,
3339 aarch64_get_qualifier_name (opnd
->qualifier
),
3340 opnd
->reglane
.index
);
3343 case AARCH64_OPND_CRn
:
3344 case AARCH64_OPND_CRm
:
3345 snprintf (buf
, size
, "C%" PRIi64
, opnd
->imm
.value
);
3348 case AARCH64_OPND_IDX
:
3349 case AARCH64_OPND_MASK
:
3350 case AARCH64_OPND_IMM
:
3351 case AARCH64_OPND_IMM_2
:
3352 case AARCH64_OPND_WIDTH
:
3353 case AARCH64_OPND_UIMM3_OP1
:
3354 case AARCH64_OPND_UIMM3_OP2
:
3355 case AARCH64_OPND_BIT_NUM
:
3356 case AARCH64_OPND_IMM_VLSL
:
3357 case AARCH64_OPND_IMM_VLSR
:
3358 case AARCH64_OPND_SHLL_IMM
:
3359 case AARCH64_OPND_IMM0
:
3360 case AARCH64_OPND_IMMR
:
3361 case AARCH64_OPND_IMMS
:
3362 case AARCH64_OPND_FBITS
:
3363 case AARCH64_OPND_TME_UIMM16
:
3364 case AARCH64_OPND_SIMM5
:
3365 case AARCH64_OPND_SVE_SHLIMM_PRED
:
3366 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
3367 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
3368 case AARCH64_OPND_SVE_SHRIMM_PRED
:
3369 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
3370 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
3371 case AARCH64_OPND_SVE_SIMM5
:
3372 case AARCH64_OPND_SVE_SIMM5B
:
3373 case AARCH64_OPND_SVE_SIMM6
:
3374 case AARCH64_OPND_SVE_SIMM8
:
3375 case AARCH64_OPND_SVE_UIMM3
:
3376 case AARCH64_OPND_SVE_UIMM7
:
3377 case AARCH64_OPND_SVE_UIMM8
:
3378 case AARCH64_OPND_SVE_UIMM8_53
:
3379 case AARCH64_OPND_IMM_ROT1
:
3380 case AARCH64_OPND_IMM_ROT2
:
3381 case AARCH64_OPND_IMM_ROT3
:
3382 case AARCH64_OPND_SVE_IMM_ROT1
:
3383 case AARCH64_OPND_SVE_IMM_ROT2
:
3384 case AARCH64_OPND_SVE_IMM_ROT3
:
3385 snprintf (buf
, size
, "#%" PRIi64
, opnd
->imm
.value
);
3388 case AARCH64_OPND_SVE_I1_HALF_ONE
:
3389 case AARCH64_OPND_SVE_I1_HALF_TWO
:
3390 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
3393 c
.i
= opnd
->imm
.value
;
3394 snprintf (buf
, size
, "#%.1f", c
.f
);
3398 case AARCH64_OPND_SVE_PATTERN
:
3399 if (optional_operand_p (opcode
, idx
)
3400 && opnd
->imm
.value
== get_optional_operand_default_value (opcode
))
3402 enum_value
= opnd
->imm
.value
;
3403 assert (enum_value
< ARRAY_SIZE (aarch64_sve_pattern_array
));
3404 if (aarch64_sve_pattern_array
[enum_value
])
3405 snprintf (buf
, size
, "%s", aarch64_sve_pattern_array
[enum_value
]);
3407 snprintf (buf
, size
, "#%" PRIi64
, opnd
->imm
.value
);
3410 case AARCH64_OPND_SVE_PATTERN_SCALED
:
3411 if (optional_operand_p (opcode
, idx
)
3412 && !opnd
->shifter
.operator_present
3413 && opnd
->imm
.value
== get_optional_operand_default_value (opcode
))
3415 enum_value
= opnd
->imm
.value
;
3416 assert (enum_value
< ARRAY_SIZE (aarch64_sve_pattern_array
));
3417 if (aarch64_sve_pattern_array
[opnd
->imm
.value
])
3418 snprintf (buf
, size
, "%s", aarch64_sve_pattern_array
[opnd
->imm
.value
]);
3420 snprintf (buf
, size
, "#%" PRIi64
, opnd
->imm
.value
);
3421 if (opnd
->shifter
.operator_present
)
3423 size_t len
= strlen (buf
);
3424 snprintf (buf
+ len
, size
- len
, ", %s #%" PRIi64
,
3425 aarch64_operand_modifiers
[opnd
->shifter
.kind
].name
,
3426 opnd
->shifter
.amount
);
3430 case AARCH64_OPND_SVE_PRFOP
:
3431 enum_value
= opnd
->imm
.value
;
3432 assert (enum_value
< ARRAY_SIZE (aarch64_sve_prfop_array
));
3433 if (aarch64_sve_prfop_array
[enum_value
])
3434 snprintf (buf
, size
, "%s", aarch64_sve_prfop_array
[enum_value
]);
3436 snprintf (buf
, size
, "#%" PRIi64
, opnd
->imm
.value
);
3439 case AARCH64_OPND_IMM_MOV
:
3440 switch (aarch64_get_qualifier_esize (opnds
[0].qualifier
))
3442 case 4: /* e.g. MOV Wd, #<imm32>. */
3444 int imm32
= opnd
->imm
.value
;
3445 snprintf (buf
, size
, "#0x%-20x\t// #%d", imm32
, imm32
);
3448 case 8: /* e.g. MOV Xd, #<imm64>. */
3449 snprintf (buf
, size
, "#0x%-20" PRIx64
"\t// #%" PRIi64
,
3450 opnd
->imm
.value
, opnd
->imm
.value
);
3452 default: assert (0);
3456 case AARCH64_OPND_FPIMM0
:
3457 snprintf (buf
, size
, "#0.0");
3460 case AARCH64_OPND_LIMM
:
3461 case AARCH64_OPND_AIMM
:
3462 case AARCH64_OPND_HALF
:
3463 case AARCH64_OPND_SVE_INV_LIMM
:
3464 case AARCH64_OPND_SVE_LIMM
:
3465 case AARCH64_OPND_SVE_LIMM_MOV
:
3466 if (opnd
->shifter
.amount
)
3467 snprintf (buf
, size
, "#0x%" PRIx64
", lsl #%" PRIi64
, opnd
->imm
.value
,
3468 opnd
->shifter
.amount
);
3470 snprintf (buf
, size
, "#0x%" PRIx64
, opnd
->imm
.value
);
3473 case AARCH64_OPND_SIMD_IMM
:
3474 case AARCH64_OPND_SIMD_IMM_SFT
:
3475 if ((! opnd
->shifter
.amount
&& opnd
->shifter
.kind
== AARCH64_MOD_LSL
)
3476 || opnd
->shifter
.kind
== AARCH64_MOD_NONE
)
3477 snprintf (buf
, size
, "#0x%" PRIx64
, opnd
->imm
.value
);
3479 snprintf (buf
, size
, "#0x%" PRIx64
", %s #%" PRIi64
, opnd
->imm
.value
,
3480 aarch64_operand_modifiers
[opnd
->shifter
.kind
].name
,
3481 opnd
->shifter
.amount
);
3484 case AARCH64_OPND_SVE_AIMM
:
3485 case AARCH64_OPND_SVE_ASIMM
:
3486 if (opnd
->shifter
.amount
)
3487 snprintf (buf
, size
, "#%" PRIi64
", lsl #%" PRIi64
, opnd
->imm
.value
,
3488 opnd
->shifter
.amount
);
3490 snprintf (buf
, size
, "#%" PRIi64
, opnd
->imm
.value
);
3493 case AARCH64_OPND_FPIMM
:
3494 case AARCH64_OPND_SIMD_FPIMM
:
3495 case AARCH64_OPND_SVE_FPIMM8
:
3496 switch (aarch64_get_qualifier_esize (opnds
[0].qualifier
))
3498 case 2: /* e.g. FMOV <Hd>, #<imm>. */
3501 c
.i
= expand_fp_imm (2, opnd
->imm
.value
);
3502 snprintf (buf
, size
, "#%.18e", c
.f
);
3505 case 4: /* e.g. FMOV <Vd>.4S, #<imm>. */
3508 c
.i
= expand_fp_imm (4, opnd
->imm
.value
);
3509 snprintf (buf
, size
, "#%.18e", c
.f
);
3512 case 8: /* e.g. FMOV <Sd>, #<imm>. */
3515 c
.i
= expand_fp_imm (8, opnd
->imm
.value
);
3516 snprintf (buf
, size
, "#%.18e", c
.d
);
3519 default: assert (0);
3523 case AARCH64_OPND_CCMP_IMM
:
3524 case AARCH64_OPND_NZCV
:
3525 case AARCH64_OPND_EXCEPTION
:
3526 case AARCH64_OPND_UIMM4
:
3527 case AARCH64_OPND_UIMM4_ADDG
:
3528 case AARCH64_OPND_UIMM7
:
3529 case AARCH64_OPND_UIMM10
:
3530 if (optional_operand_p (opcode
, idx
) == TRUE
3531 && (opnd
->imm
.value
==
3532 (int64_t) get_optional_operand_default_value (opcode
)))
3533 /* Omit the operand, e.g. DCPS1. */
3535 snprintf (buf
, size
, "#0x%x", (unsigned int)opnd
->imm
.value
);
3538 case AARCH64_OPND_COND
:
3539 case AARCH64_OPND_COND1
:
3540 snprintf (buf
, size
, "%s", opnd
->cond
->names
[0]);
3541 num_conds
= ARRAY_SIZE (opnd
->cond
->names
);
3542 for (i
= 1; i
< num_conds
&& opnd
->cond
->names
[i
]; ++i
)
3544 size_t len
= strlen (buf
);
3546 snprintf (buf
+ len
, size
- len
, " // %s = %s",
3547 opnd
->cond
->names
[0], opnd
->cond
->names
[i
]);
3549 snprintf (buf
+ len
, size
- len
, ", %s",
3550 opnd
->cond
->names
[i
]);
3554 case AARCH64_OPND_ADDR_ADRP
:
3555 addr
= ((pc
+ AARCH64_PCREL_OFFSET
) & ~(uint64_t)0xfff)
3561 /* This is not necessary during the disassembling, as print_address_func
3562 in the disassemble_info will take care of the printing. But some
3563 other callers may be still interested in getting the string in *STR,
3564 so here we do snprintf regardless. */
3565 snprintf (buf
, size
, "#0x%" PRIx64
, addr
);
3568 case AARCH64_OPND_ADDR_PCREL14
:
3569 case AARCH64_OPND_ADDR_PCREL19
:
3570 case AARCH64_OPND_ADDR_PCREL21
:
3571 case AARCH64_OPND_ADDR_PCREL26
:
3572 addr
= pc
+ AARCH64_PCREL_OFFSET
+ opnd
->imm
.value
;
3577 /* This is not necessary during the disassembling, as print_address_func
3578 in the disassemble_info will take care of the printing. But some
3579 other callers may be still interested in getting the string in *STR,
3580 so here we do snprintf regardless. */
3581 snprintf (buf
, size
, "#0x%" PRIx64
, addr
);
3584 case AARCH64_OPND_ADDR_SIMPLE
:
3585 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
3586 case AARCH64_OPND_SIMD_ADDR_POST
:
3587 name
= get_64bit_int_reg_name (opnd
->addr
.base_regno
, 1);
3588 if (opnd
->type
== AARCH64_OPND_SIMD_ADDR_POST
)
3590 if (opnd
->addr
.offset
.is_reg
)
3591 snprintf (buf
, size
, "[%s], x%d", name
, opnd
->addr
.offset
.regno
);
3593 snprintf (buf
, size
, "[%s], #%d", name
, opnd
->addr
.offset
.imm
);
3596 snprintf (buf
, size
, "[%s]", name
);
3599 case AARCH64_OPND_ADDR_REGOFF
:
3600 case AARCH64_OPND_SVE_ADDR_R
:
3601 case AARCH64_OPND_SVE_ADDR_RR
:
3602 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
3603 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
3604 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
3605 case AARCH64_OPND_SVE_ADDR_RX
:
3606 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
3607 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
3608 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
3609 print_register_offset_address
3610 (buf
, size
, opnd
, get_64bit_int_reg_name (opnd
->addr
.base_regno
, 1),
3611 get_offset_int_reg_name (opnd
));
3614 case AARCH64_OPND_SVE_ADDR_ZX
:
3615 print_register_offset_address
3617 get_addr_sve_reg_name (opnd
->addr
.base_regno
, opnd
->qualifier
),
3618 get_64bit_int_reg_name (opnd
->addr
.offset
.regno
, 0));
3621 case AARCH64_OPND_SVE_ADDR_RZ
:
3622 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
3623 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
3624 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
3625 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
3626 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
3627 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
3628 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
3629 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
3630 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
3631 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
3632 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
3633 print_register_offset_address
3634 (buf
, size
, opnd
, get_64bit_int_reg_name (opnd
->addr
.base_regno
, 1),
3635 get_addr_sve_reg_name (opnd
->addr
.offset
.regno
, opnd
->qualifier
));
3638 case AARCH64_OPND_ADDR_SIMM7
:
3639 case AARCH64_OPND_ADDR_SIMM9
:
3640 case AARCH64_OPND_ADDR_SIMM9_2
:
3641 case AARCH64_OPND_ADDR_SIMM10
:
3642 case AARCH64_OPND_ADDR_SIMM11
:
3643 case AARCH64_OPND_ADDR_SIMM13
:
3644 case AARCH64_OPND_ADDR_OFFSET
:
3645 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
3646 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
3647 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
3648 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
3649 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
3650 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
3651 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
3652 case AARCH64_OPND_SVE_ADDR_RI_U6
:
3653 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
3654 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
3655 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
3656 print_immediate_offset_address
3657 (buf
, size
, opnd
, get_64bit_int_reg_name (opnd
->addr
.base_regno
, 1));
3660 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
3661 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
3662 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
3663 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
3664 print_immediate_offset_address
3666 get_addr_sve_reg_name (opnd
->addr
.base_regno
, opnd
->qualifier
));
3669 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
3670 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
3671 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
3672 print_register_offset_address
3674 get_addr_sve_reg_name (opnd
->addr
.base_regno
, opnd
->qualifier
),
3675 get_addr_sve_reg_name (opnd
->addr
.offset
.regno
, opnd
->qualifier
));
3678 case AARCH64_OPND_ADDR_UIMM12
:
3679 name
= get_64bit_int_reg_name (opnd
->addr
.base_regno
, 1);
3680 if (opnd
->addr
.offset
.imm
)
3681 snprintf (buf
, size
, "[%s, #%d]", name
, opnd
->addr
.offset
.imm
);
3683 snprintf (buf
, size
, "[%s]", name
);
3686 case AARCH64_OPND_SYSREG
:
3687 for (i
= 0; aarch64_sys_regs
[i
].name
; ++i
)
3689 bfd_boolean exact_match
3690 = (aarch64_sys_regs
[i
].flags
& opnd
->sysreg
.flags
)
3691 == opnd
->sysreg
.flags
;
3693 /* Try and find an exact match, But if that fails, return the first
3694 partial match that was found. */
3695 if (aarch64_sys_regs
[i
].value
== opnd
->sysreg
.value
3696 && ! aarch64_sys_reg_deprecated_p (&aarch64_sys_regs
[i
])
3697 && (name
== NULL
|| exact_match
))
3699 name
= aarch64_sys_regs
[i
].name
;
3707 /* If we didn't match exactly, that means the presense of a flag
3708 indicates what we didn't want for this instruction. e.g. If
3709 F_REG_READ is there, that means we were looking for a write
3710 register. See aarch64_ext_sysreg. */
3711 if (aarch64_sys_regs
[i
].flags
& F_REG_WRITE
)
3712 *notes
= _("reading from a write-only register");
3713 else if (aarch64_sys_regs
[i
].flags
& F_REG_READ
)
3714 *notes
= _("writing to a read-only register");
3719 snprintf (buf
, size
, "%s", name
);
3722 /* Implementation defined system register. */
3723 unsigned int value
= opnd
->sysreg
.value
;
3724 snprintf (buf
, size
, "s%u_%u_c%u_c%u_%u", (value
>> 14) & 0x3,
3725 (value
>> 11) & 0x7, (value
>> 7) & 0xf, (value
>> 3) & 0xf,
3730 case AARCH64_OPND_PSTATEFIELD
:
3731 for (i
= 0; aarch64_pstatefields
[i
].name
; ++i
)
3732 if (aarch64_pstatefields
[i
].value
== opnd
->pstatefield
)
3734 assert (aarch64_pstatefields
[i
].name
);
3735 snprintf (buf
, size
, "%s", aarch64_pstatefields
[i
].name
);
3738 case AARCH64_OPND_SYSREG_AT
:
3739 case AARCH64_OPND_SYSREG_DC
:
3740 case AARCH64_OPND_SYSREG_IC
:
3741 case AARCH64_OPND_SYSREG_TLBI
:
3742 case AARCH64_OPND_SYSREG_SR
:
3743 snprintf (buf
, size
, "%s", opnd
->sysins_op
->name
);
3746 case AARCH64_OPND_BARRIER
:
3747 snprintf (buf
, size
, "%s", opnd
->barrier
->name
);
3750 case AARCH64_OPND_BARRIER_ISB
:
3751 /* Operand can be omitted, e.g. in DCPS1. */
3752 if (! optional_operand_p (opcode
, idx
)
3753 || (opnd
->barrier
->value
3754 != get_optional_operand_default_value (opcode
)))
3755 snprintf (buf
, size
, "#0x%x", opnd
->barrier
->value
);
3758 case AARCH64_OPND_PRFOP
:
3759 if (opnd
->prfop
->name
!= NULL
)
3760 snprintf (buf
, size
, "%s", opnd
->prfop
->name
);
3762 snprintf (buf
, size
, "#0x%02x", opnd
->prfop
->value
);
3765 case AARCH64_OPND_BARRIER_PSB
:
3766 case AARCH64_OPND_BTI_TARGET
:
3767 if ((HINT_FLAG (opnd
->hint_option
->value
) & HINT_OPD_F_NOPRINT
) == 0)
3768 snprintf (buf
, size
, "%s", opnd
->hint_option
->name
);
3776 #define CPENC(op0,op1,crn,crm,op2) \
3777 ((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5)
3778 /* for 3.9.3 Instructions for Accessing Special Purpose Registers */
3779 #define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
3780 /* for 3.9.10 System Instructions */
3781 #define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
3800 /* TODO there is one more issues need to be resolved
3801 1. handle cpu-implementation-defined system registers. */
3802 const aarch64_sys_reg aarch64_sys_regs
[] =
3804 { "spsr_el1", CPEN_(0,C0
,0), 0 }, /* = spsr_svc */
3805 { "spsr_el12", CPEN_ (5, C0
, 0), F_ARCHEXT
},
3806 { "elr_el1", CPEN_(0,C0
,1), 0 },
3807 { "elr_el12", CPEN_ (5, C0
, 1), F_ARCHEXT
},
3808 { "sp_el0", CPEN_(0,C1
,0), 0 },
3809 { "spsel", CPEN_(0,C2
,0), 0 },
3810 { "daif", CPEN_(3,C2
,1), 0 },
3811 { "currentel", CPEN_(0,C2
,2), F_REG_READ
}, /* RO */
3812 { "pan", CPEN_(0,C2
,3), F_ARCHEXT
},
3813 { "uao", CPEN_ (0, C2
, 4), F_ARCHEXT
},
3814 { "nzcv", CPEN_(3,C2
,0), 0 },
3815 { "ssbs", CPEN_(3,C2
,6), F_ARCHEXT
},
3816 { "fpcr", CPEN_(3,C4
,0), 0 },
3817 { "fpsr", CPEN_(3,C4
,1), 0 },
3818 { "dspsr_el0", CPEN_(3,C5
,0), 0 },
3819 { "dlr_el0", CPEN_(3,C5
,1), 0 },
3820 { "spsr_el2", CPEN_(4,C0
,0), 0 }, /* = spsr_hyp */
3821 { "elr_el2", CPEN_(4,C0
,1), 0 },
3822 { "sp_el1", CPEN_(4,C1
,0), 0 },
3823 { "spsr_irq", CPEN_(4,C3
,0), 0 },
3824 { "spsr_abt", CPEN_(4,C3
,1), 0 },
3825 { "spsr_und", CPEN_(4,C3
,2), 0 },
3826 { "spsr_fiq", CPEN_(4,C3
,3), 0 },
3827 { "spsr_el3", CPEN_(6,C0
,0), 0 },
3828 { "elr_el3", CPEN_(6,C0
,1), 0 },
3829 { "sp_el2", CPEN_(6,C1
,0), 0 },
3830 { "spsr_svc", CPEN_(0,C0
,0), F_DEPRECATED
}, /* = spsr_el1 */
3831 { "spsr_hyp", CPEN_(4,C0
,0), F_DEPRECATED
}, /* = spsr_el2 */
3832 { "midr_el1", CPENC(3,0,C0
,C0
,0), F_REG_READ
}, /* RO */
3833 { "ctr_el0", CPENC(3,3,C0
,C0
,1), F_REG_READ
}, /* RO */
3834 { "mpidr_el1", CPENC(3,0,C0
,C0
,5), F_REG_READ
}, /* RO */
3835 { "revidr_el1", CPENC(3,0,C0
,C0
,6), F_REG_READ
}, /* RO */
3836 { "aidr_el1", CPENC(3,1,C0
,C0
,7), F_REG_READ
}, /* RO */
3837 { "dczid_el0", CPENC(3,3,C0
,C0
,7), F_REG_READ
}, /* RO */
3838 { "id_dfr0_el1", CPENC(3,0,C0
,C1
,2), F_REG_READ
}, /* RO */
3839 { "id_pfr0_el1", CPENC(3,0,C0
,C1
,0), F_REG_READ
}, /* RO */
3840 { "id_pfr1_el1", CPENC(3,0,C0
,C1
,1), F_REG_READ
}, /* RO */
3841 { "id_pfr2_el1", CPENC(3,0,C0
,C3
,4), F_ARCHEXT
| F_REG_READ
}, /* RO */
3842 { "id_afr0_el1", CPENC(3,0,C0
,C1
,3), F_REG_READ
}, /* RO */
3843 { "id_mmfr0_el1", CPENC(3,0,C0
,C1
,4), F_REG_READ
}, /* RO */
3844 { "id_mmfr1_el1", CPENC(3,0,C0
,C1
,5), F_REG_READ
}, /* RO */
3845 { "id_mmfr2_el1", CPENC(3,0,C0
,C1
,6), F_REG_READ
}, /* RO */
3846 { "id_mmfr3_el1", CPENC(3,0,C0
,C1
,7), F_REG_READ
}, /* RO */
3847 { "id_mmfr4_el1", CPENC(3,0,C0
,C2
,6), F_REG_READ
}, /* RO */
3848 { "id_isar0_el1", CPENC(3,0,C0
,C2
,0), F_REG_READ
}, /* RO */
3849 { "id_isar1_el1", CPENC(3,0,C0
,C2
,1), F_REG_READ
}, /* RO */
3850 { "id_isar2_el1", CPENC(3,0,C0
,C2
,2), F_REG_READ
}, /* RO */
3851 { "id_isar3_el1", CPENC(3,0,C0
,C2
,3), F_REG_READ
}, /* RO */
3852 { "id_isar4_el1", CPENC(3,0,C0
,C2
,4), F_REG_READ
}, /* RO */
3853 { "id_isar5_el1", CPENC(3,0,C0
,C2
,5), F_REG_READ
}, /* RO */
3854 { "mvfr0_el1", CPENC(3,0,C0
,C3
,0), F_REG_READ
}, /* RO */
3855 { "mvfr1_el1", CPENC(3,0,C0
,C3
,1), F_REG_READ
}, /* RO */
3856 { "mvfr2_el1", CPENC(3,0,C0
,C3
,2), F_REG_READ
}, /* RO */
3857 { "ccsidr_el1", CPENC(3,1,C0
,C0
,0), F_REG_READ
}, /* RO */
3858 { "id_aa64pfr0_el1", CPENC(3,0,C0
,C4
,0), F_REG_READ
}, /* RO */
3859 { "id_aa64pfr1_el1", CPENC(3,0,C0
,C4
,1), F_REG_READ
}, /* RO */
3860 { "id_aa64dfr0_el1", CPENC(3,0,C0
,C5
,0), F_REG_READ
}, /* RO */
3861 { "id_aa64dfr1_el1", CPENC(3,0,C0
,C5
,1), F_REG_READ
}, /* RO */
3862 { "id_aa64isar0_el1", CPENC(3,0,C0
,C6
,0), F_REG_READ
}, /* RO */
3863 { "id_aa64isar1_el1", CPENC(3,0,C0
,C6
,1), F_REG_READ
}, /* RO */
3864 { "id_aa64mmfr0_el1", CPENC(3,0,C0
,C7
,0), F_REG_READ
}, /* RO */
3865 { "id_aa64mmfr1_el1", CPENC(3,0,C0
,C7
,1), F_REG_READ
}, /* RO */
3866 { "id_aa64mmfr2_el1", CPENC (3, 0, C0
, C7
, 2), F_ARCHEXT
| F_REG_READ
}, /* RO */
3867 { "id_aa64afr0_el1", CPENC(3,0,C0
,C5
,4), F_REG_READ
}, /* RO */
3868 { "id_aa64afr1_el1", CPENC(3,0,C0
,C5
,5), F_REG_READ
}, /* RO */
3869 { "id_aa64zfr0_el1", CPENC (3, 0, C0
, C4
, 4), F_ARCHEXT
| F_REG_READ
}, /* RO */
3870 { "clidr_el1", CPENC(3,1,C0
,C0
,1), F_REG_READ
}, /* RO */
3871 { "csselr_el1", CPENC(3,2,C0
,C0
,0), 0 },
3872 { "vpidr_el2", CPENC(3,4,C0
,C0
,0), 0 },
3873 { "vmpidr_el2", CPENC(3,4,C0
,C0
,5), 0 },
3874 { "sctlr_el1", CPENC(3,0,C1
,C0
,0), 0 },
3875 { "sctlr_el2", CPENC(3,4,C1
,C0
,0), 0 },
3876 { "sctlr_el3", CPENC(3,6,C1
,C0
,0), 0 },
3877 { "sctlr_el12", CPENC (3, 5, C1
, C0
, 0), F_ARCHEXT
},
3878 { "actlr_el1", CPENC(3,0,C1
,C0
,1), 0 },
3879 { "actlr_el2", CPENC(3,4,C1
,C0
,1), 0 },
3880 { "actlr_el3", CPENC(3,6,C1
,C0
,1), 0 },
3881 { "cpacr_el1", CPENC(3,0,C1
,C0
,2), 0 },
3882 { "cpacr_el12", CPENC (3, 5, C1
, C0
, 2), F_ARCHEXT
},
3883 { "cptr_el2", CPENC(3,4,C1
,C1
,2), 0 },
3884 { "cptr_el3", CPENC(3,6,C1
,C1
,2), 0 },
3885 { "scr_el3", CPENC(3,6,C1
,C1
,0), 0 },
3886 { "hcr_el2", CPENC(3,4,C1
,C1
,0), 0 },
3887 { "mdcr_el2", CPENC(3,4,C1
,C1
,1), 0 },
3888 { "mdcr_el3", CPENC(3,6,C1
,C3
,1), 0 },
3889 { "hstr_el2", CPENC(3,4,C1
,C1
,3), 0 },
3890 { "hacr_el2", CPENC(3,4,C1
,C1
,7), 0 },
3891 { "zcr_el1", CPENC (3, 0, C1
, C2
, 0), F_ARCHEXT
},
3892 { "zcr_el12", CPENC (3, 5, C1
, C2
, 0), F_ARCHEXT
},
3893 { "zcr_el2", CPENC (3, 4, C1
, C2
, 0), F_ARCHEXT
},
3894 { "zcr_el3", CPENC (3, 6, C1
, C2
, 0), F_ARCHEXT
},
3895 { "zidr_el1", CPENC (3, 0, C0
, C0
, 7), F_ARCHEXT
},
3896 { "ttbr0_el1", CPENC(3,0,C2
,C0
,0), 0 },
3897 { "ttbr1_el1", CPENC(3,0,C2
,C0
,1), 0 },
3898 { "ttbr0_el2", CPENC(3,4,C2
,C0
,0), 0 },
3899 { "ttbr1_el2", CPENC (3, 4, C2
, C0
, 1), F_ARCHEXT
},
3900 { "ttbr0_el3", CPENC(3,6,C2
,C0
,0), 0 },
3901 { "ttbr0_el12", CPENC (3, 5, C2
, C0
, 0), F_ARCHEXT
},
3902 { "ttbr1_el12", CPENC (3, 5, C2
, C0
, 1), F_ARCHEXT
},
3903 { "vttbr_el2", CPENC(3,4,C2
,C1
,0), 0 },
3904 { "tcr_el1", CPENC(3,0,C2
,C0
,2), 0 },
3905 { "tcr_el2", CPENC(3,4,C2
,C0
,2), 0 },
3906 { "tcr_el3", CPENC(3,6,C2
,C0
,2), 0 },
3907 { "tcr_el12", CPENC (3, 5, C2
, C0
, 2), F_ARCHEXT
},
3908 { "vtcr_el2", CPENC(3,4,C2
,C1
,2), 0 },
3909 { "apiakeylo_el1", CPENC (3, 0, C2
, C1
, 0), F_ARCHEXT
},
3910 { "apiakeyhi_el1", CPENC (3, 0, C2
, C1
, 1), F_ARCHEXT
},
3911 { "apibkeylo_el1", CPENC (3, 0, C2
, C1
, 2), F_ARCHEXT
},
3912 { "apibkeyhi_el1", CPENC (3, 0, C2
, C1
, 3), F_ARCHEXT
},
3913 { "apdakeylo_el1", CPENC (3, 0, C2
, C2
, 0), F_ARCHEXT
},
3914 { "apdakeyhi_el1", CPENC (3, 0, C2
, C2
, 1), F_ARCHEXT
},
3915 { "apdbkeylo_el1", CPENC (3, 0, C2
, C2
, 2), F_ARCHEXT
},
3916 { "apdbkeyhi_el1", CPENC (3, 0, C2
, C2
, 3), F_ARCHEXT
},
3917 { "apgakeylo_el1", CPENC (3, 0, C2
, C3
, 0), F_ARCHEXT
},
3918 { "apgakeyhi_el1", CPENC (3, 0, C2
, C3
, 1), F_ARCHEXT
},
3919 { "afsr0_el1", CPENC(3,0,C5
,C1
,0), 0 },
3920 { "afsr1_el1", CPENC(3,0,C5
,C1
,1), 0 },
3921 { "afsr0_el2", CPENC(3,4,C5
,C1
,0), 0 },
3922 { "afsr1_el2", CPENC(3,4,C5
,C1
,1), 0 },
3923 { "afsr0_el3", CPENC(3,6,C5
,C1
,0), 0 },
3924 { "afsr0_el12", CPENC (3, 5, C5
, C1
, 0), F_ARCHEXT
},
3925 { "afsr1_el3", CPENC(3,6,C5
,C1
,1), 0 },
3926 { "afsr1_el12", CPENC (3, 5, C5
, C1
, 1), F_ARCHEXT
},
3927 { "esr_el1", CPENC(3,0,C5
,C2
,0), 0 },
3928 { "esr_el2", CPENC(3,4,C5
,C2
,0), 0 },
3929 { "esr_el3", CPENC(3,6,C5
,C2
,0), 0 },
3930 { "esr_el12", CPENC (3, 5, C5
, C2
, 0), F_ARCHEXT
},
3931 { "vsesr_el2", CPENC (3, 4, C5
, C2
, 3), F_ARCHEXT
},
3932 { "fpexc32_el2", CPENC(3,4,C5
,C3
,0), 0 },
3933 { "erridr_el1", CPENC (3, 0, C5
, C3
, 0), F_ARCHEXT
| F_REG_READ
}, /* RO */
3934 { "errselr_el1", CPENC (3, 0, C5
, C3
, 1), F_ARCHEXT
},
3935 { "erxfr_el1", CPENC (3, 0, C5
, C4
, 0), F_ARCHEXT
| F_REG_READ
}, /* RO */
3936 { "erxctlr_el1", CPENC (3, 0, C5
, C4
, 1), F_ARCHEXT
},
3937 { "erxstatus_el1", CPENC (3, 0, C5
, C4
, 2), F_ARCHEXT
},
3938 { "erxaddr_el1", CPENC (3, 0, C5
, C4
, 3), F_ARCHEXT
},
3939 { "erxmisc0_el1", CPENC (3, 0, C5
, C5
, 0), F_ARCHEXT
},
3940 { "erxmisc1_el1", CPENC (3, 0, C5
, C5
, 1), F_ARCHEXT
},
3941 { "far_el1", CPENC(3,0,C6
,C0
,0), 0 },
3942 { "far_el2", CPENC(3,4,C6
,C0
,0), 0 },
3943 { "far_el3", CPENC(3,6,C6
,C0
,0), 0 },
3944 { "far_el12", CPENC (3, 5, C6
, C0
, 0), F_ARCHEXT
},
3945 { "hpfar_el2", CPENC(3,4,C6
,C0
,4), 0 },
3946 { "par_el1", CPENC(3,0,C7
,C4
,0), 0 },
3947 { "mair_el1", CPENC(3,0,C10
,C2
,0), 0 },
3948 { "mair_el2", CPENC(3,4,C10
,C2
,0), 0 },
3949 { "mair_el3", CPENC(3,6,C10
,C2
,0), 0 },
3950 { "mair_el12", CPENC (3, 5, C10
, C2
, 0), F_ARCHEXT
},
3951 { "amair_el1", CPENC(3,0,C10
,C3
,0), 0 },
3952 { "amair_el2", CPENC(3,4,C10
,C3
,0), 0 },
3953 { "amair_el3", CPENC(3,6,C10
,C3
,0), 0 },
3954 { "amair_el12", CPENC (3, 5, C10
, C3
, 0), F_ARCHEXT
},
3955 { "vbar_el1", CPENC(3,0,C12
,C0
,0), 0 },
3956 { "vbar_el2", CPENC(3,4,C12
,C0
,0), 0 },
3957 { "vbar_el3", CPENC(3,6,C12
,C0
,0), 0 },
3958 { "vbar_el12", CPENC (3, 5, C12
, C0
, 0), F_ARCHEXT
},
3959 { "rvbar_el1", CPENC(3,0,C12
,C0
,1), F_REG_READ
}, /* RO */
3960 { "rvbar_el2", CPENC(3,4,C12
,C0
,1), F_REG_READ
}, /* RO */
3961 { "rvbar_el3", CPENC(3,6,C12
,C0
,1), F_REG_READ
}, /* RO */
3962 { "rmr_el1", CPENC(3,0,C12
,C0
,2), 0 },
3963 { "rmr_el2", CPENC(3,4,C12
,C0
,2), 0 },
3964 { "rmr_el3", CPENC(3,6,C12
,C0
,2), 0 },
3965 { "isr_el1", CPENC(3,0,C12
,C1
,0), F_REG_READ
}, /* RO */
3966 { "disr_el1", CPENC (3, 0, C12
, C1
, 1), F_ARCHEXT
},
3967 { "vdisr_el2", CPENC (3, 4, C12
, C1
, 1), F_ARCHEXT
},
3968 { "contextidr_el1", CPENC(3,0,C13
,C0
,1), 0 },
3969 { "contextidr_el2", CPENC (3, 4, C13
, C0
, 1), F_ARCHEXT
},
3970 { "contextidr_el12", CPENC (3, 5, C13
, C0
, 1), F_ARCHEXT
},
3971 { "rndr", CPENC(3,3,C2
,C4
,0), F_ARCHEXT
| F_REG_READ
}, /* RO */
3972 { "rndrrs", CPENC(3,3,C2
,C4
,1), F_ARCHEXT
| F_REG_READ
}, /* RO */
3973 { "tco", CPENC(3,3,C4
,C2
,7), F_ARCHEXT
},
3974 { "tfsre0_el1", CPENC(3,0,C5
,C6
,1), F_ARCHEXT
},
3975 { "tfsr_el1", CPENC(3,0,C5
,C6
,0), F_ARCHEXT
},
3976 { "tfsr_el2", CPENC(3,4,C5
,C6
,0), F_ARCHEXT
},
3977 { "tfsr_el3", CPENC(3,6,C5
,C6
,0), F_ARCHEXT
},
3978 { "tfsr_el12", CPENC(3,5,C5
,C6
,0), F_ARCHEXT
},
3979 { "rgsr_el1", CPENC(3,0,C1
,C0
,5), F_ARCHEXT
},
3980 { "gcr_el1", CPENC(3,0,C1
,C0
,6), F_ARCHEXT
},
3981 { "gmid_el1", CPENC(3,1,C0
,C0
,4), F_ARCHEXT
| F_REG_READ
}, /* RO */
3982 { "tpidr_el0", CPENC(3,3,C13
,C0
,2), 0 },
3983 { "tpidrro_el0", CPENC(3,3,C13
,C0
,3), 0 }, /* RW */
3984 { "tpidr_el1", CPENC(3,0,C13
,C0
,4), 0 },
3985 { "tpidr_el2", CPENC(3,4,C13
,C0
,2), 0 },
3986 { "tpidr_el3", CPENC(3,6,C13
,C0
,2), 0 },
3987 { "scxtnum_el0", CPENC(3,3,C13
,C0
,7), F_ARCHEXT
},
3988 { "scxtnum_el1", CPENC(3,0,C13
,C0
,7), F_ARCHEXT
},
3989 { "scxtnum_el2", CPENC(3,4,C13
,C0
,7), F_ARCHEXT
},
3990 { "scxtnum_el12", CPENC(3,5,C13
,C0
,7), F_ARCHEXT
},
3991 { "scxtnum_el3", CPENC(3,6,C13
,C0
,7), F_ARCHEXT
},
3992 { "teecr32_el1", CPENC(2,2,C0
, C0
,0), 0 }, /* See section 3.9.7.1 */
3993 { "cntfrq_el0", CPENC(3,3,C14
,C0
,0), 0 }, /* RW */
3994 { "cntpct_el0", CPENC(3,3,C14
,C0
,1), F_REG_READ
}, /* RO */
3995 { "cntvct_el0", CPENC(3,3,C14
,C0
,2), F_REG_READ
}, /* RO */
3996 { "cntvoff_el2", CPENC(3,4,C14
,C0
,3), 0 },
3997 { "cntkctl_el1", CPENC(3,0,C14
,C1
,0), 0 },
3998 { "cntkctl_el12", CPENC (3, 5, C14
, C1
, 0), F_ARCHEXT
},
3999 { "cnthctl_el2", CPENC(3,4,C14
,C1
,0), 0 },
4000 { "cntp_tval_el0", CPENC(3,3,C14
,C2
,0), 0 },
4001 { "cntp_tval_el02", CPENC (3, 5, C14
, C2
, 0), F_ARCHEXT
},
4002 { "cntp_ctl_el0", CPENC(3,3,C14
,C2
,1), 0 },
4003 { "cntp_ctl_el02", CPENC (3, 5, C14
, C2
, 1), F_ARCHEXT
},
4004 { "cntp_cval_el0", CPENC(3,3,C14
,C2
,2), 0 },
4005 { "cntp_cval_el02", CPENC (3, 5, C14
, C2
, 2), F_ARCHEXT
},
4006 { "cntv_tval_el0", CPENC(3,3,C14
,C3
,0), 0 },
4007 { "cntv_tval_el02", CPENC (3, 5, C14
, C3
, 0), F_ARCHEXT
},
4008 { "cntv_ctl_el0", CPENC(3,3,C14
,C3
,1), 0 },
4009 { "cntv_ctl_el02", CPENC (3, 5, C14
, C3
, 1), F_ARCHEXT
},
4010 { "cntv_cval_el0", CPENC(3,3,C14
,C3
,2), 0 },
4011 { "cntv_cval_el02", CPENC (3, 5, C14
, C3
, 2), F_ARCHEXT
},
4012 { "cnthp_tval_el2", CPENC(3,4,C14
,C2
,0), 0 },
4013 { "cnthp_ctl_el2", CPENC(3,4,C14
,C2
,1), 0 },
4014 { "cnthp_cval_el2", CPENC(3,4,C14
,C2
,2), 0 },
4015 { "cntps_tval_el1", CPENC(3,7,C14
,C2
,0), 0 },
4016 { "cntps_ctl_el1", CPENC(3,7,C14
,C2
,1), 0 },
4017 { "cntps_cval_el1", CPENC(3,7,C14
,C2
,2), 0 },
4018 { "cnthv_tval_el2", CPENC (3, 4, C14
, C3
, 0), F_ARCHEXT
},
4019 { "cnthv_ctl_el2", CPENC (3, 4, C14
, C3
, 1), F_ARCHEXT
},
4020 { "cnthv_cval_el2", CPENC (3, 4, C14
, C3
, 2), F_ARCHEXT
},
4021 { "dacr32_el2", CPENC(3,4,C3
,C0
,0), 0 },
4022 { "ifsr32_el2", CPENC(3,4,C5
,C0
,1), 0 },
4023 { "teehbr32_el1", CPENC(2,2,C1
,C0
,0), 0 },
4024 { "sder32_el3", CPENC(3,6,C1
,C1
,1), 0 },
4025 { "mdscr_el1", CPENC(2,0,C0
, C2
, 2), 0 },
4026 { "mdccsr_el0", CPENC(2,3,C0
, C1
, 0), F_REG_READ
}, /* r */
4027 { "mdccint_el1", CPENC(2,0,C0
, C2
, 0), 0 },
4028 { "dbgdtr_el0", CPENC(2,3,C0
, C4
, 0), 0 },
4029 { "dbgdtrrx_el0", CPENC(2,3,C0
, C5
, 0), F_REG_READ
}, /* r */
4030 { "dbgdtrtx_el0", CPENC(2,3,C0
, C5
, 0), F_REG_WRITE
}, /* w */
4031 { "osdtrrx_el1", CPENC(2,0,C0
, C0
, 2), 0 },
4032 { "osdtrtx_el1", CPENC(2,0,C0
, C3
, 2), 0 },
4033 { "oseccr_el1", CPENC(2,0,C0
, C6
, 2), 0 },
4034 { "dbgvcr32_el2", CPENC(2,4,C0
, C7
, 0), 0 },
4035 { "dbgbvr0_el1", CPENC(2,0,C0
, C0
, 4), 0 },
4036 { "dbgbvr1_el1", CPENC(2,0,C0
, C1
, 4), 0 },
4037 { "dbgbvr2_el1", CPENC(2,0,C0
, C2
, 4), 0 },
4038 { "dbgbvr3_el1", CPENC(2,0,C0
, C3
, 4), 0 },
4039 { "dbgbvr4_el1", CPENC(2,0,C0
, C4
, 4), 0 },
4040 { "dbgbvr5_el1", CPENC(2,0,C0
, C5
, 4), 0 },
4041 { "dbgbvr6_el1", CPENC(2,0,C0
, C6
, 4), 0 },
4042 { "dbgbvr7_el1", CPENC(2,0,C0
, C7
, 4), 0 },
4043 { "dbgbvr8_el1", CPENC(2,0,C0
, C8
, 4), 0 },
4044 { "dbgbvr9_el1", CPENC(2,0,C0
, C9
, 4), 0 },
4045 { "dbgbvr10_el1", CPENC(2,0,C0
, C10
,4), 0 },
4046 { "dbgbvr11_el1", CPENC(2,0,C0
, C11
,4), 0 },
4047 { "dbgbvr12_el1", CPENC(2,0,C0
, C12
,4), 0 },
4048 { "dbgbvr13_el1", CPENC(2,0,C0
, C13
,4), 0 },
4049 { "dbgbvr14_el1", CPENC(2,0,C0
, C14
,4), 0 },
4050 { "dbgbvr15_el1", CPENC(2,0,C0
, C15
,4), 0 },
4051 { "dbgbcr0_el1", CPENC(2,0,C0
, C0
, 5), 0 },
4052 { "dbgbcr1_el1", CPENC(2,0,C0
, C1
, 5), 0 },
4053 { "dbgbcr2_el1", CPENC(2,0,C0
, C2
, 5), 0 },
4054 { "dbgbcr3_el1", CPENC(2,0,C0
, C3
, 5), 0 },
4055 { "dbgbcr4_el1", CPENC(2,0,C0
, C4
, 5), 0 },
4056 { "dbgbcr5_el1", CPENC(2,0,C0
, C5
, 5), 0 },
4057 { "dbgbcr6_el1", CPENC(2,0,C0
, C6
, 5), 0 },
4058 { "dbgbcr7_el1", CPENC(2,0,C0
, C7
, 5), 0 },
4059 { "dbgbcr8_el1", CPENC(2,0,C0
, C8
, 5), 0 },
4060 { "dbgbcr9_el1", CPENC(2,0,C0
, C9
, 5), 0 },
4061 { "dbgbcr10_el1", CPENC(2,0,C0
, C10
,5), 0 },
4062 { "dbgbcr11_el1", CPENC(2,0,C0
, C11
,5), 0 },
4063 { "dbgbcr12_el1", CPENC(2,0,C0
, C12
,5), 0 },
4064 { "dbgbcr13_el1", CPENC(2,0,C0
, C13
,5), 0 },
4065 { "dbgbcr14_el1", CPENC(2,0,C0
, C14
,5), 0 },
4066 { "dbgbcr15_el1", CPENC(2,0,C0
, C15
,5), 0 },
4067 { "dbgwvr0_el1", CPENC(2,0,C0
, C0
, 6), 0 },
4068 { "dbgwvr1_el1", CPENC(2,0,C0
, C1
, 6), 0 },
4069 { "dbgwvr2_el1", CPENC(2,0,C0
, C2
, 6), 0 },
4070 { "dbgwvr3_el1", CPENC(2,0,C0
, C3
, 6), 0 },
4071 { "dbgwvr4_el1", CPENC(2,0,C0
, C4
, 6), 0 },
4072 { "dbgwvr5_el1", CPENC(2,0,C0
, C5
, 6), 0 },
4073 { "dbgwvr6_el1", CPENC(2,0,C0
, C6
, 6), 0 },
4074 { "dbgwvr7_el1", CPENC(2,0,C0
, C7
, 6), 0 },
4075 { "dbgwvr8_el1", CPENC(2,0,C0
, C8
, 6), 0 },
4076 { "dbgwvr9_el1", CPENC(2,0,C0
, C9
, 6), 0 },
4077 { "dbgwvr10_el1", CPENC(2,0,C0
, C10
,6), 0 },
4078 { "dbgwvr11_el1", CPENC(2,0,C0
, C11
,6), 0 },
4079 { "dbgwvr12_el1", CPENC(2,0,C0
, C12
,6), 0 },
4080 { "dbgwvr13_el1", CPENC(2,0,C0
, C13
,6), 0 },
4081 { "dbgwvr14_el1", CPENC(2,0,C0
, C14
,6), 0 },
4082 { "dbgwvr15_el1", CPENC(2,0,C0
, C15
,6), 0 },
4083 { "dbgwcr0_el1", CPENC(2,0,C0
, C0
, 7), 0 },
4084 { "dbgwcr1_el1", CPENC(2,0,C0
, C1
, 7), 0 },
4085 { "dbgwcr2_el1", CPENC(2,0,C0
, C2
, 7), 0 },
4086 { "dbgwcr3_el1", CPENC(2,0,C0
, C3
, 7), 0 },
4087 { "dbgwcr4_el1", CPENC(2,0,C0
, C4
, 7), 0 },
4088 { "dbgwcr5_el1", CPENC(2,0,C0
, C5
, 7), 0 },
4089 { "dbgwcr6_el1", CPENC(2,0,C0
, C6
, 7), 0 },
4090 { "dbgwcr7_el1", CPENC(2,0,C0
, C7
, 7), 0 },
4091 { "dbgwcr8_el1", CPENC(2,0,C0
, C8
, 7), 0 },
4092 { "dbgwcr9_el1", CPENC(2,0,C0
, C9
, 7), 0 },
4093 { "dbgwcr10_el1", CPENC(2,0,C0
, C10
,7), 0 },
4094 { "dbgwcr11_el1", CPENC(2,0,C0
, C11
,7), 0 },
4095 { "dbgwcr12_el1", CPENC(2,0,C0
, C12
,7), 0 },
4096 { "dbgwcr13_el1", CPENC(2,0,C0
, C13
,7), 0 },
4097 { "dbgwcr14_el1", CPENC(2,0,C0
, C14
,7), 0 },
4098 { "dbgwcr15_el1", CPENC(2,0,C0
, C15
,7), 0 },
4099 { "mdrar_el1", CPENC(2,0,C1
, C0
, 0), F_REG_READ
}, /* r */
4100 { "oslar_el1", CPENC(2,0,C1
, C0
, 4), F_REG_WRITE
}, /* w */
4101 { "oslsr_el1", CPENC(2,0,C1
, C1
, 4), F_REG_READ
}, /* r */
4102 { "osdlr_el1", CPENC(2,0,C1
, C3
, 4), 0 },
4103 { "dbgprcr_el1", CPENC(2,0,C1
, C4
, 4), 0 },
4104 { "dbgclaimset_el1", CPENC(2,0,C7
, C8
, 6), 0 },
4105 { "dbgclaimclr_el1", CPENC(2,0,C7
, C9
, 6), 0 },
4106 { "dbgauthstatus_el1", CPENC(2,0,C7
, C14
,6), F_REG_READ
}, /* r */
4107 { "pmblimitr_el1", CPENC (3, 0, C9
, C10
, 0), F_ARCHEXT
}, /* rw */
4108 { "pmbptr_el1", CPENC (3, 0, C9
, C10
, 1), F_ARCHEXT
}, /* rw */
4109 { "pmbsr_el1", CPENC (3, 0, C9
, C10
, 3), F_ARCHEXT
}, /* rw */
4110 { "pmbidr_el1", CPENC (3, 0, C9
, C10
, 7), F_ARCHEXT
| F_REG_READ
}, /* ro */
4111 { "pmscr_el1", CPENC (3, 0, C9
, C9
, 0), F_ARCHEXT
}, /* rw */
4112 { "pmsicr_el1", CPENC (3, 0, C9
, C9
, 2), F_ARCHEXT
}, /* rw */
4113 { "pmsirr_el1", CPENC (3, 0, C9
, C9
, 3), F_ARCHEXT
}, /* rw */
4114 { "pmsfcr_el1", CPENC (3, 0, C9
, C9
, 4), F_ARCHEXT
}, /* rw */
4115 { "pmsevfr_el1", CPENC (3, 0, C9
, C9
, 5), F_ARCHEXT
}, /* rw */
4116 { "pmslatfr_el1", CPENC (3, 0, C9
, C9
, 6), F_ARCHEXT
}, /* rw */
4117 { "pmsidr_el1", CPENC (3, 0, C9
, C9
, 7), F_ARCHEXT
}, /* rw */
4118 { "pmscr_el2", CPENC (3, 4, C9
, C9
, 0), F_ARCHEXT
}, /* rw */
4119 { "pmscr_el12", CPENC (3, 5, C9
, C9
, 0), F_ARCHEXT
}, /* rw */
4120 { "pmcr_el0", CPENC(3,3,C9
,C12
, 0), 0 },
4121 { "pmcntenset_el0", CPENC(3,3,C9
,C12
, 1), 0 },
4122 { "pmcntenclr_el0", CPENC(3,3,C9
,C12
, 2), 0 },
4123 { "pmovsclr_el0", CPENC(3,3,C9
,C12
, 3), 0 },
4124 { "pmswinc_el0", CPENC(3,3,C9
,C12
, 4), F_REG_WRITE
}, /* w */
4125 { "pmselr_el0", CPENC(3,3,C9
,C12
, 5), 0 },
4126 { "pmceid0_el0", CPENC(3,3,C9
,C12
, 6), F_REG_READ
}, /* r */
4127 { "pmceid1_el0", CPENC(3,3,C9
,C12
, 7), F_REG_READ
}, /* r */
4128 { "pmccntr_el0", CPENC(3,3,C9
,C13
, 0), 0 },
4129 { "pmxevtyper_el0", CPENC(3,3,C9
,C13
, 1), 0 },
4130 { "pmxevcntr_el0", CPENC(3,3,C9
,C13
, 2), 0 },
4131 { "pmuserenr_el0", CPENC(3,3,C9
,C14
, 0), 0 },
4132 { "pmintenset_el1", CPENC(3,0,C9
,C14
, 1), 0 },
4133 { "pmintenclr_el1", CPENC(3,0,C9
,C14
, 2), 0 },
4134 { "pmovsset_el0", CPENC(3,3,C9
,C14
, 3), 0 },
4135 { "pmevcntr0_el0", CPENC(3,3,C14
,C8
, 0), 0 },
4136 { "pmevcntr1_el0", CPENC(3,3,C14
,C8
, 1), 0 },
4137 { "pmevcntr2_el0", CPENC(3,3,C14
,C8
, 2), 0 },
4138 { "pmevcntr3_el0", CPENC(3,3,C14
,C8
, 3), 0 },
4139 { "pmevcntr4_el0", CPENC(3,3,C14
,C8
, 4), 0 },
4140 { "pmevcntr5_el0", CPENC(3,3,C14
,C8
, 5), 0 },
4141 { "pmevcntr6_el0", CPENC(3,3,C14
,C8
, 6), 0 },
4142 { "pmevcntr7_el0", CPENC(3,3,C14
,C8
, 7), 0 },
4143 { "pmevcntr8_el0", CPENC(3,3,C14
,C9
, 0), 0 },
4144 { "pmevcntr9_el0", CPENC(3,3,C14
,C9
, 1), 0 },
4145 { "pmevcntr10_el0", CPENC(3,3,C14
,C9
, 2), 0 },
4146 { "pmevcntr11_el0", CPENC(3,3,C14
,C9
, 3), 0 },
4147 { "pmevcntr12_el0", CPENC(3,3,C14
,C9
, 4), 0 },
4148 { "pmevcntr13_el0", CPENC(3,3,C14
,C9
, 5), 0 },
4149 { "pmevcntr14_el0", CPENC(3,3,C14
,C9
, 6), 0 },
4150 { "pmevcntr15_el0", CPENC(3,3,C14
,C9
, 7), 0 },
4151 { "pmevcntr16_el0", CPENC(3,3,C14
,C10
,0), 0 },
4152 { "pmevcntr17_el0", CPENC(3,3,C14
,C10
,1), 0 },
4153 { "pmevcntr18_el0", CPENC(3,3,C14
,C10
,2), 0 },
4154 { "pmevcntr19_el0", CPENC(3,3,C14
,C10
,3), 0 },
4155 { "pmevcntr20_el0", CPENC(3,3,C14
,C10
,4), 0 },
4156 { "pmevcntr21_el0", CPENC(3,3,C14
,C10
,5), 0 },
4157 { "pmevcntr22_el0", CPENC(3,3,C14
,C10
,6), 0 },
4158 { "pmevcntr23_el0", CPENC(3,3,C14
,C10
,7), 0 },
4159 { "pmevcntr24_el0", CPENC(3,3,C14
,C11
,0), 0 },
4160 { "pmevcntr25_el0", CPENC(3,3,C14
,C11
,1), 0 },
4161 { "pmevcntr26_el0", CPENC(3,3,C14
,C11
,2), 0 },
4162 { "pmevcntr27_el0", CPENC(3,3,C14
,C11
,3), 0 },
4163 { "pmevcntr28_el0", CPENC(3,3,C14
,C11
,4), 0 },
4164 { "pmevcntr29_el0", CPENC(3,3,C14
,C11
,5), 0 },
4165 { "pmevcntr30_el0", CPENC(3,3,C14
,C11
,6), 0 },
4166 { "pmevtyper0_el0", CPENC(3,3,C14
,C12
,0), 0 },
4167 { "pmevtyper1_el0", CPENC(3,3,C14
,C12
,1), 0 },
4168 { "pmevtyper2_el0", CPENC(3,3,C14
,C12
,2), 0 },
4169 { "pmevtyper3_el0", CPENC(3,3,C14
,C12
,3), 0 },
4170 { "pmevtyper4_el0", CPENC(3,3,C14
,C12
,4), 0 },
4171 { "pmevtyper5_el0", CPENC(3,3,C14
,C12
,5), 0 },
4172 { "pmevtyper6_el0", CPENC(3,3,C14
,C12
,6), 0 },
4173 { "pmevtyper7_el0", CPENC(3,3,C14
,C12
,7), 0 },
4174 { "pmevtyper8_el0", CPENC(3,3,C14
,C13
,0), 0 },
4175 { "pmevtyper9_el0", CPENC(3,3,C14
,C13
,1), 0 },
4176 { "pmevtyper10_el0", CPENC(3,3,C14
,C13
,2), 0 },
4177 { "pmevtyper11_el0", CPENC(3,3,C14
,C13
,3), 0 },
4178 { "pmevtyper12_el0", CPENC(3,3,C14
,C13
,4), 0 },
4179 { "pmevtyper13_el0", CPENC(3,3,C14
,C13
,5), 0 },
4180 { "pmevtyper14_el0", CPENC(3,3,C14
,C13
,6), 0 },
4181 { "pmevtyper15_el0", CPENC(3,3,C14
,C13
,7), 0 },
4182 { "pmevtyper16_el0", CPENC(3,3,C14
,C14
,0), 0 },
4183 { "pmevtyper17_el0", CPENC(3,3,C14
,C14
,1), 0 },
4184 { "pmevtyper18_el0", CPENC(3,3,C14
,C14
,2), 0 },
4185 { "pmevtyper19_el0", CPENC(3,3,C14
,C14
,3), 0 },
4186 { "pmevtyper20_el0", CPENC(3,3,C14
,C14
,4), 0 },
4187 { "pmevtyper21_el0", CPENC(3,3,C14
,C14
,5), 0 },
4188 { "pmevtyper22_el0", CPENC(3,3,C14
,C14
,6), 0 },
4189 { "pmevtyper23_el0", CPENC(3,3,C14
,C14
,7), 0 },
4190 { "pmevtyper24_el0", CPENC(3,3,C14
,C15
,0), 0 },
4191 { "pmevtyper25_el0", CPENC(3,3,C14
,C15
,1), 0 },
4192 { "pmevtyper26_el0", CPENC(3,3,C14
,C15
,2), 0 },
4193 { "pmevtyper27_el0", CPENC(3,3,C14
,C15
,3), 0 },
4194 { "pmevtyper28_el0", CPENC(3,3,C14
,C15
,4), 0 },
4195 { "pmevtyper29_el0", CPENC(3,3,C14
,C15
,5), 0 },
4196 { "pmevtyper30_el0", CPENC(3,3,C14
,C15
,6), 0 },
4197 { "pmccfiltr_el0", CPENC(3,3,C14
,C15
,7), 0 },
4199 { "dit", CPEN_ (3, C2
, 5), F_ARCHEXT
},
4200 { "vstcr_el2", CPENC(3, 4, C2
, C6
, 2), F_ARCHEXT
},
4201 { "vsttbr_el2", CPENC(3, 4, C2
, C6
, 0), F_ARCHEXT
},
4202 { "cnthvs_tval_el2", CPENC(3, 4, C14
, C4
, 0), F_ARCHEXT
},
4203 { "cnthvs_cval_el2", CPENC(3, 4, C14
, C4
, 2), F_ARCHEXT
},
4204 { "cnthvs_ctl_el2", CPENC(3, 4, C14
, C4
, 1), F_ARCHEXT
},
4205 { "cnthps_tval_el2", CPENC(3, 4, C14
, C5
, 0), F_ARCHEXT
},
4206 { "cnthps_cval_el2", CPENC(3, 4, C14
, C5
, 2), F_ARCHEXT
},
4207 { "cnthps_ctl_el2", CPENC(3, 4, C14
, C5
, 1), F_ARCHEXT
},
4208 { "sder32_el2", CPENC(3, 4, C1
, C3
, 1), F_ARCHEXT
},
4209 { "vncr_el2", CPENC(3, 4, C2
, C2
, 0), F_ARCHEXT
},
4210 { 0, CPENC(0,0,0,0,0), 0 },
4214 aarch64_sys_reg_deprecated_p (const aarch64_sys_reg
*reg
)
4216 return (reg
->flags
& F_DEPRECATED
) != 0;
4220 aarch64_sys_reg_supported_p (const aarch64_feature_set features
,
4221 const aarch64_sys_reg
*reg
)
4223 if (!(reg
->flags
& F_ARCHEXT
))
4226 /* PAN. Values are from aarch64_sys_regs. */
4227 if (reg
->value
== CPEN_(0,C2
,3)
4228 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_PAN
))
4231 /* SCXTNUM_ELx registers. */
4232 if ((reg
->value
== CPENC (3, 3, C13
, C0
, 7)
4233 || reg
->value
== CPENC (3, 0, C13
, C0
, 7)
4234 || reg
->value
== CPENC (3, 4, C13
, C0
, 7)
4235 || reg
->value
== CPENC (3, 6, C13
, C0
, 7)
4236 || reg
->value
== CPENC (3, 5, C13
, C0
, 7))
4237 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_SCXTNUM
))
4240 /* ID_PFR2_EL1 register. */
4241 if (reg
->value
== CPENC(3, 0, C0
, C3
, 4)
4242 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_ID_PFR2
))
4245 /* SSBS. Values are from aarch64_sys_regs. */
4246 if (reg
->value
== CPEN_(3,C2
,6)
4247 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_SSBS
))
4250 /* Virtualization host extensions: system registers. */
4251 if ((reg
->value
== CPENC (3, 4, C2
, C0
, 1)
4252 || reg
->value
== CPENC (3, 4, C13
, C0
, 1)
4253 || reg
->value
== CPENC (3, 4, C14
, C3
, 0)
4254 || reg
->value
== CPENC (3, 4, C14
, C3
, 1)
4255 || reg
->value
== CPENC (3, 4, C14
, C3
, 2))
4256 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_V8_1
))
4259 /* Virtualization host extensions: *_el12 names of *_el1 registers. */
4260 if ((reg
->value
== CPEN_ (5, C0
, 0)
4261 || reg
->value
== CPEN_ (5, C0
, 1)
4262 || reg
->value
== CPENC (3, 5, C1
, C0
, 0)
4263 || reg
->value
== CPENC (3, 5, C1
, C0
, 2)
4264 || reg
->value
== CPENC (3, 5, C2
, C0
, 0)
4265 || reg
->value
== CPENC (3, 5, C2
, C0
, 1)
4266 || reg
->value
== CPENC (3, 5, C2
, C0
, 2)
4267 || reg
->value
== CPENC (3, 5, C5
, C1
, 0)
4268 || reg
->value
== CPENC (3, 5, C5
, C1
, 1)
4269 || reg
->value
== CPENC (3, 5, C5
, C2
, 0)
4270 || reg
->value
== CPENC (3, 5, C6
, C0
, 0)
4271 || reg
->value
== CPENC (3, 5, C10
, C2
, 0)
4272 || reg
->value
== CPENC (3, 5, C10
, C3
, 0)
4273 || reg
->value
== CPENC (3, 5, C12
, C0
, 0)
4274 || reg
->value
== CPENC (3, 5, C13
, C0
, 1)
4275 || reg
->value
== CPENC (3, 5, C14
, C1
, 0))
4276 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_V8_1
))
4279 /* Virtualization host extensions: *_el02 names of *_el0 registers. */
4280 if ((reg
->value
== CPENC (3, 5, C14
, C2
, 0)
4281 || reg
->value
== CPENC (3, 5, C14
, C2
, 1)
4282 || reg
->value
== CPENC (3, 5, C14
, C2
, 2)
4283 || reg
->value
== CPENC (3, 5, C14
, C3
, 0)
4284 || reg
->value
== CPENC (3, 5, C14
, C3
, 1)
4285 || reg
->value
== CPENC (3, 5, C14
, C3
, 2))
4286 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_V8_1
))
4289 /* ARMv8.2 features. */
4291 /* ID_AA64MMFR2_EL1. */
4292 if (reg
->value
== CPENC (3, 0, C0
, C7
, 2)
4293 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_V8_2
))
4297 if (reg
->value
== CPEN_ (0, C2
, 4)
4298 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_V8_2
))
4301 /* RAS extension. */
4303 /* ERRIDR_EL1, ERRSELR_EL1, ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1,
4304 ERXMISC0_EL1 AND ERXMISC1_EL1. */
4305 if ((reg
->value
== CPENC (3, 0, C5
, C3
, 0)
4306 || reg
->value
== CPENC (3, 0, C5
, C3
, 1)
4307 || reg
->value
== CPENC (3, 0, C5
, C3
, 2)
4308 || reg
->value
== CPENC (3, 0, C5
, C3
, 3)
4309 || reg
->value
== CPENC (3, 0, C5
, C4
, 0)
4310 || reg
->value
== CPENC (3, 0, C5
, C4
, 1)
4311 || reg
->value
== CPENC (3, 0, C5
, C4
, 2)
4312 || reg
->value
== CPENC (3, 0, C5
, C4
, 3)
4313 || reg
->value
== CPENC (3, 0, C5
, C5
, 0)
4314 || reg
->value
== CPENC (3, 0, C5
, C5
, 1))
4315 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_RAS
))
4318 /* VSESR_EL2, DISR_EL1 and VDISR_EL2. */
4319 if ((reg
->value
== CPENC (3, 4, C5
, C2
, 3)
4320 || reg
->value
== CPENC (3, 0, C12
, C1
, 1)
4321 || reg
->value
== CPENC (3, 4, C12
, C1
, 1))
4322 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_RAS
))
4325 /* Statistical Profiling extension. */
4326 if ((reg
->value
== CPENC (3, 0, C9
, C10
, 0)
4327 || reg
->value
== CPENC (3, 0, C9
, C10
, 1)
4328 || reg
->value
== CPENC (3, 0, C9
, C10
, 3)
4329 || reg
->value
== CPENC (3, 0, C9
, C10
, 7)
4330 || reg
->value
== CPENC (3, 0, C9
, C9
, 0)
4331 || reg
->value
== CPENC (3, 0, C9
, C9
, 2)
4332 || reg
->value
== CPENC (3, 0, C9
, C9
, 3)
4333 || reg
->value
== CPENC (3, 0, C9
, C9
, 4)
4334 || reg
->value
== CPENC (3, 0, C9
, C9
, 5)
4335 || reg
->value
== CPENC (3, 0, C9
, C9
, 6)
4336 || reg
->value
== CPENC (3, 0, C9
, C9
, 7)
4337 || reg
->value
== CPENC (3, 4, C9
, C9
, 0)
4338 || reg
->value
== CPENC (3, 5, C9
, C9
, 0))
4339 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_PROFILE
))
4342 /* ARMv8.3 Pointer authentication keys. */
4343 if ((reg
->value
== CPENC (3, 0, C2
, C1
, 0)
4344 || reg
->value
== CPENC (3, 0, C2
, C1
, 1)
4345 || reg
->value
== CPENC (3, 0, C2
, C1
, 2)
4346 || reg
->value
== CPENC (3, 0, C2
, C1
, 3)
4347 || reg
->value
== CPENC (3, 0, C2
, C2
, 0)
4348 || reg
->value
== CPENC (3, 0, C2
, C2
, 1)
4349 || reg
->value
== CPENC (3, 0, C2
, C2
, 2)
4350 || reg
->value
== CPENC (3, 0, C2
, C2
, 3)
4351 || reg
->value
== CPENC (3, 0, C2
, C3
, 0)
4352 || reg
->value
== CPENC (3, 0, C2
, C3
, 1))
4353 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_V8_3
))
4357 if ((reg
->value
== CPENC (3, 0, C0
, C4
, 4)
4358 || reg
->value
== CPENC (3, 0, C1
, C2
, 0)
4359 || reg
->value
== CPENC (3, 4, C1
, C2
, 0)
4360 || reg
->value
== CPENC (3, 6, C1
, C2
, 0)
4361 || reg
->value
== CPENC (3, 5, C1
, C2
, 0)
4362 || reg
->value
== CPENC (3, 0, C0
, C0
, 7))
4363 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_SVE
))
4366 /* ARMv8.4 features. */
4369 if (reg
->value
== CPEN_ (3, C2
, 5)
4370 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_V8_4
))
4373 /* Virtualization extensions. */
4374 if ((reg
->value
== CPENC(3, 4, C2
, C6
, 2)
4375 || reg
->value
== CPENC(3, 4, C2
, C6
, 0)
4376 || reg
->value
== CPENC(3, 4, C14
, C4
, 0)
4377 || reg
->value
== CPENC(3, 4, C14
, C4
, 2)
4378 || reg
->value
== CPENC(3, 4, C14
, C4
, 1)
4379 || reg
->value
== CPENC(3, 4, C14
, C5
, 0)
4380 || reg
->value
== CPENC(3, 4, C14
, C5
, 2)
4381 || reg
->value
== CPENC(3, 4, C14
, C5
, 1)
4382 || reg
->value
== CPENC(3, 4, C1
, C3
, 1)
4383 || reg
->value
== CPENC(3, 4, C2
, C2
, 0))
4384 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_V8_4
))
4387 /* ARMv8.4 TLB instructions. */
4388 if ((reg
->value
== CPENS (0, C8
, C1
, 0)
4389 || reg
->value
== CPENS (0, C8
, C1
, 1)
4390 || reg
->value
== CPENS (0, C8
, C1
, 2)
4391 || reg
->value
== CPENS (0, C8
, C1
, 3)
4392 || reg
->value
== CPENS (0, C8
, C1
, 5)
4393 || reg
->value
== CPENS (0, C8
, C1
, 7)
4394 || reg
->value
== CPENS (4, C8
, C4
, 0)
4395 || reg
->value
== CPENS (4, C8
, C4
, 4)
4396 || reg
->value
== CPENS (4, C8
, C1
, 1)
4397 || reg
->value
== CPENS (4, C8
, C1
, 5)
4398 || reg
->value
== CPENS (4, C8
, C1
, 6)
4399 || reg
->value
== CPENS (6, C8
, C1
, 1)
4400 || reg
->value
== CPENS (6, C8
, C1
, 5)
4401 || reg
->value
== CPENS (4, C8
, C1
, 0)
4402 || reg
->value
== CPENS (4, C8
, C1
, 4)
4403 || reg
->value
== CPENS (6, C8
, C1
, 0)
4404 || reg
->value
== CPENS (0, C8
, C6
, 1)
4405 || reg
->value
== CPENS (0, C8
, C6
, 3)
4406 || reg
->value
== CPENS (0, C8
, C6
, 5)
4407 || reg
->value
== CPENS (0, C8
, C6
, 7)
4408 || reg
->value
== CPENS (0, C8
, C2
, 1)
4409 || reg
->value
== CPENS (0, C8
, C2
, 3)
4410 || reg
->value
== CPENS (0, C8
, C2
, 5)
4411 || reg
->value
== CPENS (0, C8
, C2
, 7)
4412 || reg
->value
== CPENS (0, C8
, C5
, 1)
4413 || reg
->value
== CPENS (0, C8
, C5
, 3)
4414 || reg
->value
== CPENS (0, C8
, C5
, 5)
4415 || reg
->value
== CPENS (0, C8
, C5
, 7)
4416 || reg
->value
== CPENS (4, C8
, C0
, 2)
4417 || reg
->value
== CPENS (4, C8
, C0
, 6)
4418 || reg
->value
== CPENS (4, C8
, C4
, 2)
4419 || reg
->value
== CPENS (4, C8
, C4
, 6)
4420 || reg
->value
== CPENS (4, C8
, C4
, 3)
4421 || reg
->value
== CPENS (4, C8
, C4
, 7)
4422 || reg
->value
== CPENS (4, C8
, C6
, 1)
4423 || reg
->value
== CPENS (4, C8
, C6
, 5)
4424 || reg
->value
== CPENS (4, C8
, C2
, 1)
4425 || reg
->value
== CPENS (4, C8
, C2
, 5)
4426 || reg
->value
== CPENS (4, C8
, C5
, 1)
4427 || reg
->value
== CPENS (4, C8
, C5
, 5)
4428 || reg
->value
== CPENS (6, C8
, C6
, 1)
4429 || reg
->value
== CPENS (6, C8
, C6
, 5)
4430 || reg
->value
== CPENS (6, C8
, C2
, 1)
4431 || reg
->value
== CPENS (6, C8
, C2
, 5)
4432 || reg
->value
== CPENS (6, C8
, C5
, 1)
4433 || reg
->value
== CPENS (6, C8
, C5
, 5))
4434 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_V8_4
))
4437 /* Random Number Instructions. For now they are available
4438 (and optional) only with ARMv8.5-A. */
4439 if ((reg
->value
== CPENC (3, 3, C2
, C4
, 0)
4440 || reg
->value
== CPENC (3, 3, C2
, C4
, 1))
4441 && !(AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_RNG
)
4442 && AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_V8_5
)))
4445 /* System Registers in ARMv8.5-A with AARCH64_FEATURE_MEMTAG. */
4446 if ((reg
->value
== CPENC (3, 3, C4
, C2
, 7)
4447 || reg
->value
== CPENC (3, 0, C5
, C6
, 1)
4448 || reg
->value
== CPENC (3, 0, C5
, C6
, 0)
4449 || reg
->value
== CPENC (3, 4, C5
, C6
, 0)
4450 || reg
->value
== CPENC (3, 6, C5
, C6
, 0)
4451 || reg
->value
== CPENC (3, 5, C5
, C6
, 0)
4452 || reg
->value
== CPENC (3, 0, C1
, C0
, 5)
4453 || reg
->value
== CPENC (3, 0, C1
, C0
, 6)
4454 || reg
->value
== CPENC (3, 1, C0
, C0
, 4))
4455 && !(AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_MEMTAG
)))
4461 /* The CPENC below is fairly misleading, the fields
4462 here are not in CPENC form. They are in op2op1 form. The fields are encoded
4463 by ins_pstatefield, which just shifts the value by the width of the fields
4464 in a loop. So if you CPENC them only the first value will be set, the rest
4465 are masked out to 0. As an example. op2 = 3, op1=2. CPENC would produce a
4466 value of 0b110000000001000000 (0x30040) while what you want is
4468 const aarch64_sys_reg aarch64_pstatefields
[] =
4470 { "spsel", 0x05, 0 },
4471 { "daifset", 0x1e, 0 },
4472 { "daifclr", 0x1f, 0 },
4473 { "pan", 0x04, F_ARCHEXT
},
4474 { "uao", 0x03, F_ARCHEXT
},
4475 { "ssbs", 0x19, F_ARCHEXT
},
4476 { "dit", 0x1a, F_ARCHEXT
},
4477 { "tco", 0x1c, F_ARCHEXT
},
4478 { 0, CPENC(0,0,0,0,0), 0 },
4482 aarch64_pstatefield_supported_p (const aarch64_feature_set features
,
4483 const aarch64_sys_reg
*reg
)
4485 if (!(reg
->flags
& F_ARCHEXT
))
4488 /* PAN. Values are from aarch64_pstatefields. */
4489 if (reg
->value
== 0x04
4490 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_PAN
))
4493 /* UAO. Values are from aarch64_pstatefields. */
4494 if (reg
->value
== 0x03
4495 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_V8_2
))
4498 /* SSBS. Values are from aarch64_pstatefields. */
4499 if (reg
->value
== 0x19
4500 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_SSBS
))
4503 /* DIT. Values are from aarch64_pstatefields. */
4504 if (reg
->value
== 0x1a
4505 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_V8_4
))
4508 /* TCO. Values are from aarch64_pstatefields. */
4509 if (reg
->value
== 0x1c
4510 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_MEMTAG
))
4516 const aarch64_sys_ins_reg aarch64_sys_regs_ic
[] =
4518 { "ialluis", CPENS(0,C7
,C1
,0), 0 },
4519 { "iallu", CPENS(0,C7
,C5
,0), 0 },
4520 { "ivau", CPENS (3, C7
, C5
, 1), F_HASXT
},
4521 { 0, CPENS(0,0,0,0), 0 }
4524 const aarch64_sys_ins_reg aarch64_sys_regs_dc
[] =
4526 { "zva", CPENS (3, C7
, C4
, 1), F_HASXT
},
4527 { "gva", CPENS (3, C7
, C4
, 3), F_HASXT
| F_ARCHEXT
},
4528 { "gzva", CPENS (3, C7
, C4
, 4), F_HASXT
| F_ARCHEXT
},
4529 { "ivac", CPENS (0, C7
, C6
, 1), F_HASXT
},
4530 { "igvac", CPENS (0, C7
, C6
, 3), F_HASXT
| F_ARCHEXT
},
4531 { "igsw", CPENS (0, C7
, C6
, 4), F_HASXT
| F_ARCHEXT
},
4532 { "isw", CPENS (0, C7
, C6
, 2), F_HASXT
},
4533 { "igdvac", CPENS (0, C7
, C6
, 5), F_HASXT
| F_ARCHEXT
},
4534 { "igdsw", CPENS (0, C7
, C6
, 6), F_HASXT
| F_ARCHEXT
},
4535 { "cvac", CPENS (3, C7
, C10
, 1), F_HASXT
},
4536 { "cgvac", CPENS (3, C7
, C10
, 3), F_HASXT
| F_ARCHEXT
},
4537 { "cgdvac", CPENS (3, C7
, C10
, 5), F_HASXT
| F_ARCHEXT
},
4538 { "csw", CPENS (0, C7
, C10
, 2), F_HASXT
},
4539 { "cgsw", CPENS (0, C7
, C10
, 4), F_HASXT
| F_ARCHEXT
},
4540 { "cgdsw", CPENS (0, C7
, C10
, 6), F_HASXT
| F_ARCHEXT
},
4541 { "cvau", CPENS (3, C7
, C11
, 1), F_HASXT
},
4542 { "cvap", CPENS (3, C7
, C12
, 1), F_HASXT
| F_ARCHEXT
},
4543 { "cgvap", CPENS (3, C7
, C12
, 3), F_HASXT
| F_ARCHEXT
},
4544 { "cgdvap", CPENS (3, C7
, C12
, 5), F_HASXT
| F_ARCHEXT
},
4545 { "cvadp", CPENS (3, C7
, C13
, 1), F_HASXT
| F_ARCHEXT
},
4546 { "cgvadp", CPENS (3, C7
, C13
, 3), F_HASXT
| F_ARCHEXT
},
4547 { "cgdvadp", CPENS (3, C7
, C13
, 5), F_HASXT
| F_ARCHEXT
},
4548 { "civac", CPENS (3, C7
, C14
, 1), F_HASXT
},
4549 { "cigvac", CPENS (3, C7
, C14
, 3), F_HASXT
| F_ARCHEXT
},
4550 { "cigdvac", CPENS (3, C7
, C14
, 5), F_HASXT
| F_ARCHEXT
},
4551 { "cisw", CPENS (0, C7
, C14
, 2), F_HASXT
},
4552 { "cigsw", CPENS (0, C7
, C14
, 4), F_HASXT
| F_ARCHEXT
},
4553 { "cigdsw", CPENS (0, C7
, C14
, 6), F_HASXT
| F_ARCHEXT
},
4554 { 0, CPENS(0,0,0,0), 0 }
4557 const aarch64_sys_ins_reg aarch64_sys_regs_at
[] =
4559 { "s1e1r", CPENS (0, C7
, C8
, 0), F_HASXT
},
4560 { "s1e1w", CPENS (0, C7
, C8
, 1), F_HASXT
},
4561 { "s1e0r", CPENS (0, C7
, C8
, 2), F_HASXT
},
4562 { "s1e0w", CPENS (0, C7
, C8
, 3), F_HASXT
},
4563 { "s12e1r", CPENS (4, C7
, C8
, 4), F_HASXT
},
4564 { "s12e1w", CPENS (4, C7
, C8
, 5), F_HASXT
},
4565 { "s12e0r", CPENS (4, C7
, C8
, 6), F_HASXT
},
4566 { "s12e0w", CPENS (4, C7
, C8
, 7), F_HASXT
},
4567 { "s1e2r", CPENS (4, C7
, C8
, 0), F_HASXT
},
4568 { "s1e2w", CPENS (4, C7
, C8
, 1), F_HASXT
},
4569 { "s1e3r", CPENS (6, C7
, C8
, 0), F_HASXT
},
4570 { "s1e3w", CPENS (6, C7
, C8
, 1), F_HASXT
},
4571 { "s1e1rp", CPENS (0, C7
, C9
, 0), F_HASXT
| F_ARCHEXT
},
4572 { "s1e1wp", CPENS (0, C7
, C9
, 1), F_HASXT
| F_ARCHEXT
},
4573 { 0, CPENS(0,0,0,0), 0 }
4576 const aarch64_sys_ins_reg aarch64_sys_regs_tlbi
[] =
4578 { "vmalle1", CPENS(0,C8
,C7
,0), 0 },
4579 { "vae1", CPENS (0, C8
, C7
, 1), F_HASXT
},
4580 { "aside1", CPENS (0, C8
, C7
, 2), F_HASXT
},
4581 { "vaae1", CPENS (0, C8
, C7
, 3), F_HASXT
},
4582 { "vmalle1is", CPENS(0,C8
,C3
,0), 0 },
4583 { "vae1is", CPENS (0, C8
, C3
, 1), F_HASXT
},
4584 { "aside1is", CPENS (0, C8
, C3
, 2), F_HASXT
},
4585 { "vaae1is", CPENS (0, C8
, C3
, 3), F_HASXT
},
4586 { "ipas2e1is", CPENS (4, C8
, C0
, 1), F_HASXT
},
4587 { "ipas2le1is",CPENS (4, C8
, C0
, 5), F_HASXT
},
4588 { "ipas2e1", CPENS (4, C8
, C4
, 1), F_HASXT
},
4589 { "ipas2le1", CPENS (4, C8
, C4
, 5), F_HASXT
},
4590 { "vae2", CPENS (4, C8
, C7
, 1), F_HASXT
},
4591 { "vae2is", CPENS (4, C8
, C3
, 1), F_HASXT
},
4592 { "vmalls12e1",CPENS(4,C8
,C7
,6), 0 },
4593 { "vmalls12e1is",CPENS(4,C8
,C3
,6), 0 },
4594 { "vae3", CPENS (6, C8
, C7
, 1), F_HASXT
},
4595 { "vae3is", CPENS (6, C8
, C3
, 1), F_HASXT
},
4596 { "alle2", CPENS(4,C8
,C7
,0), 0 },
4597 { "alle2is", CPENS(4,C8
,C3
,0), 0 },
4598 { "alle1", CPENS(4,C8
,C7
,4), 0 },
4599 { "alle1is", CPENS(4,C8
,C3
,4), 0 },
4600 { "alle3", CPENS(6,C8
,C7
,0), 0 },
4601 { "alle3is", CPENS(6,C8
,C3
,0), 0 },
4602 { "vale1is", CPENS (0, C8
, C3
, 5), F_HASXT
},
4603 { "vale2is", CPENS (4, C8
, C3
, 5), F_HASXT
},
4604 { "vale3is", CPENS (6, C8
, C3
, 5), F_HASXT
},
4605 { "vaale1is", CPENS (0, C8
, C3
, 7), F_HASXT
},
4606 { "vale1", CPENS (0, C8
, C7
, 5), F_HASXT
},
4607 { "vale2", CPENS (4, C8
, C7
, 5), F_HASXT
},
4608 { "vale3", CPENS (6, C8
, C7
, 5), F_HASXT
},
4609 { "vaale1", CPENS (0, C8
, C7
, 7), F_HASXT
},
4611 { "vmalle1os", CPENS (0, C8
, C1
, 0), F_ARCHEXT
},
4612 { "vae1os", CPENS (0, C8
, C1
, 1), F_HASXT
| F_ARCHEXT
},
4613 { "aside1os", CPENS (0, C8
, C1
, 2), F_HASXT
| F_ARCHEXT
},
4614 { "vaae1os", CPENS (0, C8
, C1
, 3), F_HASXT
| F_ARCHEXT
},
4615 { "vale1os", CPENS (0, C8
, C1
, 5), F_HASXT
| F_ARCHEXT
},
4616 { "vaale1os", CPENS (0, C8
, C1
, 7), F_HASXT
| F_ARCHEXT
},
4617 { "ipas2e1os", CPENS (4, C8
, C4
, 0), F_HASXT
| F_ARCHEXT
},
4618 { "ipas2le1os", CPENS (4, C8
, C4
, 4), F_HASXT
| F_ARCHEXT
},
4619 { "vae2os", CPENS (4, C8
, C1
, 1), F_HASXT
| F_ARCHEXT
},
4620 { "vale2os", CPENS (4, C8
, C1
, 5), F_HASXT
| F_ARCHEXT
},
4621 { "vmalls12e1os", CPENS (4, C8
, C1
, 6), F_ARCHEXT
},
4622 { "vae3os", CPENS (6, C8
, C1
, 1), F_HASXT
| F_ARCHEXT
},
4623 { "vale3os", CPENS (6, C8
, C1
, 5), F_HASXT
| F_ARCHEXT
},
4624 { "alle2os", CPENS (4, C8
, C1
, 0), F_ARCHEXT
},
4625 { "alle1os", CPENS (4, C8
, C1
, 4), F_ARCHEXT
},
4626 { "alle3os", CPENS (6, C8
, C1
, 0), F_ARCHEXT
},
4628 { "rvae1", CPENS (0, C8
, C6
, 1), F_HASXT
| F_ARCHEXT
},
4629 { "rvaae1", CPENS (0, C8
, C6
, 3), F_HASXT
| F_ARCHEXT
},
4630 { "rvale1", CPENS (0, C8
, C6
, 5), F_HASXT
| F_ARCHEXT
},
4631 { "rvaale1", CPENS (0, C8
, C6
, 7), F_HASXT
| F_ARCHEXT
},
4632 { "rvae1is", CPENS (0, C8
, C2
, 1), F_HASXT
| F_ARCHEXT
},
4633 { "rvaae1is", CPENS (0, C8
, C2
, 3), F_HASXT
| F_ARCHEXT
},
4634 { "rvale1is", CPENS (0, C8
, C2
, 5), F_HASXT
| F_ARCHEXT
},
4635 { "rvaale1is", CPENS (0, C8
, C2
, 7), F_HASXT
| F_ARCHEXT
},
4636 { "rvae1os", CPENS (0, C8
, C5
, 1), F_HASXT
| F_ARCHEXT
},
4637 { "rvaae1os", CPENS (0, C8
, C5
, 3), F_HASXT
| F_ARCHEXT
},
4638 { "rvale1os", CPENS (0, C8
, C5
, 5), F_HASXT
| F_ARCHEXT
},
4639 { "rvaale1os", CPENS (0, C8
, C5
, 7), F_HASXT
| F_ARCHEXT
},
4640 { "ripas2e1is", CPENS (4, C8
, C0
, 2), F_HASXT
| F_ARCHEXT
},
4641 { "ripas2le1is",CPENS (4, C8
, C0
, 6), F_HASXT
| F_ARCHEXT
},
4642 { "ripas2e1", CPENS (4, C8
, C4
, 2), F_HASXT
| F_ARCHEXT
},
4643 { "ripas2le1", CPENS (4, C8
, C4
, 6), F_HASXT
| F_ARCHEXT
},
4644 { "ripas2e1os", CPENS (4, C8
, C4
, 3), F_HASXT
| F_ARCHEXT
},
4645 { "ripas2le1os",CPENS (4, C8
, C4
, 7), F_HASXT
| F_ARCHEXT
},
4646 { "rvae2", CPENS (4, C8
, C6
, 1), F_HASXT
| F_ARCHEXT
},
4647 { "rvale2", CPENS (4, C8
, C6
, 5), F_HASXT
| F_ARCHEXT
},
4648 { "rvae2is", CPENS (4, C8
, C2
, 1), F_HASXT
| F_ARCHEXT
},
4649 { "rvale2is", CPENS (4, C8
, C2
, 5), F_HASXT
| F_ARCHEXT
},
4650 { "rvae2os", CPENS (4, C8
, C5
, 1), F_HASXT
| F_ARCHEXT
},
4651 { "rvale2os", CPENS (4, C8
, C5
, 5), F_HASXT
| F_ARCHEXT
},
4652 { "rvae3", CPENS (6, C8
, C6
, 1), F_HASXT
| F_ARCHEXT
},
4653 { "rvale3", CPENS (6, C8
, C6
, 5), F_HASXT
| F_ARCHEXT
},
4654 { "rvae3is", CPENS (6, C8
, C2
, 1), F_HASXT
| F_ARCHEXT
},
4655 { "rvale3is", CPENS (6, C8
, C2
, 5), F_HASXT
| F_ARCHEXT
},
4656 { "rvae3os", CPENS (6, C8
, C5
, 1), F_HASXT
| F_ARCHEXT
},
4657 { "rvale3os", CPENS (6, C8
, C5
, 5), F_HASXT
| F_ARCHEXT
},
4659 { 0, CPENS(0,0,0,0), 0 }
4662 const aarch64_sys_ins_reg aarch64_sys_regs_sr
[] =
4664 /* RCTX is somewhat unique in a way that it has different values
4665 (op2) based on the instruction in which it is used (cfp/dvp/cpp).
4666 Thus op2 is masked out and instead encoded directly in the
4667 aarch64_opcode_table entries for the respective instructions. */
4668 { "rctx", CPENS(3,C7
,C3
,0), F_HASXT
| F_ARCHEXT
| F_REG_WRITE
}, /* WO */
4670 { 0, CPENS(0,0,0,0), 0 }
4674 aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg
*sys_ins_reg
)
4676 return (sys_ins_reg
->flags
& F_HASXT
) != 0;
4680 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features
,
4681 const aarch64_sys_ins_reg
*reg
)
4683 if (!(reg
->flags
& F_ARCHEXT
))
4686 /* DC CVAP. Values are from aarch64_sys_regs_dc. */
4687 if (reg
->value
== CPENS (3, C7
, C12
, 1)
4688 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_V8_2
))
4691 /* DC CVADP. Values are from aarch64_sys_regs_dc. */
4692 if (reg
->value
== CPENS (3, C7
, C13
, 1)
4693 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_CVADP
))
4696 /* DC <dc_op> for ARMv8.5-A Memory Tagging Extension. */
4697 if ((reg
->value
== CPENS (0, C7
, C6
, 3)
4698 || reg
->value
== CPENS (0, C7
, C6
, 4)
4699 || reg
->value
== CPENS (0, C7
, C10
, 4)
4700 || reg
->value
== CPENS (0, C7
, C14
, 4)
4701 || reg
->value
== CPENS (3, C7
, C10
, 3)
4702 || reg
->value
== CPENS (3, C7
, C12
, 3)
4703 || reg
->value
== CPENS (3, C7
, C13
, 3)
4704 || reg
->value
== CPENS (3, C7
, C14
, 3)
4705 || reg
->value
== CPENS (3, C7
, C4
, 3)
4706 || reg
->value
== CPENS (0, C7
, C6
, 5)
4707 || reg
->value
== CPENS (0, C7
, C6
, 6)
4708 || reg
->value
== CPENS (0, C7
, C10
, 6)
4709 || reg
->value
== CPENS (0, C7
, C14
, 6)
4710 || reg
->value
== CPENS (3, C7
, C10
, 5)
4711 || reg
->value
== CPENS (3, C7
, C12
, 5)
4712 || reg
->value
== CPENS (3, C7
, C13
, 5)
4713 || reg
->value
== CPENS (3, C7
, C14
, 5)
4714 || reg
->value
== CPENS (3, C7
, C4
, 4))
4715 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_MEMTAG
))
4718 /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
4719 if ((reg
->value
== CPENS (0, C7
, C9
, 0)
4720 || reg
->value
== CPENS (0, C7
, C9
, 1))
4721 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_V8_2
))
4724 /* CFP/DVP/CPP RCTX : Value are from aarch64_sys_regs_sr. */
4725 if (reg
->value
== CPENS (3, C7
, C3
, 0)
4726 && !AARCH64_CPU_HAS_FEATURE (features
, AARCH64_FEATURE_PREDRES
))
4749 #define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
4750 #define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
4752 static enum err_type
4753 verify_ldpsw (const struct aarch64_inst
*inst ATTRIBUTE_UNUSED
,
4754 const aarch64_insn insn
, bfd_vma pc ATTRIBUTE_UNUSED
,
4755 bfd_boolean encoding ATTRIBUTE_UNUSED
,
4756 aarch64_operand_error
*mismatch_detail ATTRIBUTE_UNUSED
,
4757 aarch64_instr_sequence
*insn_sequence ATTRIBUTE_UNUSED
)
4759 int t
= BITS (insn
, 4, 0);
4760 int n
= BITS (insn
, 9, 5);
4761 int t2
= BITS (insn
, 14, 10);
4765 /* Write back enabled. */
4766 if ((t
== n
|| t2
== n
) && n
!= 31)
4780 /* Verifier for vector by element 3 operands functions where the
4781 conditions `if sz:L == 11 then UNDEFINED` holds. */
4783 static enum err_type
4784 verify_elem_sd (const struct aarch64_inst
*inst
, const aarch64_insn insn
,
4785 bfd_vma pc ATTRIBUTE_UNUSED
, bfd_boolean encoding
,
4786 aarch64_operand_error
*mismatch_detail ATTRIBUTE_UNUSED
,
4787 aarch64_instr_sequence
*insn_sequence ATTRIBUTE_UNUSED
)
4789 const aarch64_insn undef_pattern
= 0x3;
4792 assert (inst
->opcode
);
4793 assert (inst
->opcode
->operands
[2] == AARCH64_OPND_Em
);
4794 value
= encoding
? inst
->value
: insn
;
4797 if (undef_pattern
== extract_fields (value
, 0, 2, FLD_sz
, FLD_L
))
4803 /* Initialize an instruction sequence insn_sequence with the instruction INST.
4804 If INST is NULL the given insn_sequence is cleared and the sequence is left
4808 init_insn_sequence (const struct aarch64_inst
*inst
,
4809 aarch64_instr_sequence
*insn_sequence
)
4811 int num_req_entries
= 0;
4812 insn_sequence
->next_insn
= 0;
4813 insn_sequence
->num_insns
= num_req_entries
;
4814 if (insn_sequence
->instr
)
4815 XDELETE (insn_sequence
->instr
);
4816 insn_sequence
->instr
= NULL
;
4820 insn_sequence
->instr
= XNEW (aarch64_inst
);
4821 memcpy (insn_sequence
->instr
, inst
, sizeof (aarch64_inst
));
4824 /* Handle all the cases here. May need to think of something smarter than
4825 a giant if/else chain if this grows. At that time, a lookup table may be
4827 if (inst
&& inst
->opcode
->constraints
& C_SCAN_MOVPRFX
)
4828 num_req_entries
= 1;
4830 if (insn_sequence
->current_insns
)
4831 XDELETEVEC (insn_sequence
->current_insns
);
4832 insn_sequence
->current_insns
= NULL
;
4834 if (num_req_entries
!= 0)
4836 size_t size
= num_req_entries
* sizeof (aarch64_inst
);
4837 insn_sequence
->current_insns
4838 = (aarch64_inst
**) XNEWVEC (aarch64_inst
, num_req_entries
);
4839 memset (insn_sequence
->current_insns
, 0, size
);
4844 /* This function verifies that the instruction INST adheres to its specified
4845 constraints. If it does then ERR_OK is returned, if not then ERR_VFI is
4846 returned and MISMATCH_DETAIL contains the reason why verification failed.
4848 The function is called both during assembly and disassembly. If assembling
4849 then ENCODING will be TRUE, else FALSE. If dissassembling PC will be set
4850 and will contain the PC of the current instruction w.r.t to the section.
4852 If ENCODING and PC=0 then you are at a start of a section. The constraints
4853 are verified against the given state insn_sequence which is updated as it
4854 transitions through the verification. */
4857 verify_constraints (const struct aarch64_inst
*inst
,
4858 const aarch64_insn insn ATTRIBUTE_UNUSED
,
4860 bfd_boolean encoding
,
4861 aarch64_operand_error
*mismatch_detail
,
4862 aarch64_instr_sequence
*insn_sequence
)
4865 assert (inst
->opcode
);
4867 const struct aarch64_opcode
*opcode
= inst
->opcode
;
4868 if (!opcode
->constraints
&& !insn_sequence
->instr
)
4871 assert (insn_sequence
);
4873 enum err_type res
= ERR_OK
;
4875 /* This instruction puts a constraint on the insn_sequence. */
4876 if (opcode
->flags
& F_SCAN
)
4878 if (insn_sequence
->instr
)
4880 mismatch_detail
->kind
= AARCH64_OPDE_SYNTAX_ERROR
;
4881 mismatch_detail
->error
= _("instruction opens new dependency "
4882 "sequence without ending previous one");
4883 mismatch_detail
->index
= -1;
4884 mismatch_detail
->non_fatal
= TRUE
;
4888 init_insn_sequence (inst
, insn_sequence
);
4892 /* Verify constraints on an existing sequence. */
4893 if (insn_sequence
->instr
)
4895 const struct aarch64_opcode
* inst_opcode
= insn_sequence
->instr
->opcode
;
4896 /* If we're decoding and we hit PC=0 with an open sequence then we haven't
4897 closed a previous one that we should have. */
4898 if (!encoding
&& pc
== 0)
4900 mismatch_detail
->kind
= AARCH64_OPDE_SYNTAX_ERROR
;
4901 mismatch_detail
->error
= _("previous `movprfx' sequence not closed");
4902 mismatch_detail
->index
= -1;
4903 mismatch_detail
->non_fatal
= TRUE
;
4905 /* Reset the sequence. */
4906 init_insn_sequence (NULL
, insn_sequence
);
4910 /* Validate C_SCAN_MOVPRFX constraints. Move this to a lookup table. */
4911 if (inst_opcode
->constraints
& C_SCAN_MOVPRFX
)
4913 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4914 instruction for better error messages. */
4915 if (!opcode
->avariant
4916 || !(*opcode
->avariant
&
4917 (AARCH64_FEATURE_SVE
| AARCH64_FEATURE_SVE2
)))
4919 mismatch_detail
->kind
= AARCH64_OPDE_SYNTAX_ERROR
;
4920 mismatch_detail
->error
= _("SVE instruction expected after "
4922 mismatch_detail
->index
= -1;
4923 mismatch_detail
->non_fatal
= TRUE
;
4928 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4929 instruction that is allowed to be used with a MOVPRFX. */
4930 if (!(opcode
->constraints
& C_SCAN_MOVPRFX
))
4932 mismatch_detail
->kind
= AARCH64_OPDE_SYNTAX_ERROR
;
4933 mismatch_detail
->error
= _("SVE `movprfx' compatible instruction "
4935 mismatch_detail
->index
= -1;
4936 mismatch_detail
->non_fatal
= TRUE
;
4941 /* Next check for usage of the predicate register. */
4942 aarch64_opnd_info blk_dest
= insn_sequence
->instr
->operands
[0];
4943 aarch64_opnd_info blk_pred
, inst_pred
;
4944 memset (&blk_pred
, 0, sizeof (aarch64_opnd_info
));
4945 memset (&inst_pred
, 0, sizeof (aarch64_opnd_info
));
4946 bfd_boolean predicated
= FALSE
;
4947 assert (blk_dest
.type
== AARCH64_OPND_SVE_Zd
);
4949 /* Determine if the movprfx instruction used is predicated or not. */
4950 if (insn_sequence
->instr
->operands
[1].type
== AARCH64_OPND_SVE_Pg3
)
4953 blk_pred
= insn_sequence
->instr
->operands
[1];
4956 unsigned char max_elem_size
= 0;
4957 unsigned char current_elem_size
;
4958 int num_op_used
= 0, last_op_usage
= 0;
4959 int i
, inst_pred_idx
= -1;
4960 int num_ops
= aarch64_num_of_operands (opcode
);
4961 for (i
= 0; i
< num_ops
; i
++)
4963 aarch64_opnd_info inst_op
= inst
->operands
[i
];
4964 switch (inst_op
.type
)
4966 case AARCH64_OPND_SVE_Zd
:
4967 case AARCH64_OPND_SVE_Zm_5
:
4968 case AARCH64_OPND_SVE_Zm_16
:
4969 case AARCH64_OPND_SVE_Zn
:
4970 case AARCH64_OPND_SVE_Zt
:
4971 case AARCH64_OPND_SVE_Vm
:
4972 case AARCH64_OPND_SVE_Vn
:
4973 case AARCH64_OPND_Va
:
4974 case AARCH64_OPND_Vn
:
4975 case AARCH64_OPND_Vm
:
4976 case AARCH64_OPND_Sn
:
4977 case AARCH64_OPND_Sm
:
4978 if (inst_op
.reg
.regno
== blk_dest
.reg
.regno
)
4984 = aarch64_get_qualifier_esize (inst_op
.qualifier
);
4985 if (current_elem_size
> max_elem_size
)
4986 max_elem_size
= current_elem_size
;
4988 case AARCH64_OPND_SVE_Pd
:
4989 case AARCH64_OPND_SVE_Pg3
:
4990 case AARCH64_OPND_SVE_Pg4_5
:
4991 case AARCH64_OPND_SVE_Pg4_10
:
4992 case AARCH64_OPND_SVE_Pg4_16
:
4993 case AARCH64_OPND_SVE_Pm
:
4994 case AARCH64_OPND_SVE_Pn
:
4995 case AARCH64_OPND_SVE_Pt
:
4996 inst_pred
= inst_op
;
5004 assert (max_elem_size
!= 0);
5005 aarch64_opnd_info inst_dest
= inst
->operands
[0];
5006 /* Determine the size that should be used to compare against the
5009 = opcode
->constraints
& C_MAX_ELEM
5011 : aarch64_get_qualifier_esize (inst_dest
.qualifier
);
5013 /* If movprfx is predicated do some extra checks. */
5016 /* The instruction must be predicated. */
5017 if (inst_pred_idx
< 0)
5019 mismatch_detail
->kind
= AARCH64_OPDE_SYNTAX_ERROR
;
5020 mismatch_detail
->error
= _("predicated instruction expected "
5022 mismatch_detail
->index
= -1;
5023 mismatch_detail
->non_fatal
= TRUE
;
5028 /* The instruction must have a merging predicate. */
5029 if (inst_pred
.qualifier
!= AARCH64_OPND_QLF_P_M
)
5031 mismatch_detail
->kind
= AARCH64_OPDE_SYNTAX_ERROR
;
5032 mismatch_detail
->error
= _("merging predicate expected due "
5033 "to preceding `movprfx'");
5034 mismatch_detail
->index
= inst_pred_idx
;
5035 mismatch_detail
->non_fatal
= TRUE
;
5040 /* The same register must be used in instruction. */
5041 if (blk_pred
.reg
.regno
!= inst_pred
.reg
.regno
)
5043 mismatch_detail
->kind
= AARCH64_OPDE_SYNTAX_ERROR
;
5044 mismatch_detail
->error
= _("predicate register differs "
5045 "from that in preceding "
5047 mismatch_detail
->index
= inst_pred_idx
;
5048 mismatch_detail
->non_fatal
= TRUE
;
5054 /* Destructive operations by definition must allow one usage of the
5057 = aarch64_is_destructive_by_operands (opcode
) ? 2 : 1;
5059 /* Operand is not used at all. */
5060 if (num_op_used
== 0)
5062 mismatch_detail
->kind
= AARCH64_OPDE_SYNTAX_ERROR
;
5063 mismatch_detail
->error
= _("output register of preceding "
5064 "`movprfx' not used in current "
5066 mismatch_detail
->index
= 0;
5067 mismatch_detail
->non_fatal
= TRUE
;
5072 /* We now know it's used, now determine exactly where it's used. */
5073 if (blk_dest
.reg
.regno
!= inst_dest
.reg
.regno
)
5075 mismatch_detail
->kind
= AARCH64_OPDE_SYNTAX_ERROR
;
5076 mismatch_detail
->error
= _("output register of preceding "
5077 "`movprfx' expected as output");
5078 mismatch_detail
->index
= 0;
5079 mismatch_detail
->non_fatal
= TRUE
;
5084 /* Operand used more than allowed for the specific opcode type. */
5085 if (num_op_used
> allowed_usage
)
5087 mismatch_detail
->kind
= AARCH64_OPDE_SYNTAX_ERROR
;
5088 mismatch_detail
->error
= _("output register of preceding "
5089 "`movprfx' used as input");
5090 mismatch_detail
->index
= last_op_usage
;
5091 mismatch_detail
->non_fatal
= TRUE
;
5096 /* Now the only thing left is the qualifiers checks. The register
5097 must have the same maximum element size. */
5098 if (inst_dest
.qualifier
5099 && blk_dest
.qualifier
5100 && current_elem_size
5101 != aarch64_get_qualifier_esize (blk_dest
.qualifier
))
5103 mismatch_detail
->kind
= AARCH64_OPDE_SYNTAX_ERROR
;
5104 mismatch_detail
->error
= _("register size not compatible with "
5105 "previous `movprfx'");
5106 mismatch_detail
->index
= 0;
5107 mismatch_detail
->non_fatal
= TRUE
;
5114 /* Add the new instruction to the sequence. */
5115 memcpy (insn_sequence
->current_insns
+ insn_sequence
->next_insn
++,
5116 inst
, sizeof (aarch64_inst
));
5118 /* Check if sequence is now full. */
5119 if (insn_sequence
->next_insn
>= insn_sequence
->num_insns
)
5121 /* Sequence is full, but we don't have anything special to do for now,
5122 so clear and reset it. */
5123 init_insn_sequence (NULL
, insn_sequence
);
5131 /* Return true if VALUE cannot be moved into an SVE register using DUP
5132 (with any element size, not just ESIZE) and if using DUPM would
5133 therefore be OK. ESIZE is the number of bytes in the immediate. */
5136 aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue
, int esize
)
5138 int64_t svalue
= uvalue
;
5139 uint64_t upper
= (uint64_t) -1 << (esize
* 4) << (esize
* 4);
5141 if ((uvalue
& ~upper
) != uvalue
&& (uvalue
| upper
) != uvalue
)
5143 if (esize
<= 4 || (uint32_t) uvalue
== (uint32_t) (uvalue
>> 32))
5145 svalue
= (int32_t) uvalue
;
5146 if (esize
<= 2 || (uint16_t) uvalue
== (uint16_t) (uvalue
>> 16))
5148 svalue
= (int16_t) uvalue
;
5149 if (esize
== 1 || (uint8_t) uvalue
== (uint8_t) (uvalue
>> 8))
5153 if ((svalue
& 0xff) == 0)
5155 return svalue
< -128 || svalue
>= 128;
5158 /* Include the opcode description table as well as the operand description
5160 #define VERIFIER(x) verify_##x
5161 #include "aarch64-tbl.h"