opcodes/aarch64-opc.h

   1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
   2    Copyright (C) 2012-2019 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef OPCODES_AARCH64_OPC_H
  22 #define OPCODES_AARCH64_OPC_H
  23
  24 #include <string.h>
  25 #include "opcode/aarch64.h"
  26
  27 /* Instruction fields.
  28    Keep synced with fields.  */
  29 enum aarch64_field_kind
  30 {
  31   FLD_NIL,
  32   FLD_cond2,
  33   FLD_nzcv,
  34   FLD_defgh,
  35   FLD_abc,
  36   FLD_imm19,
  37   FLD_immhi,
  38   FLD_immlo,
  39   FLD_size,
  40   FLD_vldst_size,
  41   FLD_op,
  42   FLD_Q,
  43   FLD_Rt,
  44   FLD_Rd,
  45   FLD_Rn,
  46   FLD_Rt2,
  47   FLD_Ra,
  48   FLD_op2,
  49   FLD_CRm,
  50   FLD_CRn,
  51   FLD_op1,
  52   FLD_op0,
  53   FLD_imm3,
  54   FLD_cond,
  55   FLD_opcode,
  56   FLD_cmode,
  57   FLD_asisdlso_opcode,
  58   FLD_len,
  59   FLD_Rm,
  60   FLD_Rs,
  61   FLD_option,
  62   FLD_S,
  63   FLD_hw,
  64   FLD_opc,
  65   FLD_opc1,
  66   FLD_shift,
  67   FLD_type,
  68   FLD_ldst_size,
  69   FLD_imm6,
  70   FLD_imm6_2,
  71   FLD_imm4,
  72   FLD_imm4_2,
  73   FLD_imm4_3,
  74   FLD_imm5,
  75   FLD_imm7,
  76   FLD_imm8,
  77   FLD_imm9,
  78   FLD_imm12,
  79   FLD_imm14,
  80   FLD_imm16,
  81   FLD_imm26,
  82   FLD_imms,
  83   FLD_immr,
  84   FLD_immb,
  85   FLD_immh,
  86   FLD_S_imm10,
  87   FLD_N,
  88   FLD_index,
  89   FLD_index2,
  90   FLD_sf,
  91   FLD_lse_sz,
  92   FLD_H,
  93   FLD_L,
  94   FLD_M,
  95   FLD_b5,
  96   FLD_b40,
  97   FLD_scale,
  98   FLD_SVE_M_4,
  99   FLD_SVE_M_14,
 100   FLD_SVE_M_16,
 101   FLD_SVE_N,
 102   FLD_SVE_Pd,
 103   FLD_SVE_Pg3,
 104   FLD_SVE_Pg4_5,
 105   FLD_SVE_Pg4_10,
 106   FLD_SVE_Pg4_16,
 107   FLD_SVE_Pm,
 108   FLD_SVE_Pn,
 109   FLD_SVE_Pt,
 110   FLD_SVE_Rm,
 111   FLD_SVE_Rn,
 112   FLD_SVE_Vd,
 113   FLD_SVE_Vm,
 114   FLD_SVE_Vn,
 115   FLD_SVE_Za_5,
 116   FLD_SVE_Za_16,
 117   FLD_SVE_Zd,
 118   FLD_SVE_Zm_5,
 119   FLD_SVE_Zm_16,
 120   FLD_SVE_Zn,
 121   FLD_SVE_Zt,
 122   FLD_SVE_i1,
 123   FLD_SVE_i3h,
 124   FLD_SVE_i3l,
 125   FLD_SVE_i3h2,
 126   FLD_SVE_imm3,
 127   FLD_SVE_imm4,
 128   FLD_SVE_imm5,
 129   FLD_SVE_imm5b,
 130   FLD_SVE_imm6,
 131   FLD_SVE_imm7,
 132   FLD_SVE_imm8,
 133   FLD_SVE_imm9,
 134   FLD_SVE_immr,
 135   FLD_SVE_imms,
 136   FLD_SVE_msz,
 137   FLD_SVE_pattern,
 138   FLD_SVE_prfop,
 139   FLD_SVE_rot1,
 140   FLD_SVE_rot2,
 141   FLD_SVE_rot3,
 142   FLD_SVE_sz,
 143   FLD_SVE_size,
 144   FLD_SVE_tsz,
 145   FLD_SVE_tszh,
 146   FLD_SVE_tszl_8,
 147   FLD_SVE_tszl_19,
 148   FLD_SVE_xs_14,
 149   FLD_SVE_xs_22,
 150   FLD_rotate1,
 151   FLD_rotate2,
 152   FLD_rotate3,
 153   FLD_SM3_imm2,
 154   FLD_sz
 155 };
 156
 157 /* Field description.  */
 158 struct aarch64_field
 159 {
 160   int lsb;
 161   int width;
 162 };
 163
 164 typedef struct aarch64_field aarch64_field;
 165
 166 extern const aarch64_field fields[];
 167 \f
 168 /* Operand description.  */
 169
 170 struct aarch64_operand
 171 {
 172   enum aarch64_operand_class op_class;
 173
 174   /* Name of the operand code; used mainly for the purpose of internal
 175      debugging.  */
 176   const char *name;
 177
 178   unsigned int flags;
 179
 180   /* The associated instruction bit-fields; no operand has more than 4
 181      bit-fields */
 182   enum aarch64_field_kind fields[4];
 183
 184   /* Brief description */
 185   const char *desc;
 186 };
 187
 188 typedef struct aarch64_operand aarch64_operand;
 189
 190 extern const aarch64_operand aarch64_operands[];
 191
 192 enum err_type
 193 verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
 194                     bfd_boolean, aarch64_operand_error *, aarch64_instr_sequence*);
 195
 196 /* Operand flags.  */
 197
 198 #define OPD_F_HAS_INSERTER      0x00000001
 199 #define OPD_F_HAS_EXTRACTOR     0x00000002
 200 #define OPD_F_SEXT              0x00000004      /* Require sign-extension.  */
 201 #define OPD_F_SHIFT_BY_2        0x00000008      /* Need to left shift the field
 202                                                    value by 2 to get the value
 203                                                    of an immediate operand.  */
 204 #define OPD_F_MAYBE_SP          0x00000010      /* May potentially be SP.  */
 205 #define OPD_F_OD_MASK           0x000000e0      /* Operand-dependent data.  */
 206 #define OPD_F_OD_LSB            5
 207 #define OPD_F_NO_ZR             0x00000100      /* ZR index not allowed.  */
 208 #define OPD_F_SHIFT_BY_4        0x00000200      /* Need to left shift the field
 209                                                    value by 4 to get the value
 210                                                    of an immediate operand.  */
 211
 212
 213 /* Register flags.  */
 214
 215 #undef F_DEPRECATED
 216 #define F_DEPRECATED    (1 << 0)  /* Deprecated system register.  */
 217
 218 #undef F_ARCHEXT
 219 #define F_ARCHEXT       (1 << 1)  /* Architecture dependent system register.  */
 220
 221 #undef F_HASXT
 222 #define F_HASXT         (1 << 2)  /* System instruction register <Xt>
 223                                      operand.  */
 224
 225 #undef F_REG_READ
 226 #define F_REG_READ      (1 << 3)  /* Register can only be used to read values
 227                                      out of.  */
 228
 229 #undef F_REG_WRITE
 230 #define F_REG_WRITE     (1 << 4)  /* Register can only be written to but not
 231                                      read from.  */
 232
 233 /* HINT operand flags.  */
 234 #define HINT_OPD_F_NOPRINT      (1 << 0)  /* Should not be printed.  */
 235
 236 /* Encode 7-bit HINT #imm in the lower 8 bits.  Use higher bits for flags.  */
 237 #define HINT_ENCODE(flag, val) ((flag << 8) | val)
 238 #define HINT_FLAG(val) (val >> 8)
 239 #define HINT_VAL(val) (val & 0xff)
 240
 241 static inline bfd_boolean
 242 operand_has_inserter (const aarch64_operand *operand)
 243 {
 244   return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
 245 }
 246
 247 static inline bfd_boolean
 248 operand_has_extractor (const aarch64_operand *operand)
 249 {
 250   return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
 251 }
 252
 253 static inline bfd_boolean
 254 operand_need_sign_extension (const aarch64_operand *operand)
 255 {
 256   return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE;
 257 }
 258
 259 static inline bfd_boolean
 260 operand_need_shift_by_two (const aarch64_operand *operand)
 261 {
 262   return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
 263 }
 264
 265 static inline bfd_boolean
 266 operand_need_shift_by_four (const aarch64_operand *operand)
 267 {
 268   return (operand->flags & OPD_F_SHIFT_BY_4) ? TRUE : FALSE;
 269 }
 270
 271 static inline bfd_boolean
 272 operand_maybe_stack_pointer (const aarch64_operand *operand)
 273 {
 274   return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
 275 }
 276
 277 /* Return the value of the operand-specific data field (OPD_F_OD_MASK).  */
 278 static inline unsigned int
 279 get_operand_specific_data (const aarch64_operand *operand)
 280 {
 281   return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
 282 }
 283
 284 /* Return the width of field number N of operand *OPERAND.  */
 285 static inline unsigned
 286 get_operand_field_width (const aarch64_operand *operand, unsigned n)
 287 {
 288   assert (operand->fields[n] != FLD_NIL);
 289   return fields[operand->fields[n]].width;
 290 }
 291
 292 /* Return the total width of the operand *OPERAND.  */
 293 static inline unsigned
 294 get_operand_fields_width (const aarch64_operand *operand)
 295 {
 296   int i = 0;
 297   unsigned width = 0;
 298   while (operand->fields[i] != FLD_NIL)
 299     width += fields[operand->fields[i++]].width;
 300   assert (width > 0 && width < 32);
 301   return width;
 302 }
 303
 304 static inline const aarch64_operand *
 305 get_operand_from_code (enum aarch64_opnd code)
 306 {
 307   return aarch64_operands + code;
 308 }
 309 \f
 310 /* Operand qualifier and operand constraint checking.  */
 311
 312 int aarch64_match_operands_constraint (aarch64_inst *,
 313                                        aarch64_operand_error *);
 314
 315 /* Operand qualifier related functions.  */
 316 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
 317 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
 318 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
 319 int aarch64_find_best_match (const aarch64_inst *,
 320                              const aarch64_opnd_qualifier_seq_t *,
 321                              int, aarch64_opnd_qualifier_t *);
 322
 323 static inline void
 324 reset_operand_qualifier (aarch64_inst *inst, int idx)
 325 {
 326   assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
 327   inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
 328 }
 329 \f
 330 /* Inline functions operating on instruction bit-field(s).  */
 331
 332 /* Generate a mask that has WIDTH number of consecutive 1s.  */
 333
 334 static inline aarch64_insn
 335 gen_mask (int width)
 336 {
 337   return ((aarch64_insn) 1 << width) - 1;
 338 }
 339
 340 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0.  */
 341 static inline int
 342 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
 343 {
 344   const aarch64_field *field = &fields[kind];
 345   if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
 346     return 0;
 347   ret->lsb = field->lsb + lsb_rel;
 348   ret->width = width;
 349   return 1;
 350 }
 351
 352 /* Insert VALUE into FIELD of CODE.  MASK can be zero or the base mask
 353    of the opcode.  */
 354
 355 static inline void
 356 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
 357                 aarch64_insn value, aarch64_insn mask)
 358 {
 359   assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
 360           && field->lsb + field->width <= 32);
 361   value &= gen_mask (field->width);
 362   value <<= field->lsb;
 363   /* In some opcodes, field can be part of the base opcode, e.g. the size
 364      field in FADD.  The following helps avoid corrupt the base opcode.  */
 365   value &= ~mask;
 366   *code |= value;
 367 }
 368
 369 /* Extract FIELD of CODE and return the value.  MASK can be zero or the base
 370    mask of the opcode.  */
 371
 372 static inline aarch64_insn
 373 extract_field_2 (const aarch64_field *field, aarch64_insn code,
 374                  aarch64_insn mask)
 375 {
 376   aarch64_insn value;
 377   /* Clear any bit that is a part of the base opcode.  */
 378   code &= ~mask;
 379   value = (code >> field->lsb) & gen_mask (field->width);
 380   return value;
 381 }
 382
 383 /* Insert VALUE into field KIND of CODE.  MASK can be zero or the base mask
 384    of the opcode.  */
 385
 386 static inline void
 387 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
 388               aarch64_insn value, aarch64_insn mask)
 389 {
 390   insert_field_2 (&fields[kind], code, value, mask);
 391 }
 392
 393 /* Extract field KIND of CODE and return the value.  MASK can be zero or the
 394    base mask of the opcode.  */
 395
 396 static inline aarch64_insn
 397 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
 398                aarch64_insn mask)
 399 {
 400   return extract_field_2 (&fields[kind], code, mask);
 401 }
 402
 403 extern aarch64_insn
 404 extract_fields (aarch64_insn code, aarch64_insn mask, ...);
 405 \f
 406 /* Inline functions selecting operand to do the encoding/decoding for a
 407    certain instruction bit-field.  */
 408
 409 /* Select the operand to do the encoding/decoding of the 'sf' field.
 410    The heuristic-based rule is that the result operand is respected more.  */
 411
 412 static inline int
 413 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
 414 {
 415   int idx = -1;
 416   if (aarch64_get_operand_class (opcode->operands[0])
 417       == AARCH64_OPND_CLASS_INT_REG)
 418     /* normal case.  */
 419     idx = 0;
 420   else if (aarch64_get_operand_class (opcode->operands[1])
 421            == AARCH64_OPND_CLASS_INT_REG)
 422     /* e.g. float2fix.  */
 423     idx = 1;
 424   else
 425     { assert (0); abort (); }
 426   return idx;
 427 }
 428
 429 /* Select the operand to do the encoding/decoding of the 'type' field in
 430    the floating-point instructions.
 431    The heuristic-based rule is that the source operand is respected more.  */
 432
 433 static inline int
 434 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
 435 {
 436   int idx;
 437   if (aarch64_get_operand_class (opcode->operands[1])
 438       == AARCH64_OPND_CLASS_FP_REG)
 439     /* normal case.  */
 440     idx = 1;
 441   else if (aarch64_get_operand_class (opcode->operands[0])
 442            == AARCH64_OPND_CLASS_FP_REG)
 443     /* e.g. float2fix.  */
 444     idx = 0;
 445   else
 446     { assert (0); abort (); }
 447   return idx;
 448 }
 449
 450 /* Select the operand to do the encoding/decoding of the 'size' field in
 451    the AdvSIMD scalar instructions.
 452    The heuristic-based rule is that the destination operand is respected
 453    more.  */
 454
 455 static inline int
 456 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
 457 {
 458   int src_size = 0, dst_size = 0;
 459   if (aarch64_get_operand_class (opcode->operands[0])
 460       == AARCH64_OPND_CLASS_SISD_REG)
 461     dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
 462   if (aarch64_get_operand_class (opcode->operands[1])
 463       == AARCH64_OPND_CLASS_SISD_REG)
 464     src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
 465   if (src_size == dst_size && src_size == 0)
 466     { assert (0); abort (); }
 467   /* When the result is not a sisd register or it is a long operantion.  */
 468   if (dst_size == 0 || dst_size == src_size << 1)
 469     return 1;
 470   else
 471     return 0;
 472 }
 473
 474 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
 475    the AdvSIMD instructions.  */
 476
 477 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
 478 \f
 479 /* Miscellaneous.  */
 480
 481 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
 482 enum aarch64_modifier_kind
 483 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
 484
 485
 486 bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
 487 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
 488 int aarch64_shrink_expanded_imm8 (uint64_t);
 489
 490 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST].  */
 491 static inline void
 492 copy_operand_info (aarch64_inst *inst, int dst, int src)
 493 {
 494   assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
 495           && src < AARCH64_MAX_OPND_NUM);
 496   memcpy (&inst->operands[dst], &inst->operands[src],
 497           sizeof (aarch64_opnd_info));
 498   inst->operands[dst].idx = dst;
 499 }
 500
 501 /* A primitive log caculator.  */
 502
 503 static inline unsigned int
 504 get_logsz (unsigned int size)
 505 {
 506   const unsigned char ls[16] =
 507     {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
 508   if (size > 16)
 509     {
 510       assert (0);
 511       return -1;
 512     }
 513   assert (ls[size - 1] != (unsigned char)-1);
 514   return ls[size - 1];
 515 }
 516
 517 #endif /* OPCODES_AARCH64_OPC_H */