1 /* Instruction printing code for the ARC.
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
27 #include "opcode/arc.h"
32 /* Globals variables. */
34 static const char * const regnames
[64] =
36 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
37 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
38 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
39 "r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink",
41 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
42 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
43 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
44 "r56", "r57", "ACCL", "ACCH", "lp_count", "rezerved", "LIMM", "pcl"
50 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
52 # define pr_debug(fmt, args...)
55 #define ARRANGE_ENDIAN(info, buf) \
56 (info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32 (bfd_getl32 (buf)) \
59 #define BITS(word,s,e) (((word) << (sizeof (word) * 8 - 1 - e)) >> \
60 (s + (sizeof (word) * 8 - 1 - e)))
61 #define OPCODE(word) (BITS ((word), 27, 31))
62 #define FIELDA(word) (BITS ((word), 21, 26))
63 #define FIELDB(word) (BITS ((word), 15, 20))
64 #define FIELDC(word) (BITS ((word), 9, 14))
66 #define OPCODE_AC(word) (BITS ((word), 11, 15))
68 /* Functions implementation. */
71 bfd_getm32 (unsigned int data
)
75 value
= ((data
& 0xff00) | (data
& 0xff)) << 16;
76 value
|= ((data
& 0xff0000) | (data
& 0xff000000)) >> 16;
81 special_flag_p (const char *opname
,
84 const struct arc_flag_special
*flg_spec
;
86 unsigned i
, j
, flgidx
;
88 for (i
= 0; i
< arc_num_flag_special
; i
++)
90 flg_spec
= &arc_flag_special_cases
[i
];
91 len
= strlen (flg_spec
->name
);
93 if (strncmp (opname
, flg_spec
->name
, len
) != 0)
96 /* Found potential special case instruction. */
99 flgidx
= flg_spec
->flags
[j
];
101 break; /* End of the array. */
103 if (strcmp (flgname
, arc_flag_operands
[flgidx
].name
) == 0)
110 /* Disassemble ARC instructions. */
113 print_insn_arc (bfd_vma memaddr
,
114 struct disassemble_info
*info
)
117 unsigned int lowbyte
, highbyte
;
121 unsigned insn
[2] = { 0, 0 };
123 const unsigned char *opidx
;
124 const unsigned char *flgidx
;
125 const struct arc_opcode
*opcode
;
126 const char *instrName
;
128 bfd_boolean need_comma
;
129 bfd_boolean open_braket
;
132 lowbyte
= ((info
->endian
== BFD_ENDIAN_LITTLE
) ? 1 : 0);
133 highbyte
= ((info
->endian
== BFD_ENDIAN_LITTLE
) ? 0 : 1);
137 case bfd_mach_arc_arc700
:
138 isa_mask
= ARC_OPCODE_ARC700
;
141 case bfd_mach_arc_arc600
:
142 isa_mask
= ARC_OPCODE_ARC600
;
145 case bfd_mach_arc_arcv2
:
147 isa_mask
= ARC_OPCODE_ARCv2HS
| ARC_OPCODE_ARCv2EM
;
151 /* Read the insn into a host word. */
152 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
155 (*info
->memory_error_func
) (status
, memaddr
, info
);
160 && !(info
->section
->flags
& SEC_CODE
))
162 /* Sort of data section, just print a 32 bit number. */
164 status
= (*info
->read_memory_func
) (memaddr
+ 2, &buffer
[2], 2, info
);
167 (*info
->memory_error_func
) (status
, memaddr
+ 2, info
);
170 insn
[0] = ARRANGE_ENDIAN (info
, buffer
);
171 (*info
->fprintf_func
) (info
->stream
, ".long %#08x", insn
[0]);
175 if ((((buffer
[lowbyte
] & 0xf8) > 0x38)
176 && ((buffer
[lowbyte
] & 0xf8) != 0x48))
177 || ((info
->mach
== bfd_mach_arc_arcv2
)
178 && ((buffer
[lowbyte
] & 0xF8) == 0x48)) /* FIXME! ugly. */
181 /* This is a short instruction. */
183 insn
[0] = (buffer
[lowbyte
] << 8) | buffer
[highbyte
];
189 /* This is a long instruction: Read the remaning 2 bytes. */
190 status
= (*info
->read_memory_func
) (memaddr
+ 2, &buffer
[2], 2, info
);
193 (*info
->memory_error_func
) (status
, memaddr
+ 2, info
);
196 insn
[0] = ARRANGE_ENDIAN (info
, buffer
);
199 /* This variable may be set by the instruction decoder. It suggests
200 the number of bytes objdump should display on a single line. If
201 the instruction decoder sets this, it should always set it to
202 the same value in order to get reasonable looking output. */
203 info
->bytes_per_line
= 8;
205 /* The next two variables control the way objdump displays the raw data.
206 For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the
207 output will look like this:
208 00: 00000000 00000000
209 with the chunks displayed according to "display_endian". */
210 info
->bytes_per_chunk
= 2;
211 info
->display_endian
= info
->endian
;
213 /* Set some defaults for the insn info. */
214 info
->insn_info_valid
= 1;
215 info
->branch_delay_insns
= 0;
217 info
->insn_type
= dis_nonbranch
;
221 /* FIXME to be moved in dissasemble_init_for_target. */
222 info
->disassembler_needs_relocs
= TRUE
;
224 /* Find the first match in the opcode table. */
225 for (i
= 0; i
< arc_num_opcodes
; i
++)
227 bfd_boolean invalid
= FALSE
;
229 opcode
= &arc_opcodes
[i
];
231 if (ARC_SHORT (opcode
->mask
) && (insnLen
== 2))
233 if (OPCODE_AC (opcode
->opcode
) != OPCODE_AC (insn
[0]))
236 else if (!ARC_SHORT (opcode
->mask
) && (insnLen
== 4))
238 if (OPCODE (opcode
->opcode
) != OPCODE (insn
[0]))
244 if ((insn
[0] ^ opcode
->opcode
) & opcode
->mask
)
247 if (!(opcode
->cpu
& isa_mask
))
250 /* Possible candidate, check the operands. */
251 for (opidx
= opcode
->operands
; *opidx
; opidx
++)
254 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
256 if (operand
->flags
& ARC_OPERAND_FAKE
)
259 if (operand
->extract
)
260 value
= (*operand
->extract
) (insn
[0], &invalid
);
262 value
= (insn
[0] >> operand
->shift
) & ((1 << operand
->bits
) - 1);
264 /* Check for LIMM indicator. If it is there, then make sure
265 we pick the right format. */
266 if (operand
->flags
& ARC_OPERAND_IR
267 && !(operand
->flags
& ARC_OPERAND_LIMM
))
269 if ((value
== 0x3E && insnLen
== 4)
270 || (value
== 0x1E && insnLen
== 2))
278 /* Check the flags. */
279 for (flgidx
= opcode
->flags
; *flgidx
; flgidx
++)
281 /* Get a valid flag class. */
282 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
283 const unsigned *flgopridx
;
284 int foundA
= 0, foundB
= 0;
286 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
288 const struct arc_flag_operand
*flg_operand
= &arc_flag_operands
[*flgopridx
];
291 value
= (insn
[0] >> flg_operand
->shift
) & ((1 << flg_operand
->bits
) - 1);
292 if (value
== flg_operand
->code
)
297 if (!foundA
&& foundB
)
307 /* The instruction is valid. */
311 /* No instruction found. Try the extenssions. */
312 instrName
= arcExtMap_instName (OPCODE (insn
[0]), insn
[0], &flags
);
315 opcode
= &arc_opcodes
[0];
316 (*info
->fprintf_func
) (info
->stream
, "%s", instrName
);
321 (*info
->fprintf_func
) (info
->stream
, ".long %#04x", insn
[0]);
323 (*info
->fprintf_func
) (info
->stream
, ".long %#08x", insn
[0]);
325 info
->insn_type
= dis_noninsn
;
329 /* Print the mnemonic. */
330 (*info
->fprintf_func
) (info
->stream
, "%s", opcode
->name
);
332 /* Preselect the insn class. */
333 switch (opcode
->class)
337 if (!strncmp (opcode
->name
, "bl", 2)
338 || !strncmp (opcode
->name
, "jl", 2))
339 info
->insn_type
= dis_jsr
;
341 info
->insn_type
= dis_branch
;
344 info
->insn_type
= dis_dref
; /* FIXME! DB indicates mov as memory! */
347 info
->insn_type
= dis_nonbranch
;
351 pr_debug ("%s: 0x%08x\n", opcode
->name
, opcode
->opcode
);
354 /* Now extract and print the flags. */
355 for (flgidx
= opcode
->flags
; *flgidx
; flgidx
++)
357 /* Get a valid flag class. */
358 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
359 const unsigned *flgopridx
;
361 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
363 const struct arc_flag_operand
*flg_operand
= &arc_flag_operands
[*flgopridx
];
366 if (!flg_operand
->favail
)
369 value
= (insn
[0] >> flg_operand
->shift
) & ((1 << flg_operand
->bits
) - 1);
370 if (value
== flg_operand
->code
)
372 /* FIXME!: print correctly nt/t flag. */
373 if (!special_flag_p (opcode
->name
, flg_operand
->name
))
374 (*info
->fprintf_func
) (info
->stream
, ".");
375 else if (info
->insn_type
== dis_dref
)
377 switch (flg_operand
->name
[0])
391 (*info
->fprintf_func
) (info
->stream
, "%s", flg_operand
->name
);
394 if (flg_operand
->name
[0] == 'd'
395 && flg_operand
->name
[1] == 0)
396 info
->branch_delay_insns
= 1;
400 if (opcode
->operands
[0] != 0)
401 (*info
->fprintf_func
) (info
->stream
, "\t");
406 /* Now extract and print the operands. */
407 for (opidx
= opcode
->operands
; *opidx
; opidx
++)
409 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
412 if (open_braket
&& (operand
->flags
& ARC_OPERAND_BRAKET
))
414 (*info
->fprintf_func
) (info
->stream
, "]");
419 /* Only take input from real operands. */
420 if ((operand
->flags
& ARC_OPERAND_FAKE
)
421 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
424 if (operand
->extract
)
425 value
= (*operand
->extract
) (insn
[0], (int *) NULL
);
428 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
430 value
= (insn
[0] >> operand
->shift
)
431 & ((1 << (operand
->bits
- 2)) - 1);
436 value
= (insn
[0] >> operand
->shift
) & ((1 << operand
->bits
) - 1);
438 if (operand
->flags
& ARC_OPERAND_SIGNED
)
440 int signbit
= 1 << (operand
->bits
- 1);
441 value
= (value
^ signbit
) - signbit
;
445 if (operand
->flags
& ARC_OPERAND_IGNORE
446 && (operand
->flags
& ARC_OPERAND_IR
451 (*info
->fprintf_func
) (info
->stream
, ",");
453 if (!open_braket
&& (operand
->flags
& ARC_OPERAND_BRAKET
))
455 (*info
->fprintf_func
) (info
->stream
, "[");
461 /* Read the limm operand, if required. */
462 if (operand
->flags
& ARC_OPERAND_LIMM
463 && !(operand
->flags
& ARC_OPERAND_DUPLICATE
))
465 status
= (*info
->read_memory_func
) (memaddr
+ insnLen
, buffer
,
469 (*info
->memory_error_func
) (status
, memaddr
+ insnLen
, info
);
472 insn
[1] = ARRANGE_ENDIAN (info
, buffer
);
475 /* Print the operand as directed by the flags. */
476 if (operand
->flags
& ARC_OPERAND_IR
)
478 assert (value
>=0 && value
< 64);
479 (*info
->fprintf_func
) (info
->stream
, "%s", regnames
[value
]);
480 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
481 (*info
->fprintf_func
) (info
->stream
, "%s", regnames
[value
+1]);
483 else if (operand
->flags
& ARC_OPERAND_LIMM
)
485 (*info
->fprintf_func
) (info
->stream
, "%#x", insn
[1]);
486 if (info
->insn_type
== dis_branch
487 || info
->insn_type
== dis_jsr
)
488 info
->target
= (bfd_vma
) insn
[1];
490 else if (operand
->flags
& ARC_OPERAND_PCREL
)
493 if (info
->flags
& INSN_HAS_RELOC
)
495 (*info
->print_address_func
) ((memaddr
& ~3) + value
, info
);
497 info
->target
= (bfd_vma
) (memaddr
& ~3) + value
;
499 else if (operand
->flags
& ARC_OPERAND_SIGNED
)
500 (*info
->fprintf_func
) (info
->stream
, "%d", value
);
502 if (operand
->flags
& ARC_OPERAND_TRUNCATE
503 && !(operand
->flags
& ARC_OPERAND_ALIGNED32
)
504 && !(operand
->flags
& ARC_OPERAND_ALIGNED16
)
505 && value
> 0 && value
<= 14)
506 (*info
->fprintf_func
) (info
->stream
, "r13-%s",
507 regnames
[13 + value
- 1]);
509 (*info
->fprintf_func
) (info
->stream
, "%#x", value
);
513 /* Adjust insn len. */
514 if (operand
->flags
& ARC_OPERAND_LIMM
515 && !(operand
->flags
& ARC_OPERAND_DUPLICATE
))
524 arc_get_disassembler (bfd
*abfd
)
526 /* Read the extenssion insns and registers, if any. */
527 build_ARC_extmap (abfd
);
530 return print_insn_arc
;
533 /* Disassemble ARC instructions. Used by debugger. */
536 arcAnalyzeInstr (bfd_vma memaddr
,
537 struct disassemble_info
*info
)
539 struct arcDisState ret
;
540 memset (&ret
, 0, sizeof (struct arcDisState
));
542 ret
.instructionLen
= print_insn_arc (memaddr
, info
);
545 ret
.words
[0] = insn
[0];
546 ret
.words
[1] = insn
[1];
548 ret
.coreRegName
= _coreRegName
;
549 ret
.auxRegName
= _auxRegName
;
550 ret
.condCodeName
= _condCodeName
;
551 ret
.instName
= _instName
;
558 eval: (c-set-style "gnu")