1 /* Instruction printing code for the ARC.
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
27 #include "opcode/arc.h"
32 #include "libiberty.h"
35 /* Structure used to iterate over, and extract the values for, operands of
38 struct arc_operand_iterator
40 /* The complete instruction value to extract operands from. */
41 unsigned long long insn
;
43 /* The LIMM if this is being tracked separately. This field is only
44 valid if we find the LIMM operand in the operand list. */
47 /* The opcode this iterator is operating on. */
48 const struct arc_opcode
*opcode
;
50 /* The index into the opcodes operand index list. */
51 const unsigned char *opidx
;
54 /* A private data used by ARC decoder. */
55 struct arc_disassemble_info
57 /* The current disassembled arc opcode. */
58 const struct arc_opcode
*opcode
;
60 /* Instruction length w/o limm field. */
63 /* TRUE if we have limm. */
66 /* LIMM value, if exists. */
69 /* Condition code, if exists. */
70 unsigned condition_code
;
73 unsigned writeback_mode
;
75 /* Number of operands. */
76 unsigned operands_count
;
78 struct arc_insn_operand operands
[MAX_INSN_ARGS
];
81 /* Globals variables. */
83 static const char * const regnames
[64] =
85 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
86 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
87 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
88 "r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink",
90 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
91 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
92 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
93 "r56", "r57", "ACCL", "ACCH", "lp_count", "rezerved", "LIMM", "pcl"
96 static const char * const addrtypenames
[ARC_NUM_ADDRTYPES
] =
98 "bd", "jid", "lbd", "mbd", "sd", "sm", "xa", "xd",
99 "cd", "cbd", "cjid", "clbd", "cm", "csd", "cxa", "cxd"
102 static int addrtypenames_max
= ARC_NUM_ADDRTYPES
- 1;
104 static const char * const addrtypeunknown
= "unknown";
106 /* This structure keeps track which instruction class(es)
107 should be ignored durring disassembling. */
109 typedef struct skipclass
111 insn_class_t insn_class
;
112 insn_subclass_t subclass
;
113 struct skipclass
*nxt
;
114 } skipclass_t
, *linkclass
;
116 /* Intial classes of instructions to be consider first when
118 static linkclass decodelist
= NULL
;
120 /* ISA mask value enforced via disassembler info options. ARC_OPCODE_NONE
121 value means that no CPU is enforced. */
123 static unsigned enforced_isa_mask
= ARC_OPCODE_NONE
;
125 /* True if we want to print using only hex numbers. */
126 static bfd_boolean print_hex
= FALSE
;
128 /* Macros section. */
131 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
133 # define pr_debug(fmt, args...)
136 #define ARRANGE_ENDIAN(info, buf) \
137 (info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32 (bfd_getl32 (buf)) \
140 #define BITS(word,s,e) (((word) << (sizeof (word) * 8 - 1 - e)) >> \
141 (s + (sizeof (word) * 8 - 1 - e)))
142 #define OPCODE_32BIT_INSN(word) (BITS ((word), 27, 31))
144 /* Functions implementation. */
146 /* Initialize private data. */
148 init_arc_disasm_info (struct disassemble_info
*info
)
150 struct arc_disassemble_info
*arc_infop
151 = calloc (sizeof (*arc_infop
), 1);
153 if (arc_infop
== NULL
)
156 info
->private_data
= arc_infop
;
160 /* Add a new element to the decode list. */
163 add_to_decodelist (insn_class_t insn_class
,
164 insn_subclass_t subclass
)
166 linkclass t
= (linkclass
) xmalloc (sizeof (skipclass_t
));
168 t
->insn_class
= insn_class
;
169 t
->subclass
= subclass
;
174 /* Return TRUE if we need to skip the opcode from being
178 skip_this_opcode (const struct arc_opcode
*opcode
)
180 linkclass t
= decodelist
;
182 /* Check opcode for major 0x06, return if it is not in. */
183 if (arc_opcode_len (opcode
) == 4
184 && (OPCODE_32BIT_INSN (opcode
->opcode
) != 0x06
185 /* Can be an APEX extensions. */
186 && OPCODE_32BIT_INSN (opcode
->opcode
) != 0x07))
189 /* or not a known truble class. */
190 switch (opcode
->insn_class
)
203 if ((t
->insn_class
== opcode
->insn_class
)
204 && (t
->subclass
== opcode
->subclass
))
213 bfd_getm32 (unsigned int data
)
217 value
= ((data
& 0xff00) | (data
& 0xff)) << 16;
218 value
|= ((data
& 0xff0000) | (data
& 0xff000000)) >> 16;
223 special_flag_p (const char *opname
,
226 const struct arc_flag_special
*flg_spec
;
227 unsigned i
, j
, flgidx
;
229 for (i
= 0; i
< arc_num_flag_special
; i
++)
231 flg_spec
= &arc_flag_special_cases
[i
];
233 if (strcmp (opname
, flg_spec
->name
))
236 /* Found potential special case instruction. */
239 flgidx
= flg_spec
->flags
[j
];
241 break; /* End of the array. */
243 if (strcmp (flgname
, arc_flag_operands
[flgidx
].name
) == 0)
250 /* Find opcode from ARC_TABLE given the instruction described by INSN and
251 INSNLEN. The ISA_MASK restricts the possible matches in ARC_TABLE. */
253 static const struct arc_opcode
*
254 find_format_from_table (struct disassemble_info
*info
,
255 const struct arc_opcode
*arc_table
,
256 unsigned long long insn
,
257 unsigned int insn_len
,
259 bfd_boolean
*has_limm
,
260 bfd_boolean overlaps
)
263 const struct arc_opcode
*opcode
= NULL
;
264 const struct arc_opcode
*t_op
= NULL
;
265 const unsigned char *opidx
;
266 const unsigned char *flgidx
;
267 bfd_boolean warn_p
= FALSE
;
271 bfd_boolean invalid
= FALSE
;
273 opcode
= &arc_table
[i
++];
275 if (!(opcode
->cpu
& isa_mask
))
278 if (arc_opcode_len (opcode
) != (int) insn_len
)
281 if ((insn
& opcode
->mask
) != opcode
->opcode
)
286 /* Possible candidate, check the operands. */
287 for (opidx
= opcode
->operands
; *opidx
; opidx
++)
290 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
292 if (operand
->flags
& ARC_OPERAND_FAKE
)
295 if (operand
->extract
)
296 value
= (*operand
->extract
) (insn
, &invalid
);
298 value
= (insn
>> operand
->shift
) & ((1 << operand
->bits
) - 1);
300 /* Check for LIMM indicator. If it is there, then make sure
301 we pick the right format. */
302 limmind
= (isa_mask
& ARC_OPCODE_ARCV2
) ? 0x1E : 0x3E;
303 if (operand
->flags
& ARC_OPERAND_IR
304 && !(operand
->flags
& ARC_OPERAND_LIMM
))
306 if ((value
== 0x3E && insn_len
== 4)
307 || (value
== limmind
&& insn_len
== 2))
314 if (operand
->flags
& ARC_OPERAND_LIMM
315 && !(operand
->flags
& ARC_OPERAND_DUPLICATE
))
319 /* Check the flags. */
320 for (flgidx
= opcode
->flags
; *flgidx
; flgidx
++)
322 /* Get a valid flag class. */
323 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
324 const unsigned *flgopridx
;
325 int foundA
= 0, foundB
= 0;
328 /* Check first the extensions. */
329 if (cl_flags
->flag_class
& F_CLASS_EXTEND
)
331 value
= (insn
& 0x1F);
332 if (arcExtMap_condCodeName (value
))
336 /* Check for the implicit flags. */
337 if (cl_flags
->flag_class
& F_CLASS_IMPLICIT
)
340 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
342 const struct arc_flag_operand
*flg_operand
=
343 &arc_flag_operands
[*flgopridx
];
345 value
= (insn
>> flg_operand
->shift
)
346 & ((1 << flg_operand
->bits
) - 1);
347 if (value
== flg_operand
->code
)
353 if (!foundA
&& foundB
)
368 if (skip_this_opcode (opcode
))
372 /* The instruction is valid. */
375 while (opcode
->mask
);
379 info
->fprintf_func (info
->stream
,
380 _("\nWarning: disassembly may be wrong due to "
381 "guessed opcode class choice.\n"
382 "Use -M<class[,class]> to select the correct "
383 "opcode class(es).\n\t\t\t\t"));
390 /* Find opcode for INSN, trying various different sources. The instruction
391 length in INSN_LEN will be updated if the instruction requires a LIMM
394 A pointer to the opcode is placed into OPCODE_RESULT, and ITER is
395 initialised, ready to iterate over the operands of the found opcode. If
396 the found opcode requires a LIMM then the LIMM value will be loaded into a
399 This function returns TRUE in almost all cases, FALSE is reserved to
400 indicate an error (failing to find an opcode is not an error) a returned
401 result of FALSE would indicate that the disassembler can't continue.
403 If no matching opcode is found then the returned result will be TRUE, the
404 value placed into OPCODE_RESULT will be NULL, ITER will be undefined, and
405 INSN_LEN will be unchanged.
407 If a matching opcode is found, then the returned result will be TRUE, the
408 opcode pointer is placed into OPCODE_RESULT, INSN_LEN will be increased by
409 4 if the instruction requires a LIMM, and the LIMM value will have been
410 loaded into a field of ITER. Finally, ITER will have been initialised so
411 that calls to OPERAND_ITERATOR_NEXT will iterate over the opcode's
415 find_format (bfd_vma memaddr
,
416 unsigned long long insn
,
417 unsigned int * insn_len
,
419 struct disassemble_info
* info
,
420 const struct arc_opcode
** opcode_result
,
421 struct arc_operand_iterator
* iter
)
423 const struct arc_opcode
*opcode
= NULL
;
424 bfd_boolean needs_limm
;
425 const extInstruction_t
*einsn
, *i
;
427 struct arc_disassemble_info
*arc_infop
= info
->private_data
;
429 /* First, try the extension instructions. */
432 einsn
= arcExtMap_insn (OPCODE_32BIT_INSN (insn
), insn
);
433 for (i
= einsn
; (i
!= NULL
) && (opcode
== NULL
); i
= i
->next
)
435 const char *errmsg
= NULL
;
437 opcode
= arcExtMap_genOpcode (i
, isa_mask
, &errmsg
);
440 (*info
->fprintf_func
) (info
->stream
, "\
441 An error occured while generating the extension instruction operations");
442 *opcode_result
= NULL
;
446 opcode
= find_format_from_table (info
, opcode
, insn
, *insn_len
,
447 isa_mask
, &needs_limm
, FALSE
);
451 /* Then, try finding the first match in the opcode table. */
453 opcode
= find_format_from_table (info
, arc_opcodes
, insn
, *insn_len
,
454 isa_mask
, &needs_limm
, TRUE
);
456 if (needs_limm
&& opcode
!= NULL
)
461 status
= (*info
->read_memory_func
) (memaddr
+ *insn_len
, buffer
,
469 limm
= ARRANGE_ENDIAN (info
, buffer
);
478 iter
->opcode
= opcode
;
479 iter
->opidx
= opcode
->operands
;
482 *opcode_result
= opcode
;
484 /* Update private data. */
485 arc_infop
->opcode
= opcode
;
486 arc_infop
->limm
= (needs_limm
) ? limm
: 0;
487 arc_infop
->limm_p
= needs_limm
;
493 print_flags (const struct arc_opcode
*opcode
,
494 unsigned long long *insn
,
495 struct disassemble_info
*info
)
497 const unsigned char *flgidx
;
499 struct arc_disassemble_info
*arc_infop
= info
->private_data
;
501 /* Now extract and print the flags. */
502 for (flgidx
= opcode
->flags
; *flgidx
; flgidx
++)
504 /* Get a valid flag class. */
505 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
506 const unsigned *flgopridx
;
508 /* Check first the extensions. */
509 if (cl_flags
->flag_class
& F_CLASS_EXTEND
)
512 value
= (insn
[0] & 0x1F);
514 name
= arcExtMap_condCodeName (value
);
517 (*info
->fprintf_func
) (info
->stream
, ".%s", name
);
522 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
524 const struct arc_flag_operand
*flg_operand
=
525 &arc_flag_operands
[*flgopridx
];
527 /* Implicit flags are only used for the insn decoder. */
528 if (cl_flags
->flag_class
& F_CLASS_IMPLICIT
)
530 if (cl_flags
->flag_class
& F_CLASS_COND
)
531 arc_infop
->condition_code
= flg_operand
->code
;
532 else if (cl_flags
->flag_class
& F_CLASS_WB
)
533 arc_infop
->writeback_mode
= flg_operand
->code
;
534 else if (cl_flags
->flag_class
& F_CLASS_ZZ
)
535 info
->data_size
= flg_operand
->code
;
539 if (!flg_operand
->favail
)
542 value
= (insn
[0] >> flg_operand
->shift
)
543 & ((1 << flg_operand
->bits
) - 1);
544 if (value
== flg_operand
->code
)
546 /* FIXME!: print correctly nt/t flag. */
547 if (!special_flag_p (opcode
->name
, flg_operand
->name
))
548 (*info
->fprintf_func
) (info
->stream
, ".");
549 else if (info
->insn_type
== dis_dref
)
551 switch (flg_operand
->name
[0])
565 if (flg_operand
->name
[0] == 'd'
566 && flg_operand
->name
[1] == 0)
567 info
->branch_delay_insns
= 1;
569 /* Check if it is a conditional flag. */
570 if (cl_flags
->flag_class
& F_CLASS_COND
)
572 if (info
->insn_type
== dis_jsr
)
573 info
->insn_type
= dis_condjsr
;
574 else if (info
->insn_type
== dis_branch
)
575 info
->insn_type
= dis_condbranch
;
576 arc_infop
->condition_code
= flg_operand
->code
;
579 /* Check for the write back modes. */
580 if (cl_flags
->flag_class
& F_CLASS_WB
)
581 arc_infop
->writeback_mode
= flg_operand
->code
;
583 (*info
->fprintf_func
) (info
->stream
, "%s", flg_operand
->name
);
590 get_auxreg (const struct arc_opcode
*opcode
,
596 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
598 if (opcode
->insn_class
!= AUXREG
)
601 name
= arcExtMap_auxRegName (value
);
605 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
607 if (!(auxr
->cpu
& isa_mask
))
610 if (auxr
->subclass
!= NONE
)
613 if (auxr
->address
== value
)
619 /* Convert a value representing an address type to a string used to refer to
620 the address type in assembly code. */
623 get_addrtype (int value
)
625 if (value
< 0 || value
> addrtypenames_max
)
626 return addrtypeunknown
;
628 return addrtypenames
[value
];
631 /* Calculate the instruction length for an instruction starting with MSB
632 and LSB, the most and least significant byte. The ISA_MASK is used to
633 filter the instructions considered to only those that are part of the
634 current architecture.
636 The instruction lengths are calculated from the ARC_OPCODE table, and
637 cached for later use. */
640 arc_insn_length (bfd_byte msb
, bfd_byte lsb
, struct disassemble_info
*info
)
642 bfd_byte major_opcode
= msb
>> 3;
646 case bfd_mach_arc_arc700
:
647 /* The nps400 extension set requires this special casing of the
648 instruction length calculation. Right now this is not causing any
649 problems as none of the known extensions overlap in opcode space,
650 but, if they ever do then we might need to start carrying
651 information around in the elf about which extensions are in use. */
652 if (major_opcode
== 0xb)
654 bfd_byte minor_opcode
= lsb
& 0x1f;
656 if (minor_opcode
< 4)
658 else if (minor_opcode
== 0x10 || minor_opcode
== 0x11)
661 if (major_opcode
== 0xa)
666 case bfd_mach_arc_arc600
:
667 return (major_opcode
> 0xb) ? 2 : 4;
670 case bfd_mach_arc_arcv2
:
671 return (major_opcode
> 0x7) ? 2 : 4;
679 /* Extract and return the value of OPERAND from the instruction whose value
680 is held in the array INSN. */
683 extract_operand_value (const struct arc_operand
*operand
,
684 unsigned long long insn
,
689 /* Read the limm operand, if required. */
690 if (operand
->flags
& ARC_OPERAND_LIMM
)
691 /* The second part of the instruction value will have been loaded as
692 part of the find_format call made earlier. */
696 if (operand
->extract
)
697 value
= (*operand
->extract
) (insn
, (int *) NULL
);
700 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
702 value
= (insn
>> operand
->shift
)
703 & ((1 << (operand
->bits
- 2)) - 1);
708 value
= (insn
>> operand
->shift
) & ((1 << operand
->bits
) - 1);
710 if (operand
->flags
& ARC_OPERAND_SIGNED
)
712 int signbit
= 1 << (operand
->bits
- 1);
713 value
= (value
^ signbit
) - signbit
;
721 /* Find the next operand, and the operands value from ITER. Return TRUE if
722 there is another operand, otherwise return FALSE. If there is an
723 operand returned then the operand is placed into OPERAND, and the value
724 into VALUE. If there is no operand returned then OPERAND and VALUE are
728 operand_iterator_next (struct arc_operand_iterator
*iter
,
729 const struct arc_operand
**operand
,
732 if (*iter
->opidx
== 0)
738 *operand
= &arc_operands
[*iter
->opidx
];
739 *value
= extract_operand_value (*operand
, iter
->insn
, iter
->limm
);
745 /* Helper for parsing the options. */
748 parse_option (const char *option
)
750 if (disassembler_options_cmp (option
, "dsp") == 0)
751 add_to_decodelist (DSP
, NONE
);
753 else if (disassembler_options_cmp (option
, "spfp") == 0)
754 add_to_decodelist (FLOAT
, SPX
);
756 else if (disassembler_options_cmp (option
, "dpfp") == 0)
757 add_to_decodelist (FLOAT
, DPX
);
759 else if (disassembler_options_cmp (option
, "quarkse_em") == 0)
761 add_to_decodelist (FLOAT
, DPX
);
762 add_to_decodelist (FLOAT
, SPX
);
763 add_to_decodelist (FLOAT
, QUARKSE1
);
764 add_to_decodelist (FLOAT
, QUARKSE2
);
767 else if (disassembler_options_cmp (option
, "fpuda") == 0)
768 add_to_decodelist (FLOAT
, DPA
);
770 else if (disassembler_options_cmp (option
, "nps400") == 0)
772 add_to_decodelist (ACL
, NPS400
);
773 add_to_decodelist (ARITH
, NPS400
);
774 add_to_decodelist (BITOP
, NPS400
);
775 add_to_decodelist (BMU
, NPS400
);
776 add_to_decodelist (CONTROL
, NPS400
);
777 add_to_decodelist (DMA
, NPS400
);
778 add_to_decodelist (DPI
, NPS400
);
779 add_to_decodelist (MEMORY
, NPS400
);
780 add_to_decodelist (MISC
, NPS400
);
781 add_to_decodelist (NET
, NPS400
);
782 add_to_decodelist (PMU
, NPS400
);
783 add_to_decodelist (PROTOCOL_DECODE
, NPS400
);
784 add_to_decodelist (ULTRAIP
, NPS400
);
787 else if (disassembler_options_cmp (option
, "fpus") == 0)
789 add_to_decodelist (FLOAT
, SP
);
790 add_to_decodelist (FLOAT
, CVT
);
793 else if (disassembler_options_cmp (option
, "fpud") == 0)
795 add_to_decodelist (FLOAT
, DP
);
796 add_to_decodelist (FLOAT
, CVT
);
798 else if (CONST_STRNEQ (option
, "hex"))
801 /* xgettext:c-format */
802 opcodes_error_handler (_("unrecognised disassembler option: %s"), option
);
805 #define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
806 { #NAME, ARC_OPCODE_ARC600, "ARC600" }
807 #define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
808 { #NAME, ARC_OPCODE_ARC700, "ARC700" }
809 #define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
810 { #NAME, ARC_OPCODE_ARCv2EM, "ARC EM" }
811 #define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
812 { #NAME, ARC_OPCODE_ARCv2HS, "ARC HS" }
813 #define ARC_CPU_TYPE_NONE \
816 /* A table of CPU names and opcode sets. */
817 static const struct cpu_type
825 #include "elf/arc-cpu.def"
828 /* Helper for parsing the CPU options. Accept any of the ARC architectures
829 values. OPTION should be a value passed to cpu=. */
832 parse_cpu_option (const char *option
)
836 for (i
= 0; cpu_types
[i
].name
; ++i
)
838 if (!disassembler_options_cmp (cpu_types
[i
].name
, option
))
840 return cpu_types
[i
].flags
;
844 /* xgettext:c-format */
845 opcodes_error_handler (_("unrecognised disassembler CPU option: %s"), option
);
846 return ARC_OPCODE_NONE
;
849 /* Go over the options list and parse it. */
852 parse_disassembler_options (const char *options
)
859 /* Disassembler might be reused for difference CPU's, and cpu option set for
860 the first one shouldn't be applied to second (which might not have
861 explicit cpu in its options. Therefore it is required to reset enforced
862 CPU when new options are being parsed. */
863 enforced_isa_mask
= ARC_OPCODE_NONE
;
865 FOR_EACH_DISASSEMBLER_OPTION (option
, options
)
867 /* A CPU option? Cannot use STRING_COMMA_LEN because strncmp is also a
868 preprocessor macro. */
869 if (strncmp (option
, "cpu=", 4) == 0)
870 /* Strip leading `cpu=`. */
871 enforced_isa_mask
= parse_cpu_option (option
+ 4);
873 parse_option (option
);
877 /* Return the instruction type for an instruction described by OPCODE. */
879 static enum dis_insn_type
880 arc_opcode_to_insn_type (const struct arc_opcode
*opcode
)
882 enum dis_insn_type insn_type
;
884 switch (opcode
->insn_class
)
896 if (!strncmp (opcode
->name
, "bl", 2)
897 || !strncmp (opcode
->name
, "jl", 2))
899 if (opcode
->subclass
== COND
)
900 insn_type
= dis_condjsr
;
906 if (opcode
->subclass
== COND
)
907 insn_type
= dis_condbranch
;
909 insn_type
= dis_branch
;
918 insn_type
= dis_dref
;
921 insn_type
= dis_branch
;
924 insn_type
= dis_nonbranch
;
931 /* Disassemble ARC instructions. */
934 print_insn_arc (bfd_vma memaddr
,
935 struct disassemble_info
*info
)
938 unsigned int highbyte
, lowbyte
;
940 unsigned int insn_len
;
941 unsigned long long insn
= 0;
942 unsigned isa_mask
= ARC_OPCODE_NONE
;
943 const struct arc_opcode
*opcode
;
944 bfd_boolean need_comma
;
945 bfd_boolean open_braket
;
947 const struct arc_operand
*operand
;
949 struct arc_operand_iterator iter
;
950 struct arc_disassemble_info
*arc_infop
;
951 bfd_boolean rpcl
= FALSE
, rset
= FALSE
;
953 if (info
->disassembler_options
)
955 parse_disassembler_options (info
->disassembler_options
);
957 /* Avoid repeated parsing of the options. */
958 info
->disassembler_options
= NULL
;
961 if (info
->private_data
== NULL
&& !init_arc_disasm_info (info
))
964 memset (&iter
, 0, sizeof (iter
));
965 highbyte
= ((info
->endian
== BFD_ENDIAN_LITTLE
) ? 1 : 0);
966 lowbyte
= ((info
->endian
== BFD_ENDIAN_LITTLE
) ? 0 : 1);
968 /* Figure out CPU type, unless it was enforced via disassembler options. */
969 if (enforced_isa_mask
== ARC_OPCODE_NONE
)
971 Elf_Internal_Ehdr
*header
= NULL
;
973 if (info
->section
&& info
->section
->owner
)
974 header
= elf_elfheader (info
->section
->owner
);
978 case bfd_mach_arc_arc700
:
979 isa_mask
= ARC_OPCODE_ARC700
;
982 case bfd_mach_arc_arc600
:
983 isa_mask
= ARC_OPCODE_ARC600
;
986 case bfd_mach_arc_arcv2
:
988 isa_mask
= ARC_OPCODE_ARCv2EM
;
989 /* TODO: Perhaps remove definition of header since it is only used at
992 && (header
->e_flags
& EF_ARC_MACH_MSK
) == EF_ARC_CPU_ARCV2HS
)
993 isa_mask
= ARC_OPCODE_ARCv2HS
;
998 isa_mask
= enforced_isa_mask
;
1000 if (isa_mask
== ARC_OPCODE_ARCv2HS
)
1002 /* FPU instructions are not extensions for HS. */
1003 add_to_decodelist (FLOAT
, SP
);
1004 add_to_decodelist (FLOAT
, DP
);
1005 add_to_decodelist (FLOAT
, CVT
);
1008 /* This variable may be set by the instruction decoder. It suggests
1009 the number of bytes objdump should display on a single line. If
1010 the instruction decoder sets this, it should always set it to
1011 the same value in order to get reasonable looking output. */
1013 info
->bytes_per_line
= 8;
1015 /* In the next lines, we set two info variables control the way
1016 objdump displays the raw data. For example, if bytes_per_line is
1017 8 and bytes_per_chunk is 4, the output will look like this:
1018 00: 00000000 00000000
1019 with the chunks displayed according to "display_endian". */
1022 && !(info
->section
->flags
& SEC_CODE
))
1024 /* This is not a CODE section. */
1025 switch (info
->section
->size
)
1030 size
= info
->section
->size
;
1033 size
= (info
->section
->size
& 0x01) ? 1 : 4;
1036 info
->bytes_per_chunk
= 1;
1037 info
->display_endian
= info
->endian
;
1042 info
->bytes_per_chunk
= 2;
1043 info
->display_endian
= info
->endian
;
1046 /* Read the insn into a host word. */
1047 status
= (*info
->read_memory_func
) (memaddr
, buffer
, size
, info
);
1051 (*info
->memory_error_func
) (status
, memaddr
, info
);
1056 && !(info
->section
->flags
& SEC_CODE
))
1061 data
= bfd_get_bits (buffer
, size
* 8,
1062 info
->display_endian
== BFD_ENDIAN_BIG
);
1066 (*info
->fprintf_func
) (info
->stream
, ".byte\t0x%02lx", data
);
1069 (*info
->fprintf_func
) (info
->stream
, ".short\t0x%04lx", data
);
1072 (*info
->fprintf_func
) (info
->stream
, ".word\t0x%08lx", data
);
1080 insn_len
= arc_insn_length (buffer
[highbyte
], buffer
[lowbyte
], info
);
1081 pr_debug ("instruction length = %d bytes\n", insn_len
);
1082 arc_infop
= info
->private_data
;
1083 arc_infop
->insn_len
= insn_len
;
1088 insn
= (buffer
[highbyte
] << 8) | buffer
[lowbyte
];
1093 /* This is a long instruction: Read the remaning 2 bytes. */
1094 status
= (*info
->read_memory_func
) (memaddr
+ 2, &buffer
[2], 2, info
);
1097 (*info
->memory_error_func
) (status
, memaddr
+ 2, info
);
1100 insn
= (unsigned long long) ARRANGE_ENDIAN (info
, buffer
);
1106 status
= (*info
->read_memory_func
) (memaddr
+ 2, &buffer
[2], 4, info
);
1109 (*info
->memory_error_func
) (status
, memaddr
+ 2, info
);
1112 insn
= (unsigned long long) ARRANGE_ENDIAN (info
, &buffer
[2]);
1113 insn
|= ((unsigned long long) buffer
[highbyte
] << 40)
1114 | ((unsigned long long) buffer
[lowbyte
] << 32);
1120 status
= (*info
->read_memory_func
) (memaddr
+ 2, &buffer
[2], 6, info
);
1123 (*info
->memory_error_func
) (status
, memaddr
+ 2, info
);
1127 ((((unsigned long long) ARRANGE_ENDIAN (info
, buffer
)) << 32)
1128 | ((unsigned long long) ARRANGE_ENDIAN (info
, &buffer
[4])));
1133 /* There is no instruction whose length is not 2, 4, 6, or 8. */
1137 pr_debug ("instruction value = %llx\n", insn
);
1139 /* Set some defaults for the insn info. */
1140 info
->insn_info_valid
= 1;
1141 info
->branch_delay_insns
= 0;
1142 info
->data_size
= 4;
1143 info
->insn_type
= dis_nonbranch
;
1147 /* FIXME to be moved in dissasemble_init_for_target. */
1148 info
->disassembler_needs_relocs
= TRUE
;
1150 /* Find the first match in the opcode table. */
1151 if (!find_format (memaddr
, insn
, &insn_len
, isa_mask
, info
, &opcode
, &iter
))
1159 (*info
->fprintf_func
) (info
->stream
, ".shor\t%#04llx",
1163 (*info
->fprintf_func
) (info
->stream
, ".word\t%#08llx",
1167 (*info
->fprintf_func
) (info
->stream
, ".long\t%#08llx",
1169 (*info
->fprintf_func
) (info
->stream
, ".long\t%#04llx",
1170 (insn
>> 32) & 0xffff);
1173 (*info
->fprintf_func
) (info
->stream
, ".long\t%#08llx",
1175 (*info
->fprintf_func
) (info
->stream
, ".long\t%#08llx",
1182 info
->insn_type
= dis_noninsn
;
1186 /* Print the mnemonic. */
1187 (*info
->fprintf_func
) (info
->stream
, "%s", opcode
->name
);
1189 /* Preselect the insn class. */
1190 info
->insn_type
= arc_opcode_to_insn_type (opcode
);
1192 pr_debug ("%s: 0x%08llx\n", opcode
->name
, opcode
->opcode
);
1194 print_flags (opcode
, &insn
, info
);
1196 if (opcode
->operands
[0] != 0)
1197 (*info
->fprintf_func
) (info
->stream
, "\t");
1200 open_braket
= FALSE
;
1201 arc_infop
->operands_count
= 0;
1203 /* Now extract and print the operands. */
1206 while (operand_iterator_next (&iter
, &operand
, &value
))
1208 if (open_braket
&& (operand
->flags
& ARC_OPERAND_BRAKET
))
1210 (*info
->fprintf_func
) (info
->stream
, "]");
1211 open_braket
= FALSE
;
1215 /* Only take input from real operands. */
1216 if (ARC_OPERAND_IS_FAKE (operand
))
1219 if ((operand
->flags
& ARC_OPERAND_IGNORE
)
1220 && (operand
->flags
& ARC_OPERAND_IR
)
1224 if (operand
->flags
& ARC_OPERAND_COLON
)
1226 (*info
->fprintf_func
) (info
->stream
, ":");
1231 (*info
->fprintf_func
) (info
->stream
, ",");
1233 if (!open_braket
&& (operand
->flags
& ARC_OPERAND_BRAKET
))
1235 (*info
->fprintf_func
) (info
->stream
, "[");
1243 if (operand
->flags
& ARC_OPERAND_PCREL
)
1249 info
->target
= (bfd_vma
) (memaddr
& ~3) + value
;
1251 else if (!(operand
->flags
& ARC_OPERAND_IR
))
1257 /* Print the operand as directed by the flags. */
1258 if (operand
->flags
& ARC_OPERAND_IR
)
1262 assert (value
>=0 && value
< 64);
1263 rname
= arcExtMap_coreRegName (value
);
1265 rname
= regnames
[value
];
1266 (*info
->fprintf_func
) (info
->stream
, "%s", rname
);
1267 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
1269 rname
= arcExtMap_coreRegName (value
+ 1);
1271 rname
= regnames
[value
+ 1];
1272 (*info
->fprintf_func
) (info
->stream
, "%s", rname
);
1279 else if (operand
->flags
& ARC_OPERAND_LIMM
)
1281 const char *rname
= get_auxreg (opcode
, value
, isa_mask
);
1283 if (rname
&& open_braket
)
1284 (*info
->fprintf_func
) (info
->stream
, "%s", rname
);
1287 (*info
->fprintf_func
) (info
->stream
, "%#x", value
);
1288 if (info
->insn_type
== dis_branch
1289 || info
->insn_type
== dis_jsr
)
1290 info
->target
= (bfd_vma
) value
;
1293 else if (operand
->flags
& ARC_OPERAND_SIGNED
)
1295 const char *rname
= get_auxreg (opcode
, value
, isa_mask
);
1296 if (rname
&& open_braket
)
1297 (*info
->fprintf_func
) (info
->stream
, "%s", rname
);
1301 (*info
->fprintf_func
) (info
->stream
, "%#x", value
);
1303 (*info
->fprintf_func
) (info
->stream
, "%d", value
);
1306 else if (operand
->flags
& ARC_OPERAND_ADDRTYPE
)
1308 const char *addrtype
= get_addrtype (value
);
1309 (*info
->fprintf_func
) (info
->stream
, "%s", addrtype
);
1310 /* A colon follow an address type. */
1315 if (operand
->flags
& ARC_OPERAND_TRUNCATE
1316 && !(operand
->flags
& ARC_OPERAND_ALIGNED32
)
1317 && !(operand
->flags
& ARC_OPERAND_ALIGNED16
)
1318 && value
>= 0 && value
<= 14)
1320 /* Leave/Enter mnemonics. */
1327 (*info
->fprintf_func
) (info
->stream
, "r13");
1330 (*info
->fprintf_func
) (info
->stream
, "r13-%s",
1331 regnames
[13 + value
- 1]);
1339 const char *rname
= get_auxreg (opcode
, value
, isa_mask
);
1340 if (rname
&& open_braket
)
1341 (*info
->fprintf_func
) (info
->stream
, "%s", rname
);
1343 (*info
->fprintf_func
) (info
->stream
, "%#x", value
);
1347 if (operand
->flags
& ARC_OPERAND_LIMM
)
1349 arc_infop
->operands
[arc_infop
->operands_count
].kind
1350 = ARC_OPERAND_KIND_LIMM
;
1351 /* It is not important to have exactly the LIMM indicator
1353 arc_infop
->operands
[arc_infop
->operands_count
].value
= 63;
1357 arc_infop
->operands
[arc_infop
->operands_count
].value
= value
;
1358 arc_infop
->operands
[arc_infop
->operands_count
].kind
1359 = (operand
->flags
& ARC_OPERAND_IR
1360 ? ARC_OPERAND_KIND_REG
1361 : ARC_OPERAND_KIND_SHIMM
);
1363 arc_infop
->operands_count
++;
1366 /* Pretty print extra info for pc-relative operands. */
1369 if (info
->flags
& INSN_HAS_RELOC
)
1370 /* If the instruction has a reloc associated with it, then the
1371 offset field in the instruction will actually be the addend
1372 for the reloc. (We are using REL type relocs). In such
1373 cases, we can ignore the pc when computing addresses, since
1374 the addend is not currently pc-relative. */
1377 (*info
->fprintf_func
) (info
->stream
, "\t;");
1378 (*info
->print_address_func
) ((memaddr
& ~3) + vpcl
, info
);
1386 arc_get_disassembler (bfd
*abfd
)
1388 /* BFD my be absent, if opcodes is invoked from the debugger that
1389 has connected to remote target and doesn't have an ELF file. */
1392 /* Read the extension insns and registers, if any. */
1393 build_ARC_extmap (abfd
);
1399 return print_insn_arc
;
1403 print_arc_disassembler_options (FILE *stream
)
1407 fprintf (stream
, _("\n\
1408 The following ARC specific disassembler options are supported for use \n\
1409 with -M switch (multiple options should be separated by commas):\n"));
1411 /* cpu=... options. */
1412 for (i
= 0; cpu_types
[i
].name
; ++i
)
1414 /* As of now all value CPU values are less than 16 characters. */
1415 fprintf (stream
, " cpu=%-16s\tEnforce %s ISA.\n",
1416 cpu_types
[i
].name
, cpu_types
[i
].isa
);
1419 fprintf (stream
, _("\
1420 dsp Recognize DSP instructions.\n"));
1421 fprintf (stream
, _("\
1422 spfp Recognize FPX SP instructions.\n"));
1423 fprintf (stream
, _("\
1424 dpfp Recognize FPX DP instructions.\n"));
1425 fprintf (stream
, _("\
1426 quarkse_em Recognize FPU QuarkSE-EM instructions.\n"));
1427 fprintf (stream
, _("\
1428 fpuda Recognize double assist FPU instructions.\n"));
1429 fprintf (stream
, _("\
1430 fpus Recognize single precision FPU instructions.\n"));
1431 fprintf (stream
, _("\
1432 fpud Recognize double precision FPU instructions.\n"));
1433 fprintf (stream
, _("\
1434 nps400 Recognize NPS400 instructions.\n"));
1435 fprintf (stream
, _("\
1436 hex Use only hexadecimal number to print immediates.\n"));
1439 void arc_insn_decode (bfd_vma addr
,
1440 struct disassemble_info
*info
,
1441 disassembler_ftype disasm_func
,
1442 struct arc_instruction
*insn
)
1444 const struct arc_opcode
*opcode
;
1445 struct arc_disassemble_info
*arc_infop
;
1447 /* Ensure that insn would be in the reset state. */
1448 memset (insn
, 0, sizeof (struct arc_instruction
));
1450 /* There was an error when disassembling, for example memory read error. */
1451 if (disasm_func (addr
, info
) < 0)
1453 insn
->valid
= FALSE
;
1457 assert (info
->private_data
!= NULL
);
1458 arc_infop
= info
->private_data
;
1460 insn
->length
= arc_infop
->insn_len
;;
1461 insn
->address
= addr
;
1463 /* Quick exit if memory at this address is not an instruction. */
1464 if (info
->insn_type
== dis_noninsn
)
1466 insn
->valid
= FALSE
;
1472 opcode
= (const struct arc_opcode
*) arc_infop
->opcode
;
1473 insn
->insn_class
= opcode
->insn_class
;
1474 insn
->limm_value
= arc_infop
->limm
;
1475 insn
->limm_p
= arc_infop
->limm_p
;
1477 insn
->is_control_flow
= (info
->insn_type
== dis_branch
1478 || info
->insn_type
== dis_condbranch
1479 || info
->insn_type
== dis_jsr
1480 || info
->insn_type
== dis_condjsr
);
1482 insn
->has_delay_slot
= info
->branch_delay_insns
;
1483 insn
->writeback_mode
1484 = (enum arc_ldst_writeback_mode
) arc_infop
->writeback_mode
;
1485 insn
->data_size_mode
= info
->data_size
;
1486 insn
->condition_code
= arc_infop
->condition_code
;
1487 memcpy (insn
->operands
, arc_infop
->operands
,
1488 sizeof (struct arc_insn_operand
) * MAX_INSN_ARGS
);
1489 insn
->operands_count
= arc_infop
->operands_count
;
1493 eval: (c-set-style "gnu")