1 /* Instruction printing code for the ARC.
2 Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2005, 2007, 2009,
3 2010, 2012 Free Software Foundation, Inc.
4 Contributed by Doug Evans (dje@cygnus.com).
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 #include "libiberty.h"
26 #include "opcode/arc.h"
40 /* Classification of the opcodes for the decoder to print
48 /* All branches other than JC. */
51 /* All loads other than immediate
57 /* All single operand instructions. */
58 CLASS_A4_OP3_SUBOPC3F
,
62 #define BIT(word,n) ((word) & (1 << n))
63 #define BITS(word,s,e) (((word) >> s) & ((1 << (e + 1 - s)) - 1))
64 #define OPCODE(word) (BITS ((word), 27, 31))
65 #define FIELDA(word) (BITS ((word), 21, 26))
66 #define FIELDB(word) (BITS ((word), 15, 20))
67 #define FIELDC(word) (BITS ((word), 9, 14))
69 /* FIELD D is signed. */
70 #define FIELDD(word) ((BITS ((word), 0, 8) ^ 0x100) - 0x100)
72 #define PUT_NEXT_WORD_IN(a) \
75 if (is_limm == 1 && !NEXT_WORD (1)) \
76 mwerror (state, _("Illegal limm reference in last instruction!\n")); \
77 a = state->words[1]; \
81 #define CHECK_FLAG_COND_NULLIFY() \
86 flag = BIT (state->words[0], 8); \
87 state->nullifyMode = BITS (state->words[0], 5, 6); \
88 cond = BITS (state->words[0], 0, 4); \
93 #define CHECK_COND() \
97 cond = BITS (state->words[0], 0, 4); \
101 #define CHECK_FIELD(field) \
108 PUT_NEXT_WORD_IN (field); \
109 limm_value = field; \
111 else if (field > 60) \
115 flag = (field == 61); \
116 field = FIELDD (state->words[0]); \
121 #define CHECK_FIELD_A() \
124 fieldA = FIELDA (state->words[0]); \
133 #define CHECK_FIELD_B() \
136 fieldB = FIELDB (state->words[0]); \
137 CHECK_FIELD (fieldB); \
141 #define CHECK_FIELD_C() \
144 fieldC = FIELDC (state->words[0]); \
145 CHECK_FIELD (fieldC); \
149 #define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
150 #define IS_REG(x) (field##x##isReg)
151 #define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT (x, "[","]","","")
152 #define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT (x, "",",[","",",[")
153 #define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT (x, ",","]",",","]")
154 #define WRITE_FORMAT_x_RB(x) WRITE_FORMAT (x, "","]","","]")
155 #define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT (x, ",","",",","")
156 #define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT (x, "",",","",",")
157 #define WRITE_FORMAT_x(x) WRITE_FORMAT (x, "","","","")
158 #define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \
159 (IS_REG (x) ? cb1"%r"ca1 : \
160 usesAuxReg ? cb"%a"ca : \
161 IS_SMALL (x) ? cb"%d"ca : cb"%h"ca))
162 #define WRITE_FORMAT_RB() strcat (formatString, "]")
163 #define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str))
164 #define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
166 #define NEXT_WORD(x) (offset += 4, state->words[x])
168 #define add_target(x) (state->targets[state->tcnt++] = (x))
170 static char comment_prefix
[] = "\t; ";
173 core_reg_name (struct arcDisState
* state
, int val
)
175 if (state
->coreRegName
)
176 return (*state
->coreRegName
)(state
->_this
, val
);
181 aux_reg_name (struct arcDisState
* state
, int val
)
183 if (state
->auxRegName
)
184 return (*state
->auxRegName
)(state
->_this
, val
);
189 cond_code_name (struct arcDisState
* state
, int val
)
191 if (state
->condCodeName
)
192 return (*state
->condCodeName
)(state
->_this
, val
);
197 instruction_name (struct arcDisState
* state
,
203 return (*state
->instName
)(state
->_this
, op1
, op2
, flags
);
208 mwerror (struct arcDisState
* state
, const char * msg
)
211 (*state
->err
)(state
->_this
, (msg
));
215 post_address (struct arcDisState
* state
, int addr
)
217 static char id
[3 * ARRAY_SIZE (state
->addresses
)];
218 int j
, i
= state
->acnt
;
220 if (i
< ((int) ARRAY_SIZE (state
->addresses
)))
222 state
->addresses
[i
] = addr
;
235 arc_sprintf (struct arcDisState
*state
, char *buf
, const char *format
, ...)
239 int size
, leading_zero
, regMap
[2];
242 va_start (ap
, format
);
254 goto DOCOMM
; /* (return) */
278 leading_zero
= 1; /* e.g. %08x */
279 while (*p
>= '0' && *p
<= '9')
281 size
= size
* 10 + *p
- '0';
286 #define inc_bp() bp = bp + strlen (bp)
290 unsigned u
= va_arg (ap
, int);
292 /* Hex. We can change the format to 0x%08x in
293 one place, here, if we wish.
294 We add underscores for easy reading. */
296 sprintf (bp
, "0x%x_%04x", u
>> 16, u
& 0xffff);
298 sprintf (bp
, "0x%x", u
);
304 int val
= va_arg (ap
, int);
308 sprintf (bp
, "%0*x", size
, val
);
310 sprintf (bp
, "%*x", size
, val
);
312 sprintf (bp
, "%x", val
);
318 int val
= va_arg (ap
, int);
321 sprintf (bp
, "%*d", size
, val
);
323 sprintf (bp
, "%d", val
);
330 int val
= va_arg (ap
, int);
332 #define REG2NAME(num, name) case num: sprintf (bp, ""name); \
333 regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break;
340 REG2NAME (29, "ilink1");
341 REG2NAME (30, "ilink2");
342 REG2NAME (31, "blink");
343 REG2NAME (60, "lp_count");
348 ext
= core_reg_name (state
, val
);
350 sprintf (bp
, "%s", ext
);
352 sprintf (bp
,"r%d",val
);
362 int val
= va_arg (ap
, int);
364 #define AUXREG2NAME(num, name) case num: sprintf (bp,name); break;
368 AUXREG2NAME (0x0, "status");
369 AUXREG2NAME (0x1, "semaphore");
370 AUXREG2NAME (0x2, "lp_start");
371 AUXREG2NAME (0x3, "lp_end");
372 AUXREG2NAME (0x4, "identity");
373 AUXREG2NAME (0x5, "debug");
378 ext
= aux_reg_name (state
, val
);
380 sprintf (bp
, "%s", ext
);
382 arc_sprintf (state
, bp
, "%h", val
);
392 sprintf (bp
, "%s", va_arg (ap
, char *));
398 fprintf (stderr
, "?? format %c\n", p
[-1]);
408 write_comments_(struct arcDisState
* state
,
413 if (state
->commentBuffer
!= 0)
419 const char *name
= post_address (state
, limm_value
+ shimm
);
422 WRITE_COMMENT (name
);
424 for (i
= 0; i
< state
->commNum
; i
++)
427 strcpy (state
->commentBuffer
, comment_prefix
);
429 strcat (state
->commentBuffer
, ", ");
430 strncat (state
->commentBuffer
, state
->comm
[i
],
431 sizeof (state
->commentBuffer
));
436 #define write_comments2(x) write_comments_ (state, x, is_limm, limm_value)
437 #define write_comments() write_comments2 (0)
439 static const char *condName
[] =
442 "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" ,
443 "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
447 write_instr_name_(struct arcDisState
* state
,
448 const char * instrName
,
450 int condCodeIsPartOfName
,
456 strcpy (state
->instrBuffer
, instrName
);
462 if (!condCodeIsPartOfName
)
463 strcat (state
->instrBuffer
, ".");
468 cc
= cond_code_name (state
, cond
);
473 strcat (state
->instrBuffer
, cc
);
477 strcat (state
->instrBuffer
, ".f");
479 switch (state
->nullifyMode
)
482 strcat (state
->instrBuffer
, ".d");
484 case BR_exec_when_jump
:
485 strcat (state
->instrBuffer
, ".jd");
490 strcat (state
->instrBuffer
, ".x");
493 strcat (state
->instrBuffer
, ".a");
496 strcat (state
->instrBuffer
, ".di");
499 #define write_instr_name() \
502 write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \
503 flag, signExtend, addrWriteBack, directMem); \
504 formatString[0] = '\0'; \
510 op_LD0
= 0, op_LD1
= 1, op_ST
= 2, op_3
= 3,
511 op_BC
= 4, op_BLC
= 5, op_LPC
= 6, op_JC
= 7,
512 op_ADD
= 8, op_ADC
= 9, op_SUB
= 10, op_SBC
= 11,
513 op_AND
= 12, op_OR
= 13, op_BIC
= 14, op_XOR
= 15
516 extern disassemble_info tm_print_insn_info
;
519 dsmOneArcInst (bfd_vma addr
, struct arcDisState
* state
)
521 int condCodeIsPartOfName
= 0;
522 a4_decoding_class decodingClass
;
523 const char * instrName
;
537 int addrWriteBack
= 0;
544 char formatString
[60];
546 state
->instructionLen
= 4;
547 state
->nullifyMode
= BR_exec_when_no_jump
;
551 state
->_mem_load
= 0;
552 state
->_ea_present
= 0;
553 state
->_load_len
= 0;
554 state
->ea_reg1
= no_reg
;
555 state
->ea_reg2
= no_reg
;
561 state
->_opcode
= OPCODE (state
->words
[0]);
563 decodingClass
= CLASS_A4_ARITH
; /* default! */
565 condCodeIsPartOfName
=0;
569 state
->flow
= noflow
;
572 if (state
->commentBuffer
)
573 state
->commentBuffer
[0] = '\0';
575 switch (state
->_opcode
)
578 switch (BITS (state
->words
[0],1,2))
582 state
->_load_len
= 4;
586 state
->_load_len
= 1;
590 state
->_load_len
= 2;
593 instrName
= "??? (0[3])";
594 state
->flow
= invalid_instr
;
597 decodingClass
= CLASS_A4_LD0
;
601 if (BIT (state
->words
[0],13))
604 decodingClass
= CLASS_A4_LR
;
608 switch (BITS (state
->words
[0], 10, 11))
612 state
->_load_len
= 4;
616 state
->_load_len
= 1;
620 state
->_load_len
= 2;
623 instrName
= "??? (1[3])";
624 state
->flow
= invalid_instr
;
627 decodingClass
= CLASS_A4_LD1
;
632 if (BIT (state
->words
[0], 25))
635 decodingClass
= CLASS_A4_SR
;
639 switch (BITS (state
->words
[0], 22, 23))
651 instrName
= "??? (2[3])";
652 state
->flow
= invalid_instr
;
655 decodingClass
= CLASS_A4_ST
;
660 decodingClass
= CLASS_A4_OP3_GENERAL
; /* default for opcode 3... */
661 switch (FIELDC (state
->words
[0]))
665 decodingClass
= CLASS_A4_FLAG
;
693 decodingClass
= CLASS_A4_OP3_SUBOPC3F
;
694 switch (FIELDD (state
->words
[0]))
707 state
->flow
=invalid_instr
;
713 /* ARC Extension Library Instructions
714 NOTE: We assume that extension codes are these instrs. */
716 instrName
= instruction_name (state
,
718 FIELDC (state
->words
[0]),
723 state
->flow
= invalid_instr
;
725 if (flags
& IGNORE_FIRST_OPD
)
742 if (BITS (state
->words
[0],9,9))
753 condCodeIsPartOfName
= 1;
754 decodingClass
= ((state
->_opcode
== op_JC
) ? CLASS_A4_JC
: CLASS_A4_BRANCH
);
761 repeatsOp
= (FIELDC (state
->words
[0]) == FIELDB (state
->words
[0]));
763 switch (state
->_opcode
)
766 instrName
= (repeatsOp
? "asl" : "add");
769 instrName
= (repeatsOp
? "rlc" : "adc");
772 instrName
= (repeatsOp
? "mov" : "and");
777 case op_SUB
: instrName
= "sub";
779 case op_SBC
: instrName
= "sbc";
781 case op_OR
: instrName
= "or";
783 case op_BIC
: instrName
= "bic";
787 if (state
->words
[0] == 0x7fffffff)
789 /* NOP encoded as xor -1, -1, -1. */
791 decodingClass
= CLASS_A4_OP3_SUBOPC3F
;
798 instrName
= instruction_name (state
,state
->_opcode
,0,&flags
);
799 /* if (instrName) printf("FLAGS=0x%x\n", flags); */
803 state
->flow
=invalid_instr
;
805 if (flags
& IGNORE_FIRST_OPD
)
810 fieldAisReg
= fieldBisReg
= fieldCisReg
= 1; /* Assume regs for now. */
811 flag
= cond
= is_shimm
= is_limm
= 0;
812 state
->nullifyMode
= BR_exec_when_no_jump
; /* 0 */
813 signExtend
= addrWriteBack
= directMem
= 0;
816 switch (decodingClass
)
823 CHECK_FLAG_COND_NULLIFY ();
829 WRITE_FORMAT_COMMA_x (B
);
831 WRITE_FORMAT_COMMA_x (C
);
832 WRITE_NOP_COMMENT ();
833 arc_sprintf (state
, state
->operandBuffer
, formatString
,
834 fieldA
, fieldB
, fieldC
);
840 WRITE_FORMAT_COMMA_x (C
);
841 arc_sprintf (state
, state
->operandBuffer
, formatString
,
847 case CLASS_A4_OP3_GENERAL
:
850 CHECK_FLAG_COND_NULLIFY ();
856 WRITE_FORMAT_COMMA_x (B
);
857 WRITE_NOP_COMMENT ();
858 arc_sprintf (state
, state
->operandBuffer
, formatString
,
864 arc_sprintf (state
, state
->operandBuffer
, formatString
, fieldB
);
871 CHECK_FLAG_COND_NULLIFY ();
872 flag
= 0; /* This is the FLAG instruction -- it's redundant. */
876 arc_sprintf (state
, state
->operandBuffer
, formatString
, fieldB
);
880 case CLASS_A4_BRANCH
:
881 fieldA
= BITS (state
->words
[0],7,26) << 2;
882 fieldA
= (fieldA
<< 10) >> 10; /* Make it signed. */
884 CHECK_FLAG_COND_NULLIFY ();
888 /* This address could be a label we know. Convert it. */
889 if (state
->_opcode
!= op_LPC
/* LP */)
891 add_target (fieldA
); /* For debugger. */
892 state
->flow
= state
->_opcode
== op_BLC
/* BL */
895 /* indirect calls are achieved by "lr blink,[status];
896 lr dest<- func addr; j [dest]" */
899 strcat (formatString
, "%s"); /* Address/label name. */
900 arc_sprintf (state
, state
->operandBuffer
, formatString
,
901 post_address (state
, fieldA
));
906 /* For op_JC -- jump to address specified.
907 Also covers jump and link--bit 9 of the instr. word
908 selects whether linked, thus "is_linked" is set above. */
911 CHECK_FLAG_COND_NULLIFY ();
916 fieldA
= (fieldB
>> 25) & 0x7F; /* Flags. */
917 fieldB
= (fieldB
& 0xFFFFFF) << 2;
918 state
->flow
= is_linked
? direct_call
: direct_jump
;
920 /* Screwy JLcc requires .jd mode to execute correctly
921 but we pretend it is .nd (no delay slot). */
922 if (is_linked
&& state
->nullifyMode
== BR_exec_when_jump
)
923 state
->nullifyMode
= BR_exec_when_no_jump
;
927 state
->flow
= is_linked
? indirect_call
: indirect_jump
;
928 /* We should also treat this as indirect call if NOT linked
929 but the preceding instruction was a "lr blink,[status]"
930 and we have a delay slot with "add blink,blink,2".
931 For now we can't detect such. */
932 state
->register_for_indirect_jump
= fieldB
;
936 strcat (formatString
,
937 IS_REG (B
) ? "[%r]" : "%s"); /* Address/label name. */
941 WRITE_FORMAT_COMMA_x (A
);
944 arc_sprintf (state
, state
->operandBuffer
, formatString
, fieldB
, fieldA
);
946 arc_sprintf (state
, state
->operandBuffer
, formatString
,
947 post_address (state
, fieldB
), fieldA
);
953 B and C can be regs, or one (both?) can be limm. */
958 printf ("5:b reg %d %d c reg %d %d \n",
959 fieldBisReg
,fieldB
,fieldCisReg
,fieldC
);
961 state
->_ea_present
= 1;
963 state
->ea_reg1
= fieldB
;
965 state
->_offset
+= fieldB
;
967 state
->ea_reg2
= fieldC
;
969 state
->_offset
+= fieldC
;
970 state
->_mem_load
= 1;
972 directMem
= BIT (state
->words
[0], 5);
973 addrWriteBack
= BIT (state
->words
[0], 3);
974 signExtend
= BIT (state
->words
[0], 0);
977 WRITE_FORMAT_x_COMMA_LB(A
);
978 if (fieldBisReg
|| fieldB
!= 0)
979 WRITE_FORMAT_x_COMMA (B
);
983 WRITE_FORMAT_x_RB (C
);
984 arc_sprintf (state
, state
->operandBuffer
, formatString
,
985 fieldA
, fieldB
, fieldC
);
990 /* LD instruction. */
993 fieldC
= FIELDD (state
->words
[0]);
996 printf ("6:b reg %d %d c 0x%x \n",
997 fieldBisReg
, fieldB
, fieldC
);
998 state
->_ea_present
= 1;
999 state
->_offset
= fieldC
;
1000 state
->_mem_load
= 1;
1002 state
->ea_reg1
= fieldB
;
1003 /* Field B is either a shimm (same as fieldC) or limm (different!)
1004 Say ea is not present, so only one of us will do the name lookup. */
1006 state
->_offset
+= fieldB
, state
->_ea_present
= 0;
1008 directMem
= BIT (state
->words
[0],14);
1009 addrWriteBack
= BIT (state
->words
[0],12);
1010 signExtend
= BIT (state
->words
[0],9);
1012 write_instr_name ();
1013 WRITE_FORMAT_x_COMMA_LB (A
);
1016 fieldB
= state
->_offset
;
1017 WRITE_FORMAT_x_RB (B
);
1022 if (fieldC
!= 0 && !BIT (state
->words
[0],13))
1025 WRITE_FORMAT_COMMA_x_RB (C
);
1030 arc_sprintf (state
, state
->operandBuffer
, formatString
,
1031 fieldA
, fieldB
, fieldC
);
1036 /* ST instruction. */
1039 fieldA
= FIELDD(state
->words
[0]); /* shimm */
1042 if (dbg
) printf("7:b reg %d %x off %x\n",
1043 fieldBisReg
,fieldB
,fieldA
);
1044 state
->_ea_present
= 1;
1045 state
->_offset
= fieldA
;
1047 state
->ea_reg1
= fieldB
;
1048 /* Field B is either a shimm (same as fieldA) or limm (different!)
1049 Say ea is not present, so only one of us will do the name lookup.
1050 (for is_limm we do the name translation here). */
1052 state
->_offset
+= fieldB
, state
->_ea_present
= 0;
1054 directMem
= BIT (state
->words
[0], 26);
1055 addrWriteBack
= BIT (state
->words
[0], 24);
1057 write_instr_name ();
1058 WRITE_FORMAT_x_COMMA_LB(C
);
1062 fieldB
= state
->_offset
;
1063 WRITE_FORMAT_x_RB (B
);
1068 if (fieldBisReg
&& fieldA
!= 0)
1071 WRITE_FORMAT_COMMA_x_RB(A
);
1076 arc_sprintf (state
, state
->operandBuffer
, formatString
,
1077 fieldC
, fieldB
, fieldA
);
1078 write_comments2 (fieldA
);
1082 /* SR instruction */
1086 write_instr_name ();
1087 WRITE_FORMAT_x_COMMA_LB(C
);
1088 /* Try to print B as an aux reg if it is not a core reg. */
1092 arc_sprintf (state
, state
->operandBuffer
, formatString
, fieldC
, fieldB
);
1096 case CLASS_A4_OP3_SUBOPC3F
:
1097 write_instr_name ();
1098 state
->operandBuffer
[0] = '\0';
1102 /* LR instruction */
1106 write_instr_name ();
1107 WRITE_FORMAT_x_COMMA_LB (A
);
1108 /* Try to print B as an aux reg if it is not a core reg. */
1112 arc_sprintf (state
, state
->operandBuffer
, formatString
, fieldA
, fieldB
);
1117 mwerror (state
, "Bad decoding class in ARC disassembler");
1121 state
->_cond
= cond
;
1122 return state
->instructionLen
= offset
;
1126 /* Returns the name the user specified core extension register. */
1129 _coreRegName(void * arg ATTRIBUTE_UNUSED
, int regval
)
1131 return arcExtMap_coreRegName (regval
);
1134 /* Returns the name the user specified AUX extension register. */
1137 _auxRegName(void *_this ATTRIBUTE_UNUSED
, int regval
)
1139 return arcExtMap_auxRegName(regval
);
1142 /* Returns the name the user specified condition code name. */
1145 _condCodeName(void *_this ATTRIBUTE_UNUSED
, int regval
)
1147 return arcExtMap_condCodeName(regval
);
1150 /* Returns the name the user specified extension instruction. */
1153 _instName (void *_this ATTRIBUTE_UNUSED
, int majop
, int minop
, int *flags
)
1155 return arcExtMap_instName(majop
, minop
, flags
);
1158 /* Decode an instruction returning the size of the instruction
1159 in bytes or zero if unrecognized. */
1162 decodeInstr (bfd_vma address
, /* Address of this instruction. */
1163 disassemble_info
* info
)
1167 struct arcDisState s
; /* ARC Disassembler state. */
1168 void *stream
= info
->stream
; /* Output stream. */
1169 fprintf_ftype func
= info
->fprintf_func
;
1171 memset (&s
, 0, sizeof(struct arcDisState
));
1173 /* read first instruction */
1174 status
= (*info
->read_memory_func
) (address
, buffer
, 4, info
);
1177 (*info
->memory_error_func
) (status
, address
, info
);
1180 if (info
->endian
== BFD_ENDIAN_LITTLE
)
1181 s
.words
[0] = bfd_getl32(buffer
);
1183 s
.words
[0] = bfd_getb32(buffer
);
1184 /* Always read second word in case of limm. */
1186 /* We ignore the result since last insn may not have a limm. */
1187 status
= (*info
->read_memory_func
) (address
+ 4, buffer
, 4, info
);
1188 if (info
->endian
== BFD_ENDIAN_LITTLE
)
1189 s
.words
[1] = bfd_getl32(buffer
);
1191 s
.words
[1] = bfd_getb32(buffer
);
1194 s
.coreRegName
= _coreRegName
;
1195 s
.auxRegName
= _auxRegName
;
1196 s
.condCodeName
= _condCodeName
;
1197 s
.instName
= _instName
;
1200 dsmOneArcInst (address
, & s
);
1202 /* Display the disassembly instruction. */
1203 (*func
) (stream
, "%08lx ", s
.words
[0]);
1204 (*func
) (stream
, " ");
1205 (*func
) (stream
, "%-10s ", s
.instrBuffer
);
1207 if (__TRANSLATION_REQUIRED (s
))
1209 bfd_vma addr
= s
.addresses
[s
.operandBuffer
[1] - '0'];
1211 (*info
->print_address_func
) ((bfd_vma
) addr
, info
);
1212 (*func
) (stream
, "\n");
1215 (*func
) (stream
, "%s",s
.operandBuffer
);
1217 return s
.instructionLen
;
1220 /* Return the print_insn function to use.
1221 Side effect: load (possibly empty) extension section */
1224 arc_get_disassembler (void *ptr
)
1227 build_ARC_extmap ((struct bfd
*) ptr
);