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Add support for the WebAssembly file format and the wasm32 ELF conversion to gas...
[deliverable/binutils-gdb.git] / opcodes / arc-opc.c
1 /* Opcode table for the ARC.
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software Foundation,
20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
21
22 #include "sysdep.h"
23 #include <stdio.h>
24 #include "bfd.h"
25 #include "opcode/arc.h"
26 #include "opintl.h"
27 #include "libiberty.h"
28
29 /* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
30 instructions. All NPS400 features are built into all ARC target builds as
31 this reduces the chances that regressions might creep in. */
32
33 /* Insert RA register into a 32-bit opcode, with checks. */
34
35 static unsigned long long
36 insert_ra_chk (unsigned long long insn,
37 long long value,
38 const char ** errmsg)
39 {
40 if (value == 60)
41 *errmsg = _("LP_COUNT register cannot be used as destination register");
42
43 return insn | (value & 0x3F);
44 }
45
46 /* Insert RB register into a 32-bit opcode. */
47
48 static unsigned long long
49 insert_rb (unsigned long long insn,
50 long long value,
51 const char ** errmsg ATTRIBUTE_UNUSED)
52 {
53 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
54 }
55
56 /* Insert RB register with checks. */
57
58 static unsigned long long
59 insert_rb_chk (unsigned long long insn,
60 long long value,
61 const char ** errmsg)
62 {
63 if (value == 60)
64 *errmsg = _("LP_COUNT register cannot be used as destination register");
65
66 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
67 }
68
69 static long long
70 extract_rb (unsigned long long insn,
71 bfd_boolean * invalid)
72 {
73 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
74
75 if (value == 0x3e && invalid)
76 *invalid = TRUE; /* A limm operand, it should be extracted in a
77 different way. */
78
79 return value;
80 }
81
82 static unsigned long long
83 insert_rad (unsigned long long insn,
84 long long value,
85 const char ** errmsg)
86 {
87 if (value & 0x01)
88 *errmsg = _("cannot use odd number destination register");
89 if (value == 60)
90 *errmsg = _("LP_COUNT register cannot be used as destination register");
91
92 return insn | (value & 0x3F);
93 }
94
95 static unsigned long long
96 insert_rcd (unsigned long long insn,
97 long long value,
98 const char ** errmsg)
99 {
100 if (value & 0x01)
101 *errmsg = _("cannot use odd number source register");
102
103 return insn | ((value & 0x3F) << 6);
104 }
105
106 /* Dummy insert ZERO operand function. */
107
108 static unsigned long long
109 insert_za (unsigned long long insn,
110 long long value,
111 const char ** errmsg)
112 {
113 if (value)
114 *errmsg = _("operand is not zero");
115 return insn;
116 }
117
118 /* Insert Y-bit in bbit/br instructions. This function is called only
119 when solving fixups. */
120
121 static unsigned long long
122 insert_Ybit (unsigned long long insn,
123 long long value,
124 const char ** errmsg ATTRIBUTE_UNUSED)
125 {
126 if (value > 0)
127 insn |= 0x08;
128
129 return insn;
130 }
131
132 /* Insert Y-bit in bbit/br instructions. This function is called only
133 when solving fixups. */
134
135 static unsigned long long
136 insert_NYbit (unsigned long long insn,
137 long long value,
138 const char ** errmsg ATTRIBUTE_UNUSED)
139 {
140 if (value < 0)
141 insn |= 0x08;
142
143 return insn;
144 }
145
146 /* Insert H register into a 16-bit opcode. */
147
148 static unsigned long long
149 insert_rhv1 (unsigned long long insn,
150 long long value,
151 const char ** errmsg ATTRIBUTE_UNUSED)
152 {
153 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
154 }
155
156 static long long
157 extract_rhv1 (unsigned long long insn,
158 bfd_boolean * invalid ATTRIBUTE_UNUSED)
159 {
160 int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7);
161
162 return value;
163 }
164
165 /* Insert H register into a 16-bit opcode. */
166
167 static unsigned long long
168 insert_rhv2 (unsigned long long insn,
169 long long value,
170 const char ** errmsg)
171 {
172 if (value == 0x1E)
173 *errmsg = _("Register R30 is a limm indicator");
174 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
175 }
176
177 static long long
178 extract_rhv2 (unsigned long long insn,
179 bfd_boolean * invalid ATTRIBUTE_UNUSED)
180 {
181 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
182
183 return value;
184 }
185
186 static unsigned long long
187 insert_r0 (unsigned long long insn,
188 long long value,
189 const char ** errmsg)
190 {
191 if (value != 0)
192 *errmsg = _("Register must be R0");
193 return insn;
194 }
195
196 static long long
197 extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED,
198 bfd_boolean * invalid ATTRIBUTE_UNUSED)
199 {
200 return 0;
201 }
202
203
204 static unsigned long long
205 insert_r1 (unsigned long long insn,
206 long long value,
207 const char ** errmsg)
208 {
209 if (value != 1)
210 *errmsg = _("Register must be R1");
211 return insn;
212 }
213
214 static long long
215 extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED,
216 bfd_boolean * invalid ATTRIBUTE_UNUSED)
217 {
218 return 1;
219 }
220
221 static unsigned long long
222 insert_r2 (unsigned long long insn,
223 long long value,
224 const char ** errmsg)
225 {
226 if (value != 2)
227 *errmsg = _("Register must be R2");
228 return insn;
229 }
230
231 static long long
232 extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED,
233 bfd_boolean * invalid ATTRIBUTE_UNUSED)
234 {
235 return 2;
236 }
237
238 static unsigned long long
239 insert_r3 (unsigned long long insn,
240 long long value,
241 const char ** errmsg)
242 {
243 if (value != 3)
244 *errmsg = _("Register must be R3");
245 return insn;
246 }
247
248 static long long
249 extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED,
250 bfd_boolean * invalid ATTRIBUTE_UNUSED)
251 {
252 return 3;
253 }
254
255 static unsigned long long
256 insert_sp (unsigned long long insn,
257 long long value,
258 const char ** errmsg)
259 {
260 if (value != 28)
261 *errmsg = _("Register must be SP");
262 return insn;
263 }
264
265 static long long
266 extract_sp (unsigned long long insn ATTRIBUTE_UNUSED,
267 bfd_boolean * invalid ATTRIBUTE_UNUSED)
268 {
269 return 28;
270 }
271
272 static unsigned long long
273 insert_gp (unsigned long long insn,
274 long long value,
275 const char ** errmsg)
276 {
277 if (value != 26)
278 *errmsg = _("Register must be GP");
279 return insn;
280 }
281
282 static long long
283 extract_gp (unsigned long long insn ATTRIBUTE_UNUSED,
284 bfd_boolean * invalid ATTRIBUTE_UNUSED)
285 {
286 return 26;
287 }
288
289 static unsigned long long
290 insert_pcl (unsigned long long insn,
291 long long value,
292 const char ** errmsg)
293 {
294 if (value != 63)
295 *errmsg = _("Register must be PCL");
296 return insn;
297 }
298
299 static long long
300 extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED,
301 bfd_boolean * invalid ATTRIBUTE_UNUSED)
302 {
303 return 63;
304 }
305
306 static unsigned long long
307 insert_blink (unsigned long long insn,
308 long long value,
309 const char ** errmsg)
310 {
311 if (value != 31)
312 *errmsg = _("Register must be BLINK");
313 return insn;
314 }
315
316 static long long
317 extract_blink (unsigned long long insn ATTRIBUTE_UNUSED,
318 bfd_boolean * invalid ATTRIBUTE_UNUSED)
319 {
320 return 31;
321 }
322
323 static unsigned long long
324 insert_ilink1 (unsigned long long insn,
325 long long value,
326 const char ** errmsg)
327 {
328 if (value != 29)
329 *errmsg = _("Register must be ILINK1");
330 return insn;
331 }
332
333 static long long
334 extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED,
335 bfd_boolean * invalid ATTRIBUTE_UNUSED)
336 {
337 return 29;
338 }
339
340 static unsigned long long
341 insert_ilink2 (unsigned long long insn,
342 long long value,
343 const char ** errmsg)
344 {
345 if (value != 30)
346 *errmsg = _("Register must be ILINK2");
347 return insn;
348 }
349
350 static long long
351 extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED,
352 bfd_boolean * invalid ATTRIBUTE_UNUSED)
353 {
354 return 30;
355 }
356
357 static unsigned long long
358 insert_ras (unsigned long long insn,
359 long long value,
360 const char ** errmsg)
361 {
362 switch (value)
363 {
364 case 0:
365 case 1:
366 case 2:
367 case 3:
368 insn |= value;
369 break;
370 case 12:
371 case 13:
372 case 14:
373 case 15:
374 insn |= (value - 8);
375 break;
376 default:
377 *errmsg = _("Register must be either r0-r3 or r12-r15");
378 break;
379 }
380 return insn;
381 }
382
383 static long long
384 extract_ras (unsigned long long insn,
385 bfd_boolean * invalid ATTRIBUTE_UNUSED)
386 {
387 int value = insn & 0x07;
388
389 if (value > 3)
390 return (value + 8);
391 else
392 return value;
393 }
394
395 static unsigned long long
396 insert_rbs (unsigned long long insn,
397 long long value,
398 const char ** errmsg)
399 {
400 switch (value)
401 {
402 case 0:
403 case 1:
404 case 2:
405 case 3:
406 insn |= value << 8;
407 break;
408 case 12:
409 case 13:
410 case 14:
411 case 15:
412 insn |= ((value - 8)) << 8;
413 break;
414 default:
415 *errmsg = _("Register must be either r0-r3 or r12-r15");
416 break;
417 }
418 return insn;
419 }
420
421 static long long
422 extract_rbs (unsigned long long insn,
423 bfd_boolean * invalid ATTRIBUTE_UNUSED)
424 {
425 int value = (insn >> 8) & 0x07;
426
427 if (value > 3)
428 return (value + 8);
429 else
430 return value;
431 }
432
433 static unsigned long long
434 insert_rcs (unsigned long long insn,
435 long long value,
436 const char ** errmsg)
437 {
438 switch (value)
439 {
440 case 0:
441 case 1:
442 case 2:
443 case 3:
444 insn |= value << 5;
445 break;
446 case 12:
447 case 13:
448 case 14:
449 case 15:
450 insn |= ((value - 8)) << 5;
451 break;
452 default:
453 *errmsg = _("Register must be either r0-r3 or r12-r15");
454 break;
455 }
456 return insn;
457 }
458
459 static long long
460 extract_rcs (unsigned long long insn,
461 bfd_boolean * invalid ATTRIBUTE_UNUSED)
462 {
463 int value = (insn >> 5) & 0x07;
464
465 if (value > 3)
466 return (value + 8);
467 else
468 return value;
469 }
470
471 static unsigned long long
472 insert_simm3s (unsigned long long insn,
473 long long value,
474 const char ** errmsg)
475 {
476 int tmp = 0;
477 switch (value)
478 {
479 case -1:
480 tmp = 0x07;
481 break;
482 case 0:
483 tmp = 0x00;
484 break;
485 case 1:
486 tmp = 0x01;
487 break;
488 case 2:
489 tmp = 0x02;
490 break;
491 case 3:
492 tmp = 0x03;
493 break;
494 case 4:
495 tmp = 0x04;
496 break;
497 case 5:
498 tmp = 0x05;
499 break;
500 case 6:
501 tmp = 0x06;
502 break;
503 default:
504 *errmsg = _("Accepted values are from -1 to 6");
505 break;
506 }
507
508 insn |= tmp << 8;
509 return insn;
510 }
511
512 static long long
513 extract_simm3s (unsigned long long insn,
514 bfd_boolean * invalid ATTRIBUTE_UNUSED)
515 {
516 int value = (insn >> 8) & 0x07;
517
518 if (value == 7)
519 return -1;
520 else
521 return value;
522 }
523
524 static unsigned long long
525 insert_rrange (unsigned long long insn,
526 long long value,
527 const char ** errmsg)
528 {
529 int reg1 = (value >> 16) & 0xFFFF;
530 int reg2 = value & 0xFFFF;
531
532 if (reg1 != 13)
533 *errmsg = _("First register of the range should be r13");
534 else if (reg2 < 13 || reg2 > 26)
535 *errmsg = _("Last register of the range doesn't fit");
536 else
537 insn |= ((reg2 - 12) & 0x0F) << 1;
538 return insn;
539 }
540
541 static long long
542 extract_rrange (unsigned long long insn,
543 bfd_boolean * invalid ATTRIBUTE_UNUSED)
544 {
545 return (insn >> 1) & 0x0F;
546 }
547
548 static unsigned long long
549 insert_fpel (unsigned long long insn,
550 long long value,
551 const char ** errmsg)
552 {
553 if (value != 27)
554 {
555 *errmsg = _("Invalid register number, should be fp");
556 return insn;
557 }
558
559 insn |= 0x0100;
560 return insn;
561 }
562
563 static long long
564 extract_fpel (unsigned long long insn,
565 bfd_boolean * invalid ATTRIBUTE_UNUSED)
566 {
567 return (insn & 0x0100) ? 27 : -1;
568 }
569
570 static unsigned long long
571 insert_blinkel (unsigned long long insn,
572 long long value,
573 const char ** errmsg)
574 {
575 if (value != 31)
576 {
577 *errmsg = _("Invalid register number, should be blink");
578 return insn;
579 }
580
581 insn |= 0x0200;
582 return insn;
583 }
584
585 static long long
586 extract_blinkel (unsigned long long insn,
587 bfd_boolean * invalid ATTRIBUTE_UNUSED)
588 {
589 return (insn & 0x0200) ? 31 : -1;
590 }
591
592 static unsigned long long
593 insert_pclel (unsigned long long insn,
594 long long value,
595 const char ** errmsg)
596 {
597 if (value != 63)
598 {
599 *errmsg = _("Invalid register number, should be pcl");
600 return insn;
601 }
602
603 insn |= 0x0400;
604 return insn;
605 }
606
607 static long long
608 extract_pclel (unsigned long long insn,
609 bfd_boolean * invalid ATTRIBUTE_UNUSED)
610 {
611 return (insn & 0x0400) ? 63 : -1;
612 }
613
614 #define INSERT_W6
615
616 /* mask = 00000000000000000000111111000000
617 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
618
619 static unsigned long long
620 insert_w6 (unsigned long long insn,
621 long long value,
622 const char ** errmsg ATTRIBUTE_UNUSED)
623 {
624 insn |= ((value >> 0) & 0x003f) << 6;
625
626 return insn;
627 }
628
629 #define EXTRACT_W6
630
631 /* mask = 00000000000000000000111111000000. */
632
633 static long long
634 extract_w6 (unsigned long long insn,
635 bfd_boolean * invalid ATTRIBUTE_UNUSED)
636 {
637 unsigned value = 0;
638
639 value |= ((insn >> 6) & 0x003f) << 0;
640
641 return value;
642 }
643
644 #define INSERT_G_S
645
646 /* mask = 0000011100022000
647 insn = 01000ggghhhGG0HH. */
648
649 static unsigned long long
650 insert_g_s (unsigned long long insn,
651 long long value,
652 const char ** errmsg ATTRIBUTE_UNUSED)
653 {
654 insn |= ((value >> 0) & 0x0007) << 8;
655 insn |= ((value >> 3) & 0x0003) << 3;
656
657 return insn;
658 }
659
660 #define EXTRACT_G_S
661
662 /* mask = 0000011100022000. */
663
664 static long long
665 extract_g_s (unsigned long long insn,
666 bfd_boolean * invalid ATTRIBUTE_UNUSED)
667 {
668 int value = 0;
669 int signbit = 1 << (6 - 1);
670
671 value |= ((insn >> 8) & 0x0007) << 0;
672 value |= ((insn >> 3) & 0x0003) << 3;
673
674 /* Extend the sign. */
675 value = (value ^ signbit) - signbit;
676
677 return value;
678 }
679
680 /* ARC NPS400 Support: See comment near head of file. */
681 #define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \
682 static unsigned long long \
683 insert_nps_3bit_reg_at_##OFFSET##_##NAME \
684 (unsigned long long insn, \
685 long long value, \
686 const char ** errmsg) \
687 { \
688 switch (value) \
689 { \
690 case 0: \
691 case 1: \
692 case 2: \
693 case 3: \
694 insn |= value << (OFFSET); \
695 break; \
696 case 12: \
697 case 13: \
698 case 14: \
699 case 15: \
700 insn |= (value - 8) << (OFFSET); \
701 break; \
702 default: \
703 *errmsg = _("Register must be either r0-r3 or r12-r15"); \
704 break; \
705 } \
706 return insn; \
707 } \
708 \
709 static long long \
710 extract_nps_3bit_reg_at_##OFFSET##_##NAME \
711 (unsigned long long insn, \
712 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
713 { \
714 int value = (insn >> (OFFSET)) & 0x07; \
715 if (value > 3) \
716 value += 8; \
717 return value; \
718 } \
719
720 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,8)
721 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,24)
722 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,40)
723 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,56)
724
725 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,5)
726 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,21)
727 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,37)
728 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,53)
729
730 static unsigned long long
731 insert_nps_bitop_size_2b (unsigned long long insn,
732 long long value,
733 const char ** errmsg)
734 {
735 switch (value)
736 {
737 case 1:
738 value = 0;
739 break;
740 case 2:
741 value = 1;
742 break;
743 case 4:
744 value = 2;
745 break;
746 case 8:
747 value = 3;
748 break;
749 default:
750 value = 0;
751 *errmsg = _("Invalid size, should be 1, 2, 4, or 8");
752 break;
753 }
754
755 insn |= value << 10;
756 return insn;
757 }
758
759 static long long
760 extract_nps_bitop_size_2b (unsigned long long insn,
761 bfd_boolean * invalid ATTRIBUTE_UNUSED)
762 {
763 return 1 << ((insn >> 10) & 0x3);
764 }
765
766 static unsigned long long
767 insert_nps_bitop_uimm8 (unsigned long long insn,
768 long long value,
769 const char ** errmsg ATTRIBUTE_UNUSED)
770 {
771 insn |= ((value >> 5) & 7) << 12;
772 insn |= (value & 0x1f);
773 return insn;
774 }
775
776 static long long
777 extract_nps_bitop_uimm8 (unsigned long long insn,
778 bfd_boolean * invalid ATTRIBUTE_UNUSED)
779 {
780 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
781 }
782
783 static unsigned long long
784 insert_nps_rflt_uimm6 (unsigned long long insn,
785 long long value,
786 const char ** errmsg)
787 {
788 switch (value)
789 {
790 case 1:
791 case 2:
792 case 4:
793 break;
794
795 default:
796 *errmsg = _("invalid immediate, must be 1, 2, or 4");
797 value = 0;
798 }
799
800 insn |= (value << 6);
801 return insn;
802 }
803
804 static long long
805 extract_nps_rflt_uimm6 (unsigned long long insn,
806 bfd_boolean * invalid ATTRIBUTE_UNUSED)
807 {
808 return (insn >> 6) & 0x3f;
809 }
810
811 static unsigned long long
812 insert_nps_dst_pos_and_size (unsigned long long insn,
813 long long value,
814 const char ** errmsg ATTRIBUTE_UNUSED)
815 {
816 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
817 return insn;
818 }
819
820 static long long
821 extract_nps_dst_pos_and_size (unsigned long long insn,
822 bfd_boolean * invalid ATTRIBUTE_UNUSED)
823 {
824 return (insn & 0x1f);
825 }
826
827 static unsigned long long
828 insert_nps_cmem_uimm16 (unsigned long long insn,
829 long long value,
830 const char ** errmsg)
831 {
832 int top = (value >> 16) & 0xffff;
833
834 if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
835 *errmsg = _("invalid value for CMEM ld/st immediate");
836 insn |= (value & 0xffff);
837 return insn;
838 }
839
840 static long long
841 extract_nps_cmem_uimm16 (unsigned long long insn,
842 bfd_boolean * invalid ATTRIBUTE_UNUSED)
843 {
844 return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
845 }
846
847 static unsigned long long
848 insert_nps_imm_offset (unsigned long long insn,
849 long long value,
850 const char ** errmsg)
851 {
852 switch (value)
853 {
854 case 0:
855 case 16:
856 case 32:
857 case 48:
858 case 64:
859 value = value >> 4;
860 break;
861 default:
862 *errmsg = _("Invalid position, should be 0, 16, 32, 48 or 64.");
863 value = 0;
864 }
865 insn |= (value << 10);
866 return insn;
867 }
868
869 static long long
870 extract_nps_imm_offset (unsigned long long insn,
871 bfd_boolean * invalid ATTRIBUTE_UNUSED)
872 {
873 return ((insn >> 10) & 0x7) * 16;
874 }
875
876 static unsigned long long
877 insert_nps_imm_entry (unsigned long long insn,
878 long long value,
879 const char ** errmsg)
880 {
881 switch (value)
882 {
883 case 16:
884 value = 0;
885 break;
886 case 32:
887 value = 1;
888 break;
889 case 64:
890 value = 2;
891 break;
892 case 128:
893 value = 3;
894 break;
895 default:
896 *errmsg = _("Invalid position, should be 16, 32, 64 or 128.");
897 value = 0;
898 }
899 insn |= (value << 2);
900 return insn;
901 }
902
903 static long long
904 extract_nps_imm_entry (unsigned long long insn,
905 bfd_boolean * invalid ATTRIBUTE_UNUSED)
906 {
907 int imm_entry = ((insn >> 2) & 0x7);
908 return (1 << (imm_entry + 4));
909 }
910
911 static unsigned long long
912 insert_nps_size_16bit (unsigned long long insn,
913 long long value,
914 const char ** errmsg)
915 {
916 if ((value < 1) || (value > 64))
917 {
918 *errmsg = _("Invalid size value must be on range 1-64.");
919 value = 0;
920 }
921 value = value & 0x3f;
922 insn |= (value << 6);
923 return insn;
924 }
925
926 static long long
927 extract_nps_size_16bit (unsigned long long insn,
928 bfd_boolean * invalid ATTRIBUTE_UNUSED)
929 {
930 return ((insn & 0xfc0) >> 6) ? ((insn & 0xfc0) >> 6) : 64;
931 }
932
933
934 #define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
935 static unsigned long long \
936 insert_nps_##NAME##_pos (unsigned long long insn, \
937 long long value, \
938 const char ** errmsg) \
939 { \
940 switch (value) \
941 { \
942 case 0: \
943 case 8: \
944 case 16: \
945 case 24: \
946 value = value / 8; \
947 break; \
948 default: \
949 *errmsg = _("Invalid position, should be 0, 8, 16, or 24"); \
950 value = 0; \
951 } \
952 insn |= (value << SHIFT); \
953 return insn; \
954 } \
955 \
956 static long long \
957 extract_nps_##NAME##_pos (unsigned long long insn, \
958 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
959 { \
960 return ((insn >> SHIFT) & 0x3) * 8; \
961 }
962
963 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
964 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
965
966 #define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT) \
967 static unsigned long long \
968 insert_nps_##NAME (unsigned long long insn, \
969 long long value, \
970 const char ** errmsg) \
971 { \
972 if (value < LOWER || value > UPPER) \
973 { \
974 *errmsg = _("Invalid size, value must be " \
975 #LOWER " to " #UPPER "."); \
976 return insn; \
977 } \
978 value -= BIAS; \
979 insn |= (value << SHIFT); \
980 return insn; \
981 } \
982 \
983 static long long \
984 extract_nps_##NAME (unsigned long long insn, \
985 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
986 { \
987 return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
988 }
989
990 MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5)
991 MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5)
992 MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5)
993 MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5)
994 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10)
995 MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9)
996 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20)
997 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25)
998 MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6)
999 MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2)
1000 MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0)
1001
1002 static long long
1003 extract_nps_qcmp_m3 (unsigned long long insn,
1004 bfd_boolean * invalid)
1005 {
1006 int m3 = (insn >> 5) & 0xf;
1007 if (m3 == 0xf)
1008 *invalid = TRUE;
1009 return m3;
1010 }
1011
1012 static long long
1013 extract_nps_qcmp_m2 (unsigned long long insn,
1014 bfd_boolean * invalid)
1015 {
1016 bfd_boolean tmp_invalid = FALSE;
1017 int m2 = (insn >> 15) & 0x1;
1018 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
1019
1020 if (m2 == 0 && m3 == 0xf)
1021 *invalid = TRUE;
1022 return m2;
1023 }
1024
1025 static long long
1026 extract_nps_qcmp_m1 (unsigned long long insn,
1027 bfd_boolean * invalid)
1028 {
1029 bfd_boolean tmp_invalid = FALSE;
1030 int m1 = (insn >> 14) & 0x1;
1031 int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
1032 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
1033
1034 if (m1 == 0 && m2 == 0 && m3 == 0xf)
1035 *invalid = TRUE;
1036 return m1;
1037 }
1038
1039 static unsigned long long
1040 insert_nps_calc_entry_size (unsigned long long insn,
1041 long long value,
1042 const char ** errmsg)
1043 {
1044 unsigned pwr;
1045
1046 if (value < 1 || value > 256)
1047 {
1048 *errmsg = _("value out of range 1 - 256");
1049 return 0;
1050 }
1051
1052 for (pwr = 0; (value & 1) == 0; value >>= 1)
1053 ++pwr;
1054
1055 if (value != 1)
1056 {
1057 *errmsg = _("value must be power of 2");
1058 return 0;
1059 }
1060
1061 return insn | (pwr << 8);
1062 }
1063
1064 static long long
1065 extract_nps_calc_entry_size (unsigned long long insn,
1066 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1067 {
1068 unsigned entry_size = (insn >> 8) & 0xf;
1069 return 1 << entry_size;
1070 }
1071
1072 static unsigned long long
1073 insert_nps_bitop_mod4 (unsigned long long insn,
1074 long long value,
1075 const char ** errmsg ATTRIBUTE_UNUSED)
1076 {
1077 return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47);
1078 }
1079
1080 static long long
1081 extract_nps_bitop_mod4 (unsigned long long insn,
1082 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1083 {
1084 return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1);
1085 }
1086
1087 static unsigned long long
1088 insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
1089 long long value,
1090 const char ** errmsg ATTRIBUTE_UNUSED)
1091 {
1092 return insn | (value << 42) | (value << 37);
1093 }
1094
1095 static long long
1096 extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
1097 bfd_boolean * invalid)
1098 {
1099 if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f))
1100 *invalid = TRUE;
1101 return ((insn >> 37) & 0x1f);
1102 }
1103
1104 static unsigned long long
1105 insert_nps_bitop_ins_ext (unsigned long long insn,
1106 long long value,
1107 const char ** errmsg)
1108 {
1109 if (value < 0 || value > 28)
1110 *errmsg = _("Value must be in the range 0 to 28");
1111 return insn | (value << 20);
1112 }
1113
1114 static long long
1115 extract_nps_bitop_ins_ext (unsigned long long insn,
1116 bfd_boolean * invalid)
1117 {
1118 int value = (insn >> 20) & 0x1f;
1119
1120 if (value > 28)
1121 *invalid = TRUE;
1122 return value;
1123 }
1124
1125 #define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \
1126 static unsigned long long \
1127 insert_nps_##NAME (unsigned long long insn, \
1128 long long value, \
1129 const char ** errmsg) \
1130 { \
1131 if (value < 1 || value > UPPER) \
1132 *errmsg = _("Value must be in the range 1 to " #UPPER); \
1133 if (value == UPPER) \
1134 value = 0; \
1135 return insn | (value << SHIFT); \
1136 } \
1137 \
1138 static long long \
1139 extract_nps_##NAME (unsigned long long insn, \
1140 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1141 { \
1142 int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
1143 if (value == 0) \
1144 value = UPPER; \
1145 return value; \
1146 }
1147
1148 MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3)
1149 MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3)
1150 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3)
1151 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8)
1152 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3)
1153 MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2)
1154 MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6)
1155
1156 static unsigned long long
1157 insert_nps_min_hofs (unsigned long long insn,
1158 long long value,
1159 const char ** errmsg)
1160 {
1161 if (value < 0 || value > 240)
1162 *errmsg = _("Value must be in the range 0 to 240");
1163 if ((value % 16) != 0)
1164 *errmsg = _("Value must be a multiple of 16");
1165 value = value / 16;
1166 return insn | (value << 6);
1167 }
1168
1169 static long long
1170 extract_nps_min_hofs (unsigned long long insn,
1171 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1172 {
1173 int value = (insn >> 6) & 0xF;
1174 return value * 16;
1175 }
1176
1177 #define MAKE_INSERT_NPS_ADDRTYPE(NAME, VALUE) \
1178 static unsigned long long \
1179 insert_nps_##NAME (unsigned long long insn, \
1180 long long value, \
1181 const char ** errmsg) \
1182 { \
1183 if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
1184 *errmsg = _("Invalid address type for operand"); \
1185 return insn; \
1186 } \
1187 \
1188 static long long \
1189 extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1190 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1191 { \
1192 return ARC_NPS400_ADDRTYPE_##VALUE; \
1193 }
1194
1195 MAKE_INSERT_NPS_ADDRTYPE (bd, BD)
1196 MAKE_INSERT_NPS_ADDRTYPE (jid, JID)
1197 MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD)
1198 MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD)
1199 MAKE_INSERT_NPS_ADDRTYPE (sd, SD)
1200 MAKE_INSERT_NPS_ADDRTYPE (sm, SM)
1201 MAKE_INSERT_NPS_ADDRTYPE (xa, XA)
1202 MAKE_INSERT_NPS_ADDRTYPE (xd, XD)
1203 MAKE_INSERT_NPS_ADDRTYPE (cd, CD)
1204 MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD)
1205 MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID)
1206 MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD)
1207 MAKE_INSERT_NPS_ADDRTYPE (cm, CM)
1208 MAKE_INSERT_NPS_ADDRTYPE (csd, CSD)
1209 MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA)
1210 MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD)
1211
1212 static unsigned long long
1213 insert_nps_rbdouble_64 (unsigned long long insn,
1214 long long value,
1215 const char ** errmsg)
1216 {
1217 if (value < 0 || value > 31)
1218 *errmsg = _("Value must be in the range 0 to 31");
1219 return insn | (value << 43) | (value << 48);
1220 }
1221
1222
1223 static long long
1224 extract_nps_rbdouble_64 (unsigned long long insn,
1225 bfd_boolean * invalid)
1226 {
1227 int value1 = (insn >> 43) & 0x1F;
1228 int value2 = (insn >> 48) & 0x1F;
1229
1230 if (value1 != value2)
1231 *invalid = TRUE;
1232
1233 return value1;
1234 }
1235
1236 static unsigned long long
1237 insert_nps_misc_imm_offset (unsigned long long insn,
1238 long long value,
1239 const char ** errmsg)
1240 {
1241 if (value & 0x3)
1242 {
1243 *errmsg = _("Invalid position, should be 0,4, 8,...124.");
1244 value = 0;
1245 }
1246 insn |= (value << 6);
1247 return insn;
1248 }
1249
1250 static long long int
1251 extract_nps_misc_imm_offset (unsigned long long insn,
1252 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1253 {
1254 return ((insn >> 8) & 0x1f) * 4;
1255 }
1256
1257 /* Include the generic extract/insert functions. Order is important
1258 as some of the functions present in the .h may be disabled via
1259 defines. */
1260 #include "arc-fxi.h"
1261
1262 /* The flag operands table.
1263
1264 The format of the table is
1265 NAME CODE BITS SHIFT FAVAIL. */
1266 const struct arc_flag_operand arc_flag_operands[] =
1267 {
1268 #define F_NULL 0
1269 { 0, 0, 0, 0, 0},
1270 #define F_ALWAYS (F_NULL + 1)
1271 { "al", 0, 0, 0, 0 },
1272 #define F_RA (F_ALWAYS + 1)
1273 { "ra", 0, 0, 0, 0 },
1274 #define F_EQUAL (F_RA + 1)
1275 { "eq", 1, 5, 0, 1 },
1276 #define F_ZERO (F_EQUAL + 1)
1277 { "z", 1, 5, 0, 0 },
1278 #define F_NOTEQUAL (F_ZERO + 1)
1279 { "ne", 2, 5, 0, 1 },
1280 #define F_NOTZERO (F_NOTEQUAL + 1)
1281 { "nz", 2, 5, 0, 0 },
1282 #define F_POZITIVE (F_NOTZERO + 1)
1283 { "p", 3, 5, 0, 1 },
1284 #define F_PL (F_POZITIVE + 1)
1285 { "pl", 3, 5, 0, 0 },
1286 #define F_NEGATIVE (F_PL + 1)
1287 { "n", 4, 5, 0, 1 },
1288 #define F_MINUS (F_NEGATIVE + 1)
1289 { "mi", 4, 5, 0, 0 },
1290 #define F_CARRY (F_MINUS + 1)
1291 { "c", 5, 5, 0, 1 },
1292 #define F_CARRYSET (F_CARRY + 1)
1293 { "cs", 5, 5, 0, 0 },
1294 #define F_LOWER (F_CARRYSET + 1)
1295 { "lo", 5, 5, 0, 0 },
1296 #define F_CARRYCLR (F_LOWER + 1)
1297 { "cc", 6, 5, 0, 0 },
1298 #define F_NOTCARRY (F_CARRYCLR + 1)
1299 { "nc", 6, 5, 0, 1 },
1300 #define F_HIGHER (F_NOTCARRY + 1)
1301 { "hs", 6, 5, 0, 0 },
1302 #define F_OVERFLOWSET (F_HIGHER + 1)
1303 { "vs", 7, 5, 0, 0 },
1304 #define F_OVERFLOW (F_OVERFLOWSET + 1)
1305 { "v", 7, 5, 0, 1 },
1306 #define F_NOTOVERFLOW (F_OVERFLOW + 1)
1307 { "nv", 8, 5, 0, 1 },
1308 #define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
1309 { "vc", 8, 5, 0, 0 },
1310 #define F_GT (F_OVERFLOWCLR + 1)
1311 { "gt", 9, 5, 0, 1 },
1312 #define F_GE (F_GT + 1)
1313 { "ge", 10, 5, 0, 1 },
1314 #define F_LT (F_GE + 1)
1315 { "lt", 11, 5, 0, 1 },
1316 #define F_LE (F_LT + 1)
1317 { "le", 12, 5, 0, 1 },
1318 #define F_HI (F_LE + 1)
1319 { "hi", 13, 5, 0, 1 },
1320 #define F_LS (F_HI + 1)
1321 { "ls", 14, 5, 0, 1 },
1322 #define F_PNZ (F_LS + 1)
1323 { "pnz", 15, 5, 0, 1 },
1324 #define F_NJ (F_PNZ + 1)
1325 { "nj", 21, 5, 0, 1 },
1326 #define F_NM (F_NJ + 1)
1327 { "nm", 23, 5, 0, 1 },
1328 #define F_NO_T (F_NM + 1)
1329 { "nt", 24, 5, 0, 1 },
1330
1331 /* FLAG. */
1332 #define F_FLAG (F_NO_T + 1)
1333 { "f", 1, 1, 15, 1 },
1334 #define F_FFAKE (F_FLAG + 1)
1335 { "f", 0, 0, 0, 1 },
1336
1337 /* Delay slot. */
1338 #define F_ND (F_FFAKE + 1)
1339 { "nd", 0, 1, 5, 0 },
1340 #define F_D (F_ND + 1)
1341 { "d", 1, 1, 5, 1 },
1342 #define F_DFAKE (F_D + 1)
1343 { "d", 0, 0, 0, 1 },
1344 #define F_DNZ_ND (F_DFAKE + 1)
1345 { "nd", 0, 1, 16, 0 },
1346 #define F_DNZ_D (F_DNZ_ND + 1)
1347 { "d", 1, 1, 16, 1 },
1348
1349 /* Data size. */
1350 #define F_SIZEB1 (F_DNZ_D + 1)
1351 { "b", 1, 2, 1, 1 },
1352 #define F_SIZEB7 (F_SIZEB1 + 1)
1353 { "b", 1, 2, 7, 1 },
1354 #define F_SIZEB17 (F_SIZEB7 + 1)
1355 { "b", 1, 2, 17, 1 },
1356 #define F_SIZEW1 (F_SIZEB17 + 1)
1357 { "w", 2, 2, 1, 0 },
1358 #define F_SIZEW7 (F_SIZEW1 + 1)
1359 { "w", 2, 2, 7, 0 },
1360 #define F_SIZEW17 (F_SIZEW7 + 1)
1361 { "w", 2, 2, 17, 0 },
1362
1363 /* Sign extension. */
1364 #define F_SIGN6 (F_SIZEW17 + 1)
1365 { "x", 1, 1, 6, 1 },
1366 #define F_SIGN16 (F_SIGN6 + 1)
1367 { "x", 1, 1, 16, 1 },
1368 #define F_SIGNX (F_SIGN16 + 1)
1369 { "x", 0, 0, 0, 1 },
1370
1371 /* Address write-back modes. */
1372 #define F_A3 (F_SIGNX + 1)
1373 { "a", 1, 2, 3, 0 },
1374 #define F_A9 (F_A3 + 1)
1375 { "a", 1, 2, 9, 0 },
1376 #define F_A22 (F_A9 + 1)
1377 { "a", 1, 2, 22, 0 },
1378 #define F_AW3 (F_A22 + 1)
1379 { "aw", 1, 2, 3, 1 },
1380 #define F_AW9 (F_AW3 + 1)
1381 { "aw", 1, 2, 9, 1 },
1382 #define F_AW22 (F_AW9 + 1)
1383 { "aw", 1, 2, 22, 1 },
1384 #define F_AB3 (F_AW22 + 1)
1385 { "ab", 2, 2, 3, 1 },
1386 #define F_AB9 (F_AB3 + 1)
1387 { "ab", 2, 2, 9, 1 },
1388 #define F_AB22 (F_AB9 + 1)
1389 { "ab", 2, 2, 22, 1 },
1390 #define F_AS3 (F_AB22 + 1)
1391 { "as", 3, 2, 3, 1 },
1392 #define F_AS9 (F_AS3 + 1)
1393 { "as", 3, 2, 9, 1 },
1394 #define F_AS22 (F_AS9 + 1)
1395 { "as", 3, 2, 22, 1 },
1396 #define F_ASFAKE (F_AS22 + 1)
1397 { "as", 0, 0, 0, 1 },
1398
1399 /* Cache bypass. */
1400 #define F_DI5 (F_ASFAKE + 1)
1401 { "di", 1, 1, 5, 1 },
1402 #define F_DI11 (F_DI5 + 1)
1403 { "di", 1, 1, 11, 1 },
1404 #define F_DI14 (F_DI11 + 1)
1405 { "di", 1, 1, 14, 1 },
1406 #define F_DI15 (F_DI14 + 1)
1407 { "di", 1, 1, 15, 1 },
1408
1409 /* ARCv2 specific. */
1410 #define F_NT (F_DI15 + 1)
1411 { "nt", 0, 1, 3, 1},
1412 #define F_T (F_NT + 1)
1413 { "t", 1, 1, 3, 1},
1414 #define F_H1 (F_T + 1)
1415 { "h", 2, 2, 1, 1 },
1416 #define F_H7 (F_H1 + 1)
1417 { "h", 2, 2, 7, 1 },
1418 #define F_H17 (F_H7 + 1)
1419 { "h", 2, 2, 17, 1 },
1420 #define F_SIZED (F_H17 + 1)
1421 { "dd", 8, 0, 0, 0 }, /* Fake. */
1422
1423 /* Fake Flags. */
1424 #define F_NE (F_SIZED + 1)
1425 { "ne", 0, 0, 0, 1 },
1426
1427 /* ARC NPS400 Support: See comment near head of file. */
1428 #define F_NPS_CL (F_NE + 1)
1429 { "cl", 0, 0, 0, 1 },
1430
1431 #define F_NPS_NA (F_NPS_CL + 1)
1432 { "na", 1, 1, 9, 1 },
1433
1434 #define F_NPS_SR (F_NPS_NA + 1)
1435 { "s", 1, 1, 13, 1 },
1436
1437 #define F_NPS_M (F_NPS_SR + 1)
1438 { "m", 1, 1, 7, 1 },
1439
1440 #define F_NPS_FLAG (F_NPS_M + 1)
1441 { "f", 1, 1, 20, 1 },
1442
1443 #define F_NPS_R (F_NPS_FLAG + 1)
1444 { "r", 1, 1, 15, 1 },
1445
1446 #define F_NPS_RW (F_NPS_R + 1)
1447 { "rw", 0, 1, 7, 1 },
1448
1449 #define F_NPS_RD (F_NPS_RW + 1)
1450 { "rd", 1, 1, 7, 1 },
1451
1452 #define F_NPS_WFT (F_NPS_RD + 1)
1453 { "wft", 0, 0, 0, 1 },
1454
1455 #define F_NPS_IE1 (F_NPS_WFT + 1)
1456 { "ie1", 1, 2, 8, 1 },
1457
1458 #define F_NPS_IE2 (F_NPS_IE1 + 1)
1459 { "ie2", 2, 2, 8, 1 },
1460
1461 #define F_NPS_IE12 (F_NPS_IE2 + 1)
1462 { "ie12", 3, 2, 8, 1 },
1463
1464 #define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
1465 { "rd", 0, 1, 6, 1 },
1466
1467 #define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
1468 { "wr", 1, 1, 6, 1 },
1469
1470 #define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
1471 { "off", 0, 0, 0, 1 },
1472
1473 #define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
1474 { "restore", 0, 0, 0, 1 },
1475
1476 #define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
1477 { "sx", 1, 1, 14, 1 },
1478
1479 #define F_NPS_AR (F_NPS_SX + 1)
1480 { "ar", 0, 1, 0, 1 },
1481
1482 #define F_NPS_AL (F_NPS_AR + 1)
1483 { "al", 1, 1, 0, 1 },
1484
1485 #define F_NPS_S (F_NPS_AL + 1)
1486 { "s", 0, 0, 0, 1 },
1487
1488 #define F_NPS_ZNCV_RD (F_NPS_S + 1)
1489 { "rd", 0, 1, 15, 1 },
1490
1491 #define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1)
1492 { "wr", 1, 1, 15, 1 },
1493
1494 #define F_NPS_P0 (F_NPS_ZNCV_WR + 1)
1495 { "p0", 0, 0, 0, 1 },
1496
1497 #define F_NPS_P1 (F_NPS_P0 + 1)
1498 { "p1", 0, 0, 0, 1 },
1499
1500 #define F_NPS_P2 (F_NPS_P1 + 1)
1501 { "p2", 0, 0, 0, 1 },
1502
1503 #define F_NPS_P3 (F_NPS_P2 + 1)
1504 { "p3", 0, 0, 0, 1 },
1505
1506 #define F_NPS_LDBIT_DI (F_NPS_P3 + 1)
1507 { "di", 0, 0, 0, 1 },
1508
1509 #define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1)
1510 { "cl", 1, 1, 6, 1 },
1511
1512 #define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1)
1513 { "cl", 1, 1, 16, 1 },
1514
1515 #define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1)
1516 { "x2", 1, 2, 9, 1 },
1517
1518 #define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1)
1519 { "x2", 1, 2, 22, 1 },
1520
1521 #define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1)
1522 { "x4", 2, 2, 9, 1 },
1523
1524 #define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1)
1525 { "x4", 2, 2, 22, 1 },
1526
1527 #define F_NPS_CORE (F_NPS_LDBIT_X4_2 + 1)
1528 { "core", 1, 3, 6, 1 },
1529
1530 #define F_NPS_CLSR (F_NPS_CORE + 1)
1531 { "clsr", 2, 3, 6, 1 },
1532
1533 #define F_NPS_ALL (F_NPS_CLSR + 1)
1534 { "all", 3, 3, 6, 1 },
1535
1536 #define F_NPS_GIC (F_NPS_ALL + 1)
1537 { "gic", 4, 3, 6, 1 },
1538
1539 #define F_NPS_RSPI_GIC (F_NPS_GIC + 1)
1540 { "gic", 5, 3, 6, 1 },
1541 };
1542
1543 const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
1544
1545 /* Table of the flag classes.
1546
1547 The format of the table is
1548 CLASS {FLAG_CODE}. */
1549 const struct arc_flag_class arc_flag_classes[] =
1550 {
1551 #define C_EMPTY 0
1552 { F_CLASS_NONE, { F_NULL } },
1553
1554 #define C_CC_EQ (C_EMPTY + 1)
1555 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} },
1556
1557 #define C_CC_GE (C_CC_EQ + 1)
1558 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} },
1559
1560 #define C_CC_GT (C_CC_GE + 1)
1561 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} },
1562
1563 #define C_CC_HI (C_CC_GT + 1)
1564 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} },
1565
1566 #define C_CC_HS (C_CC_HI + 1)
1567 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} },
1568
1569 #define C_CC_LE (C_CC_HS + 1)
1570 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} },
1571
1572 #define C_CC_LO (C_CC_LE + 1)
1573 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} },
1574
1575 #define C_CC_LS (C_CC_LO + 1)
1576 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} },
1577
1578 #define C_CC_LT (C_CC_LS + 1)
1579 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} },
1580
1581 #define C_CC_NE (C_CC_LT + 1)
1582 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} },
1583
1584 #define C_AA_AB (C_CC_NE + 1)
1585 {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} },
1586
1587 #define C_AA_AW (C_AA_AB + 1)
1588 {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} },
1589
1590 #define C_ZZ_D (C_AA_AW + 1)
1591 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} },
1592
1593 #define C_ZZ_H (C_ZZ_D + 1)
1594 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} },
1595
1596 #define C_ZZ_B (C_ZZ_H + 1)
1597 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} },
1598
1599 #define C_CC (C_ZZ_B + 1)
1600 { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
1601 { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1602 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
1603 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1604 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
1605 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
1606 F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T, F_NULL } },
1607
1608 #define C_AA_ADDR3 (C_CC + 1)
1609 #define C_AA27 (C_CC + 1)
1610 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
1611 #define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1612 #define C_AA21 (C_AA_ADDR3 + 1)
1613 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
1614 #define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1615 #define C_AA8 (C_AA_ADDR9 + 1)
1616 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
1617
1618 #define C_F (C_AA_ADDR22 + 1)
1619 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
1620 #define C_FHARD (C_F + 1)
1621 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
1622
1623 #define C_T (C_FHARD + 1)
1624 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
1625 #define C_D (C_T + 1)
1626 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
1627 #define C_DNZ_D (C_D + 1)
1628 { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } },
1629
1630 #define C_DHARD (C_DNZ_D + 1)
1631 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
1632
1633 #define C_DI20 (C_DHARD + 1)
1634 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
1635 #define C_DI14 (C_DI20 + 1)
1636 { F_CLASS_OPTIONAL, { F_DI14, F_NULL }},
1637 #define C_DI16 (C_DI14 + 1)
1638 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
1639 #define C_DI26 (C_DI16 + 1)
1640 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
1641
1642 #define C_X25 (C_DI26 + 1)
1643 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
1644 #define C_X15 (C_X25 + 1)
1645 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
1646 #define C_XHARD (C_X15 + 1)
1647 #define C_X (C_X15 + 1)
1648 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
1649
1650 #define C_ZZ13 (C_X + 1)
1651 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
1652 #define C_ZZ23 (C_ZZ13 + 1)
1653 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
1654 #define C_ZZ29 (C_ZZ23 + 1)
1655 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
1656
1657 #define C_AS (C_ZZ29 + 1)
1658 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
1659
1660 #define C_NE (C_AS + 1)
1661 { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
1662
1663 /* ARC NPS400 Support: See comment near head of file. */
1664 #define C_NPS_CL (C_NE + 1)
1665 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
1666
1667 #define C_NPS_NA (C_NPS_CL + 1)
1668 { F_CLASS_OPTIONAL, { F_NPS_NA, F_NULL}},
1669
1670 #define C_NPS_SR (C_NPS_NA + 1)
1671 { F_CLASS_OPTIONAL, { F_NPS_SR, F_NULL}},
1672
1673 #define C_NPS_M (C_NPS_SR + 1)
1674 { F_CLASS_OPTIONAL, { F_NPS_M, F_NULL}},
1675
1676 #define C_NPS_F (C_NPS_M + 1)
1677 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
1678
1679 #define C_NPS_R (C_NPS_F + 1)
1680 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
1681
1682 #define C_NPS_SCHD_RW (C_NPS_R + 1)
1683 { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
1684
1685 #define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
1686 { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
1687
1688 #define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
1689 { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
1690
1691 #define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
1692 { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
1693
1694 #define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
1695 { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
1696
1697 #define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
1698 { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
1699
1700 #define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
1701 { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
1702
1703 #define C_NPS_AR_AL (C_NPS_SX + 1)
1704 { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
1705
1706 #define C_NPS_S (C_NPS_AR_AL + 1)
1707 { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}},
1708
1709 #define C_NPS_ZNCV (C_NPS_S + 1)
1710 { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}},
1711
1712 #define C_NPS_P0 (C_NPS_ZNCV + 1)
1713 { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }},
1714
1715 #define C_NPS_P1 (C_NPS_P0 + 1)
1716 { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }},
1717
1718 #define C_NPS_P2 (C_NPS_P1 + 1)
1719 { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }},
1720
1721 #define C_NPS_P3 (C_NPS_P2 + 1)
1722 { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }},
1723
1724 #define C_NPS_LDBIT_DI (C_NPS_P3 + 1)
1725 { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }},
1726
1727 #define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1)
1728 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }},
1729
1730 #define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1)
1731 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }},
1732
1733 #define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1)
1734 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }},
1735
1736 #define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
1737 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }},
1738
1739 #define C_NPS_CORE (C_NPS_LDBIT_X_2 + 1)
1740 { F_CLASS_REQUIRED, { F_NPS_CORE, F_NULL}},
1741
1742 #define C_NPS_CLSR (C_NPS_CORE + 1)
1743 { F_CLASS_REQUIRED, { F_NPS_CLSR, F_NULL}},
1744
1745 #define C_NPS_ALL (C_NPS_CLSR + 1)
1746 { F_CLASS_REQUIRED, { F_NPS_ALL, F_NULL}},
1747
1748 #define C_NPS_GIC (C_NPS_ALL + 1)
1749 { F_CLASS_REQUIRED, { F_NPS_GIC, F_NULL}},
1750
1751 #define C_NPS_RSPI_GIC (C_NPS_GIC + 1)
1752 { F_CLASS_REQUIRED, { F_NPS_RSPI_GIC, F_NULL}},
1753 };
1754
1755 const unsigned char flags_none[] = { 0 };
1756 const unsigned char flags_f[] = { C_F };
1757 const unsigned char flags_cc[] = { C_CC };
1758 const unsigned char flags_ccf[] = { C_CC, C_F };
1759
1760 /* The operands table.
1761
1762 The format of the operands table is:
1763
1764 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
1765 const struct arc_operand arc_operands[] =
1766 {
1767 /* The fields are bits, shift, insert, extract, flags. The zero
1768 index is used to indicate end-of-list. */
1769 #define UNUSED 0
1770 { 0, 0, 0, 0, 0, 0 },
1771
1772 #define IGNORED (UNUSED + 1)
1773 { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 },
1774
1775 /* The plain integer register fields. Used by 32 bit
1776 instructions. */
1777 #define RA (IGNORED + 1)
1778 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
1779 #define RA_CHK (RA + 1)
1780 { 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 },
1781 #define RB (RA_CHK + 1)
1782 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
1783 #define RB_CHK (RB + 1)
1784 { 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb },
1785 #define RC (RB_CHK + 1)
1786 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1787 #define RBdup (RC + 1)
1788 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1789
1790 #define RAD (RBdup + 1)
1791 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1792 #define RCD (RAD + 1)
1793 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1794
1795 /* The plain integer register fields. Used by short
1796 instructions. */
1797 #define RA16 (RCD + 1)
1798 #define RA_S (RCD + 1)
1799 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1800 #define RB16 (RA16 + 1)
1801 #define RB_S (RA16 + 1)
1802 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1803 #define RB16dup (RB16 + 1)
1804 #define RB_Sdup (RB16 + 1)
1805 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1806 #define RC16 (RB16dup + 1)
1807 #define RC_S (RB16dup + 1)
1808 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1809 #define R6H (RC16 + 1) /* 6bit register field 'h' used
1810 by V1 cpus. */
1811 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1812 #define R5H (R6H + 1) /* 5bit register field 'h' used
1813 by V2 cpus. */
1814 #define RH_S (R6H + 1) /* 5bit register field 'h' used
1815 by V2 cpus. */
1816 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1817 #define R5Hdup (R5H + 1)
1818 #define RH_Sdup (R5H + 1)
1819 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1820 insert_rhv2, extract_rhv2 },
1821
1822 #define RG (R5Hdup + 1)
1823 #define G_S (R5Hdup + 1)
1824 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1825
1826 /* Fix registers. */
1827 #define R0 (RG + 1)
1828 #define R0_S (RG + 1)
1829 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1830 #define R1 (R0 + 1)
1831 #define R1_S (R0 + 1)
1832 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1833 #define R2 (R1 + 1)
1834 #define R2_S (R1 + 1)
1835 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1836 #define R3 (R2 + 1)
1837 #define R3_S (R2 + 1)
1838 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
1839 #define RSP (R3 + 1)
1840 #define SP_S (R3 + 1)
1841 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
1842 #define SPdup (RSP + 1)
1843 #define SP_Sdup (RSP + 1)
1844 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1845 #define GP (SPdup + 1)
1846 #define GP_S (SPdup + 1)
1847 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1848
1849 #define PCL_S (GP + 1)
1850 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1851
1852 #define BLINK (PCL_S + 1)
1853 #define BLINK_S (PCL_S + 1)
1854 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1855
1856 #define ILINK1 (BLINK + 1)
1857 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1858 #define ILINK2 (ILINK1 + 1)
1859 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1860
1861 /* Long immediate. */
1862 #define LIMM (ILINK2 + 1)
1863 #define LIMM_S (ILINK2 + 1)
1864 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1865 #define LIMMdup (LIMM + 1)
1866 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1867
1868 /* Special operands. */
1869 #define ZA (LIMMdup + 1)
1870 #define ZB (LIMMdup + 1)
1871 #define ZA_S (LIMMdup + 1)
1872 #define ZB_S (LIMMdup + 1)
1873 #define ZC_S (LIMMdup + 1)
1874 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1875
1876 #define RRANGE_EL (ZA + 1)
1877 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1878 insert_rrange, extract_rrange},
1879 #define FP_EL (RRANGE_EL + 1)
1880 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1881 insert_fpel, extract_fpel },
1882 #define BLINK_EL (FP_EL + 1)
1883 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1884 insert_blinkel, extract_blinkel },
1885 #define PCL_EL (BLINK_EL + 1)
1886 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1887 insert_pclel, extract_pclel },
1888
1889 /* Fake operand to handle the T flag. */
1890 #define BRAKET (PCL_EL + 1)
1891 #define BRAKETdup (PCL_EL + 1)
1892 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1893
1894 /* Fake operand to handle the T flag. */
1895 #define FKT_T (BRAKET + 1)
1896 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1897 /* Fake operand to handle the T flag. */
1898 #define FKT_NT (FKT_T + 1)
1899 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1900
1901 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1902 #define UIMM6_20 (FKT_NT + 1)
1903 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1904
1905 /* Exactly like the above but used by relaxation. */
1906 #define UIMM6_20R (UIMM6_20 + 1)
1907 {6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
1908 insert_uimm6_20, extract_uimm6_20},
1909
1910 /* SIMM12_20 mask = 00000000000000000000111111222222. */
1911 #define SIMM12_20 (UIMM6_20R + 1)
1912 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1913
1914 /* Exactly like the above but used by relaxation. */
1915 #define SIMM12_20R (SIMM12_20 + 1)
1916 {12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL,
1917 insert_simm12_20, extract_simm12_20},
1918
1919 /* SIMM3_5_S mask = 0000011100000000. */
1920 #define SIMM3_5_S (SIMM12_20R + 1)
1921 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1922 insert_simm3s, extract_simm3s},
1923
1924 /* UIMM7_A32_11_S mask = 0000000000011111. */
1925 #define UIMM7_A32_11_S (SIMM3_5_S + 1)
1926 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1927 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1928 extract_uimm7_a32_11_s},
1929
1930 /* The same as above but used by relaxation. */
1931 #define UIMM7_A32_11R_S (UIMM7_A32_11_S + 1)
1932 {7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1933 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL,
1934 insert_uimm7_a32_11_s, extract_uimm7_a32_11_s},
1935
1936 /* UIMM7_9_S mask = 0000000001111111. */
1937 #define UIMM7_9_S (UIMM7_A32_11R_S + 1)
1938 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1939
1940 /* UIMM3_13_S mask = 0000000000000111. */
1941 #define UIMM3_13_S (UIMM7_9_S + 1)
1942 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1943
1944 /* Exactly like the above but used for relaxation. */
1945 #define UIMM3_13R_S (UIMM3_13_S + 1)
1946 {3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
1947 insert_uimm3_13_s, extract_uimm3_13_s},
1948
1949 /* SIMM11_A32_7_S mask = 0000000111111111. */
1950 #define SIMM11_A32_7_S (UIMM3_13R_S + 1)
1951 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1952 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1953
1954 /* UIMM6_13_S mask = 0000000002220111. */
1955 #define UIMM6_13_S (SIMM11_A32_7_S + 1)
1956 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1957 /* UIMM5_11_S mask = 0000000000011111. */
1958 #define UIMM5_11_S (UIMM6_13_S + 1)
1959 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
1960 extract_uimm5_11_s},
1961
1962 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
1963 #define SIMM9_A16_8 (UIMM5_11_S + 1)
1964 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1965 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
1966 extract_simm9_a16_8},
1967
1968 /* UIMM6_8 mask = 00000000000000000000111111000000. */
1969 #define UIMM6_8 (SIMM9_A16_8 + 1)
1970 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
1971
1972 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
1973 #define SIMM21_A16_5 (UIMM6_8 + 1)
1974 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
1975 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
1976 insert_simm21_a16_5, extract_simm21_a16_5},
1977
1978 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
1979 #define SIMM25_A16_5 (SIMM21_A16_5 + 1)
1980 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
1981 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
1982 insert_simm25_a16_5, extract_simm25_a16_5},
1983
1984 /* SIMM10_A16_7_S mask = 0000000111111111. */
1985 #define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
1986 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1987 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
1988 extract_simm10_a16_7_s},
1989
1990 #define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
1991 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1992 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
1993
1994 /* SIMM7_A16_10_S mask = 0000000000111111. */
1995 #define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
1996 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1997 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
1998 extract_simm7_a16_10_s},
1999
2000 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
2001 #define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
2002 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2003 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
2004 extract_simm21_a32_5},
2005
2006 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
2007 #define SIMM25_A32_5 (SIMM21_A32_5 + 1)
2008 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2009 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
2010 extract_simm25_a32_5},
2011
2012 /* SIMM13_A32_5_S mask = 0000011111111111. */
2013 #define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
2014 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2015 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
2016 extract_simm13_a32_5_s},
2017
2018 /* SIMM8_A16_9_S mask = 0000000001111111. */
2019 #define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
2020 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2021 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
2022 extract_simm8_a16_9_s},
2023
2024 /* UIMM3_23 mask = 00000000000000000000000111000000. */
2025 #define UIMM3_23 (SIMM8_A16_9_S + 1)
2026 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
2027
2028 /* UIMM10_6_S mask = 0000001111111111. */
2029 #define UIMM10_6_S (UIMM3_23 + 1)
2030 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
2031
2032 /* UIMM6_11_S mask = 0000002200011110. */
2033 #define UIMM6_11_S (UIMM10_6_S + 1)
2034 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
2035
2036 /* SIMM9_8 mask = 00000000111111112000000000000000. */
2037 #define SIMM9_8 (UIMM6_11_S + 1)
2038 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
2039 insert_simm9_8, extract_simm9_8},
2040
2041 /* The same as above but used by relaxation. */
2042 #define SIMM9_8R (SIMM9_8 + 1)
2043 {9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE
2044 | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8},
2045
2046 /* UIMM10_A32_8_S mask = 0000000011111111. */
2047 #define UIMM10_A32_8_S (SIMM9_8R + 1)
2048 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
2049 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
2050 extract_uimm10_a32_8_s},
2051
2052 /* SIMM9_7_S mask = 0000000111111111. */
2053 #define SIMM9_7_S (UIMM10_A32_8_S + 1)
2054 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
2055 extract_simm9_7_s},
2056
2057 /* UIMM6_A16_11_S mask = 0000000000011111. */
2058 #define UIMM6_A16_11_S (SIMM9_7_S + 1)
2059 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
2060 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
2061 extract_uimm6_a16_11_s},
2062
2063 /* UIMM5_A32_11_S mask = 0000020000011000. */
2064 #define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
2065 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
2066 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
2067 extract_uimm5_a32_11_s},
2068
2069 /* SIMM11_A32_13_S mask = 0000022222200111. */
2070 #define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
2071 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2072 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
2073
2074 /* UIMM7_13_S mask = 0000000022220111. */
2075 #define UIMM7_13_S (SIMM11_A32_13_S + 1)
2076 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
2077
2078 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
2079 #define UIMM6_A16_21 (UIMM7_13_S + 1)
2080 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
2081 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
2082
2083 /* UIMM7_11_S mask = 0000022200011110. */
2084 #define UIMM7_11_S (UIMM6_A16_21 + 1)
2085 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
2086
2087 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
2088 #define UIMM7_A16_20 (UIMM7_11_S + 1)
2089 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
2090 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
2091 extract_uimm7_a16_20},
2092
2093 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
2094 #define SIMM13_A16_20 (UIMM7_A16_20 + 1)
2095 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2096 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
2097 extract_simm13_a16_20},
2098
2099 /* UIMM8_8_S mask = 0000000011111111. */
2100 #define UIMM8_8_S (SIMM13_A16_20 + 1)
2101 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
2102
2103 /* The same as above but used for relaxation. */
2104 #define UIMM8_8R_S (UIMM8_8_S + 1)
2105 {8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
2106 insert_uimm8_8_s, extract_uimm8_8_s},
2107
2108 /* W6 mask = 00000000000000000000111111000000. */
2109 #define W6 (UIMM8_8R_S + 1)
2110 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
2111
2112 /* UIMM6_5_S mask = 0000011111100000. */
2113 #define UIMM6_5_S (W6 + 1)
2114 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
2115
2116 /* ARC NPS400 Support: See comment near head of file. */
2117 #define NPS_R_DST_3B (UIMM6_5_S + 1)
2118 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2119 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
2120
2121 #define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
2122 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2123 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
2124
2125 #define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
2126 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2127 insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2 },
2128
2129 #define NPS_R_DST (NPS_R_SRC2_3B + 1)
2130 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
2131
2132 #define NPS_R_SRC1 (NPS_R_DST + 1)
2133 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
2134
2135 #define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
2136 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
2137
2138 #define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
2139 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
2140
2141 #define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
2142 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2143 insert_nps_bitop_size, extract_nps_bitop_size },
2144
2145 #define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
2146 { 5, 0, 0, ARC_OPERAND_UNSIGNED,
2147 insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
2148
2149 #define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
2150 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2151 insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
2152
2153 #define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
2154 { 8, 0, 0, ARC_OPERAND_UNSIGNED,
2155 insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
2156
2157 #define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
2158 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2159
2160 #define NPS_SIMM16 (NPS_UIMM16 + 1)
2161 { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL },
2162
2163 #define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1)
2164 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2165 insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
2166
2167 #define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
2168 { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2169 insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
2170
2171 #define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
2172 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2173 insert_nps_src2_pos, extract_nps_src2_pos },
2174
2175 #define NPS_SRC1_POS (NPS_SRC2_POS + 1)
2176 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2177 insert_nps_src1_pos, extract_nps_src1_pos },
2178
2179 #define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
2180 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2181 insert_nps_addb_size, extract_nps_addb_size },
2182
2183 #define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
2184 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2185 insert_nps_andb_size, extract_nps_andb_size },
2186
2187 #define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
2188 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2189 insert_nps_fxorb_size, extract_nps_fxorb_size },
2190
2191 #define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
2192 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2193 insert_nps_wxorb_size, extract_nps_wxorb_size },
2194
2195 #define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
2196 { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL },
2197
2198 #define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
2199 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2200
2201 #define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
2202 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2203 insert_nps_qcmp_size, extract_nps_qcmp_size },
2204
2205 #define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
2206 { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 },
2207
2208 #define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
2209 { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 },
2210
2211 #define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
2212 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 },
2213
2214 #define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
2215 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2216 insert_nps_calc_entry_size, extract_nps_calc_entry_size },
2217
2218 #define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1)
2219 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2220 insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
2221
2222 #define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1)
2223 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2224 insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
2225
2226 #define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1)
2227 { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2228 insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2 },
2229
2230 #define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1)
2231 { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2232 insert_nps_bitop2_size, extract_nps_bitop2_size },
2233
2234 #define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1)
2235 { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2236 insert_nps_bitop1_size, extract_nps_bitop1_size },
2237
2238 #define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1)
2239 { 5, 0, 0, ARC_OPERAND_UNSIGNED,
2240 insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 },
2241
2242 #define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1)
2243 { 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2244
2245 #define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1)
2246 { 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2247
2248 #define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1)
2249 { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2250
2251 #define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1)
2252 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2253
2254 #define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1)
2255 { 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2256
2257 #define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1)
2258 { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2259
2260 #define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1)
2261 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2262
2263 #define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1)
2264 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2265
2266 #define NPS_BITOP_MOD4 (NPS_BITOP_SRC_POS1 + 1)
2267 { 2, 0, 0, ARC_OPERAND_UNSIGNED,
2268 insert_nps_bitop_mod4, extract_nps_bitop_mod4 },
2269
2270 #define NPS_BITOP_MOD3 (NPS_BITOP_MOD4 + 1)
2271 { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2272
2273 #define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1)
2274 { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2275
2276 #define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1)
2277 { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2278
2279 #define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1)
2280 { 5, 20, 0, ARC_OPERAND_UNSIGNED,
2281 insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext },
2282
2283 #define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1)
2284 { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2285
2286 #define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1)
2287 { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2288 insert_nps_field_size, extract_nps_field_size },
2289
2290 #define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1)
2291 { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2292 insert_nps_shift_factor, extract_nps_shift_factor },
2293
2294 #define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1)
2295 { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2296 insert_nps_bits_to_scramble, extract_nps_bits_to_scramble },
2297
2298 #define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1)
2299 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2300
2301 #define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1)
2302 { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2303 insert_nps_bdlen_max_len, extract_nps_bdlen_max_len },
2304
2305 #define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1)
2306 { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2307 insert_nps_min_hofs, extract_nps_min_hofs },
2308
2309 #define NPS_PSBC (NPS_MIN_HOFS + 1)
2310 { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2311
2312 #define NPS_DPI_DST (NPS_PSBC + 1)
2313 { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL },
2314
2315 /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B
2316 but doesn't duplicate an operand. */
2317 #define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1)
2318 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2319 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
2320
2321 #define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1)
2322 { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2323 insert_nps_hash_width, extract_nps_hash_width },
2324
2325 #define NPS_HASH_PERM (NPS_HASH_WIDTH + 1)
2326 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2327
2328 #define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1)
2329 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2330
2331 #define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1)
2332 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2333
2334 #define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1)
2335 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2336 insert_nps_hash_len, extract_nps_hash_len },
2337
2338 #define NPS_HASH_OFS (NPS_HASH_LEN + 1)
2339 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2340
2341 #define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1)
2342 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2343
2344 #define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1)
2345 { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2346
2347 #define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1)
2348 { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2349
2350 #define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1)
2351 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2352
2353 #define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1)
2354 { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2355 insert_nps_index3, extract_nps_index3 },
2356
2357 #define COLON (NPS_E4BY_INDEX3 + 1)
2358 { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL },
2359
2360 #define NPS_BD (COLON + 1)
2361 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2362 insert_nps_bd, extract_nps_bd },
2363
2364 #define NPS_JID (NPS_BD + 1)
2365 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2366 insert_nps_jid, extract_nps_jid },
2367
2368 #define NPS_LBD (NPS_JID + 1)
2369 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2370 insert_nps_lbd, extract_nps_lbd },
2371
2372 #define NPS_MBD (NPS_LBD + 1)
2373 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2374 insert_nps_mbd, extract_nps_mbd },
2375
2376 #define NPS_SD (NPS_MBD + 1)
2377 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2378 insert_nps_sd, extract_nps_sd },
2379
2380 #define NPS_SM (NPS_SD + 1)
2381 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2382 insert_nps_sm, extract_nps_sm },
2383
2384 #define NPS_XA (NPS_SM + 1)
2385 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2386 insert_nps_xa, extract_nps_xa },
2387
2388 #define NPS_XD (NPS_XA + 1)
2389 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2390 insert_nps_xd, extract_nps_xd },
2391
2392 #define NPS_CD (NPS_XD + 1)
2393 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2394 insert_nps_cd, extract_nps_cd },
2395
2396 #define NPS_CBD (NPS_CD + 1)
2397 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2398 insert_nps_cbd, extract_nps_cbd },
2399
2400 #define NPS_CJID (NPS_CBD + 1)
2401 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2402 insert_nps_cjid, extract_nps_cjid },
2403
2404 #define NPS_CLBD (NPS_CJID + 1)
2405 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2406 insert_nps_clbd, extract_nps_clbd },
2407
2408 #define NPS_CM (NPS_CLBD + 1)
2409 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2410 insert_nps_cm, extract_nps_cm },
2411
2412 #define NPS_CSD (NPS_CM + 1)
2413 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2414 insert_nps_csd, extract_nps_csd },
2415
2416 #define NPS_CXA (NPS_CSD + 1)
2417 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2418 insert_nps_cxa, extract_nps_cxa },
2419
2420 #define NPS_CXD (NPS_CXA + 1)
2421 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2422 insert_nps_cxd, extract_nps_cxd },
2423
2424 #define NPS_BD_TYPE (NPS_CXD + 1)
2425 { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2426
2427 #define NPS_BMU_NUM (NPS_BD_TYPE + 1)
2428 { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2429 insert_nps_bd_num_buff, extract_nps_bd_num_buff },
2430
2431 #define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1)
2432 { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2433
2434 #define NPS_WHASH_SIZE (NPS_PMU_NXT_DST + 1)
2435 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2436 insert_nps_size_16bit, extract_nps_size_16bit },
2437
2438 #define NPS_PMU_NUM_JOB (NPS_WHASH_SIZE + 1)
2439 { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2440 insert_nps_pmu_num_job, extract_nps_pmu_num_job },
2441
2442 #define NPS_DMA_IMM_ENTRY (NPS_PMU_NUM_JOB + 1)
2443 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2444 insert_nps_imm_entry, extract_nps_imm_entry },
2445
2446 #define NPS_DMA_IMM_OFFSET (NPS_DMA_IMM_ENTRY + 1)
2447 { 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2448 insert_nps_imm_offset, extract_nps_imm_offset },
2449
2450 #define NPS_MISC_IMM_SIZE (NPS_DMA_IMM_OFFSET + 1)
2451 { 7, 0, 0, ARC_OPERAND_UNSIGNED , NULL, NULL },
2452
2453 #define NPS_MISC_IMM_OFFSET (NPS_MISC_IMM_SIZE + 1)
2454 { 5, 8, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2455 insert_nps_misc_imm_offset, extract_nps_misc_imm_offset },
2456
2457 #define NPS_R_DST_3B_48 (NPS_MISC_IMM_OFFSET + 1)
2458 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2459 insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
2460
2461 #define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1)
2462 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2463 insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
2464
2465 #define NPS_R_SRC2_3B_48 (NPS_R_SRC1_3B_48 + 1)
2466 { 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2467 insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2 },
2468
2469 #define NPS_R_DST_3B_64 (NPS_R_SRC2_3B_48 + 1)
2470 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2471 insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
2472
2473 #define NPS_R_SRC1_3B_64 (NPS_R_DST_3B_64 + 1)
2474 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2475 insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
2476
2477 #define NPS_R_SRC2_3B_64 (NPS_R_SRC1_3B_64 + 1)
2478 { 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2479 insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2 },
2480
2481 #define NPS_RA_64 (NPS_R_SRC2_3B_64 + 1)
2482 { 6, 53, 0, ARC_OPERAND_IR, NULL, NULL },
2483
2484 #define NPS_RB_64 (NPS_RA_64 + 1)
2485 { 5, 48, 0, ARC_OPERAND_IR, NULL, NULL },
2486
2487 #define NPS_RBdup_64 (NPS_RB_64 + 1)
2488 { 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
2489
2490 #define NPS_RBdouble_64 (NPS_RBdup_64 + 1)
2491 { 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2492 insert_nps_rbdouble_64, extract_nps_rbdouble_64 },
2493
2494 #define NPS_RC_64 (NPS_RBdouble_64 + 1)
2495 { 5, 43, 0, ARC_OPERAND_IR, NULL, NULL },
2496
2497 #define NPS_UIMM16_0_64 (NPS_RC_64 + 1)
2498 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2499
2500 #define NPS_PROTO_SIZE (NPS_UIMM16_0_64 + 1)
2501 { 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2502 insert_nps_proto_size, extract_nps_proto_size }
2503 };
2504 const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
2505
2506 const unsigned arc_Toperand = FKT_T;
2507 const unsigned arc_NToperand = FKT_NT;
2508
2509 const unsigned char arg_none[] = { 0 };
2510 const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
2511 const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
2512 const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
2513 const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
2514 const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
2515 const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
2516 const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
2517 const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
2518 const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
2519 const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
2520 const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
2521
2522 const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
2523 const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
2524 const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
2525
2526 const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
2527 const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
2528 const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
2529
2530 const unsigned char arg_32bit_rbrc[] = { RB, RC };
2531 const unsigned char arg_32bit_zarc[] = { ZA, RC };
2532 const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
2533 const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
2534 const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
2535 const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
2536
2537 const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
2538 const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
2539 const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
2540 const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
2541
2542 const unsigned char arg_32bit_rc[] = { RC };
2543 const unsigned char arg_32bit_u6[] = { UIMM6_20 };
2544 const unsigned char arg_32bit_limm[] = { LIMM };
2545
2546 /* The opcode table.
2547
2548 The format of the opcode table is:
2549
2550 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
2551
2552 The table is organised such that, where possible, all instructions with
2553 the same mnemonic are together in a block. When the assembler searches
2554 for a suitable instruction the entries are checked in table order, so
2555 more specific, or specialised cases should appear earlier in the table.
2556
2557 As an example, consider two instructions 'add a,b,u6' and 'add
2558 a,b,limm'. The first takes a 6-bit immediate that is encoded within the
2559 32-bit instruction, while the second takes a 32-bit immediate that is
2560 encoded in a follow-on 32-bit, making the total instruction length
2561 64-bits. In this case the u6 variant must appear first in the table, as
2562 all u6 immediates could also be encoded using the 'limm' extension,
2563 however, we want to use the shorter instruction wherever possible.
2564
2565 It is possible though to split instructions with the same mnemonic into
2566 multiple groups. However, the instructions are still checked in table
2567 order, even across groups. The only time that instructions with the
2568 same mnemonic should be split into different groups is when different
2569 variants of the instruction appear in different architectures, in which
2570 case, grouping all instructions from a particular architecture together
2571 might be preferable to merging the instruction into the main instruction
2572 table.
2573
2574 An example of this split instruction groups can be found with the 'sync'
2575 instruction. The core arc architecture provides a 'sync' instruction,
2576 while the nps instruction set extension provides 'sync.rd' and
2577 'sync.wr'. The rd/wr flags are instruction flags, not part of the
2578 mnemonic, so we end up with two groups for the sync instruction, the
2579 first within the core arc instruction table, and the second within the
2580 nps extension instructions. */
2581 const struct arc_opcode arc_opcodes[] =
2582 {
2583 #include "arc-tbl.h"
2584 #include "arc-nps400-tbl.h"
2585 #include "arc-ext-tbl.h"
2586
2587 { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
2588 };
2589
2590 /* List with special cases instructions and the applicable flags. */
2591 const struct arc_flag_special arc_flag_special_cases[] =
2592 {
2593 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2594 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2595 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2596 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM,
2597 F_NO_T, F_NULL } },
2598 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2599 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2600 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2601 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2602 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2603 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2604 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2605 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2606 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2607 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2608 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2609 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2610 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2611 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2612 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2613 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2614 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2615 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2616 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2617 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2618 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2619 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2620 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2621 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2622 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
2623 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
2624 };
2625
2626 const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
2627
2628 /* Relocations. */
2629 const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
2630 {
2631 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
2632 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2633 { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
2634 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2635 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
2636 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2637 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
2638 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2639
2640 /* Next two entries will cover the undefined behavior ldb/stb with
2641 address scaling. */
2642 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
2643 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2644 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
2645 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
2646
2647 { "sda", "ld", { F_ASFAKE, F_NULL },
2648 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2649 { "sda", "st", { F_ASFAKE, F_NULL },
2650 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
2651 { "sda", "ldd", { F_ASFAKE, F_NULL },
2652 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2653 { "sda", "std", { F_ASFAKE, F_NULL },
2654 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
2655
2656 /* Short instructions. */
2657 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
2658 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
2659 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
2660 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
2661
2662 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
2663 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2664
2665 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
2666 BFD_RELOC_ARC_S25H_PCREL_PLT },
2667 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
2668 BFD_RELOC_ARC_S21H_PCREL_PLT },
2669 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
2670 BFD_RELOC_ARC_S25W_PCREL_PLT },
2671 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
2672 BFD_RELOC_ARC_S21W_PCREL_PLT },
2673
2674 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
2675 };
2676
2677 const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
2678
2679 const struct arc_pseudo_insn arc_pseudo_insns[] =
2680 {
2681 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2682 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
2683 { BRAKETdup, 1, 0, 4} } },
2684 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2685 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
2686 { BRAKETdup, 1, 0, 4} } },
2687
2688 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2689 { SIMM9_A16_8, 0, 0, 2 } } },
2690 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2691 { SIMM9_A16_8, 0, 0, 2 } } },
2692 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2693 { SIMM9_A16_8, 0, 0, 2 } } },
2694 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2695 { SIMM9_A16_8, 0, 0, 2 } } },
2696 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2697 { SIMM9_A16_8, 0, 0, 2 } } },
2698
2699 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2700 { SIMM9_A16_8, 0, 0, 2 } } },
2701 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2702 { SIMM9_A16_8, 0, 0, 2 } } },
2703 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2704 { SIMM9_A16_8, 0, 0, 2 } } },
2705 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2706 { SIMM9_A16_8, 0, 0, 2 } } },
2707 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2708 { SIMM9_A16_8, 0, 0, 2 } } },
2709
2710 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2711 { SIMM9_A16_8, 0, 0, 2 } } },
2712 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2713 { SIMM9_A16_8, 0, 0, 2 } } },
2714 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2715 { SIMM9_A16_8, 0, 0, 2 } } },
2716 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2717 { SIMM9_A16_8, 0, 0, 2 } } },
2718 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2719 { SIMM9_A16_8, 0, 0, 2 } } },
2720
2721 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2722 { SIMM9_A16_8, 0, 0, 2 } } },
2723 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2724 { SIMM9_A16_8, 0, 0, 2 } } },
2725 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2726 { SIMM9_A16_8, 0, 0, 2 } } },
2727 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2728 { SIMM9_A16_8, 0, 0, 2 } } },
2729 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2730 { SIMM9_A16_8, 0, 0, 2 } } },
2731 };
2732
2733 const unsigned arc_num_pseudo_insn =
2734 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
2735
2736 const struct arc_aux_reg arc_aux_regs[] =
2737 {
2738 #undef DEF
2739 #define DEF(ADDR, CPU, SUBCLASS, NAME) \
2740 { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
2741
2742 #include "arc-regs.h"
2743
2744 #undef DEF
2745 };
2746
2747 const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
2748
2749 /* NOTE: The order of this array MUST be consistent with 'enum
2750 arc_rlx_types' located in tc-arc.h! */
2751 const struct arc_opcode arc_relax_opcodes[] =
2752 {
2753 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
2754
2755 /* bl_s s13 11111sssssssssss. */
2756 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2757 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2758 { SIMM13_A32_5_S }, { 0 }},
2759
2760 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
2761 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2762 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2763 { SIMM25_A32_5 }, { C_D }},
2764
2765 /* b_s s10 1111000sssssssss. */
2766 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2767 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2768 { SIMM10_A16_7_S }, { 0 }},
2769
2770 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
2771 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2772 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2773 { SIMM25_A16_5 }, { C_D }},
2774
2775 /* add_s c,b,u3 01101bbbccc00uuu. */
2776 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2777 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2778 { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
2779
2780 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */
2781 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2782 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2783 { RA, RB, UIMM6_20R }, { C_F }},
2784
2785 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
2786 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2787 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2788 { RA, RB, LIMM }, { C_F }},
2789
2790 /* ld_s c,b,u7 10000bbbcccuuuuu. */
2791 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2792 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2793 { RC_S, BRAKET, RB_S, UIMM7_A32_11R_S, BRAKETdup }, { 0 }},
2794
2795 /* ld<.di><.aa><.x><zz> a,b,s9
2796 00010bbbssssssssSBBBDaaZZXAAAAAA. */
2797 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2798 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2799 { RA, BRAKET, RB, SIMM9_8R, BRAKETdup },
2800 { C_ZZ23, C_DI20, C_AA21, C_X25 }},
2801
2802 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
2803 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2804 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2805 { RA, BRAKET, RB, LIMM, BRAKETdup },
2806 { C_ZZ13, C_DI16, C_AA8, C_X15 }},
2807
2808 /* mov_s b,u8 11011bbbuuuuuuuu. */
2809 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2810 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2811 { RB_S, UIMM8_8R_S }, { 0 }},
2812
2813 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */
2814 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2815 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2816 { RB, SIMM12_20R }, { C_F }},
2817
2818 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
2819 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2820 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2821 { RB, LIMM }, { C_F }},
2822
2823 /* sub_s c,b,u3 01101bbbccc01uuu. */
2824 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2825 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2826 { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
2827
2828 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */
2829 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2830 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2831 { RA, RB, UIMM6_20R }, { C_F }},
2832
2833 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
2834 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2835 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2836 { RA, RB, LIMM }, { C_F }},
2837
2838 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */
2839 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2840 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20R }, { C_F }},
2841
2842 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
2843 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2844 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
2845
2846 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */
2847 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2848 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2849 { RB, UIMM6_20R }, { C_F, C_CC }},
2850
2851 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
2852 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2853 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2854 { RB, LIMM }, { C_F, C_CC }},
2855
2856 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */
2857 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2858 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2859 { RB, RBdup, UIMM6_20R }, { C_F, C_CC }},
2860
2861 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
2862 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2863 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2864 { RB, RBdup, LIMM }, { C_F, C_CC }}
2865 };
2866
2867 const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
2868
2869 /* Return length of an opcode in bytes. */
2870
2871 int
2872 arc_opcode_len (const struct arc_opcode *opcode)
2873 {
2874 if (opcode->mask < 0x10000ull)
2875 return 2;
2876
2877 if (opcode->mask < 0x100000000ull)
2878 return 4;
2879
2880 if (opcode->mask < 0x1000000000000ull)
2881 return 6;
2882
2883 return 8;
2884 }
GDB Binutils - Deliverables
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