1 /* Opcode table for the ARC.
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software Foundation,
20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
25 #include "opcode/arc.h"
27 #include "libiberty.h"
29 /* Insert RB register into a 32-bit opcode. */
31 insert_rb (unsigned insn
,
33 const char **errmsg ATTRIBUTE_UNUSED
)
35 return insn
| ((value
& 0x07) << 24) | (((value
>> 3) & 0x07) << 12);
39 extract_rb (unsigned insn ATTRIBUTE_UNUSED
,
40 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
42 int value
= (((insn
>> 12) & 0x07) << 3) | ((insn
>> 24) & 0x07);
44 if (value
== 0x3e && invalid
)
45 *invalid
= TRUE
; /* A limm operand, it should be extracted in a
52 insert_rad (unsigned insn
,
54 const char **errmsg ATTRIBUTE_UNUSED
)
57 *errmsg
= _("Improper register value.");
59 return insn
| (value
& 0x3F);
63 insert_rcd (unsigned insn
,
65 const char **errmsg ATTRIBUTE_UNUSED
)
68 *errmsg
= _("Improper register value.");
70 return insn
| ((value
& 0x3F) << 6);
73 /* Dummy insert ZERO operand function. */
76 insert_za (unsigned insn
,
81 *errmsg
= _("operand is not zero");
85 /* Insert Y-bit in bbit/br instructions. This function is called only
86 when solving fixups. */
89 insert_Ybit (unsigned insn
,
91 const char **errmsg ATTRIBUTE_UNUSED
)
99 /* Insert Y-bit in bbit/br instructions. This function is called only
100 when solving fixups. */
103 insert_NYbit (unsigned insn
,
105 const char **errmsg ATTRIBUTE_UNUSED
)
113 /* Insert H register into a 16-bit opcode. */
116 insert_rhv1 (unsigned insn
,
118 const char **errmsg ATTRIBUTE_UNUSED
)
120 return insn
|= ((value
& 0x07) << 5) | ((value
>> 3) & 0x07);
124 extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED
,
125 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
132 /* Insert H register into a 16-bit opcode. */
135 insert_rhv2 (unsigned insn
,
141 _("Register R30 is a limm indicator for this type of instruction.");
142 return insn
|= ((value
& 0x07) << 5) | ((value
>> 3) & 0x03);
146 extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED
,
147 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
149 int value
= ((insn
>> 5) & 0x07) | ((insn
& 0x03) << 3);
155 insert_r0 (unsigned insn
,
157 const char **errmsg ATTRIBUTE_UNUSED
)
160 *errmsg
= _("Register must be R0.");
165 extract_r0 (unsigned insn ATTRIBUTE_UNUSED
,
166 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
173 insert_r1 (unsigned insn
,
175 const char **errmsg ATTRIBUTE_UNUSED
)
178 *errmsg
= _("Register must be R1.");
183 extract_r1 (unsigned insn ATTRIBUTE_UNUSED
,
184 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
190 insert_r2 (unsigned insn
,
192 const char **errmsg ATTRIBUTE_UNUSED
)
195 *errmsg
= _("Register must be R2.");
200 extract_r2 (unsigned insn ATTRIBUTE_UNUSED
,
201 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
207 insert_r3 (unsigned insn
,
209 const char **errmsg ATTRIBUTE_UNUSED
)
212 *errmsg
= _("Register must be R3.");
217 extract_r3 (unsigned insn ATTRIBUTE_UNUSED
,
218 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
224 insert_sp (unsigned insn
,
226 const char **errmsg ATTRIBUTE_UNUSED
)
229 *errmsg
= _("Register must be SP.");
234 extract_sp (unsigned insn ATTRIBUTE_UNUSED
,
235 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
241 insert_gp (unsigned insn
,
243 const char **errmsg ATTRIBUTE_UNUSED
)
246 *errmsg
= _("Register must be GP.");
251 extract_gp (unsigned insn ATTRIBUTE_UNUSED
,
252 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
258 insert_pcl (unsigned insn
,
260 const char **errmsg ATTRIBUTE_UNUSED
)
263 *errmsg
= _("Register must be PCL.");
268 extract_pcl (unsigned insn ATTRIBUTE_UNUSED
,
269 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
275 insert_blink (unsigned insn
,
277 const char **errmsg ATTRIBUTE_UNUSED
)
280 *errmsg
= _("Register must be BLINK.");
285 extract_blink (unsigned insn ATTRIBUTE_UNUSED
,
286 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
292 insert_ilink1 (unsigned insn
,
294 const char **errmsg ATTRIBUTE_UNUSED
)
297 *errmsg
= _("Register must be ILINK1.");
302 extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED
,
303 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
309 insert_ilink2 (unsigned insn
,
311 const char **errmsg ATTRIBUTE_UNUSED
)
314 *errmsg
= _("Register must be ILINK2.");
319 extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED
,
320 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
326 insert_ras (unsigned insn
,
328 const char **errmsg ATTRIBUTE_UNUSED
)
345 *errmsg
= _("Register must be either r0-r3 or r12-r15.");
352 extract_ras (unsigned insn ATTRIBUTE_UNUSED
,
353 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
355 int value
= insn
& 0x07;
363 insert_rbs (unsigned insn
,
365 const char **errmsg ATTRIBUTE_UNUSED
)
379 insn
|= ((value
- 8)) << 8;
382 *errmsg
= _("Register must be either r0-r3 or r12-r15.");
389 extract_rbs (unsigned insn ATTRIBUTE_UNUSED
,
390 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
392 int value
= (insn
>> 8) & 0x07;
400 insert_rcs (unsigned insn
,
402 const char **errmsg ATTRIBUTE_UNUSED
)
416 insn
|= ((value
- 8)) << 5;
419 *errmsg
= _("Register must be either r0-r3 or r12-r15.");
426 extract_rcs (unsigned insn ATTRIBUTE_UNUSED
,
427 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
429 int value
= (insn
>> 5) & 0x07;
437 insert_simm3s (unsigned insn
,
439 const char **errmsg ATTRIBUTE_UNUSED
)
469 *errmsg
= _("Accepted values are from -1 to 6.");
478 extract_simm3s (unsigned insn ATTRIBUTE_UNUSED
,
479 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
481 int value
= (insn
>> 8) & 0x07;
489 insert_rrange (unsigned insn
,
491 const char **errmsg ATTRIBUTE_UNUSED
)
493 int reg1
= (value
>> 16) & 0xFFFF;
494 int reg2
= value
& 0xFFFF;
497 *errmsg
= _("First register of the range should be r13.");
500 if (reg2
< 13 || reg2
> 26)
502 *errmsg
= _("Last register of the range doesn't fit.");
505 insn
|= ((reg2
- 12) & 0x0F) << 1;
510 extract_rrange (unsigned insn ATTRIBUTE_UNUSED
,
511 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
513 return (insn
>> 1) & 0x0F;
517 insert_fpel (unsigned insn
,
519 const char **errmsg ATTRIBUTE_UNUSED
)
523 *errmsg
= _("Invalid register number, should be fp.");
532 extract_fpel (unsigned insn ATTRIBUTE_UNUSED
,
533 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
535 return (insn
& 0x0100) ? 27 : -1;
539 insert_blinkel (unsigned insn
,
541 const char **errmsg ATTRIBUTE_UNUSED
)
545 *errmsg
= _("Invalid register number, should be blink.");
554 extract_blinkel (unsigned insn ATTRIBUTE_UNUSED
,
555 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
557 return (insn
& 0x0200) ? 31 : -1;
561 insert_pclel (unsigned insn
,
563 const char **errmsg ATTRIBUTE_UNUSED
)
567 *errmsg
= _("Invalid register number, should be pcl.");
576 extract_pclel (unsigned insn ATTRIBUTE_UNUSED
,
577 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
579 return (insn
& 0x0400) ? 63 : -1;
583 /* mask = 00000000000000000000111111000000
584 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
586 insert_w6 (unsigned insn ATTRIBUTE_UNUSED
,
587 int value ATTRIBUTE_UNUSED
,
588 const char **errmsg ATTRIBUTE_UNUSED
)
590 insn
|= ((value
>> 0) & 0x003f) << 6;
596 /* mask = 00000000000000000000111111000000. */
598 extract_w6 (unsigned insn ATTRIBUTE_UNUSED
,
599 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
603 value
|= ((insn
>> 6) & 0x003f) << 0;
609 /* mask = 0000011100022000
610 insn = 01000ggghhhGG0HH. */
612 insert_g_s (unsigned insn ATTRIBUTE_UNUSED
,
613 int value ATTRIBUTE_UNUSED
,
614 const char **errmsg ATTRIBUTE_UNUSED
)
616 insn
|= ((value
>> 0) & 0x0007) << 8;
617 insn
|= ((value
>> 3) & 0x0003) << 3;
623 /* mask = 0000011100022000. */
625 extract_g_s (unsigned insn ATTRIBUTE_UNUSED
,
626 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
630 value
|= ((insn
>> 8) & 0x0007) << 0;
631 value
|= ((insn
>> 3) & 0x0003) << 3;
633 /* Extend the sign. */
634 int signbit
= 1 << (6 - 1);
635 value
= (value
^ signbit
) - signbit
;
640 /* Include the generic extract/insert functions. Order is important
641 as some of the functions present in the .h may be disabled via
645 /* Abbreviations for instruction subsets. */
646 #define BASE ARC_OPCODE_BASE
648 /* The flag operands table.
650 The format of the table is
651 NAME CODE BITS SHIFT FAVAIL. */
652 const struct arc_flag_operand arc_flag_operands
[] =
656 #define F_ALWAYS (F_NULL + 1)
657 { "al", 0, 0, 0, 0 },
658 #define F_RA (F_ALWAYS + 1)
659 { "ra", 0, 0, 0, 0 },
660 #define F_EQUAL (F_RA + 1)
661 { "eq", 1, 5, 0, 1 },
662 #define F_ZERO (F_EQUAL + 1)
664 #define F_NOTEQUAL (F_ZERO + 1)
665 { "ne", 2, 5, 0, 1 },
666 #define F_NOTZERO (F_NOTEQUAL + 1)
667 { "nz", 2, 5, 0, 0 },
668 #define F_POZITIVE (F_NOTZERO + 1)
670 #define F_PL (F_POZITIVE + 1)
671 { "pl", 3, 5, 0, 0 },
672 #define F_NEGATIVE (F_PL + 1)
674 #define F_MINUS (F_NEGATIVE + 1)
675 { "mi", 4, 5, 0, 0 },
676 #define F_CARRY (F_MINUS + 1)
678 #define F_CARRYSET (F_CARRY + 1)
679 { "cs", 5, 5, 0, 0 },
680 #define F_LOWER (F_CARRYSET + 1)
681 { "lo", 5, 5, 0, 0 },
682 #define F_CARRYCLR (F_LOWER + 1)
683 { "cc", 6, 5, 0, 0 },
684 #define F_NOTCARRY (F_CARRYCLR + 1)
685 { "nc", 6, 5, 0, 1 },
686 #define F_HIGHER (F_NOTCARRY + 1)
687 { "hs", 6, 5, 0, 0 },
688 #define F_OVERFLOWSET (F_HIGHER + 1)
689 { "vs", 7, 5, 0, 0 },
690 #define F_OVERFLOW (F_OVERFLOWSET + 1)
692 #define F_NOTOVERFLOW (F_OVERFLOW + 1)
693 { "nv", 8, 5, 0, 1 },
694 #define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
695 { "vc", 8, 5, 0, 0 },
696 #define F_GT (F_OVERFLOWCLR + 1)
697 { "gt", 9, 5, 0, 1 },
698 #define F_GE (F_GT + 1)
699 { "ge", 10, 5, 0, 1 },
700 #define F_LT (F_GE + 1)
701 { "lt", 11, 5, 0, 1 },
702 #define F_LE (F_LT + 1)
703 { "le", 12, 5, 0, 1 },
704 #define F_HI (F_LE + 1)
705 { "hi", 13, 5, 0, 1 },
706 #define F_LS (F_HI + 1)
707 { "ls", 14, 5, 0, 1 },
708 #define F_PNZ (F_LS + 1)
709 { "pnz", 15, 5, 0, 1 },
712 #define F_FLAG (F_PNZ + 1)
713 { "f", 1, 1, 15, 1 },
714 #define F_FFAKE (F_FLAG + 1)
718 #define F_ND (F_FFAKE + 1)
719 { "nd", 0, 1, 5, 0 },
720 #define F_D (F_ND + 1)
722 #define F_DFAKE (F_D + 1)
726 #define F_SIZEB1 (F_DFAKE + 1)
728 #define F_SIZEB7 (F_SIZEB1 + 1)
730 #define F_SIZEB17 (F_SIZEB7 + 1)
731 { "b", 1, 2, 17, 1 },
732 #define F_SIZEW1 (F_SIZEB17 + 1)
734 #define F_SIZEW7 (F_SIZEW1 + 1)
736 #define F_SIZEW17 (F_SIZEW7 + 1)
737 { "w", 2, 2, 17, 0 },
739 /* Sign extension. */
740 #define F_SIGN6 (F_SIZEW17 + 1)
742 #define F_SIGN16 (F_SIGN6 + 1)
743 { "x", 1, 1, 16, 1 },
744 #define F_SIGNX (F_SIGN16 + 1)
747 /* Address write-back modes. */
748 #define F_A3 (F_SIGNX + 1)
750 #define F_A9 (F_A3 + 1)
752 #define F_A22 (F_A9 + 1)
753 { "a", 1, 2, 22, 0 },
754 #define F_AW3 (F_A22 + 1)
755 { "aw", 1, 2, 3, 1 },
756 #define F_AW9 (F_AW3 + 1)
757 { "aw", 1, 2, 9, 1 },
758 #define F_AW22 (F_AW9 + 1)
759 { "aw", 1, 2, 22, 1 },
760 #define F_AB3 (F_AW22 + 1)
761 { "ab", 2, 2, 3, 1 },
762 #define F_AB9 (F_AB3 + 1)
763 { "ab", 2, 2, 9, 1 },
764 #define F_AB22 (F_AB9 + 1)
765 { "ab", 2, 2, 22, 1 },
766 #define F_AS3 (F_AB22 + 1)
767 { "as", 3, 2, 3, 1 },
768 #define F_AS9 (F_AS3 + 1)
769 { "as", 3, 2, 9, 1 },
770 #define F_AS22 (F_AS9 + 1)
771 { "as", 3, 2, 22, 1 },
772 #define F_ASFAKE (F_AS22 + 1)
773 { "as", 0, 0, 0, 1 },
776 #define F_DI5 (F_ASFAKE + 1)
777 { "di", 1, 1, 5, 1 },
778 #define F_DI11 (F_DI5 + 1)
779 { "di", 1, 1, 11, 1 },
780 #define F_DI15 (F_DI11 + 1)
781 { "di", 1, 1, 15, 1 },
783 /* ARCv2 specific. */
784 #define F_NT (F_DI15 + 1)
786 #define F_T (F_NT + 1)
788 #define F_H1 (F_T + 1)
790 #define F_H7 (F_H1 + 1)
792 #define F_H17 (F_H7 + 1)
793 { "h", 2, 2, 17, 1 },
796 #define F_NE (F_H17 + 1)
797 { "ne", 0, 0, 0, 1 },
800 const unsigned arc_num_flag_operands
= ARRAY_SIZE (arc_flag_operands
);
802 /* Table of the flag classes.
804 The format of the table is
805 CLASS {FLAG_CODE}. */
806 const struct arc_flag_class arc_flag_classes
[] =
809 { FNONE
, { F_NULL
} },
811 #define C_CC (C_EMPTY + 1)
812 { CND
, { F_ALWAYS
, F_RA
, F_EQUAL
, F_ZERO
, F_NOTEQUAL
, F_NOTZERO
,
813 F_POZITIVE
, F_PL
, F_NEGATIVE
, F_MINUS
, F_CARRY
, F_CARRYSET
,
814 F_LOWER
, F_CARRYCLR
, F_NOTCARRY
, F_HIGHER
, F_OVERFLOWSET
,
815 F_OVERFLOW
, F_NOTOVERFLOW
, F_OVERFLOWCLR
, F_GT
, F_GE
, F_LT
,
816 F_LE
, F_HI
, F_LS
, F_PNZ
, F_NULL
} },
818 #define C_AA_ADDR3 (C_CC + 1)
819 #define C_AA27 (C_CC + 1)
820 { WBM
, { F_A3
, F_AW3
, F_AB3
, F_AS3
, F_NULL
} },
821 #define C_AA_ADDR9 (C_AA_ADDR3 + 1)
822 #define C_AA21 (C_AA_ADDR3 + 1)
823 { WBM
, { F_A9
, F_AW9
, F_AB9
, F_AS9
, F_NULL
} },
824 #define C_AA_ADDR22 (C_AA_ADDR9 + 1)
825 #define C_AA8 (C_AA_ADDR9 + 1)
826 { WBM
, { F_A22
, F_AW22
, F_AB22
, F_AS22
, F_NULL
} },
828 #define C_F (C_AA_ADDR22 + 1)
829 { FLG
, { F_FLAG
, F_NULL
} },
830 #define C_FHARD (C_F + 1)
831 { FLG
, { F_FFAKE
, F_NULL
} },
833 #define C_T (C_FHARD + 1)
834 { SBP
, { F_NT
, F_T
, F_NULL
} },
835 #define C_D (C_T + 1)
836 { DLY
, { F_ND
, F_D
, F_NULL
} },
838 #define C_DHARD (C_D + 1)
839 { DLY
, { F_DFAKE
, F_NULL
} },
841 #define C_DI20 (C_DHARD + 1)
842 { DIF
, { F_DI11
, F_NULL
}},
843 #define C_DI16 (C_DI20 + 1)
844 { DIF
, { F_DI15
, F_NULL
}},
845 #define C_DI26 (C_DI16 + 1)
846 { DIF
, { F_DI5
, F_NULL
}},
848 #define C_X25 (C_DI26 + 1)
849 { SGX
, { F_SIGN6
, F_NULL
}},
850 #define C_X15 (C_X25 + 1)
851 { SGX
, { F_SIGN16
, F_NULL
}},
852 #define C_XHARD (C_X15 + 1)
853 #define C_X (C_X15 + 1)
854 { SGX
, { F_SIGNX
, F_NULL
}},
856 #define C_ZZ13 (C_X + 1)
857 { SZM
, { F_SIZEB17
, F_SIZEW17
, F_H17
, F_NULL
}},
858 #define C_ZZ23 (C_ZZ13 + 1)
859 { SZM
, { F_SIZEB7
, F_SIZEW7
, F_H7
, F_NULL
}},
860 #define C_ZZ29 (C_ZZ23 + 1)
861 { SZM
, { F_SIZEB1
, F_SIZEW1
, F_H1
, F_NULL
}},
863 #define C_AS (C_ZZ29 + 1)
864 { SZM
, { F_ASFAKE
, F_NULL
}},
866 #define C_NE (C_AS + 1)
867 { CND
, { F_NE
, F_NULL
}},
870 /* The operands table.
872 The format of the operands table is:
874 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
875 const struct arc_operand arc_operands
[] =
877 /* The fields are bits, shift, insert, extract, flags. The zero
878 index is used to indicate end-of-list. */
880 { 0, 0, 0, 0, 0, 0 },
881 /* The plain integer register fields. Used by 32 bit
883 #define RA (UNUSED + 1)
884 { 6, 0, 0, ARC_OPERAND_IR
, 0, 0 },
886 { 6, 12, 0, ARC_OPERAND_IR
, insert_rb
, extract_rb
},
888 { 6, 6, 0, ARC_OPERAND_IR
, 0, 0 },
889 #define RBdup (RC + 1)
890 { 6, 12, 0, ARC_OPERAND_IR
| ARC_OPERAND_DUPLICATE
, insert_rb
, extract_rb
},
892 #define RAD (RBdup + 1)
893 { 6, 0, 0, ARC_OPERAND_IR
| ARC_OPERAND_TRUNCATE
, insert_rad
, 0 },
894 #define RCD (RAD + 1)
895 { 6, 6, 0, ARC_OPERAND_IR
| ARC_OPERAND_TRUNCATE
, insert_rcd
, 0 },
897 /* The plain integer register fields. Used by short
899 #define RA16 (RCD + 1)
900 #define RA_S (RCD + 1)
901 { 4, 0, 0, ARC_OPERAND_IR
, insert_ras
, extract_ras
},
902 #define RB16 (RA16 + 1)
903 #define RB_S (RA16 + 1)
904 { 4, 8, 0, ARC_OPERAND_IR
, insert_rbs
, extract_rbs
},
905 #define RB16dup (RB16 + 1)
906 #define RB_Sdup (RB16 + 1)
907 { 4, 8, 0, ARC_OPERAND_IR
| ARC_OPERAND_DUPLICATE
, insert_rbs
, extract_rbs
},
908 #define RC16 (RB16dup + 1)
909 #define RC_S (RB16dup + 1)
910 { 4, 5, 0, ARC_OPERAND_IR
, insert_rcs
, extract_rcs
},
911 #define R6H (RC16 + 1) /* 6bit register field 'h' used
913 { 6, 5, 0, ARC_OPERAND_IR
, insert_rhv1
, extract_rhv1
},
914 #define R5H (R6H + 1) /* 5bit register field 'h' used
916 #define RH_S (R6H + 1) /* 5bit register field 'h' used
918 { 5, 5, 0, ARC_OPERAND_IR
, insert_rhv2
, extract_rhv2
},
919 #define R5Hdup (R5H + 1)
920 #define RH_Sdup (R5H + 1)
921 { 5, 5, 0, ARC_OPERAND_IR
| ARC_OPERAND_DUPLICATE
,
922 insert_rhv2
, extract_rhv2
},
924 #define RG (R5Hdup + 1)
925 #define G_S (R5Hdup + 1)
926 { 5, 5, 0, ARC_OPERAND_IR
, insert_g_s
, extract_g_s
},
930 #define R0_S (RG + 1)
931 { 0, 0, 0, ARC_OPERAND_IR
, insert_r0
, extract_r0
},
933 #define R1_S (R0 + 1)
934 { 1, 0, 0, ARC_OPERAND_IR
, insert_r1
, extract_r1
},
936 #define R2_S (R1 + 1)
937 { 2, 0, 0, ARC_OPERAND_IR
, insert_r2
, extract_r2
},
939 #define R3_S (R2 + 1)
940 { 2, 0, 0, ARC_OPERAND_IR
, insert_r3
, extract_r3
},
942 #define SP_S (R3 + 1)
943 { 5, 0, 0, ARC_OPERAND_IR
, insert_sp
, extract_sp
},
944 #define SPdup (SP + 1)
945 #define SP_Sdup (SP + 1)
946 { 5, 0, 0, ARC_OPERAND_IR
| ARC_OPERAND_DUPLICATE
, insert_sp
, extract_sp
},
947 #define GP (SPdup + 1)
948 #define GP_S (SPdup + 1)
949 { 5, 0, 0, ARC_OPERAND_IR
, insert_gp
, extract_gp
},
951 #define PCL_S (GP + 1)
952 { 1, 0, 0, ARC_OPERAND_IR
| ARC_OPERAND_NCHK
, insert_pcl
, extract_pcl
},
954 #define BLINK (PCL_S + 1)
955 #define BLINK_S (PCL_S + 1)
956 { 5, 0, 0, ARC_OPERAND_IR
, insert_blink
, extract_blink
},
958 #define ILINK1 (BLINK + 1)
959 { 5, 0, 0, ARC_OPERAND_IR
, insert_ilink1
, extract_ilink1
},
960 #define ILINK2 (ILINK1 + 1)
961 { 5, 0, 0, ARC_OPERAND_IR
, insert_ilink2
, extract_ilink2
},
963 /* Long immediate. */
964 #define LIMM (ILINK2 + 1)
965 #define LIMM_S (ILINK2 + 1)
966 { 32, 0, BFD_RELOC_ARC_32_ME
, ARC_OPERAND_LIMM
, insert_limm
, 0 },
967 #define LIMMdup (LIMM + 1)
968 { 32, 0, 0, ARC_OPERAND_LIMM
| ARC_OPERAND_DUPLICATE
, insert_limm
, 0 },
970 /* Special operands. */
971 #define ZA (LIMMdup + 1)
972 #define ZB (LIMMdup + 1)
973 #define ZA_S (LIMMdup + 1)
974 #define ZB_S (LIMMdup + 1)
975 #define ZC_S (LIMMdup + 1)
976 { 0, 0, 0, ARC_OPERAND_UNSIGNED
, insert_za
, 0 },
978 #define RRANGE_EL (ZA + 1)
979 { 4, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
| ARC_OPERAND_TRUNCATE
,
980 insert_rrange
, extract_rrange
},
981 #define FP_EL (RRANGE_EL + 1)
982 { 1, 0, 0, ARC_OPERAND_IR
| ARC_OPERAND_IGNORE
| ARC_OPERAND_NCHK
,
983 insert_fpel
, extract_fpel
},
984 #define BLINK_EL (FP_EL + 1)
985 { 1, 0, 0, ARC_OPERAND_IR
| ARC_OPERAND_IGNORE
| ARC_OPERAND_NCHK
,
986 insert_blinkel
, extract_blinkel
},
987 #define PCL_EL (BLINK_EL + 1)
988 { 1, 0, 0, ARC_OPERAND_IR
| ARC_OPERAND_IGNORE
| ARC_OPERAND_NCHK
,
989 insert_pclel
, extract_pclel
},
991 /* Fake operand to handle the T flag. */
992 #define BRAKET (PCL_EL + 1)
993 #define BRAKETdup (PCL_EL + 1)
994 { 0, 0, 0, ARC_OPERAND_FAKE
| ARC_OPERAND_BRAKET
, 0, 0 },
996 /* Fake operand to handle the T flag. */
997 #define FKT_T (BRAKET + 1)
998 { 1, 3, 0, ARC_OPERAND_FAKE
, insert_Ybit
, 0 },
999 /* Fake operand to handle the T flag. */
1000 #define FKT_NT (FKT_T + 1)
1001 { 1, 3, 0, ARC_OPERAND_FAKE
, insert_NYbit
, 0 },
1003 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1004 #define UIMM6_20 (FKT_NT + 1)
1005 {6, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm6_20
, extract_uimm6_20
},
1007 /* SIMM12_20 mask = 00000000000000000000111111222222. */
1008 #define SIMM12_20 (UIMM6_20 + 1)
1009 {12, 0, 0, ARC_OPERAND_SIGNED
, insert_simm12_20
, extract_simm12_20
},
1011 /* SIMM3_5_S mask = 0000011100000000. */
1012 #define SIMM3_5_S (SIMM12_20 + 1)
1013 {3, 0, 0, ARC_OPERAND_SIGNED
| ARC_OPERAND_NCHK
,
1014 insert_simm3s
, extract_simm3s
},
1016 /* UIMM7_A32_11_S mask = 0000000000011111. */
1017 #define UIMM7_A32_11_S (SIMM3_5_S + 1)
1018 {7, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_ALIGNED32
1019 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_IGNORE
, insert_uimm7_a32_11_s
,
1020 extract_uimm7_a32_11_s
},
1022 /* UIMM7_9_S mask = 0000000001111111. */
1023 #define UIMM7_9_S (UIMM7_A32_11_S + 1)
1024 {7, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm7_9_s
, extract_uimm7_9_s
},
1026 /* UIMM3_13_S mask = 0000000000000111. */
1027 #define UIMM3_13_S (UIMM7_9_S + 1)
1028 {3, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm3_13_s
, extract_uimm3_13_s
},
1030 /* SIMM11_A32_7_S mask = 0000000111111111. */
1031 #define SIMM11_A32_7_S (UIMM3_13_S + 1)
1032 {11, 0, BFD_RELOC_ARC_SDA16_LD2
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED32
1033 | ARC_OPERAND_TRUNCATE
, insert_simm11_a32_7_s
, extract_simm11_a32_7_s
},
1035 /* UIMM6_13_S mask = 0000000002220111. */
1036 #define UIMM6_13_S (SIMM11_A32_7_S + 1)
1037 {6, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm6_13_s
, extract_uimm6_13_s
},
1038 /* UIMM5_11_S mask = 0000000000011111. */
1039 #define UIMM5_11_S (UIMM6_13_S + 1)
1040 {5, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_IGNORE
, insert_uimm5_11_s
,
1041 extract_uimm5_11_s
},
1043 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
1044 #define SIMM9_A16_8 (UIMM5_11_S + 1)
1045 {9, 0, -SIMM9_A16_8
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED16
1046 | ARC_OPERAND_PCREL
| ARC_OPERAND_TRUNCATE
, insert_simm9_a16_8
,
1047 extract_simm9_a16_8
},
1049 /* UIMM6_8 mask = 00000000000000000000111111000000. */
1050 #define UIMM6_8 (SIMM9_A16_8 + 1)
1051 {6, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm6_8
, extract_uimm6_8
},
1053 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
1054 #define SIMM21_A16_5 (UIMM6_8 + 1)
1055 {21, 0, BFD_RELOC_ARC_S21H_PCREL
, ARC_OPERAND_SIGNED
1056 | ARC_OPERAND_ALIGNED16
| ARC_OPERAND_TRUNCATE
,
1057 insert_simm21_a16_5
, extract_simm21_a16_5
},
1059 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
1060 #define SIMM25_A16_5 (SIMM21_A16_5 + 1)
1061 {25, 0, BFD_RELOC_ARC_S25H_PCREL
, ARC_OPERAND_SIGNED
1062 | ARC_OPERAND_ALIGNED16
| ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
,
1063 insert_simm25_a16_5
, extract_simm25_a16_5
},
1065 /* SIMM10_A16_7_S mask = 0000000111111111. */
1066 #define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
1067 {10, 0, -SIMM10_A16_7_S
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED16
1068 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_simm10_a16_7_s
,
1069 extract_simm10_a16_7_s
},
1071 #define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
1072 {10, 0, -SIMM10_A16_7_Sbis
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED16
1073 | ARC_OPERAND_TRUNCATE
, insert_simm10_a16_7_s
, extract_simm10_a16_7_s
},
1075 /* SIMM7_A16_10_S mask = 0000000000111111. */
1076 #define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
1077 {7, 0, -SIMM7_A16_10_S
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED16
1078 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_simm7_a16_10_s
,
1079 extract_simm7_a16_10_s
},
1081 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
1082 #define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
1083 {21, 0, BFD_RELOC_ARC_S21W_PCREL
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED32
1084 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_simm21_a32_5
,
1085 extract_simm21_a32_5
},
1087 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
1088 #define SIMM25_A32_5 (SIMM21_A32_5 + 1)
1089 {25, 0, BFD_RELOC_ARC_S25W_PCREL
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED32
1090 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_simm25_a32_5
,
1091 extract_simm25_a32_5
},
1093 /* SIMM13_A32_5_S mask = 0000011111111111. */
1094 #define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
1095 {13, 0, BFD_RELOC_ARC_S13_PCREL
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED32
1096 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_simm13_a32_5_s
,
1097 extract_simm13_a32_5_s
},
1099 /* SIMM8_A16_9_S mask = 0000000001111111. */
1100 #define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
1101 {8, 0, -SIMM8_A16_9_S
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED16
1102 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_simm8_a16_9_s
,
1103 extract_simm8_a16_9_s
},
1105 /* UIMM3_23 mask = 00000000000000000000000111000000. */
1106 #define UIMM3_23 (SIMM8_A16_9_S + 1)
1107 {3, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm3_23
, extract_uimm3_23
},
1109 /* UIMM10_6_S mask = 0000001111111111. */
1110 #define UIMM10_6_S (UIMM3_23 + 1)
1111 {10, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm10_6_s
, extract_uimm10_6_s
},
1113 /* UIMM6_11_S mask = 0000002200011110. */
1114 #define UIMM6_11_S (UIMM10_6_S + 1)
1115 {6, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm6_11_s
, extract_uimm6_11_s
},
1117 /* SIMM9_8 mask = 00000000111111112000000000000000. */
1118 #define SIMM9_8 (UIMM6_11_S + 1)
1119 {9, 0, BFD_RELOC_ARC_SDA_LDST
, ARC_OPERAND_SIGNED
| ARC_OPERAND_IGNORE
,
1120 insert_simm9_8
, extract_simm9_8
},
1122 /* UIMM10_A32_8_S mask = 0000000011111111. */
1123 #define UIMM10_A32_8_S (SIMM9_8 + 1)
1124 {10, 0, -UIMM10_A32_8_S
, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_ALIGNED32
1125 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_uimm10_a32_8_s
,
1126 extract_uimm10_a32_8_s
},
1128 /* SIMM9_7_S mask = 0000000111111111. */
1129 #define SIMM9_7_S (UIMM10_A32_8_S + 1)
1130 {9, 0, BFD_RELOC_ARC_SDA16_LD
, ARC_OPERAND_SIGNED
, insert_simm9_7_s
,
1133 /* UIMM6_A16_11_S mask = 0000000000011111. */
1134 #define UIMM6_A16_11_S (SIMM9_7_S + 1)
1135 {6, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_ALIGNED16
1136 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_IGNORE
, insert_uimm6_a16_11_s
,
1137 extract_uimm6_a16_11_s
},
1139 /* UIMM5_A32_11_S mask = 0000020000011000. */
1140 #define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
1141 {5, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_ALIGNED32
1142 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_IGNORE
, insert_uimm5_a32_11_s
,
1143 extract_uimm5_a32_11_s
},
1145 /* SIMM11_A32_13_S mask = 0000022222200111. */
1146 #define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
1147 {11, 0, BFD_RELOC_ARC_SDA16_ST2
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED32
1148 | ARC_OPERAND_TRUNCATE
, insert_simm11_a32_13_s
, extract_simm11_a32_13_s
},
1150 /* UIMM7_13_S mask = 0000000022220111. */
1151 #define UIMM7_13_S (SIMM11_A32_13_S + 1)
1152 {7, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm7_13_s
, extract_uimm7_13_s
},
1154 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
1155 #define UIMM6_A16_21 (UIMM7_13_S + 1)
1156 {6, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_ALIGNED16
1157 | ARC_OPERAND_TRUNCATE
, insert_uimm6_a16_21
, extract_uimm6_a16_21
},
1159 /* UIMM7_11_S mask = 0000022200011110. */
1160 #define UIMM7_11_S (UIMM6_A16_21 + 1)
1161 {7, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm7_11_s
, extract_uimm7_11_s
},
1163 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
1164 #define UIMM7_A16_20 (UIMM7_11_S + 1)
1165 {7, 0, -UIMM7_A16_20
, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_ALIGNED16
1166 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_uimm7_a16_20
,
1167 extract_uimm7_a16_20
},
1169 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
1170 #define SIMM13_A16_20 (UIMM7_A16_20 + 1)
1171 {13, 0, -SIMM13_A16_20
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED16
1172 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_simm13_a16_20
,
1173 extract_simm13_a16_20
},
1175 /* UIMM8_8_S mask = 0000000011111111. */
1176 #define UIMM8_8_S (SIMM13_A16_20 + 1)
1177 {8, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm8_8_s
, extract_uimm8_8_s
},
1179 /* W6 mask = 00000000000000000000111111000000. */
1180 #define W6 (UIMM8_8_S + 1)
1181 {6, 0, 0, ARC_OPERAND_SIGNED
, insert_w6
, extract_w6
},
1183 /* UIMM6_5_S mask = 0000011111100000. */
1184 #define UIMM6_5_S (W6 + 1)
1185 {6, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm6_5_s
, extract_uimm6_5_s
},
1188 const unsigned arc_num_operands
= ARRAY_SIZE (arc_operands
);
1190 const unsigned arc_Toperand
= FKT_T
;
1191 const unsigned arc_NToperand
= FKT_NT
;
1193 /* The opcode table.
1195 The format of the opcode table is:
1197 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }. */
1198 const struct arc_opcode arc_opcodes
[] =
1200 #include "arc-tbl.h"
1203 const unsigned arc_num_opcodes
= ARRAY_SIZE (arc_opcodes
);
1205 /* List with special cases instructions and the applicable flags. */
1206 const struct arc_flag_special arc_flag_special_cases
[] =
1208 { "b", { F_ALWAYS
, F_RA
, F_EQUAL
, F_ZERO
, F_NOTEQUAL
, F_NOTZERO
, F_POZITIVE
,
1209 F_PL
, F_NEGATIVE
, F_MINUS
, F_CARRY
, F_CARRYSET
, F_LOWER
, F_CARRYCLR
,
1210 F_NOTCARRY
, F_HIGHER
, F_OVERFLOWSET
, F_OVERFLOW
, F_NOTOVERFLOW
,
1211 F_OVERFLOWCLR
, F_GT
, F_GE
, F_LT
, F_LE
, F_HI
, F_LS
, F_PNZ
, F_NULL
} },
1212 { "bl", { F_ALWAYS
, F_RA
, F_EQUAL
, F_ZERO
, F_NOTEQUAL
, F_NOTZERO
, F_POZITIVE
,
1213 F_PL
, F_NEGATIVE
, F_MINUS
, F_CARRY
, F_CARRYSET
, F_LOWER
, F_CARRYCLR
,
1214 F_NOTCARRY
, F_HIGHER
, F_OVERFLOWSET
, F_OVERFLOW
, F_NOTOVERFLOW
,
1215 F_OVERFLOWCLR
, F_GT
, F_GE
, F_LT
, F_LE
, F_HI
, F_LS
, F_PNZ
, F_NULL
} },
1216 { "br", { F_ALWAYS
, F_RA
, F_EQUAL
, F_ZERO
, F_NOTEQUAL
, F_NOTZERO
, F_POZITIVE
,
1217 F_PL
, F_NEGATIVE
, F_MINUS
, F_CARRY
, F_CARRYSET
, F_LOWER
, F_CARRYCLR
,
1218 F_NOTCARRY
, F_HIGHER
, F_OVERFLOWSET
, F_OVERFLOW
, F_NOTOVERFLOW
,
1219 F_OVERFLOWCLR
, F_GT
, F_GE
, F_LT
, F_LE
, F_HI
, F_LS
, F_PNZ
, F_NULL
} },
1220 { "j", { F_ALWAYS
, F_RA
, F_EQUAL
, F_ZERO
, F_NOTEQUAL
, F_NOTZERO
, F_POZITIVE
,
1221 F_PL
, F_NEGATIVE
, F_MINUS
, F_CARRY
, F_CARRYSET
, F_LOWER
, F_CARRYCLR
,
1222 F_NOTCARRY
, F_HIGHER
, F_OVERFLOWSET
, F_OVERFLOW
, F_NOTOVERFLOW
,
1223 F_OVERFLOWCLR
, F_GT
, F_GE
, F_LT
, F_LE
, F_HI
, F_LS
, F_PNZ
, F_NULL
} },
1224 { "jl", { F_ALWAYS
, F_RA
, F_EQUAL
, F_ZERO
, F_NOTEQUAL
, F_NOTZERO
, F_POZITIVE
,
1225 F_PL
, F_NEGATIVE
, F_MINUS
, F_CARRY
, F_CARRYSET
, F_LOWER
, F_CARRYCLR
,
1226 F_NOTCARRY
, F_HIGHER
, F_OVERFLOWSET
, F_OVERFLOW
, F_NOTOVERFLOW
,
1227 F_OVERFLOWCLR
, F_GT
, F_GE
, F_LT
, F_LE
, F_HI
, F_LS
, F_PNZ
, F_NULL
} },
1228 { "lp", { F_ALWAYS
, F_RA
, F_EQUAL
, F_ZERO
, F_NOTEQUAL
, F_NOTZERO
, F_POZITIVE
,
1229 F_PL
, F_NEGATIVE
, F_MINUS
, F_CARRY
, F_CARRYSET
, F_LOWER
, F_CARRYCLR
,
1230 F_NOTCARRY
, F_HIGHER
, F_OVERFLOWSET
, F_OVERFLOW
, F_NOTOVERFLOW
,
1231 F_OVERFLOWCLR
, F_GT
, F_GE
, F_LT
, F_LE
, F_HI
, F_LS
, F_PNZ
, F_NULL
} },
1232 { "set", { F_ALWAYS
, F_RA
, F_EQUAL
, F_ZERO
, F_NOTEQUAL
, F_NOTZERO
, F_POZITIVE
,
1233 F_PL
, F_NEGATIVE
, F_MINUS
, F_CARRY
, F_CARRYSET
, F_LOWER
, F_CARRYCLR
,
1234 F_NOTCARRY
, F_HIGHER
, F_OVERFLOWSET
, F_OVERFLOW
, F_NOTOVERFLOW
,
1235 F_OVERFLOWCLR
, F_GT
, F_GE
, F_LT
, F_LE
, F_HI
, F_LS
, F_PNZ
, F_NULL
} },
1236 { "ld", { F_SIZEB17
, F_SIZEW17
, F_H17
, F_NULL
} },
1237 { "st", { F_SIZEB1
, F_SIZEW1
, F_H1
, F_NULL
} }
1240 const unsigned arc_num_flag_special
= ARRAY_SIZE (arc_flag_special_cases
);
1244 #define DEF(NAME, EXC1, EXC2, RELOC1, RELOC2) \
1245 { #NAME, EXC1, EXC2, RELOC1, RELOC2}
1247 const struct arc_reloc_equiv_tab arc_reloc_equiv
[] =
1249 DEF (sda
, "ld", F_AS9
, BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST2
),
1250 DEF (sda
, "st", F_AS9
, BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST2
),
1251 DEF (sda
, "ldw", F_AS9
, BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST1
),
1252 DEF (sda
, "ldh", F_AS9
, BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST1
),
1253 DEF (sda
, "stw", F_AS9
, BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST1
),
1254 DEF (sda
, "sth", F_AS9
, BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST1
),
1256 /* Short instructions. */
1257 DEF (sda
, 0, F_NULL
, BFD_RELOC_ARC_SDA16_LD
, BFD_RELOC_ARC_SDA16_LD
),
1258 DEF (sda
, 0, F_NULL
, -SIMM10_A16_7_Sbis
, BFD_RELOC_ARC_SDA16_LD1
),
1259 DEF (sda
, 0, F_NULL
, BFD_RELOC_ARC_SDA16_LD2
, BFD_RELOC_ARC_SDA16_LD2
),
1260 DEF (sda
, 0, F_NULL
, BFD_RELOC_ARC_SDA16_ST2
, BFD_RELOC_ARC_SDA16_ST2
),
1262 DEF (sda
, 0, F_NULL
, BFD_RELOC_ARC_32_ME
, BFD_RELOC_ARC_SDA32_ME
),
1263 DEF (sda
, 0, F_NULL
, BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST
),
1265 DEF (plt
, 0, F_NULL
, BFD_RELOC_ARC_S25H_PCREL
,
1266 BFD_RELOC_ARC_S25H_PCREL_PLT
),
1267 DEF (plt
, 0, F_NULL
, BFD_RELOC_ARC_S21H_PCREL
,
1268 BFD_RELOC_ARC_S21H_PCREL_PLT
),
1269 DEF (plt
, 0, F_NULL
, BFD_RELOC_ARC_S25W_PCREL
,
1270 BFD_RELOC_ARC_S25W_PCREL_PLT
),
1271 DEF (plt
, 0, F_NULL
, BFD_RELOC_ARC_S21W_PCREL
,
1272 BFD_RELOC_ARC_S21W_PCREL_PLT
),
1274 DEF (plt
, 0, F_NULL
, BFD_RELOC_ARC_32_ME
, BFD_RELOC_ARC_PLT32
),
1277 const unsigned arc_num_equiv_tab
= ARRAY_SIZE (arc_reloc_equiv
);
1279 const struct arc_pseudo_insn arc_pseudo_insns
[] =
1281 { "push", "st", ".aw", 5, { { RC
, 0, 0, 0 }, { BRAKET
, 1, 0, 1 },
1282 { RB
, 1, 28, 2 }, { SIMM9_8
, 1, -4, 3 },
1283 { BRAKETdup
, 1, 0, 4} } },
1284 { "pop", "ld", ".ab", 5, { { RA
, 0, 0, 0 }, { BRAKET
, 1, 0, 1 },
1285 { RB
, 1, 28, 2 }, { SIMM9_8
, 1, 4, 3 },
1286 { BRAKETdup
, 1, 0, 4} } },
1288 { "brgt", "brlt", NULL
, 3, { { RB
, 0, 0, 1 }, { RC
, 0, 0, 0 },
1289 { SIMM9_A16_8
, 0, 0, 2 } } },
1290 { "brgt", "brge", NULL
, 3, { { RB
, 0, 0, 0 }, { UIMM6_8
, 0, 1, 1 },
1291 { SIMM9_A16_8
, 0, 0, 2 } } },
1292 { "brgt", "brlt", NULL
, 3, { { RB
, 0, 0, 1 }, { LIMM
, 0, 0, 0 },
1293 { SIMM9_A16_8
, 0, 0, 2 } } },
1294 { "brgt", "brlt", NULL
, 3, { { LIMM
, 0, 0, 1 }, { RC
, 0, 0, 0 },
1295 { SIMM9_A16_8
, 0, 0, 2 } } },
1296 { "brgt", "brge", NULL
, 3, { { LIMM
, 0, 0, 0 }, { UIMM6_8
, 0, 1, 1 },
1297 { SIMM9_A16_8
, 0, 0, 2 } } },
1299 { "brhi", "brlo", NULL
, 3, { { RB
, 0, 0, 1 }, { RC
, 0, 0, 0 },
1300 { SIMM9_A16_8
, 0, 0, 2 } } },
1301 { "brhi", "brhs", NULL
, 3, { { RB
, 0, 0, 0 }, { UIMM6_8
, 0, 1, 1 },
1302 { SIMM9_A16_8
, 0, 0, 2 } } },
1303 { "brhi", "brlo", NULL
, 3, { { RB
, 0, 0, 1 }, { LIMM
, 0, 0, 0 },
1304 { SIMM9_A16_8
, 0, 0, 2 } } },
1305 { "brhi", "brlo", NULL
, 3, { { LIMM
, 0, 0, 1 }, { RC
, 0, 0, 0 },
1306 { SIMM9_A16_8
, 0, 0, 2 } } },
1307 { "brhi", "brhs", NULL
, 3, { { LIMM
, 0, 0, 0 }, { UIMM6_8
, 0, 1, 1 },
1308 { SIMM9_A16_8
, 0, 0, 2 } } },
1310 { "brle", "brge", NULL
, 3, { { RB
, 0, 0, 1 }, { RC
, 0, 0, 0 },
1311 { SIMM9_A16_8
, 0, 0, 2 } } },
1312 { "brle", "brlt", NULL
, 3, { { RB
, 0, 0, 0 }, { UIMM6_8
, 0, 1, 1 },
1313 { SIMM9_A16_8
, 0, 0, 2 } } },
1314 { "brle", "brge", NULL
, 3, { { RB
, 0, 0, 1 }, { LIMM
, 0, 0, 0 },
1315 { SIMM9_A16_8
, 0, 0, 2 } } },
1316 { "brle", "brge", NULL
, 3, { { LIMM
, 0, 0, 1 }, { RC
, 0, 0, 0 },
1317 { SIMM9_A16_8
, 0, 0, 2 } } },
1318 { "brle", "brlt", NULL
, 3, { { LIMM
, 0, 0, 0 }, { UIMM6_8
, 0, 1, 1 },
1319 { SIMM9_A16_8
, 0, 0, 2 } } },
1321 { "brls", "brhs", NULL
, 3, { { RB
, 0, 0, 1 }, { RC
, 0, 0, 0 },
1322 { SIMM9_A16_8
, 0, 0, 2 } } },
1323 { "brls", "brlo", NULL
, 3, { { RB
, 0, 0, 0 }, { UIMM6_8
, 0, 1, 1 },
1324 { SIMM9_A16_8
, 0, 0, 2 } } },
1325 { "brls", "brhs", NULL
, 3, { { RB
, 0, 0, 1 }, { LIMM
, 0, 0, 0 },
1326 { SIMM9_A16_8
, 0, 0, 2 } } },
1327 { "brls", "brhs", NULL
, 3, { { LIMM
, 0, 0, 1 }, { RC
, 0, 0, 0 },
1328 { SIMM9_A16_8
, 0, 0, 2 } } },
1329 { "brls", "brlo", NULL
, 3, { { LIMM
, 0, 0, 0 }, { UIMM6_8
, 0, 1, 1 },
1330 { SIMM9_A16_8
, 0, 0, 2 } } },
1333 const unsigned arc_num_pseudo_insn
=
1334 sizeof (arc_pseudo_insns
) / sizeof (*arc_pseudo_insns
);
1336 const struct arc_aux_reg arc_aux_regs
[] =
1339 #define DEF(ADDR, NAME) \
1340 { ADDR, #NAME, sizeof (#NAME)-1 },
1342 #include "arc-regs.h"
1347 const unsigned arc_num_aux_regs
= ARRAY_SIZE (arc_aux_regs
);