opcodes/arc-opc.c

   1 /* Opcode table for the ARC.
   2    Copyright (C) 1994-2016 Free Software Foundation, Inc.
   3
   4    Contributed by Claudiu Zissulescu (claziss@synopsys.com)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software Foundation,
  20    Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  21
  22 #include "sysdep.h"
  23 #include <stdio.h>
  24 #include "bfd.h"
  25 #include "opcode/arc.h"
  26 #include "opintl.h"
  27 #include "libiberty.h"
  28
  29 /* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
  30    instructions.  Support for this target is available when binutils is
  31    configured and built for the 'arc*-mellanox-*-*' target.  As far as
  32    possible all ARC NPS400 features are built into all ARC target builds as
  33    this reduces the chances that regressions might creep in.  */
  34
  35 /* Insert RB register into a 32-bit opcode.  */
  36 static unsigned
  37 insert_rb (unsigned insn,
  38            int value,
  39            const char **errmsg ATTRIBUTE_UNUSED)
  40 {
  41   return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
  42 }
  43
  44 static int
  45 extract_rb (unsigned insn ATTRIBUTE_UNUSED,
  46             bfd_boolean * invalid ATTRIBUTE_UNUSED)
  47 {
  48   int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
  49
  50   if (value == 0x3e && invalid)
  51     *invalid = TRUE; /* A limm operand, it should be extracted in a
  52                         different way.  */
  53
  54   return value;
  55 }
  56
  57 static unsigned
  58 insert_rad (unsigned insn,
  59             int value,
  60             const char **errmsg ATTRIBUTE_UNUSED)
  61 {
  62   if (value & 0x01)
  63     *errmsg = _("Improper register value.");
  64
  65   return insn | (value & 0x3F);
  66 }
  67
  68 static unsigned
  69 insert_rcd (unsigned insn,
  70             int value,
  71             const char **errmsg ATTRIBUTE_UNUSED)
  72 {
  73   if (value & 0x01)
  74     *errmsg = _("Improper register value.");
  75
  76   return insn | ((value & 0x3F) << 6);
  77 }
  78
  79 /* Dummy insert ZERO operand function.  */
  80
  81 static unsigned
  82 insert_za (unsigned insn,
  83            int value,
  84            const char **errmsg)
  85 {
  86   if (value)
  87     *errmsg = _("operand is not zero");
  88   return insn;
  89 }
  90
  91 /* Insert Y-bit in bbit/br instructions.  This function is called only
  92    when solving fixups.  */
  93
  94 static unsigned
  95 insert_Ybit (unsigned insn,
  96              int value,
  97              const char **errmsg ATTRIBUTE_UNUSED)
  98 {
  99   if (value > 0)
 100     insn |= 0x08;
 101
 102   return insn;
 103 }
 104
 105 /* Insert Y-bit in bbit/br instructions.  This function is called only
 106    when solving fixups.  */
 107
 108 static unsigned
 109 insert_NYbit (unsigned insn,
 110               int value,
 111               const char **errmsg ATTRIBUTE_UNUSED)
 112 {
 113   if (value < 0)
 114     insn |= 0x08;
 115
 116   return insn;
 117 }
 118
 119 /* Insert H register into a 16-bit opcode.  */
 120
 121 static unsigned
 122 insert_rhv1 (unsigned insn,
 123              int value,
 124              const char **errmsg ATTRIBUTE_UNUSED)
 125 {
 126   return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
 127 }
 128
 129 static int
 130 extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED,
 131               bfd_boolean * invalid ATTRIBUTE_UNUSED)
 132 {
 133   int value = 0;
 134
 135   return value;
 136 }
 137
 138 /* Insert H register into a 16-bit opcode.  */
 139
 140 static unsigned
 141 insert_rhv2 (unsigned insn,
 142              int value,
 143              const char **errmsg)
 144 {
 145   if (value == 0x1E)
 146     *errmsg =
 147       _("Register R30 is a limm indicator for this type of instruction.");
 148   return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
 149 }
 150
 151 static int
 152 extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED,
 153               bfd_boolean * invalid ATTRIBUTE_UNUSED)
 154 {
 155   int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
 156
 157   return value;
 158 }
 159
 160 static unsigned
 161 insert_r0 (unsigned insn,
 162            int value,
 163            const char **errmsg ATTRIBUTE_UNUSED)
 164 {
 165   if (value != 0)
 166     *errmsg = _("Register must be R0.");
 167   return insn;
 168 }
 169
 170 static int
 171 extract_r0 (unsigned insn ATTRIBUTE_UNUSED,
 172             bfd_boolean * invalid ATTRIBUTE_UNUSED)
 173 {
 174   return 0;
 175 }
 176
 177
 178 static unsigned
 179 insert_r1 (unsigned insn,
 180            int value,
 181            const char **errmsg ATTRIBUTE_UNUSED)
 182 {
 183   if (value != 1)
 184     *errmsg = _("Register must be R1.");
 185   return insn;
 186 }
 187
 188 static int
 189 extract_r1 (unsigned insn ATTRIBUTE_UNUSED,
 190             bfd_boolean * invalid ATTRIBUTE_UNUSED)
 191 {
 192   return 1;
 193 }
 194
 195 static unsigned
 196 insert_r2 (unsigned insn,
 197            int value,
 198            const char **errmsg ATTRIBUTE_UNUSED)
 199 {
 200   if (value != 2)
 201     *errmsg = _("Register must be R2.");
 202   return insn;
 203 }
 204
 205 static int
 206 extract_r2 (unsigned insn ATTRIBUTE_UNUSED,
 207             bfd_boolean * invalid ATTRIBUTE_UNUSED)
 208 {
 209   return 2;
 210 }
 211
 212 static unsigned
 213 insert_r3 (unsigned insn,
 214            int value,
 215            const char **errmsg ATTRIBUTE_UNUSED)
 216 {
 217   if (value != 3)
 218     *errmsg = _("Register must be R3.");
 219   return insn;
 220 }
 221
 222 static int
 223 extract_r3 (unsigned insn ATTRIBUTE_UNUSED,
 224             bfd_boolean * invalid ATTRIBUTE_UNUSED)
 225 {
 226   return 3;
 227 }
 228
 229 static unsigned
 230 insert_sp (unsigned insn,
 231            int value,
 232            const char **errmsg ATTRIBUTE_UNUSED)
 233 {
 234   if (value != 28)
 235     *errmsg = _("Register must be SP.");
 236   return insn;
 237 }
 238
 239 static int
 240 extract_sp (unsigned insn ATTRIBUTE_UNUSED,
 241             bfd_boolean * invalid ATTRIBUTE_UNUSED)
 242 {
 243   return 28;
 244 }
 245
 246 static unsigned
 247 insert_gp (unsigned insn,
 248            int value,
 249            const char **errmsg ATTRIBUTE_UNUSED)
 250 {
 251   if (value != 26)
 252     *errmsg = _("Register must be GP.");
 253   return insn;
 254 }
 255
 256 static int
 257 extract_gp (unsigned insn ATTRIBUTE_UNUSED,
 258             bfd_boolean * invalid ATTRIBUTE_UNUSED)
 259 {
 260   return 26;
 261 }
 262
 263 static unsigned
 264 insert_pcl (unsigned insn,
 265             int value,
 266             const char **errmsg ATTRIBUTE_UNUSED)
 267 {
 268   if (value != 63)
 269     *errmsg = _("Register must be PCL.");
 270   return insn;
 271 }
 272
 273 static int
 274 extract_pcl (unsigned insn ATTRIBUTE_UNUSED,
 275              bfd_boolean * invalid ATTRIBUTE_UNUSED)
 276 {
 277   return 63;
 278 }
 279
 280 static unsigned
 281 insert_blink (unsigned insn,
 282               int value,
 283               const char **errmsg ATTRIBUTE_UNUSED)
 284 {
 285   if (value != 31)
 286     *errmsg = _("Register must be BLINK.");
 287   return insn;
 288 }
 289
 290 static int
 291 extract_blink (unsigned insn ATTRIBUTE_UNUSED,
 292                bfd_boolean * invalid ATTRIBUTE_UNUSED)
 293 {
 294   return 31;
 295 }
 296
 297 static unsigned
 298 insert_ilink1 (unsigned insn,
 299                int value,
 300                const char **errmsg ATTRIBUTE_UNUSED)
 301 {
 302   if (value != 29)
 303     *errmsg = _("Register must be ILINK1.");
 304   return insn;
 305 }
 306
 307 static int
 308 extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED,
 309                 bfd_boolean * invalid ATTRIBUTE_UNUSED)
 310 {
 311   return 29;
 312 }
 313
 314 static unsigned
 315 insert_ilink2 (unsigned insn,
 316                int value,
 317                const char **errmsg ATTRIBUTE_UNUSED)
 318 {
 319   if (value != 30)
 320     *errmsg = _("Register must be ILINK2.");
 321   return insn;
 322 }
 323
 324 static int
 325 extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED,
 326                 bfd_boolean * invalid ATTRIBUTE_UNUSED)
 327 {
 328   return 30;
 329 }
 330
 331 static unsigned
 332 insert_ras (unsigned insn,
 333             int value,
 334             const char **errmsg ATTRIBUTE_UNUSED)
 335 {
 336   switch (value)
 337     {
 338     case 0:
 339     case 1:
 340     case 2:
 341     case 3:
 342       insn |= value;
 343       break;
 344     case 12:
 345     case 13:
 346     case 14:
 347     case 15:
 348       insn |= (value - 8);
 349       break;
 350     default:
 351       *errmsg = _("Register must be either r0-r3 or r12-r15.");
 352       break;
 353     }
 354   return insn;
 355 }
 356
 357 static int
 358 extract_ras (unsigned insn ATTRIBUTE_UNUSED,
 359              bfd_boolean * invalid ATTRIBUTE_UNUSED)
 360 {
 361   int value = insn & 0x07;
 362   if (value > 3)
 363     return (value + 8);
 364   else
 365     return value;
 366 }
 367
 368 static unsigned
 369 insert_rbs (unsigned insn,
 370             int value,
 371             const char **errmsg ATTRIBUTE_UNUSED)
 372 {
 373   switch (value)
 374     {
 375     case 0:
 376     case 1:
 377     case 2:
 378     case 3:
 379       insn |= value << 8;
 380       break;
 381     case 12:
 382     case 13:
 383     case 14:
 384     case 15:
 385       insn |= ((value - 8)) << 8;
 386       break;
 387     default:
 388       *errmsg = _("Register must be either r0-r3 or r12-r15.");
 389       break;
 390     }
 391   return insn;
 392 }
 393
 394 static int
 395 extract_rbs (unsigned insn ATTRIBUTE_UNUSED,
 396              bfd_boolean * invalid ATTRIBUTE_UNUSED)
 397 {
 398   int value = (insn >> 8) & 0x07;
 399   if (value > 3)
 400     return (value + 8);
 401   else
 402     return value;
 403 }
 404
 405 static unsigned
 406 insert_rcs (unsigned insn,
 407             int value,
 408             const char **errmsg ATTRIBUTE_UNUSED)
 409 {
 410   switch (value)
 411     {
 412     case 0:
 413     case 1:
 414     case 2:
 415     case 3:
 416       insn |= value << 5;
 417       break;
 418     case 12:
 419     case 13:
 420     case 14:
 421     case 15:
 422       insn |= ((value - 8)) << 5;
 423       break;
 424     default:
 425       *errmsg = _("Register must be either r0-r3 or r12-r15.");
 426       break;
 427     }
 428   return insn;
 429 }
 430
 431 static int
 432 extract_rcs (unsigned insn ATTRIBUTE_UNUSED,
 433              bfd_boolean * invalid ATTRIBUTE_UNUSED)
 434 {
 435   int value = (insn >> 5) & 0x07;
 436   if (value > 3)
 437     return (value + 8);
 438   else
 439     return value;
 440 }
 441
 442 static unsigned
 443 insert_simm3s (unsigned insn,
 444                int value,
 445                const char **errmsg ATTRIBUTE_UNUSED)
 446 {
 447   int tmp = 0;
 448   switch (value)
 449     {
 450     case -1:
 451       tmp = 0x07;
 452       break;
 453     case 0:
 454       tmp = 0x00;
 455       break;
 456     case 1:
 457       tmp = 0x01;
 458       break;
 459     case 2:
 460       tmp = 0x02;
 461       break;
 462     case 3:
 463       tmp = 0x03;
 464       break;
 465     case 4:
 466       tmp = 0x04;
 467       break;
 468     case 5:
 469       tmp = 0x05;
 470       break;
 471     case 6:
 472       tmp = 0x06;
 473       break;
 474     default:
 475       *errmsg = _("Accepted values are from -1 to 6.");
 476       break;
 477     }
 478
 479   insn |= tmp << 8;
 480   return insn;
 481 }
 482
 483 static int
 484 extract_simm3s (unsigned insn ATTRIBUTE_UNUSED,
 485                 bfd_boolean * invalid ATTRIBUTE_UNUSED)
 486 {
 487   int value = (insn >> 8) & 0x07;
 488   if (value == 7)
 489     return -1;
 490   else
 491     return value;
 492 }
 493
 494 static unsigned
 495 insert_rrange (unsigned insn,
 496                int value,
 497                const char **errmsg ATTRIBUTE_UNUSED)
 498 {
 499   int reg1 = (value >> 16) & 0xFFFF;
 500   int reg2 = value & 0xFFFF;
 501   if (reg1 != 13)
 502     {
 503       *errmsg = _("First register of the range should be r13.");
 504       return insn;
 505     }
 506   if (reg2 < 13 || reg2 > 26)
 507     {
 508       *errmsg = _("Last register of the range doesn't fit.");
 509       return insn;
 510     }
 511   insn |= ((reg2 - 12) & 0x0F) << 1;
 512   return insn;
 513 }
 514
 515 static int
 516 extract_rrange (unsigned insn  ATTRIBUTE_UNUSED,
 517                 bfd_boolean * invalid  ATTRIBUTE_UNUSED)
 518 {
 519   return (insn >> 1) & 0x0F;
 520 }
 521
 522 static unsigned
 523 insert_fpel (unsigned insn,
 524              int value,
 525              const char **errmsg ATTRIBUTE_UNUSED)
 526 {
 527   if (value != 27)
 528     {
 529       *errmsg = _("Invalid register number, should be fp.");
 530       return insn;
 531     }
 532
 533   insn |= 0x0100;
 534   return insn;
 535 }
 536
 537 static int
 538 extract_fpel (unsigned insn  ATTRIBUTE_UNUSED,
 539               bfd_boolean * invalid  ATTRIBUTE_UNUSED)
 540 {
 541   return (insn & 0x0100) ? 27 : -1;
 542 }
 543
 544 static unsigned
 545 insert_blinkel (unsigned insn,
 546                 int value,
 547                 const char **errmsg ATTRIBUTE_UNUSED)
 548 {
 549   if (value != 31)
 550     {
 551       *errmsg = _("Invalid register number, should be blink.");
 552       return insn;
 553     }
 554
 555   insn |= 0x0200;
 556   return insn;
 557 }
 558
 559 static int
 560 extract_blinkel (unsigned insn  ATTRIBUTE_UNUSED,
 561                  bfd_boolean * invalid  ATTRIBUTE_UNUSED)
 562 {
 563   return (insn & 0x0200) ? 31 : -1;
 564 }
 565
 566 static unsigned
 567 insert_pclel (unsigned insn,
 568               int value,
 569               const char **errmsg ATTRIBUTE_UNUSED)
 570 {
 571   if (value != 63)
 572     {
 573       *errmsg = _("Invalid register number, should be pcl.");
 574       return insn;
 575     }
 576
 577   insn |= 0x0400;
 578   return insn;
 579 }
 580
 581 static int
 582 extract_pclel (unsigned insn  ATTRIBUTE_UNUSED,
 583                bfd_boolean * invalid  ATTRIBUTE_UNUSED)
 584 {
 585   return (insn & 0x0400) ? 63 : -1;
 586 }
 587
 588 #define INSERT_W6
 589 /* mask = 00000000000000000000111111000000
 590    insn = 00011bbb000000000BBBwwwwwwDaaZZ1.  */
 591 static unsigned
 592 insert_w6 (unsigned insn ATTRIBUTE_UNUSED,
 593            int value ATTRIBUTE_UNUSED,
 594            const char **errmsg ATTRIBUTE_UNUSED)
 595 {
 596   insn |= ((value >> 0) & 0x003f) << 6;
 597
 598   return insn;
 599 }
 600
 601 #define EXTRACT_W6
 602 /* mask = 00000000000000000000111111000000.  */
 603 static int
 604 extract_w6 (unsigned insn ATTRIBUTE_UNUSED,
 605             bfd_boolean * invalid ATTRIBUTE_UNUSED)
 606 {
 607   unsigned value = 0;
 608
 609   value |= ((insn >> 6) & 0x003f) << 0;
 610
 611   return value;
 612 }
 613
 614 #define INSERT_G_S
 615 /* mask = 0000011100022000
 616    insn = 01000ggghhhGG0HH.  */
 617 static unsigned
 618 insert_g_s (unsigned insn ATTRIBUTE_UNUSED,
 619             int value ATTRIBUTE_UNUSED,
 620             const char **errmsg ATTRIBUTE_UNUSED)
 621 {
 622   insn |= ((value >> 0) & 0x0007) << 8;
 623   insn |= ((value >> 3) & 0x0003) << 3;
 624
 625   return insn;
 626 }
 627
 628 #define EXTRACT_G_S
 629 /* mask = 0000011100022000.  */
 630 static int
 631 extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
 632              bfd_boolean * invalid ATTRIBUTE_UNUSED)
 633 {
 634   int value = 0;
 635
 636   value |= ((insn >> 8) & 0x0007) << 0;
 637   value |= ((insn >> 3) & 0x0003) << 3;
 638
 639   /* Extend the sign.  */
 640   int signbit = 1 << (6 - 1);
 641   value = (value ^ signbit) - signbit;
 642
 643   return value;
 644 }
 645
 646 /* ARC NPS400 Support: See comment near head of file.  */
 647 static unsigned
 648 insert_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
 649                      int value ATTRIBUTE_UNUSED,
 650                      const char **errmsg ATTRIBUTE_UNUSED)
 651 {
 652   switch (value)
 653     {
 654     case 0:
 655     case 1:
 656     case 2:
 657     case 3:
 658       insn |= value << 24;
 659       break;
 660     case 12:
 661     case 13:
 662     case 14:
 663     case 15:
 664       insn |= (value - 8) << 24;
 665       break;
 666     default:
 667       *errmsg = _("Register must be either r0-r3 or r12-r15.");
 668       break;
 669     }
 670   return insn;
 671 }
 672
 673 static int
 674 extract_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
 675                       bfd_boolean * invalid ATTRIBUTE_UNUSED)
 676 {
 677   int value = (insn >> 24) & 0x07;
 678   if (value > 3)
 679     return (value + 8);
 680   else
 681     return value;
 682 }
 683
 684 static unsigned
 685 insert_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
 686                       int value ATTRIBUTE_UNUSED,
 687                       const char **errmsg ATTRIBUTE_UNUSED)
 688 {
 689   switch (value)
 690     {
 691     case 0:
 692     case 1:
 693     case 2:
 694     case 3:
 695       insn |= value << 21;
 696       break;
 697     case 12:
 698     case 13:
 699     case 14:
 700     case 15:
 701       insn |= (value - 8) << 21;
 702       break;
 703     default:
 704       *errmsg = _("Register must be either r0-r3 or r12-r15.");
 705       break;
 706     }
 707   return insn;
 708 }
 709
 710 static int
 711 extract_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
 712                        bfd_boolean * invalid ATTRIBUTE_UNUSED)
 713 {
 714   int value = (insn >> 21) & 0x07;
 715   if (value > 3)
 716     return (value + 8);
 717   else
 718     return value;
 719 }
 720
 721 static unsigned
 722 insert_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
 723                       int value ATTRIBUTE_UNUSED,
 724                       const char **errmsg ATTRIBUTE_UNUSED)
 725 {
 726   if (value < 1 || value > 32)
 727     {
 728       *errmsg = _("Invalid bit size, should be between 1 and 32 inclusive.");
 729       return insn;
 730     }
 731
 732   --value;
 733   insn |= ((value & 0x1f) << 10);
 734   return insn;
 735 }
 736
 737 static int
 738 extract_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
 739                        bfd_boolean * invalid ATTRIBUTE_UNUSED)
 740 {
 741   return ((insn >> 10) & 0x1f) + 1;
 742 }
 743
 744 static unsigned
 745 insert_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
 746                           int value ATTRIBUTE_UNUSED,
 747                           const char **errmsg ATTRIBUTE_UNUSED)
 748 {
 749   switch (value)
 750     {
 751     case 1:
 752       value = 0;
 753       break;
 754     case 2:
 755       value = 1;
 756       break;
 757     case 4:
 758       value = 2;
 759       break;
 760     case 8:
 761       value = 3;
 762       break;
 763     default:
 764       value = 0;
 765       *errmsg = _("Invalid size, should be 1, 2, 4, or 8.");
 766       break;
 767     }
 768
 769   insn |= value << 10;
 770   return insn;
 771 }
 772
 773 static int
 774 extract_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
 775                            bfd_boolean * invalid ATTRIBUTE_UNUSED)
 776 {
 777   return  1 << ((insn >> 10) & 0x3);
 778 }
 779
 780 static unsigned
 781 insert_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
 782                         int value ATTRIBUTE_UNUSED,
 783                         const char **errmsg ATTRIBUTE_UNUSED)
 784 {
 785   insn |= ((value >> 5) & 7) << 12;
 786   insn |= (value & 0x1f);
 787   return insn;
 788 }
 789
 790 static int
 791 extract_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
 792                          bfd_boolean * invalid ATTRIBUTE_UNUSED)
 793 {
 794   return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
 795 }
 796
 797 static unsigned
 798 insert_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
 799                        int value ATTRIBUTE_UNUSED,
 800                        const char **errmsg ATTRIBUTE_UNUSED)
 801 {
 802   switch (value)
 803     {
 804     case 1:
 805     case 2:
 806     case 4:
 807       break;
 808
 809     default:
 810       *errmsg = _("invalid immediate, must be 1, 2, or 4");
 811       value = 0;
 812     }
 813
 814   insn |= (value << 6);
 815   return insn;
 816 }
 817
 818 static int
 819 extract_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
 820                          bfd_boolean * invalid ATTRIBUTE_UNUSED)
 821 {
 822   return (insn >> 6) & 0x3f;
 823 }
 824
 825 static unsigned
 826 insert_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
 827                              int value ATTRIBUTE_UNUSED,
 828                              const char **errmsg ATTRIBUTE_UNUSED)
 829 {
 830   insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
 831   return insn;
 832 }
 833
 834 static int
 835 extract_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
 836                               bfd_boolean * invalid ATTRIBUTE_UNUSED)
 837 {
 838   return (insn & 0x1f);
 839 }
 840
 841 /* Include the generic extract/insert functions.  Order is important
 842    as some of the functions present in the .h may be disabled via
 843    defines.  */
 844 #include "arc-fxi.h"
 845
 846 /* The flag operands table.
 847
 848    The format of the table is
 849    NAME CODE BITS SHIFT FAVAIL.  */
 850 const struct arc_flag_operand arc_flag_operands[] =
 851 {
 852 #define F_NULL  0
 853   { 0, 0, 0, 0, 0},
 854 #define F_ALWAYS    (F_NULL + 1)
 855   { "al", 0, 0, 0, 0 },
 856 #define F_RA        (F_ALWAYS + 1)
 857   { "ra", 0, 0, 0, 0 },
 858 #define F_EQUAL     (F_RA + 1)
 859   { "eq", 1, 5, 0, 1 },
 860 #define F_ZERO      (F_EQUAL + 1)
 861   { "z",  1, 5, 0, 0 },
 862 #define F_NOTEQUAL  (F_ZERO + 1)
 863   { "ne", 2, 5, 0, 1 },
 864 #define F_NOTZERO   (F_NOTEQUAL + 1)
 865   { "nz", 2, 5, 0, 0 },
 866 #define F_POZITIVE  (F_NOTZERO + 1)
 867   { "p",  3, 5, 0, 1 },
 868 #define F_PL        (F_POZITIVE + 1)
 869   { "pl", 3, 5, 0, 0 },
 870 #define F_NEGATIVE  (F_PL + 1)
 871   { "n",  4, 5, 0, 1 },
 872 #define F_MINUS     (F_NEGATIVE + 1)
 873   { "mi", 4, 5, 0, 0 },
 874 #define F_CARRY     (F_MINUS + 1)
 875   { "c",  5, 5, 0, 1 },
 876 #define F_CARRYSET  (F_CARRY + 1)
 877   { "cs", 5, 5, 0, 0 },
 878 #define F_LOWER     (F_CARRYSET + 1)
 879   { "lo", 5, 5, 0, 0 },
 880 #define F_CARRYCLR  (F_LOWER + 1)
 881   { "cc", 6, 5, 0, 0 },
 882 #define F_NOTCARRY (F_CARRYCLR + 1)
 883   { "nc", 6, 5, 0, 1 },
 884 #define F_HIGHER   (F_NOTCARRY + 1)
 885   { "hs", 6, 5, 0, 0 },
 886 #define F_OVERFLOWSET (F_HIGHER + 1)
 887   { "vs", 7, 5, 0, 0 },
 888 #define F_OVERFLOW (F_OVERFLOWSET + 1)
 889   { "v",  7, 5, 0, 1 },
 890 #define F_NOTOVERFLOW (F_OVERFLOW + 1)
 891   { "nv", 8, 5, 0, 1 },
 892 #define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
 893   { "vc", 8, 5, 0, 0 },
 894 #define F_GT       (F_OVERFLOWCLR + 1)
 895   { "gt", 9, 5, 0, 1 },
 896 #define F_GE       (F_GT + 1)
 897   { "ge", 10, 5, 0, 1 },
 898 #define F_LT       (F_GE + 1)
 899   { "lt", 11, 5, 0, 1 },
 900 #define F_LE       (F_LT + 1)
 901   { "le", 12, 5, 0, 1 },
 902 #define F_HI       (F_LE + 1)
 903   { "hi", 13, 5, 0, 1 },
 904 #define F_LS       (F_HI + 1)
 905   { "ls", 14, 5, 0, 1 },
 906 #define F_PNZ      (F_LS + 1)
 907   { "pnz", 15, 5, 0, 1 },
 908
 909   /* FLAG.  */
 910 #define F_FLAG     (F_PNZ + 1)
 911   { "f",  1, 1, 15, 1 },
 912 #define F_FFAKE     (F_FLAG + 1)
 913   { "f",  0, 0, 0, 1 },
 914
 915   /* Delay slot.  */
 916 #define F_ND       (F_FFAKE + 1)
 917   { "nd", 0, 1, 5, 0 },
 918 #define F_D        (F_ND + 1)
 919   { "d",  1, 1, 5, 1 },
 920 #define F_DFAKE    (F_D + 1)
 921   { "d",  0, 0, 0, 1 },
 922
 923   /* Data size.  */
 924 #define F_SIZEB1   (F_DFAKE + 1)
 925   { "b", 1, 2, 1, 1 },
 926 #define F_SIZEB7   (F_SIZEB1 + 1)
 927   { "b", 1, 2, 7, 1 },
 928 #define F_SIZEB17  (F_SIZEB7 + 1)
 929   { "b", 1, 2, 17, 1 },
 930 #define F_SIZEW1   (F_SIZEB17 + 1)
 931   { "w", 2, 2, 1, 0 },
 932 #define F_SIZEW7   (F_SIZEW1 + 1)
 933   { "w", 2, 2, 7, 0 },
 934 #define F_SIZEW17  (F_SIZEW7 + 1)
 935   { "w", 2, 2, 17, 0 },
 936
 937   /* Sign extension.  */
 938 #define F_SIGN6   (F_SIZEW17 + 1)
 939   { "x", 1, 1, 6, 1 },
 940 #define F_SIGN16  (F_SIGN6 + 1)
 941   { "x", 1, 1, 16, 1 },
 942 #define F_SIGNX   (F_SIGN16 + 1)
 943   { "x", 0, 0, 0, 1 },
 944
 945   /* Address write-back modes.  */
 946 #define F_A3       (F_SIGNX + 1)
 947   { "a", 1, 2, 3, 0 },
 948 #define F_A9       (F_A3 + 1)
 949   { "a", 1, 2, 9, 0 },
 950 #define F_A22      (F_A9 + 1)
 951   { "a", 1, 2, 22, 0 },
 952 #define F_AW3      (F_A22 + 1)
 953   { "aw", 1, 2, 3, 1 },
 954 #define F_AW9      (F_AW3 + 1)
 955   { "aw", 1, 2, 9, 1 },
 956 #define F_AW22     (F_AW9 + 1)
 957   { "aw", 1, 2, 22, 1 },
 958 #define F_AB3      (F_AW22 + 1)
 959   { "ab", 2, 2, 3, 1 },
 960 #define F_AB9      (F_AB3 + 1)
 961   { "ab", 2, 2, 9, 1 },
 962 #define F_AB22     (F_AB9 + 1)
 963   { "ab", 2, 2, 22, 1 },
 964 #define F_AS3      (F_AB22 + 1)
 965   { "as", 3, 2, 3, 1 },
 966 #define F_AS9      (F_AS3 + 1)
 967   { "as", 3, 2, 9, 1 },
 968 #define F_AS22     (F_AS9 + 1)
 969   { "as", 3, 2, 22, 1 },
 970 #define F_ASFAKE   (F_AS22 + 1)
 971   { "as", 0, 0, 0, 1 },
 972
 973   /* Cache bypass.  */
 974 #define F_DI5     (F_ASFAKE + 1)
 975   { "di", 1, 1, 5, 1 },
 976 #define F_DI11    (F_DI5 + 1)
 977   { "di", 1, 1, 11, 1 },
 978 #define F_DI15    (F_DI11 + 1)
 979   { "di", 1, 1, 15, 1 },
 980
 981   /* ARCv2 specific.  */
 982 #define F_NT     (F_DI15 + 1)
 983   { "nt", 0, 1, 3, 1},
 984 #define F_T      (F_NT + 1)
 985   { "t", 1, 1, 3, 1},
 986 #define F_H1     (F_T + 1)
 987   { "h", 2, 2, 1, 1 },
 988 #define F_H7     (F_H1 + 1)
 989   { "h", 2, 2, 7, 1 },
 990 #define F_H17    (F_H7 + 1)
 991   { "h", 2, 2, 17, 1 },
 992
 993   /* Fake Flags.  */
 994 #define F_NE   (F_H17 + 1)
 995   { "ne", 0, 0, 0, 1 },
 996
 997   /* ARC NPS400 Support: See comment near head of file.  */
 998 #define F_NPS_CL (F_NE + 1)
 999   { "cl", 0, 0, 0, 1 },
1000
1001 #define F_NPS_FLAG (F_NPS_CL + 1)
1002   { "f", 1, 1, 20, 1 },
1003
1004 #define F_NPS_R     (F_NPS_FLAG + 1)
1005   { "r",  1, 1, 15, 1 },
1006 };
1007
1008 const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
1009
1010 /* Table of the flag classes.
1011
1012    The format of the table is
1013    CLASS {FLAG_CODE}.  */
1014 const struct arc_flag_class arc_flag_classes[] =
1015 {
1016 #define C_EMPTY     0
1017   { F_CLASS_NONE, { F_NULL } },
1018
1019 #define C_CC        (C_EMPTY + 1)
1020   { F_CLASS_OPTIONAL, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1021                         F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
1022                         F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1023                         F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
1024                         F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
1025                         F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1026
1027 #define C_AA_ADDR3  (C_CC + 1)
1028 #define C_AA27      (C_CC + 1)
1029   { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
1030 #define C_AA_ADDR9  (C_AA_ADDR3 + 1)
1031 #define C_AA21       (C_AA_ADDR3 + 1)
1032   { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
1033 #define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1034 #define C_AA8      (C_AA_ADDR9 + 1)
1035   { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
1036
1037 #define C_F         (C_AA_ADDR22 + 1)
1038   { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
1039 #define C_FHARD     (C_F + 1)
1040   { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
1041
1042 #define C_T         (C_FHARD + 1)
1043   { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
1044 #define C_D         (C_T + 1)
1045   { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
1046
1047 #define C_DHARD     (C_D + 1)
1048   { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
1049
1050 #define C_DI20      (C_DHARD + 1)
1051   { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
1052 #define C_DI16      (C_DI20 + 1)
1053   { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
1054 #define C_DI26      (C_DI16 + 1)
1055   { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
1056
1057 #define C_X25       (C_DI26 + 1)
1058   { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
1059 #define C_X15      (C_X25 + 1)
1060   { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
1061 #define C_XHARD    (C_X15 + 1)
1062 #define C_X        (C_X15 + 1)
1063   { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
1064
1065 #define C_ZZ13        (C_X + 1)
1066   { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
1067 #define C_ZZ23        (C_ZZ13 + 1)
1068   { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
1069 #define C_ZZ29        (C_ZZ23 + 1)
1070   { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
1071
1072 #define C_AS        (C_ZZ29 + 1)
1073   { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
1074
1075 #define C_NE        (C_AS + 1)
1076   { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
1077
1078   /* ARC NPS400 Support: See comment near head of file.  */
1079 #define C_NPS_CL     (C_NE + 1)
1080   { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
1081
1082 #define C_NPS_F     (C_NPS_CL + 1)
1083   { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
1084
1085 #define C_NPS_R     (C_NPS_F + 1)
1086   { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
1087 };
1088
1089 /* The operands table.
1090
1091    The format of the operands table is:
1092
1093    BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN.  */
1094 const struct arc_operand arc_operands[] =
1095 {
1096   /* The fields are bits, shift, insert, extract, flags.  The zero
1097      index is used to indicate end-of-list.  */
1098 #define UNUSED          0
1099   { 0, 0, 0, 0, 0, 0 },
1100   /* The plain integer register fields.  Used by 32 bit
1101      instructions.  */
1102 #define RA              (UNUSED + 1)
1103   { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
1104 #define RB              (RA + 1)
1105   { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
1106 #define RC              (RB + 1)
1107   { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1108 #define RBdup           (RC + 1)
1109   { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1110
1111 #define RAD             (RBdup + 1)
1112   { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1113 #define RCD             (RAD + 1)
1114   { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1115
1116   /* The plain integer register fields.  Used by short
1117      instructions.  */
1118 #define RA16            (RCD + 1)
1119 #define RA_S            (RCD + 1)
1120   { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1121 #define RB16            (RA16 + 1)
1122 #define RB_S            (RA16 + 1)
1123   { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1124 #define RB16dup         (RB16 + 1)
1125 #define RB_Sdup         (RB16 + 1)
1126   { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1127 #define RC16            (RB16dup + 1)
1128 #define RC_S            (RB16dup + 1)
1129   { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1130 #define R6H             (RC16 + 1)   /* 6bit register field 'h' used
1131                                         by V1 cpus.  */
1132   { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1133 #define R5H             (R6H + 1)    /* 5bit register field 'h' used
1134                                         by V2 cpus.  */
1135 #define RH_S            (R6H + 1)    /* 5bit register field 'h' used
1136                                         by V2 cpus.  */
1137   { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1138 #define R5Hdup          (R5H + 1)
1139 #define RH_Sdup         (R5H + 1)
1140   { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1141     insert_rhv2, extract_rhv2 },
1142
1143 #define RG              (R5Hdup + 1)
1144 #define G_S             (R5Hdup + 1)
1145   { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1146
1147   /* Fix registers.  */
1148 #define R0              (RG + 1)
1149 #define R0_S            (RG + 1)
1150   { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1151 #define R1              (R0 + 1)
1152 #define R1_S            (R0 + 1)
1153   { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1154 #define R2              (R1 + 1)
1155 #define R2_S            (R1 + 1)
1156   { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1157 #define R3              (R2 + 1)
1158 #define R3_S            (R2 + 1)
1159   { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
1160 #define RSP             (R3 + 1)
1161 #define SP_S            (R3 + 1)
1162   { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
1163 #define SPdup           (RSP + 1)
1164 #define SP_Sdup         (RSP + 1)
1165   { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1166 #define GP              (SPdup + 1)
1167 #define GP_S            (SPdup + 1)
1168   { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1169
1170 #define PCL_S           (GP + 1)
1171   { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1172
1173 #define BLINK           (PCL_S + 1)
1174 #define BLINK_S         (PCL_S + 1)
1175   { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1176
1177 #define ILINK1          (BLINK + 1)
1178   { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1179 #define ILINK2          (ILINK1 + 1)
1180   { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1181
1182   /* Long immediate.  */
1183 #define LIMM            (ILINK2 + 1)
1184 #define LIMM_S          (ILINK2 + 1)
1185   { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1186 #define LIMMdup         (LIMM + 1)
1187   { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1188
1189   /* Special operands.  */
1190 #define ZA              (LIMMdup + 1)
1191 #define ZB              (LIMMdup + 1)
1192 #define ZA_S            (LIMMdup + 1)
1193 #define ZB_S            (LIMMdup + 1)
1194 #define ZC_S            (LIMMdup + 1)
1195   { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1196
1197 #define RRANGE_EL       (ZA + 1)
1198   { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1199     insert_rrange, extract_rrange},
1200 #define FP_EL           (RRANGE_EL + 1)
1201   { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1202     insert_fpel, extract_fpel },
1203 #define BLINK_EL        (FP_EL + 1)
1204   { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1205     insert_blinkel, extract_blinkel },
1206 #define PCL_EL          (BLINK_EL + 1)
1207   { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1208     insert_pclel, extract_pclel },
1209
1210   /* Fake operand to handle the T flag.  */
1211 #define BRAKET          (PCL_EL + 1)
1212 #define BRAKETdup       (PCL_EL + 1)
1213   { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1214
1215   /* Fake operand to handle the T flag.  */
1216 #define FKT_T           (BRAKET + 1)
1217   { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1218   /* Fake operand to handle the T flag.  */
1219 #define FKT_NT          (FKT_T + 1)
1220   { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1221
1222   /* UIMM6_20 mask = 00000000000000000000111111000000.  */
1223 #define UIMM6_20       (FKT_NT + 1)
1224   {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1225
1226   /* SIMM12_20 mask = 00000000000000000000111111222222.  */
1227 #define SIMM12_20       (UIMM6_20 + 1)
1228   {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1229
1230   /* SIMM3_5_S mask = 0000011100000000.  */
1231 #define SIMM3_5_S       (SIMM12_20 + 1)
1232   {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1233    insert_simm3s, extract_simm3s},
1234
1235   /* UIMM7_A32_11_S mask = 0000000000011111.  */
1236 #define UIMM7_A32_11_S       (SIMM3_5_S + 1)
1237   {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1238    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1239    extract_uimm7_a32_11_s},
1240
1241   /* UIMM7_9_S mask = 0000000001111111.  */
1242 #define UIMM7_9_S       (UIMM7_A32_11_S + 1)
1243   {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1244
1245   /* UIMM3_13_S mask = 0000000000000111.  */
1246 #define UIMM3_13_S       (UIMM7_9_S + 1)
1247   {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1248
1249   /* SIMM11_A32_7_S mask = 0000000111111111.  */
1250 #define SIMM11_A32_7_S       (UIMM3_13_S + 1)
1251   {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1252    | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1253
1254   /* UIMM6_13_S mask = 0000000002220111.  */
1255 #define UIMM6_13_S       (SIMM11_A32_7_S + 1)
1256   {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1257   /* UIMM5_11_S mask = 0000000000011111.  */
1258 #define UIMM5_11_S       (UIMM6_13_S + 1)
1259   {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
1260    extract_uimm5_11_s},
1261
1262   /* SIMM9_A16_8 mask = 00000000111111102000000000000000.  */
1263 #define SIMM9_A16_8       (UIMM5_11_S + 1)
1264   {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1265    | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
1266    extract_simm9_a16_8},
1267
1268   /* UIMM6_8 mask = 00000000000000000000111111000000.    */
1269 #define UIMM6_8       (SIMM9_A16_8 + 1)
1270   {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
1271
1272   /* SIMM21_A16_5 mask = 00000111111111102222222222000000.  */
1273 #define SIMM21_A16_5       (UIMM6_8 + 1)
1274   {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
1275    | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
1276    insert_simm21_a16_5, extract_simm21_a16_5},
1277
1278   /* SIMM25_A16_5 mask = 00000111111111102222222222003333.  */
1279 #define SIMM25_A16_5       (SIMM21_A16_5 + 1)
1280   {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
1281    | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
1282    insert_simm25_a16_5, extract_simm25_a16_5},
1283
1284   /* SIMM10_A16_7_S mask = 0000000111111111.  */
1285 #define SIMM10_A16_7_S       (SIMM25_A16_5 + 1)
1286   {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1287    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
1288    extract_simm10_a16_7_s},
1289
1290 #define SIMM10_A16_7_Sbis    (SIMM10_A16_7_S + 1)
1291   {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1292    | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
1293
1294   /* SIMM7_A16_10_S mask = 0000000000111111.  */
1295 #define SIMM7_A16_10_S       (SIMM10_A16_7_Sbis + 1)
1296   {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1297    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
1298    extract_simm7_a16_10_s},
1299
1300   /* SIMM21_A32_5 mask = 00000111111111002222222222000000.  */
1301 #define SIMM21_A32_5       (SIMM7_A16_10_S + 1)
1302   {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1303    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
1304    extract_simm21_a32_5},
1305
1306   /* SIMM25_A32_5 mask = 00000111111111002222222222003333.  */
1307 #define SIMM25_A32_5       (SIMM21_A32_5 + 1)
1308   {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1309    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
1310    extract_simm25_a32_5},
1311
1312   /* SIMM13_A32_5_S mask = 0000011111111111.  */
1313 #define SIMM13_A32_5_S       (SIMM25_A32_5 + 1)
1314   {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1315    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
1316    extract_simm13_a32_5_s},
1317
1318   /* SIMM8_A16_9_S mask = 0000000001111111.  */
1319 #define SIMM8_A16_9_S       (SIMM13_A32_5_S + 1)
1320   {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1321    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
1322    extract_simm8_a16_9_s},
1323
1324   /* UIMM3_23 mask = 00000000000000000000000111000000.  */
1325 #define UIMM3_23       (SIMM8_A16_9_S + 1)
1326   {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
1327
1328   /* UIMM10_6_S mask = 0000001111111111.  */
1329 #define UIMM10_6_S       (UIMM3_23 + 1)
1330   {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
1331
1332   /* UIMM6_11_S mask = 0000002200011110.  */
1333 #define UIMM6_11_S       (UIMM10_6_S + 1)
1334   {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
1335
1336   /* SIMM9_8 mask = 00000000111111112000000000000000.    */
1337 #define SIMM9_8       (UIMM6_11_S + 1)
1338   {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
1339    insert_simm9_8, extract_simm9_8},
1340
1341   /* UIMM10_A32_8_S mask = 0000000011111111.  */
1342 #define UIMM10_A32_8_S       (SIMM9_8 + 1)
1343   {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1344    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
1345    extract_uimm10_a32_8_s},
1346
1347   /* SIMM9_7_S mask = 0000000111111111.  */
1348 #define SIMM9_7_S       (UIMM10_A32_8_S + 1)
1349   {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
1350    extract_simm9_7_s},
1351
1352   /* UIMM6_A16_11_S mask = 0000000000011111.  */
1353 #define UIMM6_A16_11_S       (SIMM9_7_S + 1)
1354   {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1355    | ARC_OPERAND_TRUNCATE  | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
1356    extract_uimm6_a16_11_s},
1357
1358   /* UIMM5_A32_11_S mask = 0000020000011000.  */
1359 #define UIMM5_A32_11_S       (UIMM6_A16_11_S + 1)
1360   {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1361    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
1362    extract_uimm5_a32_11_s},
1363
1364   /* SIMM11_A32_13_S mask = 0000022222200111.    */
1365 #define SIMM11_A32_13_S       (UIMM5_A32_11_S + 1)
1366   {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1367    | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
1368
1369   /* UIMM7_13_S mask = 0000000022220111.  */
1370 #define UIMM7_13_S       (SIMM11_A32_13_S + 1)
1371   {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
1372
1373   /* UIMM6_A16_21 mask = 00000000000000000000011111000000.  */
1374 #define UIMM6_A16_21       (UIMM7_13_S + 1)
1375   {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1376    | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
1377
1378   /* UIMM7_11_S mask = 0000022200011110.  */
1379 #define UIMM7_11_S       (UIMM6_A16_21 + 1)
1380   {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
1381
1382   /* UIMM7_A16_20 mask = 00000000000000000000111111000000.  */
1383 #define UIMM7_A16_20       (UIMM7_11_S + 1)
1384   {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1385    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
1386    extract_uimm7_a16_20},
1387
1388   /* SIMM13_A16_20 mask = 00000000000000000000111111222222.  */
1389 #define SIMM13_A16_20       (UIMM7_A16_20 + 1)
1390   {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1391    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
1392    extract_simm13_a16_20},
1393
1394   /* UIMM8_8_S mask = 0000000011111111.  */
1395 #define UIMM8_8_S       (SIMM13_A16_20 + 1)
1396   {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
1397
1398   /* W6 mask = 00000000000000000000111111000000.  */
1399 #define W6       (UIMM8_8_S + 1)
1400   {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
1401
1402   /* UIMM6_5_S mask = 0000011111100000.  */
1403 #define UIMM6_5_S       (W6 + 1)
1404   {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
1405
1406   /* ARC NPS400 Support: See comment near head of file.  */
1407 #define NPS_R_DST_3B    (UIMM6_5_S + 1)
1408   { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1409
1410 #define NPS_R_SRC1_3B   (NPS_R_DST_3B + 1)
1411   { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1412
1413 #define NPS_R_SRC2_3B   (NPS_R_SRC1_3B + 1)
1414   { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2, extract_nps_3bit_src2 },
1415
1416 #define NPS_R_DST       (NPS_R_SRC2_3B + 1)
1417   { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
1418
1419 #define NPS_R_SRC1      (NPS_R_DST + 1)
1420   { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
1421
1422 #define NPS_BITOP_DST_POS       (NPS_R_SRC1 + 1)
1423   { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1424
1425 #define NPS_BITOP_SRC_POS       (NPS_BITOP_DST_POS + 1)
1426   { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1427
1428 #define NPS_BITOP_SIZE          (NPS_BITOP_SRC_POS + 1)
1429   { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size },
1430
1431 #define NPS_BITOP_DST_POS_SZ    (NPS_BITOP_SIZE + 1)
1432   { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
1433
1434 #define NPS_BITOP_SIZE_2B       (NPS_BITOP_DST_POS_SZ + 1)
1435   { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
1436
1437 #define NPS_BITOP_UIMM8         (NPS_BITOP_SIZE_2B + 1)
1438   { 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
1439
1440 #define NPS_UIMM16              (NPS_BITOP_UIMM8 + 1)
1441   { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1442
1443 #define NPS_RFLT_UIMM6          (NPS_UIMM16 + 1)
1444   { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
1445 };
1446
1447 const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
1448
1449 const unsigned arc_Toperand = FKT_T;
1450 const unsigned arc_NToperand = FKT_NT;
1451
1452 /* The opcode table.
1453
1454    The format of the opcode table is:
1455
1456    NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
1457
1458    The table is organised such that, where possible, all instructions with
1459    the same mnemonic are together in a block.  When the assembler searches
1460    for a suitable instruction the entries are checked in table order, so
1461    more specific, or specialised cases should appear earlier in the table.
1462
1463    As an example, consider two instructions 'add a,b,u6' and 'add
1464    a,b,limm'.  The first takes a 6-bit immediate that is encoded within the
1465    32-bit instruction, while the second takes a 32-bit immediate that is
1466    encoded in a follow-on 32-bit, making the total instruction length
1467    64-bits.  In this case the u6 variant must appear first in the table, as
1468    all u6 immediates could also be encoded using the 'limm' extension,
1469    however, we want to use the shorter instruction wherever possible.
1470
1471    It is possible though to split instructions with the same mnemonic into
1472    multiple groups.  However, the instructions are still checked in table
1473    order, even across groups.  The only time that instructions with the
1474    same mnemonic should be split into different groups is when different
1475    variants of the instruction appear in different architectures, in which
1476    case, grouping all instructions from a particular architecture together
1477    might be preferable to merging the instruction into the main instruction
1478    table.
1479
1480    An example of this split instruction groups can be found with the 'sync'
1481    instruction.  The core arc architecture provides a 'sync' instruction,
1482    while the nps instruction set extension provides 'sync.rd' and
1483    'sync.wr'.  The rd/wr flags are instruction flags, not part of the
1484    mnemonic, so we end up with two groups for the sync instruction, the
1485    first within the core arc instruction table, and the second within the
1486    nps extension instructions.  */
1487 const struct arc_opcode arc_opcodes[] =
1488 {
1489 #include "arc-tbl.h"
1490 #include "arc-nps400-tbl.h"
1491 #include "arc-ext-tbl.h"
1492 };
1493
1494 const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes);
1495
1496 /* List with special cases instructions and the applicable flags.  */
1497 const struct arc_flag_special arc_flag_special_cases[] =
1498 {
1499   { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1500            F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1501            F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1502            F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1503   { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1504             F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1505             F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1506             F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1507   { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1508             F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1509             F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1510             F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1511   { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1512            F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1513            F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1514            F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1515   { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1516             F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1517             F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1518             F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1519   { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1520             F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1521             F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1522             F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1523   { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1524              F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1525              F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1526              F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1527   { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
1528   { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
1529 };
1530
1531 const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
1532
1533 /* Relocations.  */
1534 const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
1535 {
1536   { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
1537     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1538   { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
1539     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1540   { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
1541     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1542   { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
1543     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1544
1545   /* Next two entries will cover the undefined behavior ldb/stb with
1546      address scaling.  */
1547   { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
1548     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
1549   { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
1550     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
1551
1552   { "sda", "ld", { F_ASFAKE, F_NULL },
1553     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
1554   { "sda", "st", { F_ASFAKE, F_NULL },
1555     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
1556   { "sda", "ldd", { F_ASFAKE, F_NULL },
1557     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
1558   { "sda", "std", { F_ASFAKE, F_NULL },
1559     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
1560
1561   /* Short instructions.  */
1562   { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
1563   { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
1564   { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
1565   { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
1566
1567   { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
1568   { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
1569
1570   { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
1571     BFD_RELOC_ARC_S25H_PCREL_PLT },
1572   { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
1573     BFD_RELOC_ARC_S21H_PCREL_PLT },
1574   { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
1575     BFD_RELOC_ARC_S25W_PCREL_PLT },
1576   { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
1577     BFD_RELOC_ARC_S21W_PCREL_PLT },
1578
1579   { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
1580 };
1581
1582 const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
1583
1584 const struct arc_pseudo_insn arc_pseudo_insns[] =
1585 {
1586   { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
1587                               { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
1588                               { BRAKETdup, 1, 0, 4} } },
1589   { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
1590                              { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
1591                              { BRAKETdup, 1, 0, 4} } },
1592
1593   { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1594                                { SIMM9_A16_8, 0, 0, 2 } } },
1595   { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1596                                { SIMM9_A16_8, 0, 0, 2 } } },
1597   { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1598                                { SIMM9_A16_8, 0, 0, 2 } } },
1599   { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1600                                { SIMM9_A16_8, 0, 0, 2 } } },
1601   { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1602                                { SIMM9_A16_8, 0, 0, 2 } } },
1603
1604   { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1605                                { SIMM9_A16_8, 0, 0, 2 } } },
1606   { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1607                                { SIMM9_A16_8, 0, 0, 2 } } },
1608   { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1609                                { SIMM9_A16_8, 0, 0, 2 } } },
1610   { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1611                                { SIMM9_A16_8, 0, 0, 2 } } },
1612   { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1613                                { SIMM9_A16_8, 0, 0, 2 } } },
1614
1615   { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1616                                { SIMM9_A16_8, 0, 0, 2 } } },
1617   { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1618                                { SIMM9_A16_8, 0, 0, 2 } } },
1619   { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1620                                { SIMM9_A16_8, 0, 0, 2 } } },
1621   { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1622                                { SIMM9_A16_8, 0, 0, 2 } } },
1623   { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1624                                { SIMM9_A16_8, 0, 0, 2 } } },
1625
1626   { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1627                                { SIMM9_A16_8, 0, 0, 2 } } },
1628   { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1629                                { SIMM9_A16_8, 0, 0, 2 } } },
1630   { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1631                                { SIMM9_A16_8, 0, 0, 2 } } },
1632   { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1633                                { SIMM9_A16_8, 0, 0, 2 } } },
1634   { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1635                                { SIMM9_A16_8, 0, 0, 2 } } },
1636 };
1637
1638 const unsigned arc_num_pseudo_insn =
1639   sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
1640
1641 const struct arc_aux_reg arc_aux_regs[] =
1642 {
1643 #undef DEF
1644 #define DEF(ADDR, SUBCLASS, NAME)               \
1645   { ADDR, SUBCLASS, #NAME, sizeof (#NAME)-1 },
1646
1647 #include "arc-regs.h"
1648
1649 #undef DEF
1650 };
1651
1652 const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
1653
1654 /* NOTE: The order of this array MUST be consistent with 'enum
1655    arc_rlx_types' located in tc-arc.h!  */
1656 const struct arc_opcode arc_relax_opcodes[] =
1657 {
1658   { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
1659
1660   /* bl_s s13 11111sssssssssss.  */
1661   { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1662     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1663     { SIMM13_A32_5_S }, { 0 }},
1664
1665   /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt.  */
1666   { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1667     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1668     { SIMM25_A32_5 }, { C_D }},
1669
1670   /* b_s s10 1111000sssssssss.  */
1671   { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1672     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1673     { SIMM10_A16_7_S }, { 0 }},
1674
1675   /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt.  */
1676   { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1677     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1678     { SIMM25_A16_5 }, { C_D }},
1679
1680   /* add_s c,b,u3 01101bbbccc00uuu.  Wants UIMM3_13_S_PCREL.  */
1681   { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1682     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1683     { RC_S, RB_S, UIMM3_13_S }, { 0 }},
1684
1685   /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA.  Wants
1686      UIMM6_20_PCREL.  */
1687   { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1688     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1689     { RA, RB, UIMM6_20 }, { C_F }},
1690
1691   /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA.  */
1692   { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1693     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1694     { RA, RB, LIMM }, { C_F }},
1695
1696   /* ld_s c,b,u7 10000bbbcccuuuuu.  Wants UIMM7_A32_11_S_PCREL.  */
1697   { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1698     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1699     { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
1700
1701   /* ld<.di><.aa><.x><zz> a,b,s9
1702      00010bbbssssssssSBBBDaaZZXAAAAAA.  Wants SIMM9_8_PCREL.  */
1703   { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1704     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1705     { RA, BRAKET, RB, SIMM9_8, BRAKETdup },
1706     { C_ZZ23, C_DI20, C_AA21, C_X25 }},
1707
1708   /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA.  */
1709   { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1710     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1711     { RA, BRAKET, RB, LIMM, BRAKETdup },
1712     { C_ZZ13, C_DI16, C_AA8, C_X15 }},
1713
1714   /* mov_s b,u8 11011bbbuuuuuuuu.  Wants UIMM8_8_S_PCREL.  */
1715   { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1716     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1717     { RB_S, UIMM8_8_S }, { 0 }},
1718
1719   /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS.  Wants
1720      SIMM12_20_PCREL.  */
1721   { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1722     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1723     { RB, SIMM12_20 }, { C_F }},
1724
1725   /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR.  */
1726   { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1727     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1728     { RB, LIMM }, { C_F }},
1729
1730   /* sub_s c,b,u3 01101bbbccc01uuu.  UIMM3_13_S_PCREL.  */
1731   { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1732     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1733     { RC_S, RB_S, UIMM3_13_S }, { 0 }},
1734
1735   /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.
1736      UIMM6_20_PCREL.  */
1737   { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1738     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1739     { RA, RB, UIMM6_20 }, { C_F }},
1740
1741   /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA.  */
1742   { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1743     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1744     { RA, RB, LIMM }, { C_F }},
1745
1746   /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.
1747      UIMM6_20_PCREL.  */
1748   { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
1749     | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
1750
1751   /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA.  */
1752   { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
1753     | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
1754
1755   /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.
1756      UIMM6_20_PCREL.  */
1757   { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1758     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1759     { RB, UIMM6_20 }, { C_F, C_CC }},
1760
1761   /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ.  */
1762   { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1763     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1764     { RB, LIMM }, { C_F, C_CC }},
1765
1766   /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.
1767      UIMM6_20_PCREL.  */
1768   { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1769     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1770     { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
1771
1772   /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ.  */
1773   { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1774     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1775     { RB, RBdup, LIMM }, { C_F, C_CC }}
1776 };
1777
1778 const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);