1 /* Opcode table for the ARC.
2 Copyright 1994, 1995, 1997, 1998, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Doug Evans (dje@cygnus.com).
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software Foundation,
18 Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 #include "opcode/arc.h"
24 #define INSERT_FN(fn) \
25 static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \
26 int, const struct arc_operand_value *, long, \
28 #define EXTRACT_FN(fn) \
29 static long fn PARAMS ((arc_insn *, const struct arc_operand *, \
30 int, const struct arc_operand_value **, int *))
32 INSERT_FN (insert_reg
);
33 INSERT_FN (insert_shimmfinish
);
34 INSERT_FN (insert_limmfinish
);
35 INSERT_FN (insert_offset
);
36 INSERT_FN (insert_base
);
37 INSERT_FN (insert_st_syntax
);
38 INSERT_FN (insert_ld_syntax
);
39 INSERT_FN (insert_addr_wb
);
40 INSERT_FN (insert_flag
);
41 INSERT_FN (insert_nullify
);
42 INSERT_FN (insert_flagfinish
);
43 INSERT_FN (insert_cond
);
44 INSERT_FN (insert_forcelimm
);
45 INSERT_FN (insert_reladdr
);
46 INSERT_FN (insert_absaddr
);
47 INSERT_FN (insert_jumpflags
);
48 INSERT_FN (insert_unopmacro
);
50 EXTRACT_FN (extract_reg
);
51 EXTRACT_FN (extract_ld_offset
);
52 EXTRACT_FN (extract_ld_syntax
);
53 EXTRACT_FN (extract_st_offset
);
54 EXTRACT_FN (extract_st_syntax
);
55 EXTRACT_FN (extract_flag
);
56 EXTRACT_FN (extract_cond
);
57 EXTRACT_FN (extract_reladdr
);
58 EXTRACT_FN (extract_jumpflags
);
59 EXTRACT_FN (extract_unopmacro
);
61 enum operand
{OP_NONE
,OP_REG
,OP_SHIMM
,OP_LIMM
};
65 enum operand ls_operand
[OPERANDS
];
72 /* Various types of ARC operands, including insn suffixes. */
74 /* Insn format values:
76 'a' REGA register A field
77 'b' REGB register B field
78 'c' REGC register C field
79 'S' SHIMMFINISH finish inserting a shimm value
80 'L' LIMMFINISH finish inserting a limm value
81 'o' OFFSET offset in st insns
82 'O' OFFSET offset in ld insns
83 '0' SYNTAX_ST_NE enforce store insn syntax, no errors
84 '1' SYNTAX_LD_NE enforce load insn syntax, no errors
85 '2' SYNTAX_ST enforce store insn syntax, errors, last pattern only
86 '3' SYNTAX_LD enforce load insn syntax, errors, last pattern only
87 's' BASE base in st insn
89 'F' FLAGFINISH finish inserting the F flag
90 'G' FLAGINSN insert F flag in "flag" insn
91 'n' DELAY N field (nullify field)
92 'q' COND condition code field
93 'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm
94 'B' BRANCH branch address (22 bit pc relative)
95 'J' JUMP jump address (26 bit absolute)
96 'j' JUMPFLAGS optional high order bits of 'J'
97 'z' SIZE1 size field in ld a,[b,c]
98 'Z' SIZE10 size field in ld a,[b,shimm]
99 'y' SIZE22 size field in st c,[b,shimm]
100 'x' SIGN0 sign extend field ld a,[b,c]
101 'X' SIGN9 sign extend field ld a,[b,shimm]
102 'w' ADDRESS3 write-back field in ld a,[b,c]
103 'W' ADDRESS12 write-back field in ld a,[b,shimm]
104 'v' ADDRESS24 write-back field in st c,[b,shimm]
105 'e' CACHEBYPASS5 cache bypass in ld a,[b,c]
106 'E' CACHEBYPASS14 cache bypass in ld a,[b,shimm]
107 'D' CACHEBYPASS26 cache bypass in st c,[b,shimm]
108 'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros
110 The following modifiers may appear between the % and char (eg: %.f):
112 '.' MODDOT '.' prefix must be present
113 'r' REG generic register value, for register table
114 'A' AUXREG auxiliary register in lr a,[b], sr c,[b]
118 CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN */
120 const struct arc_operand arc_operands
[] =
122 /* place holder (??? not sure if needed). */
124 { 0, 0, 0, 0, 0, 0 },
126 /* register A or shimm/limm indicator. */
127 #define REGA (UNUSED + 1)
128 { 'a', 6, ARC_SHIFT_REGA
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ERROR
, insert_reg
, extract_reg
},
130 /* register B or shimm/limm indicator. */
131 #define REGB (REGA + 1)
132 { 'b', 6, ARC_SHIFT_REGB
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ERROR
, insert_reg
, extract_reg
},
134 /* register C or shimm/limm indicator. */
135 #define REGC (REGB + 1)
136 { 'c', 6, ARC_SHIFT_REGC
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ERROR
, insert_reg
, extract_reg
},
138 /* fake operand used to insert shimm value into most instructions. */
139 #define SHIMMFINISH (REGC + 1)
140 { 'S', 9, 0, ARC_OPERAND_SIGNED
+ ARC_OPERAND_FAKE
, insert_shimmfinish
, 0 },
142 /* fake operand used to insert limm value into most instructions. */
143 #define LIMMFINISH (SHIMMFINISH + 1)
144 { 'L', 32, 32, ARC_OPERAND_ADDRESS
+ ARC_OPERAND_LIMM
+ ARC_OPERAND_FAKE
, insert_limmfinish
, 0 },
146 /* shimm operand when there is no reg indicator (st). */
147 #define ST_OFFSET (LIMMFINISH + 1)
148 { 'o', 9, 0, ARC_OPERAND_LIMM
| ARC_OPERAND_SIGNED
| ARC_OPERAND_STORE
, insert_offset
, extract_st_offset
},
150 /* shimm operand when there is no reg indicator (ld). */
151 #define LD_OFFSET (ST_OFFSET + 1)
152 { 'O', 9, 0,ARC_OPERAND_LIMM
| ARC_OPERAND_SIGNED
| ARC_OPERAND_LOAD
, insert_offset
, extract_ld_offset
},
154 /* operand for base. */
155 #define BASE (LD_OFFSET + 1)
156 { 's', 6, ARC_SHIFT_REGB
, ARC_OPERAND_LIMM
| ARC_OPERAND_SIGNED
, insert_base
, extract_reg
},
158 /* 0 enforce syntax for st insns. */
159 #define SYNTAX_ST_NE (BASE + 1)
160 { '0', 9, 0, ARC_OPERAND_FAKE
, insert_st_syntax
, extract_st_syntax
},
162 /* 1 enforce syntax for ld insns. */
163 #define SYNTAX_LD_NE (SYNTAX_ST_NE + 1)
164 { '1', 9, 0, ARC_OPERAND_FAKE
, insert_ld_syntax
, extract_ld_syntax
},
166 /* 0 enforce syntax for st insns. */
167 #define SYNTAX_ST (SYNTAX_LD_NE + 1)
168 { '2', 9, 0, ARC_OPERAND_FAKE
| ARC_OPERAND_ERROR
, insert_st_syntax
, extract_st_syntax
},
170 /* 0 enforce syntax for ld insns. */
171 #define SYNTAX_LD (SYNTAX_ST + 1)
172 { '3', 9, 0, ARC_OPERAND_FAKE
| ARC_OPERAND_ERROR
, insert_ld_syntax
, extract_ld_syntax
},
174 /* flag update bit (insertion is defered until we know how). */
175 #define FLAG (SYNTAX_LD + 1)
176 { 'f', 1, 8, ARC_OPERAND_SUFFIX
, insert_flag
, extract_flag
},
178 /* fake utility operand to finish 'f' suffix handling. */
179 #define FLAGFINISH (FLAG + 1)
180 { 'F', 1, 8, ARC_OPERAND_FAKE
, insert_flagfinish
, 0 },
182 /* fake utility operand to set the 'f' flag for the "flag" insn. */
183 #define FLAGINSN (FLAGFINISH + 1)
184 { 'G', 1, 8, ARC_OPERAND_FAKE
, insert_flag
, 0 },
186 /* branch delay types. */
187 #define DELAY (FLAGINSN + 1)
188 { 'n', 2, 5, ARC_OPERAND_SUFFIX
, insert_nullify
, 0 },
191 #define COND (DELAY + 1)
192 { 'q', 5, 0, ARC_OPERAND_SUFFIX
, insert_cond
, extract_cond
},
194 /* set `cond_p' to 1 to ensure a constant is treated as a limm. */
195 #define FORCELIMM (COND + 1)
196 { 'Q', 0, 0, ARC_OPERAND_FAKE
, insert_forcelimm
, 0 },
198 /* branch address; b, bl, and lp insns. */
199 #define BRANCH (FORCELIMM + 1)
200 { 'B', 20, 7, (ARC_OPERAND_RELATIVE_BRANCH
+ ARC_OPERAND_SIGNED
) | ARC_OPERAND_ERROR
, insert_reladdr
, extract_reladdr
},
202 /* jump address; j insn (this is basically the same as 'L' except that the
203 value is right shifted by 2). */
204 #define JUMP (BRANCH + 1)
205 { 'J', 24, 32, ARC_OPERAND_ERROR
| (ARC_OPERAND_ABSOLUTE_BRANCH
+ ARC_OPERAND_LIMM
+ ARC_OPERAND_FAKE
), insert_absaddr
, 0 },
207 /* jump flags; j{,l} insn value or'ed into 'J' addr for flag values. */
208 #define JUMPFLAGS (JUMP + 1)
209 { 'j', 6, 26, ARC_OPERAND_JUMPFLAGS
| ARC_OPERAND_ERROR
, insert_jumpflags
, extract_jumpflags
},
211 /* size field, stored in bit 1,2. */
212 #define SIZE1 (JUMPFLAGS + 1)
213 { 'z', 2, 1, ARC_OPERAND_SUFFIX
, 0, 0 },
215 /* size field, stored in bit 10,11. */
216 #define SIZE10 (SIZE1 + 1)
217 { 'Z', 2, 10, ARC_OPERAND_SUFFIX
, 0, 0 },
219 /* size field, stored in bit 22,23. */
220 #define SIZE22 (SIZE10 + 1)
221 { 'y', 2, 22, ARC_OPERAND_SUFFIX
, 0, 0 },
223 /* sign extend field, stored in bit 0. */
224 #define SIGN0 (SIZE22 + 1)
225 { 'x', 1, 0, ARC_OPERAND_SUFFIX
, 0, 0 },
227 /* sign extend field, stored in bit 9. */
228 #define SIGN9 (SIGN0 + 1)
229 { 'X', 1, 9, ARC_OPERAND_SUFFIX
, 0, 0 },
231 /* address write back, stored in bit 3. */
232 #define ADDRESS3 (SIGN9 + 1)
233 { 'w', 1, 3, ARC_OPERAND_SUFFIX
, insert_addr_wb
, 0},
235 /* address write back, stored in bit 12. */
236 #define ADDRESS12 (ADDRESS3 + 1)
237 { 'W', 1, 12, ARC_OPERAND_SUFFIX
, insert_addr_wb
, 0},
239 /* address write back, stored in bit 24. */
240 #define ADDRESS24 (ADDRESS12 + 1)
241 { 'v', 1, 24, ARC_OPERAND_SUFFIX
, insert_addr_wb
, 0},
243 /* cache bypass, stored in bit 5. */
244 #define CACHEBYPASS5 (ADDRESS24 + 1)
245 { 'e', 1, 5, ARC_OPERAND_SUFFIX
, 0, 0 },
247 /* cache bypass, stored in bit 14. */
248 #define CACHEBYPASS14 (CACHEBYPASS5 + 1)
249 { 'E', 1, 14, ARC_OPERAND_SUFFIX
, 0, 0 },
251 /* cache bypass, stored in bit 26. */
252 #define CACHEBYPASS26 (CACHEBYPASS14 + 1)
253 { 'D', 1, 26, ARC_OPERAND_SUFFIX
, 0, 0 },
255 /* unop macro, used to copy REGB to REGC. */
256 #define UNOPMACRO (CACHEBYPASS26 + 1)
257 { 'U', 6, ARC_SHIFT_REGC
, ARC_OPERAND_FAKE
, insert_unopmacro
, extract_unopmacro
},
259 /* '.' modifier ('.' required). */
260 #define MODDOT (UNOPMACRO + 1)
261 { '.', 1, 0, ARC_MOD_DOT
, 0, 0 },
263 /* Dummy 'r' modifier for the register table.
264 It's called a "dummy" because there's no point in inserting an 'r' into all
265 the %a/%b/%c occurrences in the insn table. */
266 #define REG (MODDOT + 1)
267 { 'r', 6, 0, ARC_MOD_REG
, 0, 0 },
269 /* Known auxiliary register modifier (stored in shimm field). */
270 #define AUXREG (REG + 1)
271 { 'A', 9, 0, ARC_MOD_AUXREG
, 0, 0 },
273 /* end of list place holder. */
277 /* Given a format letter, yields the index into `arc_operands'.
278 eg: arc_operand_map['a'] = REGA. */
279 unsigned char arc_operand_map
[256];
283 Longer versions of insns must appear before shorter ones (if gas sees
284 "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is
285 junk). This isn't necessary for `ld' because of the trailing ']'.
287 Instructions that are really macros based on other insns must appear
288 before the real insn so they're chosen when disassembling. Eg: The `mov'
289 insn is really the `and' insn. */
291 struct arc_opcode arc_opcodes
[] =
293 /* Base case instruction set (core versions 5-8) */
295 /* "mov" is really an "and". */
296 { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5
, 0, 0 },
297 /* "asl" is really an "add". */
298 { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5
, 0, 0 },
299 /* "lsl" is really an "add". */
300 { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5
, 0, 0 },
301 /* "nop" is really an "xor". */
302 { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5
, 0, 0 },
303 /* "rlc" is really an "adc". */
304 { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5
, 0, 0 },
305 { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5
, 0, 0 },
306 { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5
, 0, 0 },
307 { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5
, 0, 0 },
308 { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5
, 0, 0 },
309 { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14), ARC_MACH_5
, 0, 0 },
310 { "b%q%.n %B", I(-1), I(4), ARC_MACH_5
| ARC_OPCODE_COND_BRANCH
, 0, 0 },
311 { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5
| ARC_OPCODE_COND_BRANCH
, 0, 0 },
312 { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5
, 0, 0 },
313 { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5
, 0, 0 },
314 { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE
)|C(0), ARC_MACH_5
, 0, 0 },
315 { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7
, 0, 0 },
316 { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7
, 0, 0 },
317 { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8
, 0, 0 },
318 /* %Q: force cond_p=1 -> no shimm values. This insn allows an
319 optional flags spec. */
320 { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5
| ARC_OPCODE_COND_BRANCH
, 0, 0 },
321 { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5
| ARC_OPCODE_COND_BRANCH
, 0, 0 },
322 /* This insn allows an optional flags spec. */
323 { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6
| ARC_OPCODE_COND_BRANCH
, 0, 0 },
324 { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6
| ARC_OPCODE_COND_BRANCH
, 0, 0 },
325 /* Put opcode 1 ld insns first so shimm gets prefered over limm.
326 "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */
327 { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5
, 0, 0 },
328 { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5
, 0, 0 },
329 { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5
, 0, 0 },
330 { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1), I(1)|R(0,13,1), ARC_MACH_5
, 0, 0 },
331 { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5
, 0, 0 },
332 { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5
, 0, 0 },
333 { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5
, 0, 0 },
334 { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5
, 0, 0 },
335 { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5
, 0, 0 },
336 { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5
, 0, 0 },
337 { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11), ARC_MACH_5
, 0, 0 },
338 { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5
, 0, 0 },
339 { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5
, 0, 0 },
340 { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5
, 0, 0 },
341 /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */
342 { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5
, 0, 0 },
343 { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5
, 0, 0 },
344 { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10), ARC_MACH_5
, 0, 0 },
345 { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15), ARC_MACH_5
, 0, 0 }
348 const int arc_opcodes_count
= sizeof (arc_opcodes
) / sizeof (arc_opcodes
[0]);
350 const struct arc_operand_value arc_reg_names
[] =
352 /* Core register set r0-r63. */
354 /* r0-r28 - general purpose registers. */
355 { "r0", 0, REG
, 0 }, { "r1", 1, REG
, 0 }, { "r2", 2, REG
, 0 },
356 { "r3", 3, REG
, 0 }, { "r4", 4, REG
, 0 }, { "r5", 5, REG
, 0 },
357 { "r6", 6, REG
, 0 }, { "r7", 7, REG
, 0 }, { "r8", 8, REG
, 0 },
358 { "r9", 9, REG
, 0 }, { "r10", 10, REG
, 0 }, { "r11", 11, REG
, 0 },
359 { "r12", 12, REG
, 0 }, { "r13", 13, REG
, 0 }, { "r14", 14, REG
, 0 },
360 { "r15", 15, REG
, 0 }, { "r16", 16, REG
, 0 }, { "r17", 17, REG
, 0 },
361 { "r18", 18, REG
, 0 }, { "r19", 19, REG
, 0 }, { "r20", 20, REG
, 0 },
362 { "r21", 21, REG
, 0 }, { "r22", 22, REG
, 0 }, { "r23", 23, REG
, 0 },
363 { "r24", 24, REG
, 0 }, { "r25", 25, REG
, 0 }, { "r26", 26, REG
, 0 },
364 { "r27", 27, REG
, 0 }, { "r28", 28, REG
, 0 },
365 /* Maskable interrupt link register. */
366 { "ilink1", 29, REG
, 0 },
367 /* Maskable interrupt link register. */
368 { "ilink2", 30, REG
, 0 },
369 /* Branch-link register. */
370 { "blink", 31, REG
, 0 },
372 /* r32-r59 reserved for extensions. */
373 { "r32", 32, REG
, 0 }, { "r33", 33, REG
, 0 }, { "r34", 34, REG
, 0 },
374 { "r35", 35, REG
, 0 }, { "r36", 36, REG
, 0 }, { "r37", 37, REG
, 0 },
375 { "r38", 38, REG
, 0 }, { "r39", 39, REG
, 0 }, { "r40", 40, REG
, 0 },
376 { "r41", 41, REG
, 0 }, { "r42", 42, REG
, 0 }, { "r43", 43, REG
, 0 },
377 { "r44", 44, REG
, 0 }, { "r45", 45, REG
, 0 }, { "r46", 46, REG
, 0 },
378 { "r47", 47, REG
, 0 }, { "r48", 48, REG
, 0 }, { "r49", 49, REG
, 0 },
379 { "r50", 50, REG
, 0 }, { "r51", 51, REG
, 0 }, { "r52", 52, REG
, 0 },
380 { "r53", 53, REG
, 0 }, { "r54", 54, REG
, 0 }, { "r55", 55, REG
, 0 },
381 { "r56", 56, REG
, 0 }, { "r57", 57, REG
, 0 }, { "r58", 58, REG
, 0 },
382 { "r59", 59, REG
, 0 },
384 /* Loop count register (24 bits). */
385 { "lp_count", 60, REG
, 0 },
386 /* Short immediate data indicator setting flags. */
387 { "r61", 61, REG
, ARC_REGISTER_READONLY
},
388 /* Long immediate data indicator setting flags. */
389 { "r62", 62, REG
, ARC_REGISTER_READONLY
},
390 /* Short immediate data indicator not setting flags. */
391 { "r63", 63, REG
, ARC_REGISTER_READONLY
},
393 /* Small-data base register. */
394 { "gp", 26, REG
, 0 },
396 { "fp", 27, REG
, 0 },
398 { "sp", 28, REG
, 0 },
400 { "r29", 29, REG
, 0 },
401 { "r30", 30, REG
, 0 },
402 { "r31", 31, REG
, 0 },
403 { "r60", 60, REG
, 0 },
405 /* Auxiliary register set. */
407 /* Auxiliary register address map:
408 0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation
409 0xfffffeff-0x80000000 - customer limm allocation
410 0x7fffffff-0x00000100 - ARC limm allocation
411 0x000000ff-0x00000000 - ARC shimm allocation */
413 /* Base case auxiliary registers (shimm address). */
414 { "status", 0x00, AUXREG
, 0 },
415 { "semaphore", 0x01, AUXREG
, 0 },
416 { "lp_start", 0x02, AUXREG
, 0 },
417 { "lp_end", 0x03, AUXREG
, 0 },
418 { "identity", 0x04, AUXREG
, ARC_REGISTER_READONLY
},
419 { "debug", 0x05, AUXREG
, 0 },
422 const int arc_reg_names_count
=
423 sizeof (arc_reg_names
) / sizeof (arc_reg_names
[0]);
426 Operands with the same name must be stored together. */
428 const struct arc_operand_value arc_suffixes
[] =
430 /* Entry 0 is special, default values aren't printed by the disassembler. */
433 /* Base case condition codes. */
434 { "al", 0, COND
, 0 },
435 { "ra", 0, COND
, 0 },
436 { "eq", 1, COND
, 0 },
438 { "ne", 2, COND
, 0 },
439 { "nz", 2, COND
, 0 },
440 { "pl", 3, COND
, 0 },
442 { "mi", 4, COND
, 0 },
444 { "cs", 5, COND
, 0 },
446 { "lo", 5, COND
, 0 },
447 { "cc", 6, COND
, 0 },
448 { "nc", 6, COND
, 0 },
449 { "hs", 6, COND
, 0 },
450 { "vs", 7, COND
, 0 },
452 { "vc", 8, COND
, 0 },
453 { "nv", 8, COND
, 0 },
454 { "gt", 9, COND
, 0 },
455 { "ge", 10, COND
, 0 },
456 { "lt", 11, COND
, 0 },
457 { "le", 12, COND
, 0 },
458 { "hi", 13, COND
, 0 },
459 { "ls", 14, COND
, 0 },
460 { "pnz", 15, COND
, 0 },
462 /* Condition codes 16-31 reserved for extensions. */
466 { "nd", ARC_DELAY_NONE
, DELAY
, 0 },
467 { "d", ARC_DELAY_NORMAL
, DELAY
, 0 },
468 { "jd", ARC_DELAY_JUMP
, DELAY
, 0 },
470 { "b", 1, SIZE1
, 0 },
471 { "b", 1, SIZE10
, 0 },
472 { "b", 1, SIZE22
, 0 },
473 { "w", 2, SIZE1
, 0 },
474 { "w", 2, SIZE10
, 0 },
475 { "w", 2, SIZE22
, 0 },
476 { "x", 1, SIGN0
, 0 },
477 { "x", 1, SIGN9
, 0 },
478 { "a", 1, ADDRESS3
, 0 },
479 { "a", 1, ADDRESS12
, 0 },
480 { "a", 1, ADDRESS24
, 0 },
482 { "di", 1, CACHEBYPASS5
, 0 },
483 { "di", 1, CACHEBYPASS14
, 0 },
484 { "di", 1, CACHEBYPASS26
, 0 },
487 const int arc_suffixes_count
=
488 sizeof (arc_suffixes
) / sizeof (arc_suffixes
[0]);
490 /* Indexed by first letter of opcode. Points to chain of opcodes with same
492 static struct arc_opcode
*opcode_map
[26 + 1];
494 /* Indexed by insn code. Points to chain of opcodes with same insn code. */
495 static struct arc_opcode
*icode_map
[32];
497 /* Configuration flags. */
499 /* Various ARC_HAVE_XXX bits. */
502 /* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */
505 arc_get_opcode_mach (bfd_mach
, big_p
)
508 static int mach_type_map
[] =
515 return mach_type_map
[bfd_mach
] | (big_p
? ARC_MACH_BIG
: 0);
518 /* Initialize any tables that need it.
519 Must be called once at start up (or when first needed).
521 FLAGS is a set of bits that say what version of the cpu we have,
522 and in particular at least (one of) ARC_MACH_XXX. */
525 arc_opcode_init_tables (flags
)
528 static int init_p
= 0;
532 /* We may be intentionally called more than once (for example gdb will call
533 us each time the user switches cpu). These tables only need to be init'd
539 memset (arc_operand_map
, 0, sizeof (arc_operand_map
));
540 n
= sizeof (arc_operands
) / sizeof (arc_operands
[0]);
541 for (i
= 0; i
< n
; ++i
)
542 arc_operand_map
[arc_operands
[i
].fmt
] = i
;
544 memset (opcode_map
, 0, sizeof (opcode_map
));
545 memset (icode_map
, 0, sizeof (icode_map
));
546 /* Scan the table backwards so macros appear at the front. */
547 for (i
= arc_opcodes_count
- 1; i
>= 0; --i
)
549 int opcode_hash
= ARC_HASH_OPCODE (arc_opcodes
[i
].syntax
);
550 int icode_hash
= ARC_HASH_ICODE (arc_opcodes
[i
].value
);
552 arc_opcodes
[i
].next_asm
= opcode_map
[opcode_hash
];
553 opcode_map
[opcode_hash
] = &arc_opcodes
[i
];
555 arc_opcodes
[i
].next_dis
= icode_map
[icode_hash
];
556 icode_map
[icode_hash
] = &arc_opcodes
[i
];
563 /* Return non-zero if OPCODE is supported on the specified cpu.
564 Cpu selection is made when calling `arc_opcode_init_tables'. */
567 arc_opcode_supported (opcode
)
568 const struct arc_opcode
*opcode
;
570 if (ARC_OPCODE_CPU (opcode
->flags
) <= cpu_type
)
575 /* Return the first insn in the chain for assembling INSN. */
577 const struct arc_opcode
*
578 arc_opcode_lookup_asm (insn
)
581 return opcode_map
[ARC_HASH_OPCODE (insn
)];
584 /* Return the first insn in the chain for disassembling INSN. */
586 const struct arc_opcode
*
587 arc_opcode_lookup_dis (insn
)
590 return icode_map
[ARC_HASH_ICODE (insn
)];
593 /* Nonzero if we've seen an 'f' suffix (in certain insns). */
596 /* Nonzero if we've finished processing the 'f' suffix. */
597 static int flagshimm_handled_p
;
599 /* Nonzero if we've seen a 'a' suffix (address writeback). */
602 /* Nonzero if we've seen a 'q' suffix (condition code). */
605 /* Nonzero if we've inserted a nullify condition. */
606 static int nullify_p
;
608 /* The value of the a nullify condition we inserted. */
611 /* Nonzero if we've inserted jumpflags. */
612 static int jumpflags_p
;
614 /* Nonzero if we've inserted a shimm. */
617 /* The value of the shimm we inserted (each insn only gets one but it can
618 appear multiple times). */
621 /* Nonzero if we've inserted a limm (during assembly) or seen a limm
622 (during disassembly). */
625 /* The value of the limm we inserted. Each insn only gets one but it can
626 appear multiple times. */
629 /* Insertion functions. */
631 /* Called by the assembler before parsing an instruction. */
634 arc_opcode_init_insert ()
638 for(i
= 0; i
< OPERANDS
; i
++)
639 ls_operand
[i
] = OP_NONE
;
642 flagshimm_handled_p
= 0;
649 nullify
= 0; /* the default is important. */
652 /* Called by the assembler to see if the insn has a limm operand.
653 Also called by the disassembler to see if the insn contains a limm. */
656 arc_opcode_limm_p (limmp
)
664 /* Insert a value into a register field.
665 If REG is NULL, then this is actually a constant.
667 We must also handle auxiliary registers for lr/sr insns. */
670 insert_reg (insn
, operand
, mods
, reg
, value
, errmsg
)
672 const struct arc_operand
*operand
;
674 const struct arc_operand_value
*reg
;
678 static char buf
[100];
679 enum operand op_type
= OP_NONE
;
683 /* We have a constant that also requires a value stored in a register
684 field. Handle these by updating the register field and saving the
685 value for later handling by either %S (shimm) or %L (limm). */
687 /* Try to use a shimm value before a limm one. */
688 if (ARC_SHIMM_CONST_P (value
)
689 /* If we've seen a conditional suffix we have to use a limm. */
691 /* If we already have a shimm value that is different than ours
692 we have to use a limm. */
693 && (!shimm_p
|| shimm
== value
))
698 /* forget about shimm as dest mlm. */
700 if ('a' != operand
->fmt
)
704 flagshimm_handled_p
= 1;
705 marker
= flag_p
? ARC_REG_SHIMM_UPDATE
: ARC_REG_SHIMM
;
709 /* don't request flag setting on shimm as dest. */
710 marker
= ARC_REG_SHIMM
;
712 insn
|= marker
<< operand
->shift
;
713 /* insn |= value & 511; - done later. */
715 /* We have to use a limm. If we've already seen one they must match. */
716 else if (!limm_p
|| limm
== value
)
721 insn
|= ARC_REG_LIMM
<< operand
->shift
;
722 /* The constant is stored later. */
726 *errmsg
= "unable to fit different valued constants into instruction";
731 /* We have to handle both normal and auxiliary registers. */
733 if (reg
->type
== AUXREG
)
735 if (!(mods
& ARC_MOD_AUXREG
))
736 *errmsg
= "auxiliary register not allowed here";
739 if ((insn
& I(-1)) == I(2)) /* check for use validity. */
741 if (reg
->flags
& ARC_REGISTER_READONLY
)
742 *errmsg
= "attempt to set readonly register";
746 if (reg
->flags
& ARC_REGISTER_WRITEONLY
)
747 *errmsg
= "attempt to read writeonly register";
749 insn
|= ARC_REG_SHIMM
<< operand
->shift
;
750 insn
|= reg
->value
<< arc_operands
[reg
->type
].shift
;
755 /* check for use validity. */
756 if ('a' == operand
->fmt
|| ((insn
& I(-1)) < I(2)))
758 if (reg
->flags
& ARC_REGISTER_READONLY
)
759 *errmsg
= "attempt to set readonly register";
761 if ('a' != operand
->fmt
)
763 if (reg
->flags
& ARC_REGISTER_WRITEONLY
)
764 *errmsg
= "attempt to read writeonly register";
766 /* We should never get an invalid register number here. */
767 if ((unsigned int) reg
->value
> 60)
769 sprintf (buf
, "invalid register number `%d'", reg
->value
);
772 insn
|= reg
->value
<< operand
->shift
;
777 switch (operand
->fmt
)
780 ls_operand
[LS_DEST
] = op_type
;
783 ls_operand
[LS_BASE
] = op_type
;
786 if ((insn
& I(-1)) == I(2))
787 ls_operand
[LS_VALUE
] = op_type
;
789 ls_operand
[LS_OFFSET
] = op_type
;
792 ls_operand
[LS_OFFSET
] = op_type
;
799 /* Called when we see an 'f' flag. */
802 insert_flag (insn
, operand
, mods
, reg
, value
, errmsg
)
804 const struct arc_operand
*operand ATTRIBUTE_UNUSED
;
805 int mods ATTRIBUTE_UNUSED
;
806 const struct arc_operand_value
*reg ATTRIBUTE_UNUSED
;
807 long value ATTRIBUTE_UNUSED
;
808 const char **errmsg ATTRIBUTE_UNUSED
;
810 /* We can't store anything in the insn until we've parsed the registers.
811 Just record the fact that we've got this flag. `insert_reg' will use it
812 to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */
817 /* Called when we see an nullify condition. */
820 insert_nullify (insn
, operand
, mods
, reg
, value
, errmsg
)
822 const struct arc_operand
*operand
;
823 int mods ATTRIBUTE_UNUSED
;
824 const struct arc_operand_value
*reg ATTRIBUTE_UNUSED
;
826 const char **errmsg ATTRIBUTE_UNUSED
;
829 insn
|= (value
& ((1 << operand
->bits
) - 1)) << operand
->shift
;
834 /* Called after completely building an insn to ensure the 'f' flag gets set
835 properly. This is needed because we don't know how to set this flag until
836 we've parsed the registers. */
839 insert_flagfinish (insn
, operand
, mods
, reg
, value
, errmsg
)
841 const struct arc_operand
*operand
;
842 int mods ATTRIBUTE_UNUSED
;
843 const struct arc_operand_value
*reg ATTRIBUTE_UNUSED
;
844 long value ATTRIBUTE_UNUSED
;
845 const char **errmsg ATTRIBUTE_UNUSED
;
847 if (flag_p
&& !flagshimm_handled_p
)
851 flagshimm_handled_p
= 1;
852 insn
|= (1 << operand
->shift
);
857 /* Called when we see a conditional flag (eg: .eq). */
860 insert_cond (insn
, operand
, mods
, reg
, value
, errmsg
)
862 const struct arc_operand
*operand
;
863 int mods ATTRIBUTE_UNUSED
;
864 const struct arc_operand_value
*reg ATTRIBUTE_UNUSED
;
866 const char **errmsg ATTRIBUTE_UNUSED
;
869 insn
|= (value
& ((1 << operand
->bits
) - 1)) << operand
->shift
;
873 /* Used in the "j" instruction to prevent constants from being interpreted as
874 shimm values (which the jump insn doesn't accept). This can also be used
875 to force the use of limm values in other situations (eg: ld r0,[foo] uses
877 ??? The mechanism is sound. Access to it is a bit klunky right now. */
880 insert_forcelimm (insn
, operand
, mods
, reg
, value
, errmsg
)
882 const struct arc_operand
*operand ATTRIBUTE_UNUSED
;
883 int mods ATTRIBUTE_UNUSED
;
884 const struct arc_operand_value
*reg ATTRIBUTE_UNUSED
;
885 long value ATTRIBUTE_UNUSED
;
886 const char **errmsg ATTRIBUTE_UNUSED
;
893 insert_addr_wb (insn
, operand
, mods
, reg
, value
, errmsg
)
895 const struct arc_operand
*operand
;
896 int mods ATTRIBUTE_UNUSED
;
897 const struct arc_operand_value
*reg ATTRIBUTE_UNUSED
;
898 long value ATTRIBUTE_UNUSED
;
899 const char **errmsg ATTRIBUTE_UNUSED
;
901 addrwb_p
= 1 << operand
->shift
;
906 insert_base (insn
, operand
, mods
, reg
, value
, errmsg
)
908 const struct arc_operand
*operand
;
910 const struct arc_operand_value
*reg
;
917 myinsn
= insert_reg (0, operand
,mods
, reg
, value
, errmsg
) >> operand
->shift
;
919 ls_operand
[LS_BASE
] = OP_REG
;
921 else if (ARC_SHIMM_CONST_P (value
) && !cond_p
)
923 if (shimm_p
&& value
!= shimm
)
925 /* convert the previous shimm operand to a limm. */
928 insn
&= ~C(-1); /* we know where the value is in insn. */
929 insn
|= C(ARC_REG_LIMM
);
930 ls_operand
[LS_VALUE
] = OP_LIMM
;
932 insn
|= ARC_REG_SHIMM
<< operand
->shift
;
935 ls_operand
[LS_BASE
] = OP_SHIMM
;
939 if (limm_p
&& value
!= limm
)
941 *errmsg
= "too many long constants";
946 insn
|= B(ARC_REG_LIMM
);
947 ls_operand
[LS_BASE
] = OP_LIMM
;
953 /* Used in ld/st insns to handle the offset field. We don't try to
954 match operand syntax here. we catch bad combinations later. */
957 insert_offset (insn
, operand
, mods
, reg
, value
, errmsg
)
959 const struct arc_operand
*operand
;
961 const struct arc_operand_value
*reg
;
970 myinsn
= insert_reg (0,operand
,mods
,reg
,value
,errmsg
) >> operand
->shift
;
971 ls_operand
[LS_OFFSET
] = OP_REG
;
972 if (operand
->flags
& ARC_OPERAND_LOAD
) /* not if store, catch it later. */
973 if ((insn
& I(-1)) != I(1)) /* not if opcode == 1, catch it later. */
978 /* This is *way* more general than necessary, but maybe some day it'll
980 if (operand
->flags
& ARC_OPERAND_SIGNED
)
982 minval
= -(1 << (operand
->bits
- 1));
983 maxval
= (1 << (operand
->bits
- 1)) - 1;
988 maxval
= (1 << operand
->bits
) - 1;
990 if ((cond_p
&& !limm_p
) || (value
< minval
|| value
> maxval
))
992 if (limm_p
&& value
!= limm
)
994 *errmsg
= "too many long constants";
1000 if (operand
->flags
& ARC_OPERAND_STORE
)
1001 insn
|= B(ARC_REG_LIMM
);
1002 if (operand
->flags
& ARC_OPERAND_LOAD
)
1003 insn
|= C(ARC_REG_LIMM
);
1004 ls_operand
[LS_OFFSET
] = OP_LIMM
;
1009 if ((value
< minval
|| value
> maxval
))
1010 *errmsg
= "need too many limms";
1011 else if (shimm_p
&& value
!= shimm
)
1013 /* check for bad operand combinations before we lose info about them. */
1014 if ((insn
& I(-1)) == I(1))
1016 *errmsg
= "to many shimms in load";
1019 if (limm_p
&& operand
->flags
& ARC_OPERAND_LOAD
)
1021 *errmsg
= "too many long constants";
1024 /* convert what we thought was a shimm to a limm. */
1027 if (ls_operand
[LS_VALUE
] == OP_SHIMM
&& operand
->flags
& ARC_OPERAND_STORE
)
1030 insn
|= C(ARC_REG_LIMM
);
1031 ls_operand
[LS_VALUE
] = OP_LIMM
;
1033 if (ls_operand
[LS_BASE
] == OP_SHIMM
&& operand
->flags
& ARC_OPERAND_STORE
)
1036 insn
|= B(ARC_REG_LIMM
);
1037 ls_operand
[LS_BASE
] = OP_LIMM
;
1042 ls_operand
[LS_OFFSET
] = OP_SHIMM
;
1049 /* Used in st insns to do final disasemble syntax check. */
1052 extract_st_syntax (insn
, operand
, mods
, opval
, invalid
)
1054 const struct arc_operand
*operand ATTRIBUTE_UNUSED
;
1055 int mods ATTRIBUTE_UNUSED
;
1056 const struct arc_operand_value
**opval ATTRIBUTE_UNUSED
;
1059 #define ST_SYNTAX(V,B,O) \
1060 ((ls_operand[LS_VALUE] == (V) && \
1061 ls_operand[LS_BASE] == (B) && \
1062 ls_operand[LS_OFFSET] == (O)))
1064 if (!((ST_SYNTAX(OP_REG
,OP_REG
,OP_NONE
) && (insn
[0] & 511) == 0)
1065 || ST_SYNTAX(OP_REG
,OP_LIMM
,OP_NONE
)
1066 || (ST_SYNTAX(OP_SHIMM
,OP_REG
,OP_NONE
) && (insn
[0] & 511) == 0)
1067 || (ST_SYNTAX(OP_SHIMM
,OP_SHIMM
,OP_NONE
) && (insn
[0] & 511) == 0)
1068 || ST_SYNTAX(OP_SHIMM
,OP_LIMM
,OP_NONE
)
1069 || ST_SYNTAX(OP_SHIMM
,OP_LIMM
,OP_SHIMM
)
1070 || ST_SYNTAX(OP_SHIMM
,OP_SHIMM
,OP_SHIMM
)
1071 || (ST_SYNTAX(OP_LIMM
,OP_REG
,OP_NONE
) && (insn
[0] & 511) == 0)
1072 || ST_SYNTAX(OP_REG
,OP_REG
,OP_SHIMM
)
1073 || ST_SYNTAX(OP_REG
,OP_SHIMM
,OP_SHIMM
)
1074 || ST_SYNTAX(OP_SHIMM
,OP_REG
,OP_SHIMM
)
1075 || ST_SYNTAX(OP_LIMM
,OP_SHIMM
,OP_SHIMM
)
1076 || ST_SYNTAX(OP_LIMM
,OP_SHIMM
,OP_NONE
)
1077 || ST_SYNTAX(OP_LIMM
,OP_REG
,OP_SHIMM
)))
1083 arc_limm_fixup_adjust(insn
)
1088 /* check for st shimm,[limm]. */
1089 if ((insn
& (I(-1) | C(-1) | B(-1))) ==
1090 (I(2) | C(ARC_REG_SHIMM
) | B(ARC_REG_LIMM
)))
1092 retval
= insn
& 0x1ff;
1093 if (retval
& 0x100) /* sign extend 9 bit offset. */
1096 return -retval
; /* negate offset for return. */
1099 /* Used in st insns to do final syntax check. */
1102 insert_st_syntax (insn
, operand
, mods
, reg
, value
, errmsg
)
1104 const struct arc_operand
*operand ATTRIBUTE_UNUSED
;
1105 int mods ATTRIBUTE_UNUSED
;
1106 const struct arc_operand_value
*reg ATTRIBUTE_UNUSED
;
1107 long value ATTRIBUTE_UNUSED
;
1108 const char **errmsg
;
1110 if (ST_SYNTAX(OP_SHIMM
,OP_REG
,OP_NONE
) && shimm
!= 0)
1112 /* change an illegal insn into a legal one, it's easier to
1113 do it here than to try to handle it during operand scan. */
1118 insn
= insn
& ~(C(-1) | 511);
1119 insn
|= ARC_REG_LIMM
<< ARC_SHIFT_REGC
;
1120 ls_operand
[LS_VALUE
] = OP_LIMM
;
1123 if (ST_SYNTAX(OP_REG
,OP_SHIMM
,OP_NONE
) || ST_SYNTAX(OP_LIMM
,OP_SHIMM
,OP_NONE
))
1125 /* try to salvage this syntax. */
1126 if (shimm
& 0x1) /* odd shimms won't work. */
1128 if (limm_p
) /* do we have a limm already? */
1130 *errmsg
= "impossible store";
1136 insn
= insn
& ~(B(-1) | 511);
1137 insn
|= B(ARC_REG_LIMM
);
1138 ls_operand
[LS_BASE
] = OP_LIMM
;
1145 ls_operand
[LS_OFFSET
] = OP_SHIMM
;
1148 if (ST_SYNTAX(OP_SHIMM
,OP_LIMM
,OP_NONE
))
1150 limm
+= arc_limm_fixup_adjust(insn
);
1152 if (!(ST_SYNTAX(OP_REG
,OP_REG
,OP_NONE
)
1153 || ST_SYNTAX(OP_REG
,OP_LIMM
,OP_NONE
)
1154 || ST_SYNTAX(OP_REG
,OP_REG
,OP_SHIMM
)
1155 || ST_SYNTAX(OP_REG
,OP_SHIMM
,OP_SHIMM
)
1156 || (ST_SYNTAX(OP_SHIMM
,OP_SHIMM
,OP_NONE
) && (shimm
== 0))
1157 || ST_SYNTAX(OP_SHIMM
,OP_LIMM
,OP_NONE
)
1158 || ST_SYNTAX(OP_SHIMM
,OP_REG
,OP_NONE
)
1159 || ST_SYNTAX(OP_SHIMM
,OP_REG
,OP_SHIMM
)
1160 || ST_SYNTAX(OP_SHIMM
,OP_SHIMM
,OP_SHIMM
)
1161 || ST_SYNTAX(OP_LIMM
,OP_SHIMM
,OP_SHIMM
)
1162 || ST_SYNTAX(OP_LIMM
,OP_REG
,OP_NONE
)
1163 || ST_SYNTAX(OP_LIMM
,OP_REG
,OP_SHIMM
)))
1164 *errmsg
= "st operand error";
1167 if (ls_operand
[LS_BASE
] != OP_REG
)
1168 *errmsg
= "address writeback not allowed";
1171 if (ST_SYNTAX(OP_SHIMM
,OP_REG
,OP_NONE
) && shimm
)
1172 *errmsg
= "store value must be zero";
1176 /* Used in ld insns to do final syntax check. */
1179 insert_ld_syntax (insn
, operand
, mods
, reg
, value
, errmsg
)
1181 const struct arc_operand
*operand ATTRIBUTE_UNUSED
;
1182 int mods ATTRIBUTE_UNUSED
;
1183 const struct arc_operand_value
*reg ATTRIBUTE_UNUSED
;
1184 long value ATTRIBUTE_UNUSED
;
1185 const char **errmsg
;
1187 #define LD_SYNTAX(D,B,O) \
1188 ((ls_operand[LS_DEST] == (D) && \
1189 ls_operand[LS_BASE] == (B) && \
1190 ls_operand[LS_OFFSET] == (O)))
1192 int test
= insn
& I(-1);
1194 if (!(test
== I(1)))
1196 if ((ls_operand
[LS_DEST
] == OP_SHIMM
|| ls_operand
[LS_BASE
] == OP_SHIMM
1197 || ls_operand
[LS_OFFSET
] == OP_SHIMM
))
1198 *errmsg
= "invalid load/shimm insn";
1200 if (!(LD_SYNTAX(OP_REG
,OP_REG
,OP_NONE
)
1201 || LD_SYNTAX(OP_REG
,OP_REG
,OP_REG
)
1202 || LD_SYNTAX(OP_REG
,OP_REG
,OP_SHIMM
)
1203 || (LD_SYNTAX(OP_REG
,OP_LIMM
,OP_REG
) && !(test
== I(1)))
1204 || (LD_SYNTAX(OP_REG
,OP_REG
,OP_LIMM
) && !(test
== I(1)))
1205 || LD_SYNTAX(OP_REG
,OP_SHIMM
,OP_SHIMM
)
1206 || (LD_SYNTAX(OP_REG
,OP_LIMM
,OP_NONE
) && (test
== I(1)))))
1207 *errmsg
= "ld operand error";
1210 if (ls_operand
[LS_BASE
] != OP_REG
)
1211 *errmsg
= "address writeback not allowed";
1217 /* Used in ld insns to do final syntax check. */
1220 extract_ld_syntax (insn
, operand
, mods
, opval
, invalid
)
1222 const struct arc_operand
*operand ATTRIBUTE_UNUSED
;
1223 int mods ATTRIBUTE_UNUSED
;
1224 const struct arc_operand_value
**opval ATTRIBUTE_UNUSED
;
1227 int test
= insn
[0] & I(-1);
1229 if (!(test
== I(1)))
1231 if ((ls_operand
[LS_DEST
] == OP_SHIMM
|| ls_operand
[LS_BASE
] == OP_SHIMM
1232 || ls_operand
[LS_OFFSET
] == OP_SHIMM
))
1235 if (!((LD_SYNTAX(OP_REG
,OP_REG
,OP_NONE
) && (test
== I(1)))
1236 || LD_SYNTAX(OP_REG
,OP_REG
,OP_REG
)
1237 || LD_SYNTAX(OP_REG
,OP_REG
,OP_SHIMM
)
1238 || (LD_SYNTAX(OP_REG
,OP_REG
,OP_LIMM
) && !(test
== I(1)))
1239 || (LD_SYNTAX(OP_REG
,OP_LIMM
,OP_REG
) && !(test
== I(1)))
1240 || (LD_SYNTAX(OP_REG
,OP_SHIMM
,OP_NONE
) && (shimm
== 0))
1241 || LD_SYNTAX(OP_REG
,OP_SHIMM
,OP_SHIMM
)
1242 || (LD_SYNTAX(OP_REG
,OP_LIMM
,OP_NONE
) && (test
== I(1)))))
1247 /* Called at the end of processing normal insns (eg: add) to insert a shimm
1248 value (if present) into the insn. */
1251 insert_shimmfinish (insn
, operand
, mods
, reg
, value
, errmsg
)
1253 const struct arc_operand
*operand
;
1254 int mods ATTRIBUTE_UNUSED
;
1255 const struct arc_operand_value
*reg ATTRIBUTE_UNUSED
;
1256 long value ATTRIBUTE_UNUSED
;
1257 const char **errmsg ATTRIBUTE_UNUSED
;
1260 insn
|= (shimm
& ((1 << operand
->bits
) - 1)) << operand
->shift
;
1264 /* Called at the end of processing normal insns (eg: add) to insert a limm
1265 value (if present) into the insn.
1267 Note that this function is only intended to handle instructions (with 4 byte
1268 immediate operands). It is not intended to handle data. */
1270 /* ??? Actually, there's nothing for us to do as we can't call frag_more, the
1271 caller must do that. The extract fns take a pointer to two words. The
1272 insert fns could be converted and then we could do something useful, but
1273 then the reloc handlers would have to know to work on the second word of
1274 a 2 word quantity. That's too much so we don't handle them. */
1277 insert_limmfinish (insn
, operand
, mods
, reg
, value
, errmsg
)
1279 const struct arc_operand
*operand ATTRIBUTE_UNUSED
;
1280 int mods ATTRIBUTE_UNUSED
;
1281 const struct arc_operand_value
*reg ATTRIBUTE_UNUSED
;
1282 long value ATTRIBUTE_UNUSED
;
1283 const char **errmsg ATTRIBUTE_UNUSED
;
1287 ; /* nothing to do, gas does it. */
1293 insert_jumpflags (insn
, operand
, mods
, reg
, value
, errmsg
)
1295 const struct arc_operand
*operand
;
1296 int mods ATTRIBUTE_UNUSED
;
1297 const struct arc_operand_value
*reg ATTRIBUTE_UNUSED
;
1299 const char **errmsg
;
1303 *errmsg
= "jump flags, but no .f seen";
1307 *errmsg
= "jump flags, but no limm addr";
1309 if (limm
& 0xfc000000)
1311 *errmsg
= "flag bits of jump address limm lost";
1313 if (limm
& 0x03000000)
1315 *errmsg
= "attempt to set HR bits";
1317 if ((value
& ((1 << operand
->bits
) - 1)) != value
)
1319 *errmsg
= "bad jump flags value";
1322 limm
= ((limm
& ((1 << operand
->shift
) - 1))
1323 | ((value
& ((1 << operand
->bits
) - 1)) << operand
->shift
));
1327 /* Called at the end of unary operand macros to copy the B field to C. */
1330 insert_unopmacro (insn
, operand
, mods
, reg
, value
, errmsg
)
1332 const struct arc_operand
*operand
;
1333 int mods ATTRIBUTE_UNUSED
;
1334 const struct arc_operand_value
*reg ATTRIBUTE_UNUSED
;
1335 long value ATTRIBUTE_UNUSED
;
1336 const char **errmsg ATTRIBUTE_UNUSED
;
1338 insn
|= ((insn
>> ARC_SHIFT_REGB
) & ARC_MASK_REG
) << operand
->shift
;
1342 /* Insert a relative address for a branch insn (b, bl, or lp). */
1345 insert_reladdr (insn
, operand
, mods
, reg
, value
, errmsg
)
1347 const struct arc_operand
*operand
;
1348 int mods ATTRIBUTE_UNUSED
;
1349 const struct arc_operand_value
*reg ATTRIBUTE_UNUSED
;
1351 const char **errmsg
;
1354 *errmsg
= "branch address not on 4 byte boundary";
1355 insn
|= ((value
>> 2) & ((1 << operand
->bits
) - 1)) << operand
->shift
;
1359 /* Insert a limm value as a 26 bit address right shifted 2 into the insn.
1361 Note that this function is only intended to handle instructions (with 4 byte
1362 immediate operands). It is not intended to handle data. */
1364 /* ??? Actually, there's little for us to do as we can't call frag_more, the
1365 caller must do that. The extract fns take a pointer to two words. The
1366 insert fns could be converted and then we could do something useful, but
1367 then the reloc handlers would have to know to work on the second word of
1368 a 2 word quantity. That's too much so we don't handle them.
1370 We do check for correct usage of the nullify suffix, or we
1371 set the default correctly, though. */
1374 insert_absaddr (insn
, operand
, mods
, reg
, value
, errmsg
)
1376 const struct arc_operand
*operand ATTRIBUTE_UNUSED
;
1377 int mods ATTRIBUTE_UNUSED
;
1378 const struct arc_operand_value
*reg ATTRIBUTE_UNUSED
;
1379 long value ATTRIBUTE_UNUSED
;
1380 const char **errmsg
;
1384 /* if it is a jump and link, .jd must be specified. */
1385 if (insn
& R(-1,9,1))
1389 insn
|= 0x02 << 5; /* default nullify to .jd. */
1393 if (nullify
!= 0x02)
1395 *errmsg
= "must specify .jd or no nullify suffix";
1403 /* Extraction functions.
1405 The suffix extraction functions' return value is redundant since it can be
1406 obtained from (*OPVAL)->value. However, the boolean suffixes don't have
1407 a suffix table entry for the "false" case, so values of zero must be
1408 obtained from the return value (*OPVAL == NULL). */
1410 static const struct arc_operand_value
*lookup_register (int type
, long regno
);
1412 /* Called by the disassembler before printing an instruction. */
1415 arc_opcode_init_extract ()
1417 arc_opcode_init_insert();
1420 /* As we're extracting registers, keep an eye out for the 'f' indicator
1421 (ARC_REG_SHIMM_UPDATE). If we find a register (not a constant marker,
1422 like ARC_REG_SHIMM), set OPVAL so our caller will know this is a register.
1424 We must also handle auxiliary registers for lr/sr insns. They are just
1425 constants with special names. */
1428 extract_reg (insn
, operand
, mods
, opval
, invalid
)
1430 const struct arc_operand
*operand
;
1432 const struct arc_operand_value
**opval
;
1433 int *invalid ATTRIBUTE_UNUSED
;
1437 enum operand op_type
;
1439 /* Get the register number. */
1440 regno
= (*insn
>> operand
->shift
) & ((1 << operand
->bits
) - 1);
1442 /* Is it a constant marker? */
1443 if (regno
== ARC_REG_SHIMM
)
1446 /* always return zero if dest is a shimm mlm. */
1448 if ('a' != operand
->fmt
)
1450 value
= *insn
& 511;
1451 if ((operand
->flags
& ARC_OPERAND_SIGNED
)
1454 if (!flagshimm_handled_p
)
1456 flagshimm_handled_p
= 1;
1463 else if (regno
== ARC_REG_SHIMM_UPDATE
)
1467 /* always return zero if dest is a shimm mlm. */
1469 if ('a' != operand
->fmt
)
1471 value
= *insn
& 511;
1472 if ((operand
->flags
& ARC_OPERAND_SIGNED
) && (value
& 256))
1480 flagshimm_handled_p
= 1;
1482 else if (regno
== ARC_REG_LIMM
)
1487 /* if this is a jump instruction (j,jl), show new pc correctly. */
1488 if (0x07 == ((*insn
& I(-1)) >> 27))
1490 value
= (value
& 0xffffff);
1493 /* It's a register, set OPVAL (that's the only way we distinguish registers
1494 from constants here). */
1497 const struct arc_operand_value
*reg
= lookup_register (REG
, regno
);
1507 /* If this field takes an auxiliary register, see if it's a known one. */
1508 if ((mods
& ARC_MOD_AUXREG
)
1509 && ARC_REG_CONSTANT_P (regno
))
1511 const struct arc_operand_value
*reg
= lookup_register (AUXREG
, value
);
1513 /* This is really a constant, but tell the caller it has a special
1515 if (reg
!= NULL
&& opval
!= NULL
)
1518 switch(operand
->fmt
)
1521 ls_operand
[LS_DEST
] = op_type
;
1524 ls_operand
[LS_BASE
] = op_type
;
1527 if ((insn
[0]& I(-1)) == I(2))
1528 ls_operand
[LS_VALUE
] = op_type
;
1530 ls_operand
[LS_OFFSET
] = op_type
;
1533 ls_operand
[LS_OFFSET
] = op_type
;
1540 /* Return the value of the "flag update" field for shimm insns.
1541 This value is actually stored in the register field. */
1544 extract_flag (insn
, operand
, mods
, opval
, invalid
)
1546 const struct arc_operand
*operand
;
1547 int mods ATTRIBUTE_UNUSED
;
1548 const struct arc_operand_value
**opval
;
1549 int *invalid ATTRIBUTE_UNUSED
;
1552 const struct arc_operand_value
*val
;
1554 if (flagshimm_handled_p
)
1557 f
= (*insn
& (1 << operand
->shift
)) != 0;
1559 /* There is no text for zero values. */
1563 val
= arc_opcode_lookup_suffix (operand
, 1);
1564 if (opval
!= NULL
&& val
!= NULL
)
1569 /* Extract the condition code (if it exists).
1570 If we've seen a shimm value in this insn (meaning that the insn can't have
1571 a condition code field), then we don't store anything in OPVAL and return
1575 extract_cond (insn
, operand
, mods
, opval
, invalid
)
1577 const struct arc_operand
*operand
;
1578 int mods ATTRIBUTE_UNUSED
;
1579 const struct arc_operand_value
**opval
;
1580 int *invalid ATTRIBUTE_UNUSED
;
1583 const struct arc_operand_value
*val
;
1585 if (flagshimm_handled_p
)
1588 cond
= (*insn
>> operand
->shift
) & ((1 << operand
->bits
) - 1);
1589 val
= arc_opcode_lookup_suffix (operand
, cond
);
1591 /* Ignore NULL values of `val'. Several condition code values are
1592 reserved for extensions. */
1593 if (opval
!= NULL
&& val
!= NULL
)
1598 /* Extract a branch address.
1599 We return the value as a real address (not right shifted by 2). */
1602 extract_reladdr (insn
, operand
, mods
, opval
, invalid
)
1604 const struct arc_operand
*operand
;
1605 int mods ATTRIBUTE_UNUSED
;
1606 const struct arc_operand_value
**opval ATTRIBUTE_UNUSED
;
1607 int *invalid ATTRIBUTE_UNUSED
;
1611 addr
= (*insn
>> operand
->shift
) & ((1 << operand
->bits
) - 1);
1612 if ((operand
->flags
& ARC_OPERAND_SIGNED
)
1613 && (addr
& (1 << (operand
->bits
- 1))))
1614 addr
-= 1 << operand
->bits
;
1618 /* extract the flags bits from a j or jl long immediate. */
1620 extract_jumpflags(insn
, operand
, mods
, opval
, invalid
)
1622 const struct arc_operand
*operand
;
1623 int mods ATTRIBUTE_UNUSED
;
1624 const struct arc_operand_value
**opval ATTRIBUTE_UNUSED
;
1627 if (!flag_p
|| !limm_p
)
1629 return ((flag_p
&& limm_p
)
1630 ? (insn
[1] >> operand
->shift
) & ((1 << operand
->bits
) -1): 0);
1633 /* extract st insn's offset. */
1636 extract_st_offset (insn
, operand
, mods
, opval
, invalid
)
1638 const struct arc_operand
*operand
;
1639 int mods ATTRIBUTE_UNUSED
;
1640 const struct arc_operand_value
**opval ATTRIBUTE_UNUSED
;
1645 if (ls_operand
[LS_VALUE
] != OP_SHIMM
|| ls_operand
[LS_BASE
] != OP_LIMM
)
1647 value
= insn
[0] & 511;
1648 if ((operand
->flags
& ARC_OPERAND_SIGNED
) && (value
& 256))
1651 ls_operand
[LS_OFFSET
] = OP_SHIMM
;
1660 /* extract ld insn's offset. */
1663 extract_ld_offset (insn
, operand
, mods
, opval
, invalid
)
1665 const struct arc_operand
*operand
;
1667 const struct arc_operand_value
**opval
;
1670 int test
= insn
[0] & I(-1);
1675 value
= insn
[0] & 511;
1676 if ((operand
->flags
& ARC_OPERAND_SIGNED
) && (value
& 256))
1679 ls_operand
[LS_OFFSET
] = OP_SHIMM
;
1682 /* if it isn't in the insn, it's concealed behind reg 'c'. */
1683 return extract_reg (insn
, &arc_operands
[arc_operand_map
['c']],
1684 mods
, opval
, invalid
);
1687 /* The only thing this does is set the `invalid' flag if B != C.
1688 This is needed because the "mov" macro appears before it's real insn "and"
1689 and we don't want the disassembler to confuse them. */
1692 extract_unopmacro (insn
, operand
, mods
, opval
, invalid
)
1694 const struct arc_operand
*operand ATTRIBUTE_UNUSED
;
1695 int mods ATTRIBUTE_UNUSED
;
1696 const struct arc_operand_value
**opval ATTRIBUTE_UNUSED
;
1699 /* This misses the case where B == ARC_REG_SHIMM_UPDATE &&
1700 C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get
1701 printed as "and"s. */
1702 if (((*insn
>> ARC_SHIFT_REGB
) & ARC_MASK_REG
)
1703 != ((*insn
>> ARC_SHIFT_REGC
) & ARC_MASK_REG
))
1704 if (invalid
!= NULL
)
1709 /* Utility for the extraction functions to return the index into
1712 const struct arc_operand_value
*
1713 arc_opcode_lookup_suffix (type
, value
)
1714 const struct arc_operand
*type
;
1717 register const struct arc_operand_value
*v
,*end
;
1718 struct arc_ext_operand_value
*ext_oper
= arc_ext_operands
;
1722 if (type
== &arc_operands
[ext_oper
->operand
.type
]
1723 && value
== ext_oper
->operand
.value
)
1724 return (&ext_oper
->operand
);
1725 ext_oper
= ext_oper
->next
;
1728 /* ??? This is a little slow and can be speeded up. */
1730 for (v
= arc_suffixes
, end
= arc_suffixes
+ arc_suffixes_count
; v
< end
; ++v
)
1731 if (type
== &arc_operands
[v
->type
]
1732 && value
== v
->value
)
1737 static const struct arc_operand_value
*
1738 lookup_register (type
, regno
)
1742 register const struct arc_operand_value
*r
,*end
;
1743 struct arc_ext_operand_value
*ext_oper
= arc_ext_operands
;
1747 if (ext_oper
->operand
.type
== type
&& ext_oper
->operand
.value
== regno
)
1748 return (&ext_oper
->operand
);
1749 ext_oper
= ext_oper
->next
;
1753 return &arc_reg_names
[regno
];
1755 /* ??? This is a little slow and can be speeded up. */
1757 for (r
= arc_reg_names
, end
= arc_reg_names
+ arc_reg_names_count
;
1759 if (type
== r
->type
&& regno
== r
->value
)
1768 return (insn
& (I(-1))) == I(0x7);
1772 arc_insn_not_jl(insn
)
1775 return ((insn
& (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1)))
1776 != (I(0x7) | R(-1,9,1)));
1780 arc_operand_type(int opertype
)
1797 struct arc_operand_value
*
1801 struct arc_ext_operand_value
*suffix
= arc_ext_operands
;
1805 if ((COND
== suffix
->operand
.type
)
1806 && !strcmp(s
,suffix
->operand
.name
))
1807 return(&suffix
->operand
);
1808 suffix
= suffix
->next
;
1814 arc_get_noshortcut_flag()
1816 return ARC_REGISTER_NOSHORT_CUT
;