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[ARC] Add SYNTAX_NOP and SYNTAX_1OP for extension instructions
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23 #include "sysdep.h"
24
25 #include "dis-asm.h"
26 #include "opcode/arm.h"
27 #include "opintl.h"
28 #include "safe-ctype.h"
29 #include "floatformat.h"
30
31 /* FIXME: This shouldn't be done here. */
32 #include "coff/internal.h"
33 #include "libcoff.h"
34 #include "elf-bfd.h"
35 #include "elf/internal.h"
36 #include "elf/arm.h"
37 #include "mach-o.h"
38
39 /* FIXME: Belongs in global header. */
40 #ifndef strneq
41 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
42 #endif
43
44 #ifndef NUM_ELEM
45 #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
46 #endif
47
48 /* Cached mapping symbol state. */
49 enum map_type
50 {
51 MAP_ARM,
52 MAP_THUMB,
53 MAP_DATA
54 };
55
56 struct arm_private_data
57 {
58 /* The features to use when disassembling optional instructions. */
59 arm_feature_set features;
60
61 /* Whether any mapping symbols are present in the provided symbol
62 table. -1 if we do not know yet, otherwise 0 or 1. */
63 int has_mapping_symbols;
64
65 /* Track the last type (although this doesn't seem to be useful) */
66 enum map_type last_type;
67
68 /* Tracking symbol table information */
69 int last_mapping_sym;
70 bfd_vma last_mapping_addr;
71 };
72
73 struct opcode32
74 {
75 arm_feature_set arch; /* Architecture defining this insn. */
76 unsigned long value; /* If arch is 0 then value is a sentinel. */
77 unsigned long mask; /* Recognise insn if (op & mask) == value. */
78 const char * assembler; /* How to disassemble this insn. */
79 };
80
81 struct opcode16
82 {
83 arm_feature_set arch; /* Architecture defining this insn. */
84 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
85 const char *assembler; /* How to disassemble this insn. */
86 };
87
88 /* print_insn_coprocessor recognizes the following format control codes:
89
90 %% %
91
92 %c print condition code (always bits 28-31 in ARM mode)
93 %q print shifter argument
94 %u print condition code (unconditional in ARM mode,
95 UNPREDICTABLE if not AL in Thumb)
96 %A print address for ldc/stc/ldf/stf instruction
97 %B print vstm/vldm register list
98 %I print cirrus signed shift immediate: bits 0..3|4..6
99 %F print the COUNT field of a LFM/SFM instruction.
100 %P print floating point precision in arithmetic insn
101 %Q print floating point precision in ldf/stf insn
102 %R print floating point rounding mode
103
104 %<bitfield>c print as a condition code (for vsel)
105 %<bitfield>r print as an ARM register
106 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
107 %<bitfield>ru as %<>r but each u register must be unique.
108 %<bitfield>d print the bitfield in decimal
109 %<bitfield>k print immediate for VFPv3 conversion instruction
110 %<bitfield>x print the bitfield in hex
111 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
112 %<bitfield>f print a floating point constant if >7 else a
113 floating point register
114 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
115 %<bitfield>g print as an iWMMXt 64-bit register
116 %<bitfield>G print as an iWMMXt general purpose or control register
117 %<bitfield>D print as a NEON D register
118 %<bitfield>Q print as a NEON Q register
119 %<bitfield>E print a quarter-float immediate value
120
121 %y<code> print a single precision VFP reg.
122 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
123 %z<code> print a double precision VFP reg
124 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
125
126 %<bitfield>'c print specified char iff bitfield is all ones
127 %<bitfield>`c print specified char iff bitfield is all zeroes
128 %<bitfield>?ab... select from array of values in big endian order
129
130 %L print as an iWMMXt N/M width field.
131 %Z print the Immediate of a WSHUFH instruction.
132 %l like 'A' except use byte offsets for 'B' & 'H'
133 versions.
134 %i print 5-bit immediate in bits 8,3..0
135 (print "32" when 0)
136 %r print register offset address for wldt/wstr instruction. */
137
138 enum opcode_sentinel_enum
139 {
140 SENTINEL_IWMMXT_START = 1,
141 SENTINEL_IWMMXT_END,
142 SENTINEL_GENERIC_START
143 } opcode_sentinels;
144
145 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
146 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
147
148 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
149
150 static const struct opcode32 coprocessor_opcodes[] =
151 {
152 /* XScale instructions. */
153 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
154 0x0e200010, 0x0fff0ff0,
155 "mia%c\tacc0, %0-3r, %12-15r"},
156 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
157 0x0e280010, 0x0fff0ff0,
158 "miaph%c\tacc0, %0-3r, %12-15r"},
159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
160 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
163 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
164 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
165
166 /* Intel Wireless MMX technology instructions. */
167 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
168 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
169 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
171 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
173 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
175 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
177 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
240 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
241 0x0e800120, 0x0f800ff0,
242 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
244 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
246 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
248 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
250 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
255 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
256 0x0e8000a0, 0x0f800ff0,
257 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
259 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
261 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
263 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
265 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
318 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
319 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
320 {ARM_FEATURE_CORE_LOW (0),
321 SENTINEL_IWMMXT_END, 0, "" },
322
323 /* Floating point coprocessor (FPA) instructions. */
324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
325 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
327 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
329 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
331 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
405 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
407 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
408 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
409 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
410
411 /* Register load/store. */
412 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
413 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
414 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
415 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
416 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
417 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
419 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
421 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
423 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
425 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
427 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
429 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
431 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
433 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
435 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
437 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
439 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
441 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
443 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
444
445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
446 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
448 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
450 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
451 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
452 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
453
454 /* Data transfer between ARM and NEON registers. */
455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
456 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
458 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
460 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
462 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
464 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
466 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
468 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
482 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
483 /* Half-precision conversion instructions. */
484 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
485 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
486 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
487 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
488 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
489 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
490 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
491 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
492
493 /* Floating point coprocessor (VFP) instructions. */
494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
495 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
496 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
497 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
498 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
499 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
501 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
503 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
505 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
507 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
509 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
521 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
523 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
525 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
527 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
529 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
531 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
533 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
535 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
537 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
539 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
541 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
543 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
545 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
547 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
549 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
551 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
553 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
555 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
557 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
559 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
561 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
563 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
565 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
567 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
569 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
571 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
573 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
575 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
577 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
579 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
581 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
583 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
585 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
587 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
589 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
591 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
593 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
595 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
597 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
599 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
601 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
603 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
605 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
607 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
609 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
611 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
613 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
615 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
617 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
619 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
621 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
623 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
625 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
627 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
628
629 /* Cirrus coprocessor instructions. */
630 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
631 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
632 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
633 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
634 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
635 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
636 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
637 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
638 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
639 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
641 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
643 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
791 0x0e000600, 0x0ff00f10,
792 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
793 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
794 0x0e100600, 0x0ff00f10,
795 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
796 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
797 0x0e200600, 0x0ff00f10,
798 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
799 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
800 0x0e300600, 0x0ff00f10,
801 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
802
803 /* VFP Fused multiply add instructions. */
804 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
805 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
806 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
807 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
808 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
809 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
810 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
811 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
812 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
813 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
815 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
817 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
819 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
820
821 /* FP v5. */
822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
825 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
827 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
828 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
829 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
831 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
833 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
835 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
837 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
839 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
841 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
843 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
845 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
846
847 /* Generic coprocessor instructions. */
848 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
850 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
852 0x0c500000, 0x0ff00000,
853 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
855 0x0e000000, 0x0f000010,
856 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
858 0x0e10f010, 0x0f10f010,
859 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
861 0x0e100010, 0x0f100010,
862 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
864 0x0e000010, 0x0f100010,
865 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
867 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
869 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
870
871 /* V6 coprocessor instructions. */
872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
873 0xfc500000, 0xfff00000,
874 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
876 0xfc400000, 0xfff00000,
877 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
878
879 /* V5 coprocessor instructions. */
880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
881 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
883 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
885 0xfe000000, 0xff000010,
886 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
888 0xfe000010, 0xff100010,
889 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
891 0xfe100010, 0xff100010,
892 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
893
894 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
895 cp_num: bit <11:8> == 0b1001.
896 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
897 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
898 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
899 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
900 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
901 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
902 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
903 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
904 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
906 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
907 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
908 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
909 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
910 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
911 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
912 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
913 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
914 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
915 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
916 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
917 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
918 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
919 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
920 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
921 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
922 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
923 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
924 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
926 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
927 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
928 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
929 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
930 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
931 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
932 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
933 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
934 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
935 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
936 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
937 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
938 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
939 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
940 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
941 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
942 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
943 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
944 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
945 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
946 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
947 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
948 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
949 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
950 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
951 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
952 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
954 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
956 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
958 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
960 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
961 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
962 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
963 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
964 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
966 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
967
968 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
969 };
970
971 /* Neon opcode table: This does not encode the top byte -- that is
972 checked by the print_insn_neon routine, as it depends on whether we are
973 doing thumb32 or arm32 disassembly. */
974
975 /* print_insn_neon recognizes the following format control codes:
976
977 %% %
978
979 %c print condition code
980 %u print condition code (unconditional in ARM mode,
981 UNPREDICTABLE if not AL in Thumb)
982 %A print v{st,ld}[1234] operands
983 %B print v{st,ld}[1234] any one operands
984 %C print v{st,ld}[1234] single->all operands
985 %D print scalar
986 %E print vmov, vmvn, vorr, vbic encoded constant
987 %F print vtbl,vtbx register list
988
989 %<bitfield>r print as an ARM register
990 %<bitfield>d print the bitfield in decimal
991 %<bitfield>e print the 2^N - bitfield in decimal
992 %<bitfield>D print as a NEON D register
993 %<bitfield>Q print as a NEON Q register
994 %<bitfield>R print as a NEON D or Q register
995 %<bitfield>Sn print byte scaled width limited by n
996 %<bitfield>Tn print short scaled width limited by n
997 %<bitfield>Un print long scaled width limited by n
998
999 %<bitfield>'c print specified char iff bitfield is all ones
1000 %<bitfield>`c print specified char iff bitfield is all zeroes
1001 %<bitfield>?ab... select from array of values in big endian order. */
1002
1003 static const struct opcode32 neon_opcodes[] =
1004 {
1005 /* Extract. */
1006 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1007 0xf2b00840, 0xffb00850,
1008 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1009 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1010 0xf2b00000, 0xffb00810,
1011 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1012
1013 /* Move data element to all lanes. */
1014 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1015 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1016 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1017 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1018 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1019 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1020
1021 /* Table lookup. */
1022 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1023 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1025 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1026
1027 /* Half-precision conversions. */
1028 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1029 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1030 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1031 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1032
1033 /* NEON fused multiply add instructions. */
1034 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1035 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1036 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1037 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1038 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1039 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1040 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1041 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1042
1043 /* Two registers, miscellaneous. */
1044 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1045 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1046 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1047 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1048 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1049 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1050 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1051 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1052 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1053 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1054 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1055 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1056 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1057 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1058 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1059 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1060 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1061 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1062 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1063 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1064 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1065 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1066 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1067 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1069 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1071 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1073 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1079 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1081 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1085 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1087 0xf3b20300, 0xffb30fd0,
1088 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1089 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1090 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1091 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1092 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1093 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1094 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1095 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1096 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1097 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1098 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1099 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1100 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1101 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1102 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1103 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1104 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1105 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1106 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1107 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1108 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1109 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1110 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1111 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1112 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1113 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1114 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1116 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1117 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1118 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1119 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1120 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1121 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1122 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1123 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1124 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1125 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1126 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1127 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1128 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1129 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1130 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1131 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1132 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1133 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1134 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1135 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1136 0xf3bb0600, 0xffbf0e10,
1137 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1138 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1139 0xf3b70600, 0xffbf0e10,
1140 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1141
1142 /* Three registers of the same length. */
1143 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1144 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1145 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1146 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1147 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1148 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1149 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1150 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1151 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1152 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1153 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1154 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1155 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1156 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1158 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1159 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1160 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1161 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1162 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1163 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1164 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1165 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1166 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1168 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1171 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1172 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1177 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1178 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1179 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1180 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1181 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1182 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1183 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1184 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1185 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1186 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1187 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1188 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1189 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1190 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1191 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1192 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1193 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1194 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1195 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1196 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1197 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1198 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1199 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1200 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1201 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1202 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1203 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1204 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1205 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1206 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1207 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1208 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1209 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1210 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1211 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1212 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1213 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1214 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1215 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1216 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1219 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1220 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1221 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1222 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1223 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1224 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1225 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1227 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1228 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1229 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1231 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1232 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1233 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1234 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1235 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1236 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1239 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1240 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1241 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1242 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1244 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1245 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1246 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1247 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1248 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1249 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1250 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1251 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1252 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1253 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1254 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1255 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1256 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1257 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1258 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1259 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1260 0xf2000b00, 0xff800f10,
1261 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1262 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1263 0xf2000b10, 0xff800f10,
1264 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1265 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1266 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1267 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1268 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1269 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1270 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272 0xf3000b00, 0xff800f10,
1273 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1274 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1275 0xf2000000, 0xfe800f10,
1276 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278 0xf2000010, 0xfe800f10,
1279 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1280 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1281 0xf2000100, 0xfe800f10,
1282 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284 0xf2000200, 0xfe800f10,
1285 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1286 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1287 0xf2000210, 0xfe800f10,
1288 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290 0xf2000300, 0xfe800f10,
1291 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1292 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1293 0xf2000310, 0xfe800f10,
1294 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf2000400, 0xfe800f10,
1297 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1299 0xf2000410, 0xfe800f10,
1300 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302 0xf2000500, 0xfe800f10,
1303 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1304 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1305 0xf2000510, 0xfe800f10,
1306 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308 0xf2000600, 0xfe800f10,
1309 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1310 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1311 0xf2000610, 0xfe800f10,
1312 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314 0xf2000700, 0xfe800f10,
1315 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317 0xf2000710, 0xfe800f10,
1318 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320 0xf2000910, 0xfe800f10,
1321 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0xf2000a00, 0xfe800f10,
1324 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326 0xf2000a10, 0xfe800f10,
1327 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1329 0xf3000b10, 0xff800f10,
1330 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1331 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1332 0xf3000c10, 0xff800f10,
1333 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1334
1335 /* One register and an immediate value. */
1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1337 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1343 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1348 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1349 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1354 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1355 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1357 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1358 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1359 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1361 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1362
1363 /* Two registers and a shift amount. */
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1366 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1367 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1369 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1372 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1373 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1375 0xf2880950, 0xfeb80fd0,
1376 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1382 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1387 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1388 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1390 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1392 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1393 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1394 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1395 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1396 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1398 0xf2900950, 0xfeb00fd0,
1399 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1437 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443 0xf2a00950, 0xfea00fd0,
1444 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1458 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1460 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1462 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1464 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1466 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1468 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1470 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1472 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482 0xf2a00e10, 0xfea00e90,
1483 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1484 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1485 0xf2a00c10, 0xfea00e90,
1486 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1487
1488 /* Three registers of different lengths. */
1489 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1490 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf2800400, 0xff800f50,
1495 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497 0xf2800600, 0xff800f50,
1498 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500 0xf2800900, 0xff800f50,
1501 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503 0xf2800b00, 0xff800f50,
1504 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf2800d00, 0xff800f50,
1507 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1509 0xf3800400, 0xff800f50,
1510 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf3800600, 0xff800f50,
1513 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1515 0xf2800000, 0xfe800f50,
1516 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf2800100, 0xfe800f50,
1519 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1521 0xf2800200, 0xfe800f50,
1522 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf2800300, 0xfe800f50,
1525 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1527 0xf2800500, 0xfe800f50,
1528 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf2800700, 0xfe800f50,
1531 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1533 0xf2800800, 0xfe800f50,
1534 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf2800a00, 0xfe800f50,
1537 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539 0xf2800c00, 0xfe800f50,
1540 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1541
1542 /* Two registers and a scalar. */
1543 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1544 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1547 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1548 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1549 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1550 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1555 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1556 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1561 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1562 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1563 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1564 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1567 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1568 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1574 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1575 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1576 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1580 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1581 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1582 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1587 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1588 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1592 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594 0xf2800240, 0xfe800f50,
1595 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597 0xf2800640, 0xfe800f50,
1598 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600 0xf2800a40, 0xfe800f50,
1601 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1603 0xf2800e40, 0xff800f50,
1604 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1606 0xf2800f40, 0xff800f50,
1607 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1609 0xf3800e40, 0xff800f50,
1610 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1612 0xf3800f40, 0xff800f50,
1613 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1614 },
1615
1616 /* Element and structure load/store. */
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1655
1656 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1657 };
1658
1659 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1660 ordered: they must be searched linearly from the top to obtain a correct
1661 match. */
1662
1663 /* print_insn_arm recognizes the following format control codes:
1664
1665 %% %
1666
1667 %a print address for ldr/str instruction
1668 %s print address for ldr/str halfword/signextend instruction
1669 %S like %s but allow UNPREDICTABLE addressing
1670 %b print branch destination
1671 %c print condition code (always bits 28-31)
1672 %m print register mask for ldm/stm instruction
1673 %o print operand2 (immediate or register + shift)
1674 %p print 'p' iff bits 12-15 are 15
1675 %t print 't' iff bit 21 set and bit 24 clear
1676 %B print arm BLX(1) destination
1677 %C print the PSR sub type.
1678 %U print barrier type.
1679 %P print address for pli instruction.
1680
1681 %<bitfield>r print as an ARM register
1682 %<bitfield>T print as an ARM register + 1
1683 %<bitfield>R as %r but r15 is UNPREDICTABLE
1684 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1685 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1686 %<bitfield>d print the bitfield in decimal
1687 %<bitfield>W print the bitfield plus one in decimal
1688 %<bitfield>x print the bitfield in hex
1689 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
1690
1691 %<bitfield>'c print specified char iff bitfield is all ones
1692 %<bitfield>`c print specified char iff bitfield is all zeroes
1693 %<bitfield>?ab... select from array of values in big endian order
1694
1695 %e print arm SMI operand (bits 0..7,8..19).
1696 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
1697 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1698 %R print the SPSR/CPSR or banked register of an MRS. */
1699
1700 static const struct opcode32 arm_opcodes[] =
1701 {
1702 /* ARM instructions. */
1703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1704 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1706 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1707
1708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1709 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1711 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1713 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1715 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1717 0x00800090, 0x0fa000f0,
1718 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1720 0x00a00090, 0x0fa000f0,
1721 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1722
1723 /* V8.2 RAS extension instructions. */
1724 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
1725 0xe320f010, 0xffffffff, "esb"},
1726
1727 /* V8 instructions. */
1728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1729 0x0320f005, 0x0fffffff, "sevl"},
1730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1731 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1732 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
1733 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1734 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1735 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1737 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1739 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1740 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1741 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1742 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1743 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1744 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1745 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1746 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1747 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1748 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1749 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1750 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1751 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1752 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1753 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1754 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1755 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1756 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1757 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1758 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1759 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
1760 /* CRC32 instructions. */
1761 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1762 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1763 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1764 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1765 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1766 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1767 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1768 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1769 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1770 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1771 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1772 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
1773
1774 /* Privileged Access Never extension instructions. */
1775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1776 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1777
1778 /* Virtualization Extension instructions. */
1779 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1780 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
1781
1782 /* Integer Divide Extension instructions. */
1783 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1784 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1785 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1786 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
1787
1788 /* MP Extension instructions. */
1789 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
1790
1791 /* V7 instructions. */
1792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
1799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1800 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
1801
1802 /* ARM V6T2 instructions. */
1803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1804 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1806 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1808 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1810 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1811
1812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1813 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1815 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1816
1817 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1818 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1819 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1820 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1822 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1824 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
1825
1826 /* ARM Security extension instructions. */
1827 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1828 0x01600070, 0x0ff000f0, "smc%c\t%e"},
1829
1830 /* ARM V6K instructions. */
1831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1832 0xf57ff01f, 0xffffffff, "clrex"},
1833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1834 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1836 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1838 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1840 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1842 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1844 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
1845
1846 /* ARM V6K NOP hints. */
1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1848 0x0320f001, 0x0fffffff, "yield%c"},
1849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1850 0x0320f002, 0x0fffffff, "wfe%c"},
1851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1852 0x0320f003, 0x0fffffff, "wfi%c"},
1853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1854 0x0320f004, 0x0fffffff, "sev%c"},
1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1856 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
1857
1858 /* ARM V6 instructions. */
1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1860 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1862 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1864 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1866 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1868 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1870 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1872 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1874 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1876 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1878 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1880 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1882 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1884 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1886 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1888 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1890 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1892 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1894 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1896 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1898 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1900 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1902 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1904 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1906 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1908 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1910 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1912 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1914 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1916 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1918 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1920 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1922 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1924 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1926 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1956 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1958 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1960 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1962 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1964 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1966 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1968 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1970 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1972 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1974 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1976 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1978 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1980 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1982 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1984 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1986 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1988 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1990 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1992 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1994 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1996 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1998 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2000 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2002 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2004 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2006 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2008 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2010 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2012 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2014 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2016 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2018 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2020 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2022 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2024 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2026 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2028 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2030 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2032 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2034 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2036 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2038 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2040 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2042 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2044 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2046 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2048 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2050 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2052 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2054 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2056 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2058 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2060 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2062 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2064 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2066 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2068 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2070 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2072 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2074 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2076 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2078 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2080 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2082 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2084 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2086 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2088 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2090 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2092 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2094 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2096 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2098 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2100 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2102 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
2103
2104 /* V5J instruction. */
2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2106 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
2107
2108 /* V5 Instructions. */
2109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2110 0xe1200070, 0xfff000f0,
2111 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2113 0xfa000000, 0xfe000000, "blx\t%B"},
2114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2115 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2117 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2118
2119 /* V5E "El Segundo" Instructions. */
2120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2121 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2123 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2125 0xf450f000, 0xfc70f000, "pld\t%a"},
2126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2127 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2129 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2131 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2133 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2134
2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2136 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2138 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2139
2140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2141 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2143 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2145 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2147 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2148
2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2150 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2152 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2154 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2156 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2157
2158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2159 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2161 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2162
2163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2164 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2166 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2168 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2170 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2171
2172 /* ARM Instructions. */
2173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2174 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2175
2176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2177 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2179 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2181 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2183 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2185 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2187 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2188
2189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2190 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2192 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2194 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2196 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2197
2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2199 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2201 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2203 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2205 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2206
2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2208 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2210 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2212 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2213
2214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2215 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2217 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2219 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2220
2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2222 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2224 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2226 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2227
2228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2229 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2231 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2233 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2234
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2236 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2238 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2240 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2241
2242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2243 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2245 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2247 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2248
2249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2250 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2252 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2254 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2255
2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2257 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2261 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2262
2263 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2264 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2266 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2268 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2269
2270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2271 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2273 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2275 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2276
2277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2278 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2280 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2282 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2284 0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"},
2285
2286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2287 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2289 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2291 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2292
2293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2294 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2296 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2298 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2299
2300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2301 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2303 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2305 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2306
2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2308 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2310 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2312 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2314 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2316 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2318 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2320 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2321
2322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2323 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2325 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2327 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2328
2329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2330 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2332 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2334 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2335
2336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2337 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2339 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2340
2341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2342 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2343
2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2345 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2347 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2348
2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2350 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2352 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2354 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2356 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2358 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2360 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2362 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2364 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2366 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2368 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2370 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2372 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2374 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2376 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2378 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2380 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2382 0x092d0000, 0x0fff0000, "push%c\t%m"},
2383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2384 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2386 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2387
2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2389 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2391 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2393 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2395 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2397 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2399 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2401 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2403 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2405 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2407 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2409 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2411 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2413 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2415 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2417 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2419 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2421 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2423 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2425 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2426
2427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2428 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2430 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2431
2432 /* The rest. */
2433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2434 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
2435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2436 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2437 {ARM_FEATURE_CORE_LOW (0),
2438 0x00000000, 0x00000000, 0}
2439 };
2440
2441 /* print_insn_thumb16 recognizes the following format control codes:
2442
2443 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2444 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2445 %<bitfield>I print bitfield as a signed decimal
2446 (top bit of range being the sign bit)
2447 %N print Thumb register mask (with LR)
2448 %O print Thumb register mask (with PC)
2449 %M print Thumb register mask
2450 %b print CZB's 6-bit unsigned branch destination
2451 %s print Thumb right-shift immediate (6..10; 0 == 32).
2452 %c print the condition code
2453 %C print the condition code, or "s" if not conditional
2454 %x print warning if conditional an not at end of IT block"
2455 %X print "\t; unpredictable <IT:code>" if conditional
2456 %I print IT instruction suffix and operands
2457 %W print Thumb Writeback indicator for LDMIA
2458 %<bitfield>r print bitfield as an ARM register
2459 %<bitfield>d print bitfield as a decimal
2460 %<bitfield>H print (bitfield * 2) as a decimal
2461 %<bitfield>W print (bitfield * 4) as a decimal
2462 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2463 %<bitfield>B print Thumb branch destination (signed displacement)
2464 %<bitfield>c print bitfield as a condition code
2465 %<bitnum>'c print specified char iff bit is one
2466 %<bitnum>?ab print a if bit is one else print b. */
2467
2468 static const struct opcode16 thumb_opcodes[] =
2469 {
2470 /* Thumb instructions. */
2471
2472 /* ARM V8 instructions. */
2473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
2475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
2476
2477 /* ARM V6K no-argument instructions. */
2478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2484
2485 /* ARM V6T2 instructions. */
2486 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2487 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2488 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2489 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
2491
2492 /* ARM V6. */
2493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2504
2505 /* ARM V5 ISA extends Thumb. */
2506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2507 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
2508 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
2509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2510 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
2511 /* ARM V4T ISA (Thumb v1). */
2512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2513 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2514 /* Format 4. */
2515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2529 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2531 /* format 13 */
2532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2534 /* format 5 */
2535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2539 /* format 14 */
2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
2542 /* format 2 */
2543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2544 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2546 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2548 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2550 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2551 /* format 8 */
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2553 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2555 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2557 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2558 /* format 7 */
2559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2560 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2562 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2563 /* format 1 */
2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2566 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2569 /* format 3 */
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2574 /* format 6 */
2575 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2577 0x4800, 0xF800,
2578 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2579 /* format 9 */
2580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2581 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2583 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2585 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2587 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2588 /* format 10 */
2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2590 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2592 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2593 /* format 11 */
2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2595 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2597 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2598 /* format 12 */
2599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2600 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2602 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2603 /* format 15 */
2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2606 /* format 17 */
2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2608 /* format 16 */
2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2612 /* format 18 */
2613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2614
2615 /* The E800 .. FFFF range is unconditionally redirected to the
2616 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2617 are processed via that table. Thus, we can never encounter a
2618 bare "second half of BL/BLX(1)" instruction here. */
2619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2620 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2621 };
2622
2623 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2624 We adopt the convention that hw1 is the high 16 bits of .value and
2625 .mask, hw2 the low 16 bits.
2626
2627 print_insn_thumb32 recognizes the following format control codes:
2628
2629 %% %
2630
2631 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2632 %M print a modified 12-bit immediate (same location)
2633 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2634 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2635 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
2636 %S print a possibly-shifted Rm
2637
2638 %L print address for a ldrd/strd instruction
2639 %a print the address of a plain load/store
2640 %w print the width and signedness of a core load/store
2641 %m print register mask for ldm/stm
2642
2643 %E print the lsb and width fields of a bfc/bfi instruction
2644 %F print the lsb and width fields of a sbfx/ubfx instruction
2645 %b print a conditional branch offset
2646 %B print an unconditional branch offset
2647 %s print the shift field of an SSAT instruction
2648 %R print the rotation field of an SXT instruction
2649 %U print barrier type.
2650 %P print address for pli instruction.
2651 %c print the condition code
2652 %x print warning if conditional an not at end of IT block"
2653 %X print "\t; unpredictable <IT:code>" if conditional
2654
2655 %<bitfield>d print bitfield in decimal
2656 %<bitfield>D print bitfield plus one in decimal
2657 %<bitfield>W print bitfield*4 in decimal
2658 %<bitfield>r print bitfield as an ARM register
2659 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2660 %<bitfield>S as %<>R but r13 is UNPREDICTABLE
2661 %<bitfield>c print bitfield as a condition code
2662
2663 %<bitfield>'c print specified char iff bitfield is all ones
2664 %<bitfield>`c print specified char iff bitfield is all zeroes
2665 %<bitfield>?ab... select from array of values in big endian order
2666
2667 With one exception at the bottom (done because BL and BLX(1) need
2668 to come dead last), this table was machine-sorted first in
2669 decreasing order of number of bits set in the mask, then in
2670 increasing numeric order of mask, then in increasing numeric order
2671 of opcode. This order is not the clearest for a human reader, but
2672 is guaranteed never to catch a special-case bit pattern with a more
2673 general mask, which is important, because this instruction encoding
2674 makes heavy use of special-case bit patterns. */
2675 static const struct opcode32 thumb32_opcodes[] =
2676 {
2677 /* V8-M instructions. */
2678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2679 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2681 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2682
2683 /* ARM V8.2 RAS extension instructions. */
2684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
2685 0xf3af8010, 0xffffffff, "esb"},
2686
2687 /* V8 instructions. */
2688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2689 0xf3af8005, 0xffffffff, "sevl%c.w"},
2690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2691 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2693 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2695 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2697 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2699 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2701 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2703 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2705 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2707 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2709 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2711 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2713 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2715 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2717 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2719 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
2720
2721 /* CRC32 instructions. */
2722 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2723 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2724 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2725 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2726 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2727 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2728 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2729 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2730 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2731 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2732 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2733 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
2734
2735 /* V7 instructions. */
2736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2743 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2744 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2745 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2746 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
2747
2748 /* Virtualization Extension instructions. */
2749 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
2750 /* We skip ERET as that is SUBS pc, lr, #0. */
2751
2752 /* MP Extension instructions. */
2753 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
2754
2755 /* Security extension instructions. */
2756 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
2757
2758 /* Instructions defined in the basic V6T2 set. */
2759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2765 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2767
2768 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2769 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2771 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2773 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2775 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2777 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2779 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2781 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2783 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2785 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2787 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2789 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2791 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2793 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2795 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2796 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2797 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2798 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2799 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2801 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2803 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2805 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2807 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2809 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2811 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2813 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2815 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2816 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2817 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2819 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2821 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2823 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2825 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2827 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2829 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2831 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2833 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2835 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2837 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2839 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2841 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2843 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2845 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2847 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2849 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2851 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2853 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2855 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2857 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2859 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2863 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2865 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2867 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2869 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2873 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2875 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2877 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2879 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2883 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2885 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2887 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2889 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2893 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2897 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2901 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2913 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2915 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
2924 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2925 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2951 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
2956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2957 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
2958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2959 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2961 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2963 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2965 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2967 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2971 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
2972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2973 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2975 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2977 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2979 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2981 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2983 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2985 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2987 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2989 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2991 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2992 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2993 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
2994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2995 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
2996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2997 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
2998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2999 0xf810f000, 0xff70f000, "pld%c\t%a"},
3000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3001 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3003 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3005 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3007 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3009 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3011 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3013 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3015 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3017 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3019 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3021 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3023 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3025 0xfb100000, 0xfff000c0,
3026 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3028 0xfbc00080, 0xfff000c0,
3029 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3031 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3033 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3035 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
3036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3037 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3039 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3040 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3041 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3043 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3044 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3045 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3047 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3049 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3051 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3053 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3055 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3057 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3059 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3061 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3063 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3065 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3066 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3067 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3069 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3071 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3073 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3075 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3077 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3079 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3081 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3083 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3085 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3087 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3089 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3091 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3093 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3095 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3097 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3099 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3101 0xe9400000, 0xff500000,
3102 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3104 0xe9500000, 0xff500000,
3105 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3107 0xe8600000, 0xff700000,
3108 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3110 0xe8700000, 0xff700000,
3111 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3113 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3115 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3116
3117 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
3118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3119 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3121 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3123 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3125 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3126
3127 /* These have been 32-bit since the invention of Thumb. */
3128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3129 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3131 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3132
3133 /* Fallback. */
3134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3135 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3136 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3137 };
3138
3139 static const char *const arm_conditional[] =
3140 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3141 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3142
3143 static const char *const arm_fp_const[] =
3144 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3145
3146 static const char *const arm_shift[] =
3147 {"lsl", "lsr", "asr", "ror"};
3148
3149 typedef struct
3150 {
3151 const char *name;
3152 const char *description;
3153 const char *reg_names[16];
3154 }
3155 arm_regname;
3156
3157 static const arm_regname regnames[] =
3158 {
3159 { "raw" , "Select raw register names",
3160 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3161 { "gcc", "Select register names used by GCC",
3162 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3163 { "std", "Select register names used in ARM's ISA documentation",
3164 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3165 { "apcs", "Select register names used in the APCS",
3166 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3167 { "atpcs", "Select register names used in the ATPCS",
3168 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3169 { "special-atpcs", "Select special register names used in the ATPCS",
3170 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
3171 };
3172
3173 static const char *const iwmmxt_wwnames[] =
3174 {"b", "h", "w", "d"};
3175
3176 static const char *const iwmmxt_wwssnames[] =
3177 {"b", "bus", "bc", "bss",
3178 "h", "hus", "hc", "hss",
3179 "w", "wus", "wc", "wss",
3180 "d", "dus", "dc", "dss"
3181 };
3182
3183 static const char *const iwmmxt_regnames[] =
3184 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3185 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3186 };
3187
3188 static const char *const iwmmxt_cregnames[] =
3189 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3190 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3191 };
3192
3193 /* Default to GCC register name set. */
3194 static unsigned int regname_selected = 1;
3195
3196 #define NUM_ARM_REGNAMES NUM_ELEM (regnames)
3197 #define arm_regnames regnames[regname_selected].reg_names
3198
3199 static bfd_boolean force_thumb = FALSE;
3200
3201 /* Current IT instruction state. This contains the same state as the IT
3202 bits in the CPSR. */
3203 static unsigned int ifthen_state;
3204 /* IT state for the next instruction. */
3205 static unsigned int ifthen_next_state;
3206 /* The address of the insn for which the IT state is valid. */
3207 static bfd_vma ifthen_address;
3208 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3209 /* Indicates that the current Conditional state is unconditional or outside
3210 an IT block. */
3211 #define COND_UNCOND 16
3212
3213 \f
3214 /* Functions. */
3215 int
3216 get_arm_regname_num_options (void)
3217 {
3218 return NUM_ARM_REGNAMES;
3219 }
3220
3221 int
3222 set_arm_regname_option (int option)
3223 {
3224 int old = regname_selected;
3225 regname_selected = option;
3226 return old;
3227 }
3228
3229 int
3230 get_arm_regnames (int option,
3231 const char **setname,
3232 const char **setdescription,
3233 const char *const **register_names)
3234 {
3235 *setname = regnames[option].name;
3236 *setdescription = regnames[option].description;
3237 *register_names = regnames[option].reg_names;
3238 return 16;
3239 }
3240
3241 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3242 Returns pointer to following character of the format string and
3243 fills in *VALUEP and *WIDTHP with the extracted value and number of
3244 bits extracted. WIDTHP can be NULL. */
3245
3246 static const char *
3247 arm_decode_bitfield (const char *ptr,
3248 unsigned long insn,
3249 unsigned long *valuep,
3250 int *widthp)
3251 {
3252 unsigned long value = 0;
3253 int width = 0;
3254
3255 do
3256 {
3257 int start, end;
3258 int bits;
3259
3260 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3261 start = start * 10 + *ptr - '0';
3262 if (*ptr == '-')
3263 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3264 end = end * 10 + *ptr - '0';
3265 else
3266 end = start;
3267 bits = end - start;
3268 if (bits < 0)
3269 abort ();
3270 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3271 width += bits + 1;
3272 }
3273 while (*ptr++ == ',');
3274 *valuep = value;
3275 if (widthp)
3276 *widthp = width;
3277 return ptr - 1;
3278 }
3279
3280 static void
3281 arm_decode_shift (long given, fprintf_ftype func, void *stream,
3282 bfd_boolean print_shift)
3283 {
3284 func (stream, "%s", arm_regnames[given & 0xf]);
3285
3286 if ((given & 0xff0) != 0)
3287 {
3288 if ((given & 0x10) == 0)
3289 {
3290 int amount = (given & 0xf80) >> 7;
3291 int shift = (given & 0x60) >> 5;
3292
3293 if (amount == 0)
3294 {
3295 if (shift == 3)
3296 {
3297 func (stream, ", rrx");
3298 return;
3299 }
3300
3301 amount = 32;
3302 }
3303
3304 if (print_shift)
3305 func (stream, ", %s #%d", arm_shift[shift], amount);
3306 else
3307 func (stream, ", #%d", amount);
3308 }
3309 else if ((given & 0x80) == 0x80)
3310 func (stream, "\t; <illegal shifter operand>");
3311 else if (print_shift)
3312 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3313 arm_regnames[(given & 0xf00) >> 8]);
3314 else
3315 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3316 }
3317 }
3318
3319 #define W_BIT 21
3320 #define I_BIT 22
3321 #define U_BIT 23
3322 #define P_BIT 24
3323
3324 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3325 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3326 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3327 #define PRE_BIT_SET (given & (1 << P_BIT))
3328
3329 /* Print one coprocessor instruction on INFO->STREAM.
3330 Return TRUE if the instuction matched, FALSE if this is not a
3331 recognised coprocessor instruction. */
3332
3333 static bfd_boolean
3334 print_insn_coprocessor (bfd_vma pc,
3335 struct disassemble_info *info,
3336 long given,
3337 bfd_boolean thumb)
3338 {
3339 const struct opcode32 *insn;
3340 void *stream = info->stream;
3341 fprintf_ftype func = info->fprintf_func;
3342 unsigned long mask;
3343 unsigned long value = 0;
3344 int cond;
3345 int cp_num;
3346 struct arm_private_data *private_data = info->private_data;
3347 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3348
3349 ARM_FEATURE_COPY (allowed_arches, private_data->features);
3350
3351 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3352 {
3353 unsigned long u_reg = 16;
3354 bfd_boolean is_unpredictable = FALSE;
3355 signed long value_in_comment = 0;
3356 const char *c;
3357
3358 if (ARM_FEATURE_ZERO (insn->arch))
3359 switch (insn->value)
3360 {
3361 case SENTINEL_IWMMXT_START:
3362 if (info->mach != bfd_mach_arm_XScale
3363 && info->mach != bfd_mach_arm_iWMMXt
3364 && info->mach != bfd_mach_arm_iWMMXt2)
3365 do
3366 insn++;
3367 while ((! ARM_FEATURE_ZERO (insn->arch))
3368 && insn->value != SENTINEL_IWMMXT_END);
3369 continue;
3370
3371 case SENTINEL_IWMMXT_END:
3372 continue;
3373
3374 case SENTINEL_GENERIC_START:
3375 ARM_FEATURE_COPY (allowed_arches, private_data->features);
3376 continue;
3377
3378 default:
3379 abort ();
3380 }
3381
3382 mask = insn->mask;
3383 value = insn->value;
3384 cp_num = (given >> 8) & 0xf;
3385
3386 if (thumb)
3387 {
3388 /* The high 4 bits are 0xe for Arm conditional instructions, and
3389 0xe for arm unconditional instructions. The rest of the
3390 encoding is the same. */
3391 mask |= 0xf0000000;
3392 value |= 0xe0000000;
3393 if (ifthen_state)
3394 cond = IFTHEN_COND;
3395 else
3396 cond = COND_UNCOND;
3397 }
3398 else
3399 {
3400 /* Only match unconditional instuctions against unconditional
3401 patterns. */
3402 if ((given & 0xf0000000) == 0xf0000000)
3403 {
3404 mask |= 0xf0000000;
3405 cond = COND_UNCOND;
3406 }
3407 else
3408 {
3409 cond = (given >> 28) & 0xf;
3410 if (cond == 0xe)
3411 cond = COND_UNCOND;
3412 }
3413 }
3414
3415 if ((given & mask) != value)
3416 continue;
3417
3418 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
3419 continue;
3420
3421 if (insn->value == 0xfe000010 /* mcr2 */
3422 || insn->value == 0xfe100010 /* mrc2 */
3423 || insn->value == 0xfc100000 /* ldc2 */
3424 || insn->value == 0xfc000000) /* stc2 */
3425 {
3426 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3427 is_unpredictable = TRUE;
3428 }
3429 else if (insn->value == 0x0e000000 /* cdp */
3430 || insn->value == 0xfe000000 /* cdp2 */
3431 || insn->value == 0x0e000010 /* mcr */
3432 || insn->value == 0x0e100010 /* mrc */
3433 || insn->value == 0x0c100000 /* ldc */
3434 || insn->value == 0x0c000000) /* stc */
3435 {
3436 /* Floating-point instructions. */
3437 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3438 continue;
3439 }
3440
3441 for (c = insn->assembler; *c; c++)
3442 {
3443 if (*c == '%')
3444 {
3445 switch (*++c)
3446 {
3447 case '%':
3448 func (stream, "%%");
3449 break;
3450
3451 case 'A':
3452 {
3453 int rn = (given >> 16) & 0xf;
3454 bfd_vma offset = given & 0xff;
3455
3456 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3457
3458 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3459 {
3460 /* Not unindexed. The offset is scaled. */
3461 if (cp_num == 9)
3462 /* vldr.16/vstr.16 will shift the address
3463 left by 1 bit only. */
3464 offset = offset * 2;
3465 else
3466 offset = offset * 4;
3467
3468 if (NEGATIVE_BIT_SET)
3469 offset = - offset;
3470 if (rn != 15)
3471 value_in_comment = offset;
3472 }
3473
3474 if (PRE_BIT_SET)
3475 {
3476 if (offset)
3477 func (stream, ", #%d]%s",
3478 (int) offset,
3479 WRITEBACK_BIT_SET ? "!" : "");
3480 else if (NEGATIVE_BIT_SET)
3481 func (stream, ", #-0]");
3482 else
3483 func (stream, "]");
3484 }
3485 else
3486 {
3487 func (stream, "]");
3488
3489 if (WRITEBACK_BIT_SET)
3490 {
3491 if (offset)
3492 func (stream, ", #%d", (int) offset);
3493 else if (NEGATIVE_BIT_SET)
3494 func (stream, ", #-0");
3495 }
3496 else
3497 {
3498 func (stream, ", {%s%d}",
3499 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
3500 (int) offset);
3501 value_in_comment = offset;
3502 }
3503 }
3504 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3505 {
3506 func (stream, "\t; ");
3507 /* For unaligned PCs, apply off-by-alignment
3508 correction. */
3509 info->print_address_func (offset + pc
3510 + info->bytes_per_chunk * 2
3511 - (pc & 3),
3512 info);
3513 }
3514 }
3515 break;
3516
3517 case 'B':
3518 {
3519 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3520 int offset = (given >> 1) & 0x3f;
3521
3522 if (offset == 1)
3523 func (stream, "{d%d}", regno);
3524 else if (regno + offset > 32)
3525 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3526 else
3527 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3528 }
3529 break;
3530
3531 case 'u':
3532 if (cond != COND_UNCOND)
3533 is_unpredictable = TRUE;
3534
3535 /* Fall through. */
3536 case 'c':
3537 if (cond != COND_UNCOND && cp_num == 9)
3538 is_unpredictable = TRUE;
3539
3540 func (stream, "%s", arm_conditional[cond]);
3541 break;
3542
3543 case 'I':
3544 /* Print a Cirrus/DSP shift immediate. */
3545 /* Immediates are 7bit signed ints with bits 0..3 in
3546 bits 0..3 of opcode and bits 4..6 in bits 5..7
3547 of opcode. */
3548 {
3549 int imm;
3550
3551 imm = (given & 0xf) | ((given & 0xe0) >> 1);
3552
3553 /* Is ``imm'' a negative number? */
3554 if (imm & 0x40)
3555 imm -= 0x80;
3556
3557 func (stream, "%d", imm);
3558 }
3559
3560 break;
3561
3562 case 'F':
3563 switch (given & 0x00408000)
3564 {
3565 case 0:
3566 func (stream, "4");
3567 break;
3568 case 0x8000:
3569 func (stream, "1");
3570 break;
3571 case 0x00400000:
3572 func (stream, "2");
3573 break;
3574 default:
3575 func (stream, "3");
3576 }
3577 break;
3578
3579 case 'P':
3580 switch (given & 0x00080080)
3581 {
3582 case 0:
3583 func (stream, "s");
3584 break;
3585 case 0x80:
3586 func (stream, "d");
3587 break;
3588 case 0x00080000:
3589 func (stream, "e");
3590 break;
3591 default:
3592 func (stream, _("<illegal precision>"));
3593 break;
3594 }
3595 break;
3596
3597 case 'Q':
3598 switch (given & 0x00408000)
3599 {
3600 case 0:
3601 func (stream, "s");
3602 break;
3603 case 0x8000:
3604 func (stream, "d");
3605 break;
3606 case 0x00400000:
3607 func (stream, "e");
3608 break;
3609 default:
3610 func (stream, "p");
3611 break;
3612 }
3613 break;
3614
3615 case 'R':
3616 switch (given & 0x60)
3617 {
3618 case 0:
3619 break;
3620 case 0x20:
3621 func (stream, "p");
3622 break;
3623 case 0x40:
3624 func (stream, "m");
3625 break;
3626 default:
3627 func (stream, "z");
3628 break;
3629 }
3630 break;
3631
3632 case '0': case '1': case '2': case '3': case '4':
3633 case '5': case '6': case '7': case '8': case '9':
3634 {
3635 int width;
3636
3637 c = arm_decode_bitfield (c, given, &value, &width);
3638
3639 switch (*c)
3640 {
3641 case 'R':
3642 if (value == 15)
3643 is_unpredictable = TRUE;
3644 /* Fall through. */
3645 case 'r':
3646 if (c[1] == 'u')
3647 {
3648 /* Eat the 'u' character. */
3649 ++ c;
3650
3651 if (u_reg == value)
3652 is_unpredictable = TRUE;
3653 u_reg = value;
3654 }
3655 func (stream, "%s", arm_regnames[value]);
3656 break;
3657 case 'D':
3658 func (stream, "d%ld", value);
3659 break;
3660 case 'Q':
3661 if (value & 1)
3662 func (stream, "<illegal reg q%ld.5>", value >> 1);
3663 else
3664 func (stream, "q%ld", value >> 1);
3665 break;
3666 case 'd':
3667 func (stream, "%ld", value);
3668 value_in_comment = value;
3669 break;
3670 case 'E':
3671 {
3672 /* Converts immediate 8 bit back to float value. */
3673 unsigned floatVal = (value & 0x80) << 24
3674 | (value & 0x3F) << 19
3675 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3676
3677 /* Quarter float have a maximum value of 31.0.
3678 Get floating point value multiplied by 1e7.
3679 The maximum value stays in limit of a 32-bit int. */
3680 unsigned decVal =
3681 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3682 (16 + (value & 0xF));
3683
3684 if (!(decVal % 1000000))
3685 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3686 floatVal, value & 0x80 ? '-' : ' ',
3687 decVal / 10000000,
3688 decVal % 10000000 / 1000000);
3689 else if (!(decVal % 10000))
3690 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3691 floatVal, value & 0x80 ? '-' : ' ',
3692 decVal / 10000000,
3693 decVal % 10000000 / 10000);
3694 else
3695 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3696 floatVal, value & 0x80 ? '-' : ' ',
3697 decVal / 10000000, decVal % 10000000);
3698 break;
3699 }
3700 case 'k':
3701 {
3702 int from = (given & (1 << 7)) ? 32 : 16;
3703 func (stream, "%ld", from - value);
3704 }
3705 break;
3706
3707 case 'f':
3708 if (value > 7)
3709 func (stream, "#%s", arm_fp_const[value & 7]);
3710 else
3711 func (stream, "f%ld", value);
3712 break;
3713
3714 case 'w':
3715 if (width == 2)
3716 func (stream, "%s", iwmmxt_wwnames[value]);
3717 else
3718 func (stream, "%s", iwmmxt_wwssnames[value]);
3719 break;
3720
3721 case 'g':
3722 func (stream, "%s", iwmmxt_regnames[value]);
3723 break;
3724 case 'G':
3725 func (stream, "%s", iwmmxt_cregnames[value]);
3726 break;
3727
3728 case 'x':
3729 func (stream, "0x%lx", (value & 0xffffffffUL));
3730 break;
3731
3732 case 'c':
3733 switch (value)
3734 {
3735 case 0:
3736 func (stream, "eq");
3737 break;
3738
3739 case 1:
3740 func (stream, "vs");
3741 break;
3742
3743 case 2:
3744 func (stream, "ge");
3745 break;
3746
3747 case 3:
3748 func (stream, "gt");
3749 break;
3750
3751 default:
3752 func (stream, "??");
3753 break;
3754 }
3755 break;
3756
3757 case '`':
3758 c++;
3759 if (value == 0)
3760 func (stream, "%c", *c);
3761 break;
3762 case '\'':
3763 c++;
3764 if (value == ((1ul << width) - 1))
3765 func (stream, "%c", *c);
3766 break;
3767 case '?':
3768 func (stream, "%c", c[(1 << width) - (int) value]);
3769 c += 1 << width;
3770 break;
3771 default:
3772 abort ();
3773 }
3774 break;
3775
3776 case 'y':
3777 case 'z':
3778 {
3779 int single = *c++ == 'y';
3780 int regno;
3781
3782 switch (*c)
3783 {
3784 case '4': /* Sm pair */
3785 case '0': /* Sm, Dm */
3786 regno = given & 0x0000000f;
3787 if (single)
3788 {
3789 regno <<= 1;
3790 regno += (given >> 5) & 1;
3791 }
3792 else
3793 regno += ((given >> 5) & 1) << 4;
3794 break;
3795
3796 case '1': /* Sd, Dd */
3797 regno = (given >> 12) & 0x0000000f;
3798 if (single)
3799 {
3800 regno <<= 1;
3801 regno += (given >> 22) & 1;
3802 }
3803 else
3804 regno += ((given >> 22) & 1) << 4;
3805 break;
3806
3807 case '2': /* Sn, Dn */
3808 regno = (given >> 16) & 0x0000000f;
3809 if (single)
3810 {
3811 regno <<= 1;
3812 regno += (given >> 7) & 1;
3813 }
3814 else
3815 regno += ((given >> 7) & 1) << 4;
3816 break;
3817
3818 case '3': /* List */
3819 func (stream, "{");
3820 regno = (given >> 12) & 0x0000000f;
3821 if (single)
3822 {
3823 regno <<= 1;
3824 regno += (given >> 22) & 1;
3825 }
3826 else
3827 regno += ((given >> 22) & 1) << 4;
3828 break;
3829
3830 default:
3831 abort ();
3832 }
3833
3834 func (stream, "%c%d", single ? 's' : 'd', regno);
3835
3836 if (*c == '3')
3837 {
3838 int count = given & 0xff;
3839
3840 if (single == 0)
3841 count >>= 1;
3842
3843 if (--count)
3844 {
3845 func (stream, "-%c%d",
3846 single ? 's' : 'd',
3847 regno + count);
3848 }
3849
3850 func (stream, "}");
3851 }
3852 else if (*c == '4')
3853 func (stream, ", %c%d", single ? 's' : 'd',
3854 regno + 1);
3855 }
3856 break;
3857
3858 case 'L':
3859 switch (given & 0x00400100)
3860 {
3861 case 0x00000000: func (stream, "b"); break;
3862 case 0x00400000: func (stream, "h"); break;
3863 case 0x00000100: func (stream, "w"); break;
3864 case 0x00400100: func (stream, "d"); break;
3865 default:
3866 break;
3867 }
3868 break;
3869
3870 case 'Z':
3871 {
3872 /* given (20, 23) | given (0, 3) */
3873 value = ((given >> 16) & 0xf0) | (given & 0xf);
3874 func (stream, "%d", (int) value);
3875 }
3876 break;
3877
3878 case 'l':
3879 /* This is like the 'A' operator, except that if
3880 the width field "M" is zero, then the offset is
3881 *not* multiplied by four. */
3882 {
3883 int offset = given & 0xff;
3884 int multiplier = (given & 0x00000100) ? 4 : 1;
3885
3886 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3887
3888 if (multiplier > 1)
3889 {
3890 value_in_comment = offset * multiplier;
3891 if (NEGATIVE_BIT_SET)
3892 value_in_comment = - value_in_comment;
3893 }
3894
3895 if (offset)
3896 {
3897 if (PRE_BIT_SET)
3898 func (stream, ", #%s%d]%s",
3899 NEGATIVE_BIT_SET ? "-" : "",
3900 offset * multiplier,
3901 WRITEBACK_BIT_SET ? "!" : "");
3902 else
3903 func (stream, "], #%s%d",
3904 NEGATIVE_BIT_SET ? "-" : "",
3905 offset * multiplier);
3906 }
3907 else
3908 func (stream, "]");
3909 }
3910 break;
3911
3912 case 'r':
3913 {
3914 int imm4 = (given >> 4) & 0xf;
3915 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3916 int ubit = ! NEGATIVE_BIT_SET;
3917 const char *rm = arm_regnames [given & 0xf];
3918 const char *rn = arm_regnames [(given >> 16) & 0xf];
3919
3920 switch (puw_bits)
3921 {
3922 case 1:
3923 case 3:
3924 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3925 if (imm4)
3926 func (stream, ", lsl #%d", imm4);
3927 break;
3928
3929 case 4:
3930 case 5:
3931 case 6:
3932 case 7:
3933 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3934 if (imm4 > 0)
3935 func (stream, ", lsl #%d", imm4);
3936 func (stream, "]");
3937 if (puw_bits == 5 || puw_bits == 7)
3938 func (stream, "!");
3939 break;
3940
3941 default:
3942 func (stream, "INVALID");
3943 }
3944 }
3945 break;
3946
3947 case 'i':
3948 {
3949 long imm5;
3950 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3951 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
3952 }
3953 break;
3954
3955 default:
3956 abort ();
3957 }
3958 }
3959 }
3960 else
3961 func (stream, "%c", *c);
3962 }
3963
3964 if (value_in_comment > 32 || value_in_comment < -16)
3965 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
3966
3967 if (is_unpredictable)
3968 func (stream, UNPREDICTABLE_INSTRUCTION);
3969
3970 return TRUE;
3971 }
3972 return FALSE;
3973 }
3974
3975 /* Decodes and prints ARM addressing modes. Returns the offset
3976 used in the address, if any, if it is worthwhile printing the
3977 offset as a hexadecimal value in a comment at the end of the
3978 line of disassembly. */
3979
3980 static signed long
3981 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
3982 {
3983 void *stream = info->stream;
3984 fprintf_ftype func = info->fprintf_func;
3985 bfd_vma offset = 0;
3986
3987 if (((given & 0x000f0000) == 0x000f0000)
3988 && ((given & 0x02000000) == 0))
3989 {
3990 offset = given & 0xfff;
3991
3992 func (stream, "[pc");
3993
3994 if (PRE_BIT_SET)
3995 {
3996 /* Pre-indexed. Elide offset of positive zero when
3997 non-writeback. */
3998 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
3999 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4000
4001 if (NEGATIVE_BIT_SET)
4002 offset = -offset;
4003
4004 offset += pc + 8;
4005
4006 /* Cope with the possibility of write-back
4007 being used. Probably a very dangerous thing
4008 for the programmer to do, but who are we to
4009 argue ? */
4010 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
4011 }
4012 else /* Post indexed. */
4013 {
4014 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4015
4016 /* Ie ignore the offset. */
4017 offset = pc + 8;
4018 }
4019
4020 func (stream, "\t; ");
4021 info->print_address_func (offset, info);
4022 offset = 0;
4023 }
4024 else
4025 {
4026 func (stream, "[%s",
4027 arm_regnames[(given >> 16) & 0xf]);
4028
4029 if (PRE_BIT_SET)
4030 {
4031 if ((given & 0x02000000) == 0)
4032 {
4033 /* Elide offset of positive zero when non-writeback. */
4034 offset = given & 0xfff;
4035 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
4036 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4037 }
4038 else
4039 {
4040 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
4041 arm_decode_shift (given, func, stream, TRUE);
4042 }
4043
4044 func (stream, "]%s",
4045 WRITEBACK_BIT_SET ? "!" : "");
4046 }
4047 else
4048 {
4049 if ((given & 0x02000000) == 0)
4050 {
4051 /* Always show offset. */
4052 offset = given & 0xfff;
4053 func (stream, "], #%s%d",
4054 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4055 }
4056 else
4057 {
4058 func (stream, "], %s",
4059 NEGATIVE_BIT_SET ? "-" : "");
4060 arm_decode_shift (given, func, stream, TRUE);
4061 }
4062 }
4063 if (NEGATIVE_BIT_SET)
4064 offset = -offset;
4065 }
4066
4067 return (signed long) offset;
4068 }
4069
4070 /* Print one neon instruction on INFO->STREAM.
4071 Return TRUE if the instuction matched, FALSE if this is not a
4072 recognised neon instruction. */
4073
4074 static bfd_boolean
4075 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4076 {
4077 const struct opcode32 *insn;
4078 void *stream = info->stream;
4079 fprintf_ftype func = info->fprintf_func;
4080
4081 if (thumb)
4082 {
4083 if ((given & 0xef000000) == 0xef000000)
4084 {
4085 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
4086 unsigned long bit28 = given & (1 << 28);
4087
4088 given &= 0x00ffffff;
4089 if (bit28)
4090 given |= 0xf3000000;
4091 else
4092 given |= 0xf2000000;
4093 }
4094 else if ((given & 0xff000000) == 0xf9000000)
4095 given ^= 0xf9000000 ^ 0xf4000000;
4096 else
4097 return FALSE;
4098 }
4099
4100 for (insn = neon_opcodes; insn->assembler; insn++)
4101 {
4102 if ((given & insn->mask) == insn->value)
4103 {
4104 signed long value_in_comment = 0;
4105 bfd_boolean is_unpredictable = FALSE;
4106 const char *c;
4107
4108 for (c = insn->assembler; *c; c++)
4109 {
4110 if (*c == '%')
4111 {
4112 switch (*++c)
4113 {
4114 case '%':
4115 func (stream, "%%");
4116 break;
4117
4118 case 'u':
4119 if (thumb && ifthen_state)
4120 is_unpredictable = TRUE;
4121
4122 /* Fall through. */
4123 case 'c':
4124 if (thumb && ifthen_state)
4125 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4126 break;
4127
4128 case 'A':
4129 {
4130 static const unsigned char enc[16] =
4131 {
4132 0x4, 0x14, /* st4 0,1 */
4133 0x4, /* st1 2 */
4134 0x4, /* st2 3 */
4135 0x3, /* st3 4 */
4136 0x13, /* st3 5 */
4137 0x3, /* st1 6 */
4138 0x1, /* st1 7 */
4139 0x2, /* st2 8 */
4140 0x12, /* st2 9 */
4141 0x2, /* st1 10 */
4142 0, 0, 0, 0, 0
4143 };
4144 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4145 int rn = ((given >> 16) & 0xf);
4146 int rm = ((given >> 0) & 0xf);
4147 int align = ((given >> 4) & 0x3);
4148 int type = ((given >> 8) & 0xf);
4149 int n = enc[type] & 0xf;
4150 int stride = (enc[type] >> 4) + 1;
4151 int ix;
4152
4153 func (stream, "{");
4154 if (stride > 1)
4155 for (ix = 0; ix != n; ix++)
4156 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4157 else if (n == 1)
4158 func (stream, "d%d", rd);
4159 else
4160 func (stream, "d%d-d%d", rd, rd + n - 1);
4161 func (stream, "}, [%s", arm_regnames[rn]);
4162 if (align)
4163 func (stream, " :%d", 32 << align);
4164 func (stream, "]");
4165 if (rm == 0xd)
4166 func (stream, "!");
4167 else if (rm != 0xf)
4168 func (stream, ", %s", arm_regnames[rm]);
4169 }
4170 break;
4171
4172 case 'B':
4173 {
4174 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4175 int rn = ((given >> 16) & 0xf);
4176 int rm = ((given >> 0) & 0xf);
4177 int idx_align = ((given >> 4) & 0xf);
4178 int align = 0;
4179 int size = ((given >> 10) & 0x3);
4180 int idx = idx_align >> (size + 1);
4181 int length = ((given >> 8) & 3) + 1;
4182 int stride = 1;
4183 int i;
4184
4185 if (length > 1 && size > 0)
4186 stride = (idx_align & (1 << size)) ? 2 : 1;
4187
4188 switch (length)
4189 {
4190 case 1:
4191 {
4192 int amask = (1 << size) - 1;
4193 if ((idx_align & (1 << size)) != 0)
4194 return FALSE;
4195 if (size > 0)
4196 {
4197 if ((idx_align & amask) == amask)
4198 align = 8 << size;
4199 else if ((idx_align & amask) != 0)
4200 return FALSE;
4201 }
4202 }
4203 break;
4204
4205 case 2:
4206 if (size == 2 && (idx_align & 2) != 0)
4207 return FALSE;
4208 align = (idx_align & 1) ? 16 << size : 0;
4209 break;
4210
4211 case 3:
4212 if ((size == 2 && (idx_align & 3) != 0)
4213 || (idx_align & 1) != 0)
4214 return FALSE;
4215 break;
4216
4217 case 4:
4218 if (size == 2)
4219 {
4220 if ((idx_align & 3) == 3)
4221 return FALSE;
4222 align = (idx_align & 3) * 64;
4223 }
4224 else
4225 align = (idx_align & 1) ? 32 << size : 0;
4226 break;
4227
4228 default:
4229 abort ();
4230 }
4231
4232 func (stream, "{");
4233 for (i = 0; i < length; i++)
4234 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4235 rd + i * stride, idx);
4236 func (stream, "}, [%s", arm_regnames[rn]);
4237 if (align)
4238 func (stream, " :%d", align);
4239 func (stream, "]");
4240 if (rm == 0xd)
4241 func (stream, "!");
4242 else if (rm != 0xf)
4243 func (stream, ", %s", arm_regnames[rm]);
4244 }
4245 break;
4246
4247 case 'C':
4248 {
4249 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4250 int rn = ((given >> 16) & 0xf);
4251 int rm = ((given >> 0) & 0xf);
4252 int align = ((given >> 4) & 0x1);
4253 int size = ((given >> 6) & 0x3);
4254 int type = ((given >> 8) & 0x3);
4255 int n = type + 1;
4256 int stride = ((given >> 5) & 0x1);
4257 int ix;
4258
4259 if (stride && (n == 1))
4260 n++;
4261 else
4262 stride++;
4263
4264 func (stream, "{");
4265 if (stride > 1)
4266 for (ix = 0; ix != n; ix++)
4267 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4268 else if (n == 1)
4269 func (stream, "d%d[]", rd);
4270 else
4271 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4272 func (stream, "}, [%s", arm_regnames[rn]);
4273 if (align)
4274 {
4275 align = (8 * (type + 1)) << size;
4276 if (type == 3)
4277 align = (size > 1) ? align >> 1 : align;
4278 if (type == 2 || (type == 0 && !size))
4279 func (stream, " :<bad align %d>", align);
4280 else
4281 func (stream, " :%d", align);
4282 }
4283 func (stream, "]");
4284 if (rm == 0xd)
4285 func (stream, "!");
4286 else if (rm != 0xf)
4287 func (stream, ", %s", arm_regnames[rm]);
4288 }
4289 break;
4290
4291 case 'D':
4292 {
4293 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4294 int size = (given >> 20) & 3;
4295 int reg = raw_reg & ((4 << size) - 1);
4296 int ix = raw_reg >> size >> 2;
4297
4298 func (stream, "d%d[%d]", reg, ix);
4299 }
4300 break;
4301
4302 case 'E':
4303 /* Neon encoded constant for mov, mvn, vorr, vbic. */
4304 {
4305 int bits = 0;
4306 int cmode = (given >> 8) & 0xf;
4307 int op = (given >> 5) & 0x1;
4308 unsigned long value = 0, hival = 0;
4309 unsigned shift;
4310 int size = 0;
4311 int isfloat = 0;
4312
4313 bits |= ((given >> 24) & 1) << 7;
4314 bits |= ((given >> 16) & 7) << 4;
4315 bits |= ((given >> 0) & 15) << 0;
4316
4317 if (cmode < 8)
4318 {
4319 shift = (cmode >> 1) & 3;
4320 value = (unsigned long) bits << (8 * shift);
4321 size = 32;
4322 }
4323 else if (cmode < 12)
4324 {
4325 shift = (cmode >> 1) & 1;
4326 value = (unsigned long) bits << (8 * shift);
4327 size = 16;
4328 }
4329 else if (cmode < 14)
4330 {
4331 shift = (cmode & 1) + 1;
4332 value = (unsigned long) bits << (8 * shift);
4333 value |= (1ul << (8 * shift)) - 1;
4334 size = 32;
4335 }
4336 else if (cmode == 14)
4337 {
4338 if (op)
4339 {
4340 /* Bit replication into bytes. */
4341 int ix;
4342 unsigned long mask;
4343
4344 value = 0;
4345 hival = 0;
4346 for (ix = 7; ix >= 0; ix--)
4347 {
4348 mask = ((bits >> ix) & 1) ? 0xff : 0;
4349 if (ix <= 3)
4350 value = (value << 8) | mask;
4351 else
4352 hival = (hival << 8) | mask;
4353 }
4354 size = 64;
4355 }
4356 else
4357 {
4358 /* Byte replication. */
4359 value = (unsigned long) bits;
4360 size = 8;
4361 }
4362 }
4363 else if (!op)
4364 {
4365 /* Floating point encoding. */
4366 int tmp;
4367
4368 value = (unsigned long) (bits & 0x7f) << 19;
4369 value |= (unsigned long) (bits & 0x80) << 24;
4370 tmp = bits & 0x40 ? 0x3c : 0x40;
4371 value |= (unsigned long) tmp << 24;
4372 size = 32;
4373 isfloat = 1;
4374 }
4375 else
4376 {
4377 func (stream, "<illegal constant %.8x:%x:%x>",
4378 bits, cmode, op);
4379 size = 32;
4380 break;
4381 }
4382 switch (size)
4383 {
4384 case 8:
4385 func (stream, "#%ld\t; 0x%.2lx", value, value);
4386 break;
4387
4388 case 16:
4389 func (stream, "#%ld\t; 0x%.4lx", value, value);
4390 break;
4391
4392 case 32:
4393 if (isfloat)
4394 {
4395 unsigned char valbytes[4];
4396 double fvalue;
4397
4398 /* Do this a byte at a time so we don't have to
4399 worry about the host's endianness. */
4400 valbytes[0] = value & 0xff;
4401 valbytes[1] = (value >> 8) & 0xff;
4402 valbytes[2] = (value >> 16) & 0xff;
4403 valbytes[3] = (value >> 24) & 0xff;
4404
4405 floatformat_to_double
4406 (& floatformat_ieee_single_little, valbytes,
4407 & fvalue);
4408
4409 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4410 value);
4411 }
4412 else
4413 func (stream, "#%ld\t; 0x%.8lx",
4414 (long) (((value & 0x80000000L) != 0)
4415 ? value | ~0xffffffffL : value),
4416 value);
4417 break;
4418
4419 case 64:
4420 func (stream, "#0x%.8lx%.8lx", hival, value);
4421 break;
4422
4423 default:
4424 abort ();
4425 }
4426 }
4427 break;
4428
4429 case 'F':
4430 {
4431 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4432 int num = (given >> 8) & 0x3;
4433
4434 if (!num)
4435 func (stream, "{d%d}", regno);
4436 else if (num + regno >= 32)
4437 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4438 else
4439 func (stream, "{d%d-d%d}", regno, regno + num);
4440 }
4441 break;
4442
4443
4444 case '0': case '1': case '2': case '3': case '4':
4445 case '5': case '6': case '7': case '8': case '9':
4446 {
4447 int width;
4448 unsigned long value;
4449
4450 c = arm_decode_bitfield (c, given, &value, &width);
4451
4452 switch (*c)
4453 {
4454 case 'r':
4455 func (stream, "%s", arm_regnames[value]);
4456 break;
4457 case 'd':
4458 func (stream, "%ld", value);
4459 value_in_comment = value;
4460 break;
4461 case 'e':
4462 func (stream, "%ld", (1ul << width) - value);
4463 break;
4464
4465 case 'S':
4466 case 'T':
4467 case 'U':
4468 /* Various width encodings. */
4469 {
4470 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4471 int limit;
4472 unsigned low, high;
4473
4474 c++;
4475 if (*c >= '0' && *c <= '9')
4476 limit = *c - '0';
4477 else if (*c >= 'a' && *c <= 'f')
4478 limit = *c - 'a' + 10;
4479 else
4480 abort ();
4481 low = limit >> 2;
4482 high = limit & 3;
4483
4484 if (value < low || value > high)
4485 func (stream, "<illegal width %d>", base << value);
4486 else
4487 func (stream, "%d", base << value);
4488 }
4489 break;
4490 case 'R':
4491 if (given & (1 << 6))
4492 goto Q;
4493 /* FALLTHROUGH */
4494 case 'D':
4495 func (stream, "d%ld", value);
4496 break;
4497 case 'Q':
4498 Q:
4499 if (value & 1)
4500 func (stream, "<illegal reg q%ld.5>", value >> 1);
4501 else
4502 func (stream, "q%ld", value >> 1);
4503 break;
4504
4505 case '`':
4506 c++;
4507 if (value == 0)
4508 func (stream, "%c", *c);
4509 break;
4510 case '\'':
4511 c++;
4512 if (value == ((1ul << width) - 1))
4513 func (stream, "%c", *c);
4514 break;
4515 case '?':
4516 func (stream, "%c", c[(1 << width) - (int) value]);
4517 c += 1 << width;
4518 break;
4519 default:
4520 abort ();
4521 }
4522 break;
4523
4524 default:
4525 abort ();
4526 }
4527 }
4528 }
4529 else
4530 func (stream, "%c", *c);
4531 }
4532
4533 if (value_in_comment > 32 || value_in_comment < -16)
4534 func (stream, "\t; 0x%lx", value_in_comment);
4535
4536 if (is_unpredictable)
4537 func (stream, UNPREDICTABLE_INSTRUCTION);
4538
4539 return TRUE;
4540 }
4541 }
4542 return FALSE;
4543 }
4544
4545 /* Return the name of a v7A special register. */
4546
4547 static const char *
4548 banked_regname (unsigned reg)
4549 {
4550 switch (reg)
4551 {
4552 case 15: return "CPSR";
4553 case 32: return "R8_usr";
4554 case 33: return "R9_usr";
4555 case 34: return "R10_usr";
4556 case 35: return "R11_usr";
4557 case 36: return "R12_usr";
4558 case 37: return "SP_usr";
4559 case 38: return "LR_usr";
4560 case 40: return "R8_fiq";
4561 case 41: return "R9_fiq";
4562 case 42: return "R10_fiq";
4563 case 43: return "R11_fiq";
4564 case 44: return "R12_fiq";
4565 case 45: return "SP_fiq";
4566 case 46: return "LR_fiq";
4567 case 48: return "LR_irq";
4568 case 49: return "SP_irq";
4569 case 50: return "LR_svc";
4570 case 51: return "SP_svc";
4571 case 52: return "LR_abt";
4572 case 53: return "SP_abt";
4573 case 54: return "LR_und";
4574 case 55: return "SP_und";
4575 case 60: return "LR_mon";
4576 case 61: return "SP_mon";
4577 case 62: return "ELR_hyp";
4578 case 63: return "SP_hyp";
4579 case 79: return "SPSR";
4580 case 110: return "SPSR_fiq";
4581 case 112: return "SPSR_irq";
4582 case 114: return "SPSR_svc";
4583 case 116: return "SPSR_abt";
4584 case 118: return "SPSR_und";
4585 case 124: return "SPSR_mon";
4586 case 126: return "SPSR_hyp";
4587 default: return NULL;
4588 }
4589 }
4590
4591 /* Return the name of the DMB/DSB option. */
4592 static const char *
4593 data_barrier_option (unsigned option)
4594 {
4595 switch (option & 0xf)
4596 {
4597 case 0xf: return "sy";
4598 case 0xe: return "st";
4599 case 0xd: return "ld";
4600 case 0xb: return "ish";
4601 case 0xa: return "ishst";
4602 case 0x9: return "ishld";
4603 case 0x7: return "un";
4604 case 0x6: return "unst";
4605 case 0x5: return "nshld";
4606 case 0x3: return "osh";
4607 case 0x2: return "oshst";
4608 case 0x1: return "oshld";
4609 default: return NULL;
4610 }
4611 }
4612
4613 /* Print one ARM instruction from PC on INFO->STREAM. */
4614
4615 static void
4616 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
4617 {
4618 const struct opcode32 *insn;
4619 void *stream = info->stream;
4620 fprintf_ftype func = info->fprintf_func;
4621 struct arm_private_data *private_data = info->private_data;
4622
4623 if (print_insn_coprocessor (pc, info, given, FALSE))
4624 return;
4625
4626 if (print_insn_neon (info, given, FALSE))
4627 return;
4628
4629 for (insn = arm_opcodes; insn->assembler; insn++)
4630 {
4631 if ((given & insn->mask) != insn->value)
4632 continue;
4633
4634 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
4635 continue;
4636
4637 /* Special case: an instruction with all bits set in the condition field
4638 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4639 or by the catchall at the end of the table. */
4640 if ((given & 0xF0000000) != 0xF0000000
4641 || (insn->mask & 0xF0000000) == 0xF0000000
4642 || (insn->mask == 0 && insn->value == 0))
4643 {
4644 unsigned long u_reg = 16;
4645 unsigned long U_reg = 16;
4646 bfd_boolean is_unpredictable = FALSE;
4647 signed long value_in_comment = 0;
4648 const char *c;
4649
4650 for (c = insn->assembler; *c; c++)
4651 {
4652 if (*c == '%')
4653 {
4654 bfd_boolean allow_unpredictable = FALSE;
4655
4656 switch (*++c)
4657 {
4658 case '%':
4659 func (stream, "%%");
4660 break;
4661
4662 case 'a':
4663 value_in_comment = print_arm_address (pc, info, given);
4664 break;
4665
4666 case 'P':
4667 /* Set P address bit and use normal address
4668 printing routine. */
4669 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
4670 break;
4671
4672 case 'S':
4673 allow_unpredictable = TRUE;
4674 case 's':
4675 if ((given & 0x004f0000) == 0x004f0000)
4676 {
4677 /* PC relative with immediate offset. */
4678 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
4679
4680 if (PRE_BIT_SET)
4681 {
4682 /* Elide positive zero offset. */
4683 if (offset || NEGATIVE_BIT_SET)
4684 func (stream, "[pc, #%s%d]\t; ",
4685 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4686 else
4687 func (stream, "[pc]\t; ");
4688 if (NEGATIVE_BIT_SET)
4689 offset = -offset;
4690 info->print_address_func (offset + pc + 8, info);
4691 }
4692 else
4693 {
4694 /* Always show the offset. */
4695 func (stream, "[pc], #%s%d",
4696 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4697 if (! allow_unpredictable)
4698 is_unpredictable = TRUE;
4699 }
4700 }
4701 else
4702 {
4703 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4704
4705 func (stream, "[%s",
4706 arm_regnames[(given >> 16) & 0xf]);
4707
4708 if (PRE_BIT_SET)
4709 {
4710 if (IMMEDIATE_BIT_SET)
4711 {
4712 /* Elide offset for non-writeback
4713 positive zero. */
4714 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4715 || offset)
4716 func (stream, ", #%s%d",
4717 NEGATIVE_BIT_SET ? "-" : "", offset);
4718
4719 if (NEGATIVE_BIT_SET)
4720 offset = -offset;
4721
4722 value_in_comment = offset;
4723 }
4724 else
4725 {
4726 /* Register Offset or Register Pre-Indexed. */
4727 func (stream, ", %s%s",
4728 NEGATIVE_BIT_SET ? "-" : "",
4729 arm_regnames[given & 0xf]);
4730
4731 /* Writing back to the register that is the source/
4732 destination of the load/store is unpredictable. */
4733 if (! allow_unpredictable
4734 && WRITEBACK_BIT_SET
4735 && ((given & 0xf) == ((given >> 12) & 0xf)))
4736 is_unpredictable = TRUE;
4737 }
4738
4739 func (stream, "]%s",
4740 WRITEBACK_BIT_SET ? "!" : "");
4741 }
4742 else
4743 {
4744 if (IMMEDIATE_BIT_SET)
4745 {
4746 /* Immediate Post-indexed. */
4747 /* PR 10924: Offset must be printed, even if it is zero. */
4748 func (stream, "], #%s%d",
4749 NEGATIVE_BIT_SET ? "-" : "", offset);
4750 if (NEGATIVE_BIT_SET)
4751 offset = -offset;
4752 value_in_comment = offset;
4753 }
4754 else
4755 {
4756 /* Register Post-indexed. */
4757 func (stream, "], %s%s",
4758 NEGATIVE_BIT_SET ? "-" : "",
4759 arm_regnames[given & 0xf]);
4760
4761 /* Writing back to the register that is the source/
4762 destination of the load/store is unpredictable. */
4763 if (! allow_unpredictable
4764 && (given & 0xf) == ((given >> 12) & 0xf))
4765 is_unpredictable = TRUE;
4766 }
4767
4768 if (! allow_unpredictable)
4769 {
4770 /* Writeback is automatically implied by post- addressing.
4771 Setting the W bit is unnecessary and ARM specify it as
4772 being unpredictable. */
4773 if (WRITEBACK_BIT_SET
4774 /* Specifying the PC register as the post-indexed
4775 registers is also unpredictable. */
4776 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4777 is_unpredictable = TRUE;
4778 }
4779 }
4780 }
4781 break;
4782
4783 case 'b':
4784 {
4785 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
4786 info->print_address_func (disp * 4 + pc + 8, info);
4787 }
4788 break;
4789
4790 case 'c':
4791 if (((given >> 28) & 0xf) != 0xe)
4792 func (stream, "%s",
4793 arm_conditional [(given >> 28) & 0xf]);
4794 break;
4795
4796 case 'm':
4797 {
4798 int started = 0;
4799 int reg;
4800
4801 func (stream, "{");
4802 for (reg = 0; reg < 16; reg++)
4803 if ((given & (1 << reg)) != 0)
4804 {
4805 if (started)
4806 func (stream, ", ");
4807 started = 1;
4808 func (stream, "%s", arm_regnames[reg]);
4809 }
4810 func (stream, "}");
4811 if (! started)
4812 is_unpredictable = TRUE;
4813 }
4814 break;
4815
4816 case 'q':
4817 arm_decode_shift (given, func, stream, FALSE);
4818 break;
4819
4820 case 'o':
4821 if ((given & 0x02000000) != 0)
4822 {
4823 unsigned int rotate = (given & 0xf00) >> 7;
4824 unsigned int immed = (given & 0xff);
4825 unsigned int a, i;
4826
4827 a = (((immed << (32 - rotate))
4828 | (immed >> rotate)) & 0xffffffff);
4829 /* If there is another encoding with smaller rotate,
4830 the rotate should be specified directly. */
4831 for (i = 0; i < 32; i += 2)
4832 if ((a << i | a >> (32 - i)) <= 0xff)
4833 break;
4834
4835 if (i != rotate)
4836 func (stream, "#%d, %d", immed, rotate);
4837 else
4838 func (stream, "#%d", a);
4839 value_in_comment = a;
4840 }
4841 else
4842 arm_decode_shift (given, func, stream, TRUE);
4843 break;
4844
4845 case 'p':
4846 if ((given & 0x0000f000) == 0x0000f000)
4847 {
4848 arm_feature_set arm_ext_v6 =
4849 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4850
4851 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4852 mechanism for setting PSR flag bits. They are
4853 obsolete in V6 onwards. */
4854 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4855 arm_ext_v6))
4856 func (stream, "p");
4857 else
4858 is_unpredictable = TRUE;
4859 }
4860 break;
4861
4862 case 't':
4863 if ((given & 0x01200000) == 0x00200000)
4864 func (stream, "t");
4865 break;
4866
4867 case 'A':
4868 {
4869 int offset = given & 0xff;
4870
4871 value_in_comment = offset * 4;
4872 if (NEGATIVE_BIT_SET)
4873 value_in_comment = - value_in_comment;
4874
4875 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
4876
4877 if (PRE_BIT_SET)
4878 {
4879 if (offset)
4880 func (stream, ", #%d]%s",
4881 (int) value_in_comment,
4882 WRITEBACK_BIT_SET ? "!" : "");
4883 else
4884 func (stream, "]");
4885 }
4886 else
4887 {
4888 func (stream, "]");
4889
4890 if (WRITEBACK_BIT_SET)
4891 {
4892 if (offset)
4893 func (stream, ", #%d", (int) value_in_comment);
4894 }
4895 else
4896 {
4897 func (stream, ", {%d}", (int) offset);
4898 value_in_comment = offset;
4899 }
4900 }
4901 }
4902 break;
4903
4904 case 'B':
4905 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4906 {
4907 bfd_vma address;
4908 bfd_vma offset = 0;
4909
4910 if (! NEGATIVE_BIT_SET)
4911 /* Is signed, hi bits should be ones. */
4912 offset = (-1) ^ 0x00ffffff;
4913
4914 /* Offset is (SignExtend(offset field)<<2). */
4915 offset += given & 0x00ffffff;
4916 offset <<= 2;
4917 address = offset + pc + 8;
4918
4919 if (given & 0x01000000)
4920 /* H bit allows addressing to 2-byte boundaries. */
4921 address += 2;
4922
4923 info->print_address_func (address, info);
4924 }
4925 break;
4926
4927 case 'C':
4928 if ((given & 0x02000200) == 0x200)
4929 {
4930 const char * name;
4931 unsigned sysm = (given & 0x004f0000) >> 16;
4932
4933 sysm |= (given & 0x300) >> 4;
4934 name = banked_regname (sysm);
4935
4936 if (name != NULL)
4937 func (stream, "%s", name);
4938 else
4939 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4940 }
4941 else
4942 {
4943 func (stream, "%cPSR_",
4944 (given & 0x00400000) ? 'S' : 'C');
4945 if (given & 0x80000)
4946 func (stream, "f");
4947 if (given & 0x40000)
4948 func (stream, "s");
4949 if (given & 0x20000)
4950 func (stream, "x");
4951 if (given & 0x10000)
4952 func (stream, "c");
4953 }
4954 break;
4955
4956 case 'U':
4957 if ((given & 0xf0) == 0x60)
4958 {
4959 switch (given & 0xf)
4960 {
4961 case 0xf: func (stream, "sy"); break;
4962 default:
4963 func (stream, "#%d", (int) given & 0xf);
4964 break;
4965 }
4966 }
4967 else
4968 {
4969 const char * opt = data_barrier_option (given & 0xf);
4970 if (opt != NULL)
4971 func (stream, "%s", opt);
4972 else
4973 func (stream, "#%d", (int) given & 0xf);
4974 }
4975 break;
4976
4977 case '0': case '1': case '2': case '3': case '4':
4978 case '5': case '6': case '7': case '8': case '9':
4979 {
4980 int width;
4981 unsigned long value;
4982
4983 c = arm_decode_bitfield (c, given, &value, &width);
4984
4985 switch (*c)
4986 {
4987 case 'R':
4988 if (value == 15)
4989 is_unpredictable = TRUE;
4990 /* Fall through. */
4991 case 'r':
4992 case 'T':
4993 /* We want register + 1 when decoding T. */
4994 if (*c == 'T')
4995 ++value;
4996
4997 if (c[1] == 'u')
4998 {
4999 /* Eat the 'u' character. */
5000 ++ c;
5001
5002 if (u_reg == value)
5003 is_unpredictable = TRUE;
5004 u_reg = value;
5005 }
5006 if (c[1] == 'U')
5007 {
5008 /* Eat the 'U' character. */
5009 ++ c;
5010
5011 if (U_reg == value)
5012 is_unpredictable = TRUE;
5013 U_reg = value;
5014 }
5015 func (stream, "%s", arm_regnames[value]);
5016 break;
5017 case 'd':
5018 func (stream, "%ld", value);
5019 value_in_comment = value;
5020 break;
5021 case 'b':
5022 func (stream, "%ld", value * 8);
5023 value_in_comment = value * 8;
5024 break;
5025 case 'W':
5026 func (stream, "%ld", value + 1);
5027 value_in_comment = value + 1;
5028 break;
5029 case 'x':
5030 func (stream, "0x%08lx", value);
5031
5032 /* Some SWI instructions have special
5033 meanings. */
5034 if ((given & 0x0fffffff) == 0x0FF00000)
5035 func (stream, "\t; IMB");
5036 else if ((given & 0x0fffffff) == 0x0FF00001)
5037 func (stream, "\t; IMBRange");
5038 break;
5039 case 'X':
5040 func (stream, "%01lx", value & 0xf);
5041 value_in_comment = value;
5042 break;
5043 case '`':
5044 c++;
5045 if (value == 0)
5046 func (stream, "%c", *c);
5047 break;
5048 case '\'':
5049 c++;
5050 if (value == ((1ul << width) - 1))
5051 func (stream, "%c", *c);
5052 break;
5053 case '?':
5054 func (stream, "%c", c[(1 << width) - (int) value]);
5055 c += 1 << width;
5056 break;
5057 default:
5058 abort ();
5059 }
5060 break;
5061
5062 case 'e':
5063 {
5064 int imm;
5065
5066 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5067 func (stream, "%d", imm);
5068 value_in_comment = imm;
5069 }
5070 break;
5071
5072 case 'E':
5073 /* LSB and WIDTH fields of BFI or BFC. The machine-
5074 language instruction encodes LSB and MSB. */
5075 {
5076 long msb = (given & 0x001f0000) >> 16;
5077 long lsb = (given & 0x00000f80) >> 7;
5078 long w = msb - lsb + 1;
5079
5080 if (w > 0)
5081 func (stream, "#%lu, #%lu", lsb, w);
5082 else
5083 func (stream, "(invalid: %lu:%lu)", lsb, msb);
5084 }
5085 break;
5086
5087 case 'R':
5088 /* Get the PSR/banked register name. */
5089 {
5090 const char * name;
5091 unsigned sysm = (given & 0x004f0000) >> 16;
5092
5093 sysm |= (given & 0x300) >> 4;
5094 name = banked_regname (sysm);
5095
5096 if (name != NULL)
5097 func (stream, "%s", name);
5098 else
5099 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5100 }
5101 break;
5102
5103 case 'V':
5104 /* 16-bit unsigned immediate from a MOVT or MOVW
5105 instruction, encoded in bits 0:11 and 15:19. */
5106 {
5107 long hi = (given & 0x000f0000) >> 4;
5108 long lo = (given & 0x00000fff);
5109 long imm16 = hi | lo;
5110
5111 func (stream, "#%lu", imm16);
5112 value_in_comment = imm16;
5113 }
5114 break;
5115
5116 default:
5117 abort ();
5118 }
5119 }
5120 }
5121 else
5122 func (stream, "%c", *c);
5123 }
5124
5125 if (value_in_comment > 32 || value_in_comment < -16)
5126 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
5127
5128 if (is_unpredictable)
5129 func (stream, UNPREDICTABLE_INSTRUCTION);
5130
5131 return;
5132 }
5133 }
5134 abort ();
5135 }
5136
5137 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
5138
5139 static void
5140 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
5141 {
5142 const struct opcode16 *insn;
5143 void *stream = info->stream;
5144 fprintf_ftype func = info->fprintf_func;
5145
5146 for (insn = thumb_opcodes; insn->assembler; insn++)
5147 if ((given & insn->mask) == insn->value)
5148 {
5149 signed long value_in_comment = 0;
5150 const char *c = insn->assembler;
5151
5152 for (; *c; c++)
5153 {
5154 int domaskpc = 0;
5155 int domasklr = 0;
5156
5157 if (*c != '%')
5158 {
5159 func (stream, "%c", *c);
5160 continue;
5161 }
5162
5163 switch (*++c)
5164 {
5165 case '%':
5166 func (stream, "%%");
5167 break;
5168
5169 case 'c':
5170 if (ifthen_state)
5171 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5172 break;
5173
5174 case 'C':
5175 if (ifthen_state)
5176 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5177 else
5178 func (stream, "s");
5179 break;
5180
5181 case 'I':
5182 {
5183 unsigned int tmp;
5184
5185 ifthen_next_state = given & 0xff;
5186 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5187 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5188 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5189 }
5190 break;
5191
5192 case 'x':
5193 if (ifthen_next_state)
5194 func (stream, "\t; unpredictable branch in IT block\n");
5195 break;
5196
5197 case 'X':
5198 if (ifthen_state)
5199 func (stream, "\t; unpredictable <IT:%s>",
5200 arm_conditional[IFTHEN_COND]);
5201 break;
5202
5203 case 'S':
5204 {
5205 long reg;
5206
5207 reg = (given >> 3) & 0x7;
5208 if (given & (1 << 6))
5209 reg += 8;
5210
5211 func (stream, "%s", arm_regnames[reg]);
5212 }
5213 break;
5214
5215 case 'D':
5216 {
5217 long reg;
5218
5219 reg = given & 0x7;
5220 if (given & (1 << 7))
5221 reg += 8;
5222
5223 func (stream, "%s", arm_regnames[reg]);
5224 }
5225 break;
5226
5227 case 'N':
5228 if (given & (1 << 8))
5229 domasklr = 1;
5230 /* Fall through. */
5231 case 'O':
5232 if (*c == 'O' && (given & (1 << 8)))
5233 domaskpc = 1;
5234 /* Fall through. */
5235 case 'M':
5236 {
5237 int started = 0;
5238 int reg;
5239
5240 func (stream, "{");
5241
5242 /* It would be nice if we could spot
5243 ranges, and generate the rS-rE format: */
5244 for (reg = 0; (reg < 8); reg++)
5245 if ((given & (1 << reg)) != 0)
5246 {
5247 if (started)
5248 func (stream, ", ");
5249 started = 1;
5250 func (stream, "%s", arm_regnames[reg]);
5251 }
5252
5253 if (domasklr)
5254 {
5255 if (started)
5256 func (stream, ", ");
5257 started = 1;
5258 func (stream, "%s", arm_regnames[14] /* "lr" */);
5259 }
5260
5261 if (domaskpc)
5262 {
5263 if (started)
5264 func (stream, ", ");
5265 func (stream, "%s", arm_regnames[15] /* "pc" */);
5266 }
5267
5268 func (stream, "}");
5269 }
5270 break;
5271
5272 case 'W':
5273 /* Print writeback indicator for a LDMIA. We are doing a
5274 writeback if the base register is not in the register
5275 mask. */
5276 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5277 func (stream, "!");
5278 break;
5279
5280 case 'b':
5281 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5282 {
5283 bfd_vma address = (pc + 4
5284 + ((given & 0x00f8) >> 2)
5285 + ((given & 0x0200) >> 3));
5286 info->print_address_func (address, info);
5287 }
5288 break;
5289
5290 case 's':
5291 /* Right shift immediate -- bits 6..10; 1-31 print
5292 as themselves, 0 prints as 32. */
5293 {
5294 long imm = (given & 0x07c0) >> 6;
5295 if (imm == 0)
5296 imm = 32;
5297 func (stream, "#%ld", imm);
5298 }
5299 break;
5300
5301 case '0': case '1': case '2': case '3': case '4':
5302 case '5': case '6': case '7': case '8': case '9':
5303 {
5304 int bitstart = *c++ - '0';
5305 int bitend = 0;
5306
5307 while (*c >= '0' && *c <= '9')
5308 bitstart = (bitstart * 10) + *c++ - '0';
5309
5310 switch (*c)
5311 {
5312 case '-':
5313 {
5314 bfd_vma reg;
5315
5316 c++;
5317 while (*c >= '0' && *c <= '9')
5318 bitend = (bitend * 10) + *c++ - '0';
5319 if (!bitend)
5320 abort ();
5321 reg = given >> bitstart;
5322 reg &= (2 << (bitend - bitstart)) - 1;
5323
5324 switch (*c)
5325 {
5326 case 'r':
5327 func (stream, "%s", arm_regnames[reg]);
5328 break;
5329
5330 case 'd':
5331 func (stream, "%ld", (long) reg);
5332 value_in_comment = reg;
5333 break;
5334
5335 case 'H':
5336 func (stream, "%ld", (long) (reg << 1));
5337 value_in_comment = reg << 1;
5338 break;
5339
5340 case 'W':
5341 func (stream, "%ld", (long) (reg << 2));
5342 value_in_comment = reg << 2;
5343 break;
5344
5345 case 'a':
5346 /* PC-relative address -- the bottom two
5347 bits of the address are dropped
5348 before the calculation. */
5349 info->print_address_func
5350 (((pc + 4) & ~3) + (reg << 2), info);
5351 value_in_comment = 0;
5352 break;
5353
5354 case 'x':
5355 func (stream, "0x%04lx", (long) reg);
5356 break;
5357
5358 case 'B':
5359 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
5360 info->print_address_func (reg * 2 + pc + 4, info);
5361 value_in_comment = 0;
5362 break;
5363
5364 case 'c':
5365 func (stream, "%s", arm_conditional [reg]);
5366 break;
5367
5368 default:
5369 abort ();
5370 }
5371 }
5372 break;
5373
5374 case '\'':
5375 c++;
5376 if ((given & (1 << bitstart)) != 0)
5377 func (stream, "%c", *c);
5378 break;
5379
5380 case '?':
5381 ++c;
5382 if ((given & (1 << bitstart)) != 0)
5383 func (stream, "%c", *c++);
5384 else
5385 func (stream, "%c", *++c);
5386 break;
5387
5388 default:
5389 abort ();
5390 }
5391 }
5392 break;
5393
5394 default:
5395 abort ();
5396 }
5397 }
5398
5399 if (value_in_comment > 32 || value_in_comment < -16)
5400 func (stream, "\t; 0x%lx", value_in_comment);
5401 return;
5402 }
5403
5404 /* No match. */
5405 abort ();
5406 }
5407
5408 /* Return the name of an V7M special register. */
5409
5410 static const char *
5411 psr_name (int regno)
5412 {
5413 switch (regno)
5414 {
5415 case 0: return "APSR";
5416 case 1: return "IAPSR";
5417 case 2: return "EAPSR";
5418 case 3: return "PSR";
5419 case 5: return "IPSR";
5420 case 6: return "EPSR";
5421 case 7: return "IEPSR";
5422 case 8: return "MSP";
5423 case 9: return "PSP";
5424 case 16: return "PRIMASK";
5425 case 17: return "BASEPRI";
5426 case 18: return "BASEPRI_MAX";
5427 case 19: return "FAULTMASK";
5428 case 20: return "CONTROL";
5429 default: return "<unknown>";
5430 }
5431 }
5432
5433 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5434
5435 static void
5436 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
5437 {
5438 const struct opcode32 *insn;
5439 void *stream = info->stream;
5440 fprintf_ftype func = info->fprintf_func;
5441
5442 if (print_insn_coprocessor (pc, info, given, TRUE))
5443 return;
5444
5445 if (print_insn_neon (info, given, TRUE))
5446 return;
5447
5448 for (insn = thumb32_opcodes; insn->assembler; insn++)
5449 if ((given & insn->mask) == insn->value)
5450 {
5451 bfd_boolean is_unpredictable = FALSE;
5452 signed long value_in_comment = 0;
5453 const char *c = insn->assembler;
5454
5455 for (; *c; c++)
5456 {
5457 if (*c != '%')
5458 {
5459 func (stream, "%c", *c);
5460 continue;
5461 }
5462
5463 switch (*++c)
5464 {
5465 case '%':
5466 func (stream, "%%");
5467 break;
5468
5469 case 'c':
5470 if (ifthen_state)
5471 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5472 break;
5473
5474 case 'x':
5475 if (ifthen_next_state)
5476 func (stream, "\t; unpredictable branch in IT block\n");
5477 break;
5478
5479 case 'X':
5480 if (ifthen_state)
5481 func (stream, "\t; unpredictable <IT:%s>",
5482 arm_conditional[IFTHEN_COND]);
5483 break;
5484
5485 case 'I':
5486 {
5487 unsigned int imm12 = 0;
5488
5489 imm12 |= (given & 0x000000ffu);
5490 imm12 |= (given & 0x00007000u) >> 4;
5491 imm12 |= (given & 0x04000000u) >> 15;
5492 func (stream, "#%u", imm12);
5493 value_in_comment = imm12;
5494 }
5495 break;
5496
5497 case 'M':
5498 {
5499 unsigned int bits = 0, imm, imm8, mod;
5500
5501 bits |= (given & 0x000000ffu);
5502 bits |= (given & 0x00007000u) >> 4;
5503 bits |= (given & 0x04000000u) >> 15;
5504 imm8 = (bits & 0x0ff);
5505 mod = (bits & 0xf00) >> 8;
5506 switch (mod)
5507 {
5508 case 0: imm = imm8; break;
5509 case 1: imm = ((imm8 << 16) | imm8); break;
5510 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5511 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
5512 default:
5513 mod = (bits & 0xf80) >> 7;
5514 imm8 = (bits & 0x07f) | 0x80;
5515 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5516 }
5517 func (stream, "#%u", imm);
5518 value_in_comment = imm;
5519 }
5520 break;
5521
5522 case 'J':
5523 {
5524 unsigned int imm = 0;
5525
5526 imm |= (given & 0x000000ffu);
5527 imm |= (given & 0x00007000u) >> 4;
5528 imm |= (given & 0x04000000u) >> 15;
5529 imm |= (given & 0x000f0000u) >> 4;
5530 func (stream, "#%u", imm);
5531 value_in_comment = imm;
5532 }
5533 break;
5534
5535 case 'K':
5536 {
5537 unsigned int imm = 0;
5538
5539 imm |= (given & 0x000f0000u) >> 16;
5540 imm |= (given & 0x00000ff0u) >> 0;
5541 imm |= (given & 0x0000000fu) << 12;
5542 func (stream, "#%u", imm);
5543 value_in_comment = imm;
5544 }
5545 break;
5546
5547 case 'H':
5548 {
5549 unsigned int imm = 0;
5550
5551 imm |= (given & 0x000f0000u) >> 4;
5552 imm |= (given & 0x00000fffu) >> 0;
5553 func (stream, "#%u", imm);
5554 value_in_comment = imm;
5555 }
5556 break;
5557
5558 case 'V':
5559 {
5560 unsigned int imm = 0;
5561
5562 imm |= (given & 0x00000fffu);
5563 imm |= (given & 0x000f0000u) >> 4;
5564 func (stream, "#%u", imm);
5565 value_in_comment = imm;
5566 }
5567 break;
5568
5569 case 'S':
5570 {
5571 unsigned int reg = (given & 0x0000000fu);
5572 unsigned int stp = (given & 0x00000030u) >> 4;
5573 unsigned int imm = 0;
5574 imm |= (given & 0x000000c0u) >> 6;
5575 imm |= (given & 0x00007000u) >> 10;
5576
5577 func (stream, "%s", arm_regnames[reg]);
5578 switch (stp)
5579 {
5580 case 0:
5581 if (imm > 0)
5582 func (stream, ", lsl #%u", imm);
5583 break;
5584
5585 case 1:
5586 if (imm == 0)
5587 imm = 32;
5588 func (stream, ", lsr #%u", imm);
5589 break;
5590
5591 case 2:
5592 if (imm == 0)
5593 imm = 32;
5594 func (stream, ", asr #%u", imm);
5595 break;
5596
5597 case 3:
5598 if (imm == 0)
5599 func (stream, ", rrx");
5600 else
5601 func (stream, ", ror #%u", imm);
5602 }
5603 }
5604 break;
5605
5606 case 'a':
5607 {
5608 unsigned int Rn = (given & 0x000f0000) >> 16;
5609 unsigned int U = ! NEGATIVE_BIT_SET;
5610 unsigned int op = (given & 0x00000f00) >> 8;
5611 unsigned int i12 = (given & 0x00000fff);
5612 unsigned int i8 = (given & 0x000000ff);
5613 bfd_boolean writeback = FALSE, postind = FALSE;
5614 bfd_vma offset = 0;
5615
5616 func (stream, "[%s", arm_regnames[Rn]);
5617 if (U) /* 12-bit positive immediate offset. */
5618 {
5619 offset = i12;
5620 if (Rn != 15)
5621 value_in_comment = offset;
5622 }
5623 else if (Rn == 15) /* 12-bit negative immediate offset. */
5624 offset = - (int) i12;
5625 else if (op == 0x0) /* Shifted register offset. */
5626 {
5627 unsigned int Rm = (i8 & 0x0f);
5628 unsigned int sh = (i8 & 0x30) >> 4;
5629
5630 func (stream, ", %s", arm_regnames[Rm]);
5631 if (sh)
5632 func (stream, ", lsl #%u", sh);
5633 func (stream, "]");
5634 break;
5635 }
5636 else switch (op)
5637 {
5638 case 0xE: /* 8-bit positive immediate offset. */
5639 offset = i8;
5640 break;
5641
5642 case 0xC: /* 8-bit negative immediate offset. */
5643 offset = -i8;
5644 break;
5645
5646 case 0xF: /* 8-bit + preindex with wb. */
5647 offset = i8;
5648 writeback = TRUE;
5649 break;
5650
5651 case 0xD: /* 8-bit - preindex with wb. */
5652 offset = -i8;
5653 writeback = TRUE;
5654 break;
5655
5656 case 0xB: /* 8-bit + postindex. */
5657 offset = i8;
5658 postind = TRUE;
5659 break;
5660
5661 case 0x9: /* 8-bit - postindex. */
5662 offset = -i8;
5663 postind = TRUE;
5664 break;
5665
5666 default:
5667 func (stream, ", <undefined>]");
5668 goto skip;
5669 }
5670
5671 if (postind)
5672 func (stream, "], #%d", (int) offset);
5673 else
5674 {
5675 if (offset)
5676 func (stream, ", #%d", (int) offset);
5677 func (stream, writeback ? "]!" : "]");
5678 }
5679
5680 if (Rn == 15)
5681 {
5682 func (stream, "\t; ");
5683 info->print_address_func (((pc + 4) & ~3) + offset, info);
5684 }
5685 }
5686 skip:
5687 break;
5688
5689 case 'A':
5690 {
5691 unsigned int U = ! NEGATIVE_BIT_SET;
5692 unsigned int W = WRITEBACK_BIT_SET;
5693 unsigned int Rn = (given & 0x000f0000) >> 16;
5694 unsigned int off = (given & 0x000000ff);
5695
5696 func (stream, "[%s", arm_regnames[Rn]);
5697
5698 if (PRE_BIT_SET)
5699 {
5700 if (off || !U)
5701 {
5702 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5703 value_in_comment = off * 4 * U ? 1 : -1;
5704 }
5705 func (stream, "]");
5706 if (W)
5707 func (stream, "!");
5708 }
5709 else
5710 {
5711 func (stream, "], ");
5712 if (W)
5713 {
5714 func (stream, "#%c%u", U ? '+' : '-', off * 4);
5715 value_in_comment = off * 4 * U ? 1 : -1;
5716 }
5717 else
5718 {
5719 func (stream, "{%u}", off);
5720 value_in_comment = off;
5721 }
5722 }
5723 }
5724 break;
5725
5726 case 'w':
5727 {
5728 unsigned int Sbit = (given & 0x01000000) >> 24;
5729 unsigned int type = (given & 0x00600000) >> 21;
5730
5731 switch (type)
5732 {
5733 case 0: func (stream, Sbit ? "sb" : "b"); break;
5734 case 1: func (stream, Sbit ? "sh" : "h"); break;
5735 case 2:
5736 if (Sbit)
5737 func (stream, "??");
5738 break;
5739 case 3:
5740 func (stream, "??");
5741 break;
5742 }
5743 }
5744 break;
5745
5746 case 'm':
5747 {
5748 int started = 0;
5749 int reg;
5750
5751 func (stream, "{");
5752 for (reg = 0; reg < 16; reg++)
5753 if ((given & (1 << reg)) != 0)
5754 {
5755 if (started)
5756 func (stream, ", ");
5757 started = 1;
5758 func (stream, "%s", arm_regnames[reg]);
5759 }
5760 func (stream, "}");
5761 }
5762 break;
5763
5764 case 'E':
5765 {
5766 unsigned int msb = (given & 0x0000001f);
5767 unsigned int lsb = 0;
5768
5769 lsb |= (given & 0x000000c0u) >> 6;
5770 lsb |= (given & 0x00007000u) >> 10;
5771 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5772 }
5773 break;
5774
5775 case 'F':
5776 {
5777 unsigned int width = (given & 0x0000001f) + 1;
5778 unsigned int lsb = 0;
5779
5780 lsb |= (given & 0x000000c0u) >> 6;
5781 lsb |= (given & 0x00007000u) >> 10;
5782 func (stream, "#%u, #%u", lsb, width);
5783 }
5784 break;
5785
5786 case 'b':
5787 {
5788 unsigned int S = (given & 0x04000000u) >> 26;
5789 unsigned int J1 = (given & 0x00002000u) >> 13;
5790 unsigned int J2 = (given & 0x00000800u) >> 11;
5791 bfd_vma offset = 0;
5792
5793 offset |= !S << 20;
5794 offset |= J2 << 19;
5795 offset |= J1 << 18;
5796 offset |= (given & 0x003f0000) >> 4;
5797 offset |= (given & 0x000007ff) << 1;
5798 offset -= (1 << 20);
5799
5800 info->print_address_func (pc + 4 + offset, info);
5801 }
5802 break;
5803
5804 case 'B':
5805 {
5806 unsigned int S = (given & 0x04000000u) >> 26;
5807 unsigned int I1 = (given & 0x00002000u) >> 13;
5808 unsigned int I2 = (given & 0x00000800u) >> 11;
5809 bfd_vma offset = 0;
5810
5811 offset |= !S << 24;
5812 offset |= !(I1 ^ S) << 23;
5813 offset |= !(I2 ^ S) << 22;
5814 offset |= (given & 0x03ff0000u) >> 4;
5815 offset |= (given & 0x000007ffu) << 1;
5816 offset -= (1 << 24);
5817 offset += pc + 4;
5818
5819 /* BLX target addresses are always word aligned. */
5820 if ((given & 0x00001000u) == 0)
5821 offset &= ~2u;
5822
5823 info->print_address_func (offset, info);
5824 }
5825 break;
5826
5827 case 's':
5828 {
5829 unsigned int shift = 0;
5830
5831 shift |= (given & 0x000000c0u) >> 6;
5832 shift |= (given & 0x00007000u) >> 10;
5833 if (WRITEBACK_BIT_SET)
5834 func (stream, ", asr #%u", shift);
5835 else if (shift)
5836 func (stream, ", lsl #%u", shift);
5837 /* else print nothing - lsl #0 */
5838 }
5839 break;
5840
5841 case 'R':
5842 {
5843 unsigned int rot = (given & 0x00000030) >> 4;
5844
5845 if (rot)
5846 func (stream, ", ror #%u", rot * 8);
5847 }
5848 break;
5849
5850 case 'U':
5851 if ((given & 0xf0) == 0x60)
5852 {
5853 switch (given & 0xf)
5854 {
5855 case 0xf: func (stream, "sy"); break;
5856 default:
5857 func (stream, "#%d", (int) given & 0xf);
5858 break;
5859 }
5860 }
5861 else
5862 {
5863 const char * opt = data_barrier_option (given & 0xf);
5864 if (opt != NULL)
5865 func (stream, "%s", opt);
5866 else
5867 func (stream, "#%d", (int) given & 0xf);
5868 }
5869 break;
5870
5871 case 'C':
5872 if ((given & 0xff) == 0)
5873 {
5874 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5875 if (given & 0x800)
5876 func (stream, "f");
5877 if (given & 0x400)
5878 func (stream, "s");
5879 if (given & 0x200)
5880 func (stream, "x");
5881 if (given & 0x100)
5882 func (stream, "c");
5883 }
5884 else if ((given & 0x20) == 0x20)
5885 {
5886 char const* name;
5887 unsigned sysm = (given & 0xf00) >> 8;
5888
5889 sysm |= (given & 0x30);
5890 sysm |= (given & 0x00100000) >> 14;
5891 name = banked_regname (sysm);
5892
5893 if (name != NULL)
5894 func (stream, "%s", name);
5895 else
5896 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5897 }
5898 else
5899 {
5900 func (stream, "%s", psr_name (given & 0xff));
5901 }
5902 break;
5903
5904 case 'D':
5905 if (((given & 0xff) == 0)
5906 || ((given & 0x20) == 0x20))
5907 {
5908 char const* name;
5909 unsigned sm = (given & 0xf0000) >> 16;
5910
5911 sm |= (given & 0x30);
5912 sm |= (given & 0x00100000) >> 14;
5913 name = banked_regname (sm);
5914
5915 if (name != NULL)
5916 func (stream, "%s", name);
5917 else
5918 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
5919 }
5920 else
5921 func (stream, "%s", psr_name (given & 0xff));
5922 break;
5923
5924 case '0': case '1': case '2': case '3': case '4':
5925 case '5': case '6': case '7': case '8': case '9':
5926 {
5927 int width;
5928 unsigned long val;
5929
5930 c = arm_decode_bitfield (c, given, &val, &width);
5931
5932 switch (*c)
5933 {
5934 case 'd':
5935 func (stream, "%lu", val);
5936 value_in_comment = val;
5937 break;
5938
5939 case 'D':
5940 func (stream, "%lu", val + 1);
5941 value_in_comment = val + 1;
5942 break;
5943
5944 case 'W':
5945 func (stream, "%lu", val * 4);
5946 value_in_comment = val * 4;
5947 break;
5948
5949 case 'S':
5950 if (val == 13)
5951 is_unpredictable = TRUE;
5952 /* Fall through. */
5953 case 'R':
5954 if (val == 15)
5955 is_unpredictable = TRUE;
5956 /* Fall through. */
5957 case 'r':
5958 func (stream, "%s", arm_regnames[val]);
5959 break;
5960
5961 case 'c':
5962 func (stream, "%s", arm_conditional[val]);
5963 break;
5964
5965 case '\'':
5966 c++;
5967 if (val == ((1ul << width) - 1))
5968 func (stream, "%c", *c);
5969 break;
5970
5971 case '`':
5972 c++;
5973 if (val == 0)
5974 func (stream, "%c", *c);
5975 break;
5976
5977 case '?':
5978 func (stream, "%c", c[(1 << width) - (int) val]);
5979 c += 1 << width;
5980 break;
5981
5982 case 'x':
5983 func (stream, "0x%lx", val & 0xffffffffUL);
5984 break;
5985
5986 default:
5987 abort ();
5988 }
5989 }
5990 break;
5991
5992 case 'L':
5993 /* PR binutils/12534
5994 If we have a PC relative offset in an LDRD or STRD
5995 instructions then display the decoded address. */
5996 if (((given >> 16) & 0xf) == 0xf)
5997 {
5998 bfd_vma offset = (given & 0xff) * 4;
5999
6000 if ((given & (1 << 23)) == 0)
6001 offset = - offset;
6002 func (stream, "\t; ");
6003 info->print_address_func ((pc & ~3) + 4 + offset, info);
6004 }
6005 break;
6006
6007 default:
6008 abort ();
6009 }
6010 }
6011
6012 if (value_in_comment > 32 || value_in_comment < -16)
6013 func (stream, "\t; 0x%lx", value_in_comment);
6014
6015 if (is_unpredictable)
6016 func (stream, UNPREDICTABLE_INSTRUCTION);
6017
6018 return;
6019 }
6020
6021 /* No match. */
6022 abort ();
6023 }
6024
6025 /* Print data bytes on INFO->STREAM. */
6026
6027 static void
6028 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6029 struct disassemble_info *info,
6030 long given)
6031 {
6032 switch (info->bytes_per_chunk)
6033 {
6034 case 1:
6035 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6036 break;
6037 case 2:
6038 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6039 break;
6040 case 4:
6041 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6042 break;
6043 default:
6044 abort ();
6045 }
6046 }
6047
6048 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
6049 being displayed in symbol relative addresses.
6050
6051 Also disallow private symbol, with __tagsym$$ prefix,
6052 from ARM RVCT toolchain being displayed. */
6053
6054 bfd_boolean
6055 arm_symbol_is_valid (asymbol * sym,
6056 struct disassemble_info * info ATTRIBUTE_UNUSED)
6057 {
6058 const char * name;
6059
6060 if (sym == NULL)
6061 return FALSE;
6062
6063 name = bfd_asymbol_name (sym);
6064
6065 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
6066 }
6067
6068 /* Parse an individual disassembler option. */
6069
6070 void
6071 parse_arm_disassembler_option (char *option)
6072 {
6073 if (option == NULL)
6074 return;
6075
6076 if (CONST_STRNEQ (option, "reg-names-"))
6077 {
6078 int i;
6079
6080 option += 10;
6081
6082 for (i = NUM_ARM_REGNAMES; i--;)
6083 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
6084 {
6085 regname_selected = i;
6086 break;
6087 }
6088
6089 if (i < 0)
6090 /* XXX - should break 'option' at following delimiter. */
6091 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
6092 }
6093 else if (CONST_STRNEQ (option, "force-thumb"))
6094 force_thumb = 1;
6095 else if (CONST_STRNEQ (option, "no-force-thumb"))
6096 force_thumb = 0;
6097 else
6098 /* XXX - should break 'option' at following delimiter. */
6099 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
6100
6101 return;
6102 }
6103
6104 /* Parse the string of disassembler options, spliting it at whitespaces
6105 or commas. (Whitespace separators supported for backwards compatibility). */
6106
6107 static void
6108 parse_disassembler_options (char *options)
6109 {
6110 if (options == NULL)
6111 return;
6112
6113 while (*options)
6114 {
6115 parse_arm_disassembler_option (options);
6116
6117 /* Skip forward to next seperator. */
6118 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
6119 ++ options;
6120 /* Skip forward past seperators. */
6121 while (ISSPACE (*options) || (*options == ','))
6122 ++ options;
6123 }
6124 }
6125
6126 static bfd_boolean
6127 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6128 enum map_type *map_symbol);
6129
6130 /* Search back through the insn stream to determine if this instruction is
6131 conditionally executed. */
6132
6133 static void
6134 find_ifthen_state (bfd_vma pc,
6135 struct disassemble_info *info,
6136 bfd_boolean little)
6137 {
6138 unsigned char b[2];
6139 unsigned int insn;
6140 int status;
6141 /* COUNT is twice the number of instructions seen. It will be odd if we
6142 just crossed an instruction boundary. */
6143 int count;
6144 int it_count;
6145 unsigned int seen_it;
6146 bfd_vma addr;
6147
6148 ifthen_address = pc;
6149 ifthen_state = 0;
6150
6151 addr = pc;
6152 count = 1;
6153 it_count = 0;
6154 seen_it = 0;
6155 /* Scan backwards looking for IT instructions, keeping track of where
6156 instruction boundaries are. We don't know if something is actually an
6157 IT instruction until we find a definite instruction boundary. */
6158 for (;;)
6159 {
6160 if (addr == 0 || info->symbol_at_address_func (addr, info))
6161 {
6162 /* A symbol must be on an instruction boundary, and will not
6163 be within an IT block. */
6164 if (seen_it && (count & 1))
6165 break;
6166
6167 return;
6168 }
6169 addr -= 2;
6170 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
6171 if (status)
6172 return;
6173
6174 if (little)
6175 insn = (b[0]) | (b[1] << 8);
6176 else
6177 insn = (b[1]) | (b[0] << 8);
6178 if (seen_it)
6179 {
6180 if ((insn & 0xf800) < 0xe800)
6181 {
6182 /* Addr + 2 is an instruction boundary. See if this matches
6183 the expected boundary based on the position of the last
6184 IT candidate. */
6185 if (count & 1)
6186 break;
6187 seen_it = 0;
6188 }
6189 }
6190 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6191 {
6192 enum map_type type = MAP_ARM;
6193 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6194
6195 if (!found || (found && type == MAP_THUMB))
6196 {
6197 /* This could be an IT instruction. */
6198 seen_it = insn;
6199 it_count = count >> 1;
6200 }
6201 }
6202 if ((insn & 0xf800) >= 0xe800)
6203 count++;
6204 else
6205 count = (count + 2) | 1;
6206 /* IT blocks contain at most 4 instructions. */
6207 if (count >= 8 && !seen_it)
6208 return;
6209 }
6210 /* We found an IT instruction. */
6211 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6212 if ((ifthen_state & 0xf) == 0)
6213 ifthen_state = 0;
6214 }
6215
6216 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6217 mapping symbol. */
6218
6219 static int
6220 is_mapping_symbol (struct disassemble_info *info, int n,
6221 enum map_type *map_type)
6222 {
6223 const char *name;
6224
6225 name = bfd_asymbol_name (info->symtab[n]);
6226 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6227 && (name[2] == 0 || name[2] == '.'))
6228 {
6229 *map_type = ((name[1] == 'a') ? MAP_ARM
6230 : (name[1] == 't') ? MAP_THUMB
6231 : MAP_DATA);
6232 return TRUE;
6233 }
6234
6235 return FALSE;
6236 }
6237
6238 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6239 Returns nonzero if *MAP_TYPE was set. */
6240
6241 static int
6242 get_map_sym_type (struct disassemble_info *info,
6243 int n,
6244 enum map_type *map_type)
6245 {
6246 /* If the symbol is in a different section, ignore it. */
6247 if (info->section != NULL && info->section != info->symtab[n]->section)
6248 return FALSE;
6249
6250 return is_mapping_symbol (info, n, map_type);
6251 }
6252
6253 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
6254 Returns nonzero if *MAP_TYPE was set. */
6255
6256 static int
6257 get_sym_code_type (struct disassemble_info *info,
6258 int n,
6259 enum map_type *map_type)
6260 {
6261 elf_symbol_type *es;
6262 unsigned int type;
6263
6264 /* If the symbol is in a different section, ignore it. */
6265 if (info->section != NULL && info->section != info->symtab[n]->section)
6266 return FALSE;
6267
6268 es = *(elf_symbol_type **)(info->symtab + n);
6269 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6270
6271 /* If the symbol has function type then use that. */
6272 if (type == STT_FUNC || type == STT_GNU_IFUNC)
6273 {
6274 if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
6275 *map_type = MAP_THUMB;
6276 else
6277 *map_type = MAP_ARM;
6278 return TRUE;
6279 }
6280
6281 return FALSE;
6282 }
6283
6284 /* Search the mapping symbol state for instruction at pc. This is only
6285 applicable for elf target.
6286
6287 There is an assumption Here, info->private_data contains the correct AND
6288 up-to-date information about current scan process. The information will be
6289 used to speed this search process.
6290
6291 Return TRUE if the mapping state can be determined, and map_symbol
6292 will be updated accordingly. Otherwise, return FALSE. */
6293
6294 static bfd_boolean
6295 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6296 enum map_type *map_symbol)
6297 {
6298 bfd_vma addr;
6299 int n, start = 0;
6300 bfd_boolean found = FALSE;
6301 enum map_type type = MAP_ARM;
6302 struct arm_private_data *private_data;
6303
6304 if (info->private_data == NULL || info->symtab_size == 0
6305 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6306 return FALSE;
6307
6308 private_data = info->private_data;
6309 if (pc == 0)
6310 start = 0;
6311 else
6312 start = private_data->last_mapping_sym;
6313
6314 start = (start == -1)? 0 : start;
6315 addr = bfd_asymbol_value (info->symtab[start]);
6316
6317 if (pc >= addr)
6318 {
6319 if (get_map_sym_type (info, start, &type))
6320 found = TRUE;
6321 }
6322 else
6323 {
6324 for (n = start - 1; n >= 0; n--)
6325 {
6326 if (get_map_sym_type (info, n, &type))
6327 {
6328 found = TRUE;
6329 break;
6330 }
6331 }
6332 }
6333
6334 /* No mapping symbols were found. A leading $d may be
6335 omitted for sections which start with data; but for
6336 compatibility with legacy and stripped binaries, only
6337 assume the leading $d if there is at least one mapping
6338 symbol in the file. */
6339 if (!found && private_data->has_mapping_symbols == 1)
6340 {
6341 type = MAP_DATA;
6342 found = TRUE;
6343 }
6344
6345 *map_symbol = type;
6346 return found;
6347 }
6348
6349 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
6350 of the supplied arm_feature_set structure with bitmasks indicating
6351 the support base architectures and coprocessor extensions.
6352
6353 FIXME: This could more efficiently implemented as a constant array,
6354 although it would also be less robust. */
6355
6356 static void
6357 select_arm_features (unsigned long mach,
6358 arm_feature_set * features)
6359 {
6360 #undef ARM_SET_FEATURES
6361 #define ARM_SET_FEATURES(FSET) \
6362 { \
6363 const arm_feature_set fset = FSET; \
6364 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6365 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
6366 }
6367
6368 switch (mach)
6369 {
6370 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6371 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6372 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6373 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6374 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6375 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6376 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6377 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6378 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6379 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6380 case bfd_mach_arm_ep9312:
6381 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6382 ARM_CEXT_MAVERICK | FPU_MAVERICK));
6383 break;
6384 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6385 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6386 /* If the machine type is unknown allow all
6387 architecture types and all extensions. */
6388 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
6389 default:
6390 abort ();
6391 }
6392
6393 #undef ARM_SET_FEATURES
6394 }
6395
6396
6397 /* NOTE: There are no checks in these routines that
6398 the relevant number of data bytes exist. */
6399
6400 static int
6401 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
6402 {
6403 unsigned char b[4];
6404 long given;
6405 int status;
6406 int is_thumb = FALSE;
6407 int is_data = FALSE;
6408 int little_code;
6409 unsigned int size = 4;
6410 void (*printer) (bfd_vma, struct disassemble_info *, long);
6411 bfd_boolean found = FALSE;
6412 struct arm_private_data *private_data;
6413
6414 if (info->disassembler_options)
6415 {
6416 parse_disassembler_options (info->disassembler_options);
6417
6418 /* To avoid repeated parsing of these options, we remove them here. */
6419 info->disassembler_options = NULL;
6420 }
6421
6422 /* PR 10288: Control which instructions will be disassembled. */
6423 if (info->private_data == NULL)
6424 {
6425 static struct arm_private_data private;
6426
6427 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6428 /* If the user did not use the -m command line switch then default to
6429 disassembling all types of ARM instruction.
6430
6431 The info->mach value has to be ignored as this will be based on
6432 the default archictecture for the target and/or hints in the notes
6433 section, but it will never be greater than the current largest arm
6434 machine value (iWMMXt2), which is only equivalent to the V5TE
6435 architecture. ARM architectures have advanced beyond the machine
6436 value encoding, and these newer architectures would be ignored if
6437 the machine value was used.
6438
6439 Ie the -m switch is used to restrict which instructions will be
6440 disassembled. If it is necessary to use the -m switch to tell
6441 objdump that an ARM binary is being disassembled, eg because the
6442 input is a raw binary file, but it is also desired to disassemble
6443 all ARM instructions then use "-marm". This will select the
6444 "unknown" arm architecture which is compatible with any ARM
6445 instruction. */
6446 info->mach = bfd_mach_arm_unknown;
6447
6448 /* Compute the architecture bitmask from the machine number.
6449 Note: This assumes that the machine number will not change
6450 during disassembly.... */
6451 select_arm_features (info->mach, & private.features);
6452
6453 private.has_mapping_symbols = -1;
6454 private.last_mapping_sym = -1;
6455 private.last_mapping_addr = 0;
6456
6457 info->private_data = & private;
6458 }
6459
6460 private_data = info->private_data;
6461
6462 /* Decide if our code is going to be little-endian, despite what the
6463 function argument might say. */
6464 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6465
6466 /* For ELF, consult the symbol table to determine what kind of code
6467 or data we have. */
6468 if (info->symtab_size != 0
6469 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6470 {
6471 bfd_vma addr;
6472 int n, start;
6473 int last_sym = -1;
6474 enum map_type type = MAP_ARM;
6475
6476 /* Start scanning at the start of the function, or wherever
6477 we finished last time. */
6478 /* PR 14006. When the address is 0 we are either at the start of the
6479 very first function, or else the first function in a new, unlinked
6480 executable section (eg because uf -ffunction-sections). Either way
6481 start scanning from the beginning of the symbol table, not where we
6482 left off last time. */
6483 if (pc == 0)
6484 start = 0;
6485 else
6486 {
6487 start = info->symtab_pos + 1;
6488 if (start < private_data->last_mapping_sym)
6489 start = private_data->last_mapping_sym;
6490 }
6491 found = FALSE;
6492
6493 /* First, look for mapping symbols. */
6494 if (private_data->has_mapping_symbols != 0)
6495 {
6496 /* Scan up to the location being disassembled. */
6497 for (n = start; n < info->symtab_size; n++)
6498 {
6499 addr = bfd_asymbol_value (info->symtab[n]);
6500 if (addr > pc)
6501 break;
6502 if (get_map_sym_type (info, n, &type))
6503 {
6504 last_sym = n;
6505 found = TRUE;
6506 }
6507 }
6508
6509 if (!found)
6510 {
6511 /* No mapping symbol found at this address. Look backwards
6512 for a preceding one. */
6513 for (n = start - 1; n >= 0; n--)
6514 {
6515 if (get_map_sym_type (info, n, &type))
6516 {
6517 last_sym = n;
6518 found = TRUE;
6519 break;
6520 }
6521 }
6522 }
6523
6524 if (found)
6525 private_data->has_mapping_symbols = 1;
6526
6527 /* No mapping symbols were found. A leading $d may be
6528 omitted for sections which start with data; but for
6529 compatibility with legacy and stripped binaries, only
6530 assume the leading $d if there is at least one mapping
6531 symbol in the file. */
6532 if (!found && private_data->has_mapping_symbols == -1)
6533 {
6534 /* Look for mapping symbols, in any section. */
6535 for (n = 0; n < info->symtab_size; n++)
6536 if (is_mapping_symbol (info, n, &type))
6537 {
6538 private_data->has_mapping_symbols = 1;
6539 break;
6540 }
6541 if (private_data->has_mapping_symbols == -1)
6542 private_data->has_mapping_symbols = 0;
6543 }
6544
6545 if (!found && private_data->has_mapping_symbols == 1)
6546 {
6547 type = MAP_DATA;
6548 found = TRUE;
6549 }
6550 }
6551
6552 /* Next search for function symbols to separate ARM from Thumb
6553 in binaries without mapping symbols. */
6554 if (!found)
6555 {
6556 /* Scan up to the location being disassembled. */
6557 for (n = start; n < info->symtab_size; n++)
6558 {
6559 addr = bfd_asymbol_value (info->symtab[n]);
6560 if (addr > pc)
6561 break;
6562 if (get_sym_code_type (info, n, &type))
6563 {
6564 last_sym = n;
6565 found = TRUE;
6566 }
6567 }
6568
6569 if (!found)
6570 {
6571 /* No mapping symbol found at this address. Look backwards
6572 for a preceding one. */
6573 for (n = start - 1; n >= 0; n--)
6574 {
6575 if (get_sym_code_type (info, n, &type))
6576 {
6577 last_sym = n;
6578 found = TRUE;
6579 break;
6580 }
6581 }
6582 }
6583 }
6584
6585 private_data->last_mapping_sym = last_sym;
6586 private_data->last_type = type;
6587 is_thumb = (private_data->last_type == MAP_THUMB);
6588 is_data = (private_data->last_type == MAP_DATA);
6589
6590 /* Look a little bit ahead to see if we should print out
6591 two or four bytes of data. If there's a symbol,
6592 mapping or otherwise, after two bytes then don't
6593 print more. */
6594 if (is_data)
6595 {
6596 size = 4 - (pc & 3);
6597 for (n = last_sym + 1; n < info->symtab_size; n++)
6598 {
6599 addr = bfd_asymbol_value (info->symtab[n]);
6600 if (addr > pc
6601 && (info->section == NULL
6602 || info->section == info->symtab[n]->section))
6603 {
6604 if (addr - pc < size)
6605 size = addr - pc;
6606 break;
6607 }
6608 }
6609 /* If the next symbol is after three bytes, we need to
6610 print only part of the data, so that we can use either
6611 .byte or .short. */
6612 if (size == 3)
6613 size = (pc & 1) ? 1 : 2;
6614 }
6615 }
6616
6617 if (info->symbols != NULL)
6618 {
6619 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6620 {
6621 coff_symbol_type * cs;
6622
6623 cs = coffsymbol (*info->symbols);
6624 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6625 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6626 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6627 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6628 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6629 }
6630 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6631 && !found)
6632 {
6633 /* If no mapping symbol has been found then fall back to the type
6634 of the function symbol. */
6635 elf_symbol_type * es;
6636 unsigned int type;
6637
6638 es = *(elf_symbol_type **)(info->symbols);
6639 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6640
6641 is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
6642 == ST_BRANCH_TO_THUMB)
6643 || type == STT_ARM_16BIT);
6644 }
6645 else if (bfd_asymbol_flavour (*info->symbols)
6646 == bfd_target_mach_o_flavour)
6647 {
6648 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6649
6650 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6651 }
6652 }
6653
6654 if (force_thumb)
6655 is_thumb = TRUE;
6656
6657 if (is_data)
6658 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6659 else
6660 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6661
6662 info->bytes_per_line = 4;
6663
6664 /* PR 10263: Disassemble data if requested to do so by the user. */
6665 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
6666 {
6667 int i;
6668
6669 /* Size was already set above. */
6670 info->bytes_per_chunk = size;
6671 printer = print_insn_data;
6672
6673 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
6674 given = 0;
6675 if (little)
6676 for (i = size - 1; i >= 0; i--)
6677 given = b[i] | (given << 8);
6678 else
6679 for (i = 0; i < (int) size; i++)
6680 given = b[i] | (given << 8);
6681 }
6682 else if (!is_thumb)
6683 {
6684 /* In ARM mode endianness is a straightforward issue: the instruction
6685 is four bytes long and is either ordered 0123 or 3210. */
6686 printer = print_insn_arm;
6687 info->bytes_per_chunk = 4;
6688 size = 4;
6689
6690 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
6691 if (little_code)
6692 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6693 else
6694 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
6695 }
6696 else
6697 {
6698 /* In Thumb mode we have the additional wrinkle of two
6699 instruction lengths. Fortunately, the bits that determine
6700 the length of the current instruction are always to be found
6701 in the first two bytes. */
6702 printer = print_insn_thumb16;
6703 info->bytes_per_chunk = 2;
6704 size = 2;
6705
6706 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
6707 if (little_code)
6708 given = (b[0]) | (b[1] << 8);
6709 else
6710 given = (b[1]) | (b[0] << 8);
6711
6712 if (!status)
6713 {
6714 /* These bit patterns signal a four-byte Thumb
6715 instruction. */
6716 if ((given & 0xF800) == 0xF800
6717 || (given & 0xF800) == 0xF000
6718 || (given & 0xF800) == 0xE800)
6719 {
6720 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
6721 if (little_code)
6722 given = (b[0]) | (b[1] << 8) | (given << 16);
6723 else
6724 given = (b[1]) | (b[0] << 8) | (given << 16);
6725
6726 printer = print_insn_thumb32;
6727 size = 4;
6728 }
6729 }
6730
6731 if (ifthen_address != pc)
6732 find_ifthen_state (pc, info, little_code);
6733
6734 if (ifthen_state)
6735 {
6736 if ((ifthen_state & 0xf) == 0x8)
6737 ifthen_next_state = 0;
6738 else
6739 ifthen_next_state = (ifthen_state & 0xe0)
6740 | ((ifthen_state & 0xf) << 1);
6741 }
6742 }
6743
6744 if (status)
6745 {
6746 info->memory_error_func (status, pc, info);
6747 return -1;
6748 }
6749 if (info->flags & INSN_HAS_RELOC)
6750 /* If the instruction has a reloc associated with it, then
6751 the offset field in the instruction will actually be the
6752 addend for the reloc. (We are using REL type relocs).
6753 In such cases, we can ignore the pc when computing
6754 addresses, since the addend is not currently pc-relative. */
6755 pc = 0;
6756
6757 printer (pc, info, given);
6758
6759 if (is_thumb)
6760 {
6761 ifthen_state = ifthen_next_state;
6762 ifthen_address += size;
6763 }
6764 return size;
6765 }
6766
6767 int
6768 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
6769 {
6770 /* Detect BE8-ness and record it in the disassembler info. */
6771 if (info->flavour == bfd_target_elf_flavour
6772 && info->section != NULL
6773 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6774 info->endian_code = BFD_ENDIAN_LITTLE;
6775
6776 return print_insn (pc, info, FALSE);
6777 }
6778
6779 int
6780 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
6781 {
6782 return print_insn (pc, info, TRUE);
6783 }
6784
6785 void
6786 print_arm_disassembler_options (FILE *stream)
6787 {
6788 int i;
6789
6790 fprintf (stream, _("\n\
6791 The following ARM specific disassembler options are supported for use with\n\
6792 the -M switch:\n"));
6793
6794 for (i = NUM_ARM_REGNAMES; i--;)
6795 fprintf (stream, " reg-names-%s %*c%s\n",
6796 regnames[i].name,
6797 (int)(14 - strlen (regnames[i].name)), ' ',
6798 regnames[i].description);
6799
6800 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
6801 fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");
6802 }
GDB Binutils - Deliverables
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