1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
26 #include "disassemble.h"
27 #include "opcode/arm.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
38 #include "elf/internal.h"
42 /* FIXME: Belongs in global header. */
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
47 /* Cached mapping symbol state. */
55 struct arm_private_data
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features
;
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type
;
63 /* Tracking symbol table information */
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset
;
68 bfd_vma last_mapping_addr
;
121 MVE_VSTRB_SCATTER_T1
,
122 MVE_VSTRH_SCATTER_T2
,
123 MVE_VSTRW_SCATTER_T3
,
124 MVE_VSTRD_SCATTER_T4
,
125 MVE_VSTRW_SCATTER_T5
,
126 MVE_VSTRD_SCATTER_T6
,
128 MVE_VCVT_BETWEEN_FP_INT
,
130 MVE_VCVT_FROM_FP_TO_INT
,
133 MVE_VMOV_GP_TO_VEC_LANE
,
136 MVE_VMOV2_VEC_LANE_TO_GP
,
137 MVE_VMOV2_GP_TO_VEC_LANE
,
138 MVE_VMOV_VEC_LANE_TO_GP
,
296 enum mve_unpredictable
298 UNPRED_IT_BLOCK
, /* Unpredictable because mve insn in it block.
300 UNPRED_FCA_0_FCB_1
, /* Unpredictable because fcA = 0 and
302 UNPRED_R13
, /* Unpredictable because r13 (sp) or
304 UNPRED_R15
, /* Unpredictable because r15 (pc) is used. */
305 UNPRED_Q_GT_4
, /* Unpredictable because
306 vec reg start > 4 (vld4/st4). */
307 UNPRED_Q_GT_6
, /* Unpredictable because
308 vec reg start > 6 (vld2/st2). */
309 UNPRED_R13_AND_WB
, /* Unpredictable becase gp reg = r13
311 UNPRED_Q_REGS_EQUAL
, /* Unpredictable because vector registers are
313 UNPRED_OS
, /* Unpredictable because offset scaled == 1. */
314 UNPRED_GP_REGS_EQUAL
, /* Unpredictable because gp registers are the
316 UNPRED_Q_REGS_EQ_AND_SIZE_1
, /* Unpredictable because q regs equal and
318 UNPRED_Q_REGS_EQ_AND_SIZE_2
, /* Unpredictable because q regs equal and
320 UNPRED_NONE
/* No unpredictable behavior. */
325 UNDEF_SIZE
, /* undefined size. */
326 UNDEF_SIZE_0
, /* undefined because size == 0. */
327 UNDEF_SIZE_2
, /* undefined because size == 2. */
328 UNDEF_SIZE_3
, /* undefined because size == 3. */
329 UNDEF_SIZE_LE_1
, /* undefined because size <= 1. */
330 UNDEF_SIZE_NOT_0
, /* undefined because size != 0. */
331 UNDEF_SIZE_NOT_2
, /* undefined because size != 2. */
332 UNDEF_SIZE_NOT_3
, /* undefined because size != 3. */
333 UNDEF_NOT_UNS_SIZE_0
, /* undefined because U == 0 and
335 UNDEF_NOT_UNS_SIZE_1
, /* undefined because U == 0 and
337 UNDEF_NOT_UNSIGNED
, /* undefined because U == 0. */
338 UNDEF_VCVT_IMM6
, /* imm6 < 32. */
339 UNDEF_VCVT_FSI_IMM6
, /* fsi = 0 and 32 >= imm6 <= 47. */
340 UNDEF_BAD_OP1_OP2
, /* undefined with op2 = 2 and
342 UNDEF_BAD_U_OP1_OP2
, /* undefined with U = 1 and
343 op2 == 0 and op1 == (0 or 1). */
344 UNDEF_OP_0_BAD_CMODE
, /* undefined because op == 0 and cmode
346 UNDEF_XCHG_UNS
, /* undefined because X == 1 and U == 1. */
347 UNDEF_NONE
/* no undefined behavior. */
352 arm_feature_set arch
; /* Architecture defining this insn. */
353 unsigned long value
; /* If arch is 0 then value is a sentinel. */
354 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
355 const char * assembler
; /* How to disassemble this insn. */
362 arm_feature_set arch
; /* Architecture defining this insn. */
363 enum mve_instructions mve_op
; /* Specific mve instruction for faster
365 unsigned long value
; /* If arch is 0 then value is a sentinel. */
366 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
367 const char * assembler
; /* How to disassemble this insn. */
377 /* Shared (between Arm and Thumb mode) opcode. */
380 enum isa isa
; /* Execution mode instruction availability. */
381 arm_feature_set arch
; /* Architecture defining this insn. */
382 unsigned long value
; /* If arch is 0 then value is a sentinel. */
383 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
384 const char * assembler
; /* How to disassemble this insn. */
389 arm_feature_set arch
; /* Architecture defining this insn. */
390 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
391 const char *assembler
; /* How to disassemble this insn. */
394 /* print_insn_coprocessor recognizes the following format control codes:
398 %c print condition code (always bits 28-31 in ARM mode)
399 %b print condition code allowing cp_num == 9
400 %q print shifter argument
401 %u print condition code (unconditional in ARM mode,
402 UNPREDICTABLE if not AL in Thumb)
403 %A print address for ldc/stc/ldf/stf instruction
404 %B print vstm/vldm register list
405 %C print vscclrm register list
406 %I print cirrus signed shift immediate: bits 0..3|4..6
407 %J print register for VLDR instruction
408 %K print address for VLDR instruction
409 %F print the COUNT field of a LFM/SFM instruction.
410 %P print floating point precision in arithmetic insn
411 %Q print floating point precision in ldf/stf insn
412 %R print floating point rounding mode
414 %<bitfield>c print as a condition code (for vsel)
415 %<bitfield>r print as an ARM register
416 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
417 %<bitfield>ru as %<>r but each u register must be unique.
418 %<bitfield>d print the bitfield in decimal
419 %<bitfield>k print immediate for VFPv3 conversion instruction
420 %<bitfield>x print the bitfield in hex
421 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
422 %<bitfield>f print a floating point constant if >7 else a
423 floating point register
424 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
425 %<bitfield>g print as an iWMMXt 64-bit register
426 %<bitfield>G print as an iWMMXt general purpose or control register
427 %<bitfield>D print as a NEON D register
428 %<bitfield>Q print as a NEON Q register
429 %<bitfield>V print as a NEON D or Q register
430 %<bitfield>E print a quarter-float immediate value
432 %y<code> print a single precision VFP reg.
433 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
434 %z<code> print a double precision VFP reg
435 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
437 %<bitfield>'c print specified char iff bitfield is all ones
438 %<bitfield>`c print specified char iff bitfield is all zeroes
439 %<bitfield>?ab... select from array of values in big endian order
441 %L print as an iWMMXt N/M width field.
442 %Z print the Immediate of a WSHUFH instruction.
443 %l like 'A' except use byte offsets for 'B' & 'H'
445 %i print 5-bit immediate in bits 8,3..0
447 %r print register offset address for wldt/wstr instruction. */
449 enum opcode_sentinel_enum
451 SENTINEL_IWMMXT_START
= 1,
453 SENTINEL_GENERIC_START
456 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
457 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
458 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
459 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
461 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
463 static const struct sopcode32 coprocessor_opcodes
[] =
465 /* XScale instructions. */
466 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
467 0x0e200010, 0x0fff0ff0,
468 "mia%c\tacc0, %0-3r, %12-15r"},
469 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
470 0x0e280010, 0x0fff0ff0,
471 "miaph%c\tacc0, %0-3r, %12-15r"},
472 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
473 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
474 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
475 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
476 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
477 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
479 /* Intel Wireless MMX technology instructions. */
480 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START
, 0, "" },
481 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
482 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
483 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
484 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
485 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
486 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
487 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
488 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
489 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
490 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
491 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
492 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
493 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
494 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
495 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
496 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
497 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
498 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
499 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
500 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
501 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
502 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
503 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
504 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
505 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
506 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
507 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
508 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
509 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
510 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
511 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
512 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
513 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
514 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
515 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
516 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
517 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
518 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
519 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
520 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
521 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
522 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
523 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
524 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
525 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
526 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
527 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
528 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
529 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
530 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
531 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
532 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
533 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
534 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
535 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
536 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
537 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
538 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
539 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
540 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
541 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
542 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
543 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
544 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
545 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
546 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
547 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
548 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
549 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
550 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
551 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
552 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
553 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
554 0x0e800120, 0x0f800ff0,
555 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
556 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
557 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
558 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
559 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
560 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
561 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
562 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
563 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
564 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
565 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
566 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
567 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
568 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
569 0x0e8000a0, 0x0f800ff0,
570 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
571 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
572 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
573 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
574 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
575 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
576 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
577 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
578 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
579 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
580 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
581 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
582 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
583 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
584 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
585 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
586 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
587 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
588 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
589 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
590 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
591 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
592 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
593 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
594 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
595 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
596 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
597 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
598 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
599 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
600 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
601 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
602 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
603 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
604 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
605 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
606 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
607 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
608 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
609 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
610 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
611 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
612 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
613 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
614 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
615 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
616 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
617 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
618 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
619 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
620 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
621 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
622 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
623 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
624 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
625 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
626 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
627 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
628 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
629 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
630 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
631 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
632 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
633 {ANY
, ARM_FEATURE_CORE_LOW (0),
634 SENTINEL_IWMMXT_END
, 0, "" },
636 /* Floating point coprocessor (FPA) instructions. */
637 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
638 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
639 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
640 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
641 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
642 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
643 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
644 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
645 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
646 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
647 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
648 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
649 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
650 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
651 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
652 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
653 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
654 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
655 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
656 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
657 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
658 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
659 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
660 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
661 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
662 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
663 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
664 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
665 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
666 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
667 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
668 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
669 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
670 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
671 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
672 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
673 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
674 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
675 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
676 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
677 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
678 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
679 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
680 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
681 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
682 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
683 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
684 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
685 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
686 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
687 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
688 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
689 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
690 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
691 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
692 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
693 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
694 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
695 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
696 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
697 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
698 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
699 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
700 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
701 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
702 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
703 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
704 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
705 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
706 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
707 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
708 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
709 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
710 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
711 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
712 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
713 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
714 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
715 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
716 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
717 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
718 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
719 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
720 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
721 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
722 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
724 /* Armv8.1-M Mainline instructions. */
725 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
726 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
727 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
728 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
730 /* ARMv8-M Mainline Security Extensions instructions. */
731 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
732 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
733 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
734 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
736 /* Register load/store. */
737 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
738 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
739 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
740 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
741 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
742 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
743 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
744 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
745 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
746 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
747 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
748 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
749 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
750 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
751 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
752 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
753 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
754 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
755 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
756 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
757 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
758 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
759 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
760 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
761 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
762 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
763 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
764 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
765 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
766 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
767 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
768 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
769 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
770 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
771 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
772 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
774 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
775 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
776 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
777 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
778 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
779 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
780 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
781 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
783 /* Data transfer between ARM and NEON registers. */
784 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
785 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
786 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
787 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
788 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
789 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
790 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
791 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
792 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
793 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
794 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
795 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
796 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
797 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
798 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
799 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
800 /* Half-precision conversion instructions. */
801 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
802 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
803 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
804 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
805 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
806 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
807 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
808 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
810 /* Floating point coprocessor (VFP) instructions. */
811 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
812 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
813 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_MVE
),
814 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
815 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
816 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
817 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
818 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
819 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
820 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
821 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
822 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
823 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
824 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
825 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
826 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
827 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
828 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
829 {ANY
, ARM_FEATURE_COPROC (FPU_MVE
),
830 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
831 {ANY
, ARM_FEATURE_COPROC (FPU_MVE
),
832 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
833 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
834 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
835 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
836 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
837 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
838 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
839 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
840 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
841 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_MVE
),
842 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
843 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
844 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
845 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
846 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
847 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
848 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
849 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
850 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
851 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
852 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
853 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
854 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
855 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
856 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
857 {ANY
, ARM_FEATURE_COPROC (FPU_MVE
),
858 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
859 {ANY
, ARM_FEATURE_COPROC (FPU_MVE
),
860 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
861 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
862 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
863 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
864 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
865 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
866 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
867 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
868 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
869 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
870 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
871 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
872 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
873 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
874 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
875 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
876 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
877 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
878 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
879 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
880 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
881 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
882 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
883 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
884 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
885 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
886 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
887 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
888 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
889 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
890 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
891 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
892 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
893 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
894 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
895 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
896 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
897 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
898 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
899 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
900 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
901 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
902 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
903 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
904 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
905 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
906 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
907 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
908 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
909 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
910 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
911 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
912 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
913 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
914 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
915 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
916 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
917 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
918 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
919 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
920 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
921 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
922 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
923 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
924 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
925 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
926 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
927 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
928 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
929 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
930 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
931 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
932 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
933 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
934 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
935 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
936 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
937 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
938 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
939 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
940 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
941 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
942 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
943 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
944 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
945 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
946 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
947 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
948 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
949 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
950 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
951 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
952 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
953 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
954 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
955 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
956 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
957 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
958 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
959 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
960 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
961 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
962 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
963 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
964 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
965 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
966 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
967 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
968 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
970 /* Cirrus coprocessor instructions. */
971 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
972 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
973 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
974 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
975 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
976 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
977 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
978 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
979 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
980 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
981 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
982 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
983 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
984 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
985 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
986 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
987 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
988 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
989 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
990 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
991 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
992 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
993 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
994 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
995 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
996 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
997 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
998 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
999 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1000 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1001 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1002 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1003 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1004 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
1005 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1006 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
1007 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1008 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
1009 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1010 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
1011 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1012 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
1013 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1014 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
1015 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1016 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
1017 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1018 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
1019 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1020 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
1021 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1022 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
1023 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1024 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
1025 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1026 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
1027 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1028 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
1029 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1030 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
1031 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1032 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
1033 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1034 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
1035 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1036 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
1037 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1038 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
1039 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1040 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
1041 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1042 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
1043 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1044 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
1045 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1046 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
1047 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1048 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
1049 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1050 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
1051 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1052 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
1053 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1054 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
1055 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1056 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
1057 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1058 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
1059 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1060 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
1061 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1062 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
1063 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1064 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
1065 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1066 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
1067 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1068 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
1069 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1070 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
1071 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1072 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
1073 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1074 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
1075 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1076 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
1077 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1078 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
1079 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1080 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
1081 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1082 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
1083 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1084 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
1085 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1086 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
1087 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1088 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1089 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1090 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1091 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1092 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1093 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1094 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1095 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1096 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1097 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1098 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1099 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1100 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1101 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1102 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1103 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1104 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1105 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1106 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1107 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1108 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1109 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1110 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1111 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1112 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1113 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1114 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1115 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1116 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1117 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1118 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1119 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1120 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1121 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1122 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1123 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1124 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1125 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1126 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1127 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1128 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1129 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1130 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1131 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1132 0x0e000600, 0x0ff00f10,
1133 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1134 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1135 0x0e100600, 0x0ff00f10,
1136 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1137 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1138 0x0e200600, 0x0ff00f10,
1139 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1140 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1141 0x0e300600, 0x0ff00f10,
1142 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1144 /* VFP Fused multiply add instructions. */
1145 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1146 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1147 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1148 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1149 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1150 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1151 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1152 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1153 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1154 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1155 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1156 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1157 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1158 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1159 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1160 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1163 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1164 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1165 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1166 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1167 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1168 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1169 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1170 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1171 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1172 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1173 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1174 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1175 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1176 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1177 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1178 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1179 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1180 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1181 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1182 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1183 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1184 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1185 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1186 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1188 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START
, 0, "" },
1189 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1190 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1191 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1192 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1193 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1194 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1195 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1196 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1197 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1198 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1199 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1200 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1201 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1202 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1203 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1204 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1205 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1206 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1207 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1208 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1209 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1211 /* BFloat16 instructions. */
1212 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1213 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1215 /* Dot Product instructions in the space of coprocessor 13. */
1216 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1217 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1218 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1219 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1221 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1222 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1223 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1224 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1225 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1226 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1227 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1228 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1229 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1230 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1231 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1232 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1233 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1234 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1235 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1236 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1237 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1239 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1240 cp_num: bit <11:8> == 0b1001.
1241 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1242 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1243 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1244 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1245 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1246 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1247 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1248 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1249 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1250 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1251 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1252 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1253 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1254 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1255 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1256 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1257 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1258 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1259 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1260 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1261 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1262 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1263 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1264 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1265 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1266 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1267 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1268 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1269 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1270 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1271 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1272 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1273 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1274 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1275 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1276 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1277 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1278 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1279 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1280 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1281 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1282 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1283 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1284 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1285 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1286 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1287 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1288 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1289 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1290 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1291 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1292 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1293 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1294 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1295 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1296 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1297 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1298 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1299 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1300 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1301 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1302 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1303 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1304 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1305 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1306 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1307 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1308 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1309 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1310 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1311 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1313 /* ARMv8.3 javascript conversion instruction. */
1314 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1315 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1317 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1320 /* Generic coprocessor instructions. These are only matched if a more specific
1321 SIMD or co-processor instruction does not match first. */
1323 static const struct sopcode32 generic_coprocessor_opcodes
[] =
1325 /* Generic coprocessor instructions. */
1326 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1327 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1328 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1329 0x0c500000, 0x0ff00000,
1330 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1331 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1332 0x0e000000, 0x0f000010,
1333 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1334 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1335 0x0e10f010, 0x0f10f010,
1336 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1337 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1338 0x0e100010, 0x0f100010,
1339 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1340 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1341 0x0e000010, 0x0f100010,
1342 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1343 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1344 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1345 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1346 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1348 /* V6 coprocessor instructions. */
1349 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1350 0xfc500000, 0xfff00000,
1351 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1352 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1353 0xfc400000, 0xfff00000,
1354 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1356 /* V5 coprocessor instructions. */
1357 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1358 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1359 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1360 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1361 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1362 0xfe000000, 0xff000010,
1363 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1364 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1365 0xfe000010, 0xff100010,
1366 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1367 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1368 0xfe100010, 0xff100010,
1369 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1371 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1374 /* Neon opcode table: This does not encode the top byte -- that is
1375 checked by the print_insn_neon routine, as it depends on whether we are
1376 doing thumb32 or arm32 disassembly. */
1378 /* print_insn_neon recognizes the following format control codes:
1382 %c print condition code
1383 %u print condition code (unconditional in ARM mode,
1384 UNPREDICTABLE if not AL in Thumb)
1385 %A print v{st,ld}[1234] operands
1386 %B print v{st,ld}[1234] any one operands
1387 %C print v{st,ld}[1234] single->all operands
1389 %E print vmov, vmvn, vorr, vbic encoded constant
1390 %F print vtbl,vtbx register list
1392 %<bitfield>r print as an ARM register
1393 %<bitfield>d print the bitfield in decimal
1394 %<bitfield>e print the 2^N - bitfield in decimal
1395 %<bitfield>D print as a NEON D register
1396 %<bitfield>Q print as a NEON Q register
1397 %<bitfield>R print as a NEON D or Q register
1398 %<bitfield>Sn print byte scaled width limited by n
1399 %<bitfield>Tn print short scaled width limited by n
1400 %<bitfield>Un print long scaled width limited by n
1402 %<bitfield>'c print specified char iff bitfield is all ones
1403 %<bitfield>`c print specified char iff bitfield is all zeroes
1404 %<bitfield>?ab... select from array of values in big endian order. */
1406 static const struct opcode32 neon_opcodes
[] =
1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1410 0xf2b00840, 0xffb00850,
1411 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1413 0xf2b00000, 0xffb00810,
1414 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1416 /* Data transfer between ARM and NEON registers. */
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1418 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1420 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1422 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1424 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1426 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1428 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1430 /* Move data element to all lanes. */
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1432 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1434 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1436 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1440 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1442 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1444 /* Half-precision conversions. */
1445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1446 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1448 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1450 /* NEON fused multiply add instructions. */
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1452 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1453 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1454 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1456 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1458 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1460 /* BFloat16 instructions. */
1461 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1462 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1464 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1465 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1466 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1467 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1468 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1470 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1471 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1472 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
1474 /* Matrix Multiply instructions. */
1475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1476 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1477 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1478 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1479 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1480 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1481 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1482 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1483 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1484 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1486 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1488 /* Two registers, miscellaneous. */
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1490 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1491 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1492 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1494 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1496 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1497 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1498 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1499 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1500 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1501 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1502 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1503 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1504 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1505 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1506 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1507 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1508 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1509 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1510 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1512 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1514 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1516 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1518 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1520 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1522 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1524 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1526 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1528 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1530 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1532 0xf3b20300, 0xffb30fd0,
1533 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1535 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1537 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1539 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1541 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1543 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1544 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1545 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1546 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1547 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1548 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1549 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1551 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1552 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1553 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1555 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1557 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1558 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1559 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1561 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1562 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1563 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1564 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1565 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1567 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1569 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1570 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1571 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1573 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1574 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1575 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1576 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1577 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1579 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1580 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1581 0xf3bb0600, 0xffbf0e10,
1582 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1583 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1584 0xf3b70600, 0xffbf0e10,
1585 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1587 /* Three registers of the same length. */
1588 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1589 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1590 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1591 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1592 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1593 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1594 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1595 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1596 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1597 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1598 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1599 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1600 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1601 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1603 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1604 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1605 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1607 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1608 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1609 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1611 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1613 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1615 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1617 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1619 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1621 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1623 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1625 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1627 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1628 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1629 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1631 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1632 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1633 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1635 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1636 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1637 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1639 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1640 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1641 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1643 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1644 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1645 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1647 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1648 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1649 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1651 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1652 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1653 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1655 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1656 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1657 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1659 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1660 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1661 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1663 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1664 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1665 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1667 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1668 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1669 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1671 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1672 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1673 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1674 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1675 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1676 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1677 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1679 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1681 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1683 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1685 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1687 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1688 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1689 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1691 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1692 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1693 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1695 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1697 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1699 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1701 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1703 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1705 0xf2000b00, 0xff800f10,
1706 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1708 0xf2000b10, 0xff800f10,
1709 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1711 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1713 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1715 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1717 0xf3000b00, 0xff800f10,
1718 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1719 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1720 0xf2000000, 0xfe800f10,
1721 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1722 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1723 0xf2000010, 0xfe800f10,
1724 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1726 0xf2000100, 0xfe800f10,
1727 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1729 0xf2000200, 0xfe800f10,
1730 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1732 0xf2000210, 0xfe800f10,
1733 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1734 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1735 0xf2000300, 0xfe800f10,
1736 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1738 0xf2000310, 0xfe800f10,
1739 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1741 0xf2000400, 0xfe800f10,
1742 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1744 0xf2000410, 0xfe800f10,
1745 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1747 0xf2000500, 0xfe800f10,
1748 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1750 0xf2000510, 0xfe800f10,
1751 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1753 0xf2000600, 0xfe800f10,
1754 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1755 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1756 0xf2000610, 0xfe800f10,
1757 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1759 0xf2000700, 0xfe800f10,
1760 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1762 0xf2000710, 0xfe800f10,
1763 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1765 0xf2000910, 0xfe800f10,
1766 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1768 0xf2000a00, 0xfe800f10,
1769 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1771 0xf2000a10, 0xfe800f10,
1772 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1774 0xf3000b10, 0xff800f10,
1775 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1777 0xf3000c10, 0xff800f10,
1778 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1780 /* One register and an immediate value. */
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1782 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1784 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1786 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1788 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1790 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1792 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1794 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1796 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1798 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1800 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1802 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1803 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1804 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1806 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1808 /* Two registers and a shift amount. */
1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1810 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1812 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1813 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1814 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1815 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1816 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1818 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1819 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1820 0xf2880950, 0xfeb80fd0,
1821 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1823 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1825 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1827 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1829 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1831 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1833 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1835 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1837 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1839 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1841 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1842 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1843 0xf2900950, 0xfeb00fd0,
1844 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1845 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1846 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1848 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1850 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1851 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1852 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1853 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1854 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1856 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1858 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1860 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1862 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1864 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1866 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1868 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1870 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1872 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1874 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1876 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1878 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1880 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1881 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1882 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1884 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1886 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1888 0xf2a00950, 0xfea00fd0,
1889 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1891 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1893 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1895 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1897 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1899 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1901 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1902 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1903 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1905 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1907 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1908 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1909 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1911 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1913 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1915 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1916 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1917 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1919 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1920 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1921 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1922 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1923 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1925 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1926 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1927 0xf2a00e10, 0xfea00e90,
1928 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1929 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1930 0xf2a00c10, 0xfea00e90,
1931 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1933 /* Three registers of different lengths. */
1934 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1935 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1937 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1938 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1939 0xf2800400, 0xff800f50,
1940 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1942 0xf2800600, 0xff800f50,
1943 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1945 0xf2800900, 0xff800f50,
1946 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1948 0xf2800b00, 0xff800f50,
1949 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1951 0xf2800d00, 0xff800f50,
1952 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1954 0xf3800400, 0xff800f50,
1955 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1956 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1957 0xf3800600, 0xff800f50,
1958 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1959 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1960 0xf2800000, 0xfe800f50,
1961 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1962 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1963 0xf2800100, 0xfe800f50,
1964 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1965 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1966 0xf2800200, 0xfe800f50,
1967 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1969 0xf2800300, 0xfe800f50,
1970 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1971 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1972 0xf2800500, 0xfe800f50,
1973 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1974 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1975 0xf2800700, 0xfe800f50,
1976 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1977 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1978 0xf2800800, 0xfe800f50,
1979 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1980 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1981 0xf2800a00, 0xfe800f50,
1982 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1984 0xf2800c00, 0xfe800f50,
1985 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1987 /* Two registers and a scalar. */
1988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1989 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1991 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1992 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1993 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1995 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1997 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1999 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2000 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2001 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
2002 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2003 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2004 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2005 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2006 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2007 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2008 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2009 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
2010 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2011 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2013 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2014 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2015 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2016 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2017 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2018 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2019 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2020 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2021 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2022 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2023 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2025 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2026 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2027 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2028 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2029 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2030 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2031 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2032 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2033 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2034 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2035 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2036 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2037 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2038 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2039 0xf2800240, 0xfe800f50,
2040 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2042 0xf2800640, 0xfe800f50,
2043 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2044 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2045 0xf2800a40, 0xfe800f50,
2046 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2048 0xf2800e40, 0xff800f50,
2049 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2050 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2051 0xf2800f40, 0xff800f50,
2052 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2053 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2054 0xf3800e40, 0xff800f50,
2055 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2056 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2057 0xf3800f40, 0xff800f50,
2058 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2061 /* Element and structure load/store. */
2062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2063 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2065 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2066 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2067 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2069 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2071 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2073 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2075 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2077 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2079 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2081 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2083 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2085 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2087 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2089 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2091 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2093 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2094 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2095 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2097 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2099 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2101 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
2104 /* mve opcode table. */
2106 /* print_insn_mve recognizes the following format control codes:
2110 %a print '+' or '-' or imm offset in vldr[bhwd] and
2112 %c print condition code
2113 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2114 %u print 'U' (unsigned) or 'S' for various mve instructions
2115 %i print MVE predicate(s) for vpt and vpst
2116 %j print a 5-bit immediate from hw2[14:12,7:6]
2117 %k print 48 if the 7th position bit is set else print 64.
2118 %m print rounding mode for vcvt and vrint
2119 %n print vector comparison code for predicated instruction
2120 %s print size for various vcvt instructions
2121 %v print vector predicate for instruction in predicated
2123 %o print offset scaled for vldr[hwd] and vstr[hwd]
2124 %w print writeback mode for MVE v{st,ld}[24]
2125 %B print v{st,ld}[24] any one operands
2126 %E print vmov, vmvn, vorr, vbic encoded constant
2127 %N print generic index for vmov
2128 %T print bottom ('b') or top ('t') of source register
2129 %X print exchange field in vmla* instructions
2131 %<bitfield>r print as an ARM register
2132 %<bitfield>d print the bitfield in decimal
2133 %<bitfield>A print accumulate or not
2134 %<bitfield>c print bitfield as a condition code
2135 %<bitfield>C print bitfield as an inverted condition code
2136 %<bitfield>Q print as a MVE Q register
2137 %<bitfield>F print as a MVE S register
2138 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2141 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
2142 %<bitfield>s print size for vector predicate & non VMOV instructions
2143 %<bitfield>I print carry flag or not
2144 %<bitfield>i print immediate for vstr/vldr reg +/- imm
2145 %<bitfield>h print high half of 64-bit destination reg
2146 %<bitfield>k print immediate for vector conversion instruction
2147 %<bitfield>l print low half of 64-bit destination reg
2148 %<bitfield>o print rotate value for vcmul
2149 %<bitfield>u print immediate value for vddup/vdwdup
2150 %<bitfield>x print the bitfield in hex.
2153 static const struct mopcode32 mve_opcodes
[] =
2157 {ARM_FEATURE_COPROC (FPU_MVE
),
2159 0xfe310f4d, 0xffbf1fff,
2163 /* Floating point VPT T1. */
2164 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2166 0xee310f00, 0xefb10f50,
2167 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2168 /* Floating point VPT T2. */
2169 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2171 0xee310f40, 0xefb10f50,
2172 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2174 /* Vector VPT T1. */
2175 {ARM_FEATURE_COPROC (FPU_MVE
),
2177 0xfe010f00, 0xff811f51,
2178 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2179 /* Vector VPT T2. */
2180 {ARM_FEATURE_COPROC (FPU_MVE
),
2182 0xfe010f01, 0xff811f51,
2183 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2184 /* Vector VPT T3. */
2185 {ARM_FEATURE_COPROC (FPU_MVE
),
2187 0xfe011f00, 0xff811f50,
2188 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2189 /* Vector VPT T4. */
2190 {ARM_FEATURE_COPROC (FPU_MVE
),
2192 0xfe010f40, 0xff811f70,
2193 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2194 /* Vector VPT T5. */
2195 {ARM_FEATURE_COPROC (FPU_MVE
),
2197 0xfe010f60, 0xff811f70,
2198 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2199 /* Vector VPT T6. */
2200 {ARM_FEATURE_COPROC (FPU_MVE
),
2202 0xfe011f40, 0xff811f50,
2203 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2205 /* Vector VBIC immediate. */
2206 {ARM_FEATURE_COPROC (FPU_MVE
),
2208 0xef800070, 0xefb81070,
2209 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2211 /* Vector VBIC register. */
2212 {ARM_FEATURE_COPROC (FPU_MVE
),
2214 0xef100150, 0xffb11f51,
2215 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2218 {ARM_FEATURE_COPROC (FPU_MVE
),
2220 0xee800f01, 0xefc10f51,
2221 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2223 /* Vector VABD floating point. */
2224 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2226 0xff200d40, 0xffa11f51,
2227 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2230 {ARM_FEATURE_COPROC (FPU_MVE
),
2232 0xef000740, 0xef811f51,
2233 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2235 /* Vector VABS floating point. */
2236 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2238 0xFFB10740, 0xFFB31FD1,
2239 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2241 {ARM_FEATURE_COPROC (FPU_MVE
),
2243 0xffb10340, 0xffb31fd1,
2244 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2246 /* Vector VADD floating point T1. */
2247 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2249 0xef000d40, 0xffa11f51,
2250 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2251 /* Vector VADD floating point T2. */
2252 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2254 0xee300f40, 0xefb11f70,
2255 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2256 /* Vector VADD T1. */
2257 {ARM_FEATURE_COPROC (FPU_MVE
),
2259 0xef000840, 0xff811f51,
2260 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2261 /* Vector VADD T2. */
2262 {ARM_FEATURE_COPROC (FPU_MVE
),
2264 0xee010f40, 0xff811f70,
2265 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2267 /* Vector VADDLV. */
2268 {ARM_FEATURE_COPROC (FPU_MVE
),
2270 0xee890f00, 0xef8f1fd1,
2271 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2274 {ARM_FEATURE_COPROC (FPU_MVE
),
2276 0xeef10f00, 0xeff31fd1,
2277 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2280 {ARM_FEATURE_COPROC (FPU_MVE
),
2282 0xee300f00, 0xffb10f51,
2283 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2286 {ARM_FEATURE_COPROC (FPU_MVE
),
2288 0xef000150, 0xffb11f51,
2289 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2291 /* Vector VBRSR register. */
2292 {ARM_FEATURE_COPROC (FPU_MVE
),
2294 0xfe011e60, 0xff811f70,
2295 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2297 /* Vector VCADD floating point. */
2298 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2300 0xfc800840, 0xfea11f51,
2301 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2304 {ARM_FEATURE_COPROC (FPU_MVE
),
2306 0xfe000f00, 0xff810f51,
2307 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2310 {ARM_FEATURE_COPROC (FPU_MVE
),
2312 0xffb00440, 0xffb31fd1,
2313 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2316 {ARM_FEATURE_COPROC (FPU_MVE
),
2318 0xffb004c0, 0xffb31fd1,
2319 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2322 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2324 0xfc200840, 0xfe211f51,
2325 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2327 /* Vector VCMP floating point T1. */
2328 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2330 0xee310f00, 0xeff1ef50,
2331 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2333 /* Vector VCMP floating point T2. */
2334 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2336 0xee310f40, 0xeff1ef50,
2337 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2339 /* Vector VCMP T1. */
2340 {ARM_FEATURE_COPROC (FPU_MVE
),
2342 0xfe010f00, 0xffc1ff51,
2343 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2344 /* Vector VCMP T2. */
2345 {ARM_FEATURE_COPROC (FPU_MVE
),
2347 0xfe010f01, 0xffc1ff51,
2348 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2349 /* Vector VCMP T3. */
2350 {ARM_FEATURE_COPROC (FPU_MVE
),
2352 0xfe011f00, 0xffc1ff50,
2353 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2354 /* Vector VCMP T4. */
2355 {ARM_FEATURE_COPROC (FPU_MVE
),
2357 0xfe010f40, 0xffc1ff70,
2358 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2359 /* Vector VCMP T5. */
2360 {ARM_FEATURE_COPROC (FPU_MVE
),
2362 0xfe010f60, 0xffc1ff70,
2363 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2364 /* Vector VCMP T6. */
2365 {ARM_FEATURE_COPROC (FPU_MVE
),
2367 0xfe011f40, 0xffc1ff50,
2368 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2371 {ARM_FEATURE_COPROC (FPU_MVE
),
2373 0xeea00b10, 0xffb10f5f,
2374 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2377 {ARM_FEATURE_COPROC (FPU_MVE
),
2379 0xff000150, 0xffd11f51,
2380 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2382 /* Vector VFMA, vector * scalar. */
2383 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2385 0xee310e40, 0xefb11f70,
2386 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2388 /* Vector VFMA floating point. */
2389 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2391 0xef000c50, 0xffa11f51,
2392 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2394 /* Vector VFMS floating point. */
2395 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2397 0xef200c50, 0xffa11f51,
2398 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2400 /* Vector VFMAS, vector * scalar. */
2401 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2402 MVE_VFMAS_FP_SCALAR
,
2403 0xee311e40, 0xefb11f70,
2404 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2406 /* Vector VHADD T1. */
2407 {ARM_FEATURE_COPROC (FPU_MVE
),
2409 0xef000040, 0xef811f51,
2410 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2412 /* Vector VHADD T2. */
2413 {ARM_FEATURE_COPROC (FPU_MVE
),
2415 0xee000f40, 0xef811f70,
2416 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2418 /* Vector VHSUB T1. */
2419 {ARM_FEATURE_COPROC (FPU_MVE
),
2421 0xef000240, 0xef811f51,
2422 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2424 /* Vector VHSUB T2. */
2425 {ARM_FEATURE_COPROC (FPU_MVE
),
2427 0xee001f40, 0xef811f70,
2428 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2431 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2433 0xee300e00, 0xefb10f50,
2434 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2437 {ARM_FEATURE_COPROC (FPU_MVE
),
2439 0xf000e801, 0xffc0ffff,
2440 "vctp%v.%20-21s\t%16-19r"},
2443 {ARM_FEATURE_COPROC (FPU_MVE
),
2445 0xeea00b10, 0xffb10f5f,
2446 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2448 /* Vector VRHADD. */
2449 {ARM_FEATURE_COPROC (FPU_MVE
),
2451 0xef000140, 0xef811f51,
2452 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2455 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2456 MVE_VCVT_FP_FIX_VEC
,
2457 0xef800c50, 0xef801cd1,
2458 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2461 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2462 MVE_VCVT_BETWEEN_FP_INT
,
2463 0xffb30640, 0xffb31e51,
2464 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2466 /* Vector VCVT between single and half-precision float, bottom half. */
2467 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2468 MVE_VCVT_FP_HALF_FP
,
2469 0xee3f0e01, 0xefbf1fd1,
2470 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2472 /* Vector VCVT between single and half-precision float, top half. */
2473 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2474 MVE_VCVT_FP_HALF_FP
,
2475 0xee3f1e01, 0xefbf1fd1,
2476 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2479 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2480 MVE_VCVT_FROM_FP_TO_INT
,
2481 0xffb30040, 0xffb31c51,
2482 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2485 {ARM_FEATURE_COPROC (FPU_MVE
),
2487 0xee011f6e, 0xff811f7e,
2488 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2490 /* Vector VDWDUP. */
2491 {ARM_FEATURE_COPROC (FPU_MVE
),
2493 0xee011f60, 0xff811f70,
2494 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2496 /* Vector VHCADD. */
2497 {ARM_FEATURE_COPROC (FPU_MVE
),
2499 0xee000f00, 0xff810f51,
2500 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2502 /* Vector VIWDUP. */
2503 {ARM_FEATURE_COPROC (FPU_MVE
),
2505 0xee010f60, 0xff811f70,
2506 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2509 {ARM_FEATURE_COPROC (FPU_MVE
),
2511 0xee010f6e, 0xff811f7e,
2512 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2515 {ARM_FEATURE_COPROC (FPU_MVE
),
2517 0xfc901e00, 0xff901e5f,
2518 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2521 {ARM_FEATURE_COPROC (FPU_MVE
),
2523 0xfc901e01, 0xff901e1f,
2524 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2526 /* Vector VLDRB gather load. */
2527 {ARM_FEATURE_COPROC (FPU_MVE
),
2528 MVE_VLDRB_GATHER_T1
,
2529 0xec900e00, 0xefb01e50,
2530 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2532 /* Vector VLDRH gather load. */
2533 {ARM_FEATURE_COPROC (FPU_MVE
),
2534 MVE_VLDRH_GATHER_T2
,
2535 0xec900e10, 0xefb01e50,
2536 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2538 /* Vector VLDRW gather load. */
2539 {ARM_FEATURE_COPROC (FPU_MVE
),
2540 MVE_VLDRW_GATHER_T3
,
2541 0xfc900f40, 0xffb01fd0,
2542 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2544 /* Vector VLDRD gather load. */
2545 {ARM_FEATURE_COPROC (FPU_MVE
),
2546 MVE_VLDRD_GATHER_T4
,
2547 0xec900fd0, 0xefb01fd0,
2548 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2550 /* Vector VLDRW gather load. */
2551 {ARM_FEATURE_COPROC (FPU_MVE
),
2552 MVE_VLDRW_GATHER_T5
,
2553 0xfd101e00, 0xff111f00,
2554 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2556 /* Vector VLDRD gather load, variant T6. */
2557 {ARM_FEATURE_COPROC (FPU_MVE
),
2558 MVE_VLDRD_GATHER_T6
,
2559 0xfd101f00, 0xff111f00,
2560 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2563 {ARM_FEATURE_COPROC (FPU_MVE
),
2565 0xec100e00, 0xee581e00,
2566 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2569 {ARM_FEATURE_COPROC (FPU_MVE
),
2571 0xec180e00, 0xee581e00,
2572 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2574 /* Vector VLDRB unsigned, variant T5. */
2575 {ARM_FEATURE_COPROC (FPU_MVE
),
2577 0xec101e00, 0xfe101f80,
2578 "vldrb%v.u8\t%13-15,22Q, %d"},
2580 /* Vector VLDRH unsigned, variant T6. */
2581 {ARM_FEATURE_COPROC (FPU_MVE
),
2583 0xec101e80, 0xfe101f80,
2584 "vldrh%v.u16\t%13-15,22Q, %d"},
2586 /* Vector VLDRW unsigned, variant T7. */
2587 {ARM_FEATURE_COPROC (FPU_MVE
),
2589 0xec101f00, 0xfe101f80,
2590 "vldrw%v.u32\t%13-15,22Q, %d"},
2593 {ARM_FEATURE_COPROC (FPU_MVE
),
2595 0xef000640, 0xef811f51,
2596 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2599 {ARM_FEATURE_COPROC (FPU_MVE
),
2601 0xee330e81, 0xffb31fd1,
2602 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2604 /* Vector VMAXNM floating point. */
2605 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2607 0xff000f50, 0xffa11f51,
2608 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2610 /* Vector VMAXNMA floating point. */
2611 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2613 0xee3f0e81, 0xefbf1fd1,
2614 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2616 /* Vector VMAXNMV floating point. */
2617 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2619 0xeeee0f00, 0xefff0fd1,
2620 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2622 /* Vector VMAXNMAV floating point. */
2623 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2625 0xeeec0f00, 0xefff0fd1,
2626 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2629 {ARM_FEATURE_COPROC (FPU_MVE
),
2631 0xeee20f00, 0xeff30fd1,
2632 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2634 /* Vector VMAXAV. */
2635 {ARM_FEATURE_COPROC (FPU_MVE
),
2637 0xeee00f00, 0xfff30fd1,
2638 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2641 {ARM_FEATURE_COPROC (FPU_MVE
),
2643 0xef000650, 0xef811f51,
2644 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2647 {ARM_FEATURE_COPROC (FPU_MVE
),
2649 0xee331e81, 0xffb31fd1,
2650 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2652 /* Vector VMINNM floating point. */
2653 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2655 0xff200f50, 0xffa11f51,
2656 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2658 /* Vector VMINNMA floating point. */
2659 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2661 0xee3f1e81, 0xefbf1fd1,
2662 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2664 /* Vector VMINNMV floating point. */
2665 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2667 0xeeee0f80, 0xefff0fd1,
2668 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2670 /* Vector VMINNMAV floating point. */
2671 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2673 0xeeec0f80, 0xefff0fd1,
2674 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2677 {ARM_FEATURE_COPROC (FPU_MVE
),
2679 0xeee20f80, 0xeff30fd1,
2680 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2682 /* Vector VMINAV. */
2683 {ARM_FEATURE_COPROC (FPU_MVE
),
2685 0xeee00f80, 0xfff30fd1,
2686 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2689 {ARM_FEATURE_COPROC (FPU_MVE
),
2691 0xee010e40, 0xef811f70,
2692 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2694 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2696 {ARM_FEATURE_COPROC (FPU_MVE
),
2698 0xee801e00, 0xef801f51,
2699 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2701 {ARM_FEATURE_COPROC (FPU_MVE
),
2703 0xee800e00, 0xef801f51,
2704 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2706 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2707 {ARM_FEATURE_COPROC (FPU_MVE
),
2709 0xeef00e00, 0xeff01f51,
2710 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2712 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2713 {ARM_FEATURE_COPROC (FPU_MVE
),
2715 0xeef00f00, 0xeff11f51,
2716 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2718 /* Vector VMLADAV T1 variant. */
2719 {ARM_FEATURE_COPROC (FPU_MVE
),
2721 0xeef01e00, 0xeff01f51,
2722 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2724 /* Vector VMLADAV T2 variant. */
2725 {ARM_FEATURE_COPROC (FPU_MVE
),
2727 0xeef01f00, 0xeff11f51,
2728 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2731 {ARM_FEATURE_COPROC (FPU_MVE
),
2733 0xee011e40, 0xef811f70,
2734 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2736 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2738 {ARM_FEATURE_COPROC (FPU_MVE
),
2740 0xfe800e01, 0xff810f51,
2741 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2743 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2745 {ARM_FEATURE_COPROC (FPU_MVE
),
2747 0xee800e01, 0xff800f51,
2748 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2750 /* Vector VMLSDAV T1 Variant. */
2751 {ARM_FEATURE_COPROC (FPU_MVE
),
2753 0xeef00e01, 0xfff00f51,
2754 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2756 /* Vector VMLSDAV T2 Variant. */
2757 {ARM_FEATURE_COPROC (FPU_MVE
),
2759 0xfef00e01, 0xfff10f51,
2760 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2762 /* Vector VMOV between gpr and half precision register, op == 0. */
2763 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2765 0xee000910, 0xfff00f7f,
2766 "vmov.f16\t%7,16-19F, %12-15r"},
2768 /* Vector VMOV between gpr and half precision register, op == 1. */
2769 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2771 0xee100910, 0xfff00f7f,
2772 "vmov.f16\t%12-15r, %7,16-19F"},
2774 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2775 MVE_VMOV_GP_TO_VEC_LANE
,
2776 0xee000b10, 0xff900f1f,
2777 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2779 /* Vector VORR immediate to vector.
2780 NOTE: MVE_VORR_IMM must appear in the table
2781 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2782 {ARM_FEATURE_COPROC (FPU_MVE
),
2784 0xef800050, 0xefb810f0,
2785 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2787 /* Vector VQSHL T2 Variant.
2788 NOTE: MVE_VQSHL_T2 must appear in the table before
2789 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2790 {ARM_FEATURE_COPROC (FPU_MVE
),
2792 0xef800750, 0xef801fd1,
2793 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2795 /* Vector VQSHLU T3 Variant
2796 NOTE: MVE_VQSHL_T2 must appear in the table before
2797 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2799 {ARM_FEATURE_COPROC (FPU_MVE
),
2801 0xff800650, 0xff801fd1,
2802 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2805 NOTE: MVE_VRSHR must appear in the table before
2806 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2807 {ARM_FEATURE_COPROC (FPU_MVE
),
2809 0xef800250, 0xef801fd1,
2810 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2813 NOTE: MVE_VSHL must appear in the table before
2814 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2815 {ARM_FEATURE_COPROC (FPU_MVE
),
2817 0xef800550, 0xff801fd1,
2818 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2821 NOTE: MVE_VSHR must appear in the table before
2822 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2823 {ARM_FEATURE_COPROC (FPU_MVE
),
2825 0xef800050, 0xef801fd1,
2826 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2829 NOTE: MVE_VSLI must appear in the table before
2830 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2831 {ARM_FEATURE_COPROC (FPU_MVE
),
2833 0xff800550, 0xff801fd1,
2834 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2837 NOTE: MVE_VSRI must appear in the table before
2838 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2839 {ARM_FEATURE_COPROC (FPU_MVE
),
2841 0xff800450, 0xff801fd1,
2842 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2844 /* Vector VMOV immediate to vector,
2845 cmode == 11x1 -> VMVN which is UNDEFINED
2846 for such a cmode. */
2847 {ARM_FEATURE_COPROC (FPU_MVE
),
2848 MVE_VMVN_IMM
, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION
},
2850 /* Vector VMOV immediate to vector. */
2851 {ARM_FEATURE_COPROC (FPU_MVE
),
2852 MVE_VMOV_IMM_TO_VEC
,
2853 0xef800050, 0xefb810d0,
2854 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2856 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2857 {ARM_FEATURE_COPROC (FPU_MVE
),
2858 MVE_VMOV2_VEC_LANE_TO_GP
,
2859 0xec000f00, 0xffb01ff0,
2860 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2862 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2863 {ARM_FEATURE_COPROC (FPU_MVE
),
2864 MVE_VMOV2_VEC_LANE_TO_GP
,
2865 0xec000f10, 0xffb01ff0,
2866 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2868 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2869 {ARM_FEATURE_COPROC (FPU_MVE
),
2870 MVE_VMOV2_GP_TO_VEC_LANE
,
2871 0xec100f00, 0xffb01ff0,
2872 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2874 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2875 {ARM_FEATURE_COPROC (FPU_MVE
),
2876 MVE_VMOV2_GP_TO_VEC_LANE
,
2877 0xec100f10, 0xffb01ff0,
2878 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2880 /* Vector VMOV Vector lane to gpr. */
2881 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2882 MVE_VMOV_VEC_LANE_TO_GP
,
2883 0xee100b10, 0xff100f1f,
2884 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2886 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2887 to instruction opcode aliasing. */
2888 {ARM_FEATURE_COPROC (FPU_MVE
),
2890 0xeea00f40, 0xefa00fd1,
2891 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2893 /* Vector VMOVL long. */
2894 {ARM_FEATURE_COPROC (FPU_MVE
),
2896 0xeea00f40, 0xefa70fd1,
2897 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2899 /* Vector VMOV and narrow. */
2900 {ARM_FEATURE_COPROC (FPU_MVE
),
2902 0xfe310e81, 0xffb30fd1,
2903 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2905 /* Floating point move extract. */
2906 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2908 0xfeb00a40, 0xffbf0fd0,
2909 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2911 /* Vector VMUL floating-point T1 variant. */
2912 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2914 0xff000d50, 0xffa11f51,
2915 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2917 /* Vector VMUL floating-point T2 variant. */
2918 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2920 0xee310e60, 0xefb11f70,
2921 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2923 /* Vector VMUL T1 variant. */
2924 {ARM_FEATURE_COPROC (FPU_MVE
),
2926 0xef000950, 0xff811f51,
2927 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2929 /* Vector VMUL T2 variant. */
2930 {ARM_FEATURE_COPROC (FPU_MVE
),
2932 0xee011e60, 0xff811f70,
2933 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2936 {ARM_FEATURE_COPROC (FPU_MVE
),
2938 0xee010e01, 0xef811f51,
2939 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2941 /* Vector VRMULH. */
2942 {ARM_FEATURE_COPROC (FPU_MVE
),
2944 0xee011e01, 0xef811f51,
2945 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2947 /* Vector VMULL integer. */
2948 {ARM_FEATURE_COPROC (FPU_MVE
),
2950 0xee010e00, 0xef810f51,
2951 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2953 /* Vector VMULL polynomial. */
2954 {ARM_FEATURE_COPROC (FPU_MVE
),
2956 0xee310e00, 0xefb10f51,
2957 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2959 /* Vector VMVN immediate to vector. */
2960 {ARM_FEATURE_COPROC (FPU_MVE
),
2962 0xef800070, 0xefb810f0,
2963 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2965 /* Vector VMVN register. */
2966 {ARM_FEATURE_COPROC (FPU_MVE
),
2968 0xffb005c0, 0xffbf1fd1,
2969 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2971 /* Vector VNEG floating point. */
2972 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2974 0xffb107c0, 0xffb31fd1,
2975 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2978 {ARM_FEATURE_COPROC (FPU_MVE
),
2980 0xffb103c0, 0xffb31fd1,
2981 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2983 /* Vector VORN, vector bitwise or not. */
2984 {ARM_FEATURE_COPROC (FPU_MVE
),
2986 0xef300150, 0xffb11f51,
2987 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2989 /* Vector VORR register. */
2990 {ARM_FEATURE_COPROC (FPU_MVE
),
2992 0xef200150, 0xffb11f51,
2993 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2995 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
2996 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
2997 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
3000 {ARM_FEATURE_COPROC (FPU_MVE
),
3001 MVE_VMOV_VEC_TO_VEC
,
3002 0xef200150, 0xffb11f51,
3003 "vmov%v\t%13-15,22Q, %17-19,7Q"},
3005 /* Vector VQDMULL T1 variant. */
3006 {ARM_FEATURE_COPROC (FPU_MVE
),
3008 0xee300f01, 0xefb10f51,
3009 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3012 {ARM_FEATURE_COPROC (FPU_MVE
),
3014 0xfe310f4d, 0xffffffff,
3018 {ARM_FEATURE_COPROC (FPU_MVE
),
3020 0xfe310f01, 0xffb11f51,
3021 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3024 {ARM_FEATURE_COPROC (FPU_MVE
),
3026 0xffb00740, 0xffb31fd1,
3027 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3029 /* Vector VQADD T1 variant. */
3030 {ARM_FEATURE_COPROC (FPU_MVE
),
3032 0xef000050, 0xef811f51,
3033 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3035 /* Vector VQADD T2 variant. */
3036 {ARM_FEATURE_COPROC (FPU_MVE
),
3038 0xee000f60, 0xef811f70,
3039 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3041 /* Vector VQDMULL T2 variant. */
3042 {ARM_FEATURE_COPROC (FPU_MVE
),
3044 0xee300f60, 0xefb10f70,
3045 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3047 /* Vector VQMOVN. */
3048 {ARM_FEATURE_COPROC (FPU_MVE
),
3050 0xee330e01, 0xefb30fd1,
3051 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3053 /* Vector VQMOVUN. */
3054 {ARM_FEATURE_COPROC (FPU_MVE
),
3056 0xee310e81, 0xffb30fd1,
3057 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3059 /* Vector VQDMLADH. */
3060 {ARM_FEATURE_COPROC (FPU_MVE
),
3062 0xee000e00, 0xff810f51,
3063 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3065 /* Vector VQRDMLADH. */
3066 {ARM_FEATURE_COPROC (FPU_MVE
),
3068 0xee000e01, 0xff810f51,
3069 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3071 /* Vector VQDMLAH. */
3072 {ARM_FEATURE_COPROC (FPU_MVE
),
3074 0xee000e60, 0xff811f70,
3075 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3077 /* Vector VQRDMLAH. */
3078 {ARM_FEATURE_COPROC (FPU_MVE
),
3080 0xee000e40, 0xff811f70,
3081 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3083 /* Vector VQDMLASH. */
3084 {ARM_FEATURE_COPROC (FPU_MVE
),
3086 0xee001e60, 0xff811f70,
3087 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3089 /* Vector VQRDMLASH. */
3090 {ARM_FEATURE_COPROC (FPU_MVE
),
3092 0xee001e40, 0xff811f70,
3093 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3095 /* Vector VQDMLSDH. */
3096 {ARM_FEATURE_COPROC (FPU_MVE
),
3098 0xfe000e00, 0xff810f51,
3099 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3101 /* Vector VQRDMLSDH. */
3102 {ARM_FEATURE_COPROC (FPU_MVE
),
3104 0xfe000e01, 0xff810f51,
3105 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3107 /* Vector VQDMULH T1 variant. */
3108 {ARM_FEATURE_COPROC (FPU_MVE
),
3110 0xef000b40, 0xff811f51,
3111 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3113 /* Vector VQRDMULH T2 variant. */
3114 {ARM_FEATURE_COPROC (FPU_MVE
),
3116 0xff000b40, 0xff811f51,
3117 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3119 /* Vector VQDMULH T3 variant. */
3120 {ARM_FEATURE_COPROC (FPU_MVE
),
3122 0xee010e60, 0xff811f70,
3123 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3125 /* Vector VQRDMULH T4 variant. */
3126 {ARM_FEATURE_COPROC (FPU_MVE
),
3128 0xfe010e60, 0xff811f70,
3129 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3132 {ARM_FEATURE_COPROC (FPU_MVE
),
3134 0xffb007c0, 0xffb31fd1,
3135 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3137 /* Vector VQRSHL T1 variant. */
3138 {ARM_FEATURE_COPROC (FPU_MVE
),
3140 0xef000550, 0xef811f51,
3141 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3143 /* Vector VQRSHL T2 variant. */
3144 {ARM_FEATURE_COPROC (FPU_MVE
),
3146 0xee331ee0, 0xefb31ff0,
3147 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3149 /* Vector VQRSHRN. */
3150 {ARM_FEATURE_COPROC (FPU_MVE
),
3152 0xee800f41, 0xefa00fd1,
3153 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3155 /* Vector VQRSHRUN. */
3156 {ARM_FEATURE_COPROC (FPU_MVE
),
3158 0xfe800fc0, 0xffa00fd1,
3159 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3161 /* Vector VQSHL T1 Variant. */
3162 {ARM_FEATURE_COPROC (FPU_MVE
),
3164 0xee311ee0, 0xefb31ff0,
3165 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3167 /* Vector VQSHL T4 Variant. */
3168 {ARM_FEATURE_COPROC (FPU_MVE
),
3170 0xef000450, 0xef811f51,
3171 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3173 /* Vector VQSHRN. */
3174 {ARM_FEATURE_COPROC (FPU_MVE
),
3176 0xee800f40, 0xefa00fd1,
3177 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3179 /* Vector VQSHRUN. */
3180 {ARM_FEATURE_COPROC (FPU_MVE
),
3182 0xee800fc0, 0xffa00fd1,
3183 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3185 /* Vector VQSUB T1 Variant. */
3186 {ARM_FEATURE_COPROC (FPU_MVE
),
3188 0xef000250, 0xef811f51,
3189 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3191 /* Vector VQSUB T2 Variant. */
3192 {ARM_FEATURE_COPROC (FPU_MVE
),
3194 0xee001f60, 0xef811f70,
3195 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3197 /* Vector VREV16. */
3198 {ARM_FEATURE_COPROC (FPU_MVE
),
3200 0xffb00140, 0xffb31fd1,
3201 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3203 /* Vector VREV32. */
3204 {ARM_FEATURE_COPROC (FPU_MVE
),
3206 0xffb000c0, 0xffb31fd1,
3207 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3209 /* Vector VREV64. */
3210 {ARM_FEATURE_COPROC (FPU_MVE
),
3212 0xffb00040, 0xffb31fd1,
3213 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3215 /* Vector VRINT floating point. */
3216 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
3218 0xffb20440, 0xffb31c51,
3219 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3221 /* Vector VRMLALDAVH. */
3222 {ARM_FEATURE_COPROC (FPU_MVE
),
3224 0xee800f00, 0xef811f51,
3225 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3227 /* Vector VRMLALDAVH. */
3228 {ARM_FEATURE_COPROC (FPU_MVE
),
3230 0xee801f00, 0xef811f51,
3231 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3233 /* Vector VRSHL T1 Variant. */
3234 {ARM_FEATURE_COPROC (FPU_MVE
),
3236 0xef000540, 0xef811f51,
3237 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3239 /* Vector VRSHL T2 Variant. */
3240 {ARM_FEATURE_COPROC (FPU_MVE
),
3242 0xee331e60, 0xefb31ff0,
3243 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3245 /* Vector VRSHRN. */
3246 {ARM_FEATURE_COPROC (FPU_MVE
),
3248 0xfe800fc1, 0xffa00fd1,
3249 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3252 {ARM_FEATURE_COPROC (FPU_MVE
),
3254 0xfe300f00, 0xffb10f51,
3255 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3257 /* Vector VSHL T2 Variant. */
3258 {ARM_FEATURE_COPROC (FPU_MVE
),
3260 0xee311e60, 0xefb31ff0,
3261 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3263 /* Vector VSHL T3 Variant. */
3264 {ARM_FEATURE_COPROC (FPU_MVE
),
3266 0xef000440, 0xef811f51,
3267 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3270 {ARM_FEATURE_COPROC (FPU_MVE
),
3272 0xeea00fc0, 0xffa01ff0,
3273 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3275 /* Vector VSHLL T2 Variant. */
3276 {ARM_FEATURE_COPROC (FPU_MVE
),
3278 0xee310e01, 0xefb30fd1,
3279 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3282 {ARM_FEATURE_COPROC (FPU_MVE
),
3284 0xee800fc1, 0xffa00fd1,
3285 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3287 /* Vector VST2 no writeback. */
3288 {ARM_FEATURE_COPROC (FPU_MVE
),
3290 0xfc801e00, 0xffb01e5f,
3291 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3293 /* Vector VST2 writeback. */
3294 {ARM_FEATURE_COPROC (FPU_MVE
),
3296 0xfca01e00, 0xffb01e5f,
3297 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3299 /* Vector VST4 no writeback. */
3300 {ARM_FEATURE_COPROC (FPU_MVE
),
3302 0xfc801e01, 0xffb01e1f,
3303 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3305 /* Vector VST4 writeback. */
3306 {ARM_FEATURE_COPROC (FPU_MVE
),
3308 0xfca01e01, 0xffb01e1f,
3309 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3311 /* Vector VSTRB scatter store, T1 variant. */
3312 {ARM_FEATURE_COPROC (FPU_MVE
),
3313 MVE_VSTRB_SCATTER_T1
,
3314 0xec800e00, 0xffb01e50,
3315 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3317 /* Vector VSTRH scatter store, T2 variant. */
3318 {ARM_FEATURE_COPROC (FPU_MVE
),
3319 MVE_VSTRH_SCATTER_T2
,
3320 0xec800e10, 0xffb01e50,
3321 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3323 /* Vector VSTRW scatter store, T3 variant. */
3324 {ARM_FEATURE_COPROC (FPU_MVE
),
3325 MVE_VSTRW_SCATTER_T3
,
3326 0xec800e40, 0xffb01e50,
3327 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3329 /* Vector VSTRD scatter store, T4 variant. */
3330 {ARM_FEATURE_COPROC (FPU_MVE
),
3331 MVE_VSTRD_SCATTER_T4
,
3332 0xec800fd0, 0xffb01fd0,
3333 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3335 /* Vector VSTRW scatter store, T5 variant. */
3336 {ARM_FEATURE_COPROC (FPU_MVE
),
3337 MVE_VSTRW_SCATTER_T5
,
3338 0xfd001e00, 0xff111f00,
3339 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3341 /* Vector VSTRD scatter store, T6 variant. */
3342 {ARM_FEATURE_COPROC (FPU_MVE
),
3343 MVE_VSTRD_SCATTER_T6
,
3344 0xfd001f00, 0xff111f00,
3345 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3348 {ARM_FEATURE_COPROC (FPU_MVE
),
3350 0xec000e00, 0xfe581e00,
3351 "vstrb%v.%7-8s\t%13-15Q, %d"},
3354 {ARM_FEATURE_COPROC (FPU_MVE
),
3356 0xec080e00, 0xfe581e00,
3357 "vstrh%v.%7-8s\t%13-15Q, %d"},
3359 /* Vector VSTRB variant T5. */
3360 {ARM_FEATURE_COPROC (FPU_MVE
),
3362 0xec001e00, 0xfe101f80,
3363 "vstrb%v.8\t%13-15,22Q, %d"},
3365 /* Vector VSTRH variant T6. */
3366 {ARM_FEATURE_COPROC (FPU_MVE
),
3368 0xec001e80, 0xfe101f80,
3369 "vstrh%v.16\t%13-15,22Q, %d"},
3371 /* Vector VSTRW variant T7. */
3372 {ARM_FEATURE_COPROC (FPU_MVE
),
3374 0xec001f00, 0xfe101f80,
3375 "vstrw%v.32\t%13-15,22Q, %d"},
3377 /* Vector VSUB floating point T1 variant. */
3378 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
3380 0xef200d40, 0xffa11f51,
3381 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3383 /* Vector VSUB floating point T2 variant. */
3384 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
3386 0xee301f40, 0xefb11f70,
3387 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3389 /* Vector VSUB T1 variant. */
3390 {ARM_FEATURE_COPROC (FPU_MVE
),
3392 0xff000840, 0xff811f51,
3393 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3395 /* Vector VSUB T2 variant. */
3396 {ARM_FEATURE_COPROC (FPU_MVE
),
3398 0xee011f40, 0xff811f70,
3399 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3401 {ARM_FEATURE_COPROC (FPU_MVE
),
3403 0xea50012f, 0xfff1813f,
3404 "asrl%c\t%17-19l, %9-11h, %j"},
3406 {ARM_FEATURE_COPROC (FPU_MVE
),
3408 0xea50012d, 0xfff101ff,
3409 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3411 {ARM_FEATURE_COPROC (FPU_MVE
),
3413 0xea50010f, 0xfff1813f,
3414 "lsll%c\t%17-19l, %9-11h, %j"},
3416 {ARM_FEATURE_COPROC (FPU_MVE
),
3418 0xea50010d, 0xfff101ff,
3419 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3421 {ARM_FEATURE_COPROC (FPU_MVE
),
3423 0xea50011f, 0xfff1813f,
3424 "lsrl%c\t%17-19l, %9-11h, %j"},
3426 {ARM_FEATURE_COPROC (FPU_MVE
),
3428 0xea51012d, 0xfff1017f,
3429 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
3431 {ARM_FEATURE_COPROC (FPU_MVE
),
3433 0xea500f2d, 0xfff00fff,
3434 "sqrshr%c\t%16-19S, %12-15S"},
3436 {ARM_FEATURE_COPROC (FPU_MVE
),
3438 0xea51013f, 0xfff1813f,
3439 "sqshll%c\t%17-19l, %9-11h, %j"},
3441 {ARM_FEATURE_COPROC (FPU_MVE
),
3443 0xea500f3f, 0xfff08f3f,
3444 "sqshl%c\t%16-19S, %j"},
3446 {ARM_FEATURE_COPROC (FPU_MVE
),
3448 0xea51012f, 0xfff1813f,
3449 "srshrl%c\t%17-19l, %9-11h, %j"},
3451 {ARM_FEATURE_COPROC (FPU_MVE
),
3453 0xea500f2f, 0xfff08f3f,
3454 "srshr%c\t%16-19S, %j"},
3456 {ARM_FEATURE_COPROC (FPU_MVE
),
3458 0xea51010d, 0xfff1017f,
3459 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
3461 {ARM_FEATURE_COPROC (FPU_MVE
),
3463 0xea500f0d, 0xfff00fff,
3464 "uqrshl%c\t%16-19S, %12-15S"},
3466 {ARM_FEATURE_COPROC (FPU_MVE
),
3468 0xea51010f, 0xfff1813f,
3469 "uqshll%c\t%17-19l, %9-11h, %j"},
3471 {ARM_FEATURE_COPROC (FPU_MVE
),
3473 0xea500f0f, 0xfff08f3f,
3474 "uqshl%c\t%16-19S, %j"},
3476 {ARM_FEATURE_COPROC (FPU_MVE
),
3478 0xea51011f, 0xfff1813f,
3479 "urshrl%c\t%17-19l, %9-11h, %j"},
3481 {ARM_FEATURE_COPROC (FPU_MVE
),
3483 0xea500f1f, 0xfff08f3f,
3484 "urshr%c\t%16-19S, %j"},
3486 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3488 0xea509000, 0xfff0f000,
3489 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3491 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3493 0xea50a000, 0xfff0f000,
3494 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3496 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3498 0xea5f900f, 0xfffff00f,
3499 "cset\t%8-11S, %4-7C"},
3501 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3503 0xea5fa00f, 0xfffff00f,
3504 "csetm\t%8-11S, %4-7C"},
3506 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3508 0xea508000, 0xfff0f000,
3509 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3513 0xea50b000, 0xfff0f000,
3514 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3516 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3518 0xea509000, 0xfff0f000,
3519 "cinc\t%8-11S, %16-19Z, %4-7C"},
3521 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3523 0xea50a000, 0xfff0f000,
3524 "cinv\t%8-11S, %16-19Z, %4-7C"},
3526 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3528 0xea50b000, 0xfff0f000,
3529 "cneg\t%8-11S, %16-19Z, %4-7C"},
3531 {ARM_FEATURE_CORE_LOW (0),
3533 0x00000000, 0x00000000, 0}
3536 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3537 ordered: they must be searched linearly from the top to obtain a correct
3540 /* print_insn_arm recognizes the following format control codes:
3544 %a print address for ldr/str instruction
3545 %s print address for ldr/str halfword/signextend instruction
3546 %S like %s but allow UNPREDICTABLE addressing
3547 %b print branch destination
3548 %c print condition code (always bits 28-31)
3549 %m print register mask for ldm/stm instruction
3550 %o print operand2 (immediate or register + shift)
3551 %p print 'p' iff bits 12-15 are 15
3552 %t print 't' iff bit 21 set and bit 24 clear
3553 %B print arm BLX(1) destination
3554 %C print the PSR sub type.
3555 %U print barrier type.
3556 %P print address for pli instruction.
3558 %<bitfield>r print as an ARM register
3559 %<bitfield>T print as an ARM register + 1
3560 %<bitfield>R as %r but r15 is UNPREDICTABLE
3561 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3562 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3563 %<bitfield>d print the bitfield in decimal
3564 %<bitfield>W print the bitfield plus one in decimal
3565 %<bitfield>x print the bitfield in hex
3566 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
3568 %<bitfield>'c print specified char iff bitfield is all ones
3569 %<bitfield>`c print specified char iff bitfield is all zeroes
3570 %<bitfield>?ab... select from array of values in big endian order
3572 %e print arm SMI operand (bits 0..7,8..19).
3573 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
3574 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3575 %R print the SPSR/CPSR or banked register of an MRS. */
3577 static const struct opcode32 arm_opcodes
[] =
3579 /* ARM instructions. */
3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3581 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3583 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
),
3586 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
3588 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
3590 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
),
3592 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
3594 0x00800090, 0x0fa000f0,
3595 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
3597 0x00a00090, 0x0fa000f0,
3598 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3600 /* V8.2 RAS extension instructions. */
3601 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
3602 0xe320f010, 0xffffffff, "esb"},
3604 /* V8 instructions. */
3605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3606 0x0320f005, 0x0fffffff, "sevl"},
3607 /* Defined in V8 but is in NOP space so available to all arch. */
3608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3609 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
3610 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
),
3611 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3612 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3613 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3615 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3617 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3619 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3621 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3622 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3623 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3624 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3625 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3626 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3627 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3629 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3631 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3632 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3633 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3634 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3635 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3636 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3637 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3638 /* CRC32 instructions. */
3639 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3640 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3641 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3642 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3643 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3644 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3645 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3646 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3647 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3648 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3649 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3650 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3652 /* Privileged Access Never extension instructions. */
3653 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
3654 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3656 /* Virtualization Extension instructions. */
3657 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x0160006e, 0x0fffffff, "eret%c"},
3658 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3660 /* Integer Divide Extension instructions. */
3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3662 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3664 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3666 /* MP Extension instructions. */
3667 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3669 /* Speculation Barriers. */
3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xe320f014, 0xffffffff, "csdb"},
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff040, 0xffffffff, "ssbb"},
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff044, 0xffffffff, "pssbb"},
3674 /* V7 instructions. */
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf450f000, 0xfd70f000, "pli\t%P"},
3676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
3683 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3685 /* ARM V6T2 instructions. */
3686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3687 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3689 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3691 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3693 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3696 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
3697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3698 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3700 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3701 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3703 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3705 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3707 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3709 /* ARM Security extension instructions. */
3710 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
3711 0x01600070, 0x0ff000f0, "smc%c\t%e"},
3713 /* ARM V6K instructions. */
3714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3715 0xf57ff01f, 0xffffffff, "clrex"},
3716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3717 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3719 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3721 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3723 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3725 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3727 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3729 /* ARMv8.5-A instructions. */
3730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf57ff070, 0xffffffff, "sb"},
3732 /* ARM V6K NOP hints. */
3733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3734 0x0320f001, 0x0fffffff, "yield%c"},
3735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3736 0x0320f002, 0x0fffffff, "wfe%c"},
3737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3738 0x0320f003, 0x0fffffff, "wfi%c"},
3739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3740 0x0320f004, 0x0fffffff, "sev%c"},
3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3742 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3744 /* ARM V6 instructions. */
3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3746 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3748 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3750 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3752 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3754 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3756 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3758 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3760 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3762 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3764 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3766 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3768 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3770 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3772 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3774 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3776 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3778 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3780 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3782 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3784 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3786 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3788 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3790 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3792 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3794 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3796 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3798 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3800 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3802 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3804 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3806 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3808 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3810 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3812 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3814 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3816 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3818 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3820 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3822 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3824 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3826 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3828 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3830 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3832 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3834 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3836 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3838 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3840 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3842 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3844 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3846 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3848 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3850 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3852 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3854 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3856 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3858 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3860 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3862 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3864 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3866 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3868 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3870 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3872 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3874 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3876 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3878 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3880 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3882 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3884 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3886 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3888 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3890 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3892 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3894 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3896 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3898 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3900 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3902 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3904 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3906 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3908 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3910 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3912 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3914 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3916 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3918 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3920 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3922 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3924 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3926 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3928 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3930 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3932 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3934 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3936 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3938 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3940 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3942 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3944 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3946 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3948 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3950 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3952 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3954 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3956 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3958 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3960 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3962 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3964 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3966 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3968 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3970 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3972 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3974 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3976 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3978 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3980 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3982 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3984 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3986 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3988 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
3990 /* V5J instruction. */
3991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
),
3992 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3994 /* V5 Instructions. */
3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3996 0xe1200070, 0xfff000f0,
3997 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3999 0xfa000000, 0xfe000000, "blx\t%B"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4001 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4003 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4005 /* V5E "El Segundo" Instructions. */
4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
4007 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
4009 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
4011 0xf450f000, 0xfc70f000, "pld\t%a"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4013 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4015 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4017 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4019 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4022 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4024 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4027 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4029 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4031 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4033 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4036 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4038 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4040 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4042 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4045 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4047 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4050 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4052 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4054 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4056 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
4058 /* ARM Instructions. */
4059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4060 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4063 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4065 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4067 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4069 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4071 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4073 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4076 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4078 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4080 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4082 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4085 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4087 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4089 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4091 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4094 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4096 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4098 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4101 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4103 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4105 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4108 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4110 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4112 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4115 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4117 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4119 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4122 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4124 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4126 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4129 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4131 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4133 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4136 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4138 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4140 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4143 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4145 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4147 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
4150 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
4152 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
4154 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4157 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4159 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4161 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4164 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
4165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4166 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4168 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4171 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4173 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4175 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4178 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4180 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4182 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4185 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4187 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4189 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4192 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4194 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4196 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4198 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4200 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4202 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4204 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4207 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4209 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4211 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4214 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4216 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4218 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4221 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4223 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4226 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4229 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4231 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4234 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4236 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4238 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4240 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4242 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4244 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4246 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4248 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4250 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4252 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4254 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4256 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4258 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4260 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4262 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4264 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4266 0x092d0000, 0x0fff0000, "push%c\t%m"},
4267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4268 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4270 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4273 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4275 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4277 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4279 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4281 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4283 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4285 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4287 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4289 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4291 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4293 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4295 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4297 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4299 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4301 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4303 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4305 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4307 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4309 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4312 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4314 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
4318 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION
},
4319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4320 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
4321 {ARM_FEATURE_CORE_LOW (0),
4322 0x00000000, 0x00000000, 0}
4325 /* print_insn_thumb16 recognizes the following format control codes:
4327 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4328 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4329 %<bitfield>I print bitfield as a signed decimal
4330 (top bit of range being the sign bit)
4331 %N print Thumb register mask (with LR)
4332 %O print Thumb register mask (with PC)
4333 %M print Thumb register mask
4334 %b print CZB's 6-bit unsigned branch destination
4335 %s print Thumb right-shift immediate (6..10; 0 == 32).
4336 %c print the condition code
4337 %C print the condition code, or "s" if not conditional
4338 %x print warning if conditional an not at end of IT block"
4339 %X print "\t; unpredictable <IT:code>" if conditional
4340 %I print IT instruction suffix and operands
4341 %W print Thumb Writeback indicator for LDMIA
4342 %<bitfield>r print bitfield as an ARM register
4343 %<bitfield>d print bitfield as a decimal
4344 %<bitfield>H print (bitfield * 2) as a decimal
4345 %<bitfield>W print (bitfield * 4) as a decimal
4346 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4347 %<bitfield>B print Thumb branch destination (signed displacement)
4348 %<bitfield>c print bitfield as a condition code
4349 %<bitnum>'c print specified char iff bit is one
4350 %<bitnum>?ab print a if bit is one else print b. */
4352 static const struct opcode16 thumb_opcodes
[] =
4354 /* Thumb instructions. */
4356 /* ARMv8-M Security Extensions instructions. */
4357 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4784, 0xff87, "blxns\t%3-6r"},
4358 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4704, 0xff87, "bxns\t%3-6r"},
4360 /* ARM V8 instructions. */
4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xbf50, 0xffff, "sevl%c"},
4362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xba80, 0xffc0, "hlt\t%0-5x"},
4363 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
), 0xb610, 0xfff7, "setpan\t#%3-3d"},
4365 /* ARM V6K no-argument instructions. */
4366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xffff, "nop%c"},
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf10, 0xffff, "yield%c"},
4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf20, 0xffff, "wfe%c"},
4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf30, 0xffff, "wfi%c"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf40, 0xffff, "sev%c"},
4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4373 /* ARM V6T2 instructions. */
4374 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4375 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4376 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4377 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xbf00, 0xff00, "it%I%X"},
4381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4393 /* ARM V5 ISA extends Thumb. */
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
4395 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
4396 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
4397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
4398 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
4399 /* ARM V4T ISA (Thumb v1). */
4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4401 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
4403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
4423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4700, 0xFF80, "bx%c\t%S%x"},
4424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4400, 0xFF00, "add%c\t%D, %S"},
4425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB400, 0xFE00, "push%c\t%N"},
4429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xBC00, 0xFE00, "pop%c\t%O"},
4431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4432 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4434 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4436 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4438 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
4440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4441 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4443 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4445 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4448 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4450 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4454 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
4463 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4466 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4469 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4471 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4473 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4475 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
4477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4478 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4480 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
4482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4483 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4485 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
4487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4488 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4490 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
4499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4503 /* The E800 .. FFFF range is unconditionally redirected to the
4504 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4505 are processed via that table. Thus, we can never encounter a
4506 bare "second half of BL/BLX(1)" instruction here. */
4507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
), 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
4508 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4511 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
4512 We adopt the convention that hw1 is the high 16 bits of .value and
4513 .mask, hw2 the low 16 bits.
4515 print_insn_thumb32 recognizes the following format control codes:
4519 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4520 %M print a modified 12-bit immediate (same location)
4521 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4522 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4523 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
4524 %S print a possibly-shifted Rm
4526 %L print address for a ldrd/strd instruction
4527 %a print the address of a plain load/store
4528 %w print the width and signedness of a core load/store
4529 %m print register mask for ldm/stm
4530 %n print register mask for clrm
4532 %E print the lsb and width fields of a bfc/bfi instruction
4533 %F print the lsb and width fields of a sbfx/ubfx instruction
4534 %G print a fallback offset for Branch Future instructions
4535 %W print an offset for BF instruction
4536 %Y print an offset for BFL instruction
4537 %Z print an offset for BFCSEL instruction
4538 %Q print an offset for Low Overhead Loop instructions
4539 %P print an offset for Low Overhead Loop end instructions
4540 %b print a conditional branch offset
4541 %B print an unconditional branch offset
4542 %s print the shift field of an SSAT instruction
4543 %R print the rotation field of an SXT instruction
4544 %U print barrier type.
4545 %P print address for pli instruction.
4546 %c print the condition code
4547 %x print warning if conditional an not at end of IT block"
4548 %X print "\t; unpredictable <IT:code>" if conditional
4550 %<bitfield>d print bitfield in decimal
4551 %<bitfield>D print bitfield plus one in decimal
4552 %<bitfield>W print bitfield*4 in decimal
4553 %<bitfield>r print bitfield as an ARM register
4554 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4555 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4556 %<bitfield>c print bitfield as a condition code
4558 %<bitfield>'c print specified char iff bitfield is all ones
4559 %<bitfield>`c print specified char iff bitfield is all zeroes
4560 %<bitfield>?ab... select from array of values in big endian order
4562 With one exception at the bottom (done because BL and BLX(1) need
4563 to come dead last), this table was machine-sorted first in
4564 decreasing order of number of bits set in the mask, then in
4565 increasing numeric order of mask, then in increasing numeric order
4566 of opcode. This order is not the clearest for a human reader, but
4567 is guaranteed never to catch a special-case bit pattern with a more
4568 general mask, which is important, because this instruction encoding
4569 makes heavy use of special-case bit patterns. */
4570 static const struct opcode32 thumb32_opcodes
[] =
4572 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4575 0xf00fe001, 0xffffffff, "lctp%c"},
4576 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4577 0xf02fc001, 0xfffff001, "le\t%P"},
4578 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4579 0xf00fc001, 0xfffff001, "le\tlr, %P"},
4580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4581 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4582 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4583 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4584 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4585 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4586 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4587 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4588 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4589 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
4591 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4592 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4593 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4594 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4596 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4597 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4598 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4599 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4600 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4602 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4603 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4605 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4606 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0xe97fe97f, 0xffffffff, "sg"},
4607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4608 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4609 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4610 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4611 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4612 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4613 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4614 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4616 /* ARM V8.2 RAS extension instructions. */
4617 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
4618 0xf3af8010, 0xffffffff, "esb"},
4620 /* V8 instructions. */
4621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4622 0xf3af8005, 0xffffffff, "sevl%c.w"},
4623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4624 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4626 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4628 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4630 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4632 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4634 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4636 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4638 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4640 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4642 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4644 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4646 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4648 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4650 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4652 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4654 /* CRC32 instructions. */
4655 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4656 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4657 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4658 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4659 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4660 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4661 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4662 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4663 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4664 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4665 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4666 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4668 /* Speculation Barriers. */
4669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8014, 0xffffffff, "csdb"},
4670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f40, 0xffffffff, "ssbb"},
4671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f44, 0xffffffff, "pssbb"},
4673 /* V7 instructions. */
4674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4681 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4682 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4683 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4684 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4686 /* Virtualization Extension instructions. */
4687 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4688 /* We skip ERET as that is SUBS pc, lr, #0. */
4690 /* MP Extension instructions. */
4691 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
4693 /* Security extension instructions. */
4694 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4696 /* ARMv8.5-A instructions. */
4697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf3bf8f70, 0xffffffff, "sb"},
4699 /* Instructions defined in the basic V6T2 set. */
4700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8000, 0xffffffff, "nop%c.w"},
4701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8001, 0xffffffff, "yield%c.w"},
4702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8004, 0xffffffff, "sev%c.w"},
4705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4706 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4709 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4710 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4712 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4714 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4716 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4718 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4720 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4722 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4724 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4726 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4728 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4730 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4732 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4734 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4736 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4737 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4738 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4740 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4742 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4744 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4746 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4748 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4750 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4752 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4754 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4756 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4757 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4758 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4760 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4762 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4764 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4766 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4768 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4770 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4772 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4774 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4776 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4778 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4780 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4782 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4784 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4786 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4788 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4790 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4792 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4794 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4796 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4798 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4800 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4802 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4804 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4806 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4808 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4810 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4812 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4814 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4816 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4818 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4820 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4822 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4824 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4826 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4828 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4830 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4832 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4834 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4836 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4838 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4840 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4842 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4844 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4846 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4848 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4850 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4852 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4854 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4856 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4858 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4860 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4862 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4864 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4865 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4866 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4868 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4870 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4872 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4874 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4876 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4878 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4880 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4882 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4884 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4886 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4888 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4890 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4892 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4894 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4896 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4898 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4900 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4902 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4904 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4906 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4908 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4910 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4912 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4914 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4916 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4918 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4920 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4922 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4924 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4926 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4928 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4930 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4932 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4933 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4934 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4936 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4938 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4940 0xf810f000, 0xff70f000, "pld%c\t%a"},
4941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4942 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4944 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4946 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4948 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4950 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4952 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4954 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4956 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4958 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4960 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4962 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4964 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4966 0xfb100000, 0xfff000c0,
4967 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4969 0xfbc00080, 0xfff000c0,
4970 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4972 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4974 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4976 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
4977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4978 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4980 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4981 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4982 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4984 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4986 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4988 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4990 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4992 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4994 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4996 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4998 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5000 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5002 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5004 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5006 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
5007 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
5008 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
5009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5010 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5012 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5014 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5016 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5018 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5020 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5022 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5024 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5026 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5028 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5030 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5032 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5034 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5036 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5038 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5040 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5042 0xe9400000, 0xff500000,
5043 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5045 0xe9500000, 0xff500000,
5046 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5048 0xe8600000, 0xff700000,
5049 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5051 0xe8700000, 0xff700000,
5052 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5054 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5056 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
5058 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
5059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5060 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5062 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5064 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5066 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
5068 /* These have been 32-bit since the invention of Thumb. */
5069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
5070 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
5072 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
5075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
5076 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
5077 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
5080 static const char *const arm_conditional
[] =
5081 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
5082 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
5084 static const char *const arm_fp_const
[] =
5085 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5087 static const char *const arm_shift
[] =
5088 {"lsl", "lsr", "asr", "ror"};
5093 const char *description
;
5094 const char *reg_names
[16];
5098 static const arm_regname regnames
[] =
5100 { "reg-names-raw", N_("Select raw register names"),
5101 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
5102 { "reg-names-gcc", N_("Select register names used by GCC"),
5103 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
5104 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
5105 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
5106 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL
} },
5107 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL
} },
5108 { "reg-names-apcs", N_("Select register names used in the APCS"),
5109 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
5110 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
5111 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
5112 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5113 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
5116 static const char *const iwmmxt_wwnames
[] =
5117 {"b", "h", "w", "d"};
5119 static const char *const iwmmxt_wwssnames
[] =
5120 {"b", "bus", "bc", "bss",
5121 "h", "hus", "hc", "hss",
5122 "w", "wus", "wc", "wss",
5123 "d", "dus", "dc", "dss"
5126 static const char *const iwmmxt_regnames
[] =
5127 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5128 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5131 static const char *const iwmmxt_cregnames
[] =
5132 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5133 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5136 static const char *const vec_condnames
[] =
5137 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5140 static const char *const mve_predicatenames
[] =
5141 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5142 "eee", "ee", "eet", "e", "ett", "et", "ete"
5145 /* Names for 2-bit size field for mve vector isntructions. */
5146 static const char *const mve_vec_sizename
[] =
5147 { "8", "16", "32", "64"};
5149 /* Indicates whether we are processing a then predicate,
5150 else predicate or none at all. */
5158 /* Information used to process a vpt block and subsequent instructions. */
5161 /* Are we in a vpt block. */
5162 bfd_boolean in_vpt_block
;
5164 /* Next predicate state if in vpt block. */
5165 enum vpt_pred_state next_pred_state
;
5167 /* Mask from vpt/vpst instruction. */
5168 long predicate_mask
;
5170 /* Instruction number in vpt block. */
5171 long current_insn_num
;
5173 /* Number of instructions in vpt block.. */
5177 static struct vpt_block vpt_block_state
=
5186 /* Default to GCC register name set. */
5187 static unsigned int regname_selected
= 1;
5189 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
5190 #define arm_regnames regnames[regname_selected].reg_names
5192 static bfd_boolean force_thumb
= FALSE
;
5194 /* Current IT instruction state. This contains the same state as the IT
5195 bits in the CPSR. */
5196 static unsigned int ifthen_state
;
5197 /* IT state for the next instruction. */
5198 static unsigned int ifthen_next_state
;
5199 /* The address of the insn for which the IT state is valid. */
5200 static bfd_vma ifthen_address
;
5201 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5202 /* Indicates that the current Conditional state is unconditional or outside
5204 #define COND_UNCOND 16
5208 /* Extract the predicate mask for a VPT or VPST instruction.
5209 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5212 mve_extract_pred_mask (long given
)
5214 return ((given
& 0x00400000) >> 19) | ((given
& 0xe000) >> 13);
5217 /* Return the number of instructions in a MVE predicate block. */
5219 num_instructions_vpt_block (long given
)
5221 long mask
= mve_extract_pred_mask (given
);
5228 if ((mask
& 7) == 4)
5231 if ((mask
& 3) == 2)
5234 if ((mask
& 1) == 1)
5241 mark_outside_vpt_block (void)
5243 vpt_block_state
.in_vpt_block
= FALSE
;
5244 vpt_block_state
.next_pred_state
= PRED_NONE
;
5245 vpt_block_state
.predicate_mask
= 0;
5246 vpt_block_state
.current_insn_num
= 0;
5247 vpt_block_state
.num_pred_insn
= 0;
5251 mark_inside_vpt_block (long given
)
5253 vpt_block_state
.in_vpt_block
= TRUE
;
5254 vpt_block_state
.next_pred_state
= PRED_THEN
;
5255 vpt_block_state
.predicate_mask
= mve_extract_pred_mask (given
);
5256 vpt_block_state
.current_insn_num
= 0;
5257 vpt_block_state
.num_pred_insn
= num_instructions_vpt_block (given
);
5258 assert (vpt_block_state
.num_pred_insn
>= 1);
5261 static enum vpt_pred_state
5262 invert_next_predicate_state (enum vpt_pred_state astate
)
5264 if (astate
== PRED_THEN
)
5266 else if (astate
== PRED_ELSE
)
5272 static enum vpt_pred_state
5273 update_next_predicate_state (void)
5275 long pred_mask
= vpt_block_state
.predicate_mask
;
5276 long mask_for_insn
= 0;
5278 switch (vpt_block_state
.current_insn_num
)
5296 if (pred_mask
& mask_for_insn
)
5297 return invert_next_predicate_state (vpt_block_state
.next_pred_state
);
5299 return vpt_block_state
.next_pred_state
;
5303 update_vpt_block_state (void)
5305 vpt_block_state
.current_insn_num
++;
5306 if (vpt_block_state
.current_insn_num
== vpt_block_state
.num_pred_insn
)
5308 /* No more instructions to process in vpt block. */
5309 mark_outside_vpt_block ();
5313 vpt_block_state
.next_pred_state
= update_next_predicate_state ();
5316 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5317 Returns pointer to following character of the format string and
5318 fills in *VALUEP and *WIDTHP with the extracted value and number of
5319 bits extracted. WIDTHP can be NULL. */
5322 arm_decode_bitfield (const char *ptr
,
5324 unsigned long *valuep
,
5327 unsigned long value
= 0;
5335 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
5336 start
= start
* 10 + *ptr
- '0';
5338 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
5339 end
= end
* 10 + *ptr
- '0';
5345 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
5348 while (*ptr
++ == ',');
5356 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
5357 bfd_boolean print_shift
)
5359 func (stream
, "%s", arm_regnames
[given
& 0xf]);
5361 if ((given
& 0xff0) != 0)
5363 if ((given
& 0x10) == 0)
5365 int amount
= (given
& 0xf80) >> 7;
5366 int shift
= (given
& 0x60) >> 5;
5372 func (stream
, ", rrx");
5380 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
5382 func (stream
, ", #%d", amount
);
5384 else if ((given
& 0x80) == 0x80)
5385 func (stream
, "\t; <illegal shifter operand>");
5386 else if (print_shift
)
5387 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
5388 arm_regnames
[(given
& 0xf00) >> 8]);
5390 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
5394 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5397 is_mve_okay_in_it (enum mve_instructions matched_insn
)
5399 switch (matched_insn
)
5401 case MVE_VMOV_GP_TO_VEC_LANE
:
5402 case MVE_VMOV2_VEC_LANE_TO_GP
:
5403 case MVE_VMOV2_GP_TO_VEC_LANE
:
5404 case MVE_VMOV_VEC_LANE_TO_GP
:
5429 is_mve_architecture (struct disassemble_info
*info
)
5431 struct arm_private_data
*private_data
= info
->private_data
;
5432 arm_feature_set allowed_arches
= private_data
->features
;
5434 arm_feature_set arm_ext_v8_1m_main
5435 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
5437 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
5438 && !ARM_CPU_IS_ANY (allowed_arches
))
5445 is_vpt_instruction (long given
)
5448 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5449 if ((given
& 0x0040e000) == 0)
5452 /* VPT floating point T1 variant. */
5453 if (((given
& 0xefb10f50) == 0xee310f00 && ((given
& 0x1001) != 0x1))
5454 /* VPT floating point T2 variant. */
5455 || ((given
& 0xefb10f50) == 0xee310f40)
5456 /* VPT vector T1 variant. */
5457 || ((given
& 0xff811f51) == 0xfe010f00)
5458 /* VPT vector T2 variant. */
5459 || ((given
& 0xff811f51) == 0xfe010f01
5460 && ((given
& 0x300000) != 0x300000))
5461 /* VPT vector T3 variant. */
5462 || ((given
& 0xff811f50) == 0xfe011f00)
5463 /* VPT vector T4 variant. */
5464 || ((given
& 0xff811f70) == 0xfe010f40)
5465 /* VPT vector T5 variant. */
5466 || ((given
& 0xff811f70) == 0xfe010f60)
5467 /* VPT vector T6 variant. */
5468 || ((given
& 0xff811f50) == 0xfe011f40)
5469 /* VPST vector T variant. */
5470 || ((given
& 0xffbf1fff) == 0xfe310f4d))
5476 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5477 and ending bitfield = END. END must be greater than START. */
5479 static unsigned long
5480 arm_decode_field (unsigned long given
, unsigned int start
, unsigned int end
)
5482 int bits
= end
- start
;
5487 return ((given
>> start
) & ((2ul << bits
) - 1));
5490 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5491 START:END and START2:END2. END/END2 must be greater than
5494 static unsigned long
5495 arm_decode_field_multiple (unsigned long given
, unsigned int start
,
5496 unsigned int end
, unsigned int start2
,
5499 int bits
= end
- start
;
5500 int bits2
= end2
- start2
;
5501 unsigned long value
= 0;
5507 value
= arm_decode_field (given
, start
, end
);
5510 value
|= ((given
>> start2
) & ((2ul << bits2
) - 1)) << width
;
5514 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5515 This helps us decode instructions that change mnemonic depending on specific
5516 operand values/encodings. */
5519 is_mve_encoding_conflict (unsigned long given
,
5520 enum mve_instructions matched_insn
)
5522 switch (matched_insn
)
5525 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5531 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5533 if ((arm_decode_field (given
, 12, 12) == 0)
5534 && (arm_decode_field (given
, 0, 0) == 1))
5539 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5541 if (arm_decode_field (given
, 0, 3) == 0xd)
5545 case MVE_VPT_VEC_T1
:
5546 case MVE_VPT_VEC_T2
:
5547 case MVE_VPT_VEC_T3
:
5548 case MVE_VPT_VEC_T4
:
5549 case MVE_VPT_VEC_T5
:
5550 case MVE_VPT_VEC_T6
:
5551 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5553 if (arm_decode_field (given
, 20, 21) == 3)
5557 case MVE_VCMP_FP_T1
:
5558 if ((arm_decode_field (given
, 12, 12) == 0)
5559 && (arm_decode_field (given
, 0, 0) == 1))
5564 case MVE_VCMP_FP_T2
:
5565 if (arm_decode_field (given
, 0, 3) == 0xd)
5572 case MVE_VMUL_VEC_T2
:
5579 case MVE_VADD_VEC_T2
:
5580 case MVE_VSUB_VEC_T2
:
5597 case MVE_VQDMULH_T3
:
5598 case MVE_VQRDMULH_T4
:
5604 case MVE_VCMP_VEC_T1
:
5605 case MVE_VCMP_VEC_T2
:
5606 case MVE_VCMP_VEC_T3
:
5607 case MVE_VCMP_VEC_T4
:
5608 case MVE_VCMP_VEC_T5
:
5609 case MVE_VCMP_VEC_T6
:
5610 if (arm_decode_field (given
, 20, 21) == 3)
5619 if (arm_decode_field (given
, 7, 8) == 3)
5626 if ((arm_decode_field (given
, 24, 24) == 0)
5627 && (arm_decode_field (given
, 21, 21) == 0))
5631 else if ((arm_decode_field (given
, 7, 8) == 3))
5639 if ((arm_decode_field (given
, 24, 24) == 0)
5640 && (arm_decode_field (given
, 21, 21) == 0))
5647 case MVE_VCVT_FP_FIX_VEC
:
5648 return (arm_decode_field (given
, 16, 21) & 0x38) == 0;
5653 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5655 if ((cmode
& 1) == 0)
5657 else if ((cmode
& 0xc) == 0xc)
5665 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5667 if ((cmode
& 9) == 1)
5669 else if ((cmode
& 5) == 1)
5671 else if ((cmode
& 0xe) == 0xe)
5677 case MVE_VMOV_IMM_TO_VEC
:
5678 if ((arm_decode_field (given
, 5, 5) == 1)
5679 && (arm_decode_field (given
, 8, 11) != 0xe))
5686 unsigned long size
= arm_decode_field (given
, 19, 20);
5687 if ((size
== 0) || (size
== 3))
5708 if (arm_decode_field (given
, 18, 19) == 3)
5714 case MVE_VRMLSLDAVH
:
5717 if (arm_decode_field (given
, 20, 22) == 7)
5722 case MVE_VRMLALDAVH
:
5723 if ((arm_decode_field (given
, 20, 22) & 6) == 6)
5730 if ((arm_decode_field (given
, 20, 21) == 3)
5731 || (arm_decode_field (given
, 1, 3) == 7))
5738 if (arm_decode_field (given
, 16, 18) == 0)
5740 unsigned long sz
= arm_decode_field (given
, 19, 20);
5742 if ((sz
== 1) || (sz
== 2))
5757 if (arm_decode_field (given
, 19, 21) == 0)
5763 if (arm_decode_field (given
, 16, 19) == 0xf)
5779 if (arm_decode_field (given
, 9, 11) == 0x7)
5787 unsigned long rm
, rn
;
5788 rm
= arm_decode_field (given
, 0, 3);
5789 rn
= arm_decode_field (given
, 16, 19);
5791 if (rm
== 0xf && rn
== 0xf)
5794 else if (rn
== rm
&& rn
!= 0xf)
5800 if (arm_decode_field (given
, 0, 3) == 0xd)
5803 else if (matched_insn
== MVE_CSNEG
)
5804 if (arm_decode_field (given
, 0, 3) == arm_decode_field (given
, 16, 19))
5809 case MVE_VADD_FP_T1
:
5810 case MVE_VADD_FP_T2
:
5811 case MVE_VADD_VEC_T1
:
5818 print_mve_vld_str_addr (struct disassemble_info
*info
,
5819 unsigned long given
,
5820 enum mve_instructions matched_insn
)
5822 void *stream
= info
->stream
;
5823 fprintf_ftype func
= info
->fprintf_func
;
5825 unsigned long p
, w
, gpr
, imm
, add
, mod_imm
;
5827 imm
= arm_decode_field (given
, 0, 6);
5830 switch (matched_insn
)
5834 gpr
= arm_decode_field (given
, 16, 18);
5839 gpr
= arm_decode_field (given
, 16, 18);
5845 gpr
= arm_decode_field (given
, 16, 19);
5851 gpr
= arm_decode_field (given
, 16, 19);
5857 gpr
= arm_decode_field (given
, 16, 19);
5864 p
= arm_decode_field (given
, 24, 24);
5865 w
= arm_decode_field (given
, 21, 21);
5867 add
= arm_decode_field (given
, 23, 23);
5871 /* Don't print anything for '+' as it is implied. */
5881 func (stream
, "[%s, #%s%lu]", arm_regnames
[gpr
], add_sub
, mod_imm
);
5882 /* Pre-indexed mode. */
5884 func (stream
, "[%s, #%s%lu]!", arm_regnames
[gpr
], add_sub
, mod_imm
);
5886 else if ((p
== 0) && (w
== 1))
5887 /* Post-index mode. */
5888 func (stream
, "[%s], #%s%lu", arm_regnames
[gpr
], add_sub
, mod_imm
);
5891 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5892 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5893 this encoding is undefined. */
5896 is_mve_undefined (unsigned long given
, enum mve_instructions matched_insn
,
5897 enum mve_undefined
*undefined_code
)
5899 *undefined_code
= UNDEF_NONE
;
5901 switch (matched_insn
)
5904 if (arm_decode_field_multiple (given
, 5, 5, 22, 22) == 3)
5906 *undefined_code
= UNDEF_SIZE_3
;
5914 case MVE_VMUL_VEC_T1
:
5916 case MVE_VADD_VEC_T1
:
5917 case MVE_VSUB_VEC_T1
:
5918 case MVE_VQDMULH_T1
:
5919 case MVE_VQRDMULH_T2
:
5923 if (arm_decode_field (given
, 20, 21) == 3)
5925 *undefined_code
= UNDEF_SIZE_3
;
5932 if (arm_decode_field (given
, 7, 8) == 3)
5934 *undefined_code
= UNDEF_SIZE_3
;
5941 if (arm_decode_field (given
, 7, 8) <= 1)
5943 *undefined_code
= UNDEF_SIZE_LE_1
;
5950 if ((arm_decode_field (given
, 7, 8) == 0))
5952 *undefined_code
= UNDEF_SIZE_0
;
5959 if ((arm_decode_field (given
, 7, 8) <= 1))
5961 *undefined_code
= UNDEF_SIZE_LE_1
;
5967 case MVE_VLDRB_GATHER_T1
:
5968 if (arm_decode_field (given
, 7, 8) == 3)
5970 *undefined_code
= UNDEF_SIZE_3
;
5973 else if ((arm_decode_field (given
, 28, 28) == 0)
5974 && (arm_decode_field (given
, 7, 8) == 0))
5976 *undefined_code
= UNDEF_NOT_UNS_SIZE_0
;
5982 case MVE_VLDRH_GATHER_T2
:
5983 if (arm_decode_field (given
, 7, 8) == 3)
5985 *undefined_code
= UNDEF_SIZE_3
;
5988 else if ((arm_decode_field (given
, 28, 28) == 0)
5989 && (arm_decode_field (given
, 7, 8) == 1))
5991 *undefined_code
= UNDEF_NOT_UNS_SIZE_1
;
5994 else if (arm_decode_field (given
, 7, 8) == 0)
5996 *undefined_code
= UNDEF_SIZE_0
;
6002 case MVE_VLDRW_GATHER_T3
:
6003 if (arm_decode_field (given
, 7, 8) != 2)
6005 *undefined_code
= UNDEF_SIZE_NOT_2
;
6008 else if (arm_decode_field (given
, 28, 28) == 0)
6010 *undefined_code
= UNDEF_NOT_UNSIGNED
;
6016 case MVE_VLDRD_GATHER_T4
:
6017 if (arm_decode_field (given
, 7, 8) != 3)
6019 *undefined_code
= UNDEF_SIZE_NOT_3
;
6022 else if (arm_decode_field (given
, 28, 28) == 0)
6024 *undefined_code
= UNDEF_NOT_UNSIGNED
;
6030 case MVE_VSTRB_SCATTER_T1
:
6031 if (arm_decode_field (given
, 7, 8) == 3)
6033 *undefined_code
= UNDEF_SIZE_3
;
6039 case MVE_VSTRH_SCATTER_T2
:
6041 unsigned long size
= arm_decode_field (given
, 7, 8);
6044 *undefined_code
= UNDEF_SIZE_3
;
6049 *undefined_code
= UNDEF_SIZE_0
;
6056 case MVE_VSTRW_SCATTER_T3
:
6057 if (arm_decode_field (given
, 7, 8) != 2)
6059 *undefined_code
= UNDEF_SIZE_NOT_2
;
6065 case MVE_VSTRD_SCATTER_T4
:
6066 if (arm_decode_field (given
, 7, 8) != 3)
6068 *undefined_code
= UNDEF_SIZE_NOT_3
;
6074 case MVE_VCVT_FP_FIX_VEC
:
6076 unsigned long imm6
= arm_decode_field (given
, 16, 21);
6077 if ((imm6
& 0x20) == 0)
6079 *undefined_code
= UNDEF_VCVT_IMM6
;
6083 if ((arm_decode_field (given
, 9, 9) == 0)
6084 && ((imm6
& 0x30) == 0x20))
6086 *undefined_code
= UNDEF_VCVT_FSI_IMM6
;
6095 case MVE_VCVT_BETWEEN_FP_INT
:
6096 case MVE_VCVT_FROM_FP_TO_INT
:
6098 unsigned long size
= arm_decode_field (given
, 18, 19);
6101 *undefined_code
= UNDEF_SIZE_0
;
6106 *undefined_code
= UNDEF_SIZE_3
;
6113 case MVE_VMOV_VEC_LANE_TO_GP
:
6115 unsigned long op1
= arm_decode_field (given
, 21, 22);
6116 unsigned long op2
= arm_decode_field (given
, 5, 6);
6117 unsigned long u
= arm_decode_field (given
, 23, 23);
6119 if ((op2
== 0) && (u
== 1))
6121 if ((op1
== 0) || (op1
== 1))
6123 *undefined_code
= UNDEF_BAD_U_OP1_OP2
;
6131 if ((op1
== 0) || (op1
== 1))
6133 *undefined_code
= UNDEF_BAD_OP1_OP2
;
6143 case MVE_VMOV_GP_TO_VEC_LANE
:
6144 if (arm_decode_field (given
, 5, 6) == 2)
6146 unsigned long op1
= arm_decode_field (given
, 21, 22);
6147 if ((op1
== 0) || (op1
== 1))
6149 *undefined_code
= UNDEF_BAD_OP1_OP2
;
6158 case MVE_VMOV_VEC_TO_VEC
:
6159 if ((arm_decode_field (given
, 5, 5) == 1)
6160 || (arm_decode_field (given
, 22, 22) == 1))
6164 case MVE_VMOV_IMM_TO_VEC
:
6165 if (arm_decode_field (given
, 5, 5) == 0)
6167 unsigned long cmode
= arm_decode_field (given
, 8, 11);
6169 if (((cmode
& 9) == 1) || ((cmode
& 5) == 1))
6171 *undefined_code
= UNDEF_OP_0_BAD_CMODE
;
6182 if (arm_decode_field (given
, 18, 19) == 2)
6184 *undefined_code
= UNDEF_SIZE_2
;
6190 case MVE_VRMLALDAVH
:
6191 case MVE_VMLADAV_T1
:
6192 case MVE_VMLADAV_T2
:
6194 if ((arm_decode_field (given
, 28, 28) == 1)
6195 && (arm_decode_field (given
, 12, 12) == 1))
6197 *undefined_code
= UNDEF_XCHG_UNS
;
6208 unsigned long sz
= arm_decode_field (given
, 19, 20);
6211 else if ((sz
& 2) == 2)
6215 *undefined_code
= UNDEF_SIZE
;
6229 unsigned long sz
= arm_decode_field (given
, 19, 21);
6232 else if ((sz
& 6) == 2)
6234 else if ((sz
& 4) == 4)
6238 *undefined_code
= UNDEF_SIZE
;
6245 if (arm_decode_field (given
, 19, 20) == 0)
6247 *undefined_code
= UNDEF_SIZE_0
;
6254 if (arm_decode_field (given
, 18, 19) == 3)
6256 *undefined_code
= UNDEF_SIZE_3
;
6267 if (arm_decode_field (given
, 18, 19) == 3)
6269 *undefined_code
= UNDEF_SIZE_3
;
6276 if (arm_decode_field (given
, 18, 19) == 0)
6280 *undefined_code
= UNDEF_SIZE_NOT_0
;
6286 unsigned long size
= arm_decode_field (given
, 18, 19);
6287 if ((size
& 2) == 2)
6289 *undefined_code
= UNDEF_SIZE_2
;
6297 if (arm_decode_field (given
, 18, 19) != 3)
6301 *undefined_code
= UNDEF_SIZE_3
;
6310 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6311 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6312 why this encoding is unpredictable. */
6315 is_mve_unpredictable (unsigned long given
, enum mve_instructions matched_insn
,
6316 enum mve_unpredictable
*unpredictable_code
)
6318 *unpredictable_code
= UNPRED_NONE
;
6320 switch (matched_insn
)
6322 case MVE_VCMP_FP_T2
:
6324 if ((arm_decode_field (given
, 12, 12) == 0)
6325 && (arm_decode_field (given
, 5, 5) == 1))
6327 *unpredictable_code
= UNPRED_FCA_0_FCB_1
;
6333 case MVE_VPT_VEC_T4
:
6334 case MVE_VPT_VEC_T5
:
6335 case MVE_VPT_VEC_T6
:
6336 case MVE_VCMP_VEC_T4
:
6337 case MVE_VCMP_VEC_T5
:
6338 case MVE_VCMP_VEC_T6
:
6339 if (arm_decode_field (given
, 0, 3) == 0xd)
6341 *unpredictable_code
= UNPRED_R13
;
6349 unsigned long gpr
= arm_decode_field (given
, 12, 15);
6352 *unpredictable_code
= UNPRED_R13
;
6355 else if (gpr
== 0xf)
6357 *unpredictable_code
= UNPRED_R15
;
6366 case MVE_VMUL_FP_T2
:
6367 case MVE_VMUL_VEC_T2
:
6370 case MVE_VADD_FP_T2
:
6371 case MVE_VSUB_FP_T2
:
6372 case MVE_VADD_VEC_T2
:
6373 case MVE_VSUB_VEC_T2
:
6383 case MVE_VQDMULH_T3
:
6384 case MVE_VQRDMULH_T4
:
6386 case MVE_VFMA_FP_SCALAR
:
6387 case MVE_VFMAS_FP_SCALAR
:
6391 unsigned long gpr
= arm_decode_field (given
, 0, 3);
6394 *unpredictable_code
= UNPRED_R13
;
6397 else if (gpr
== 0xf)
6399 *unpredictable_code
= UNPRED_R15
;
6409 unsigned long rn
= arm_decode_field (given
, 16, 19);
6411 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6413 *unpredictable_code
= UNPRED_R13_AND_WB
;
6419 *unpredictable_code
= UNPRED_R15
;
6423 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 6)
6425 *unpredictable_code
= UNPRED_Q_GT_6
;
6435 unsigned long rn
= arm_decode_field (given
, 16, 19);
6437 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6439 *unpredictable_code
= UNPRED_R13_AND_WB
;
6445 *unpredictable_code
= UNPRED_R15
;
6449 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 4)
6451 *unpredictable_code
= UNPRED_Q_GT_4
;
6465 unsigned long rn
= arm_decode_field (given
, 16, 19);
6467 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6469 *unpredictable_code
= UNPRED_R13_AND_WB
;
6474 *unpredictable_code
= UNPRED_R15
;
6481 case MVE_VLDRB_GATHER_T1
:
6482 if (arm_decode_field (given
, 0, 0) == 1)
6484 *unpredictable_code
= UNPRED_OS
;
6489 /* To handle common code with T2-T4 variants. */
6490 case MVE_VLDRH_GATHER_T2
:
6491 case MVE_VLDRW_GATHER_T3
:
6492 case MVE_VLDRD_GATHER_T4
:
6494 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6495 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6499 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6503 if (arm_decode_field (given
, 16, 19) == 0xf)
6505 *unpredictable_code
= UNPRED_R15
;
6512 case MVE_VLDRW_GATHER_T5
:
6513 case MVE_VLDRD_GATHER_T6
:
6515 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6516 unsigned long qm
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6520 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6527 case MVE_VSTRB_SCATTER_T1
:
6528 if (arm_decode_field (given
, 16, 19) == 0xf)
6530 *unpredictable_code
= UNPRED_R15
;
6533 else if (arm_decode_field (given
, 0, 0) == 1)
6535 *unpredictable_code
= UNPRED_OS
;
6541 case MVE_VSTRH_SCATTER_T2
:
6542 case MVE_VSTRW_SCATTER_T3
:
6543 case MVE_VSTRD_SCATTER_T4
:
6544 if (arm_decode_field (given
, 16, 19) == 0xf)
6546 *unpredictable_code
= UNPRED_R15
;
6552 case MVE_VMOV2_VEC_LANE_TO_GP
:
6553 case MVE_VMOV2_GP_TO_VEC_LANE
:
6554 case MVE_VCVT_BETWEEN_FP_INT
:
6555 case MVE_VCVT_FROM_FP_TO_INT
:
6557 unsigned long rt
= arm_decode_field (given
, 0, 3);
6558 unsigned long rt2
= arm_decode_field (given
, 16, 19);
6560 if ((rt
== 0xd) || (rt2
== 0xd))
6562 *unpredictable_code
= UNPRED_R13
;
6565 else if ((rt
== 0xf) || (rt2
== 0xf))
6567 *unpredictable_code
= UNPRED_R15
;
6572 *unpredictable_code
= UNPRED_GP_REGS_EQUAL
;
6581 case MVE_VMAXNMV_FP
:
6582 case MVE_VMAXNMAV_FP
:
6583 case MVE_VMINNMV_FP
:
6584 case MVE_VMINNMAV_FP
:
6588 case MVE_VMOV_HFP_TO_GP
:
6589 case MVE_VMOV_GP_TO_VEC_LANE
:
6590 case MVE_VMOV_VEC_LANE_TO_GP
:
6592 unsigned long rda
= arm_decode_field (given
, 12, 15);
6595 *unpredictable_code
= UNPRED_R13
;
6598 else if (rda
== 0xf)
6600 *unpredictable_code
= UNPRED_R15
;
6613 if (arm_decode_field (given
, 20, 21) == 2)
6615 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6616 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6617 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6619 if ((Qd
== Qn
) || (Qd
== Qm
))
6621 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
6632 case MVE_VQDMULL_T1
:
6638 if (arm_decode_field (given
, 28, 28) == 1)
6640 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6641 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6642 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6644 if ((Qd
== Qn
) || (Qd
== Qm
))
6646 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6656 case MVE_VQDMULL_T2
:
6658 unsigned long gpr
= arm_decode_field (given
, 0, 3);
6661 *unpredictable_code
= UNPRED_R13
;
6664 else if (gpr
== 0xf)
6666 *unpredictable_code
= UNPRED_R15
;
6670 if (arm_decode_field (given
, 28, 28) == 1)
6673 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
6674 unsigned long Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6678 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6689 case MVE_VRMLSLDAVH
:
6692 if (arm_decode_field (given
, 20, 22) == 6)
6694 *unpredictable_code
= UNPRED_R13
;
6702 if (arm_decode_field (given
, 1, 3) == 6)
6704 *unpredictable_code
= UNPRED_R13
;
6713 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6714 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6715 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 21) == 2)
6717 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
6726 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6727 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6728 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 20) == 1)
6730 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6743 if (arm_decode_field (given
, 20, 20) == 1)
6745 Qda
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6746 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6747 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6749 if ((Qda
== Qn
) || (Qda
== Qm
))
6751 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6763 if (arm_decode_field (given
, 16, 19) == 0xd)
6765 *unpredictable_code
= UNPRED_R13
;
6773 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6774 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 6, 6);
6778 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6797 unsigned long gpr
= arm_decode_field (given
, 9, 11);
6798 gpr
= ((gpr
<< 1) | 1);
6801 *unpredictable_code
= UNPRED_R13
;
6804 else if (gpr
== 0xf)
6806 *unpredictable_code
= UNPRED_R15
;
6819 print_mve_vmov_index (struct disassemble_info
*info
, unsigned long given
)
6821 unsigned long op1
= arm_decode_field (given
, 21, 22);
6822 unsigned long op2
= arm_decode_field (given
, 5, 6);
6823 unsigned long h
= arm_decode_field (given
, 16, 16);
6824 unsigned long index_operand
, esize
, targetBeat
, idx
;
6825 void *stream
= info
->stream
;
6826 fprintf_ftype func
= info
->fprintf_func
;
6828 if ((op1
& 0x2) == 0x2)
6830 index_operand
= op2
;
6833 else if (((op1
& 0x2) == 0x0) && ((op2
& 0x1) == 0x1))
6835 index_operand
= op2
>> 1;
6838 else if (((op1
& 0x2) == 0) && ((op2
& 0x3) == 0))
6845 func (stream
, "<undefined index>");
6849 targetBeat
= (op1
& 0x1) | (h
<< 1);
6850 idx
= index_operand
+ targetBeat
* (32/esize
);
6852 func (stream
, "%lu", idx
);
6855 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6856 in length and integer of floating-point type. */
6858 print_simd_imm8 (struct disassemble_info
*info
, unsigned long given
,
6859 unsigned int ibit_loc
, const struct mopcode32
*insn
)
6862 int cmode
= (given
>> 8) & 0xf;
6863 int op
= (given
>> 5) & 0x1;
6864 unsigned long value
= 0, hival
= 0;
6868 void *stream
= info
->stream
;
6869 fprintf_ftype func
= info
->fprintf_func
;
6871 /* On Neon the 'i' bit is at bit 24, on mve it is
6873 bits
|= ((given
>> ibit_loc
) & 1) << 7;
6874 bits
|= ((given
>> 16) & 7) << 4;
6875 bits
|= ((given
>> 0) & 15) << 0;
6879 shift
= (cmode
>> 1) & 3;
6880 value
= (unsigned long) bits
<< (8 * shift
);
6883 else if (cmode
< 12)
6885 shift
= (cmode
>> 1) & 1;
6886 value
= (unsigned long) bits
<< (8 * shift
);
6889 else if (cmode
< 14)
6891 shift
= (cmode
& 1) + 1;
6892 value
= (unsigned long) bits
<< (8 * shift
);
6893 value
|= (1ul << (8 * shift
)) - 1;
6896 else if (cmode
== 14)
6900 /* Bit replication into bytes. */
6906 for (ix
= 7; ix
>= 0; ix
--)
6908 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
6910 value
= (value
<< 8) | mask
;
6912 hival
= (hival
<< 8) | mask
;
6918 /* Byte replication. */
6919 value
= (unsigned long) bits
;
6925 /* Floating point encoding. */
6928 value
= (unsigned long) (bits
& 0x7f) << 19;
6929 value
|= (unsigned long) (bits
& 0x80) << 24;
6930 tmp
= bits
& 0x40 ? 0x3c : 0x40;
6931 value
|= (unsigned long) tmp
<< 24;
6937 func (stream
, "<illegal constant %.8x:%x:%x>",
6943 // printU determines whether the immediate value should be printed as
6945 unsigned printU
= 0;
6946 switch (insn
->mve_op
)
6950 // We want this for instructions that don't have a 'signed' type
6954 case MVE_VMOV_IMM_TO_VEC
:
6961 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
6968 : "#%ld\t; 0x%.4lx", value
, value
);
6974 unsigned char valbytes
[4];
6977 /* Do this a byte at a time so we don't have to
6978 worry about the host's endianness. */
6979 valbytes
[0] = value
& 0xff;
6980 valbytes
[1] = (value
>> 8) & 0xff;
6981 valbytes
[2] = (value
>> 16) & 0xff;
6982 valbytes
[3] = (value
>> 24) & 0xff;
6984 floatformat_to_double
6985 (& floatformat_ieee_single_little
, valbytes
,
6988 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
6995 : "#%ld\t; 0x%.8lx",
6996 (long) (((value
& 0x80000000L
) != 0)
6998 ? value
| ~0xffffffffL
: value
),
7003 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
7013 print_mve_undefined (struct disassemble_info
*info
,
7014 enum mve_undefined undefined_code
)
7016 void *stream
= info
->stream
;
7017 fprintf_ftype func
= info
->fprintf_func
;
7019 func (stream
, "\t\tundefined instruction: ");
7021 switch (undefined_code
)
7024 func (stream
, "illegal size");
7028 func (stream
, "size equals zero");
7032 func (stream
, "size equals two");
7036 func (stream
, "size equals three");
7039 case UNDEF_SIZE_LE_1
:
7040 func (stream
, "size <= 1");
7043 case UNDEF_SIZE_NOT_0
:
7044 func (stream
, "size not equal to 0");
7047 case UNDEF_SIZE_NOT_2
:
7048 func (stream
, "size not equal to 2");
7051 case UNDEF_SIZE_NOT_3
:
7052 func (stream
, "size not equal to 3");
7055 case UNDEF_NOT_UNS_SIZE_0
:
7056 func (stream
, "not unsigned and size = zero");
7059 case UNDEF_NOT_UNS_SIZE_1
:
7060 func (stream
, "not unsigned and size = one");
7063 case UNDEF_NOT_UNSIGNED
:
7064 func (stream
, "not unsigned");
7067 case UNDEF_VCVT_IMM6
:
7068 func (stream
, "invalid imm6");
7071 case UNDEF_VCVT_FSI_IMM6
:
7072 func (stream
, "fsi = 0 and invalid imm6");
7075 case UNDEF_BAD_OP1_OP2
:
7076 func (stream
, "bad size with op2 = 2 and op1 = 0 or 1");
7079 case UNDEF_BAD_U_OP1_OP2
:
7080 func (stream
, "unsigned with op2 = 0 and op1 = 0 or 1");
7083 case UNDEF_OP_0_BAD_CMODE
:
7084 func (stream
, "op field equal 0 and bad cmode");
7087 case UNDEF_XCHG_UNS
:
7088 func (stream
, "exchange and unsigned together");
7098 print_mve_unpredictable (struct disassemble_info
*info
,
7099 enum mve_unpredictable unpredict_code
)
7101 void *stream
= info
->stream
;
7102 fprintf_ftype func
= info
->fprintf_func
;
7104 func (stream
, "%s: ", UNPREDICTABLE_INSTRUCTION
);
7106 switch (unpredict_code
)
7108 case UNPRED_IT_BLOCK
:
7109 func (stream
, "mve instruction in it block");
7112 case UNPRED_FCA_0_FCB_1
:
7113 func (stream
, "condition bits, fca = 0 and fcb = 1");
7117 func (stream
, "use of r13 (sp)");
7121 func (stream
, "use of r15 (pc)");
7125 func (stream
, "start register block > r4");
7129 func (stream
, "start register block > r6");
7132 case UNPRED_R13_AND_WB
:
7133 func (stream
, "use of r13 and write back");
7136 case UNPRED_Q_REGS_EQUAL
:
7138 "same vector register used for destination and other operand");
7142 func (stream
, "use of offset scaled");
7145 case UNPRED_GP_REGS_EQUAL
:
7146 func (stream
, "same general-purpose register used for both operands");
7149 case UNPRED_Q_REGS_EQ_AND_SIZE_1
:
7150 func (stream
, "use of identical q registers and size = 1");
7153 case UNPRED_Q_REGS_EQ_AND_SIZE_2
:
7154 func (stream
, "use of identical q registers and size = 1");
7162 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
7165 print_mve_register_blocks (struct disassemble_info
*info
,
7166 unsigned long given
,
7167 enum mve_instructions matched_insn
)
7169 void *stream
= info
->stream
;
7170 fprintf_ftype func
= info
->fprintf_func
;
7172 unsigned long q_reg_start
= arm_decode_field_multiple (given
,
7175 switch (matched_insn
)
7179 if (q_reg_start
<= 6)
7180 func (stream
, "{q%ld, q%ld}", q_reg_start
, q_reg_start
+ 1);
7182 func (stream
, "<illegal reg q%ld>", q_reg_start
);
7187 if (q_reg_start
<= 4)
7188 func (stream
, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start
,
7189 q_reg_start
+ 1, q_reg_start
+ 2,
7192 func (stream
, "<illegal reg q%ld>", q_reg_start
);
7201 print_mve_rounding_mode (struct disassemble_info
*info
,
7202 unsigned long given
,
7203 enum mve_instructions matched_insn
)
7205 void *stream
= info
->stream
;
7206 fprintf_ftype func
= info
->fprintf_func
;
7208 switch (matched_insn
)
7210 case MVE_VCVT_FROM_FP_TO_INT
:
7212 switch (arm_decode_field (given
, 8, 9))
7238 switch (arm_decode_field (given
, 7, 9))
7277 print_mve_vcvt_size (struct disassemble_info
*info
,
7278 unsigned long given
,
7279 enum mve_instructions matched_insn
)
7281 unsigned long mode
= 0;
7282 void *stream
= info
->stream
;
7283 fprintf_ftype func
= info
->fprintf_func
;
7285 switch (matched_insn
)
7287 case MVE_VCVT_FP_FIX_VEC
:
7289 mode
= (((given
& 0x200) >> 7)
7290 | ((given
& 0x10000000) >> 27)
7291 | ((given
& 0x100) >> 8));
7296 func (stream
, "f16.s16");
7300 func (stream
, "s16.f16");
7304 func (stream
, "f16.u16");
7308 func (stream
, "u16.f16");
7312 func (stream
, "f32.s32");
7316 func (stream
, "s32.f32");
7320 func (stream
, "f32.u32");
7324 func (stream
, "u32.f32");
7332 case MVE_VCVT_BETWEEN_FP_INT
:
7334 unsigned long size
= arm_decode_field (given
, 18, 19);
7335 unsigned long op
= arm_decode_field (given
, 7, 8);
7342 func (stream
, "f16.s16");
7346 func (stream
, "f16.u16");
7350 func (stream
, "s16.f16");
7354 func (stream
, "u16.f16");
7366 func (stream
, "f32.s32");
7370 func (stream
, "f32.u32");
7374 func (stream
, "s32.f32");
7378 func (stream
, "u32.f32");
7385 case MVE_VCVT_FP_HALF_FP
:
7387 unsigned long op
= arm_decode_field (given
, 28, 28);
7389 func (stream
, "f16.f32");
7391 func (stream
, "f32.f16");
7395 case MVE_VCVT_FROM_FP_TO_INT
:
7397 unsigned long size
= arm_decode_field_multiple (given
, 7, 7, 18, 19);
7402 func (stream
, "s16.f16");
7406 func (stream
, "u16.f16");
7410 func (stream
, "s32.f32");
7414 func (stream
, "u32.f32");
7429 print_mve_rotate (struct disassemble_info
*info
, unsigned long rot
,
7430 unsigned long rot_width
)
7432 void *stream
= info
->stream
;
7433 fprintf_ftype func
= info
->fprintf_func
;
7440 func (stream
, "90");
7443 func (stream
, "270");
7449 else if (rot_width
== 2)
7457 func (stream
, "90");
7460 func (stream
, "180");
7463 func (stream
, "270");
7472 print_instruction_predicate (struct disassemble_info
*info
)
7474 void *stream
= info
->stream
;
7475 fprintf_ftype func
= info
->fprintf_func
;
7477 if (vpt_block_state
.next_pred_state
== PRED_THEN
)
7479 else if (vpt_block_state
.next_pred_state
== PRED_ELSE
)
7484 print_mve_size (struct disassemble_info
*info
,
7486 enum mve_instructions matched_insn
)
7488 void *stream
= info
->stream
;
7489 fprintf_ftype func
= info
->fprintf_func
;
7491 switch (matched_insn
)
7497 case MVE_VADD_VEC_T1
:
7498 case MVE_VADD_VEC_T2
:
7504 case MVE_VCMP_VEC_T1
:
7505 case MVE_VCMP_VEC_T2
:
7506 case MVE_VCMP_VEC_T3
:
7507 case MVE_VCMP_VEC_T4
:
7508 case MVE_VCMP_VEC_T5
:
7509 case MVE_VCMP_VEC_T6
:
7522 case MVE_VLDRB_GATHER_T1
:
7523 case MVE_VLDRH_GATHER_T2
:
7524 case MVE_VLDRW_GATHER_T3
:
7525 case MVE_VLDRD_GATHER_T4
:
7538 case MVE_VMUL_VEC_T1
:
7539 case MVE_VMUL_VEC_T2
:
7545 case MVE_VPT_VEC_T1
:
7546 case MVE_VPT_VEC_T2
:
7547 case MVE_VPT_VEC_T3
:
7548 case MVE_VPT_VEC_T4
:
7549 case MVE_VPT_VEC_T5
:
7550 case MVE_VPT_VEC_T6
:
7562 case MVE_VQDMULH_T1
:
7563 case MVE_VQRDMULH_T2
:
7564 case MVE_VQDMULH_T3
:
7565 case MVE_VQRDMULH_T4
:
7584 case MVE_VSTRB_SCATTER_T1
:
7585 case MVE_VSTRH_SCATTER_T2
:
7586 case MVE_VSTRW_SCATTER_T3
:
7589 case MVE_VSUB_VEC_T1
:
7590 case MVE_VSUB_VEC_T2
:
7592 func (stream
, "%s", mve_vec_sizename
[size
]);
7594 func (stream
, "<undef size>");
7598 case MVE_VADD_FP_T1
:
7599 case MVE_VADD_FP_T2
:
7600 case MVE_VSUB_FP_T1
:
7601 case MVE_VSUB_FP_T2
:
7602 case MVE_VCMP_FP_T1
:
7603 case MVE_VCMP_FP_T2
:
7604 case MVE_VFMA_FP_SCALAR
:
7607 case MVE_VFMAS_FP_SCALAR
:
7609 case MVE_VMAXNMA_FP
:
7610 case MVE_VMAXNMV_FP
:
7611 case MVE_VMAXNMAV_FP
:
7613 case MVE_VMINNMA_FP
:
7614 case MVE_VMINNMV_FP
:
7615 case MVE_VMINNMAV_FP
:
7616 case MVE_VMUL_FP_T1
:
7617 case MVE_VMUL_FP_T2
:
7621 func (stream
, "32");
7623 func (stream
, "16");
7629 case MVE_VMLADAV_T1
:
7631 case MVE_VMLSDAV_T1
:
7634 case MVE_VQDMULL_T1
:
7635 case MVE_VQDMULL_T2
:
7639 func (stream
, "16");
7641 func (stream
, "32");
7648 func (stream
, "16");
7655 func (stream
, "32");
7658 func (stream
, "16");
7668 case MVE_VMOV_GP_TO_VEC_LANE
:
7669 case MVE_VMOV_VEC_LANE_TO_GP
:
7673 func (stream
, "32");
7678 func (stream
, "16");
7681 case 8: case 9: case 10: case 11:
7682 case 12: case 13: case 14: case 15:
7691 case MVE_VMOV_IMM_TO_VEC
:
7694 case 0: case 4: case 8:
7695 case 12: case 24: case 26:
7696 func (stream
, "i32");
7699 func (stream
, "i16");
7702 func (stream
, "i8");
7705 func (stream
, "i64");
7708 func (stream
, "f32");
7715 case MVE_VMULL_POLY
:
7717 func (stream
, "p8");
7719 func (stream
, "p16");
7725 case 0: case 2: case 4:
7726 case 6: case 12: case 13:
7727 func (stream
, "32");
7731 func (stream
, "16");
7745 func (stream
, "32");
7749 func (stream
, "16");
7767 func (stream
, "16");
7771 func (stream
, "32");
7796 func (stream
, "16");
7799 case 4: case 5: case 6: case 7:
7800 func (stream
, "32");
7815 print_mve_shift_n (struct disassemble_info
*info
, long given
,
7816 enum mve_instructions matched_insn
)
7818 void *stream
= info
->stream
;
7819 fprintf_ftype func
= info
->fprintf_func
;
7822 = matched_insn
== MVE_VQSHL_T2
7823 || matched_insn
== MVE_VQSHLU_T3
7824 || matched_insn
== MVE_VSHL_T1
7825 || matched_insn
== MVE_VSHLL_T1
7826 || matched_insn
== MVE_VSLI
;
7828 unsigned imm6
= (given
& 0x3f0000) >> 16;
7830 if (matched_insn
== MVE_VSHLL_T1
)
7833 unsigned shiftAmount
= 0;
7834 if ((imm6
& 0x20) != 0)
7835 shiftAmount
= startAt0
? imm6
- 32 : 64 - imm6
;
7836 else if ((imm6
& 0x10) != 0)
7837 shiftAmount
= startAt0
? imm6
- 16 : 32 - imm6
;
7838 else if ((imm6
& 0x08) != 0)
7839 shiftAmount
= startAt0
? imm6
- 8 : 16 - imm6
;
7841 print_mve_undefined (info
, UNDEF_SIZE_0
);
7843 func (stream
, "%u", shiftAmount
);
7847 print_vec_condition (struct disassemble_info
*info
, long given
,
7848 enum mve_instructions matched_insn
)
7850 void *stream
= info
->stream
;
7851 fprintf_ftype func
= info
->fprintf_func
;
7854 switch (matched_insn
)
7857 case MVE_VCMP_FP_T1
:
7858 vec_cond
= (((given
& 0x1000) >> 10)
7859 | ((given
& 1) << 1)
7860 | ((given
& 0x0080) >> 7));
7861 func (stream
, "%s",vec_condnames
[vec_cond
]);
7865 case MVE_VCMP_FP_T2
:
7866 vec_cond
= (((given
& 0x1000) >> 10)
7867 | ((given
& 0x0020) >> 4)
7868 | ((given
& 0x0080) >> 7));
7869 func (stream
, "%s",vec_condnames
[vec_cond
]);
7872 case MVE_VPT_VEC_T1
:
7873 case MVE_VCMP_VEC_T1
:
7874 vec_cond
= (given
& 0x0080) >> 7;
7875 func (stream
, "%s",vec_condnames
[vec_cond
]);
7878 case MVE_VPT_VEC_T2
:
7879 case MVE_VCMP_VEC_T2
:
7880 vec_cond
= 2 | ((given
& 0x0080) >> 7);
7881 func (stream
, "%s",vec_condnames
[vec_cond
]);
7884 case MVE_VPT_VEC_T3
:
7885 case MVE_VCMP_VEC_T3
:
7886 vec_cond
= 4 | ((given
& 1) << 1) | ((given
& 0x0080) >> 7);
7887 func (stream
, "%s",vec_condnames
[vec_cond
]);
7890 case MVE_VPT_VEC_T4
:
7891 case MVE_VCMP_VEC_T4
:
7892 vec_cond
= (given
& 0x0080) >> 7;
7893 func (stream
, "%s",vec_condnames
[vec_cond
]);
7896 case MVE_VPT_VEC_T5
:
7897 case MVE_VCMP_VEC_T5
:
7898 vec_cond
= 2 | ((given
& 0x0080) >> 7);
7899 func (stream
, "%s",vec_condnames
[vec_cond
]);
7902 case MVE_VPT_VEC_T6
:
7903 case MVE_VCMP_VEC_T6
:
7904 vec_cond
= 4 | ((given
& 0x0020) >> 4) | ((given
& 0x0080) >> 7);
7905 func (stream
, "%s",vec_condnames
[vec_cond
]);
7920 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7921 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7922 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7923 #define PRE_BIT_SET (given & (1 << P_BIT))
7926 /* Print one coprocessor instruction on INFO->STREAM.
7927 Return TRUE if the instuction matched, FALSE if this is not a
7928 recognised coprocessor instruction. */
7931 print_insn_coprocessor_1 (const struct sopcode32
*opcodes
,
7933 struct disassemble_info
*info
,
7937 const struct sopcode32
*insn
;
7938 void *stream
= info
->stream
;
7939 fprintf_ftype func
= info
->fprintf_func
;
7941 unsigned long value
= 0;
7944 struct arm_private_data
*private_data
= info
->private_data
;
7945 arm_feature_set allowed_arches
= ARM_ARCH_NONE
;
7946 arm_feature_set arm_ext_v8_1m_main
=
7947 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
7949 allowed_arches
= private_data
->features
;
7951 for (insn
= opcodes
; insn
->assembler
; insn
++)
7953 unsigned long u_reg
= 16;
7954 bfd_boolean is_unpredictable
= FALSE
;
7955 signed long value_in_comment
= 0;
7958 if (ARM_FEATURE_ZERO (insn
->arch
))
7959 switch (insn
->value
)
7961 case SENTINEL_IWMMXT_START
:
7962 if (info
->mach
!= bfd_mach_arm_XScale
7963 && info
->mach
!= bfd_mach_arm_iWMMXt
7964 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
7967 while ((! ARM_FEATURE_ZERO (insn
->arch
))
7968 && insn
->value
!= SENTINEL_IWMMXT_END
);
7971 case SENTINEL_IWMMXT_END
:
7974 case SENTINEL_GENERIC_START
:
7975 allowed_arches
= private_data
->features
;
7983 value
= insn
->value
;
7984 cp_num
= (given
>> 8) & 0xf;
7988 /* The high 4 bits are 0xe for Arm conditional instructions, and
7989 0xe for arm unconditional instructions. The rest of the
7990 encoding is the same. */
7992 value
|= 0xe0000000;
8000 /* Only match unconditional instuctions against unconditional
8002 if ((given
& 0xf0000000) == 0xf0000000)
8009 cond
= (given
>> 28) & 0xf;
8015 if ((insn
->isa
== T32
&& !thumb
)
8016 || (insn
->isa
== ARM
&& thumb
))
8019 if ((given
& mask
) != value
)
8022 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, allowed_arches
))
8025 if (insn
->value
== 0xfe000010 /* mcr2 */
8026 || insn
->value
== 0xfe100010 /* mrc2 */
8027 || insn
->value
== 0xfc100000 /* ldc2 */
8028 || insn
->value
== 0xfc000000) /* stc2 */
8030 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
8031 is_unpredictable
= TRUE
;
8033 /* Armv8.1-M Mainline FP & MVE instructions. */
8034 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
8035 && !ARM_CPU_IS_ANY (allowed_arches
)
8036 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
8040 else if (insn
->value
== 0x0e000000 /* cdp */
8041 || insn
->value
== 0xfe000000 /* cdp2 */
8042 || insn
->value
== 0x0e000010 /* mcr */
8043 || insn
->value
== 0x0e100010 /* mrc */
8044 || insn
->value
== 0x0c100000 /* ldc */
8045 || insn
->value
== 0x0c000000) /* stc */
8047 /* Floating-point instructions. */
8048 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
8051 /* Armv8.1-M Mainline FP & MVE instructions. */
8052 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
8053 && !ARM_CPU_IS_ANY (allowed_arches
)
8054 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
8057 else if ((insn
->value
== 0xec100f80 /* vldr (system register) */
8058 || insn
->value
== 0xec000f80) /* vstr (system register) */
8059 && arm_decode_field (given
, 24, 24) == 0
8060 && arm_decode_field (given
, 21, 21) == 0)
8061 /* If the P and W bits are both 0 then these encodings match the MVE
8062 VLDR and VSTR instructions, these are in a different table, so we
8063 don't let it match here. */
8066 for (c
= insn
->assembler
; *c
; c
++)
8070 const char mod
= *++c
;
8074 func (stream
, "%%");
8080 int rn
= (given
>> 16) & 0xf;
8081 bfd_vma offset
= given
& 0xff;
8084 offset
= given
& 0x7f;
8086 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
8088 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
8090 /* Not unindexed. The offset is scaled. */
8092 /* vldr.16/vstr.16 will shift the address
8093 left by 1 bit only. */
8094 offset
= offset
* 2;
8096 offset
= offset
* 4;
8098 if (NEGATIVE_BIT_SET
)
8101 value_in_comment
= offset
;
8107 func (stream
, ", #%d]%s",
8109 WRITEBACK_BIT_SET
? "!" : "");
8110 else if (NEGATIVE_BIT_SET
)
8111 func (stream
, ", #-0]");
8119 if (WRITEBACK_BIT_SET
)
8122 func (stream
, ", #%d", (int) offset
);
8123 else if (NEGATIVE_BIT_SET
)
8124 func (stream
, ", #-0");
8128 func (stream
, ", {%s%d}",
8129 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
8131 value_in_comment
= offset
;
8134 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
8136 func (stream
, "\t; ");
8137 /* For unaligned PCs, apply off-by-alignment
8139 info
->print_address_func (offset
+ pc
8140 + info
->bytes_per_chunk
* 2
8149 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
8150 int offset
= (given
>> 1) & 0x3f;
8153 func (stream
, "{d%d}", regno
);
8154 else if (regno
+ offset
> 32)
8155 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
8157 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
8163 bfd_boolean single
= ((given
>> 8) & 1) == 0;
8164 char reg_prefix
= single
? 's' : 'd';
8165 int Dreg
= (given
>> 22) & 0x1;
8166 int Vdreg
= (given
>> 12) & 0xf;
8167 int reg
= single
? ((Vdreg
<< 1) | Dreg
)
8168 : ((Dreg
<< 4) | Vdreg
);
8169 int num
= (given
>> (single
? 0 : 1)) & 0x7f;
8170 int maxreg
= single
? 31 : 15;
8171 int topreg
= reg
+ num
- 1;
8174 func (stream
, "{VPR}");
8176 func (stream
, "{%c%d, VPR}", reg_prefix
, reg
);
8177 else if (topreg
> maxreg
)
8178 func (stream
, "{%c%d-<overflow reg d%d, VPR}",
8179 reg_prefix
, reg
, single
? topreg
>> 1 : topreg
);
8181 func (stream
, "{%c%d-%c%d, VPR}", reg_prefix
, reg
,
8182 reg_prefix
, topreg
);
8187 if (cond
!= COND_UNCOND
)
8188 is_unpredictable
= TRUE
;
8192 if (cond
!= COND_UNCOND
&& cp_num
== 9)
8193 is_unpredictable
= TRUE
;
8197 func (stream
, "%s", arm_conditional
[cond
]);
8201 /* Print a Cirrus/DSP shift immediate. */
8202 /* Immediates are 7bit signed ints with bits 0..3 in
8203 bits 0..3 of opcode and bits 4..6 in bits 5..7
8208 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
8210 /* Is ``imm'' a negative number? */
8214 func (stream
, "%d", imm
);
8222 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
8227 func (stream
, "FPSCR");
8230 func (stream
, "FPSCR_nzcvqc");
8233 func (stream
, "VPR");
8236 func (stream
, "P0");
8239 func (stream
, "FPCXTNS");
8242 func (stream
, "FPCXTS");
8245 func (stream
, "<invalid reg %lu>", regno
);
8252 switch (given
& 0x00408000)
8269 switch (given
& 0x00080080)
8281 func (stream
, _("<illegal precision>"));
8287 switch (given
& 0x00408000)
8305 switch (given
& 0x60)
8321 case '0': case '1': case '2': case '3': case '4':
8322 case '5': case '6': case '7': case '8': case '9':
8326 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8332 is_unpredictable
= TRUE
;
8337 /* Eat the 'u' character. */
8341 is_unpredictable
= TRUE
;
8344 func (stream
, "%s", arm_regnames
[value
]);
8347 if (given
& (1 << 6))
8351 func (stream
, "d%ld", value
);
8356 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
8358 func (stream
, "q%ld", value
>> 1);
8361 func (stream
, "%ld", value
);
8362 value_in_comment
= value
;
8366 /* Converts immediate 8 bit back to float value. */
8367 unsigned floatVal
= (value
& 0x80) << 24
8368 | (value
& 0x3F) << 19
8369 | ((value
& 0x40) ? (0xF8 << 22) : (1 << 30));
8371 /* Quarter float have a maximum value of 31.0.
8372 Get floating point value multiplied by 1e7.
8373 The maximum value stays in limit of a 32-bit int. */
8375 (78125 << (((floatVal
>> 23) & 0xFF) - 124)) *
8376 (16 + (value
& 0xF));
8378 if (!(decVal
% 1000000))
8379 func (stream
, "%ld\t; 0x%08x %c%u.%01u", value
,
8380 floatVal
, value
& 0x80 ? '-' : ' ',
8382 decVal
% 10000000 / 1000000);
8383 else if (!(decVal
% 10000))
8384 func (stream
, "%ld\t; 0x%08x %c%u.%03u", value
,
8385 floatVal
, value
& 0x80 ? '-' : ' ',
8387 decVal
% 10000000 / 10000);
8389 func (stream
, "%ld\t; 0x%08x %c%u.%07u", value
,
8390 floatVal
, value
& 0x80 ? '-' : ' ',
8391 decVal
/ 10000000, decVal
% 10000000);
8396 int from
= (given
& (1 << 7)) ? 32 : 16;
8397 func (stream
, "%ld", from
- value
);
8403 func (stream
, "#%s", arm_fp_const
[value
& 7]);
8405 func (stream
, "f%ld", value
);
8410 func (stream
, "%s", iwmmxt_wwnames
[value
]);
8412 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
8416 func (stream
, "%s", iwmmxt_regnames
[value
]);
8419 func (stream
, "%s", iwmmxt_cregnames
[value
]);
8423 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
8430 func (stream
, "eq");
8434 func (stream
, "vs");
8438 func (stream
, "ge");
8442 func (stream
, "gt");
8446 func (stream
, "??");
8454 func (stream
, "%c", *c
);
8458 if (value
== ((1ul << width
) - 1))
8459 func (stream
, "%c", *c
);
8462 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
8474 int single
= *c
++ == 'y';
8479 case '4': /* Sm pair */
8480 case '0': /* Sm, Dm */
8481 regno
= given
& 0x0000000f;
8485 regno
+= (given
>> 5) & 1;
8488 regno
+= ((given
>> 5) & 1) << 4;
8491 case '1': /* Sd, Dd */
8492 regno
= (given
>> 12) & 0x0000000f;
8496 regno
+= (given
>> 22) & 1;
8499 regno
+= ((given
>> 22) & 1) << 4;
8502 case '2': /* Sn, Dn */
8503 regno
= (given
>> 16) & 0x0000000f;
8507 regno
+= (given
>> 7) & 1;
8510 regno
+= ((given
>> 7) & 1) << 4;
8513 case '3': /* List */
8515 regno
= (given
>> 12) & 0x0000000f;
8519 regno
+= (given
>> 22) & 1;
8522 regno
+= ((given
>> 22) & 1) << 4;
8529 func (stream
, "%c%d", single
? 's' : 'd', regno
);
8533 int count
= given
& 0xff;
8540 func (stream
, "-%c%d",
8548 func (stream
, ", %c%d", single
? 's' : 'd',
8554 switch (given
& 0x00400100)
8556 case 0x00000000: func (stream
, "b"); break;
8557 case 0x00400000: func (stream
, "h"); break;
8558 case 0x00000100: func (stream
, "w"); break;
8559 case 0x00400100: func (stream
, "d"); break;
8567 /* given (20, 23) | given (0, 3) */
8568 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
8569 func (stream
, "%d", (int) value
);
8574 /* This is like the 'A' operator, except that if
8575 the width field "M" is zero, then the offset is
8576 *not* multiplied by four. */
8578 int offset
= given
& 0xff;
8579 int multiplier
= (given
& 0x00000100) ? 4 : 1;
8581 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
8585 value_in_comment
= offset
* multiplier
;
8586 if (NEGATIVE_BIT_SET
)
8587 value_in_comment
= - value_in_comment
;
8593 func (stream
, ", #%s%d]%s",
8594 NEGATIVE_BIT_SET
? "-" : "",
8595 offset
* multiplier
,
8596 WRITEBACK_BIT_SET
? "!" : "");
8598 func (stream
, "], #%s%d",
8599 NEGATIVE_BIT_SET
? "-" : "",
8600 offset
* multiplier
);
8609 int imm4
= (given
>> 4) & 0xf;
8610 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
8611 int ubit
= ! NEGATIVE_BIT_SET
;
8612 const char *rm
= arm_regnames
[given
& 0xf];
8613 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
8619 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
8621 func (stream
, ", lsl #%d", imm4
);
8628 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
8630 func (stream
, ", lsl #%d", imm4
);
8632 if (puw_bits
== 5 || puw_bits
== 7)
8637 func (stream
, "INVALID");
8645 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
8646 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
8655 func (stream
, "%c", *c
);
8658 if (value_in_comment
> 32 || value_in_comment
< -16)
8659 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
8661 if (is_unpredictable
)
8662 func (stream
, UNPREDICTABLE_INSTRUCTION
);
8670 print_insn_coprocessor (bfd_vma pc
,
8671 struct disassemble_info
*info
,
8675 return print_insn_coprocessor_1 (coprocessor_opcodes
,
8676 pc
, info
, given
, thumb
);
8680 print_insn_generic_coprocessor (bfd_vma pc
,
8681 struct disassemble_info
*info
,
8685 return print_insn_coprocessor_1 (generic_coprocessor_opcodes
,
8686 pc
, info
, given
, thumb
);
8689 /* Decodes and prints ARM addressing modes. Returns the offset
8690 used in the address, if any, if it is worthwhile printing the
8691 offset as a hexadecimal value in a comment at the end of the
8692 line of disassembly. */
8695 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8697 void *stream
= info
->stream
;
8698 fprintf_ftype func
= info
->fprintf_func
;
8701 if (((given
& 0x000f0000) == 0x000f0000)
8702 && ((given
& 0x02000000) == 0))
8704 offset
= given
& 0xfff;
8706 func (stream
, "[pc");
8710 /* Pre-indexed. Elide offset of positive zero when
8712 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
8713 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8715 if (NEGATIVE_BIT_SET
)
8720 /* Cope with the possibility of write-back
8721 being used. Probably a very dangerous thing
8722 for the programmer to do, but who are we to
8724 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
8726 else /* Post indexed. */
8728 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8730 /* Ie ignore the offset. */
8734 func (stream
, "\t; ");
8735 info
->print_address_func (offset
, info
);
8740 func (stream
, "[%s",
8741 arm_regnames
[(given
>> 16) & 0xf]);
8745 if ((given
& 0x02000000) == 0)
8747 /* Elide offset of positive zero when non-writeback. */
8748 offset
= given
& 0xfff;
8749 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
8750 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8754 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
8755 arm_decode_shift (given
, func
, stream
, TRUE
);
8758 func (stream
, "]%s",
8759 WRITEBACK_BIT_SET
? "!" : "");
8763 if ((given
& 0x02000000) == 0)
8765 /* Always show offset. */
8766 offset
= given
& 0xfff;
8767 func (stream
, "], #%s%d",
8768 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8772 func (stream
, "], %s",
8773 NEGATIVE_BIT_SET
? "-" : "");
8774 arm_decode_shift (given
, func
, stream
, TRUE
);
8777 if (NEGATIVE_BIT_SET
)
8781 return (signed long) offset
;
8784 /* Print one neon instruction on INFO->STREAM.
8785 Return TRUE if the instuction matched, FALSE if this is not a
8786 recognised neon instruction. */
8789 print_insn_neon (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
8791 const struct opcode32
*insn
;
8792 void *stream
= info
->stream
;
8793 fprintf_ftype func
= info
->fprintf_func
;
8797 if ((given
& 0xef000000) == 0xef000000)
8799 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
8800 unsigned long bit28
= given
& (1 << 28);
8802 given
&= 0x00ffffff;
8804 given
|= 0xf3000000;
8806 given
|= 0xf2000000;
8808 else if ((given
& 0xff000000) == 0xf9000000)
8809 given
^= 0xf9000000 ^ 0xf4000000;
8810 /* BFloat16 neon instructions without special top byte handling. */
8811 else if ((given
& 0xff000000) == 0xfe000000
8812 || (given
& 0xff000000) == 0xfc000000)
8814 /* vdup is also a valid neon instruction. */
8815 else if ((given
& 0xff910f5f) != 0xee800b10)
8819 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
8821 if ((given
& insn
->mask
) == insn
->value
)
8823 signed long value_in_comment
= 0;
8824 bfd_boolean is_unpredictable
= FALSE
;
8827 for (c
= insn
->assembler
; *c
; c
++)
8834 func (stream
, "%%");
8838 if (thumb
&& ifthen_state
)
8839 is_unpredictable
= TRUE
;
8843 if (thumb
&& ifthen_state
)
8844 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
8849 static const unsigned char enc
[16] =
8851 0x4, 0x14, /* st4 0,1 */
8863 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
8864 int rn
= ((given
>> 16) & 0xf);
8865 int rm
= ((given
>> 0) & 0xf);
8866 int align
= ((given
>> 4) & 0x3);
8867 int type
= ((given
>> 8) & 0xf);
8868 int n
= enc
[type
] & 0xf;
8869 int stride
= (enc
[type
] >> 4) + 1;
8874 for (ix
= 0; ix
!= n
; ix
++)
8875 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
8877 func (stream
, "d%d", rd
);
8879 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
8880 func (stream
, "}, [%s", arm_regnames
[rn
]);
8882 func (stream
, " :%d", 32 << align
);
8887 func (stream
, ", %s", arm_regnames
[rm
]);
8893 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
8894 int rn
= ((given
>> 16) & 0xf);
8895 int rm
= ((given
>> 0) & 0xf);
8896 int idx_align
= ((given
>> 4) & 0xf);
8898 int size
= ((given
>> 10) & 0x3);
8899 int idx
= idx_align
>> (size
+ 1);
8900 int length
= ((given
>> 8) & 3) + 1;
8904 if (length
> 1 && size
> 0)
8905 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
8911 int amask
= (1 << size
) - 1;
8912 if ((idx_align
& (1 << size
)) != 0)
8916 if ((idx_align
& amask
) == amask
)
8918 else if ((idx_align
& amask
) != 0)
8925 if (size
== 2 && (idx_align
& 2) != 0)
8927 align
= (idx_align
& 1) ? 16 << size
: 0;
8931 if ((size
== 2 && (idx_align
& 3) != 0)
8932 || (idx_align
& 1) != 0)
8939 if ((idx_align
& 3) == 3)
8941 align
= (idx_align
& 3) * 64;
8944 align
= (idx_align
& 1) ? 32 << size
: 0;
8952 for (i
= 0; i
< length
; i
++)
8953 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
8954 rd
+ i
* stride
, idx
);
8955 func (stream
, "}, [%s", arm_regnames
[rn
]);
8957 func (stream
, " :%d", align
);
8962 func (stream
, ", %s", arm_regnames
[rm
]);
8968 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
8969 int rn
= ((given
>> 16) & 0xf);
8970 int rm
= ((given
>> 0) & 0xf);
8971 int align
= ((given
>> 4) & 0x1);
8972 int size
= ((given
>> 6) & 0x3);
8973 int type
= ((given
>> 8) & 0x3);
8975 int stride
= ((given
>> 5) & 0x1);
8978 if (stride
&& (n
== 1))
8985 for (ix
= 0; ix
!= n
; ix
++)
8986 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
8988 func (stream
, "d%d[]", rd
);
8990 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
8991 func (stream
, "}, [%s", arm_regnames
[rn
]);
8994 align
= (8 * (type
+ 1)) << size
;
8996 align
= (size
> 1) ? align
>> 1 : align
;
8997 if (type
== 2 || (type
== 0 && !size
))
8998 func (stream
, " :<bad align %d>", align
);
9000 func (stream
, " :%d", align
);
9006 func (stream
, ", %s", arm_regnames
[rm
]);
9012 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
9013 int size
= (given
>> 20) & 3;
9014 int reg
= raw_reg
& ((4 << size
) - 1);
9015 int ix
= raw_reg
>> size
>> 2;
9017 func (stream
, "d%d[%d]", reg
, ix
);
9022 /* Neon encoded constant for mov, mvn, vorr, vbic. */
9025 int cmode
= (given
>> 8) & 0xf;
9026 int op
= (given
>> 5) & 0x1;
9027 unsigned long value
= 0, hival
= 0;
9032 bits
|= ((given
>> 24) & 1) << 7;
9033 bits
|= ((given
>> 16) & 7) << 4;
9034 bits
|= ((given
>> 0) & 15) << 0;
9038 shift
= (cmode
>> 1) & 3;
9039 value
= (unsigned long) bits
<< (8 * shift
);
9042 else if (cmode
< 12)
9044 shift
= (cmode
>> 1) & 1;
9045 value
= (unsigned long) bits
<< (8 * shift
);
9048 else if (cmode
< 14)
9050 shift
= (cmode
& 1) + 1;
9051 value
= (unsigned long) bits
<< (8 * shift
);
9052 value
|= (1ul << (8 * shift
)) - 1;
9055 else if (cmode
== 14)
9059 /* Bit replication into bytes. */
9065 for (ix
= 7; ix
>= 0; ix
--)
9067 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
9069 value
= (value
<< 8) | mask
;
9071 hival
= (hival
<< 8) | mask
;
9077 /* Byte replication. */
9078 value
= (unsigned long) bits
;
9084 /* Floating point encoding. */
9087 value
= (unsigned long) (bits
& 0x7f) << 19;
9088 value
|= (unsigned long) (bits
& 0x80) << 24;
9089 tmp
= bits
& 0x40 ? 0x3c : 0x40;
9090 value
|= (unsigned long) tmp
<< 24;
9096 func (stream
, "<illegal constant %.8x:%x:%x>",
9104 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
9108 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
9114 unsigned char valbytes
[4];
9117 /* Do this a byte at a time so we don't have to
9118 worry about the host's endianness. */
9119 valbytes
[0] = value
& 0xff;
9120 valbytes
[1] = (value
>> 8) & 0xff;
9121 valbytes
[2] = (value
>> 16) & 0xff;
9122 valbytes
[3] = (value
>> 24) & 0xff;
9124 floatformat_to_double
9125 (& floatformat_ieee_single_little
, valbytes
,
9128 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
9132 func (stream
, "#%ld\t; 0x%.8lx",
9133 (long) (((value
& 0x80000000L
) != 0)
9134 ? value
| ~0xffffffffL
: value
),
9139 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
9150 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
9151 int num
= (given
>> 8) & 0x3;
9154 func (stream
, "{d%d}", regno
);
9155 else if (num
+ regno
>= 32)
9156 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
9158 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
9163 case '0': case '1': case '2': case '3': case '4':
9164 case '5': case '6': case '7': case '8': case '9':
9167 unsigned long value
;
9169 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
9174 func (stream
, "%s", arm_regnames
[value
]);
9177 func (stream
, "%ld", value
);
9178 value_in_comment
= value
;
9181 func (stream
, "%ld", (1ul << width
) - value
);
9187 /* Various width encodings. */
9189 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
9194 if (*c
>= '0' && *c
<= '9')
9196 else if (*c
>= 'a' && *c
<= 'f')
9197 limit
= *c
- 'a' + 10;
9203 if (value
< low
|| value
> high
)
9204 func (stream
, "<illegal width %d>", base
<< value
);
9206 func (stream
, "%d", base
<< value
);
9210 if (given
& (1 << 6))
9214 func (stream
, "d%ld", value
);
9219 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
9221 func (stream
, "q%ld", value
>> 1);
9227 func (stream
, "%c", *c
);
9231 if (value
== ((1ul << width
) - 1))
9232 func (stream
, "%c", *c
);
9235 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
9249 func (stream
, "%c", *c
);
9252 if (value_in_comment
> 32 || value_in_comment
< -16)
9253 func (stream
, "\t; 0x%lx", value_in_comment
);
9255 if (is_unpredictable
)
9256 func (stream
, UNPREDICTABLE_INSTRUCTION
);
9264 /* Print one mve instruction on INFO->STREAM.
9265 Return TRUE if the instuction matched, FALSE if this is not a
9266 recognised mve instruction. */
9269 print_insn_mve (struct disassemble_info
*info
, long given
)
9271 const struct mopcode32
*insn
;
9272 void *stream
= info
->stream
;
9273 fprintf_ftype func
= info
->fprintf_func
;
9275 for (insn
= mve_opcodes
; insn
->assembler
; insn
++)
9277 if (((given
& insn
->mask
) == insn
->value
)
9278 && !is_mve_encoding_conflict (given
, insn
->mve_op
))
9280 signed long value_in_comment
= 0;
9281 bfd_boolean is_unpredictable
= FALSE
;
9282 bfd_boolean is_undefined
= FALSE
;
9284 enum mve_unpredictable unpredictable_cond
= UNPRED_NONE
;
9285 enum mve_undefined undefined_cond
= UNDEF_NONE
;
9287 /* Most vector mve instruction are illegal in a it block.
9288 There are a few exceptions; check for them. */
9289 if (ifthen_state
&& !is_mve_okay_in_it (insn
->mve_op
))
9291 is_unpredictable
= TRUE
;
9292 unpredictable_cond
= UNPRED_IT_BLOCK
;
9294 else if (is_mve_unpredictable (given
, insn
->mve_op
,
9295 &unpredictable_cond
))
9296 is_unpredictable
= TRUE
;
9298 if (is_mve_undefined (given
, insn
->mve_op
, &undefined_cond
))
9299 is_undefined
= TRUE
;
9301 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9302 i.e "VMOV Qd, Qm". */
9303 if ((insn
->mve_op
== MVE_VORR_REG
)
9304 && (arm_decode_field (given
, 1, 3)
9305 == arm_decode_field (given
, 17, 19)))
9308 for (c
= insn
->assembler
; *c
; c
++)
9315 func (stream
, "%%");
9319 /* Don't print anything for '+' as it is implied. */
9320 if (arm_decode_field (given
, 23, 23) == 0)
9326 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
9330 print_mve_vld_str_addr (info
, given
, insn
->mve_op
);
9335 long mve_mask
= mve_extract_pred_mask (given
);
9336 func (stream
, "%s", mve_predicatenames
[mve_mask
]);
9342 unsigned int imm5
= 0;
9343 imm5
|= arm_decode_field (given
, 6, 7);
9344 imm5
|= (arm_decode_field (given
, 12, 14) << 2);
9345 func (stream
, "#%u", (imm5
== 0) ? 32 : imm5
);
9350 func (stream
, "#%u",
9351 (arm_decode_field (given
, 7, 7) == 0) ? 64 : 48);
9355 print_vec_condition (info
, given
, insn
->mve_op
);
9359 if (arm_decode_field (given
, 0, 0) == 1)
9362 = arm_decode_field (given
, 4, 4)
9363 | (arm_decode_field (given
, 6, 6) << 1);
9365 func (stream
, ", uxtw #%lu", size
);
9370 print_mve_rounding_mode (info
, given
, insn
->mve_op
);
9374 print_mve_vcvt_size (info
, given
, insn
->mve_op
);
9379 unsigned long op1
= arm_decode_field (given
, 21, 22);
9381 if ((insn
->mve_op
== MVE_VMOV_VEC_LANE_TO_GP
))
9383 /* Check for signed. */
9384 if (arm_decode_field (given
, 23, 23) == 0)
9386 /* We don't print 's' for S32. */
9387 if ((arm_decode_field (given
, 5, 6) == 0)
9388 && ((op1
== 0) || (op1
== 1)))
9398 if (arm_decode_field (given
, 28, 28) == 0)
9407 print_instruction_predicate (info
);
9411 if (arm_decode_field (given
, 21, 21) == 1)
9416 print_mve_register_blocks (info
, given
, insn
->mve_op
);
9420 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9422 print_simd_imm8 (info
, given
, 28, insn
);
9426 print_mve_vmov_index (info
, given
);
9430 if (arm_decode_field (given
, 12, 12) == 0)
9437 if (arm_decode_field (given
, 12, 12) == 1)
9441 case '0': case '1': case '2': case '3': case '4':
9442 case '5': case '6': case '7': case '8': case '9':
9445 unsigned long value
;
9447 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
9453 is_unpredictable
= TRUE
;
9454 else if (value
== 15)
9455 func (stream
, "zr");
9457 func (stream
, "%s", arm_regnames
[value
]);
9461 func (stream
, "%s", arm_conditional
[value
]);
9466 func (stream
, "%s", arm_conditional
[value
]);
9470 if (value
== 13 || value
== 15)
9471 is_unpredictable
= TRUE
;
9473 func (stream
, "%s", arm_regnames
[value
]);
9477 print_mve_size (info
,
9491 unsigned int odd_reg
= (value
<< 1) | 1;
9492 func (stream
, "%s", arm_regnames
[odd_reg
]);
9498 = arm_decode_field (given
, 0, 6);
9499 unsigned long mod_imm
= imm
;
9501 switch (insn
->mve_op
)
9503 case MVE_VLDRW_GATHER_T5
:
9504 case MVE_VSTRW_SCATTER_T5
:
9505 mod_imm
= mod_imm
<< 2;
9507 case MVE_VSTRD_SCATTER_T6
:
9508 case MVE_VLDRD_GATHER_T6
:
9509 mod_imm
= mod_imm
<< 3;
9516 func (stream
, "%lu", mod_imm
);
9520 func (stream
, "%lu", 64 - value
);
9524 unsigned int even_reg
= value
<< 1;
9525 func (stream
, "%s", arm_regnames
[even_reg
]);
9548 print_mve_rotate (info
, value
, width
);
9551 func (stream
, "%s", arm_regnames
[value
]);
9554 if (insn
->mve_op
== MVE_VQSHL_T2
9555 || insn
->mve_op
== MVE_VQSHLU_T3
9556 || insn
->mve_op
== MVE_VRSHR
9557 || insn
->mve_op
== MVE_VRSHRN
9558 || insn
->mve_op
== MVE_VSHL_T1
9559 || insn
->mve_op
== MVE_VSHLL_T1
9560 || insn
->mve_op
== MVE_VSHR
9561 || insn
->mve_op
== MVE_VSHRN
9562 || insn
->mve_op
== MVE_VSLI
9563 || insn
->mve_op
== MVE_VSRI
)
9564 print_mve_shift_n (info
, given
, insn
->mve_op
);
9565 else if (insn
->mve_op
== MVE_VSHLL_T2
)
9573 func (stream
, "16");
9576 print_mve_undefined (info
, UNDEF_SIZE_0
);
9585 if (insn
->mve_op
== MVE_VSHLC
&& value
== 0)
9587 func (stream
, "%ld", value
);
9588 value_in_comment
= value
;
9592 func (stream
, "s%ld", value
);
9596 func (stream
, "<illegal reg q%ld.5>", value
);
9598 func (stream
, "q%ld", value
);
9601 func (stream
, "0x%08lx", value
);
9613 func (stream
, "%c", *c
);
9616 if (value_in_comment
> 32 || value_in_comment
< -16)
9617 func (stream
, "\t; 0x%lx", value_in_comment
);
9619 if (is_unpredictable
)
9620 print_mve_unpredictable (info
, unpredictable_cond
);
9623 print_mve_undefined (info
, undefined_cond
);
9625 if ((vpt_block_state
.in_vpt_block
== FALSE
)
9627 && (is_vpt_instruction (given
) == TRUE
))
9628 mark_inside_vpt_block (given
);
9629 else if (vpt_block_state
.in_vpt_block
== TRUE
)
9630 update_vpt_block_state ();
9639 /* Return the name of a v7A special register. */
9642 banked_regname (unsigned reg
)
9646 case 15: return "CPSR";
9647 case 32: return "R8_usr";
9648 case 33: return "R9_usr";
9649 case 34: return "R10_usr";
9650 case 35: return "R11_usr";
9651 case 36: return "R12_usr";
9652 case 37: return "SP_usr";
9653 case 38: return "LR_usr";
9654 case 40: return "R8_fiq";
9655 case 41: return "R9_fiq";
9656 case 42: return "R10_fiq";
9657 case 43: return "R11_fiq";
9658 case 44: return "R12_fiq";
9659 case 45: return "SP_fiq";
9660 case 46: return "LR_fiq";
9661 case 48: return "LR_irq";
9662 case 49: return "SP_irq";
9663 case 50: return "LR_svc";
9664 case 51: return "SP_svc";
9665 case 52: return "LR_abt";
9666 case 53: return "SP_abt";
9667 case 54: return "LR_und";
9668 case 55: return "SP_und";
9669 case 60: return "LR_mon";
9670 case 61: return "SP_mon";
9671 case 62: return "ELR_hyp";
9672 case 63: return "SP_hyp";
9673 case 79: return "SPSR";
9674 case 110: return "SPSR_fiq";
9675 case 112: return "SPSR_irq";
9676 case 114: return "SPSR_svc";
9677 case 116: return "SPSR_abt";
9678 case 118: return "SPSR_und";
9679 case 124: return "SPSR_mon";
9680 case 126: return "SPSR_hyp";
9681 default: return NULL
;
9685 /* Return the name of the DMB/DSB option. */
9687 data_barrier_option (unsigned option
)
9689 switch (option
& 0xf)
9691 case 0xf: return "sy";
9692 case 0xe: return "st";
9693 case 0xd: return "ld";
9694 case 0xb: return "ish";
9695 case 0xa: return "ishst";
9696 case 0x9: return "ishld";
9697 case 0x7: return "un";
9698 case 0x6: return "unst";
9699 case 0x5: return "nshld";
9700 case 0x3: return "osh";
9701 case 0x2: return "oshst";
9702 case 0x1: return "oshld";
9703 default: return NULL
;
9707 /* Print one ARM instruction from PC on INFO->STREAM. */
9710 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
9712 const struct opcode32
*insn
;
9713 void *stream
= info
->stream
;
9714 fprintf_ftype func
= info
->fprintf_func
;
9715 struct arm_private_data
*private_data
= info
->private_data
;
9717 if (print_insn_coprocessor (pc
, info
, given
, FALSE
))
9720 if (print_insn_neon (info
, given
, FALSE
))
9723 if (print_insn_generic_coprocessor (pc
, info
, given
, FALSE
))
9726 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
9728 if ((given
& insn
->mask
) != insn
->value
)
9731 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, private_data
->features
))
9734 /* Special case: an instruction with all bits set in the condition field
9735 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9736 or by the catchall at the end of the table. */
9737 if ((given
& 0xF0000000) != 0xF0000000
9738 || (insn
->mask
& 0xF0000000) == 0xF0000000
9739 || (insn
->mask
== 0 && insn
->value
== 0))
9741 unsigned long u_reg
= 16;
9742 unsigned long U_reg
= 16;
9743 bfd_boolean is_unpredictable
= FALSE
;
9744 signed long value_in_comment
= 0;
9747 for (c
= insn
->assembler
; *c
; c
++)
9751 bfd_boolean allow_unpredictable
= FALSE
;
9756 func (stream
, "%%");
9760 value_in_comment
= print_arm_address (pc
, info
, given
);
9764 /* Set P address bit and use normal address
9765 printing routine. */
9766 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
9770 allow_unpredictable
= TRUE
;
9773 if ((given
& 0x004f0000) == 0x004f0000)
9775 /* PC relative with immediate offset. */
9776 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
9780 /* Elide positive zero offset. */
9781 if (offset
|| NEGATIVE_BIT_SET
)
9782 func (stream
, "[pc, #%s%d]\t; ",
9783 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
9785 func (stream
, "[pc]\t; ");
9786 if (NEGATIVE_BIT_SET
)
9788 info
->print_address_func (offset
+ pc
+ 8, info
);
9792 /* Always show the offset. */
9793 func (stream
, "[pc], #%s%d",
9794 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
9795 if (! allow_unpredictable
)
9796 is_unpredictable
= TRUE
;
9801 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
9803 func (stream
, "[%s",
9804 arm_regnames
[(given
>> 16) & 0xf]);
9808 if (IMMEDIATE_BIT_SET
)
9810 /* Elide offset for non-writeback
9812 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
9814 func (stream
, ", #%s%d",
9815 NEGATIVE_BIT_SET
? "-" : "", offset
);
9817 if (NEGATIVE_BIT_SET
)
9820 value_in_comment
= offset
;
9824 /* Register Offset or Register Pre-Indexed. */
9825 func (stream
, ", %s%s",
9826 NEGATIVE_BIT_SET
? "-" : "",
9827 arm_regnames
[given
& 0xf]);
9829 /* Writing back to the register that is the source/
9830 destination of the load/store is unpredictable. */
9831 if (! allow_unpredictable
9832 && WRITEBACK_BIT_SET
9833 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
9834 is_unpredictable
= TRUE
;
9837 func (stream
, "]%s",
9838 WRITEBACK_BIT_SET
? "!" : "");
9842 if (IMMEDIATE_BIT_SET
)
9844 /* Immediate Post-indexed. */
9845 /* PR 10924: Offset must be printed, even if it is zero. */
9846 func (stream
, "], #%s%d",
9847 NEGATIVE_BIT_SET
? "-" : "", offset
);
9848 if (NEGATIVE_BIT_SET
)
9850 value_in_comment
= offset
;
9854 /* Register Post-indexed. */
9855 func (stream
, "], %s%s",
9856 NEGATIVE_BIT_SET
? "-" : "",
9857 arm_regnames
[given
& 0xf]);
9859 /* Writing back to the register that is the source/
9860 destination of the load/store is unpredictable. */
9861 if (! allow_unpredictable
9862 && (given
& 0xf) == ((given
>> 12) & 0xf))
9863 is_unpredictable
= TRUE
;
9866 if (! allow_unpredictable
)
9868 /* Writeback is automatically implied by post- addressing.
9869 Setting the W bit is unnecessary and ARM specify it as
9870 being unpredictable. */
9871 if (WRITEBACK_BIT_SET
9872 /* Specifying the PC register as the post-indexed
9873 registers is also unpredictable. */
9874 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
9875 is_unpredictable
= TRUE
;
9883 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
9884 info
->print_address_func (disp
* 4 + pc
+ 8, info
);
9889 if (((given
>> 28) & 0xf) != 0xe)
9891 arm_conditional
[(given
>> 28) & 0xf]);
9900 for (reg
= 0; reg
< 16; reg
++)
9901 if ((given
& (1 << reg
)) != 0)
9904 func (stream
, ", ");
9906 func (stream
, "%s", arm_regnames
[reg
]);
9910 is_unpredictable
= TRUE
;
9915 arm_decode_shift (given
, func
, stream
, FALSE
);
9919 if ((given
& 0x02000000) != 0)
9921 unsigned int rotate
= (given
& 0xf00) >> 7;
9922 unsigned int immed
= (given
& 0xff);
9925 a
= (((immed
<< (32 - rotate
))
9926 | (immed
>> rotate
)) & 0xffffffff);
9927 /* If there is another encoding with smaller rotate,
9928 the rotate should be specified directly. */
9929 for (i
= 0; i
< 32; i
+= 2)
9930 if ((a
<< i
| a
>> (32 - i
)) <= 0xff)
9934 func (stream
, "#%d, %d", immed
, rotate
);
9936 func (stream
, "#%d", a
);
9937 value_in_comment
= a
;
9940 arm_decode_shift (given
, func
, stream
, TRUE
);
9944 if ((given
& 0x0000f000) == 0x0000f000)
9946 arm_feature_set arm_ext_v6
=
9947 ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
9949 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9950 mechanism for setting PSR flag bits. They are
9951 obsolete in V6 onwards. */
9952 if (! ARM_CPU_HAS_FEATURE (private_data
->features
, \
9956 is_unpredictable
= TRUE
;
9961 if ((given
& 0x01200000) == 0x00200000)
9967 int offset
= given
& 0xff;
9969 value_in_comment
= offset
* 4;
9970 if (NEGATIVE_BIT_SET
)
9971 value_in_comment
= - value_in_comment
;
9973 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
9978 func (stream
, ", #%d]%s",
9979 (int) value_in_comment
,
9980 WRITEBACK_BIT_SET
? "!" : "");
9988 if (WRITEBACK_BIT_SET
)
9991 func (stream
, ", #%d", (int) value_in_comment
);
9995 func (stream
, ", {%d}", (int) offset
);
9996 value_in_comment
= offset
;
10003 /* Print ARM V5 BLX(1) address: pc+25 bits. */
10006 bfd_vma offset
= 0;
10008 if (! NEGATIVE_BIT_SET
)
10009 /* Is signed, hi bits should be ones. */
10010 offset
= (-1) ^ 0x00ffffff;
10012 /* Offset is (SignExtend(offset field)<<2). */
10013 offset
+= given
& 0x00ffffff;
10015 address
= offset
+ pc
+ 8;
10017 if (given
& 0x01000000)
10018 /* H bit allows addressing to 2-byte boundaries. */
10021 info
->print_address_func (address
, info
);
10026 if ((given
& 0x02000200) == 0x200)
10029 unsigned sysm
= (given
& 0x004f0000) >> 16;
10031 sysm
|= (given
& 0x300) >> 4;
10032 name
= banked_regname (sysm
);
10035 func (stream
, "%s", name
);
10037 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
10041 func (stream
, "%cPSR_",
10042 (given
& 0x00400000) ? 'S' : 'C');
10043 if (given
& 0x80000)
10044 func (stream
, "f");
10045 if (given
& 0x40000)
10046 func (stream
, "s");
10047 if (given
& 0x20000)
10048 func (stream
, "x");
10049 if (given
& 0x10000)
10050 func (stream
, "c");
10055 if ((given
& 0xf0) == 0x60)
10057 switch (given
& 0xf)
10059 case 0xf: func (stream
, "sy"); break;
10061 func (stream
, "#%d", (int) given
& 0xf);
10067 const char * opt
= data_barrier_option (given
& 0xf);
10069 func (stream
, "%s", opt
);
10071 func (stream
, "#%d", (int) given
& 0xf);
10075 case '0': case '1': case '2': case '3': case '4':
10076 case '5': case '6': case '7': case '8': case '9':
10079 unsigned long value
;
10081 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
10087 is_unpredictable
= TRUE
;
10088 /* Fall through. */
10091 /* We want register + 1 when decoding T. */
10097 /* Eat the 'u' character. */
10100 if (u_reg
== value
)
10101 is_unpredictable
= TRUE
;
10106 /* Eat the 'U' character. */
10109 if (U_reg
== value
)
10110 is_unpredictable
= TRUE
;
10113 func (stream
, "%s", arm_regnames
[value
]);
10116 func (stream
, "%ld", value
);
10117 value_in_comment
= value
;
10120 func (stream
, "%ld", value
* 8);
10121 value_in_comment
= value
* 8;
10124 func (stream
, "%ld", value
+ 1);
10125 value_in_comment
= value
+ 1;
10128 func (stream
, "0x%08lx", value
);
10130 /* Some SWI instructions have special
10132 if ((given
& 0x0fffffff) == 0x0FF00000)
10133 func (stream
, "\t; IMB");
10134 else if ((given
& 0x0fffffff) == 0x0FF00001)
10135 func (stream
, "\t; IMBRange");
10138 func (stream
, "%01lx", value
& 0xf);
10139 value_in_comment
= value
;
10144 func (stream
, "%c", *c
);
10148 if (value
== ((1ul << width
) - 1))
10149 func (stream
, "%c", *c
);
10152 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
10165 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
10166 func (stream
, "%d", imm
);
10167 value_in_comment
= imm
;
10172 /* LSB and WIDTH fields of BFI or BFC. The machine-
10173 language instruction encodes LSB and MSB. */
10175 long msb
= (given
& 0x001f0000) >> 16;
10176 long lsb
= (given
& 0x00000f80) >> 7;
10177 long w
= msb
- lsb
+ 1;
10180 func (stream
, "#%lu, #%lu", lsb
, w
);
10182 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
10187 /* Get the PSR/banked register name. */
10190 unsigned sysm
= (given
& 0x004f0000) >> 16;
10192 sysm
|= (given
& 0x300) >> 4;
10193 name
= banked_regname (sysm
);
10196 func (stream
, "%s", name
);
10198 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
10203 /* 16-bit unsigned immediate from a MOVT or MOVW
10204 instruction, encoded in bits 0:11 and 15:19. */
10206 long hi
= (given
& 0x000f0000) >> 4;
10207 long lo
= (given
& 0x00000fff);
10208 long imm16
= hi
| lo
;
10210 func (stream
, "#%lu", imm16
);
10211 value_in_comment
= imm16
;
10220 func (stream
, "%c", *c
);
10223 if (value_in_comment
> 32 || value_in_comment
< -16)
10224 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
10226 if (is_unpredictable
)
10227 func (stream
, UNPREDICTABLE_INSTRUCTION
);
10232 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
10236 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
10239 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
10241 const struct opcode16
*insn
;
10242 void *stream
= info
->stream
;
10243 fprintf_ftype func
= info
->fprintf_func
;
10245 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
10246 if ((given
& insn
->mask
) == insn
->value
)
10248 signed long value_in_comment
= 0;
10249 const char *c
= insn
->assembler
;
10258 func (stream
, "%c", *c
);
10265 func (stream
, "%%");
10270 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10275 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10277 func (stream
, "s");
10284 ifthen_next_state
= given
& 0xff;
10285 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
10286 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
10287 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
10292 if (ifthen_next_state
)
10293 func (stream
, "\t; unpredictable branch in IT block\n");
10298 func (stream
, "\t; unpredictable <IT:%s>",
10299 arm_conditional
[IFTHEN_COND
]);
10306 reg
= (given
>> 3) & 0x7;
10307 if (given
& (1 << 6))
10310 func (stream
, "%s", arm_regnames
[reg
]);
10319 if (given
& (1 << 7))
10322 func (stream
, "%s", arm_regnames
[reg
]);
10327 if (given
& (1 << 8))
10329 /* Fall through. */
10331 if (*c
== 'O' && (given
& (1 << 8)))
10333 /* Fall through. */
10339 func (stream
, "{");
10341 /* It would be nice if we could spot
10342 ranges, and generate the rS-rE format: */
10343 for (reg
= 0; (reg
< 8); reg
++)
10344 if ((given
& (1 << reg
)) != 0)
10347 func (stream
, ", ");
10349 func (stream
, "%s", arm_regnames
[reg
]);
10355 func (stream
, ", ");
10357 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
10363 func (stream
, ", ");
10364 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
10367 func (stream
, "}");
10372 /* Print writeback indicator for a LDMIA. We are doing a
10373 writeback if the base register is not in the register
10375 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
10376 func (stream
, "!");
10380 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10382 bfd_vma address
= (pc
+ 4
10383 + ((given
& 0x00f8) >> 2)
10384 + ((given
& 0x0200) >> 3));
10385 info
->print_address_func (address
, info
);
10390 /* Right shift immediate -- bits 6..10; 1-31 print
10391 as themselves, 0 prints as 32. */
10393 long imm
= (given
& 0x07c0) >> 6;
10396 func (stream
, "#%ld", imm
);
10400 case '0': case '1': case '2': case '3': case '4':
10401 case '5': case '6': case '7': case '8': case '9':
10403 int bitstart
= *c
++ - '0';
10406 while (*c
>= '0' && *c
<= '9')
10407 bitstart
= (bitstart
* 10) + *c
++ - '0';
10416 while (*c
>= '0' && *c
<= '9')
10417 bitend
= (bitend
* 10) + *c
++ - '0';
10420 reg
= given
>> bitstart
;
10421 reg
&= (2 << (bitend
- bitstart
)) - 1;
10426 func (stream
, "%s", arm_regnames
[reg
]);
10430 func (stream
, "%ld", (long) reg
);
10431 value_in_comment
= reg
;
10435 func (stream
, "%ld", (long) (reg
<< 1));
10436 value_in_comment
= reg
<< 1;
10440 func (stream
, "%ld", (long) (reg
<< 2));
10441 value_in_comment
= reg
<< 2;
10445 /* PC-relative address -- the bottom two
10446 bits of the address are dropped
10447 before the calculation. */
10448 info
->print_address_func
10449 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
10450 value_in_comment
= 0;
10454 func (stream
, "0x%04lx", (long) reg
);
10458 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
10459 info
->print_address_func (reg
* 2 + pc
+ 4, info
);
10460 value_in_comment
= 0;
10464 func (stream
, "%s", arm_conditional
[reg
]);
10475 if ((given
& (1 << bitstart
)) != 0)
10476 func (stream
, "%c", *c
);
10481 if ((given
& (1 << bitstart
)) != 0)
10482 func (stream
, "%c", *c
++);
10484 func (stream
, "%c", *++c
);
10498 if (value_in_comment
> 32 || value_in_comment
< -16)
10499 func (stream
, "\t; 0x%lx", value_in_comment
);
10504 func (stream
, UNKNOWN_INSTRUCTION_16BIT
, (unsigned)given
);
10508 /* Return the name of an V7M special register. */
10510 static const char *
10511 psr_name (int regno
)
10515 case 0x0: return "APSR";
10516 case 0x1: return "IAPSR";
10517 case 0x2: return "EAPSR";
10518 case 0x3: return "PSR";
10519 case 0x5: return "IPSR";
10520 case 0x6: return "EPSR";
10521 case 0x7: return "IEPSR";
10522 case 0x8: return "MSP";
10523 case 0x9: return "PSP";
10524 case 0xa: return "MSPLIM";
10525 case 0xb: return "PSPLIM";
10526 case 0x10: return "PRIMASK";
10527 case 0x11: return "BASEPRI";
10528 case 0x12: return "BASEPRI_MAX";
10529 case 0x13: return "FAULTMASK";
10530 case 0x14: return "CONTROL";
10531 case 0x88: return "MSP_NS";
10532 case 0x89: return "PSP_NS";
10533 case 0x8a: return "MSPLIM_NS";
10534 case 0x8b: return "PSPLIM_NS";
10535 case 0x90: return "PRIMASK_NS";
10536 case 0x91: return "BASEPRI_NS";
10537 case 0x93: return "FAULTMASK_NS";
10538 case 0x94: return "CONTROL_NS";
10539 case 0x98: return "SP_NS";
10540 default: return "<unknown>";
10544 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10547 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
10549 const struct opcode32
*insn
;
10550 void *stream
= info
->stream
;
10551 fprintf_ftype func
= info
->fprintf_func
;
10552 bfd_boolean is_mve
= is_mve_architecture (info
);
10554 if (print_insn_coprocessor (pc
, info
, given
, TRUE
))
10557 if ((is_mve
== FALSE
) && print_insn_neon (info
, given
, TRUE
))
10560 if (is_mve
&& print_insn_mve (info
, given
))
10563 if (print_insn_generic_coprocessor (pc
, info
, given
, TRUE
))
10566 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
10567 if ((given
& insn
->mask
) == insn
->value
)
10569 bfd_boolean is_clrm
= FALSE
;
10570 bfd_boolean is_unpredictable
= FALSE
;
10571 signed long value_in_comment
= 0;
10572 const char *c
= insn
->assembler
;
10578 func (stream
, "%c", *c
);
10585 func (stream
, "%%");
10590 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10594 if (ifthen_next_state
)
10595 func (stream
, "\t; unpredictable branch in IT block\n");
10600 func (stream
, "\t; unpredictable <IT:%s>",
10601 arm_conditional
[IFTHEN_COND
]);
10606 unsigned int imm12
= 0;
10608 imm12
|= (given
& 0x000000ffu
);
10609 imm12
|= (given
& 0x00007000u
) >> 4;
10610 imm12
|= (given
& 0x04000000u
) >> 15;
10611 func (stream
, "#%u", imm12
);
10612 value_in_comment
= imm12
;
10618 unsigned int bits
= 0, imm
, imm8
, mod
;
10620 bits
|= (given
& 0x000000ffu
);
10621 bits
|= (given
& 0x00007000u
) >> 4;
10622 bits
|= (given
& 0x04000000u
) >> 15;
10623 imm8
= (bits
& 0x0ff);
10624 mod
= (bits
& 0xf00) >> 8;
10627 case 0: imm
= imm8
; break;
10628 case 1: imm
= ((imm8
<< 16) | imm8
); break;
10629 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
10630 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
10632 mod
= (bits
& 0xf80) >> 7;
10633 imm8
= (bits
& 0x07f) | 0x80;
10634 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
10636 func (stream
, "#%u", imm
);
10637 value_in_comment
= imm
;
10643 unsigned int imm
= 0;
10645 imm
|= (given
& 0x000000ffu
);
10646 imm
|= (given
& 0x00007000u
) >> 4;
10647 imm
|= (given
& 0x04000000u
) >> 15;
10648 imm
|= (given
& 0x000f0000u
) >> 4;
10649 func (stream
, "#%u", imm
);
10650 value_in_comment
= imm
;
10656 unsigned int imm
= 0;
10658 imm
|= (given
& 0x000f0000u
) >> 16;
10659 imm
|= (given
& 0x00000ff0u
) >> 0;
10660 imm
|= (given
& 0x0000000fu
) << 12;
10661 func (stream
, "#%u", imm
);
10662 value_in_comment
= imm
;
10668 unsigned int imm
= 0;
10670 imm
|= (given
& 0x000f0000u
) >> 4;
10671 imm
|= (given
& 0x00000fffu
) >> 0;
10672 func (stream
, "#%u", imm
);
10673 value_in_comment
= imm
;
10679 unsigned int imm
= 0;
10681 imm
|= (given
& 0x00000fffu
);
10682 imm
|= (given
& 0x000f0000u
) >> 4;
10683 func (stream
, "#%u", imm
);
10684 value_in_comment
= imm
;
10690 unsigned int reg
= (given
& 0x0000000fu
);
10691 unsigned int stp
= (given
& 0x00000030u
) >> 4;
10692 unsigned int imm
= 0;
10693 imm
|= (given
& 0x000000c0u
) >> 6;
10694 imm
|= (given
& 0x00007000u
) >> 10;
10696 func (stream
, "%s", arm_regnames
[reg
]);
10701 func (stream
, ", lsl #%u", imm
);
10707 func (stream
, ", lsr #%u", imm
);
10713 func (stream
, ", asr #%u", imm
);
10718 func (stream
, ", rrx");
10720 func (stream
, ", ror #%u", imm
);
10727 unsigned int Rn
= (given
& 0x000f0000) >> 16;
10728 unsigned int U
= ! NEGATIVE_BIT_SET
;
10729 unsigned int op
= (given
& 0x00000f00) >> 8;
10730 unsigned int i12
= (given
& 0x00000fff);
10731 unsigned int i8
= (given
& 0x000000ff);
10732 bfd_boolean writeback
= FALSE
, postind
= FALSE
;
10733 bfd_vma offset
= 0;
10735 func (stream
, "[%s", arm_regnames
[Rn
]);
10736 if (U
) /* 12-bit positive immediate offset. */
10740 value_in_comment
= offset
;
10742 else if (Rn
== 15) /* 12-bit negative immediate offset. */
10743 offset
= - (int) i12
;
10744 else if (op
== 0x0) /* Shifted register offset. */
10746 unsigned int Rm
= (i8
& 0x0f);
10747 unsigned int sh
= (i8
& 0x30) >> 4;
10749 func (stream
, ", %s", arm_regnames
[Rm
]);
10751 func (stream
, ", lsl #%u", sh
);
10752 func (stream
, "]");
10757 case 0xE: /* 8-bit positive immediate offset. */
10761 case 0xC: /* 8-bit negative immediate offset. */
10765 case 0xF: /* 8-bit + preindex with wb. */
10770 case 0xD: /* 8-bit - preindex with wb. */
10775 case 0xB: /* 8-bit + postindex. */
10780 case 0x9: /* 8-bit - postindex. */
10786 func (stream
, ", <undefined>]");
10791 func (stream
, "], #%d", (int) offset
);
10795 func (stream
, ", #%d", (int) offset
);
10796 func (stream
, writeback
? "]!" : "]");
10801 func (stream
, "\t; ");
10802 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
10810 unsigned int U
= ! NEGATIVE_BIT_SET
;
10811 unsigned int W
= WRITEBACK_BIT_SET
;
10812 unsigned int Rn
= (given
& 0x000f0000) >> 16;
10813 unsigned int off
= (given
& 0x000000ff);
10815 func (stream
, "[%s", arm_regnames
[Rn
]);
10821 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
10822 value_in_comment
= off
* 4 * (U
? 1 : -1);
10824 func (stream
, "]");
10826 func (stream
, "!");
10830 func (stream
, "], ");
10833 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
10834 value_in_comment
= off
* 4 * (U
? 1 : -1);
10838 func (stream
, "{%u}", off
);
10839 value_in_comment
= off
;
10847 unsigned int Sbit
= (given
& 0x01000000) >> 24;
10848 unsigned int type
= (given
& 0x00600000) >> 21;
10852 case 0: func (stream
, Sbit
? "sb" : "b"); break;
10853 case 1: func (stream
, Sbit
? "sh" : "h"); break;
10856 func (stream
, "??");
10859 func (stream
, "??");
10867 /* Fall through. */
10873 func (stream
, "{");
10874 for (reg
= 0; reg
< 16; reg
++)
10875 if ((given
& (1 << reg
)) != 0)
10878 func (stream
, ", ");
10880 if (is_clrm
&& reg
== 13)
10881 func (stream
, "(invalid: %s)", arm_regnames
[reg
]);
10882 else if (is_clrm
&& reg
== 15)
10883 func (stream
, "%s", "APSR");
10885 func (stream
, "%s", arm_regnames
[reg
]);
10887 func (stream
, "}");
10893 unsigned int msb
= (given
& 0x0000001f);
10894 unsigned int lsb
= 0;
10896 lsb
|= (given
& 0x000000c0u
) >> 6;
10897 lsb
|= (given
& 0x00007000u
) >> 10;
10898 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
10904 unsigned int width
= (given
& 0x0000001f) + 1;
10905 unsigned int lsb
= 0;
10907 lsb
|= (given
& 0x000000c0u
) >> 6;
10908 lsb
|= (given
& 0x00007000u
) >> 10;
10909 func (stream
, "#%u, #%u", lsb
, width
);
10915 unsigned int boff
= (((given
& 0x07800000) >> 23) << 1);
10916 func (stream
, "%x", boff
);
10922 unsigned int immA
= (given
& 0x001f0000u
) >> 16;
10923 unsigned int immB
= (given
& 0x000007feu
) >> 1;
10924 unsigned int immC
= (given
& 0x00000800u
) >> 11;
10925 bfd_vma offset
= 0;
10927 offset
|= immA
<< 12;
10928 offset
|= immB
<< 2;
10929 offset
|= immC
<< 1;
10931 offset
= (offset
& 0x10000) ? offset
- (1 << 17) : offset
;
10933 info
->print_address_func (pc
+ 4 + offset
, info
);
10939 unsigned int immA
= (given
& 0x007f0000u
) >> 16;
10940 unsigned int immB
= (given
& 0x000007feu
) >> 1;
10941 unsigned int immC
= (given
& 0x00000800u
) >> 11;
10942 bfd_vma offset
= 0;
10944 offset
|= immA
<< 12;
10945 offset
|= immB
<< 2;
10946 offset
|= immC
<< 1;
10948 offset
= (offset
& 0x40000) ? offset
- (1 << 19) : offset
;
10950 info
->print_address_func (pc
+ 4 + offset
, info
);
10956 unsigned int immA
= (given
& 0x00010000u
) >> 16;
10957 unsigned int immB
= (given
& 0x000007feu
) >> 1;
10958 unsigned int immC
= (given
& 0x00000800u
) >> 11;
10959 bfd_vma offset
= 0;
10961 offset
|= immA
<< 12;
10962 offset
|= immB
<< 2;
10963 offset
|= immC
<< 1;
10965 offset
= (offset
& 0x1000) ? offset
- (1 << 13) : offset
;
10967 info
->print_address_func (pc
+ 4 + offset
, info
);
10969 unsigned int T
= (given
& 0x00020000u
) >> 17;
10970 unsigned int endoffset
= (((given
& 0x07800000) >> 23) << 1);
10971 unsigned int boffset
= (T
== 1) ? 4 : 2;
10972 func (stream
, ", ");
10973 func (stream
, "%x", endoffset
+ boffset
);
10979 unsigned int immh
= (given
& 0x000007feu
) >> 1;
10980 unsigned int imml
= (given
& 0x00000800u
) >> 11;
10983 imm32
|= immh
<< 2;
10984 imm32
|= imml
<< 1;
10986 info
->print_address_func (pc
+ 4 + imm32
, info
);
10992 unsigned int immh
= (given
& 0x000007feu
) >> 1;
10993 unsigned int imml
= (given
& 0x00000800u
) >> 11;
10996 imm32
|= immh
<< 2;
10997 imm32
|= imml
<< 1;
10999 info
->print_address_func (pc
+ 4 - imm32
, info
);
11005 unsigned int S
= (given
& 0x04000000u
) >> 26;
11006 unsigned int J1
= (given
& 0x00002000u
) >> 13;
11007 unsigned int J2
= (given
& 0x00000800u
) >> 11;
11008 bfd_vma offset
= 0;
11010 offset
|= !S
<< 20;
11011 offset
|= J2
<< 19;
11012 offset
|= J1
<< 18;
11013 offset
|= (given
& 0x003f0000) >> 4;
11014 offset
|= (given
& 0x000007ff) << 1;
11015 offset
-= (1 << 20);
11017 info
->print_address_func (pc
+ 4 + offset
, info
);
11023 unsigned int S
= (given
& 0x04000000u
) >> 26;
11024 unsigned int I1
= (given
& 0x00002000u
) >> 13;
11025 unsigned int I2
= (given
& 0x00000800u
) >> 11;
11026 bfd_vma offset
= 0;
11028 offset
|= !S
<< 24;
11029 offset
|= !(I1
^ S
) << 23;
11030 offset
|= !(I2
^ S
) << 22;
11031 offset
|= (given
& 0x03ff0000u
) >> 4;
11032 offset
|= (given
& 0x000007ffu
) << 1;
11033 offset
-= (1 << 24);
11036 /* BLX target addresses are always word aligned. */
11037 if ((given
& 0x00001000u
) == 0)
11040 info
->print_address_func (offset
, info
);
11046 unsigned int shift
= 0;
11048 shift
|= (given
& 0x000000c0u
) >> 6;
11049 shift
|= (given
& 0x00007000u
) >> 10;
11050 if (WRITEBACK_BIT_SET
)
11051 func (stream
, ", asr #%u", shift
);
11053 func (stream
, ", lsl #%u", shift
);
11054 /* else print nothing - lsl #0 */
11060 unsigned int rot
= (given
& 0x00000030) >> 4;
11063 func (stream
, ", ror #%u", rot
* 8);
11068 if ((given
& 0xf0) == 0x60)
11070 switch (given
& 0xf)
11072 case 0xf: func (stream
, "sy"); break;
11074 func (stream
, "#%d", (int) given
& 0xf);
11080 const char * opt
= data_barrier_option (given
& 0xf);
11082 func (stream
, "%s", opt
);
11084 func (stream
, "#%d", (int) given
& 0xf);
11089 if ((given
& 0xff) == 0)
11091 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
11093 func (stream
, "f");
11095 func (stream
, "s");
11097 func (stream
, "x");
11099 func (stream
, "c");
11101 else if ((given
& 0x20) == 0x20)
11104 unsigned sysm
= (given
& 0xf00) >> 8;
11106 sysm
|= (given
& 0x30);
11107 sysm
|= (given
& 0x00100000) >> 14;
11108 name
= banked_regname (sysm
);
11111 func (stream
, "%s", name
);
11113 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
11117 func (stream
, "%s", psr_name (given
& 0xff));
11122 if (((given
& 0xff) == 0)
11123 || ((given
& 0x20) == 0x20))
11126 unsigned sm
= (given
& 0xf0000) >> 16;
11128 sm
|= (given
& 0x30);
11129 sm
|= (given
& 0x00100000) >> 14;
11130 name
= banked_regname (sm
);
11133 func (stream
, "%s", name
);
11135 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
11138 func (stream
, "%s", psr_name (given
& 0xff));
11141 case '0': case '1': case '2': case '3': case '4':
11142 case '5': case '6': case '7': case '8': case '9':
11147 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
11153 func (stream
, "%s", mve_vec_sizename
[val
]);
11155 func (stream
, "<undef size>");
11159 func (stream
, "%lu", val
);
11160 value_in_comment
= val
;
11164 func (stream
, "%lu", val
+ 1);
11165 value_in_comment
= val
+ 1;
11169 func (stream
, "%lu", val
* 4);
11170 value_in_comment
= val
* 4;
11175 is_unpredictable
= TRUE
;
11176 /* Fall through. */
11179 is_unpredictable
= TRUE
;
11180 /* Fall through. */
11182 func (stream
, "%s", arm_regnames
[val
]);
11186 func (stream
, "%s", arm_conditional
[val
]);
11191 if (val
== ((1ul << width
) - 1))
11192 func (stream
, "%c", *c
);
11198 func (stream
, "%c", *c
);
11202 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
11207 func (stream
, "0x%lx", val
& 0xffffffffUL
);
11217 /* PR binutils/12534
11218 If we have a PC relative offset in an LDRD or STRD
11219 instructions then display the decoded address. */
11220 if (((given
>> 16) & 0xf) == 0xf)
11222 bfd_vma offset
= (given
& 0xff) * 4;
11224 if ((given
& (1 << 23)) == 0)
11226 func (stream
, "\t; ");
11227 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
11236 if (value_in_comment
> 32 || value_in_comment
< -16)
11237 func (stream
, "\t; 0x%lx", value_in_comment
);
11239 if (is_unpredictable
)
11240 func (stream
, UNPREDICTABLE_INSTRUCTION
);
11246 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
11250 /* Print data bytes on INFO->STREAM. */
11253 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
11254 struct disassemble_info
*info
,
11257 switch (info
->bytes_per_chunk
)
11260 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
11263 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
11266 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
11273 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
11274 being displayed in symbol relative addresses.
11276 Also disallow private symbol, with __tagsym$$ prefix,
11277 from ARM RVCT toolchain being displayed. */
11280 arm_symbol_is_valid (asymbol
* sym
,
11281 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
11288 name
= bfd_asymbol_name (sym
);
11290 return (name
&& *name
!= '$' && strncmp (name
, "__tagsym$$", 10));
11293 /* Parse the string of disassembler options. */
11296 parse_arm_disassembler_options (const char *options
)
11300 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
11302 if (CONST_STRNEQ (opt
, "reg-names-"))
11305 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
11306 if (disassembler_options_cmp (opt
, regnames
[i
].name
) == 0)
11308 regname_selected
= i
;
11312 if (i
>= NUM_ARM_OPTIONS
)
11313 /* xgettext: c-format */
11314 opcodes_error_handler (_("unrecognised register name set: %s"),
11317 else if (CONST_STRNEQ (opt
, "force-thumb"))
11319 else if (CONST_STRNEQ (opt
, "no-force-thumb"))
11322 /* xgettext: c-format */
11323 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt
);
11330 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
11331 enum map_type
*map_symbol
);
11333 /* Search back through the insn stream to determine if this instruction is
11334 conditionally executed. */
11337 find_ifthen_state (bfd_vma pc
,
11338 struct disassemble_info
*info
,
11339 bfd_boolean little
)
11341 unsigned char b
[2];
11344 /* COUNT is twice the number of instructions seen. It will be odd if we
11345 just crossed an instruction boundary. */
11348 unsigned int seen_it
;
11351 ifthen_address
= pc
;
11358 /* Scan backwards looking for IT instructions, keeping track of where
11359 instruction boundaries are. We don't know if something is actually an
11360 IT instruction until we find a definite instruction boundary. */
11363 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
11365 /* A symbol must be on an instruction boundary, and will not
11366 be within an IT block. */
11367 if (seen_it
&& (count
& 1))
11373 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
11378 insn
= (b
[0]) | (b
[1] << 8);
11380 insn
= (b
[1]) | (b
[0] << 8);
11383 if ((insn
& 0xf800) < 0xe800)
11385 /* Addr + 2 is an instruction boundary. See if this matches
11386 the expected boundary based on the position of the last
11393 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
11395 enum map_type type
= MAP_ARM
;
11396 bfd_boolean found
= mapping_symbol_for_insn (addr
, info
, &type
);
11398 if (!found
|| (found
&& type
== MAP_THUMB
))
11400 /* This could be an IT instruction. */
11402 it_count
= count
>> 1;
11405 if ((insn
& 0xf800) >= 0xe800)
11408 count
= (count
+ 2) | 1;
11409 /* IT blocks contain at most 4 instructions. */
11410 if (count
>= 8 && !seen_it
)
11413 /* We found an IT instruction. */
11414 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
11415 if ((ifthen_state
& 0xf) == 0)
11419 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11423 is_mapping_symbol (struct disassemble_info
*info
, int n
,
11424 enum map_type
*map_type
)
11428 name
= bfd_asymbol_name (info
->symtab
[n
]);
11429 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
11430 && (name
[2] == 0 || name
[2] == '.'))
11432 *map_type
= ((name
[1] == 'a') ? MAP_ARM
11433 : (name
[1] == 't') ? MAP_THUMB
11441 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11442 Returns nonzero if *MAP_TYPE was set. */
11445 get_map_sym_type (struct disassemble_info
*info
,
11447 enum map_type
*map_type
)
11449 /* If the symbol is in a different section, ignore it. */
11450 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
11453 return is_mapping_symbol (info
, n
, map_type
);
11456 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
11457 Returns nonzero if *MAP_TYPE was set. */
11460 get_sym_code_type (struct disassemble_info
*info
,
11462 enum map_type
*map_type
)
11464 elf_symbol_type
*es
;
11467 /* If the symbol is in a different section, ignore it. */
11468 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
11471 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
11472 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
11474 /* If the symbol has function type then use that. */
11475 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
11477 if (ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
11478 == ST_BRANCH_TO_THUMB
)
11479 *map_type
= MAP_THUMB
;
11481 *map_type
= MAP_ARM
;
11488 /* Search the mapping symbol state for instruction at pc. This is only
11489 applicable for elf target.
11491 There is an assumption Here, info->private_data contains the correct AND
11492 up-to-date information about current scan process. The information will be
11493 used to speed this search process.
11495 Return TRUE if the mapping state can be determined, and map_symbol
11496 will be updated accordingly. Otherwise, return FALSE. */
11499 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
11500 enum map_type
*map_symbol
)
11502 bfd_vma addr
, section_vma
= 0;
11503 int n
, last_sym
= -1;
11504 bfd_boolean found
= FALSE
;
11505 bfd_boolean can_use_search_opt_p
= FALSE
;
11507 /* Default to DATA. A text section is required by the ABI to contain an
11508 INSN mapping symbol at the start. A data section has no such
11509 requirement, hence if no mapping symbol is found the section must
11510 contain only data. This however isn't very useful if the user has
11511 fully stripped the binaries. If this is the case use the section
11512 attributes to determine the default. If we have no section default to
11513 INSN as well, as we may be disassembling some raw bytes on a baremetal
11514 HEX file or similar. */
11515 enum map_type type
= MAP_DATA
;
11516 if ((info
->section
&& info
->section
->flags
& SEC_CODE
) || !info
->section
)
11518 struct arm_private_data
*private_data
;
11520 if (info
->private_data
== NULL
11521 || bfd_asymbol_flavour (*info
->symtab
) != bfd_target_elf_flavour
)
11524 private_data
= info
->private_data
;
11526 /* First, look for mapping symbols. */
11527 if (info
->symtab_size
!= 0)
11529 if (pc
<= private_data
->last_mapping_addr
)
11530 private_data
->last_mapping_sym
= -1;
11532 /* Start scanning at the start of the function, or wherever
11533 we finished last time. */
11534 n
= info
->symtab_pos
+ 1;
11536 /* If the last stop offset is different from the current one it means we
11537 are disassembling a different glob of bytes. As such the optimization
11538 would not be safe and we should start over. */
11539 can_use_search_opt_p
11540 = private_data
->last_mapping_sym
>= 0
11541 && info
->stop_offset
== private_data
->last_stop_offset
;
11543 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
11544 n
= private_data
->last_mapping_sym
;
11546 /* Look down while we haven't passed the location being disassembled.
11547 The reason for this is that there's no defined order between a symbol
11548 and an mapping symbol that may be at the same address. We may have to
11549 look at least one position ahead. */
11550 for (; n
< info
->symtab_size
; n
++)
11552 addr
= bfd_asymbol_value (info
->symtab
[n
]);
11555 if (get_map_sym_type (info
, n
, &type
))
11564 n
= info
->symtab_pos
;
11565 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
11566 n
= private_data
->last_mapping_sym
;
11568 /* No mapping symbol found at this address. Look backwards
11569 for a preceeding one, but don't go pass the section start
11570 otherwise a data section with no mapping symbol can pick up
11571 a text mapping symbol of a preceeding section. The documentation
11572 says section can be NULL, in which case we will seek up all the
11575 section_vma
= info
->section
->vma
;
11577 for (; n
>= 0; n
--)
11579 addr
= bfd_asymbol_value (info
->symtab
[n
]);
11580 if (addr
< section_vma
)
11583 if (get_map_sym_type (info
, n
, &type
))
11593 /* If no mapping symbol was found, try looking up without a mapping
11594 symbol. This is done by walking up from the current PC to the nearest
11595 symbol. We don't actually have to loop here since symtab_pos will
11596 contain the nearest symbol already. */
11599 n
= info
->symtab_pos
;
11600 if (n
>= 0 && get_sym_code_type (info
, n
, &type
))
11607 private_data
->last_mapping_sym
= last_sym
;
11608 private_data
->last_type
= type
;
11609 private_data
->last_stop_offset
= info
->stop_offset
;
11611 *map_symbol
= type
;
11615 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
11616 of the supplied arm_feature_set structure with bitmasks indicating
11617 the supported base architectures and coprocessor extensions.
11619 FIXME: This could more efficiently implemented as a constant array,
11620 although it would also be less robust. */
11623 select_arm_features (unsigned long mach
,
11624 arm_feature_set
* features
)
11626 arm_feature_set arch_fset
;
11627 const arm_feature_set fpu_any
= FPU_ANY
;
11629 #undef ARM_SET_FEATURES
11630 #define ARM_SET_FEATURES(FSET) \
11632 const arm_feature_set fset = FSET; \
11633 arch_fset = fset; \
11636 /* When several architecture versions share the same bfd_mach_arm_XXX value
11637 the most featureful is chosen. */
11640 case bfd_mach_arm_2
: ARM_SET_FEATURES (ARM_ARCH_V2
); break;
11641 case bfd_mach_arm_2a
: ARM_SET_FEATURES (ARM_ARCH_V2S
); break;
11642 case bfd_mach_arm_3
: ARM_SET_FEATURES (ARM_ARCH_V3
); break;
11643 case bfd_mach_arm_3M
: ARM_SET_FEATURES (ARM_ARCH_V3M
); break;
11644 case bfd_mach_arm_4
: ARM_SET_FEATURES (ARM_ARCH_V4
); break;
11645 case bfd_mach_arm_4T
: ARM_SET_FEATURES (ARM_ARCH_V4T
); break;
11646 case bfd_mach_arm_5
: ARM_SET_FEATURES (ARM_ARCH_V5
); break;
11647 case bfd_mach_arm_5T
: ARM_SET_FEATURES (ARM_ARCH_V5T
); break;
11648 case bfd_mach_arm_5TE
: ARM_SET_FEATURES (ARM_ARCH_V5TE
); break;
11649 case bfd_mach_arm_XScale
: ARM_SET_FEATURES (ARM_ARCH_XSCALE
); break;
11650 case bfd_mach_arm_ep9312
:
11651 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T
,
11652 ARM_CEXT_MAVERICK
| FPU_MAVERICK
));
11654 case bfd_mach_arm_iWMMXt
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT
); break;
11655 case bfd_mach_arm_iWMMXt2
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2
); break;
11656 case bfd_mach_arm_5TEJ
: ARM_SET_FEATURES (ARM_ARCH_V5TEJ
); break;
11657 case bfd_mach_arm_6
: ARM_SET_FEATURES (ARM_ARCH_V6
); break;
11658 case bfd_mach_arm_6KZ
: ARM_SET_FEATURES (ARM_ARCH_V6KZ
); break;
11659 case bfd_mach_arm_6T2
: ARM_SET_FEATURES (ARM_ARCH_V6KZT2
); break;
11660 case bfd_mach_arm_6K
: ARM_SET_FEATURES (ARM_ARCH_V6K
); break;
11661 case bfd_mach_arm_7
: ARM_SET_FEATURES (ARM_ARCH_V7VE
); break;
11662 case bfd_mach_arm_6M
: ARM_SET_FEATURES (ARM_ARCH_V6M
); break;
11663 case bfd_mach_arm_6SM
: ARM_SET_FEATURES (ARM_ARCH_V6SM
); break;
11664 case bfd_mach_arm_7EM
: ARM_SET_FEATURES (ARM_ARCH_V7EM
); break;
11665 case bfd_mach_arm_8
:
11667 /* Add bits for extensions that Armv8.6-A recognizes. */
11668 arm_feature_set armv8_6_ext_fset
11669 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
11670 ARM_SET_FEATURES (ARM_ARCH_V8_6A
);
11671 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, armv8_6_ext_fset
);
11674 case bfd_mach_arm_8R
: ARM_SET_FEATURES (ARM_ARCH_V8R
); break;
11675 case bfd_mach_arm_8M_BASE
: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE
); break;
11676 case bfd_mach_arm_8M_MAIN
: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN
); break;
11677 case bfd_mach_arm_8_1M_MAIN
:
11678 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN
);
11681 /* If the machine type is unknown allow all architecture types and all
11683 case bfd_mach_arm_unknown
: ARM_SET_FEATURES (ARM_FEATURE_ALL
); break;
11687 #undef ARM_SET_FEATURES
11689 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
11690 and thus on bfd_mach_arm_XXX value. Therefore for a given
11691 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
11692 ARM_MERGE_FEATURE_SETS (*features
, arch_fset
, fpu_any
);
11696 /* NOTE: There are no checks in these routines that
11697 the relevant number of data bytes exist. */
11700 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bfd_boolean little
)
11702 unsigned char b
[4];
11705 int is_thumb
= FALSE
;
11706 int is_data
= FALSE
;
11708 unsigned int size
= 4;
11709 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
11710 bfd_boolean found
= FALSE
;
11711 struct arm_private_data
*private_data
;
11713 if (info
->disassembler_options
)
11715 parse_arm_disassembler_options (info
->disassembler_options
);
11717 /* To avoid repeated parsing of these options, we remove them here. */
11718 info
->disassembler_options
= NULL
;
11721 /* PR 10288: Control which instructions will be disassembled. */
11722 if (info
->private_data
== NULL
)
11724 static struct arm_private_data
private;
11726 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
11727 /* If the user did not use the -m command line switch then default to
11728 disassembling all types of ARM instruction.
11730 The info->mach value has to be ignored as this will be based on
11731 the default archictecture for the target and/or hints in the notes
11732 section, but it will never be greater than the current largest arm
11733 machine value (iWMMXt2), which is only equivalent to the V5TE
11734 architecture. ARM architectures have advanced beyond the machine
11735 value encoding, and these newer architectures would be ignored if
11736 the machine value was used.
11738 Ie the -m switch is used to restrict which instructions will be
11739 disassembled. If it is necessary to use the -m switch to tell
11740 objdump that an ARM binary is being disassembled, eg because the
11741 input is a raw binary file, but it is also desired to disassemble
11742 all ARM instructions then use "-marm". This will select the
11743 "unknown" arm architecture which is compatible with any ARM
11745 info
->mach
= bfd_mach_arm_unknown
;
11747 /* Compute the architecture bitmask from the machine number.
11748 Note: This assumes that the machine number will not change
11749 during disassembly.... */
11750 select_arm_features (info
->mach
, & private.features
);
11752 private.last_mapping_sym
= -1;
11753 private.last_mapping_addr
= 0;
11754 private.last_stop_offset
= 0;
11756 info
->private_data
= & private;
11759 private_data
= info
->private_data
;
11761 /* Decide if our code is going to be little-endian, despite what the
11762 function argument might say. */
11763 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
11765 /* For ELF, consult the symbol table to determine what kind of code
11766 or data we have. */
11767 if (info
->symtab_size
!= 0
11768 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
11773 enum map_type type
= MAP_ARM
;
11775 found
= mapping_symbol_for_insn (pc
, info
, &type
);
11776 last_sym
= private_data
->last_mapping_sym
;
11778 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
11779 is_data
= (private_data
->last_type
== MAP_DATA
);
11781 /* Look a little bit ahead to see if we should print out
11782 two or four bytes of data. If there's a symbol,
11783 mapping or otherwise, after two bytes then don't
11787 size
= 4 - (pc
& 3);
11788 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
11790 addr
= bfd_asymbol_value (info
->symtab
[n
]);
11792 && (info
->section
== NULL
11793 || info
->section
== info
->symtab
[n
]->section
))
11795 if (addr
- pc
< size
)
11800 /* If the next symbol is after three bytes, we need to
11801 print only part of the data, so that we can use either
11802 .byte or .short. */
11804 size
= (pc
& 1) ? 1 : 2;
11808 if (info
->symbols
!= NULL
)
11810 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
11812 coff_symbol_type
* cs
;
11814 cs
= coffsymbol (*info
->symbols
);
11815 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
11816 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
11817 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
11818 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
11819 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
11821 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
11824 /* If no mapping symbol has been found then fall back to the type
11825 of the function symbol. */
11826 elf_symbol_type
* es
;
11829 es
= *(elf_symbol_type
**)(info
->symbols
);
11830 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
11833 ((ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
11834 == ST_BRANCH_TO_THUMB
) || type
== STT_ARM_16BIT
);
11836 else if (bfd_asymbol_flavour (*info
->symbols
)
11837 == bfd_target_mach_o_flavour
)
11839 bfd_mach_o_asymbol
*asym
= (bfd_mach_o_asymbol
*)*info
->symbols
;
11841 is_thumb
= (asym
->n_desc
& BFD_MACH_O_N_ARM_THUMB_DEF
);
11849 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
11851 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
11853 info
->bytes_per_line
= 4;
11855 /* PR 10263: Disassemble data if requested to do so by the user. */
11856 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
11860 /* Size was already set above. */
11861 info
->bytes_per_chunk
= size
;
11862 printer
= print_insn_data
;
11864 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
11867 for (i
= size
- 1; i
>= 0; i
--)
11868 given
= b
[i
] | (given
<< 8);
11870 for (i
= 0; i
< (int) size
; i
++)
11871 given
= b
[i
] | (given
<< 8);
11873 else if (!is_thumb
)
11875 /* In ARM mode endianness is a straightforward issue: the instruction
11876 is four bytes long and is either ordered 0123 or 3210. */
11877 printer
= print_insn_arm
;
11878 info
->bytes_per_chunk
= 4;
11881 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
11883 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | (b
[3] << 24);
11885 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | (b
[0] << 24);
11889 /* In Thumb mode we have the additional wrinkle of two
11890 instruction lengths. Fortunately, the bits that determine
11891 the length of the current instruction are always to be found
11892 in the first two bytes. */
11893 printer
= print_insn_thumb16
;
11894 info
->bytes_per_chunk
= 2;
11897 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
11899 given
= (b
[0]) | (b
[1] << 8);
11901 given
= (b
[1]) | (b
[0] << 8);
11905 /* These bit patterns signal a four-byte Thumb
11907 if ((given
& 0xF800) == 0xF800
11908 || (given
& 0xF800) == 0xF000
11909 || (given
& 0xF800) == 0xE800)
11911 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
11913 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
11915 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
11917 printer
= print_insn_thumb32
;
11922 if (ifthen_address
!= pc
)
11923 find_ifthen_state (pc
, info
, little_code
);
11927 if ((ifthen_state
& 0xf) == 0x8)
11928 ifthen_next_state
= 0;
11930 ifthen_next_state
= (ifthen_state
& 0xe0)
11931 | ((ifthen_state
& 0xf) << 1);
11937 info
->memory_error_func (status
, pc
, info
);
11940 if (info
->flags
& INSN_HAS_RELOC
)
11941 /* If the instruction has a reloc associated with it, then
11942 the offset field in the instruction will actually be the
11943 addend for the reloc. (We are using REL type relocs).
11944 In such cases, we can ignore the pc when computing
11945 addresses, since the addend is not currently pc-relative. */
11948 printer (pc
, info
, given
);
11952 ifthen_state
= ifthen_next_state
;
11953 ifthen_address
+= size
;
11959 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
11961 /* Detect BE8-ness and record it in the disassembler info. */
11962 if (info
->flavour
== bfd_target_elf_flavour
11963 && info
->section
!= NULL
11964 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
11965 info
->endian_code
= BFD_ENDIAN_LITTLE
;
11967 return print_insn (pc
, info
, FALSE
);
11971 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
11973 return print_insn (pc
, info
, TRUE
);
11976 const disasm_options_and_args_t
*
11977 disassembler_options_arm (void)
11979 static disasm_options_and_args_t
*opts_and_args
;
11981 if (opts_and_args
== NULL
)
11983 disasm_options_t
*opts
;
11986 opts_and_args
= XNEW (disasm_options_and_args_t
);
11987 opts_and_args
->args
= NULL
;
11989 opts
= &opts_and_args
->options
;
11990 opts
->name
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
11991 opts
->description
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
11993 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
11995 opts
->name
[i
] = regnames
[i
].name
;
11996 if (regnames
[i
].description
!= NULL
)
11997 opts
->description
[i
] = _(regnames
[i
].description
);
11999 opts
->description
[i
] = NULL
;
12001 /* The array we return must be NULL terminated. */
12002 opts
->name
[i
] = NULL
;
12003 opts
->description
[i
] = NULL
;
12006 return opts_and_args
;
12010 print_arm_disassembler_options (FILE *stream
)
12012 unsigned int i
, max_len
= 0;
12013 fprintf (stream
, _("\n\
12014 The following ARM specific disassembler options are supported for use with\n\
12015 the -M switch:\n"));
12017 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
12019 unsigned int len
= strlen (regnames
[i
].name
);
12024 for (i
= 0, max_len
++; i
< NUM_ARM_OPTIONS
; i
++)
12025 fprintf (stream
, " %s%*c %s\n",
12027 (int)(max_len
- strlen (regnames
[i
].name
)), ' ',
12028 _(regnames
[i
].description
));