1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
26 #include "disassemble.h"
27 #include "opcode/arm.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
38 #include "elf/internal.h"
42 /* FIXME: Belongs in global header. */
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
47 /* Cached mapping symbol state. */
55 struct arm_private_data
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features
;
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type
;
63 /* Tracking symbol table information */
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset
;
68 bfd_vma last_mapping_addr
;
121 MVE_VSTRB_SCATTER_T1
,
122 MVE_VSTRH_SCATTER_T2
,
123 MVE_VSTRW_SCATTER_T3
,
124 MVE_VSTRD_SCATTER_T4
,
125 MVE_VSTRW_SCATTER_T5
,
126 MVE_VSTRD_SCATTER_T6
,
128 MVE_VCVT_BETWEEN_FP_INT
,
130 MVE_VCVT_FROM_FP_TO_INT
,
133 MVE_VMOV_GP_TO_VEC_LANE
,
136 MVE_VMOV2_VEC_LANE_TO_GP
,
137 MVE_VMOV2_GP_TO_VEC_LANE
,
138 MVE_VMOV_VEC_LANE_TO_GP
,
150 enum mve_unpredictable
152 UNPRED_IT_BLOCK
, /* Unpredictable because mve insn in it block.
154 UNPRED_FCA_0_FCB_1
, /* Unpredictable because fcA = 0 and
156 UNPRED_R13
, /* Unpredictable because r13 (sp) or
158 UNPRED_R15
, /* Unpredictable because r15 (pc) is used. */
159 UNPRED_Q_GT_4
, /* Unpredictable because
160 vec reg start > 4 (vld4/st4). */
161 UNPRED_Q_GT_6
, /* Unpredictable because
162 vec reg start > 6 (vld2/st2). */
163 UNPRED_R13_AND_WB
, /* Unpredictable becase gp reg = r13
165 UNPRED_Q_REGS_EQUAL
, /* Unpredictable because vector registers are
167 UNPRED_OS
, /* Unpredictable because offset scaled == 1. */
168 UNPRED_GP_REGS_EQUAL
, /* Unpredictable because gp registers are the
170 UNPRED_Q_REGS_EQ_AND_SIZE_1
, /* Unpredictable because q regs equal and
172 UNPRED_Q_REGS_EQ_AND_SIZE_2
, /* Unpredictable because q regs equal and
174 UNPRED_NONE
/* No unpredictable behavior. */
179 UNDEF_SIZE_0
, /* undefined because size == 0. */
180 UNDEF_SIZE_2
, /* undefined because size == 2. */
181 UNDEF_SIZE_3
, /* undefined because size == 3. */
182 UNDEF_SIZE_LE_1
, /* undefined because size <= 1. */
183 UNDEF_SIZE_NOT_2
, /* undefined because size != 2. */
184 UNDEF_SIZE_NOT_3
, /* undefined because size != 3. */
185 UNDEF_NOT_UNS_SIZE_0
, /* undefined because U == 0 and
187 UNDEF_NOT_UNS_SIZE_1
, /* undefined because U == 0 and
189 UNDEF_NOT_UNSIGNED
, /* undefined because U == 0. */
190 UNDEF_VCVT_IMM6
, /* imm6 < 32. */
191 UNDEF_VCVT_FSI_IMM6
, /* fsi = 0 and 32 >= imm6 <= 47. */
192 UNDEF_BAD_OP1_OP2
, /* undefined with op2 = 2 and
194 UNDEF_BAD_U_OP1_OP2
, /* undefined with U = 1 and
195 op2 == 0 and op1 == (0 or 1). */
196 UNDEF_OP_0_BAD_CMODE
, /* undefined because op == 0 and cmode
198 UNDEF_NONE
/* no undefined behavior. */
203 arm_feature_set arch
; /* Architecture defining this insn. */
204 unsigned long value
; /* If arch is 0 then value is a sentinel. */
205 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
206 const char * assembler
; /* How to disassemble this insn. */
213 arm_feature_set arch
; /* Architecture defining this insn. */
214 enum mve_instructions mve_op
; /* Specific mve instruction for faster
216 unsigned long value
; /* If arch is 0 then value is a sentinel. */
217 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
218 const char * assembler
; /* How to disassemble this insn. */
228 /* Shared (between Arm and Thumb mode) opcode. */
231 enum isa isa
; /* Execution mode instruction availability. */
232 arm_feature_set arch
; /* Architecture defining this insn. */
233 unsigned long value
; /* If arch is 0 then value is a sentinel. */
234 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
235 const char * assembler
; /* How to disassemble this insn. */
240 arm_feature_set arch
; /* Architecture defining this insn. */
241 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
242 const char *assembler
; /* How to disassemble this insn. */
245 /* print_insn_coprocessor recognizes the following format control codes:
249 %c print condition code (always bits 28-31 in ARM mode)
250 %q print shifter argument
251 %u print condition code (unconditional in ARM mode,
252 UNPREDICTABLE if not AL in Thumb)
253 %A print address for ldc/stc/ldf/stf instruction
254 %B print vstm/vldm register list
255 %C print vscclrm register list
256 %I print cirrus signed shift immediate: bits 0..3|4..6
257 %J print register for VLDR instruction
258 %K print address for VLDR instruction
259 %F print the COUNT field of a LFM/SFM instruction.
260 %P print floating point precision in arithmetic insn
261 %Q print floating point precision in ldf/stf insn
262 %R print floating point rounding mode
264 %<bitfield>c print as a condition code (for vsel)
265 %<bitfield>r print as an ARM register
266 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
267 %<bitfield>ru as %<>r but each u register must be unique.
268 %<bitfield>d print the bitfield in decimal
269 %<bitfield>k print immediate for VFPv3 conversion instruction
270 %<bitfield>x print the bitfield in hex
271 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
272 %<bitfield>f print a floating point constant if >7 else a
273 floating point register
274 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
275 %<bitfield>g print as an iWMMXt 64-bit register
276 %<bitfield>G print as an iWMMXt general purpose or control register
277 %<bitfield>D print as a NEON D register
278 %<bitfield>Q print as a NEON Q register
279 %<bitfield>V print as a NEON D or Q register
280 %<bitfield>E print a quarter-float immediate value
282 %y<code> print a single precision VFP reg.
283 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
284 %z<code> print a double precision VFP reg
285 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
287 %<bitfield>'c print specified char iff bitfield is all ones
288 %<bitfield>`c print specified char iff bitfield is all zeroes
289 %<bitfield>?ab... select from array of values in big endian order
291 %L print as an iWMMXt N/M width field.
292 %Z print the Immediate of a WSHUFH instruction.
293 %l like 'A' except use byte offsets for 'B' & 'H'
295 %i print 5-bit immediate in bits 8,3..0
297 %r print register offset address for wldt/wstr instruction. */
299 enum opcode_sentinel_enum
301 SENTINEL_IWMMXT_START
= 1,
303 SENTINEL_GENERIC_START
306 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
307 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
308 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
309 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
311 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
313 static const struct sopcode32 coprocessor_opcodes
[] =
315 /* XScale instructions. */
316 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
317 0x0e200010, 0x0fff0ff0,
318 "mia%c\tacc0, %0-3r, %12-15r"},
319 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
320 0x0e280010, 0x0fff0ff0,
321 "miaph%c\tacc0, %0-3r, %12-15r"},
322 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
323 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
324 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
325 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
326 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
327 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
329 /* Intel Wireless MMX technology instructions. */
330 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START
, 0, "" },
331 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
332 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
333 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
334 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
335 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
336 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
337 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
338 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
339 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
340 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
341 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
342 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
343 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
344 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
345 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
346 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
347 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
348 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
349 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
350 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
351 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
352 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
353 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
354 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
355 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
356 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
357 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
358 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
359 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
360 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
361 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
362 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
363 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
364 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
365 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
366 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
367 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
368 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
369 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
370 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
371 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
372 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
373 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
374 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
375 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
376 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
377 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
378 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
379 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
380 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
381 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
382 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
383 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
384 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
385 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
386 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
387 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
388 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
389 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
390 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
391 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
392 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
393 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
394 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
395 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
396 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
397 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
398 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
399 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
400 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
401 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
402 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
403 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
404 0x0e800120, 0x0f800ff0,
405 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
406 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
407 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
408 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
409 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
410 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
411 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
412 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
413 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
414 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
415 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
416 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
417 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
418 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
419 0x0e8000a0, 0x0f800ff0,
420 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
421 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
422 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
423 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
424 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
425 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
426 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
427 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
428 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
429 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
430 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
431 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
432 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
433 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
434 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
435 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
436 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
437 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
438 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
439 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
440 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
441 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
442 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
443 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
444 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
445 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
446 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
447 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
448 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
449 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
450 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
451 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
452 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
453 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
454 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
455 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
456 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
457 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
458 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
459 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
460 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
461 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
462 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
463 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
464 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
465 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
466 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
467 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
468 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
469 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
470 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
471 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
472 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
473 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
474 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
475 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
476 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
477 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
478 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
479 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
480 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
481 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
482 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
483 {ANY
, ARM_FEATURE_CORE_LOW (0),
484 SENTINEL_IWMMXT_END
, 0, "" },
486 /* Floating point coprocessor (FPA) instructions. */
487 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
488 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
489 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
490 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
491 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
492 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
493 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
494 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
495 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
496 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
497 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
498 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
499 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
500 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
501 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
502 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
503 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
504 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
505 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
506 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
507 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
508 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
509 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
510 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
511 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
512 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
513 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
514 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
515 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
516 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
517 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
518 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
519 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
520 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
521 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
522 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
523 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
524 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
525 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
526 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
527 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
528 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
529 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
530 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
531 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
532 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
533 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
534 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
535 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
536 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
537 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
538 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
539 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
540 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
541 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
542 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
543 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
544 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
545 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
546 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
547 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
548 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
549 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
550 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
551 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
552 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
553 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
554 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
555 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
556 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
557 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
558 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
559 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
560 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
561 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
562 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
563 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
564 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
565 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
566 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
567 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
568 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
569 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
570 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
571 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
572 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
574 /* Armv8.1-M Mainline instructions. */
575 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
576 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
577 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
578 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
580 /* ARMv8-M Mainline Security Extensions instructions. */
581 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
582 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
583 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
584 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
586 /* Register load/store. */
587 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
588 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
589 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
590 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
591 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
592 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
593 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
594 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
595 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
596 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
597 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
598 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
599 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
600 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
601 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
602 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
603 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
604 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
605 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
606 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
607 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
608 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
609 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
610 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
611 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
612 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
613 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
614 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
615 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
616 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
617 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
618 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
619 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
620 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
621 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
622 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
624 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
625 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
626 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
627 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
628 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
629 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
630 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
631 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
633 /* Data transfer between ARM and NEON registers. */
634 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
635 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
636 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
637 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
638 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
639 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
640 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
641 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
642 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
643 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
644 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
645 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
646 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
647 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
648 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
649 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
650 /* Half-precision conversion instructions. */
651 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
652 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
653 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
654 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
655 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
656 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
657 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
658 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
660 /* Floating point coprocessor (VFP) instructions. */
661 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
662 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
663 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
664 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
665 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
666 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
667 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
668 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
669 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
670 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
671 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
672 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
673 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
674 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
675 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
676 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
677 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
678 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
679 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
680 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
681 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
682 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
683 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
684 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
685 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
686 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
687 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
688 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
689 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
690 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
691 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
692 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
693 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
694 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
695 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
696 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
697 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
698 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
699 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
700 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
701 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
702 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
703 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
704 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
705 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
706 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
707 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
708 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
709 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
710 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
711 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
712 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
713 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
714 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
715 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
716 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
717 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
718 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
719 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
720 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
721 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
722 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
723 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
724 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
725 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
726 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
727 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
728 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
729 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
730 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
731 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
732 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
733 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
734 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
735 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
736 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
737 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
738 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
739 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
740 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
741 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
742 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
743 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
744 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
745 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
746 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
747 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
748 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
749 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
750 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
751 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
752 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
753 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
754 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
755 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
756 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
757 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
758 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
759 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
760 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
761 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
762 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
763 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
764 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
765 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
766 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
767 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
768 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
769 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
770 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
771 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
772 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
773 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
774 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
775 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
776 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
777 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
778 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
779 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
780 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
781 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
782 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
783 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
784 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
785 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
786 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
787 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
788 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
789 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
790 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
791 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
792 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
793 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
794 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
795 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
796 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
797 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
798 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
800 /* Cirrus coprocessor instructions. */
801 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
802 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
803 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
804 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
805 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
806 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
807 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
808 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
809 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
810 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
811 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
812 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
813 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
814 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
815 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
816 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
817 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
818 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
819 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
820 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
821 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
822 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
823 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
824 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
825 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
826 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
827 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
828 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
829 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
830 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
831 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
832 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
833 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
834 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
835 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
836 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
837 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
838 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
839 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
840 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
841 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
842 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
843 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
844 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
845 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
846 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
847 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
848 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
849 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
850 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
851 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
852 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
853 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
854 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
855 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
856 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
857 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
858 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
859 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
860 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
861 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
862 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
863 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
864 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
865 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
866 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
867 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
868 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
869 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
870 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
871 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
872 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
873 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
874 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
875 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
876 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
877 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
878 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
879 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
880 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
881 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
882 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
883 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
884 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
885 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
886 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
887 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
888 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
889 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
890 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
891 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
892 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
893 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
894 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
895 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
896 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
897 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
898 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
899 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
900 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
901 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
902 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
903 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
904 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
905 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
906 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
907 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
908 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
909 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
910 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
911 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
912 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
913 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
914 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
915 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
916 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
917 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
918 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
919 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
920 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
921 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
922 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
923 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
924 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
925 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
926 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
927 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
928 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
929 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
930 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
931 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
932 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
933 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
934 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
935 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
936 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
937 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
938 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
939 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
940 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
941 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
942 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
943 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
944 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
945 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
946 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
947 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
948 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
949 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
950 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
951 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
952 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
953 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
954 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
955 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
956 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
957 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
958 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
959 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
960 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
961 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
962 0x0e000600, 0x0ff00f10,
963 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
964 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
965 0x0e100600, 0x0ff00f10,
966 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
967 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
968 0x0e200600, 0x0ff00f10,
969 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
970 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
971 0x0e300600, 0x0ff00f10,
972 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
974 /* VFP Fused multiply add instructions. */
975 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
976 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
977 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
978 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
979 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
980 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
981 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
982 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
983 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
984 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
985 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
986 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
987 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
988 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
989 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
990 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
993 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
994 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
995 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
996 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
997 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
998 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
999 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1000 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1001 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1002 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1003 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1004 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1005 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1006 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1007 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1008 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1009 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1010 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1011 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1012 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1013 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1014 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1015 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1016 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1018 /* Generic coprocessor instructions. */
1019 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START
, 0, "" },
1020 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1021 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1022 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1023 0x0c500000, 0x0ff00000,
1024 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1025 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1026 0x0e000000, 0x0f000010,
1027 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1028 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1029 0x0e10f010, 0x0f10f010,
1030 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1031 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1032 0x0e100010, 0x0f100010,
1033 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1034 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1035 0x0e000010, 0x0f100010,
1036 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1037 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1038 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1039 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1040 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1042 /* V6 coprocessor instructions. */
1043 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1044 0xfc500000, 0xfff00000,
1045 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1046 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1047 0xfc400000, 0xfff00000,
1048 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1050 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1051 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1052 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1053 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1054 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1055 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1056 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1057 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1058 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1059 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1060 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1061 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1062 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1063 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1064 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1065 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1066 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1067 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1068 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1069 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1070 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1072 /* Dot Product instructions in the space of coprocessor 13. */
1073 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1074 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1075 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1076 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1078 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1079 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1080 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1081 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1082 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1083 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1084 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1085 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1086 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1087 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1088 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1089 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1090 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1091 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1092 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1093 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1094 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1096 /* V5 coprocessor instructions. */
1097 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1098 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1099 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1100 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1101 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1102 0xfe000000, 0xff000010,
1103 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1104 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1105 0xfe000010, 0xff100010,
1106 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1107 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1108 0xfe100010, 0xff100010,
1109 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1111 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1112 cp_num: bit <11:8> == 0b1001.
1113 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1114 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1115 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1116 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1117 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1118 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1119 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1120 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1121 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1122 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1123 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1124 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1125 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1126 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1127 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1128 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1129 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1130 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1131 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1132 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1133 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1134 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1135 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1136 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1137 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1138 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1139 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1140 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1141 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1142 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1143 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1144 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1145 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1146 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1147 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1148 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1149 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1150 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1151 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1152 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1153 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1154 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1155 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1156 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1157 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1158 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1159 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1160 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1161 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1162 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1163 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1164 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1165 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1166 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1167 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1168 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1169 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1170 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1171 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1172 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1173 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1174 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1175 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1176 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1177 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1178 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1179 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1180 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1181 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1182 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1183 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1185 /* ARMv8.3 javascript conversion instruction. */
1186 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1187 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1189 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1192 /* Neon opcode table: This does not encode the top byte -- that is
1193 checked by the print_insn_neon routine, as it depends on whether we are
1194 doing thumb32 or arm32 disassembly. */
1196 /* print_insn_neon recognizes the following format control codes:
1200 %c print condition code
1201 %u print condition code (unconditional in ARM mode,
1202 UNPREDICTABLE if not AL in Thumb)
1203 %A print v{st,ld}[1234] operands
1204 %B print v{st,ld}[1234] any one operands
1205 %C print v{st,ld}[1234] single->all operands
1207 %E print vmov, vmvn, vorr, vbic encoded constant
1208 %F print vtbl,vtbx register list
1210 %<bitfield>r print as an ARM register
1211 %<bitfield>d print the bitfield in decimal
1212 %<bitfield>e print the 2^N - bitfield in decimal
1213 %<bitfield>D print as a NEON D register
1214 %<bitfield>Q print as a NEON Q register
1215 %<bitfield>R print as a NEON D or Q register
1216 %<bitfield>Sn print byte scaled width limited by n
1217 %<bitfield>Tn print short scaled width limited by n
1218 %<bitfield>Un print long scaled width limited by n
1220 %<bitfield>'c print specified char iff bitfield is all ones
1221 %<bitfield>`c print specified char iff bitfield is all zeroes
1222 %<bitfield>?ab... select from array of values in big endian order. */
1224 static const struct opcode32 neon_opcodes
[] =
1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1228 0xf2b00840, 0xffb00850,
1229 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1230 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1231 0xf2b00000, 0xffb00810,
1232 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1234 /* Data transfer between ARM and NEON registers. */
1235 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1236 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1238 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1239 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1240 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1241 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1242 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1243 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1244 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1245 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1246 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1248 /* Move data element to all lanes. */
1249 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1250 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1251 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1252 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1253 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1254 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1257 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1258 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1259 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1260 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1262 /* Half-precision conversions. */
1263 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1264 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1265 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1266 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1268 /* NEON fused multiply add instructions. */
1269 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1270 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1272 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1274 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1275 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1276 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1278 /* Two registers, miscellaneous. */
1279 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1280 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1281 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1282 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1284 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1285 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1286 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1287 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1288 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1289 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1290 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1291 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1292 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1293 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1294 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1295 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1296 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1297 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1298 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1299 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1300 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1302 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1303 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1304 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1306 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1308 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1310 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1312 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1314 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1315 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1316 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1318 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1320 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1321 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1322 0xf3b20300, 0xffb30fd0,
1323 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1325 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1327 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1329 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1330 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1331 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1333 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1335 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1337 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1339 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1341 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1343 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1345 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1347 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1348 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1349 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1351 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1353 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1354 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1355 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1357 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1358 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1359 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1361 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1363 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1365 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1366 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1367 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1369 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1371 0xf3bb0600, 0xffbf0e10,
1372 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1373 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1374 0xf3b70600, 0xffbf0e10,
1375 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1377 /* Three registers of the same length. */
1378 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1379 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1380 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1381 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1382 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1383 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1384 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1385 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1386 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1387 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1388 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1389 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1390 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1391 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1392 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1393 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1394 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1395 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1397 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1398 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1399 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1401 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1403 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1405 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1407 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1409 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1411 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1413 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1415 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1417 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1418 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1419 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1421 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1422 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1423 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1425 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1426 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1427 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1429 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1430 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1431 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1433 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1435 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1437 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1438 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1439 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1441 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1442 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1443 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1445 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1446 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1447 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1449 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1451 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1453 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1454 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1455 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1457 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1458 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1459 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1461 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1463 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1465 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1466 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1467 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1469 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1470 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1471 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1473 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1475 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1477 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1478 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1479 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1481 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1482 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1483 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1485 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1486 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1487 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1489 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1491 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1493 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1495 0xf2000b00, 0xff800f10,
1496 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1498 0xf2000b10, 0xff800f10,
1499 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1501 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1503 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1505 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1507 0xf3000b00, 0xff800f10,
1508 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1510 0xf2000000, 0xfe800f10,
1511 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1513 0xf2000010, 0xfe800f10,
1514 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1516 0xf2000100, 0xfe800f10,
1517 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1519 0xf2000200, 0xfe800f10,
1520 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1522 0xf2000210, 0xfe800f10,
1523 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1525 0xf2000300, 0xfe800f10,
1526 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1528 0xf2000310, 0xfe800f10,
1529 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1531 0xf2000400, 0xfe800f10,
1532 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1534 0xf2000410, 0xfe800f10,
1535 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1537 0xf2000500, 0xfe800f10,
1538 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1540 0xf2000510, 0xfe800f10,
1541 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1543 0xf2000600, 0xfe800f10,
1544 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1546 0xf2000610, 0xfe800f10,
1547 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1548 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1549 0xf2000700, 0xfe800f10,
1550 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1552 0xf2000710, 0xfe800f10,
1553 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1555 0xf2000910, 0xfe800f10,
1556 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1558 0xf2000a00, 0xfe800f10,
1559 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1561 0xf2000a10, 0xfe800f10,
1562 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1564 0xf3000b10, 0xff800f10,
1565 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1567 0xf3000c10, 0xff800f10,
1568 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1570 /* One register and an immediate value. */
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1572 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1574 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1576 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1578 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1580 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1582 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1584 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1586 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1588 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1590 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1592 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1594 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1596 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1598 /* Two registers and a shift amount. */
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1600 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1602 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1604 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1606 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1608 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1610 0xf2880950, 0xfeb80fd0,
1611 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1613 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1615 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1617 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1619 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1621 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1623 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1625 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1627 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1629 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1631 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1633 0xf2900950, 0xfeb00fd0,
1634 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1636 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1638 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1640 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1642 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1644 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1646 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1648 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1650 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1652 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1654 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1656 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1658 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1660 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1662 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1664 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1665 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1666 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1668 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1670 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1672 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1674 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1676 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1678 0xf2a00950, 0xfea00fd0,
1679 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1681 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1683 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1685 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1687 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1689 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1691 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1693 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1695 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1697 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1699 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1701 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1703 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1705 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1706 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1707 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1709 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1711 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1713 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1715 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1717 0xf2a00e10, 0xfea00e90,
1718 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1719 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1720 0xf2a00c10, 0xfea00e90,
1721 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1723 /* Three registers of different lengths. */
1724 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1725 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1727 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1729 0xf2800400, 0xff800f50,
1730 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1732 0xf2800600, 0xff800f50,
1733 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1734 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1735 0xf2800900, 0xff800f50,
1736 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1738 0xf2800b00, 0xff800f50,
1739 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1741 0xf2800d00, 0xff800f50,
1742 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1744 0xf3800400, 0xff800f50,
1745 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1747 0xf3800600, 0xff800f50,
1748 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1750 0xf2800000, 0xfe800f50,
1751 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1753 0xf2800100, 0xfe800f50,
1754 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1755 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1756 0xf2800200, 0xfe800f50,
1757 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1759 0xf2800300, 0xfe800f50,
1760 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1762 0xf2800500, 0xfe800f50,
1763 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1765 0xf2800700, 0xfe800f50,
1766 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1768 0xf2800800, 0xfe800f50,
1769 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1771 0xf2800a00, 0xfe800f50,
1772 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1774 0xf2800c00, 0xfe800f50,
1775 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1777 /* Two registers and a scalar. */
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1779 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1780 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1781 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1782 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1783 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1785 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1787 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1789 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1790 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1791 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1792 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1793 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1794 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1795 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1797 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1798 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1799 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1800 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1801 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1803 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1804 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1805 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1806 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1807 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1809 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1810 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1811 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1813 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1815 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1816 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1817 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1819 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1821 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1822 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1823 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1825 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1827 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1829 0xf2800240, 0xfe800f50,
1830 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1831 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1832 0xf2800640, 0xfe800f50,
1833 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1835 0xf2800a40, 0xfe800f50,
1836 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1837 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1838 0xf2800e40, 0xff800f50,
1839 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1841 0xf2800f40, 0xff800f50,
1842 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1843 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1844 0xf3800e40, 0xff800f50,
1845 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1847 0xf3800f40, 0xff800f50,
1848 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1851 /* Element and structure load/store. */
1852 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1853 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1854 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1855 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1856 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1857 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1858 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1859 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1860 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1861 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1862 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1863 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1864 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1865 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1866 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1867 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1868 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1869 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1870 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1871 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1872 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1873 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1874 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1875 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1876 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1877 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1878 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1879 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1880 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1881 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1882 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1883 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1884 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1885 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1886 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1887 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1888 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1889 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1891 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1894 /* mve opcode table. */
1896 /* print_insn_mve recognizes the following format control codes:
1900 %a print '+' or '-' or imm offset in vldr[bhwd] and
1902 %c print condition code
1903 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1904 %u print 'U' (unsigned) or 'S' for various mve instructions
1905 %i print MVE predicate(s) for vpt and vpst
1906 %m print rounding mode for vcvt and vrint
1907 %n print vector comparison code for predicated instruction
1908 %s print size for various vcvt instructions
1909 %v print vector predicate for instruction in predicated
1911 %o print offset scaled for vldr[hwd] and vstr[hwd]
1912 %w print writeback mode for MVE v{st,ld}[24]
1913 %B print v{st,ld}[24] any one operands
1914 %E print vmov, vmvn, vorr, vbic encoded constant
1915 %N print generic index for vmov
1917 %<bitfield>r print as an ARM register
1918 %<bitfield>d print the bitfield in decimal
1919 %<bitfield>Q print as a MVE Q register
1920 %<bitfield>F print as a MVE S register
1921 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
1923 %<bitfield>s print size for vector predicate & non VMOV instructions
1924 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1925 %<bitfield>k print immediate for vector conversion instruction
1926 %<bitfield>x print the bitfield in hex.
1929 static const struct mopcode32 mve_opcodes
[] =
1933 {ARM_FEATURE_COPROC (FPU_MVE
),
1935 0xfe310f4d, 0xffbf1fff,
1939 /* Floating point VPT T1. */
1940 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1942 0xee310f00, 0xefb10f50,
1943 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
1944 /* Floating point VPT T2. */
1945 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1947 0xee310f40, 0xefb10f50,
1948 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
1950 /* Vector VPT T1. */
1951 {ARM_FEATURE_COPROC (FPU_MVE
),
1953 0xfe010f00, 0xff811f51,
1954 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1955 /* Vector VPT T2. */
1956 {ARM_FEATURE_COPROC (FPU_MVE
),
1958 0xfe010f01, 0xff811f51,
1959 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1960 /* Vector VPT T3. */
1961 {ARM_FEATURE_COPROC (FPU_MVE
),
1963 0xfe011f00, 0xff811f50,
1964 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
1965 /* Vector VPT T4. */
1966 {ARM_FEATURE_COPROC (FPU_MVE
),
1968 0xfe010f40, 0xff811f70,
1969 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
1970 /* Vector VPT T5. */
1971 {ARM_FEATURE_COPROC (FPU_MVE
),
1973 0xfe010f60, 0xff811f70,
1974 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
1975 /* Vector VPT T6. */
1976 {ARM_FEATURE_COPROC (FPU_MVE
),
1978 0xfe011f40, 0xff811f50,
1979 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
1981 /* Vector VBIC immediate. */
1982 {ARM_FEATURE_COPROC (FPU_MVE
),
1984 0xef800070, 0xefb81070,
1985 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
1987 /* Vector VBIC register. */
1988 {ARM_FEATURE_COPROC (FPU_MVE
),
1990 0xef100150, 0xffb11f51,
1991 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
1993 /* Vector VCMP floating point T1. */
1994 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1996 0xee310f00, 0xeff1ef50,
1997 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
1999 /* Vector VCMP floating point T2. */
2000 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2002 0xee310f40, 0xeff1ef50,
2003 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2005 /* Vector VCMP T1. */
2006 {ARM_FEATURE_COPROC (FPU_MVE
),
2008 0xfe010f00, 0xffc1ff51,
2009 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2010 /* Vector VCMP T2. */
2011 {ARM_FEATURE_COPROC (FPU_MVE
),
2013 0xfe010f01, 0xffc1ff51,
2014 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2015 /* Vector VCMP T3. */
2016 {ARM_FEATURE_COPROC (FPU_MVE
),
2018 0xfe011f00, 0xffc1ff50,
2019 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2020 /* Vector VCMP T4. */
2021 {ARM_FEATURE_COPROC (FPU_MVE
),
2023 0xfe010f40, 0xffc1ff70,
2024 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2025 /* Vector VCMP T5. */
2026 {ARM_FEATURE_COPROC (FPU_MVE
),
2028 0xfe010f60, 0xffc1ff70,
2029 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2030 /* Vector VCMP T6. */
2031 {ARM_FEATURE_COPROC (FPU_MVE
),
2033 0xfe011f40, 0xffc1ff50,
2034 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2037 {ARM_FEATURE_COPROC (FPU_MVE
),
2039 0xeea00b10, 0xffb10f5f,
2040 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2043 {ARM_FEATURE_COPROC (FPU_MVE
),
2045 0xff000150, 0xffd11f51,
2046 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2048 /* Vector VFMA, vector * scalar. */
2049 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2051 0xee310e40, 0xefb11f70,
2052 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2054 /* Vector VFMA floating point. */
2055 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2057 0xef000c50, 0xffa11f51,
2058 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2060 /* Vector VFMS floating point. */
2061 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2063 0xef200c50, 0xffa11f51,
2064 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2066 /* Vector VFMAS, vector * scalar. */
2067 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2068 MVE_VFMAS_FP_SCALAR
,
2069 0xee311e40, 0xefb11f70,
2070 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2072 /* Vector VHADD T1. */
2073 {ARM_FEATURE_COPROC (FPU_MVE
),
2075 0xef000040, 0xef811f51,
2076 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2078 /* Vector VHADD T2. */
2079 {ARM_FEATURE_COPROC (FPU_MVE
),
2081 0xee000f40, 0xef811f70,
2082 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2084 /* Vector VHSUB T1. */
2085 {ARM_FEATURE_COPROC (FPU_MVE
),
2087 0xef000240, 0xef811f51,
2088 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2090 /* Vector VHSUB T2. */
2091 {ARM_FEATURE_COPROC (FPU_MVE
),
2093 0xee001f40, 0xef811f70,
2094 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2097 {ARM_FEATURE_COPROC (FPU_MVE
),
2099 0xeea00b10, 0xffb10f5f,
2100 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2102 /* Vector VRHADD. */
2103 {ARM_FEATURE_COPROC (FPU_MVE
),
2105 0xef000140, 0xef811f51,
2106 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2109 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2110 MVE_VCVT_FP_FIX_VEC
,
2111 0xef800c50, 0xef801cd1,
2112 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2115 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2116 MVE_VCVT_BETWEEN_FP_INT
,
2117 0xffb30640, 0xffb31e51,
2118 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2120 /* Vector VCVT between single and half-precision float, bottom half. */
2121 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2122 MVE_VCVT_FP_HALF_FP
,
2123 0xee3f0e01, 0xefbf1fd1,
2124 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2126 /* Vector VCVT between single and half-precision float, top half. */
2127 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2128 MVE_VCVT_FP_HALF_FP
,
2129 0xee3f1e01, 0xefbf1fd1,
2130 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2133 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2134 MVE_VCVT_FROM_FP_TO_INT
,
2135 0xffb30040, 0xffb31c51,
2136 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2139 {ARM_FEATURE_COPROC (FPU_MVE
),
2141 0xfc901e00, 0xff901e5f,
2142 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2145 {ARM_FEATURE_COPROC (FPU_MVE
),
2147 0xfc901e01, 0xff901e1f,
2148 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2150 /* Vector VLDRB gather load. */
2151 {ARM_FEATURE_COPROC (FPU_MVE
),
2152 MVE_VLDRB_GATHER_T1
,
2153 0xec900e00, 0xefb01e50,
2154 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2156 /* Vector VLDRH gather load. */
2157 {ARM_FEATURE_COPROC (FPU_MVE
),
2158 MVE_VLDRH_GATHER_T2
,
2159 0xec900e10, 0xefb01e50,
2160 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2162 /* Vector VLDRW gather load. */
2163 {ARM_FEATURE_COPROC (FPU_MVE
),
2164 MVE_VLDRW_GATHER_T3
,
2165 0xfc900f40, 0xffb01fd0,
2166 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2168 /* Vector VLDRD gather load. */
2169 {ARM_FEATURE_COPROC (FPU_MVE
),
2170 MVE_VLDRD_GATHER_T4
,
2171 0xec900fd0, 0xefb01fd0,
2172 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2174 /* Vector VLDRW gather load. */
2175 {ARM_FEATURE_COPROC (FPU_MVE
),
2176 MVE_VLDRW_GATHER_T5
,
2177 0xfd101e00, 0xff111f00,
2178 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2180 /* Vector VLDRD gather load, variant T6. */
2181 {ARM_FEATURE_COPROC (FPU_MVE
),
2182 MVE_VLDRD_GATHER_T6
,
2183 0xfd101f00, 0xff111f00,
2184 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2187 {ARM_FEATURE_COPROC (FPU_MVE
),
2189 0xec100e00, 0xee581e00,
2190 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2193 {ARM_FEATURE_COPROC (FPU_MVE
),
2195 0xec180e00, 0xee581e00,
2196 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2198 /* Vector VLDRB unsigned, variant T5. */
2199 {ARM_FEATURE_COPROC (FPU_MVE
),
2201 0xec101e00, 0xfe101f80,
2202 "vldrb%v.u8\t%13-15,22Q, %d"},
2204 /* Vector VLDRH unsigned, variant T6. */
2205 {ARM_FEATURE_COPROC (FPU_MVE
),
2207 0xec101e80, 0xfe101f80,
2208 "vldrh%v.u16\t%13-15,22Q, %d"},
2210 /* Vector VLDRW unsigned, variant T7. */
2211 {ARM_FEATURE_COPROC (FPU_MVE
),
2213 0xec101f00, 0xfe101f80,
2214 "vldrw%v.u32\t%13-15,22Q, %d"},
2216 /* Vector VMOV between gpr and half precision register, op == 0. */
2217 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2219 0xee000910, 0xfff00f7f,
2220 "vmov.f16\t%7,16-19F, %12-15r"},
2222 /* Vector VMOV between gpr and half precision register, op == 1. */
2223 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2225 0xee100910, 0xfff00f7f,
2226 "vmov.f16\t%12-15r, %7,16-19F"},
2228 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2229 MVE_VMOV_GP_TO_VEC_LANE
,
2230 0xee000b10, 0xff900f1f,
2231 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2233 /* Vector VORR immediate to vector.
2234 NOTE: MVE_VORR_IMM must appear in the table
2235 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2236 {ARM_FEATURE_COPROC (FPU_MVE
),
2238 0xef800050, 0xefb810f0,
2239 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2241 /* Vector VMOV immediate to vector,
2242 cmode == 11x1 -> VMVN which is UNDEFINED
2243 for such a cmode. */
2244 {ARM_FEATURE_COPROC (FPU_MVE
),
2245 MVE_VMVN_IMM
, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION
},
2247 /* Vector VMOV immediate to vector. */
2248 {ARM_FEATURE_COPROC (FPU_MVE
),
2249 MVE_VMOV_IMM_TO_VEC
,
2250 0xef800050, 0xefb810d0,
2251 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2253 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2254 {ARM_FEATURE_COPROC (FPU_MVE
),
2255 MVE_VMOV2_VEC_LANE_TO_GP
,
2256 0xec000f00, 0xffb01ff0,
2257 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2259 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2260 {ARM_FEATURE_COPROC (FPU_MVE
),
2261 MVE_VMOV2_VEC_LANE_TO_GP
,
2262 0xec000f10, 0xffb01ff0,
2263 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2265 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2266 {ARM_FEATURE_COPROC (FPU_MVE
),
2267 MVE_VMOV2_GP_TO_VEC_LANE
,
2268 0xec100f00, 0xffb01ff0,
2269 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2271 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2272 {ARM_FEATURE_COPROC (FPU_MVE
),
2273 MVE_VMOV2_GP_TO_VEC_LANE
,
2274 0xec100f10, 0xffb01ff0,
2275 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2277 /* Vector VMOV Vector lane to gpr. */
2278 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2279 MVE_VMOV_VEC_LANE_TO_GP
,
2280 0xee100b10, 0xff100f1f,
2281 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2283 /* Floating point move extract. */
2284 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2286 0xfeb00a40, 0xffbf0fd0,
2287 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2289 /* Vector VMVN immediate to vector. */
2290 {ARM_FEATURE_COPROC (FPU_MVE
),
2292 0xef800070, 0xefb810f0,
2293 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2295 /* Vector VMVN register. */
2296 {ARM_FEATURE_COPROC (FPU_MVE
),
2298 0xffb005c0, 0xffbf1fd1,
2299 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2301 /* Vector VORN, vector bitwise or not. */
2302 {ARM_FEATURE_COPROC (FPU_MVE
),
2304 0xef300150, 0xffb11f51,
2305 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2307 /* Vector VORR register. */
2308 {ARM_FEATURE_COPROC (FPU_MVE
),
2310 0xef200150, 0xffb11f51,
2311 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2313 /* Vector VRINT floating point. */
2314 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2316 0xffb20440, 0xffb31c51,
2317 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2319 /* Vector VST2 no writeback. */
2320 {ARM_FEATURE_COPROC (FPU_MVE
),
2322 0xfc801e00, 0xffb01e5f,
2323 "vst2%5d.%7-8s\t%B, [%16-19r]"},
2325 /* Vector VST2 writeback. */
2326 {ARM_FEATURE_COPROC (FPU_MVE
),
2328 0xfca01e00, 0xffb01e5f,
2329 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2331 /* Vector VST4 no writeback. */
2332 {ARM_FEATURE_COPROC (FPU_MVE
),
2334 0xfc801e01, 0xffb01e1f,
2335 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2337 /* Vector VST4 writeback. */
2338 {ARM_FEATURE_COPROC (FPU_MVE
),
2340 0xfca01e01, 0xffb01e1f,
2341 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2343 /* Vector VSTRB scatter store, T1 variant. */
2344 {ARM_FEATURE_COPROC (FPU_MVE
),
2345 MVE_VSTRB_SCATTER_T1
,
2346 0xec800e00, 0xffb01e50,
2347 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2349 /* Vector VSTRH scatter store, T2 variant. */
2350 {ARM_FEATURE_COPROC (FPU_MVE
),
2351 MVE_VSTRH_SCATTER_T2
,
2352 0xec800e10, 0xffb01e50,
2353 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2355 /* Vector VSTRW scatter store, T3 variant. */
2356 {ARM_FEATURE_COPROC (FPU_MVE
),
2357 MVE_VSTRW_SCATTER_T3
,
2358 0xec800e40, 0xffb01e50,
2359 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2361 /* Vector VSTRD scatter store, T4 variant. */
2362 {ARM_FEATURE_COPROC (FPU_MVE
),
2363 MVE_VSTRD_SCATTER_T4
,
2364 0xec800fd0, 0xffb01fd0,
2365 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2367 /* Vector VSTRW scatter store, T5 variant. */
2368 {ARM_FEATURE_COPROC (FPU_MVE
),
2369 MVE_VSTRW_SCATTER_T5
,
2370 0xfd001e00, 0xff111f00,
2371 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2373 /* Vector VSTRD scatter store, T6 variant. */
2374 {ARM_FEATURE_COPROC (FPU_MVE
),
2375 MVE_VSTRD_SCATTER_T6
,
2376 0xfd001f00, 0xff111f00,
2377 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2380 {ARM_FEATURE_COPROC (FPU_MVE
),
2382 0xec000e00, 0xfe581e00,
2383 "vstrb%v.%7-8s\t%13-15Q, %d"},
2386 {ARM_FEATURE_COPROC (FPU_MVE
),
2388 0xec080e00, 0xfe581e00,
2389 "vstrh%v.%7-8s\t%13-15Q, %d"},
2391 /* Vector VSTRB variant T5. */
2392 {ARM_FEATURE_COPROC (FPU_MVE
),
2394 0xec001e00, 0xfe101f80,
2395 "vstrb%v.8\t%13-15,22Q, %d"},
2397 /* Vector VSTRH variant T6. */
2398 {ARM_FEATURE_COPROC (FPU_MVE
),
2400 0xec001e80, 0xfe101f80,
2401 "vstrh%v.16\t%13-15,22Q, %d"},
2403 /* Vector VSTRW variant T7. */
2404 {ARM_FEATURE_COPROC (FPU_MVE
),
2406 0xec001f00, 0xfe101f80,
2407 "vstrw%v.32\t%13-15,22Q, %d"},
2409 {ARM_FEATURE_CORE_LOW (0),
2411 0x00000000, 0x00000000, 0}
2414 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
2415 ordered: they must be searched linearly from the top to obtain a correct
2418 /* print_insn_arm recognizes the following format control codes:
2422 %a print address for ldr/str instruction
2423 %s print address for ldr/str halfword/signextend instruction
2424 %S like %s but allow UNPREDICTABLE addressing
2425 %b print branch destination
2426 %c print condition code (always bits 28-31)
2427 %m print register mask for ldm/stm instruction
2428 %o print operand2 (immediate or register + shift)
2429 %p print 'p' iff bits 12-15 are 15
2430 %t print 't' iff bit 21 set and bit 24 clear
2431 %B print arm BLX(1) destination
2432 %C print the PSR sub type.
2433 %U print barrier type.
2434 %P print address for pli instruction.
2436 %<bitfield>r print as an ARM register
2437 %<bitfield>T print as an ARM register + 1
2438 %<bitfield>R as %r but r15 is UNPREDICTABLE
2439 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
2440 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
2441 %<bitfield>d print the bitfield in decimal
2442 %<bitfield>W print the bitfield plus one in decimal
2443 %<bitfield>x print the bitfield in hex
2444 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2446 %<bitfield>'c print specified char iff bitfield is all ones
2447 %<bitfield>`c print specified char iff bitfield is all zeroes
2448 %<bitfield>?ab... select from array of values in big endian order
2450 %e print arm SMI operand (bits 0..7,8..19).
2451 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
2452 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
2453 %R print the SPSR/CPSR or banked register of an MRS. */
2455 static const struct opcode32 arm_opcodes
[] =
2457 /* ARM instructions. */
2458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2459 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2461 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
2463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
),
2464 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
2465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
2466 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
2467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
2468 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
),
2470 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
2471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
2472 0x00800090, 0x0fa000f0,
2473 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
2475 0x00a00090, 0x0fa000f0,
2476 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2478 /* V8.2 RAS extension instructions. */
2479 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
2480 0xe320f010, 0xffffffff, "esb"},
2482 /* V8 instructions. */
2483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2484 0x0320f005, 0x0fffffff, "sevl"},
2485 /* Defined in V8 but is in NOP space so available to all arch. */
2486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2487 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
2488 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
),
2489 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
2490 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2491 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2493 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
2494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2495 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
2496 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2497 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
2498 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2499 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2500 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2501 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
2502 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2503 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2504 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2505 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
2506 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2507 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
2508 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2509 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
2510 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2511 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2512 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2513 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
2514 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2515 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2516 /* CRC32 instructions. */
2517 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2518 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
2519 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2520 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
2521 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2522 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
2523 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2524 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
2525 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2526 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
2527 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2528 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
2530 /* Privileged Access Never extension instructions. */
2531 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
2532 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
2534 /* Virtualization Extension instructions. */
2535 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x0160006e, 0x0fffffff, "eret%c"},
2536 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
2538 /* Integer Divide Extension instructions. */
2539 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
2540 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
2541 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
2542 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
2544 /* MP Extension instructions. */
2545 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf410f000, 0xfc70f000, "pldw\t%a"},
2547 /* Speculation Barriers. */
2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xe320f014, 0xffffffff, "csdb"},
2549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff040, 0xffffffff, "ssbb"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff044, 0xffffffff, "pssbb"},
2552 /* V7 instructions. */
2553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf450f000, 0xfd70f000, "pli\t%P"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
2555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
2557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
2559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff060, 0xfffffff0, "isb\t%U"},
2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
2561 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
2563 /* ARM V6T2 instructions. */
2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2565 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2567 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2569 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2571 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
2573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2574 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
2575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2576 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
2578 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2579 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
2580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2581 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2583 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2585 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
2587 /* ARM Security extension instructions. */
2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
2589 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2591 /* ARM V6K instructions. */
2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2593 0xf57ff01f, 0xffffffff, "clrex"},
2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2595 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2597 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2599 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2601 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
2602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2603 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2605 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
2607 /* ARMv8.5-A instructions. */
2608 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf57ff070, 0xffffffff, "sb"},
2610 /* ARM V6K NOP hints. */
2611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2612 0x0320f001, 0x0fffffff, "yield%c"},
2613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2614 0x0320f002, 0x0fffffff, "wfe%c"},
2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2616 0x0320f003, 0x0fffffff, "wfi%c"},
2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2618 0x0320f004, 0x0fffffff, "sev%c"},
2619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2620 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
2622 /* ARM V6 instructions. */
2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2624 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
2625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2626 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
2627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2628 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
2629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2630 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
2631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2632 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
2633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2634 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
2635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2636 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
2637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2638 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
2639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2640 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
2641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2642 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
2643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2644 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
2645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2646 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
2647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2648 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
2649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2650 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
2651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2652 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
2653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2654 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
2655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2656 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
2657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2658 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
2659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2660 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
2661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2662 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
2663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2664 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
2665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2666 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
2667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2668 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
2669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2670 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2672 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2674 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2676 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2678 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2680 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2682 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2684 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2686 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
2687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2688 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
2689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2690 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
2691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2692 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
2693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2694 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2696 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2698 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2700 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2702 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2704 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2706 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2708 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2710 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2712 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2714 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2716 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2718 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2720 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2722 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2724 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2726 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2728 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2730 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2732 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2734 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2736 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2738 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2740 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2742 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2744 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2746 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2748 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2750 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2752 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2754 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2756 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2758 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2760 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2762 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2764 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2766 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2768 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2770 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2772 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2774 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2776 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2778 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2780 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2782 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2784 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2786 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2788 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2790 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2792 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2794 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2796 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2798 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2800 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2802 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2804 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2806 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2808 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2810 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2812 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2814 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2816 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2818 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2820 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2822 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2824 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2826 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2828 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2830 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2832 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2834 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2836 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2838 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2840 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2842 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2844 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2846 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2848 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2850 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2852 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2854 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2856 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2858 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2860 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2862 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2864 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2866 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
2868 /* V5J instruction. */
2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
),
2870 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
2872 /* V5 Instructions. */
2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2874 0xe1200070, 0xfff000f0,
2875 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2877 0xfa000000, 0xfe000000, "blx\t%B"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2879 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2881 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2883 /* V5E "El Segundo" Instructions. */
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
2885 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
2887 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
2889 0xf450f000, 0xfc70f000, "pld\t%a"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2891 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2893 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2895 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2897 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2900 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2902 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2905 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2907 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2909 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2911 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2914 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2916 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2918 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2920 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2923 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2925 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2928 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2930 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2932 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2934 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2936 /* ARM Instructions. */
2937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2938 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2941 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2943 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2945 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2947 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2949 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2951 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2954 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2956 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2958 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2960 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2963 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2965 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2967 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2969 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2972 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2974 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2976 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2979 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2981 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2983 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2986 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2988 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2990 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2993 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2995 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2997 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3000 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3002 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3004 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3007 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3009 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3011 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3014 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3016 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3018 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3021 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3023 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3025 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3027 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
3028 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
3030 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
3032 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3035 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3037 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3039 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3042 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
3043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3044 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
3045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3046 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3049 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3051 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3053 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3056 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3058 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3060 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3063 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3065 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3067 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3070 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3072 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3074 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3076 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3078 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3080 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3082 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3085 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3087 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3089 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3092 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3094 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3096 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3099 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
3100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3101 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3104 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3107 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3109 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3112 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3114 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3116 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3118 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3120 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3122 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3124 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3126 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3128 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3130 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3132 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3134 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3136 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3138 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3140 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3142 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3144 0x092d0000, 0x0fff0000, "push%c\t%m"},
3145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3146 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3148 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3151 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3153 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3155 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3157 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3159 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3161 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3163 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3165 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3167 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3169 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3171 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3173 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3175 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3177 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3179 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3181 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3183 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3185 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3187 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3190 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3192 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
3195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
3196 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION
},
3197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3198 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
3199 {ARM_FEATURE_CORE_LOW (0),
3200 0x00000000, 0x00000000, 0}
3203 /* print_insn_thumb16 recognizes the following format control codes:
3205 %S print Thumb register (bits 3..5 as high number if bit 6 set)
3206 %D print Thumb register (bits 0..2 as high number if bit 7 set)
3207 %<bitfield>I print bitfield as a signed decimal
3208 (top bit of range being the sign bit)
3209 %N print Thumb register mask (with LR)
3210 %O print Thumb register mask (with PC)
3211 %M print Thumb register mask
3212 %b print CZB's 6-bit unsigned branch destination
3213 %s print Thumb right-shift immediate (6..10; 0 == 32).
3214 %c print the condition code
3215 %C print the condition code, or "s" if not conditional
3216 %x print warning if conditional an not at end of IT block"
3217 %X print "\t; unpredictable <IT:code>" if conditional
3218 %I print IT instruction suffix and operands
3219 %W print Thumb Writeback indicator for LDMIA
3220 %<bitfield>r print bitfield as an ARM register
3221 %<bitfield>d print bitfield as a decimal
3222 %<bitfield>H print (bitfield * 2) as a decimal
3223 %<bitfield>W print (bitfield * 4) as a decimal
3224 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3225 %<bitfield>B print Thumb branch destination (signed displacement)
3226 %<bitfield>c print bitfield as a condition code
3227 %<bitnum>'c print specified char iff bit is one
3228 %<bitnum>?ab print a if bit is one else print b. */
3230 static const struct opcode16 thumb_opcodes
[] =
3232 /* Thumb instructions. */
3234 /* ARMv8-M Security Extensions instructions. */
3235 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4784, 0xff87, "blxns\t%3-6r"},
3236 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4704, 0xff87, "bxns\t%3-6r"},
3238 /* ARM V8 instructions. */
3239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xbf50, 0xffff, "sevl%c"},
3240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xba80, 0xffc0, "hlt\t%0-5x"},
3241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
), 0xb610, 0xfff7, "setpan\t#%3-3d"},
3243 /* ARM V6K no-argument instructions. */
3244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xffff, "nop%c"},
3245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf10, 0xffff, "yield%c"},
3246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf20, 0xffff, "wfe%c"},
3247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf30, 0xffff, "wfi%c"},
3248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf40, 0xffff, "sev%c"},
3249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
3251 /* ARM V6T2 instructions. */
3252 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3253 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
3254 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3255 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
3256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xbf00, 0xff00, "it%I%X"},
3259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
3260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
3261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
3262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
3263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
3264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
3265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb650, 0xfff7, "setend\t%3?ble%X"},
3266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
3267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
3268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
3269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
3271 /* ARM V5 ISA extends Thumb. */
3272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
3273 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
3274 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
3275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
3276 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
3277 /* ARM V4T ISA (Thumb v1). */
3278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3279 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
3281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
3282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
3283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
3284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
3298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
3301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4700, 0xFF80, "bx%c\t%S%x"},
3302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4400, 0xFF00, "add%c\t%D, %S"},
3303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4600, 0xFF00, "mov%c\t%D, %S"},
3306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB400, 0xFE00, "push%c\t%N"},
3307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xBC00, 0xFE00, "pop%c\t%O"},
3309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3310 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3312 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3314 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3316 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
3318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3319 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3321 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3323 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
3325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3326 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3328 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3332 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
3336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
3341 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3344 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
3346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3347 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3349 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3351 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3353 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
3355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3356 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3358 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
3360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3361 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3363 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
3365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3366 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3368 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
3370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
3373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
3375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
3376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
3377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
3379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
3381 /* The E800 .. FFFF range is unconditionally redirected to the
3382 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3383 are processed via that table. Thus, we can never encounter a
3384 bare "second half of BL/BLX(1)" instruction here. */
3385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
), 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
3386 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3389 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
3390 We adopt the convention that hw1 is the high 16 bits of .value and
3391 .mask, hw2 the low 16 bits.
3393 print_insn_thumb32 recognizes the following format control codes:
3397 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3398 %M print a modified 12-bit immediate (same location)
3399 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
3400 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
3401 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
3402 %S print a possibly-shifted Rm
3404 %L print address for a ldrd/strd instruction
3405 %a print the address of a plain load/store
3406 %w print the width and signedness of a core load/store
3407 %m print register mask for ldm/stm
3408 %n print register mask for clrm
3410 %E print the lsb and width fields of a bfc/bfi instruction
3411 %F print the lsb and width fields of a sbfx/ubfx instruction
3412 %G print a fallback offset for Branch Future instructions
3413 %W print an offset for BF instruction
3414 %Y print an offset for BFL instruction
3415 %Z print an offset for BFCSEL instruction
3416 %Q print an offset for Low Overhead Loop instructions
3417 %P print an offset for Low Overhead Loop end instructions
3418 %b print a conditional branch offset
3419 %B print an unconditional branch offset
3420 %s print the shift field of an SSAT instruction
3421 %R print the rotation field of an SXT instruction
3422 %U print barrier type.
3423 %P print address for pli instruction.
3424 %c print the condition code
3425 %x print warning if conditional an not at end of IT block"
3426 %X print "\t; unpredictable <IT:code>" if conditional
3428 %<bitfield>d print bitfield in decimal
3429 %<bitfield>D print bitfield plus one in decimal
3430 %<bitfield>W print bitfield*4 in decimal
3431 %<bitfield>r print bitfield as an ARM register
3432 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
3433 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
3434 %<bitfield>c print bitfield as a condition code
3436 %<bitfield>'c print specified char iff bitfield is all ones
3437 %<bitfield>`c print specified char iff bitfield is all zeroes
3438 %<bitfield>?ab... select from array of values in big endian order
3440 With one exception at the bottom (done because BL and BLX(1) need
3441 to come dead last), this table was machine-sorted first in
3442 decreasing order of number of bits set in the mask, then in
3443 increasing numeric order of mask, then in increasing numeric order
3444 of opcode. This order is not the clearest for a human reader, but
3445 is guaranteed never to catch a special-case bit pattern with a more
3446 general mask, which is important, because this instruction encoding
3447 makes heavy use of special-case bit patterns. */
3448 static const struct opcode32 thumb32_opcodes
[] =
3450 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
3452 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3453 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
3454 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3455 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
3456 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3457 0xf02fc001, 0xfffff001, "le\t%P"},
3458 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3459 0xf00fc001, 0xfffff001, "le\tlr, %P"},
3461 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3462 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
3463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3464 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
3465 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3466 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
3467 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3468 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
3469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3470 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
3472 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3473 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
3475 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
3476 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0xe97fe97f, 0xffffffff, "sg"},
3477 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3478 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
3479 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3480 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
3481 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3482 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
3483 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3484 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
3486 /* ARM V8.2 RAS extension instructions. */
3487 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
3488 0xf3af8010, 0xffffffff, "esb"},
3490 /* V8 instructions. */
3491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3492 0xf3af8005, 0xffffffff, "sevl%c.w"},
3493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3494 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
3495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3496 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
3497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3498 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
3499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3500 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
3501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3502 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
3503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3504 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
3505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3506 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
3507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3508 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
3509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3510 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3512 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3514 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
3515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3516 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3518 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3520 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3522 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
3524 /* CRC32 instructions. */
3525 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3526 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
3527 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3528 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
3529 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3530 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
3531 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3532 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
3533 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3534 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
3535 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3536 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
3538 /* Speculation Barriers. */
3539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8014, 0xffffffff, "csdb"},
3540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f40, 0xffffffff, "ssbb"},
3541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f44, 0xffffffff, "pssbb"},
3543 /* V7 instructions. */
3544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf910f000, 0xff70f000, "pli%c\t%a"},
3545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
3546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
3547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
3548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
3549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
3550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
3551 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
3552 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
3553 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
3554 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
3556 /* Virtualization Extension instructions. */
3557 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
3558 /* We skip ERET as that is SUBS pc, lr, #0. */
3560 /* MP Extension instructions. */
3561 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
3563 /* Security extension instructions. */
3564 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
3566 /* ARMv8.5-A instructions. */
3567 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf3bf8f70, 0xffffffff, "sb"},
3569 /* Instructions defined in the basic V6T2 set. */
3570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8000, 0xffffffff, "nop%c.w"},
3571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8001, 0xffffffff, "yield%c.w"},
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8002, 0xffffffff, "wfe%c.w"},
3573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8003, 0xffffffff, "wfi%c.w"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8004, 0xffffffff, "sev%c.w"},
3575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3576 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
3577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
3579 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3580 0xf3bf8f2f, 0xffffffff, "clrex%c"},
3581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3582 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
3583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3584 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
3585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3586 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
3587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3588 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
3589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3590 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
3591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3592 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
3593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3594 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
3595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3596 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
3597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3598 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
3599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3600 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
3601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3602 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
3603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3604 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
3605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3606 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
3607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3608 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
3609 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3610 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
3611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3612 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
3613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3614 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
3615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3616 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
3617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3618 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
3619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3620 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
3621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3622 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
3623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3624 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
3625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3626 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
3627 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3628 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
3629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3630 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
3631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3632 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
3633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3634 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
3635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3636 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
3637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3638 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
3639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3640 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
3641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3642 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
3643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3644 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
3645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3646 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
3647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3648 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3650 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3652 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3654 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
3655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3656 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
3657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3658 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3660 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3662 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3664 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3666 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3668 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3670 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3672 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3674 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3676 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3678 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3680 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3682 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3684 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3686 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3688 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3690 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3692 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3694 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3696 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3698 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3700 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3702 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3704 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3706 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3708 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3710 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3712 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3714 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3716 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3718 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3720 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3722 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3724 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3726 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3728 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3730 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3732 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3734 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
3735 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3736 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3738 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
3739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3740 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3742 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3744 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3746 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3748 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3750 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3752 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3754 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3756 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3758 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3760 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3762 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3764 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3766 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3768 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3770 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3772 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3774 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3776 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3778 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3780 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3782 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3784 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3786 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3788 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3790 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3792 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3794 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3796 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3798 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3800 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3802 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3803 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3804 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3806 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3808 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3810 0xf810f000, 0xff70f000, "pld%c\t%a"},
3811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3812 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3814 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3816 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3818 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3820 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3822 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3824 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3826 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3828 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3830 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3832 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3834 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3836 0xfb100000, 0xfff000c0,
3837 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3839 0xfbc00080, 0xfff000c0,
3840 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3842 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3844 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3846 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
3847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3848 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3850 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3851 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3852 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3854 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3855 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3856 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3858 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3860 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3862 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3864 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3866 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3868 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3870 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3872 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3874 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3876 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3877 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3878 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3880 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3882 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3884 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3886 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3888 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3890 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3892 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3894 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3896 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3898 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3900 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3902 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3904 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3906 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3908 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3910 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3912 0xe9400000, 0xff500000,
3913 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3915 0xe9500000, 0xff500000,
3916 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3918 0xe8600000, 0xff700000,
3919 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3921 0xe8700000, 0xff700000,
3922 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3924 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3926 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3928 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
3929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3930 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3932 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3934 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3936 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3938 /* These have been 32-bit since the invention of Thumb. */
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3940 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3942 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3946 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
3947 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3950 static const char *const arm_conditional
[] =
3951 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3952 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3954 static const char *const arm_fp_const
[] =
3955 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3957 static const char *const arm_shift
[] =
3958 {"lsl", "lsr", "asr", "ror"};
3963 const char *description
;
3964 const char *reg_names
[16];
3968 static const arm_regname regnames
[] =
3970 { "reg-names-raw", N_("Select raw register names"),
3971 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3972 { "reg-names-gcc", N_("Select register names used by GCC"),
3973 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3974 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
3975 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3976 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL
} },
3977 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL
} },
3978 { "reg-names-apcs", N_("Select register names used in the APCS"),
3979 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3980 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
3981 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3982 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3983 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
3986 static const char *const iwmmxt_wwnames
[] =
3987 {"b", "h", "w", "d"};
3989 static const char *const iwmmxt_wwssnames
[] =
3990 {"b", "bus", "bc", "bss",
3991 "h", "hus", "hc", "hss",
3992 "w", "wus", "wc", "wss",
3993 "d", "dus", "dc", "dss"
3996 static const char *const iwmmxt_regnames
[] =
3997 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3998 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4001 static const char *const iwmmxt_cregnames
[] =
4002 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4003 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4006 static const char *const vec_condnames
[] =
4007 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4010 static const char *const mve_predicatenames
[] =
4011 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4012 "eee", "ee", "eet", "e", "ett", "et", "ete"
4015 /* Names for 2-bit size field for mve vector isntructions. */
4016 static const char *const mve_vec_sizename
[] =
4017 { "8", "16", "32", "64"};
4019 /* Indicates whether we are processing a then predicate,
4020 else predicate or none at all. */
4028 /* Information used to process a vpt block and subsequent instructions. */
4031 /* Are we in a vpt block. */
4032 bfd_boolean in_vpt_block
;
4034 /* Next predicate state if in vpt block. */
4035 enum vpt_pred_state next_pred_state
;
4037 /* Mask from vpt/vpst instruction. */
4038 long predicate_mask
;
4040 /* Instruction number in vpt block. */
4041 long current_insn_num
;
4043 /* Number of instructions in vpt block.. */
4047 static struct vpt_block vpt_block_state
=
4056 /* Default to GCC register name set. */
4057 static unsigned int regname_selected
= 1;
4059 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
4060 #define arm_regnames regnames[regname_selected].reg_names
4062 static bfd_boolean force_thumb
= FALSE
;
4064 /* Current IT instruction state. This contains the same state as the IT
4065 bits in the CPSR. */
4066 static unsigned int ifthen_state
;
4067 /* IT state for the next instruction. */
4068 static unsigned int ifthen_next_state
;
4069 /* The address of the insn for which the IT state is valid. */
4070 static bfd_vma ifthen_address
;
4071 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
4072 /* Indicates that the current Conditional state is unconditional or outside
4074 #define COND_UNCOND 16
4078 /* Extract the predicate mask for a VPT or VPST instruction.
4079 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
4082 mve_extract_pred_mask (long given
)
4084 return ((given
& 0x00400000) >> 19) | ((given
& 0xe000) >> 13);
4087 /* Return the number of instructions in a MVE predicate block. */
4089 num_instructions_vpt_block (long given
)
4091 long mask
= mve_extract_pred_mask (given
);
4098 if ((mask
& 7) == 4)
4101 if ((mask
& 3) == 2)
4104 if ((mask
& 1) == 1)
4111 mark_outside_vpt_block (void)
4113 vpt_block_state
.in_vpt_block
= FALSE
;
4114 vpt_block_state
.next_pred_state
= PRED_NONE
;
4115 vpt_block_state
.predicate_mask
= 0;
4116 vpt_block_state
.current_insn_num
= 0;
4117 vpt_block_state
.num_pred_insn
= 0;
4121 mark_inside_vpt_block (long given
)
4123 vpt_block_state
.in_vpt_block
= TRUE
;
4124 vpt_block_state
.next_pred_state
= PRED_THEN
;
4125 vpt_block_state
.predicate_mask
= mve_extract_pred_mask (given
);
4126 vpt_block_state
.current_insn_num
= 0;
4127 vpt_block_state
.num_pred_insn
= num_instructions_vpt_block (given
);
4128 assert (vpt_block_state
.num_pred_insn
>= 1);
4131 static enum vpt_pred_state
4132 invert_next_predicate_state (enum vpt_pred_state astate
)
4134 if (astate
== PRED_THEN
)
4136 else if (astate
== PRED_ELSE
)
4142 static enum vpt_pred_state
4143 update_next_predicate_state (void)
4145 long pred_mask
= vpt_block_state
.predicate_mask
;
4146 long mask_for_insn
= 0;
4148 switch (vpt_block_state
.current_insn_num
)
4166 if (pred_mask
& mask_for_insn
)
4167 return invert_next_predicate_state (vpt_block_state
.next_pred_state
);
4169 return vpt_block_state
.next_pred_state
;
4173 update_vpt_block_state (void)
4175 vpt_block_state
.current_insn_num
++;
4176 if (vpt_block_state
.current_insn_num
== vpt_block_state
.num_pred_insn
)
4178 /* No more instructions to process in vpt block. */
4179 mark_outside_vpt_block ();
4183 vpt_block_state
.next_pred_state
= update_next_predicate_state ();
4186 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
4187 Returns pointer to following character of the format string and
4188 fills in *VALUEP and *WIDTHP with the extracted value and number of
4189 bits extracted. WIDTHP can be NULL. */
4192 arm_decode_bitfield (const char *ptr
,
4194 unsigned long *valuep
,
4197 unsigned long value
= 0;
4205 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
4206 start
= start
* 10 + *ptr
- '0';
4208 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
4209 end
= end
* 10 + *ptr
- '0';
4215 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
4218 while (*ptr
++ == ',');
4226 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
4227 bfd_boolean print_shift
)
4229 func (stream
, "%s", arm_regnames
[given
& 0xf]);
4231 if ((given
& 0xff0) != 0)
4233 if ((given
& 0x10) == 0)
4235 int amount
= (given
& 0xf80) >> 7;
4236 int shift
= (given
& 0x60) >> 5;
4242 func (stream
, ", rrx");
4250 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
4252 func (stream
, ", #%d", amount
);
4254 else if ((given
& 0x80) == 0x80)
4255 func (stream
, "\t; <illegal shifter operand>");
4256 else if (print_shift
)
4257 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
4258 arm_regnames
[(given
& 0xf00) >> 8]);
4260 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
4264 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
4267 is_mve_okay_in_it (enum mve_instructions matched_insn
)
4269 switch (matched_insn
)
4271 case MVE_VMOV_GP_TO_VEC_LANE
:
4272 case MVE_VMOV2_VEC_LANE_TO_GP
:
4273 case MVE_VMOV2_GP_TO_VEC_LANE
:
4274 case MVE_VMOV_VEC_LANE_TO_GP
:
4282 is_mve_architecture (struct disassemble_info
*info
)
4284 struct arm_private_data
*private_data
= info
->private_data
;
4285 arm_feature_set allowed_arches
= private_data
->features
;
4287 arm_feature_set arm_ext_v8_1m_main
4288 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
4290 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
4291 && !ARM_CPU_IS_ANY (allowed_arches
))
4298 is_vpt_instruction (long given
)
4301 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
4302 if ((given
& 0x0040e000) == 0)
4305 /* VPT floating point T1 variant. */
4306 if (((given
& 0xefb10f50) == 0xee310f00 && ((given
& 0x1001) != 0x1))
4307 /* VPT floating point T2 variant. */
4308 || ((given
& 0xefb10f50) == 0xee310f40)
4309 /* VPT vector T1 variant. */
4310 || ((given
& 0xff811f51) == 0xfe010f00)
4311 /* VPT vector T2 variant. */
4312 || ((given
& 0xff811f51) == 0xfe010f01
4313 && ((given
& 0x300000) != 0x300000))
4314 /* VPT vector T3 variant. */
4315 || ((given
& 0xff811f50) == 0xfe011f00)
4316 /* VPT vector T4 variant. */
4317 || ((given
& 0xff811f70) == 0xfe010f40)
4318 /* VPT vector T5 variant. */
4319 || ((given
& 0xff811f70) == 0xfe010f60)
4320 /* VPT vector T6 variant. */
4321 || ((given
& 0xff811f50) == 0xfe011f40)
4322 /* VPST vector T variant. */
4323 || ((given
& 0xffbf1fff) == 0xfe310f4d))
4329 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
4330 and ending bitfield = END. END must be greater than START. */
4332 static unsigned long
4333 arm_decode_field (unsigned long given
, unsigned int start
, unsigned int end
)
4335 int bits
= end
- start
;
4340 return ((given
>> start
) & ((2ul << bits
) - 1));
4343 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
4344 START:END and START2:END2. END/END2 must be greater than
4347 static unsigned long
4348 arm_decode_field_multiple (unsigned long given
, unsigned int start
,
4349 unsigned int end
, unsigned int start2
,
4352 int bits
= end
- start
;
4353 int bits2
= end2
- start2
;
4354 unsigned long value
= 0;
4360 value
= arm_decode_field (given
, start
, end
);
4363 value
|= ((given
>> start2
) & ((2ul << bits2
) - 1)) << width
;
4367 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
4368 This helps us decode instructions that change mnemonic depending on specific
4369 operand values/encodings. */
4372 is_mve_encoding_conflict (unsigned long given
,
4373 enum mve_instructions matched_insn
)
4375 switch (matched_insn
)
4378 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4384 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4386 if ((arm_decode_field (given
, 12, 12) == 0)
4387 && (arm_decode_field (given
, 0, 0) == 1))
4392 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4394 if (arm_decode_field (given
, 0, 3) == 0xd)
4398 case MVE_VPT_VEC_T1
:
4399 case MVE_VPT_VEC_T2
:
4400 case MVE_VPT_VEC_T3
:
4401 case MVE_VPT_VEC_T4
:
4402 case MVE_VPT_VEC_T5
:
4403 case MVE_VPT_VEC_T6
:
4404 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4406 if (arm_decode_field (given
, 20, 21) == 3)
4410 case MVE_VCMP_FP_T1
:
4411 if ((arm_decode_field (given
, 12, 12) == 0)
4412 && (arm_decode_field (given
, 0, 0) == 1))
4417 case MVE_VCMP_FP_T2
:
4418 if (arm_decode_field (given
, 0, 3) == 0xd)
4425 case MVE_VCMP_VEC_T1
:
4426 case MVE_VCMP_VEC_T2
:
4427 case MVE_VCMP_VEC_T3
:
4428 case MVE_VCMP_VEC_T4
:
4429 case MVE_VCMP_VEC_T5
:
4430 case MVE_VCMP_VEC_T6
:
4431 if (arm_decode_field (given
, 20, 21) == 3)
4440 if (arm_decode_field (given
, 7, 8) == 3)
4447 if ((arm_decode_field (given
, 24, 24) == 0)
4448 && (arm_decode_field (given
, 21, 21) == 0))
4452 else if ((arm_decode_field (given
, 7, 8) == 3))
4460 if ((arm_decode_field (given
, 24, 24) == 0)
4461 && (arm_decode_field (given
, 21, 21) == 0))
4468 case MVE_VCVT_FP_FIX_VEC
:
4469 return (arm_decode_field (given
, 16, 21) & 0x38) == 0;
4474 unsigned long cmode
= arm_decode_field (given
, 8, 11);
4476 if ((cmode
& 1) == 0)
4478 else if ((cmode
& 0xc) == 0xc)
4486 unsigned long cmode
= arm_decode_field (given
, 8, 11);
4488 if ((cmode
& 9) == 1)
4490 else if ((cmode
& 5) == 1)
4492 else if ((cmode
& 0xe) == 0xe)
4498 case MVE_VMOV_IMM_TO_VEC
:
4499 if ((arm_decode_field (given
, 5, 5) == 1)
4500 && (arm_decode_field (given
, 8, 11) != 0xe))
4512 print_mve_vld_str_addr (struct disassemble_info
*info
,
4513 unsigned long given
,
4514 enum mve_instructions matched_insn
)
4516 void *stream
= info
->stream
;
4517 fprintf_ftype func
= info
->fprintf_func
;
4519 unsigned long p
, w
, gpr
, imm
, add
, mod_imm
;
4521 imm
= arm_decode_field (given
, 0, 6);
4524 switch (matched_insn
)
4528 gpr
= arm_decode_field (given
, 16, 18);
4533 gpr
= arm_decode_field (given
, 16, 18);
4539 gpr
= arm_decode_field (given
, 16, 19);
4545 gpr
= arm_decode_field (given
, 16, 19);
4551 gpr
= arm_decode_field (given
, 16, 19);
4558 p
= arm_decode_field (given
, 24, 24);
4559 w
= arm_decode_field (given
, 21, 21);
4561 add
= arm_decode_field (given
, 23, 23);
4565 /* Don't print anything for '+' as it is implied. */
4575 func (stream
, "[%s, #%s%lu]", arm_regnames
[gpr
], add_sub
, mod_imm
);
4576 /* Pre-indexed mode. */
4578 func (stream
, "[%s, #%s%lu]!", arm_regnames
[gpr
], add_sub
, mod_imm
);
4580 else if ((p
== 0) && (w
== 1))
4581 /* Post-index mode. */
4582 func (stream
, "[%s], #%s%lu", arm_regnames
[gpr
], add_sub
, mod_imm
);
4585 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
4586 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
4587 this encoding is undefined. */
4590 is_mve_undefined (unsigned long given
, enum mve_instructions matched_insn
,
4591 enum mve_undefined
*undefined_code
)
4593 *undefined_code
= UNDEF_NONE
;
4595 switch (matched_insn
)
4598 if (arm_decode_field_multiple (given
, 5, 5, 22, 22) == 3)
4600 *undefined_code
= UNDEF_SIZE_3
;
4609 if (arm_decode_field (given
, 20, 21) == 3)
4611 *undefined_code
= UNDEF_SIZE_3
;
4618 if (arm_decode_field (given
, 7, 8) == 3)
4620 *undefined_code
= UNDEF_SIZE_3
;
4627 if (arm_decode_field (given
, 7, 8) <= 1)
4629 *undefined_code
= UNDEF_SIZE_LE_1
;
4636 if ((arm_decode_field (given
, 7, 8) == 0))
4638 *undefined_code
= UNDEF_SIZE_0
;
4645 if ((arm_decode_field (given
, 7, 8) <= 1))
4647 *undefined_code
= UNDEF_SIZE_LE_1
;
4653 case MVE_VLDRB_GATHER_T1
:
4654 if (arm_decode_field (given
, 7, 8) == 3)
4656 *undefined_code
= UNDEF_SIZE_3
;
4659 else if ((arm_decode_field (given
, 28, 28) == 0)
4660 && (arm_decode_field (given
, 7, 8) == 0))
4662 *undefined_code
= UNDEF_NOT_UNS_SIZE_0
;
4668 case MVE_VLDRH_GATHER_T2
:
4669 if (arm_decode_field (given
, 7, 8) == 3)
4671 *undefined_code
= UNDEF_SIZE_3
;
4674 else if ((arm_decode_field (given
, 28, 28) == 0)
4675 && (arm_decode_field (given
, 7, 8) == 1))
4677 *undefined_code
= UNDEF_NOT_UNS_SIZE_1
;
4680 else if (arm_decode_field (given
, 7, 8) == 0)
4682 *undefined_code
= UNDEF_SIZE_0
;
4688 case MVE_VLDRW_GATHER_T3
:
4689 if (arm_decode_field (given
, 7, 8) != 2)
4691 *undefined_code
= UNDEF_SIZE_NOT_2
;
4694 else if (arm_decode_field (given
, 28, 28) == 0)
4696 *undefined_code
= UNDEF_NOT_UNSIGNED
;
4702 case MVE_VLDRD_GATHER_T4
:
4703 if (arm_decode_field (given
, 7, 8) != 3)
4705 *undefined_code
= UNDEF_SIZE_NOT_3
;
4708 else if (arm_decode_field (given
, 28, 28) == 0)
4710 *undefined_code
= UNDEF_NOT_UNSIGNED
;
4716 case MVE_VSTRB_SCATTER_T1
:
4717 if (arm_decode_field (given
, 7, 8) == 3)
4719 *undefined_code
= UNDEF_SIZE_3
;
4725 case MVE_VSTRH_SCATTER_T2
:
4727 unsigned long size
= arm_decode_field (given
, 7, 8);
4730 *undefined_code
= UNDEF_SIZE_3
;
4735 *undefined_code
= UNDEF_SIZE_0
;
4742 case MVE_VSTRW_SCATTER_T3
:
4743 if (arm_decode_field (given
, 7, 8) != 2)
4745 *undefined_code
= UNDEF_SIZE_NOT_2
;
4751 case MVE_VSTRD_SCATTER_T4
:
4752 if (arm_decode_field (given
, 7, 8) != 3)
4754 *undefined_code
= UNDEF_SIZE_NOT_3
;
4760 case MVE_VCVT_FP_FIX_VEC
:
4762 unsigned long imm6
= arm_decode_field (given
, 16, 21);
4763 if ((imm6
& 0x20) == 0)
4765 *undefined_code
= UNDEF_VCVT_IMM6
;
4769 if ((arm_decode_field (given
, 9, 9) == 0)
4770 && ((imm6
& 0x30) == 0x20))
4772 *undefined_code
= UNDEF_VCVT_FSI_IMM6
;
4779 case MVE_VCVT_BETWEEN_FP_INT
:
4780 case MVE_VCVT_FROM_FP_TO_INT
:
4782 unsigned long size
= arm_decode_field (given
, 18, 19);
4785 *undefined_code
= UNDEF_SIZE_0
;
4790 *undefined_code
= UNDEF_SIZE_3
;
4797 case MVE_VMOV_VEC_LANE_TO_GP
:
4799 unsigned long op1
= arm_decode_field (given
, 21, 22);
4800 unsigned long op2
= arm_decode_field (given
, 5, 6);
4801 unsigned long u
= arm_decode_field (given
, 23, 23);
4803 if ((op2
== 0) && (u
== 1))
4805 if ((op1
== 0) || (op1
== 1))
4807 *undefined_code
= UNDEF_BAD_U_OP1_OP2
;
4815 if ((op1
== 0) || (op1
== 1))
4817 *undefined_code
= UNDEF_BAD_OP1_OP2
;
4827 case MVE_VMOV_GP_TO_VEC_LANE
:
4828 if (arm_decode_field (given
, 5, 6) == 2)
4830 unsigned long op1
= arm_decode_field (given
, 21, 22);
4831 if ((op1
== 0) || (op1
== 1))
4833 *undefined_code
= UNDEF_BAD_OP1_OP2
;
4842 case MVE_VMOV_IMM_TO_VEC
:
4843 if (arm_decode_field (given
, 5, 5) == 0)
4845 unsigned long cmode
= arm_decode_field (given
, 8, 11);
4847 if (((cmode
& 9) == 1) || ((cmode
& 5) == 1))
4849 *undefined_code
= UNDEF_OP_0_BAD_CMODE
;
4863 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
4864 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
4865 why this encoding is unpredictable. */
4868 is_mve_unpredictable (unsigned long given
, enum mve_instructions matched_insn
,
4869 enum mve_unpredictable
*unpredictable_code
)
4871 *unpredictable_code
= UNPRED_NONE
;
4873 switch (matched_insn
)
4875 case MVE_VCMP_FP_T2
:
4877 if ((arm_decode_field (given
, 12, 12) == 0)
4878 && (arm_decode_field (given
, 5, 5) == 1))
4880 *unpredictable_code
= UNPRED_FCA_0_FCB_1
;
4886 case MVE_VPT_VEC_T4
:
4887 case MVE_VPT_VEC_T5
:
4888 case MVE_VPT_VEC_T6
:
4889 case MVE_VCMP_VEC_T4
:
4890 case MVE_VCMP_VEC_T5
:
4891 case MVE_VCMP_VEC_T6
:
4892 if (arm_decode_field (given
, 0, 3) == 0xd)
4894 *unpredictable_code
= UNPRED_R13
;
4902 unsigned long gpr
= arm_decode_field (given
, 12, 15);
4905 *unpredictable_code
= UNPRED_R13
;
4908 else if (gpr
== 0xf)
4910 *unpredictable_code
= UNPRED_R15
;
4917 case MVE_VFMA_FP_SCALAR
:
4918 case MVE_VFMAS_FP_SCALAR
:
4922 unsigned long gpr
= arm_decode_field (given
, 0, 3);
4925 *unpredictable_code
= UNPRED_R13
;
4928 else if (gpr
== 0xf)
4930 *unpredictable_code
= UNPRED_R15
;
4940 unsigned long rn
= arm_decode_field (given
, 16, 19);
4942 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
4944 *unpredictable_code
= UNPRED_R13_AND_WB
;
4950 *unpredictable_code
= UNPRED_R15
;
4954 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 6)
4956 *unpredictable_code
= UNPRED_Q_GT_6
;
4966 unsigned long rn
= arm_decode_field (given
, 16, 19);
4968 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
4970 *unpredictable_code
= UNPRED_R13_AND_WB
;
4976 *unpredictable_code
= UNPRED_R15
;
4980 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 4)
4982 *unpredictable_code
= UNPRED_Q_GT_4
;
4996 unsigned long rn
= arm_decode_field (given
, 16, 19);
4998 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
5000 *unpredictable_code
= UNPRED_R13_AND_WB
;
5005 *unpredictable_code
= UNPRED_R15
;
5012 case MVE_VLDRB_GATHER_T1
:
5013 if (arm_decode_field (given
, 0, 0) == 1)
5015 *unpredictable_code
= UNPRED_OS
;
5020 /* To handle common code with T2-T4 variants. */
5021 case MVE_VLDRH_GATHER_T2
:
5022 case MVE_VLDRW_GATHER_T3
:
5023 case MVE_VLDRD_GATHER_T4
:
5025 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5026 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5030 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
5034 if (arm_decode_field (given
, 16, 19) == 0xf)
5036 *unpredictable_code
= UNPRED_R15
;
5043 case MVE_VLDRW_GATHER_T5
:
5044 case MVE_VLDRD_GATHER_T6
:
5046 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5047 unsigned long qm
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5051 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
5058 case MVE_VSTRB_SCATTER_T1
:
5059 if (arm_decode_field (given
, 16, 19) == 0xf)
5061 *unpredictable_code
= UNPRED_R15
;
5064 else if (arm_decode_field (given
, 0, 0) == 1)
5066 *unpredictable_code
= UNPRED_OS
;
5072 case MVE_VSTRH_SCATTER_T2
:
5073 case MVE_VSTRW_SCATTER_T3
:
5074 case MVE_VSTRD_SCATTER_T4
:
5075 if (arm_decode_field (given
, 16, 19) == 0xf)
5077 *unpredictable_code
= UNPRED_R15
;
5083 case MVE_VMOV2_VEC_LANE_TO_GP
:
5084 case MVE_VMOV2_GP_TO_VEC_LANE
:
5085 case MVE_VCVT_BETWEEN_FP_INT
:
5086 case MVE_VCVT_FROM_FP_TO_INT
:
5088 unsigned long rt
= arm_decode_field (given
, 0, 3);
5089 unsigned long rt2
= arm_decode_field (given
, 16, 19);
5091 if ((rt
== 0xd) || (rt2
== 0xd))
5093 *unpredictable_code
= UNPRED_R13
;
5096 else if ((rt
== 0xf) || (rt2
== 0xf))
5098 *unpredictable_code
= UNPRED_R15
;
5103 *unpredictable_code
= UNPRED_GP_REGS_EQUAL
;
5110 case MVE_VMOV_HFP_TO_GP
:
5111 case MVE_VMOV_GP_TO_VEC_LANE
:
5112 case MVE_VMOV_VEC_LANE_TO_GP
:
5114 unsigned long rda
= arm_decode_field (given
, 12, 15);
5117 *unpredictable_code
= UNPRED_R13
;
5120 else if (rda
== 0xf)
5122 *unpredictable_code
= UNPRED_R15
;
5135 print_mve_vmov_index (struct disassemble_info
*info
, unsigned long given
)
5137 unsigned long op1
= arm_decode_field (given
, 21, 22);
5138 unsigned long op2
= arm_decode_field (given
, 5, 6);
5139 unsigned long h
= arm_decode_field (given
, 16, 16);
5140 unsigned long index
, esize
, targetBeat
, idx
;
5141 void *stream
= info
->stream
;
5142 fprintf_ftype func
= info
->fprintf_func
;
5144 if ((op1
& 0x2) == 0x2)
5149 else if (((op1
& 0x2) == 0x0) && ((op2
& 0x1) == 0x1))
5154 else if (((op1
& 0x2) == 0) && ((op2
& 0x3) == 0))
5161 func (stream
, "<undefined index>");
5165 targetBeat
= (op1
& 0x1) | (h
<< 1);
5166 idx
= index
+ targetBeat
* (32/esize
);
5168 func (stream
, "%lu", idx
);
5171 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
5172 in length and integer of floating-point type. */
5174 print_simd_imm8 (struct disassemble_info
*info
, unsigned long given
,
5175 unsigned int ibit_loc
, const struct mopcode32
*insn
)
5178 int cmode
= (given
>> 8) & 0xf;
5179 int op
= (given
>> 5) & 0x1;
5180 unsigned long value
= 0, hival
= 0;
5184 void *stream
= info
->stream
;
5185 fprintf_ftype func
= info
->fprintf_func
;
5187 /* On Neon the 'i' bit is at bit 24, on mve it is
5189 bits
|= ((given
>> ibit_loc
) & 1) << 7;
5190 bits
|= ((given
>> 16) & 7) << 4;
5191 bits
|= ((given
>> 0) & 15) << 0;
5195 shift
= (cmode
>> 1) & 3;
5196 value
= (unsigned long) bits
<< (8 * shift
);
5199 else if (cmode
< 12)
5201 shift
= (cmode
>> 1) & 1;
5202 value
= (unsigned long) bits
<< (8 * shift
);
5205 else if (cmode
< 14)
5207 shift
= (cmode
& 1) + 1;
5208 value
= (unsigned long) bits
<< (8 * shift
);
5209 value
|= (1ul << (8 * shift
)) - 1;
5212 else if (cmode
== 14)
5216 /* Bit replication into bytes. */
5222 for (ix
= 7; ix
>= 0; ix
--)
5224 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
5226 value
= (value
<< 8) | mask
;
5228 hival
= (hival
<< 8) | mask
;
5234 /* Byte replication. */
5235 value
= (unsigned long) bits
;
5241 /* Floating point encoding. */
5244 value
= (unsigned long) (bits
& 0x7f) << 19;
5245 value
|= (unsigned long) (bits
& 0x80) << 24;
5246 tmp
= bits
& 0x40 ? 0x3c : 0x40;
5247 value
|= (unsigned long) tmp
<< 24;
5253 func (stream
, "<illegal constant %.8x:%x:%x>",
5259 // printU determines whether the immediate value should be printed as
5261 unsigned printU
= 0;
5262 switch (insn
->mve_op
)
5266 // We want this for instructions that don't have a 'signed' type
5270 case MVE_VMOV_IMM_TO_VEC
:
5277 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
5284 : "#%ld\t; 0x%.4lx", value
, value
);
5290 unsigned char valbytes
[4];
5293 /* Do this a byte at a time so we don't have to
5294 worry about the host's endianness. */
5295 valbytes
[0] = value
& 0xff;
5296 valbytes
[1] = (value
>> 8) & 0xff;
5297 valbytes
[2] = (value
>> 16) & 0xff;
5298 valbytes
[3] = (value
>> 24) & 0xff;
5300 floatformat_to_double
5301 (& floatformat_ieee_single_little
, valbytes
,
5304 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
5311 : "#%ld\t; 0x%.8lx",
5312 (long) (((value
& 0x80000000L
) != 0)
5314 ? value
| ~0xffffffffL
: value
),
5319 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
5329 print_mve_undefined (struct disassemble_info
*info
,
5330 enum mve_undefined undefined_code
)
5332 void *stream
= info
->stream
;
5333 fprintf_ftype func
= info
->fprintf_func
;
5335 func (stream
, "\t\tundefined instruction: ");
5337 switch (undefined_code
)
5340 func (stream
, "size equals zero");
5344 func (stream
, "size equals two");
5348 func (stream
, "size equals three");
5351 case UNDEF_SIZE_LE_1
:
5352 func (stream
, "size <= 1");
5355 case UNDEF_SIZE_NOT_2
:
5356 func (stream
, "size not equal to 2");
5359 case UNDEF_SIZE_NOT_3
:
5360 func (stream
, "size not equal to 3");
5363 case UNDEF_NOT_UNS_SIZE_0
:
5364 func (stream
, "not unsigned and size = zero");
5367 case UNDEF_NOT_UNS_SIZE_1
:
5368 func (stream
, "not unsigned and size = one");
5371 case UNDEF_NOT_UNSIGNED
:
5372 func (stream
, "not unsigned");
5375 case UNDEF_VCVT_IMM6
:
5376 func (stream
, "invalid imm6");
5379 case UNDEF_VCVT_FSI_IMM6
:
5380 func (stream
, "fsi = 0 and invalid imm6");
5383 case UNDEF_BAD_OP1_OP2
:
5384 func (stream
, "bad size with op2 = 2 and op1 = 0 or 1");
5387 case UNDEF_BAD_U_OP1_OP2
:
5388 func (stream
, "unsigned with op2 = 0 and op1 = 0 or 1");
5391 case UNDEF_OP_0_BAD_CMODE
:
5392 func (stream
, "op field equal 0 and bad cmode");
5402 print_mve_unpredictable (struct disassemble_info
*info
,
5403 enum mve_unpredictable unpredict_code
)
5405 void *stream
= info
->stream
;
5406 fprintf_ftype func
= info
->fprintf_func
;
5408 func (stream
, "%s: ", UNPREDICTABLE_INSTRUCTION
);
5410 switch (unpredict_code
)
5412 case UNPRED_IT_BLOCK
:
5413 func (stream
, "mve instruction in it block");
5416 case UNPRED_FCA_0_FCB_1
:
5417 func (stream
, "condition bits, fca = 0 and fcb = 1");
5421 func (stream
, "use of r13 (sp)");
5425 func (stream
, "use of r15 (pc)");
5429 func (stream
, "start register block > r4");
5433 func (stream
, "start register block > r6");
5436 case UNPRED_R13_AND_WB
:
5437 func (stream
, "use of r13 and write back");
5440 case UNPRED_Q_REGS_EQUAL
:
5442 "same vector register used for destination and other operand");
5446 func (stream
, "use of offset scaled");
5449 case UNPRED_GP_REGS_EQUAL
:
5450 func (stream
, "same general-purpose register used for both operands");
5453 case UNPRED_Q_REGS_EQ_AND_SIZE_1
:
5454 func (stream
, "use of identical q registers and size = 1");
5457 case UNPRED_Q_REGS_EQ_AND_SIZE_2
:
5458 func (stream
, "use of identical q registers and size = 1");
5466 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
5469 print_mve_register_blocks (struct disassemble_info
*info
,
5470 unsigned long given
,
5471 enum mve_instructions matched_insn
)
5473 void *stream
= info
->stream
;
5474 fprintf_ftype func
= info
->fprintf_func
;
5476 unsigned long q_reg_start
= arm_decode_field_multiple (given
,
5479 switch (matched_insn
)
5483 if (q_reg_start
<= 6)
5484 func (stream
, "{q%ld, q%ld}", q_reg_start
, q_reg_start
+ 1);
5486 func (stream
, "<illegal reg q%ld>", q_reg_start
);
5491 if (q_reg_start
<= 4)
5492 func (stream
, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start
,
5493 q_reg_start
+ 1, q_reg_start
+ 2,
5496 func (stream
, "<illegal reg q%ld>", q_reg_start
);
5505 print_mve_rounding_mode (struct disassemble_info
*info
,
5506 unsigned long given
,
5507 enum mve_instructions matched_insn
)
5509 void *stream
= info
->stream
;
5510 fprintf_ftype func
= info
->fprintf_func
;
5512 switch (matched_insn
)
5514 case MVE_VCVT_FROM_FP_TO_INT
:
5516 switch (arm_decode_field (given
, 8, 9))
5542 switch (arm_decode_field (given
, 7, 9))
5581 print_mve_vcvt_size (struct disassemble_info
*info
,
5582 unsigned long given
,
5583 enum mve_instructions matched_insn
)
5585 unsigned long mode
= 0;
5586 void *stream
= info
->stream
;
5587 fprintf_ftype func
= info
->fprintf_func
;
5589 switch (matched_insn
)
5591 case MVE_VCVT_FP_FIX_VEC
:
5593 mode
= (((given
& 0x200) >> 7)
5594 | ((given
& 0x10000000) >> 27)
5595 | ((given
& 0x100) >> 8));
5600 func (stream
, "f16.s16");
5604 func (stream
, "s16.f16");
5608 func (stream
, "f16.u16");
5612 func (stream
, "u16.f16");
5616 func (stream
, "f32.s32");
5620 func (stream
, "s32.f32");
5624 func (stream
, "f32.u32");
5628 func (stream
, "u32.f32");
5636 case MVE_VCVT_BETWEEN_FP_INT
:
5638 unsigned long size
= arm_decode_field (given
, 18, 19);
5639 unsigned long op
= arm_decode_field (given
, 7, 8);
5646 func (stream
, "f16.s16");
5650 func (stream
, "f16.u16");
5654 func (stream
, "s16.f16");
5658 func (stream
, "u16.f16");
5670 func (stream
, "f32.s32");
5674 func (stream
, "f32.u32");
5678 func (stream
, "s32.f32");
5682 func (stream
, "u32.f32");
5689 case MVE_VCVT_FP_HALF_FP
:
5691 unsigned long op
= arm_decode_field (given
, 28, 28);
5693 func (stream
, "f16.f32");
5695 func (stream
, "f32.f16");
5699 case MVE_VCVT_FROM_FP_TO_INT
:
5701 unsigned long size
= arm_decode_field_multiple (given
, 7, 7, 18, 19);
5706 func (stream
, "s16.f16");
5710 func (stream
, "u16.f16");
5714 func (stream
, "s32.f32");
5718 func (stream
, "u32.f32");
5733 print_instruction_predicate (struct disassemble_info
*info
)
5735 void *stream
= info
->stream
;
5736 fprintf_ftype func
= info
->fprintf_func
;
5738 if (vpt_block_state
.next_pred_state
== PRED_THEN
)
5740 else if (vpt_block_state
.next_pred_state
== PRED_ELSE
)
5745 print_mve_size (struct disassemble_info
*info
,
5747 enum mve_instructions matched_insn
)
5749 void *stream
= info
->stream
;
5750 fprintf_ftype func
= info
->fprintf_func
;
5752 switch (matched_insn
)
5754 case MVE_VCMP_VEC_T1
:
5755 case MVE_VCMP_VEC_T2
:
5756 case MVE_VCMP_VEC_T3
:
5757 case MVE_VCMP_VEC_T4
:
5758 case MVE_VCMP_VEC_T5
:
5759 case MVE_VCMP_VEC_T6
:
5766 case MVE_VLDRB_GATHER_T1
:
5767 case MVE_VLDRH_GATHER_T2
:
5768 case MVE_VLDRW_GATHER_T3
:
5769 case MVE_VLDRD_GATHER_T4
:
5772 case MVE_VPT_VEC_T1
:
5773 case MVE_VPT_VEC_T2
:
5774 case MVE_VPT_VEC_T3
:
5775 case MVE_VPT_VEC_T4
:
5776 case MVE_VPT_VEC_T5
:
5777 case MVE_VPT_VEC_T6
:
5782 case MVE_VSTRB_SCATTER_T1
:
5783 case MVE_VSTRH_SCATTER_T2
:
5784 case MVE_VSTRW_SCATTER_T3
:
5788 func (stream
, "%s", mve_vec_sizename
[size
]);
5790 func (stream
, "<undef size>");
5793 case MVE_VCMP_FP_T1
:
5794 case MVE_VCMP_FP_T2
:
5795 case MVE_VFMA_FP_SCALAR
:
5798 case MVE_VFMAS_FP_SCALAR
:
5802 func (stream
, "32");
5804 func (stream
, "16");
5811 func (stream
, "32");
5814 func (stream
, "16");
5824 case MVE_VMOV_GP_TO_VEC_LANE
:
5825 case MVE_VMOV_VEC_LANE_TO_GP
:
5829 func (stream
, "32");
5834 func (stream
, "16");
5837 case 8: case 9: case 10: case 11:
5838 case 12: case 13: case 14: case 15:
5847 case MVE_VMOV_IMM_TO_VEC
:
5850 case 0: case 4: case 8:
5851 case 12: case 24: case 26:
5852 func (stream
, "i32");
5855 func (stream
, "i16");
5858 func (stream
, "i8");
5861 func (stream
, "i64");
5864 func (stream
, "f32");
5874 case 0: case 2: case 4:
5875 case 6: case 12: case 13:
5876 func (stream
, "32");
5880 func (stream
, "16");
5894 func (stream
, "32");
5898 func (stream
, "16");
5912 print_vec_condition (struct disassemble_info
*info
, long given
,
5913 enum mve_instructions matched_insn
)
5915 void *stream
= info
->stream
;
5916 fprintf_ftype func
= info
->fprintf_func
;
5919 switch (matched_insn
)
5922 case MVE_VCMP_FP_T1
:
5923 vec_cond
= (((given
& 0x1000) >> 10)
5924 | ((given
& 1) << 1)
5925 | ((given
& 0x0080) >> 7));
5926 func (stream
, "%s",vec_condnames
[vec_cond
]);
5930 case MVE_VCMP_FP_T2
:
5931 vec_cond
= (((given
& 0x1000) >> 10)
5932 | ((given
& 0x0020) >> 4)
5933 | ((given
& 0x0080) >> 7));
5934 func (stream
, "%s",vec_condnames
[vec_cond
]);
5937 case MVE_VPT_VEC_T1
:
5938 case MVE_VCMP_VEC_T1
:
5939 vec_cond
= (given
& 0x0080) >> 7;
5940 func (stream
, "%s",vec_condnames
[vec_cond
]);
5943 case MVE_VPT_VEC_T2
:
5944 case MVE_VCMP_VEC_T2
:
5945 vec_cond
= 2 | ((given
& 0x0080) >> 7);
5946 func (stream
, "%s",vec_condnames
[vec_cond
]);
5949 case MVE_VPT_VEC_T3
:
5950 case MVE_VCMP_VEC_T3
:
5951 vec_cond
= 4 | ((given
& 1) << 1) | ((given
& 0x0080) >> 7);
5952 func (stream
, "%s",vec_condnames
[vec_cond
]);
5955 case MVE_VPT_VEC_T4
:
5956 case MVE_VCMP_VEC_T4
:
5957 vec_cond
= (given
& 0x0080) >> 7;
5958 func (stream
, "%s",vec_condnames
[vec_cond
]);
5961 case MVE_VPT_VEC_T5
:
5962 case MVE_VCMP_VEC_T5
:
5963 vec_cond
= 2 | ((given
& 0x0080) >> 7);
5964 func (stream
, "%s",vec_condnames
[vec_cond
]);
5967 case MVE_VPT_VEC_T6
:
5968 case MVE_VCMP_VEC_T6
:
5969 vec_cond
= 4 | ((given
& 0x0020) >> 4) | ((given
& 0x0080) >> 7);
5970 func (stream
, "%s",vec_condnames
[vec_cond
]);
5985 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
5986 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
5987 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
5988 #define PRE_BIT_SET (given & (1 << P_BIT))
5991 /* Print one coprocessor instruction on INFO->STREAM.
5992 Return TRUE if the instuction matched, FALSE if this is not a
5993 recognised coprocessor instruction. */
5996 print_insn_coprocessor (bfd_vma pc
,
5997 struct disassemble_info
*info
,
6001 const struct sopcode32
*insn
;
6002 void *stream
= info
->stream
;
6003 fprintf_ftype func
= info
->fprintf_func
;
6005 unsigned long value
= 0;
6008 struct arm_private_data
*private_data
= info
->private_data
;
6009 arm_feature_set allowed_arches
= ARM_ARCH_NONE
;
6010 arm_feature_set arm_ext_v8_1m_main
=
6011 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
6013 allowed_arches
= private_data
->features
;
6015 for (insn
= coprocessor_opcodes
; insn
->assembler
; insn
++)
6017 unsigned long u_reg
= 16;
6018 bfd_boolean is_unpredictable
= FALSE
;
6019 signed long value_in_comment
= 0;
6022 if (ARM_FEATURE_ZERO (insn
->arch
))
6023 switch (insn
->value
)
6025 case SENTINEL_IWMMXT_START
:
6026 if (info
->mach
!= bfd_mach_arm_XScale
6027 && info
->mach
!= bfd_mach_arm_iWMMXt
6028 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
6031 while ((! ARM_FEATURE_ZERO (insn
->arch
))
6032 && insn
->value
!= SENTINEL_IWMMXT_END
);
6035 case SENTINEL_IWMMXT_END
:
6038 case SENTINEL_GENERIC_START
:
6039 allowed_arches
= private_data
->features
;
6047 value
= insn
->value
;
6048 cp_num
= (given
>> 8) & 0xf;
6052 /* The high 4 bits are 0xe for Arm conditional instructions, and
6053 0xe for arm unconditional instructions. The rest of the
6054 encoding is the same. */
6056 value
|= 0xe0000000;
6064 /* Only match unconditional instuctions against unconditional
6066 if ((given
& 0xf0000000) == 0xf0000000)
6073 cond
= (given
>> 28) & 0xf;
6079 if ((insn
->isa
== T32
&& !thumb
)
6080 || (insn
->isa
== ARM
&& thumb
))
6083 if ((given
& mask
) != value
)
6086 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, allowed_arches
))
6089 if (insn
->value
== 0xfe000010 /* mcr2 */
6090 || insn
->value
== 0xfe100010 /* mrc2 */
6091 || insn
->value
== 0xfc100000 /* ldc2 */
6092 || insn
->value
== 0xfc000000) /* stc2 */
6094 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
6095 is_unpredictable
= TRUE
;
6097 /* Armv8.1-M Mainline FP & MVE instructions. */
6098 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
6099 && !ARM_CPU_IS_ANY (allowed_arches
)
6100 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
6104 else if (insn
->value
== 0x0e000000 /* cdp */
6105 || insn
->value
== 0xfe000000 /* cdp2 */
6106 || insn
->value
== 0x0e000010 /* mcr */
6107 || insn
->value
== 0x0e100010 /* mrc */
6108 || insn
->value
== 0x0c100000 /* ldc */
6109 || insn
->value
== 0x0c000000) /* stc */
6111 /* Floating-point instructions. */
6112 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
6115 /* Armv8.1-M Mainline FP & MVE instructions. */
6116 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
6117 && !ARM_CPU_IS_ANY (allowed_arches
)
6118 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
6121 else if ((insn
->value
== 0xec100f80 /* vldr (system register) */
6122 || insn
->value
== 0xec000f80) /* vstr (system register) */
6123 && arm_decode_field (given
, 24, 24) == 0
6124 && arm_decode_field (given
, 21, 21) == 0)
6125 /* If the P and W bits are both 0 then these encodings match the MVE
6126 VLDR and VSTR instructions, these are in a different table, so we
6127 don't let it match here. */
6130 for (c
= insn
->assembler
; *c
; c
++)
6134 const char mod
= *++c
;
6138 func (stream
, "%%");
6144 int rn
= (given
>> 16) & 0xf;
6145 bfd_vma offset
= given
& 0xff;
6148 offset
= given
& 0x7f;
6150 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
6152 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
6154 /* Not unindexed. The offset is scaled. */
6156 /* vldr.16/vstr.16 will shift the address
6157 left by 1 bit only. */
6158 offset
= offset
* 2;
6160 offset
= offset
* 4;
6162 if (NEGATIVE_BIT_SET
)
6165 value_in_comment
= offset
;
6171 func (stream
, ", #%d]%s",
6173 WRITEBACK_BIT_SET
? "!" : "");
6174 else if (NEGATIVE_BIT_SET
)
6175 func (stream
, ", #-0]");
6183 if (WRITEBACK_BIT_SET
)
6186 func (stream
, ", #%d", (int) offset
);
6187 else if (NEGATIVE_BIT_SET
)
6188 func (stream
, ", #-0");
6192 func (stream
, ", {%s%d}",
6193 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
6195 value_in_comment
= offset
;
6198 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
6200 func (stream
, "\t; ");
6201 /* For unaligned PCs, apply off-by-alignment
6203 info
->print_address_func (offset
+ pc
6204 + info
->bytes_per_chunk
* 2
6213 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
6214 int offset
= (given
>> 1) & 0x3f;
6217 func (stream
, "{d%d}", regno
);
6218 else if (regno
+ offset
> 32)
6219 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
6221 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
6227 bfd_boolean single
= ((given
>> 8) & 1) == 0;
6228 char reg_prefix
= single
? 's' : 'd';
6229 int Dreg
= (given
>> 22) & 0x1;
6230 int Vdreg
= (given
>> 12) & 0xf;
6231 int reg
= single
? ((Vdreg
<< 1) | Dreg
)
6232 : ((Dreg
<< 4) | Vdreg
);
6233 int num
= (given
>> (single
? 0 : 1)) & 0x7f;
6234 int maxreg
= single
? 31 : 15;
6235 int topreg
= reg
+ num
- 1;
6238 func (stream
, "{VPR}");
6240 func (stream
, "{%c%d, VPR}", reg_prefix
, reg
);
6241 else if (topreg
> maxreg
)
6242 func (stream
, "{%c%d-<overflow reg d%d, VPR}",
6243 reg_prefix
, reg
, single
? topreg
>> 1 : topreg
);
6245 func (stream
, "{%c%d-%c%d, VPR}", reg_prefix
, reg
,
6246 reg_prefix
, topreg
);
6251 if (cond
!= COND_UNCOND
)
6252 is_unpredictable
= TRUE
;
6256 if (cond
!= COND_UNCOND
&& cp_num
== 9)
6257 is_unpredictable
= TRUE
;
6259 func (stream
, "%s", arm_conditional
[cond
]);
6263 /* Print a Cirrus/DSP shift immediate. */
6264 /* Immediates are 7bit signed ints with bits 0..3 in
6265 bits 0..3 of opcode and bits 4..6 in bits 5..7
6270 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
6272 /* Is ``imm'' a negative number? */
6276 func (stream
, "%d", imm
);
6284 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
6289 func (stream
, "FPSCR");
6292 func (stream
, "FPSCR_nzcvqc");
6295 func (stream
, "VPR");
6298 func (stream
, "P0");
6301 func (stream
, "FPCXTNS");
6304 func (stream
, "FPCXTS");
6307 func (stream
, "<invalid reg %lu>", regno
);
6314 switch (given
& 0x00408000)
6331 switch (given
& 0x00080080)
6343 func (stream
, _("<illegal precision>"));
6349 switch (given
& 0x00408000)
6367 switch (given
& 0x60)
6383 case '0': case '1': case '2': case '3': case '4':
6384 case '5': case '6': case '7': case '8': case '9':
6388 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
6394 is_unpredictable
= TRUE
;
6399 /* Eat the 'u' character. */
6403 is_unpredictable
= TRUE
;
6406 func (stream
, "%s", arm_regnames
[value
]);
6409 if (given
& (1 << 6))
6413 func (stream
, "d%ld", value
);
6418 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
6420 func (stream
, "q%ld", value
>> 1);
6423 func (stream
, "%ld", value
);
6424 value_in_comment
= value
;
6428 /* Converts immediate 8 bit back to float value. */
6429 unsigned floatVal
= (value
& 0x80) << 24
6430 | (value
& 0x3F) << 19
6431 | ((value
& 0x40) ? (0xF8 << 22) : (1 << 30));
6433 /* Quarter float have a maximum value of 31.0.
6434 Get floating point value multiplied by 1e7.
6435 The maximum value stays in limit of a 32-bit int. */
6437 (78125 << (((floatVal
>> 23) & 0xFF) - 124)) *
6438 (16 + (value
& 0xF));
6440 if (!(decVal
% 1000000))
6441 func (stream
, "%ld\t; 0x%08x %c%u.%01u", value
,
6442 floatVal
, value
& 0x80 ? '-' : ' ',
6444 decVal
% 10000000 / 1000000);
6445 else if (!(decVal
% 10000))
6446 func (stream
, "%ld\t; 0x%08x %c%u.%03u", value
,
6447 floatVal
, value
& 0x80 ? '-' : ' ',
6449 decVal
% 10000000 / 10000);
6451 func (stream
, "%ld\t; 0x%08x %c%u.%07u", value
,
6452 floatVal
, value
& 0x80 ? '-' : ' ',
6453 decVal
/ 10000000, decVal
% 10000000);
6458 int from
= (given
& (1 << 7)) ? 32 : 16;
6459 func (stream
, "%ld", from
- value
);
6465 func (stream
, "#%s", arm_fp_const
[value
& 7]);
6467 func (stream
, "f%ld", value
);
6472 func (stream
, "%s", iwmmxt_wwnames
[value
]);
6474 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
6478 func (stream
, "%s", iwmmxt_regnames
[value
]);
6481 func (stream
, "%s", iwmmxt_cregnames
[value
]);
6485 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
6492 func (stream
, "eq");
6496 func (stream
, "vs");
6500 func (stream
, "ge");
6504 func (stream
, "gt");
6508 func (stream
, "??");
6516 func (stream
, "%c", *c
);
6520 if (value
== ((1ul << width
) - 1))
6521 func (stream
, "%c", *c
);
6524 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
6536 int single
= *c
++ == 'y';
6541 case '4': /* Sm pair */
6542 case '0': /* Sm, Dm */
6543 regno
= given
& 0x0000000f;
6547 regno
+= (given
>> 5) & 1;
6550 regno
+= ((given
>> 5) & 1) << 4;
6553 case '1': /* Sd, Dd */
6554 regno
= (given
>> 12) & 0x0000000f;
6558 regno
+= (given
>> 22) & 1;
6561 regno
+= ((given
>> 22) & 1) << 4;
6564 case '2': /* Sn, Dn */
6565 regno
= (given
>> 16) & 0x0000000f;
6569 regno
+= (given
>> 7) & 1;
6572 regno
+= ((given
>> 7) & 1) << 4;
6575 case '3': /* List */
6577 regno
= (given
>> 12) & 0x0000000f;
6581 regno
+= (given
>> 22) & 1;
6584 regno
+= ((given
>> 22) & 1) << 4;
6591 func (stream
, "%c%d", single
? 's' : 'd', regno
);
6595 int count
= given
& 0xff;
6602 func (stream
, "-%c%d",
6610 func (stream
, ", %c%d", single
? 's' : 'd',
6616 switch (given
& 0x00400100)
6618 case 0x00000000: func (stream
, "b"); break;
6619 case 0x00400000: func (stream
, "h"); break;
6620 case 0x00000100: func (stream
, "w"); break;
6621 case 0x00400100: func (stream
, "d"); break;
6629 /* given (20, 23) | given (0, 3) */
6630 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
6631 func (stream
, "%d", (int) value
);
6636 /* This is like the 'A' operator, except that if
6637 the width field "M" is zero, then the offset is
6638 *not* multiplied by four. */
6640 int offset
= given
& 0xff;
6641 int multiplier
= (given
& 0x00000100) ? 4 : 1;
6643 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
6647 value_in_comment
= offset
* multiplier
;
6648 if (NEGATIVE_BIT_SET
)
6649 value_in_comment
= - value_in_comment
;
6655 func (stream
, ", #%s%d]%s",
6656 NEGATIVE_BIT_SET
? "-" : "",
6657 offset
* multiplier
,
6658 WRITEBACK_BIT_SET
? "!" : "");
6660 func (stream
, "], #%s%d",
6661 NEGATIVE_BIT_SET
? "-" : "",
6662 offset
* multiplier
);
6671 int imm4
= (given
>> 4) & 0xf;
6672 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
6673 int ubit
= ! NEGATIVE_BIT_SET
;
6674 const char *rm
= arm_regnames
[given
& 0xf];
6675 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
6681 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
6683 func (stream
, ", lsl #%d", imm4
);
6690 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
6692 func (stream
, ", lsl #%d", imm4
);
6694 if (puw_bits
== 5 || puw_bits
== 7)
6699 func (stream
, "INVALID");
6707 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
6708 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
6717 func (stream
, "%c", *c
);
6720 if (value_in_comment
> 32 || value_in_comment
< -16)
6721 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
6723 if (is_unpredictable
)
6724 func (stream
, UNPREDICTABLE_INSTRUCTION
);
6731 /* Decodes and prints ARM addressing modes. Returns the offset
6732 used in the address, if any, if it is worthwhile printing the
6733 offset as a hexadecimal value in a comment at the end of the
6734 line of disassembly. */
6737 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
6739 void *stream
= info
->stream
;
6740 fprintf_ftype func
= info
->fprintf_func
;
6743 if (((given
& 0x000f0000) == 0x000f0000)
6744 && ((given
& 0x02000000) == 0))
6746 offset
= given
& 0xfff;
6748 func (stream
, "[pc");
6752 /* Pre-indexed. Elide offset of positive zero when
6754 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
6755 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
6757 if (NEGATIVE_BIT_SET
)
6762 /* Cope with the possibility of write-back
6763 being used. Probably a very dangerous thing
6764 for the programmer to do, but who are we to
6766 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
6768 else /* Post indexed. */
6770 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
6772 /* Ie ignore the offset. */
6776 func (stream
, "\t; ");
6777 info
->print_address_func (offset
, info
);
6782 func (stream
, "[%s",
6783 arm_regnames
[(given
>> 16) & 0xf]);
6787 if ((given
& 0x02000000) == 0)
6789 /* Elide offset of positive zero when non-writeback. */
6790 offset
= given
& 0xfff;
6791 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
6792 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
6796 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
6797 arm_decode_shift (given
, func
, stream
, TRUE
);
6800 func (stream
, "]%s",
6801 WRITEBACK_BIT_SET
? "!" : "");
6805 if ((given
& 0x02000000) == 0)
6807 /* Always show offset. */
6808 offset
= given
& 0xfff;
6809 func (stream
, "], #%s%d",
6810 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
6814 func (stream
, "], %s",
6815 NEGATIVE_BIT_SET
? "-" : "");
6816 arm_decode_shift (given
, func
, stream
, TRUE
);
6819 if (NEGATIVE_BIT_SET
)
6823 return (signed long) offset
;
6826 /* Print one neon instruction on INFO->STREAM.
6827 Return TRUE if the instuction matched, FALSE if this is not a
6828 recognised neon instruction. */
6831 print_insn_neon (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
6833 const struct opcode32
*insn
;
6834 void *stream
= info
->stream
;
6835 fprintf_ftype func
= info
->fprintf_func
;
6839 if ((given
& 0xef000000) == 0xef000000)
6841 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
6842 unsigned long bit28
= given
& (1 << 28);
6844 given
&= 0x00ffffff;
6846 given
|= 0xf3000000;
6848 given
|= 0xf2000000;
6850 else if ((given
& 0xff000000) == 0xf9000000)
6851 given
^= 0xf9000000 ^ 0xf4000000;
6852 /* vdup is also a valid neon instruction. */
6853 else if ((given
& 0xff910f5f) != 0xee800b10)
6857 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
6859 if ((given
& insn
->mask
) == insn
->value
)
6861 signed long value_in_comment
= 0;
6862 bfd_boolean is_unpredictable
= FALSE
;
6865 for (c
= insn
->assembler
; *c
; c
++)
6872 func (stream
, "%%");
6876 if (thumb
&& ifthen_state
)
6877 is_unpredictable
= TRUE
;
6881 if (thumb
&& ifthen_state
)
6882 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
6887 static const unsigned char enc
[16] =
6889 0x4, 0x14, /* st4 0,1 */
6901 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
6902 int rn
= ((given
>> 16) & 0xf);
6903 int rm
= ((given
>> 0) & 0xf);
6904 int align
= ((given
>> 4) & 0x3);
6905 int type
= ((given
>> 8) & 0xf);
6906 int n
= enc
[type
] & 0xf;
6907 int stride
= (enc
[type
] >> 4) + 1;
6912 for (ix
= 0; ix
!= n
; ix
++)
6913 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
6915 func (stream
, "d%d", rd
);
6917 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
6918 func (stream
, "}, [%s", arm_regnames
[rn
]);
6920 func (stream
, " :%d", 32 << align
);
6925 func (stream
, ", %s", arm_regnames
[rm
]);
6931 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
6932 int rn
= ((given
>> 16) & 0xf);
6933 int rm
= ((given
>> 0) & 0xf);
6934 int idx_align
= ((given
>> 4) & 0xf);
6936 int size
= ((given
>> 10) & 0x3);
6937 int idx
= idx_align
>> (size
+ 1);
6938 int length
= ((given
>> 8) & 3) + 1;
6942 if (length
> 1 && size
> 0)
6943 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
6949 int amask
= (1 << size
) - 1;
6950 if ((idx_align
& (1 << size
)) != 0)
6954 if ((idx_align
& amask
) == amask
)
6956 else if ((idx_align
& amask
) != 0)
6963 if (size
== 2 && (idx_align
& 2) != 0)
6965 align
= (idx_align
& 1) ? 16 << size
: 0;
6969 if ((size
== 2 && (idx_align
& 3) != 0)
6970 || (idx_align
& 1) != 0)
6977 if ((idx_align
& 3) == 3)
6979 align
= (idx_align
& 3) * 64;
6982 align
= (idx_align
& 1) ? 32 << size
: 0;
6990 for (i
= 0; i
< length
; i
++)
6991 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
6992 rd
+ i
* stride
, idx
);
6993 func (stream
, "}, [%s", arm_regnames
[rn
]);
6995 func (stream
, " :%d", align
);
7000 func (stream
, ", %s", arm_regnames
[rm
]);
7006 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
7007 int rn
= ((given
>> 16) & 0xf);
7008 int rm
= ((given
>> 0) & 0xf);
7009 int align
= ((given
>> 4) & 0x1);
7010 int size
= ((given
>> 6) & 0x3);
7011 int type
= ((given
>> 8) & 0x3);
7013 int stride
= ((given
>> 5) & 0x1);
7016 if (stride
&& (n
== 1))
7023 for (ix
= 0; ix
!= n
; ix
++)
7024 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
7026 func (stream
, "d%d[]", rd
);
7028 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
7029 func (stream
, "}, [%s", arm_regnames
[rn
]);
7032 align
= (8 * (type
+ 1)) << size
;
7034 align
= (size
> 1) ? align
>> 1 : align
;
7035 if (type
== 2 || (type
== 0 && !size
))
7036 func (stream
, " :<bad align %d>", align
);
7038 func (stream
, " :%d", align
);
7044 func (stream
, ", %s", arm_regnames
[rm
]);
7050 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
7051 int size
= (given
>> 20) & 3;
7052 int reg
= raw_reg
& ((4 << size
) - 1);
7053 int ix
= raw_reg
>> size
>> 2;
7055 func (stream
, "d%d[%d]", reg
, ix
);
7060 /* Neon encoded constant for mov, mvn, vorr, vbic. */
7063 int cmode
= (given
>> 8) & 0xf;
7064 int op
= (given
>> 5) & 0x1;
7065 unsigned long value
= 0, hival
= 0;
7070 bits
|= ((given
>> 24) & 1) << 7;
7071 bits
|= ((given
>> 16) & 7) << 4;
7072 bits
|= ((given
>> 0) & 15) << 0;
7076 shift
= (cmode
>> 1) & 3;
7077 value
= (unsigned long) bits
<< (8 * shift
);
7080 else if (cmode
< 12)
7082 shift
= (cmode
>> 1) & 1;
7083 value
= (unsigned long) bits
<< (8 * shift
);
7086 else if (cmode
< 14)
7088 shift
= (cmode
& 1) + 1;
7089 value
= (unsigned long) bits
<< (8 * shift
);
7090 value
|= (1ul << (8 * shift
)) - 1;
7093 else if (cmode
== 14)
7097 /* Bit replication into bytes. */
7103 for (ix
= 7; ix
>= 0; ix
--)
7105 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
7107 value
= (value
<< 8) | mask
;
7109 hival
= (hival
<< 8) | mask
;
7115 /* Byte replication. */
7116 value
= (unsigned long) bits
;
7122 /* Floating point encoding. */
7125 value
= (unsigned long) (bits
& 0x7f) << 19;
7126 value
|= (unsigned long) (bits
& 0x80) << 24;
7127 tmp
= bits
& 0x40 ? 0x3c : 0x40;
7128 value
|= (unsigned long) tmp
<< 24;
7134 func (stream
, "<illegal constant %.8x:%x:%x>",
7142 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
7146 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
7152 unsigned char valbytes
[4];
7155 /* Do this a byte at a time so we don't have to
7156 worry about the host's endianness. */
7157 valbytes
[0] = value
& 0xff;
7158 valbytes
[1] = (value
>> 8) & 0xff;
7159 valbytes
[2] = (value
>> 16) & 0xff;
7160 valbytes
[3] = (value
>> 24) & 0xff;
7162 floatformat_to_double
7163 (& floatformat_ieee_single_little
, valbytes
,
7166 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
7170 func (stream
, "#%ld\t; 0x%.8lx",
7171 (long) (((value
& 0x80000000L
) != 0)
7172 ? value
| ~0xffffffffL
: value
),
7177 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
7188 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
7189 int num
= (given
>> 8) & 0x3;
7192 func (stream
, "{d%d}", regno
);
7193 else if (num
+ regno
>= 32)
7194 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
7196 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
7201 case '0': case '1': case '2': case '3': case '4':
7202 case '5': case '6': case '7': case '8': case '9':
7205 unsigned long value
;
7207 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
7212 func (stream
, "%s", arm_regnames
[value
]);
7215 func (stream
, "%ld", value
);
7216 value_in_comment
= value
;
7219 func (stream
, "%ld", (1ul << width
) - value
);
7225 /* Various width encodings. */
7227 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
7232 if (*c
>= '0' && *c
<= '9')
7234 else if (*c
>= 'a' && *c
<= 'f')
7235 limit
= *c
- 'a' + 10;
7241 if (value
< low
|| value
> high
)
7242 func (stream
, "<illegal width %d>", base
<< value
);
7244 func (stream
, "%d", base
<< value
);
7248 if (given
& (1 << 6))
7252 func (stream
, "d%ld", value
);
7257 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
7259 func (stream
, "q%ld", value
>> 1);
7265 func (stream
, "%c", *c
);
7269 if (value
== ((1ul << width
) - 1))
7270 func (stream
, "%c", *c
);
7273 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
7287 func (stream
, "%c", *c
);
7290 if (value_in_comment
> 32 || value_in_comment
< -16)
7291 func (stream
, "\t; 0x%lx", value_in_comment
);
7293 if (is_unpredictable
)
7294 func (stream
, UNPREDICTABLE_INSTRUCTION
);
7302 /* Print one mve instruction on INFO->STREAM.
7303 Return TRUE if the instuction matched, FALSE if this is not a
7304 recognised mve instruction. */
7307 print_insn_mve (struct disassemble_info
*info
, long given
)
7309 const struct mopcode32
*insn
;
7310 void *stream
= info
->stream
;
7311 fprintf_ftype func
= info
->fprintf_func
;
7313 for (insn
= mve_opcodes
; insn
->assembler
; insn
++)
7315 if (((given
& insn
->mask
) == insn
->value
)
7316 && !is_mve_encoding_conflict (given
, insn
->mve_op
))
7318 signed long value_in_comment
= 0;
7319 bfd_boolean is_unpredictable
= FALSE
;
7320 bfd_boolean is_undefined
= FALSE
;
7322 enum mve_unpredictable unpredictable_cond
= UNPRED_NONE
;
7323 enum mve_undefined undefined_cond
= UNDEF_NONE
;
7325 /* Most vector mve instruction are illegal in a it block.
7326 There are a few exceptions; check for them. */
7327 if (ifthen_state
&& !is_mve_okay_in_it (insn
->mve_op
))
7329 is_unpredictable
= TRUE
;
7330 unpredictable_cond
= UNPRED_IT_BLOCK
;
7332 else if (is_mve_unpredictable (given
, insn
->mve_op
,
7333 &unpredictable_cond
))
7334 is_unpredictable
= TRUE
;
7336 if (is_mve_undefined (given
, insn
->mve_op
, &undefined_cond
))
7337 is_undefined
= TRUE
;
7339 for (c
= insn
->assembler
; *c
; c
++)
7346 func (stream
, "%%");
7350 /* Don't print anything for '+' as it is implied. */
7351 if (arm_decode_field (given
, 23, 23) == 0)
7357 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
7361 print_mve_vld_str_addr (info
, given
, insn
->mve_op
);
7366 long mve_mask
= mve_extract_pred_mask (given
);
7367 func (stream
, "%s", mve_predicatenames
[mve_mask
]);
7372 print_vec_condition (info
, given
, insn
->mve_op
);
7376 if (arm_decode_field (given
, 0, 0) == 1)
7379 = arm_decode_field (given
, 4, 4)
7380 | (arm_decode_field (given
, 6, 6) << 1);
7382 func (stream
, ", uxtw #%lu", size
);
7387 print_mve_rounding_mode (info
, given
, insn
->mve_op
);
7391 print_mve_vcvt_size (info
, given
, insn
->mve_op
);
7396 unsigned long op1
= arm_decode_field (given
, 21, 22);
7398 if ((insn
->mve_op
== MVE_VMOV_VEC_LANE_TO_GP
))
7400 /* Check for signed. */
7401 if (arm_decode_field (given
, 23, 23) == 0)
7403 /* We don't print 's' for S32. */
7404 if ((arm_decode_field (given
, 5, 6) == 0)
7405 && ((op1
== 0) || (op1
== 1)))
7415 if (arm_decode_field (given
, 28, 28) == 0)
7424 print_instruction_predicate (info
);
7428 if (arm_decode_field (given
, 21, 21) == 1)
7433 print_mve_register_blocks (info
, given
, insn
->mve_op
);
7437 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
7439 print_simd_imm8 (info
, given
, 28, insn
);
7443 print_mve_vmov_index (info
, given
);
7446 case '0': case '1': case '2': case '3': case '4':
7447 case '5': case '6': case '7': case '8': case '9':
7450 unsigned long value
;
7452 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
7458 is_unpredictable
= TRUE
;
7459 else if (value
== 15)
7460 func (stream
, "zr");
7462 func (stream
, "%s", arm_regnames
[value
]);
7465 print_mve_size (info
,
7472 = arm_decode_field (given
, 0, 6);
7473 unsigned long mod_imm
= imm
;
7475 switch (insn
->mve_op
)
7477 case MVE_VLDRW_GATHER_T5
:
7478 case MVE_VSTRW_SCATTER_T5
:
7479 mod_imm
= mod_imm
<< 2;
7481 case MVE_VSTRD_SCATTER_T6
:
7482 case MVE_VLDRD_GATHER_T6
:
7483 mod_imm
= mod_imm
<< 3;
7490 func (stream
, "%lu", mod_imm
);
7494 func (stream
, "%lu", 64 - value
);
7497 func (stream
, "%s", arm_regnames
[value
]);
7500 func (stream
, "%ld", value
);
7501 value_in_comment
= value
;
7504 func (stream
, "s%ld", value
);
7508 func (stream
, "<illegal reg q%ld.5>", value
);
7510 func (stream
, "q%ld", value
);
7513 func (stream
, "0x%08lx", value
);
7525 func (stream
, "%c", *c
);
7528 if (value_in_comment
> 32 || value_in_comment
< -16)
7529 func (stream
, "\t; 0x%lx", value_in_comment
);
7531 if (is_unpredictable
)
7532 print_mve_unpredictable (info
, unpredictable_cond
);
7535 print_mve_undefined (info
, undefined_cond
);
7537 if ((vpt_block_state
.in_vpt_block
== FALSE
)
7539 && (is_vpt_instruction (given
) == TRUE
))
7540 mark_inside_vpt_block (given
);
7541 else if (vpt_block_state
.in_vpt_block
== TRUE
)
7542 update_vpt_block_state ();
7551 /* Return the name of a v7A special register. */
7554 banked_regname (unsigned reg
)
7558 case 15: return "CPSR";
7559 case 32: return "R8_usr";
7560 case 33: return "R9_usr";
7561 case 34: return "R10_usr";
7562 case 35: return "R11_usr";
7563 case 36: return "R12_usr";
7564 case 37: return "SP_usr";
7565 case 38: return "LR_usr";
7566 case 40: return "R8_fiq";
7567 case 41: return "R9_fiq";
7568 case 42: return "R10_fiq";
7569 case 43: return "R11_fiq";
7570 case 44: return "R12_fiq";
7571 case 45: return "SP_fiq";
7572 case 46: return "LR_fiq";
7573 case 48: return "LR_irq";
7574 case 49: return "SP_irq";
7575 case 50: return "LR_svc";
7576 case 51: return "SP_svc";
7577 case 52: return "LR_abt";
7578 case 53: return "SP_abt";
7579 case 54: return "LR_und";
7580 case 55: return "SP_und";
7581 case 60: return "LR_mon";
7582 case 61: return "SP_mon";
7583 case 62: return "ELR_hyp";
7584 case 63: return "SP_hyp";
7585 case 79: return "SPSR";
7586 case 110: return "SPSR_fiq";
7587 case 112: return "SPSR_irq";
7588 case 114: return "SPSR_svc";
7589 case 116: return "SPSR_abt";
7590 case 118: return "SPSR_und";
7591 case 124: return "SPSR_mon";
7592 case 126: return "SPSR_hyp";
7593 default: return NULL
;
7597 /* Return the name of the DMB/DSB option. */
7599 data_barrier_option (unsigned option
)
7601 switch (option
& 0xf)
7603 case 0xf: return "sy";
7604 case 0xe: return "st";
7605 case 0xd: return "ld";
7606 case 0xb: return "ish";
7607 case 0xa: return "ishst";
7608 case 0x9: return "ishld";
7609 case 0x7: return "un";
7610 case 0x6: return "unst";
7611 case 0x5: return "nshld";
7612 case 0x3: return "osh";
7613 case 0x2: return "oshst";
7614 case 0x1: return "oshld";
7615 default: return NULL
;
7619 /* Print one ARM instruction from PC on INFO->STREAM. */
7622 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
7624 const struct opcode32
*insn
;
7625 void *stream
= info
->stream
;
7626 fprintf_ftype func
= info
->fprintf_func
;
7627 struct arm_private_data
*private_data
= info
->private_data
;
7629 if (print_insn_coprocessor (pc
, info
, given
, FALSE
))
7632 if (print_insn_neon (info
, given
, FALSE
))
7635 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
7637 if ((given
& insn
->mask
) != insn
->value
)
7640 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, private_data
->features
))
7643 /* Special case: an instruction with all bits set in the condition field
7644 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
7645 or by the catchall at the end of the table. */
7646 if ((given
& 0xF0000000) != 0xF0000000
7647 || (insn
->mask
& 0xF0000000) == 0xF0000000
7648 || (insn
->mask
== 0 && insn
->value
== 0))
7650 unsigned long u_reg
= 16;
7651 unsigned long U_reg
= 16;
7652 bfd_boolean is_unpredictable
= FALSE
;
7653 signed long value_in_comment
= 0;
7656 for (c
= insn
->assembler
; *c
; c
++)
7660 bfd_boolean allow_unpredictable
= FALSE
;
7665 func (stream
, "%%");
7669 value_in_comment
= print_arm_address (pc
, info
, given
);
7673 /* Set P address bit and use normal address
7674 printing routine. */
7675 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
7679 allow_unpredictable
= TRUE
;
7682 if ((given
& 0x004f0000) == 0x004f0000)
7684 /* PC relative with immediate offset. */
7685 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
7689 /* Elide positive zero offset. */
7690 if (offset
|| NEGATIVE_BIT_SET
)
7691 func (stream
, "[pc, #%s%d]\t; ",
7692 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7694 func (stream
, "[pc]\t; ");
7695 if (NEGATIVE_BIT_SET
)
7697 info
->print_address_func (offset
+ pc
+ 8, info
);
7701 /* Always show the offset. */
7702 func (stream
, "[pc], #%s%d",
7703 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7704 if (! allow_unpredictable
)
7705 is_unpredictable
= TRUE
;
7710 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
7712 func (stream
, "[%s",
7713 arm_regnames
[(given
>> 16) & 0xf]);
7717 if (IMMEDIATE_BIT_SET
)
7719 /* Elide offset for non-writeback
7721 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
7723 func (stream
, ", #%s%d",
7724 NEGATIVE_BIT_SET
? "-" : "", offset
);
7726 if (NEGATIVE_BIT_SET
)
7729 value_in_comment
= offset
;
7733 /* Register Offset or Register Pre-Indexed. */
7734 func (stream
, ", %s%s",
7735 NEGATIVE_BIT_SET
? "-" : "",
7736 arm_regnames
[given
& 0xf]);
7738 /* Writing back to the register that is the source/
7739 destination of the load/store is unpredictable. */
7740 if (! allow_unpredictable
7741 && WRITEBACK_BIT_SET
7742 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
7743 is_unpredictable
= TRUE
;
7746 func (stream
, "]%s",
7747 WRITEBACK_BIT_SET
? "!" : "");
7751 if (IMMEDIATE_BIT_SET
)
7753 /* Immediate Post-indexed. */
7754 /* PR 10924: Offset must be printed, even if it is zero. */
7755 func (stream
, "], #%s%d",
7756 NEGATIVE_BIT_SET
? "-" : "", offset
);
7757 if (NEGATIVE_BIT_SET
)
7759 value_in_comment
= offset
;
7763 /* Register Post-indexed. */
7764 func (stream
, "], %s%s",
7765 NEGATIVE_BIT_SET
? "-" : "",
7766 arm_regnames
[given
& 0xf]);
7768 /* Writing back to the register that is the source/
7769 destination of the load/store is unpredictable. */
7770 if (! allow_unpredictable
7771 && (given
& 0xf) == ((given
>> 12) & 0xf))
7772 is_unpredictable
= TRUE
;
7775 if (! allow_unpredictable
)
7777 /* Writeback is automatically implied by post- addressing.
7778 Setting the W bit is unnecessary and ARM specify it as
7779 being unpredictable. */
7780 if (WRITEBACK_BIT_SET
7781 /* Specifying the PC register as the post-indexed
7782 registers is also unpredictable. */
7783 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
7784 is_unpredictable
= TRUE
;
7792 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
7793 info
->print_address_func (disp
* 4 + pc
+ 8, info
);
7798 if (((given
>> 28) & 0xf) != 0xe)
7800 arm_conditional
[(given
>> 28) & 0xf]);
7809 for (reg
= 0; reg
< 16; reg
++)
7810 if ((given
& (1 << reg
)) != 0)
7813 func (stream
, ", ");
7815 func (stream
, "%s", arm_regnames
[reg
]);
7819 is_unpredictable
= TRUE
;
7824 arm_decode_shift (given
, func
, stream
, FALSE
);
7828 if ((given
& 0x02000000) != 0)
7830 unsigned int rotate
= (given
& 0xf00) >> 7;
7831 unsigned int immed
= (given
& 0xff);
7834 a
= (((immed
<< (32 - rotate
))
7835 | (immed
>> rotate
)) & 0xffffffff);
7836 /* If there is another encoding with smaller rotate,
7837 the rotate should be specified directly. */
7838 for (i
= 0; i
< 32; i
+= 2)
7839 if ((a
<< i
| a
>> (32 - i
)) <= 0xff)
7843 func (stream
, "#%d, %d", immed
, rotate
);
7845 func (stream
, "#%d", a
);
7846 value_in_comment
= a
;
7849 arm_decode_shift (given
, func
, stream
, TRUE
);
7853 if ((given
& 0x0000f000) == 0x0000f000)
7855 arm_feature_set arm_ext_v6
=
7856 ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
7858 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
7859 mechanism for setting PSR flag bits. They are
7860 obsolete in V6 onwards. */
7861 if (! ARM_CPU_HAS_FEATURE (private_data
->features
, \
7865 is_unpredictable
= TRUE
;
7870 if ((given
& 0x01200000) == 0x00200000)
7876 int offset
= given
& 0xff;
7878 value_in_comment
= offset
* 4;
7879 if (NEGATIVE_BIT_SET
)
7880 value_in_comment
= - value_in_comment
;
7882 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
7887 func (stream
, ", #%d]%s",
7888 (int) value_in_comment
,
7889 WRITEBACK_BIT_SET
? "!" : "");
7897 if (WRITEBACK_BIT_SET
)
7900 func (stream
, ", #%d", (int) value_in_comment
);
7904 func (stream
, ", {%d}", (int) offset
);
7905 value_in_comment
= offset
;
7912 /* Print ARM V5 BLX(1) address: pc+25 bits. */
7917 if (! NEGATIVE_BIT_SET
)
7918 /* Is signed, hi bits should be ones. */
7919 offset
= (-1) ^ 0x00ffffff;
7921 /* Offset is (SignExtend(offset field)<<2). */
7922 offset
+= given
& 0x00ffffff;
7924 address
= offset
+ pc
+ 8;
7926 if (given
& 0x01000000)
7927 /* H bit allows addressing to 2-byte boundaries. */
7930 info
->print_address_func (address
, info
);
7935 if ((given
& 0x02000200) == 0x200)
7938 unsigned sysm
= (given
& 0x004f0000) >> 16;
7940 sysm
|= (given
& 0x300) >> 4;
7941 name
= banked_regname (sysm
);
7944 func (stream
, "%s", name
);
7946 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
7950 func (stream
, "%cPSR_",
7951 (given
& 0x00400000) ? 'S' : 'C');
7952 if (given
& 0x80000)
7954 if (given
& 0x40000)
7956 if (given
& 0x20000)
7958 if (given
& 0x10000)
7964 if ((given
& 0xf0) == 0x60)
7966 switch (given
& 0xf)
7968 case 0xf: func (stream
, "sy"); break;
7970 func (stream
, "#%d", (int) given
& 0xf);
7976 const char * opt
= data_barrier_option (given
& 0xf);
7978 func (stream
, "%s", opt
);
7980 func (stream
, "#%d", (int) given
& 0xf);
7984 case '0': case '1': case '2': case '3': case '4':
7985 case '5': case '6': case '7': case '8': case '9':
7988 unsigned long value
;
7990 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
7996 is_unpredictable
= TRUE
;
8000 /* We want register + 1 when decoding T. */
8006 /* Eat the 'u' character. */
8010 is_unpredictable
= TRUE
;
8015 /* Eat the 'U' character. */
8019 is_unpredictable
= TRUE
;
8022 func (stream
, "%s", arm_regnames
[value
]);
8025 func (stream
, "%ld", value
);
8026 value_in_comment
= value
;
8029 func (stream
, "%ld", value
* 8);
8030 value_in_comment
= value
* 8;
8033 func (stream
, "%ld", value
+ 1);
8034 value_in_comment
= value
+ 1;
8037 func (stream
, "0x%08lx", value
);
8039 /* Some SWI instructions have special
8041 if ((given
& 0x0fffffff) == 0x0FF00000)
8042 func (stream
, "\t; IMB");
8043 else if ((given
& 0x0fffffff) == 0x0FF00001)
8044 func (stream
, "\t; IMBRange");
8047 func (stream
, "%01lx", value
& 0xf);
8048 value_in_comment
= value
;
8053 func (stream
, "%c", *c
);
8057 if (value
== ((1ul << width
) - 1))
8058 func (stream
, "%c", *c
);
8061 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
8074 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
8075 func (stream
, "%d", imm
);
8076 value_in_comment
= imm
;
8081 /* LSB and WIDTH fields of BFI or BFC. The machine-
8082 language instruction encodes LSB and MSB. */
8084 long msb
= (given
& 0x001f0000) >> 16;
8085 long lsb
= (given
& 0x00000f80) >> 7;
8086 long w
= msb
- lsb
+ 1;
8089 func (stream
, "#%lu, #%lu", lsb
, w
);
8091 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
8096 /* Get the PSR/banked register name. */
8099 unsigned sysm
= (given
& 0x004f0000) >> 16;
8101 sysm
|= (given
& 0x300) >> 4;
8102 name
= banked_regname (sysm
);
8105 func (stream
, "%s", name
);
8107 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
8112 /* 16-bit unsigned immediate from a MOVT or MOVW
8113 instruction, encoded in bits 0:11 and 15:19. */
8115 long hi
= (given
& 0x000f0000) >> 4;
8116 long lo
= (given
& 0x00000fff);
8117 long imm16
= hi
| lo
;
8119 func (stream
, "#%lu", imm16
);
8120 value_in_comment
= imm16
;
8129 func (stream
, "%c", *c
);
8132 if (value_in_comment
> 32 || value_in_comment
< -16)
8133 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
8135 if (is_unpredictable
)
8136 func (stream
, UNPREDICTABLE_INSTRUCTION
);
8141 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
8145 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
8148 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8150 const struct opcode16
*insn
;
8151 void *stream
= info
->stream
;
8152 fprintf_ftype func
= info
->fprintf_func
;
8154 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
8155 if ((given
& insn
->mask
) == insn
->value
)
8157 signed long value_in_comment
= 0;
8158 const char *c
= insn
->assembler
;
8167 func (stream
, "%c", *c
);
8174 func (stream
, "%%");
8179 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
8184 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
8193 ifthen_next_state
= given
& 0xff;
8194 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
8195 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
8196 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
8201 if (ifthen_next_state
)
8202 func (stream
, "\t; unpredictable branch in IT block\n");
8207 func (stream
, "\t; unpredictable <IT:%s>",
8208 arm_conditional
[IFTHEN_COND
]);
8215 reg
= (given
>> 3) & 0x7;
8216 if (given
& (1 << 6))
8219 func (stream
, "%s", arm_regnames
[reg
]);
8228 if (given
& (1 << 7))
8231 func (stream
, "%s", arm_regnames
[reg
]);
8236 if (given
& (1 << 8))
8240 if (*c
== 'O' && (given
& (1 << 8)))
8250 /* It would be nice if we could spot
8251 ranges, and generate the rS-rE format: */
8252 for (reg
= 0; (reg
< 8); reg
++)
8253 if ((given
& (1 << reg
)) != 0)
8256 func (stream
, ", ");
8258 func (stream
, "%s", arm_regnames
[reg
]);
8264 func (stream
, ", ");
8266 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
8272 func (stream
, ", ");
8273 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
8281 /* Print writeback indicator for a LDMIA. We are doing a
8282 writeback if the base register is not in the register
8284 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
8289 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
8291 bfd_vma address
= (pc
+ 4
8292 + ((given
& 0x00f8) >> 2)
8293 + ((given
& 0x0200) >> 3));
8294 info
->print_address_func (address
, info
);
8299 /* Right shift immediate -- bits 6..10; 1-31 print
8300 as themselves, 0 prints as 32. */
8302 long imm
= (given
& 0x07c0) >> 6;
8305 func (stream
, "#%ld", imm
);
8309 case '0': case '1': case '2': case '3': case '4':
8310 case '5': case '6': case '7': case '8': case '9':
8312 int bitstart
= *c
++ - '0';
8315 while (*c
>= '0' && *c
<= '9')
8316 bitstart
= (bitstart
* 10) + *c
++ - '0';
8325 while (*c
>= '0' && *c
<= '9')
8326 bitend
= (bitend
* 10) + *c
++ - '0';
8329 reg
= given
>> bitstart
;
8330 reg
&= (2 << (bitend
- bitstart
)) - 1;
8335 func (stream
, "%s", arm_regnames
[reg
]);
8339 func (stream
, "%ld", (long) reg
);
8340 value_in_comment
= reg
;
8344 func (stream
, "%ld", (long) (reg
<< 1));
8345 value_in_comment
= reg
<< 1;
8349 func (stream
, "%ld", (long) (reg
<< 2));
8350 value_in_comment
= reg
<< 2;
8354 /* PC-relative address -- the bottom two
8355 bits of the address are dropped
8356 before the calculation. */
8357 info
->print_address_func
8358 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
8359 value_in_comment
= 0;
8363 func (stream
, "0x%04lx", (long) reg
);
8367 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
8368 info
->print_address_func (reg
* 2 + pc
+ 4, info
);
8369 value_in_comment
= 0;
8373 func (stream
, "%s", arm_conditional
[reg
]);
8384 if ((given
& (1 << bitstart
)) != 0)
8385 func (stream
, "%c", *c
);
8390 if ((given
& (1 << bitstart
)) != 0)
8391 func (stream
, "%c", *c
++);
8393 func (stream
, "%c", *++c
);
8407 if (value_in_comment
> 32 || value_in_comment
< -16)
8408 func (stream
, "\t; 0x%lx", value_in_comment
);
8413 func (stream
, UNKNOWN_INSTRUCTION_16BIT
, (unsigned)given
);
8417 /* Return the name of an V7M special register. */
8420 psr_name (int regno
)
8424 case 0x0: return "APSR";
8425 case 0x1: return "IAPSR";
8426 case 0x2: return "EAPSR";
8427 case 0x3: return "PSR";
8428 case 0x5: return "IPSR";
8429 case 0x6: return "EPSR";
8430 case 0x7: return "IEPSR";
8431 case 0x8: return "MSP";
8432 case 0x9: return "PSP";
8433 case 0xa: return "MSPLIM";
8434 case 0xb: return "PSPLIM";
8435 case 0x10: return "PRIMASK";
8436 case 0x11: return "BASEPRI";
8437 case 0x12: return "BASEPRI_MAX";
8438 case 0x13: return "FAULTMASK";
8439 case 0x14: return "CONTROL";
8440 case 0x88: return "MSP_NS";
8441 case 0x89: return "PSP_NS";
8442 case 0x8a: return "MSPLIM_NS";
8443 case 0x8b: return "PSPLIM_NS";
8444 case 0x90: return "PRIMASK_NS";
8445 case 0x91: return "BASEPRI_NS";
8446 case 0x93: return "FAULTMASK_NS";
8447 case 0x94: return "CONTROL_NS";
8448 case 0x98: return "SP_NS";
8449 default: return "<unknown>";
8453 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
8456 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8458 const struct opcode32
*insn
;
8459 void *stream
= info
->stream
;
8460 fprintf_ftype func
= info
->fprintf_func
;
8461 bfd_boolean is_mve
= is_mve_architecture (info
);
8463 if (print_insn_coprocessor (pc
, info
, given
, TRUE
))
8466 if ((is_mve
== FALSE
) && print_insn_neon (info
, given
, TRUE
))
8469 if (is_mve
&& print_insn_mve (info
, given
))
8472 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
8473 if ((given
& insn
->mask
) == insn
->value
)
8475 bfd_boolean is_clrm
= FALSE
;
8476 bfd_boolean is_unpredictable
= FALSE
;
8477 signed long value_in_comment
= 0;
8478 const char *c
= insn
->assembler
;
8484 func (stream
, "%c", *c
);
8491 func (stream
, "%%");
8496 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
8500 if (ifthen_next_state
)
8501 func (stream
, "\t; unpredictable branch in IT block\n");
8506 func (stream
, "\t; unpredictable <IT:%s>",
8507 arm_conditional
[IFTHEN_COND
]);
8512 unsigned int imm12
= 0;
8514 imm12
|= (given
& 0x000000ffu
);
8515 imm12
|= (given
& 0x00007000u
) >> 4;
8516 imm12
|= (given
& 0x04000000u
) >> 15;
8517 func (stream
, "#%u", imm12
);
8518 value_in_comment
= imm12
;
8524 unsigned int bits
= 0, imm
, imm8
, mod
;
8526 bits
|= (given
& 0x000000ffu
);
8527 bits
|= (given
& 0x00007000u
) >> 4;
8528 bits
|= (given
& 0x04000000u
) >> 15;
8529 imm8
= (bits
& 0x0ff);
8530 mod
= (bits
& 0xf00) >> 8;
8533 case 0: imm
= imm8
; break;
8534 case 1: imm
= ((imm8
<< 16) | imm8
); break;
8535 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
8536 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
8538 mod
= (bits
& 0xf80) >> 7;
8539 imm8
= (bits
& 0x07f) | 0x80;
8540 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
8542 func (stream
, "#%u", imm
);
8543 value_in_comment
= imm
;
8549 unsigned int imm
= 0;
8551 imm
|= (given
& 0x000000ffu
);
8552 imm
|= (given
& 0x00007000u
) >> 4;
8553 imm
|= (given
& 0x04000000u
) >> 15;
8554 imm
|= (given
& 0x000f0000u
) >> 4;
8555 func (stream
, "#%u", imm
);
8556 value_in_comment
= imm
;
8562 unsigned int imm
= 0;
8564 imm
|= (given
& 0x000f0000u
) >> 16;
8565 imm
|= (given
& 0x00000ff0u
) >> 0;
8566 imm
|= (given
& 0x0000000fu
) << 12;
8567 func (stream
, "#%u", imm
);
8568 value_in_comment
= imm
;
8574 unsigned int imm
= 0;
8576 imm
|= (given
& 0x000f0000u
) >> 4;
8577 imm
|= (given
& 0x00000fffu
) >> 0;
8578 func (stream
, "#%u", imm
);
8579 value_in_comment
= imm
;
8585 unsigned int imm
= 0;
8587 imm
|= (given
& 0x00000fffu
);
8588 imm
|= (given
& 0x000f0000u
) >> 4;
8589 func (stream
, "#%u", imm
);
8590 value_in_comment
= imm
;
8596 unsigned int reg
= (given
& 0x0000000fu
);
8597 unsigned int stp
= (given
& 0x00000030u
) >> 4;
8598 unsigned int imm
= 0;
8599 imm
|= (given
& 0x000000c0u
) >> 6;
8600 imm
|= (given
& 0x00007000u
) >> 10;
8602 func (stream
, "%s", arm_regnames
[reg
]);
8607 func (stream
, ", lsl #%u", imm
);
8613 func (stream
, ", lsr #%u", imm
);
8619 func (stream
, ", asr #%u", imm
);
8624 func (stream
, ", rrx");
8626 func (stream
, ", ror #%u", imm
);
8633 unsigned int Rn
= (given
& 0x000f0000) >> 16;
8634 unsigned int U
= ! NEGATIVE_BIT_SET
;
8635 unsigned int op
= (given
& 0x00000f00) >> 8;
8636 unsigned int i12
= (given
& 0x00000fff);
8637 unsigned int i8
= (given
& 0x000000ff);
8638 bfd_boolean writeback
= FALSE
, postind
= FALSE
;
8641 func (stream
, "[%s", arm_regnames
[Rn
]);
8642 if (U
) /* 12-bit positive immediate offset. */
8646 value_in_comment
= offset
;
8648 else if (Rn
== 15) /* 12-bit negative immediate offset. */
8649 offset
= - (int) i12
;
8650 else if (op
== 0x0) /* Shifted register offset. */
8652 unsigned int Rm
= (i8
& 0x0f);
8653 unsigned int sh
= (i8
& 0x30) >> 4;
8655 func (stream
, ", %s", arm_regnames
[Rm
]);
8657 func (stream
, ", lsl #%u", sh
);
8663 case 0xE: /* 8-bit positive immediate offset. */
8667 case 0xC: /* 8-bit negative immediate offset. */
8671 case 0xF: /* 8-bit + preindex with wb. */
8676 case 0xD: /* 8-bit - preindex with wb. */
8681 case 0xB: /* 8-bit + postindex. */
8686 case 0x9: /* 8-bit - postindex. */
8692 func (stream
, ", <undefined>]");
8697 func (stream
, "], #%d", (int) offset
);
8701 func (stream
, ", #%d", (int) offset
);
8702 func (stream
, writeback
? "]!" : "]");
8707 func (stream
, "\t; ");
8708 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
8716 unsigned int U
= ! NEGATIVE_BIT_SET
;
8717 unsigned int W
= WRITEBACK_BIT_SET
;
8718 unsigned int Rn
= (given
& 0x000f0000) >> 16;
8719 unsigned int off
= (given
& 0x000000ff);
8721 func (stream
, "[%s", arm_regnames
[Rn
]);
8727 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
8728 value_in_comment
= off
* 4 * (U
? 1 : -1);
8736 func (stream
, "], ");
8739 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
8740 value_in_comment
= off
* 4 * (U
? 1 : -1);
8744 func (stream
, "{%u}", off
);
8745 value_in_comment
= off
;
8753 unsigned int Sbit
= (given
& 0x01000000) >> 24;
8754 unsigned int type
= (given
& 0x00600000) >> 21;
8758 case 0: func (stream
, Sbit
? "sb" : "b"); break;
8759 case 1: func (stream
, Sbit
? "sh" : "h"); break;
8762 func (stream
, "??");
8765 func (stream
, "??");
8780 for (reg
= 0; reg
< 16; reg
++)
8781 if ((given
& (1 << reg
)) != 0)
8784 func (stream
, ", ");
8786 if (is_clrm
&& reg
== 13)
8787 func (stream
, "(invalid: %s)", arm_regnames
[reg
]);
8788 else if (is_clrm
&& reg
== 15)
8789 func (stream
, "%s", "APSR");
8791 func (stream
, "%s", arm_regnames
[reg
]);
8799 unsigned int msb
= (given
& 0x0000001f);
8800 unsigned int lsb
= 0;
8802 lsb
|= (given
& 0x000000c0u
) >> 6;
8803 lsb
|= (given
& 0x00007000u
) >> 10;
8804 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
8810 unsigned int width
= (given
& 0x0000001f) + 1;
8811 unsigned int lsb
= 0;
8813 lsb
|= (given
& 0x000000c0u
) >> 6;
8814 lsb
|= (given
& 0x00007000u
) >> 10;
8815 func (stream
, "#%u, #%u", lsb
, width
);
8821 unsigned int boff
= (((given
& 0x07800000) >> 23) << 1);
8822 func (stream
, "%x", boff
);
8828 unsigned int immA
= (given
& 0x001f0000u
) >> 16;
8829 unsigned int immB
= (given
& 0x000007feu
) >> 1;
8830 unsigned int immC
= (given
& 0x00000800u
) >> 11;
8833 offset
|= immA
<< 12;
8834 offset
|= immB
<< 2;
8835 offset
|= immC
<< 1;
8837 offset
= (offset
& 0x10000) ? offset
- (1 << 17) : offset
;
8839 info
->print_address_func (pc
+ 4 + offset
, info
);
8845 unsigned int immA
= (given
& 0x007f0000u
) >> 16;
8846 unsigned int immB
= (given
& 0x000007feu
) >> 1;
8847 unsigned int immC
= (given
& 0x00000800u
) >> 11;
8850 offset
|= immA
<< 12;
8851 offset
|= immB
<< 2;
8852 offset
|= immC
<< 1;
8854 offset
= (offset
& 0x40000) ? offset
- (1 << 19) : offset
;
8856 info
->print_address_func (pc
+ 4 + offset
, info
);
8862 unsigned int immA
= (given
& 0x00010000u
) >> 16;
8863 unsigned int immB
= (given
& 0x000007feu
) >> 1;
8864 unsigned int immC
= (given
& 0x00000800u
) >> 11;
8867 offset
|= immA
<< 12;
8868 offset
|= immB
<< 2;
8869 offset
|= immC
<< 1;
8871 offset
= (offset
& 0x1000) ? offset
- (1 << 13) : offset
;
8873 info
->print_address_func (pc
+ 4 + offset
, info
);
8875 unsigned int T
= (given
& 0x00020000u
) >> 17;
8876 unsigned int endoffset
= (((given
& 0x07800000) >> 23) << 1);
8877 unsigned int boffset
= (T
== 1) ? 4 : 2;
8878 func (stream
, ", ");
8879 func (stream
, "%x", endoffset
+ boffset
);
8885 unsigned int immh
= (given
& 0x000007feu
) >> 1;
8886 unsigned int imml
= (given
& 0x00000800u
) >> 11;
8892 info
->print_address_func (pc
+ 4 + imm32
, info
);
8898 unsigned int immh
= (given
& 0x000007feu
) >> 1;
8899 unsigned int imml
= (given
& 0x00000800u
) >> 11;
8905 info
->print_address_func (pc
+ 4 - imm32
, info
);
8911 unsigned int S
= (given
& 0x04000000u
) >> 26;
8912 unsigned int J1
= (given
& 0x00002000u
) >> 13;
8913 unsigned int J2
= (given
& 0x00000800u
) >> 11;
8919 offset
|= (given
& 0x003f0000) >> 4;
8920 offset
|= (given
& 0x000007ff) << 1;
8921 offset
-= (1 << 20);
8923 info
->print_address_func (pc
+ 4 + offset
, info
);
8929 unsigned int S
= (given
& 0x04000000u
) >> 26;
8930 unsigned int I1
= (given
& 0x00002000u
) >> 13;
8931 unsigned int I2
= (given
& 0x00000800u
) >> 11;
8935 offset
|= !(I1
^ S
) << 23;
8936 offset
|= !(I2
^ S
) << 22;
8937 offset
|= (given
& 0x03ff0000u
) >> 4;
8938 offset
|= (given
& 0x000007ffu
) << 1;
8939 offset
-= (1 << 24);
8942 /* BLX target addresses are always word aligned. */
8943 if ((given
& 0x00001000u
) == 0)
8946 info
->print_address_func (offset
, info
);
8952 unsigned int shift
= 0;
8954 shift
|= (given
& 0x000000c0u
) >> 6;
8955 shift
|= (given
& 0x00007000u
) >> 10;
8956 if (WRITEBACK_BIT_SET
)
8957 func (stream
, ", asr #%u", shift
);
8959 func (stream
, ", lsl #%u", shift
);
8960 /* else print nothing - lsl #0 */
8966 unsigned int rot
= (given
& 0x00000030) >> 4;
8969 func (stream
, ", ror #%u", rot
* 8);
8974 if ((given
& 0xf0) == 0x60)
8976 switch (given
& 0xf)
8978 case 0xf: func (stream
, "sy"); break;
8980 func (stream
, "#%d", (int) given
& 0xf);
8986 const char * opt
= data_barrier_option (given
& 0xf);
8988 func (stream
, "%s", opt
);
8990 func (stream
, "#%d", (int) given
& 0xf);
8995 if ((given
& 0xff) == 0)
8997 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
9007 else if ((given
& 0x20) == 0x20)
9010 unsigned sysm
= (given
& 0xf00) >> 8;
9012 sysm
|= (given
& 0x30);
9013 sysm
|= (given
& 0x00100000) >> 14;
9014 name
= banked_regname (sysm
);
9017 func (stream
, "%s", name
);
9019 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
9023 func (stream
, "%s", psr_name (given
& 0xff));
9028 if (((given
& 0xff) == 0)
9029 || ((given
& 0x20) == 0x20))
9032 unsigned sm
= (given
& 0xf0000) >> 16;
9034 sm
|= (given
& 0x30);
9035 sm
|= (given
& 0x00100000) >> 14;
9036 name
= banked_regname (sm
);
9039 func (stream
, "%s", name
);
9041 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
9044 func (stream
, "%s", psr_name (given
& 0xff));
9047 case '0': case '1': case '2': case '3': case '4':
9048 case '5': case '6': case '7': case '8': case '9':
9053 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
9058 func (stream
, "%lu", val
);
9059 value_in_comment
= val
;
9063 func (stream
, "%lu", val
+ 1);
9064 value_in_comment
= val
+ 1;
9068 func (stream
, "%lu", val
* 4);
9069 value_in_comment
= val
* 4;
9074 is_unpredictable
= TRUE
;
9078 is_unpredictable
= TRUE
;
9081 func (stream
, "%s", arm_regnames
[val
]);
9085 func (stream
, "%s", arm_conditional
[val
]);
9090 if (val
== ((1ul << width
) - 1))
9091 func (stream
, "%c", *c
);
9097 func (stream
, "%c", *c
);
9101 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
9106 func (stream
, "0x%lx", val
& 0xffffffffUL
);
9116 /* PR binutils/12534
9117 If we have a PC relative offset in an LDRD or STRD
9118 instructions then display the decoded address. */
9119 if (((given
>> 16) & 0xf) == 0xf)
9121 bfd_vma offset
= (given
& 0xff) * 4;
9123 if ((given
& (1 << 23)) == 0)
9125 func (stream
, "\t; ");
9126 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
9135 if (value_in_comment
> 32 || value_in_comment
< -16)
9136 func (stream
, "\t; 0x%lx", value_in_comment
);
9138 if (is_unpredictable
)
9139 func (stream
, UNPREDICTABLE_INSTRUCTION
);
9145 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
9149 /* Print data bytes on INFO->STREAM. */
9152 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
9153 struct disassemble_info
*info
,
9156 switch (info
->bytes_per_chunk
)
9159 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
9162 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
9165 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
9172 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
9173 being displayed in symbol relative addresses.
9175 Also disallow private symbol, with __tagsym$$ prefix,
9176 from ARM RVCT toolchain being displayed. */
9179 arm_symbol_is_valid (asymbol
* sym
,
9180 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
9187 name
= bfd_asymbol_name (sym
);
9189 return (name
&& *name
!= '$' && strncmp (name
, "__tagsym$$", 10));
9192 /* Parse the string of disassembler options. */
9195 parse_arm_disassembler_options (const char *options
)
9199 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
9201 if (CONST_STRNEQ (opt
, "reg-names-"))
9204 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
9205 if (disassembler_options_cmp (opt
, regnames
[i
].name
) == 0)
9207 regname_selected
= i
;
9211 if (i
>= NUM_ARM_OPTIONS
)
9212 /* xgettext: c-format */
9213 opcodes_error_handler (_("unrecognised register name set: %s"),
9216 else if (CONST_STRNEQ (opt
, "force-thumb"))
9218 else if (CONST_STRNEQ (opt
, "no-force-thumb"))
9221 /* xgettext: c-format */
9222 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt
);
9229 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
9230 enum map_type
*map_symbol
);
9232 /* Search back through the insn stream to determine if this instruction is
9233 conditionally executed. */
9236 find_ifthen_state (bfd_vma pc
,
9237 struct disassemble_info
*info
,
9243 /* COUNT is twice the number of instructions seen. It will be odd if we
9244 just crossed an instruction boundary. */
9247 unsigned int seen_it
;
9250 ifthen_address
= pc
;
9257 /* Scan backwards looking for IT instructions, keeping track of where
9258 instruction boundaries are. We don't know if something is actually an
9259 IT instruction until we find a definite instruction boundary. */
9262 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
9264 /* A symbol must be on an instruction boundary, and will not
9265 be within an IT block. */
9266 if (seen_it
&& (count
& 1))
9272 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
9277 insn
= (b
[0]) | (b
[1] << 8);
9279 insn
= (b
[1]) | (b
[0] << 8);
9282 if ((insn
& 0xf800) < 0xe800)
9284 /* Addr + 2 is an instruction boundary. See if this matches
9285 the expected boundary based on the position of the last
9292 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
9294 enum map_type type
= MAP_ARM
;
9295 bfd_boolean found
= mapping_symbol_for_insn (addr
, info
, &type
);
9297 if (!found
|| (found
&& type
== MAP_THUMB
))
9299 /* This could be an IT instruction. */
9301 it_count
= count
>> 1;
9304 if ((insn
& 0xf800) >= 0xe800)
9307 count
= (count
+ 2) | 1;
9308 /* IT blocks contain at most 4 instructions. */
9309 if (count
>= 8 && !seen_it
)
9312 /* We found an IT instruction. */
9313 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
9314 if ((ifthen_state
& 0xf) == 0)
9318 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
9322 is_mapping_symbol (struct disassemble_info
*info
, int n
,
9323 enum map_type
*map_type
)
9327 name
= bfd_asymbol_name (info
->symtab
[n
]);
9328 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
9329 && (name
[2] == 0 || name
[2] == '.'))
9331 *map_type
= ((name
[1] == 'a') ? MAP_ARM
9332 : (name
[1] == 't') ? MAP_THUMB
9340 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
9341 Returns nonzero if *MAP_TYPE was set. */
9344 get_map_sym_type (struct disassemble_info
*info
,
9346 enum map_type
*map_type
)
9348 /* If the symbol is in a different section, ignore it. */
9349 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
9352 return is_mapping_symbol (info
, n
, map_type
);
9355 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
9356 Returns nonzero if *MAP_TYPE was set. */
9359 get_sym_code_type (struct disassemble_info
*info
,
9361 enum map_type
*map_type
)
9363 elf_symbol_type
*es
;
9366 /* If the symbol is in a different section, ignore it. */
9367 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
9370 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
9371 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
9373 /* If the symbol has function type then use that. */
9374 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
9376 if (ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
9377 == ST_BRANCH_TO_THUMB
)
9378 *map_type
= MAP_THUMB
;
9380 *map_type
= MAP_ARM
;
9387 /* Search the mapping symbol state for instruction at pc. This is only
9388 applicable for elf target.
9390 There is an assumption Here, info->private_data contains the correct AND
9391 up-to-date information about current scan process. The information will be
9392 used to speed this search process.
9394 Return TRUE if the mapping state can be determined, and map_symbol
9395 will be updated accordingly. Otherwise, return FALSE. */
9398 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
9399 enum map_type
*map_symbol
)
9401 bfd_vma addr
, section_vma
= 0;
9402 int n
, last_sym
= -1;
9403 bfd_boolean found
= FALSE
;
9404 bfd_boolean can_use_search_opt_p
= FALSE
;
9406 /* Default to DATA. A text section is required by the ABI to contain an
9407 INSN mapping symbol at the start. A data section has no such
9408 requirement, hence if no mapping symbol is found the section must
9409 contain only data. This however isn't very useful if the user has
9410 fully stripped the binaries. If this is the case use the section
9411 attributes to determine the default. If we have no section default to
9412 INSN as well, as we may be disassembling some raw bytes on a baremetal
9413 HEX file or similar. */
9414 enum map_type type
= MAP_DATA
;
9415 if ((info
->section
&& info
->section
->flags
& SEC_CODE
) || !info
->section
)
9417 struct arm_private_data
*private_data
;
9419 if (info
->private_data
== NULL
9420 || bfd_asymbol_flavour (*info
->symtab
) != bfd_target_elf_flavour
)
9423 private_data
= info
->private_data
;
9425 /* First, look for mapping symbols. */
9426 if (info
->symtab_size
!= 0)
9428 if (pc
<= private_data
->last_mapping_addr
)
9429 private_data
->last_mapping_sym
= -1;
9431 /* Start scanning at the start of the function, or wherever
9432 we finished last time. */
9433 n
= info
->symtab_pos
+ 1;
9435 /* If the last stop offset is different from the current one it means we
9436 are disassembling a different glob of bytes. As such the optimization
9437 would not be safe and we should start over. */
9438 can_use_search_opt_p
9439 = private_data
->last_mapping_sym
>= 0
9440 && info
->stop_offset
== private_data
->last_stop_offset
;
9442 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
9443 n
= private_data
->last_mapping_sym
;
9445 /* Look down while we haven't passed the location being disassembled.
9446 The reason for this is that there's no defined order between a symbol
9447 and an mapping symbol that may be at the same address. We may have to
9448 look at least one position ahead. */
9449 for (; n
< info
->symtab_size
; n
++)
9451 addr
= bfd_asymbol_value (info
->symtab
[n
]);
9454 if (get_map_sym_type (info
, n
, &type
))
9463 n
= info
->symtab_pos
;
9464 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
9465 n
= private_data
->last_mapping_sym
;
9467 /* No mapping symbol found at this address. Look backwards
9468 for a preceeding one, but don't go pass the section start
9469 otherwise a data section with no mapping symbol can pick up
9470 a text mapping symbol of a preceeding section. The documentation
9471 says section can be NULL, in which case we will seek up all the
9474 section_vma
= info
->section
->vma
;
9478 addr
= bfd_asymbol_value (info
->symtab
[n
]);
9479 if (addr
< section_vma
)
9482 if (get_map_sym_type (info
, n
, &type
))
9492 /* If no mapping symbol was found, try looking up without a mapping
9493 symbol. This is done by walking up from the current PC to the nearest
9494 symbol. We don't actually have to loop here since symtab_pos will
9495 contain the nearest symbol already. */
9498 n
= info
->symtab_pos
;
9499 if (n
>= 0 && get_sym_code_type (info
, n
, &type
))
9506 private_data
->last_mapping_sym
= last_sym
;
9507 private_data
->last_type
= type
;
9508 private_data
->last_stop_offset
= info
->stop_offset
;
9514 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
9515 of the supplied arm_feature_set structure with bitmasks indicating
9516 the supported base architectures and coprocessor extensions.
9518 FIXME: This could more efficiently implemented as a constant array,
9519 although it would also be less robust. */
9522 select_arm_features (unsigned long mach
,
9523 arm_feature_set
* features
)
9525 arm_feature_set arch_fset
;
9526 const arm_feature_set fpu_any
= FPU_ANY
;
9528 #undef ARM_SET_FEATURES
9529 #define ARM_SET_FEATURES(FSET) \
9531 const arm_feature_set fset = FSET; \
9535 /* When several architecture versions share the same bfd_mach_arm_XXX value
9536 the most featureful is chosen. */
9539 case bfd_mach_arm_2
: ARM_SET_FEATURES (ARM_ARCH_V2
); break;
9540 case bfd_mach_arm_2a
: ARM_SET_FEATURES (ARM_ARCH_V2S
); break;
9541 case bfd_mach_arm_3
: ARM_SET_FEATURES (ARM_ARCH_V3
); break;
9542 case bfd_mach_arm_3M
: ARM_SET_FEATURES (ARM_ARCH_V3M
); break;
9543 case bfd_mach_arm_4
: ARM_SET_FEATURES (ARM_ARCH_V4
); break;
9544 case bfd_mach_arm_4T
: ARM_SET_FEATURES (ARM_ARCH_V4T
); break;
9545 case bfd_mach_arm_5
: ARM_SET_FEATURES (ARM_ARCH_V5
); break;
9546 case bfd_mach_arm_5T
: ARM_SET_FEATURES (ARM_ARCH_V5T
); break;
9547 case bfd_mach_arm_5TE
: ARM_SET_FEATURES (ARM_ARCH_V5TE
); break;
9548 case bfd_mach_arm_XScale
: ARM_SET_FEATURES (ARM_ARCH_XSCALE
); break;
9549 case bfd_mach_arm_ep9312
:
9550 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T
,
9551 ARM_CEXT_MAVERICK
| FPU_MAVERICK
));
9553 case bfd_mach_arm_iWMMXt
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT
); break;
9554 case bfd_mach_arm_iWMMXt2
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2
); break;
9555 case bfd_mach_arm_5TEJ
: ARM_SET_FEATURES (ARM_ARCH_V5TEJ
); break;
9556 case bfd_mach_arm_6
: ARM_SET_FEATURES (ARM_ARCH_V6
); break;
9557 case bfd_mach_arm_6KZ
: ARM_SET_FEATURES (ARM_ARCH_V6KZ
); break;
9558 case bfd_mach_arm_6T2
: ARM_SET_FEATURES (ARM_ARCH_V6KZT2
); break;
9559 case bfd_mach_arm_6K
: ARM_SET_FEATURES (ARM_ARCH_V6K
); break;
9560 case bfd_mach_arm_7
: ARM_SET_FEATURES (ARM_ARCH_V7VE
); break;
9561 case bfd_mach_arm_6M
: ARM_SET_FEATURES (ARM_ARCH_V6M
); break;
9562 case bfd_mach_arm_6SM
: ARM_SET_FEATURES (ARM_ARCH_V6SM
); break;
9563 case bfd_mach_arm_7EM
: ARM_SET_FEATURES (ARM_ARCH_V7EM
); break;
9564 case bfd_mach_arm_8
:
9566 /* Add bits for extensions that Armv8.5-A recognizes. */
9567 arm_feature_set armv8_5_ext_fset
9568 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
9569 ARM_SET_FEATURES (ARM_ARCH_V8_5A
);
9570 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, armv8_5_ext_fset
);
9573 case bfd_mach_arm_8R
: ARM_SET_FEATURES (ARM_ARCH_V8R
); break;
9574 case bfd_mach_arm_8M_BASE
: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE
); break;
9575 case bfd_mach_arm_8M_MAIN
: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN
); break;
9576 case bfd_mach_arm_8_1M_MAIN
:
9577 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN
);
9580 /* If the machine type is unknown allow all architecture types and all
9582 case bfd_mach_arm_unknown
: ARM_SET_FEATURES (ARM_FEATURE_ALL
); break;
9586 #undef ARM_SET_FEATURES
9588 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
9589 and thus on bfd_mach_arm_XXX value. Therefore for a given
9590 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
9591 ARM_MERGE_FEATURE_SETS (*features
, arch_fset
, fpu_any
);
9595 /* NOTE: There are no checks in these routines that
9596 the relevant number of data bytes exist. */
9599 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bfd_boolean little
)
9604 int is_thumb
= FALSE
;
9605 int is_data
= FALSE
;
9607 unsigned int size
= 4;
9608 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
9609 bfd_boolean found
= FALSE
;
9610 struct arm_private_data
*private_data
;
9612 if (info
->disassembler_options
)
9614 parse_arm_disassembler_options (info
->disassembler_options
);
9616 /* To avoid repeated parsing of these options, we remove them here. */
9617 info
->disassembler_options
= NULL
;
9620 /* PR 10288: Control which instructions will be disassembled. */
9621 if (info
->private_data
== NULL
)
9623 static struct arm_private_data
private;
9625 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
9626 /* If the user did not use the -m command line switch then default to
9627 disassembling all types of ARM instruction.
9629 The info->mach value has to be ignored as this will be based on
9630 the default archictecture for the target and/or hints in the notes
9631 section, but it will never be greater than the current largest arm
9632 machine value (iWMMXt2), which is only equivalent to the V5TE
9633 architecture. ARM architectures have advanced beyond the machine
9634 value encoding, and these newer architectures would be ignored if
9635 the machine value was used.
9637 Ie the -m switch is used to restrict which instructions will be
9638 disassembled. If it is necessary to use the -m switch to tell
9639 objdump that an ARM binary is being disassembled, eg because the
9640 input is a raw binary file, but it is also desired to disassemble
9641 all ARM instructions then use "-marm". This will select the
9642 "unknown" arm architecture which is compatible with any ARM
9644 info
->mach
= bfd_mach_arm_unknown
;
9646 /* Compute the architecture bitmask from the machine number.
9647 Note: This assumes that the machine number will not change
9648 during disassembly.... */
9649 select_arm_features (info
->mach
, & private.features
);
9651 private.last_mapping_sym
= -1;
9652 private.last_mapping_addr
= 0;
9653 private.last_stop_offset
= 0;
9655 info
->private_data
= & private;
9658 private_data
= info
->private_data
;
9660 /* Decide if our code is going to be little-endian, despite what the
9661 function argument might say. */
9662 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
9664 /* For ELF, consult the symbol table to determine what kind of code
9666 if (info
->symtab_size
!= 0
9667 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
9672 enum map_type type
= MAP_ARM
;
9674 found
= mapping_symbol_for_insn (pc
, info
, &type
);
9675 last_sym
= private_data
->last_mapping_sym
;
9677 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
9678 is_data
= (private_data
->last_type
== MAP_DATA
);
9680 /* Look a little bit ahead to see if we should print out
9681 two or four bytes of data. If there's a symbol,
9682 mapping or otherwise, after two bytes then don't
9686 size
= 4 - (pc
& 3);
9687 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
9689 addr
= bfd_asymbol_value (info
->symtab
[n
]);
9691 && (info
->section
== NULL
9692 || info
->section
== info
->symtab
[n
]->section
))
9694 if (addr
- pc
< size
)
9699 /* If the next symbol is after three bytes, we need to
9700 print only part of the data, so that we can use either
9703 size
= (pc
& 1) ? 1 : 2;
9707 if (info
->symbols
!= NULL
)
9709 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
9711 coff_symbol_type
* cs
;
9713 cs
= coffsymbol (*info
->symbols
);
9714 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
9715 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
9716 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
9717 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
9718 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
9720 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
9723 /* If no mapping symbol has been found then fall back to the type
9724 of the function symbol. */
9725 elf_symbol_type
* es
;
9728 es
= *(elf_symbol_type
**)(info
->symbols
);
9729 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
9732 ((ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
9733 == ST_BRANCH_TO_THUMB
) || type
== STT_ARM_16BIT
);
9735 else if (bfd_asymbol_flavour (*info
->symbols
)
9736 == bfd_target_mach_o_flavour
)
9738 bfd_mach_o_asymbol
*asym
= (bfd_mach_o_asymbol
*)*info
->symbols
;
9740 is_thumb
= (asym
->n_desc
& BFD_MACH_O_N_ARM_THUMB_DEF
);
9748 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
9750 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
9752 info
->bytes_per_line
= 4;
9754 /* PR 10263: Disassemble data if requested to do so by the user. */
9755 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
9759 /* Size was already set above. */
9760 info
->bytes_per_chunk
= size
;
9761 printer
= print_insn_data
;
9763 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
9766 for (i
= size
- 1; i
>= 0; i
--)
9767 given
= b
[i
] | (given
<< 8);
9769 for (i
= 0; i
< (int) size
; i
++)
9770 given
= b
[i
] | (given
<< 8);
9774 /* In ARM mode endianness is a straightforward issue: the instruction
9775 is four bytes long and is either ordered 0123 or 3210. */
9776 printer
= print_insn_arm
;
9777 info
->bytes_per_chunk
= 4;
9780 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
9782 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | (b
[3] << 24);
9784 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | (b
[0] << 24);
9788 /* In Thumb mode we have the additional wrinkle of two
9789 instruction lengths. Fortunately, the bits that determine
9790 the length of the current instruction are always to be found
9791 in the first two bytes. */
9792 printer
= print_insn_thumb16
;
9793 info
->bytes_per_chunk
= 2;
9796 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
9798 given
= (b
[0]) | (b
[1] << 8);
9800 given
= (b
[1]) | (b
[0] << 8);
9804 /* These bit patterns signal a four-byte Thumb
9806 if ((given
& 0xF800) == 0xF800
9807 || (given
& 0xF800) == 0xF000
9808 || (given
& 0xF800) == 0xE800)
9810 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
9812 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
9814 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
9816 printer
= print_insn_thumb32
;
9821 if (ifthen_address
!= pc
)
9822 find_ifthen_state (pc
, info
, little_code
);
9826 if ((ifthen_state
& 0xf) == 0x8)
9827 ifthen_next_state
= 0;
9829 ifthen_next_state
= (ifthen_state
& 0xe0)
9830 | ((ifthen_state
& 0xf) << 1);
9836 info
->memory_error_func (status
, pc
, info
);
9839 if (info
->flags
& INSN_HAS_RELOC
)
9840 /* If the instruction has a reloc associated with it, then
9841 the offset field in the instruction will actually be the
9842 addend for the reloc. (We are using REL type relocs).
9843 In such cases, we can ignore the pc when computing
9844 addresses, since the addend is not currently pc-relative. */
9847 printer (pc
, info
, given
);
9851 ifthen_state
= ifthen_next_state
;
9852 ifthen_address
+= size
;
9858 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
9860 /* Detect BE8-ness and record it in the disassembler info. */
9861 if (info
->flavour
== bfd_target_elf_flavour
9862 && info
->section
!= NULL
9863 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
9864 info
->endian_code
= BFD_ENDIAN_LITTLE
;
9866 return print_insn (pc
, info
, FALSE
);
9870 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
9872 return print_insn (pc
, info
, TRUE
);
9875 const disasm_options_and_args_t
*
9876 disassembler_options_arm (void)
9878 static disasm_options_and_args_t
*opts_and_args
;
9880 if (opts_and_args
== NULL
)
9882 disasm_options_t
*opts
;
9885 opts_and_args
= XNEW (disasm_options_and_args_t
);
9886 opts_and_args
->args
= NULL
;
9888 opts
= &opts_and_args
->options
;
9889 opts
->name
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
9890 opts
->description
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
9892 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
9894 opts
->name
[i
] = regnames
[i
].name
;
9895 if (regnames
[i
].description
!= NULL
)
9896 opts
->description
[i
] = _(regnames
[i
].description
);
9898 opts
->description
[i
] = NULL
;
9900 /* The array we return must be NULL terminated. */
9901 opts
->name
[i
] = NULL
;
9902 opts
->description
[i
] = NULL
;
9905 return opts_and_args
;
9909 print_arm_disassembler_options (FILE *stream
)
9911 unsigned int i
, max_len
= 0;
9912 fprintf (stream
, _("\n\
9913 The following ARM specific disassembler options are supported for use with\n\
9914 the -M switch:\n"));
9916 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
9918 unsigned int len
= strlen (regnames
[i
].name
);
9923 for (i
= 0, max_len
++; i
< NUM_ARM_OPTIONS
; i
++)
9924 fprintf (stream
, " %s%*c %s\n",
9926 (int)(max_len
- strlen (regnames
[i
].name
)), ' ',
9927 _(regnames
[i
].description
));