opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright (C) 1994-2019 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   4    Modification by James G. Smith (jsmith@cygnus.co.uk)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24
  25 #include "disassemble.h"
  26 #include "opcode/arm.h"
  27 #include "opintl.h"
  28 #include "safe-ctype.h"
  29 #include "libiberty.h"
  30 #include "floatformat.h"
  31
  32 /* FIXME: This shouldn't be done here.  */
  33 #include "coff/internal.h"
  34 #include "libcoff.h"
  35 #include "bfd.h"
  36 #include "elf-bfd.h"
  37 #include "elf/internal.h"
  38 #include "elf/arm.h"
  39 #include "mach-o.h"
  40
  41 /* FIXME: Belongs in global header.  */
  42 #ifndef strneq
  43 #define strneq(a,b,n)   (strncmp ((a), (b), (n)) == 0)
  44 #endif
  45
  46 /* Cached mapping symbol state.  */
  47 enum map_type
  48 {
  49   MAP_ARM,
  50   MAP_THUMB,
  51   MAP_DATA
  52 };
  53
  54 struct arm_private_data
  55 {
  56   /* The features to use when disassembling optional instructions.  */
  57   arm_feature_set features;
  58
  59   /* Track the last type (although this doesn't seem to be useful) */
  60   enum map_type last_type;
  61
  62   /* Tracking symbol table information */
  63   int last_mapping_sym;
  64
  65   /* The end range of the current range being disassembled.  */
  66   bfd_vma last_stop_offset;
  67   bfd_vma last_mapping_addr;
  68 };
  69
  70 struct opcode32
  71 {
  72   arm_feature_set arch;         /* Architecture defining this insn.  */
  73   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
  74   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
  75   const char *  assembler;      /* How to disassemble this insn.  */
  76 };
  77
  78 struct opcode16
  79 {
  80   arm_feature_set arch;         /* Architecture defining this insn.  */
  81   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
  82   const char *assembler;        /* How to disassemble this insn.  */
  83 };
  84
  85 /* print_insn_coprocessor recognizes the following format control codes:
  86
  87    %%                   %
  88
  89    %c                   print condition code (always bits 28-31 in ARM mode)
  90    %q                   print shifter argument
  91    %u                   print condition code (unconditional in ARM mode,
  92                           UNPREDICTABLE if not AL in Thumb)
  93    %A                   print address for ldc/stc/ldf/stf instruction
  94    %B                   print vstm/vldm register list
  95    %I                   print cirrus signed shift immediate: bits 0..3|4..6
  96    %F                   print the COUNT field of a LFM/SFM instruction.
  97    %P                   print floating point precision in arithmetic insn
  98    %Q                   print floating point precision in ldf/stf insn
  99    %R                   print floating point rounding mode
 100
 101    %<bitfield>c         print as a condition code (for vsel)
 102    %<bitfield>r         print as an ARM register
 103    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 104    %<bitfield>ru        as %<>r but each u register must be unique.
 105    %<bitfield>d         print the bitfield in decimal
 106    %<bitfield>k         print immediate for VFPv3 conversion instruction
 107    %<bitfield>x         print the bitfield in hex
 108    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 109    %<bitfield>f         print a floating point constant if >7 else a
 110                         floating point register
 111    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 112    %<bitfield>g         print as an iWMMXt 64-bit register
 113    %<bitfield>G         print as an iWMMXt general purpose or control register
 114    %<bitfield>D         print as a NEON D register
 115    %<bitfield>Q         print as a NEON Q register
 116    %<bitfield>V         print as a NEON D or Q register
 117    %<bitfield>E         print a quarter-float immediate value
 118
 119    %y<code>             print a single precision VFP reg.
 120                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 121    %z<code>             print a double precision VFP reg
 122                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 123
 124    %<bitfield>'c        print specified char iff bitfield is all ones
 125    %<bitfield>`c        print specified char iff bitfield is all zeroes
 126    %<bitfield>?ab...    select from array of values in big endian order
 127
 128    %L                   print as an iWMMXt N/M width field.
 129    %Z                   print the Immediate of a WSHUFH instruction.
 130    %l                   like 'A' except use byte offsets for 'B' & 'H'
 131                         versions.
 132    %i                   print 5-bit immediate in bits 8,3..0
 133                         (print "32" when 0)
 134    %r                   print register offset address for wldt/wstr instruction.  */
 135
 136 enum opcode_sentinel_enum
 137 {
 138   SENTINEL_IWMMXT_START = 1,
 139   SENTINEL_IWMMXT_END,
 140   SENTINEL_GENERIC_START
 141 } opcode_sentinels;
 142
 143 #define UNDEFINED_INSTRUCTION      "\t\t; <UNDEFINED> instruction: %0-31x"
 144 #define UNKNOWN_INSTRUCTION_32BIT  "\t\t; <UNDEFINED> instruction: %08x"
 145 #define UNKNOWN_INSTRUCTION_16BIT  "\t\t; <UNDEFINED> instruction: %04x"
 146 #define UNPREDICTABLE_INSTRUCTION  "\t; <UNPREDICTABLE>"
 147
 148 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 149
 150 static const struct opcode32 coprocessor_opcodes[] =
 151 {
 152   /* XScale instructions.  */
 153   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 154     0x0e200010, 0x0fff0ff0,
 155     "mia%c\tacc0, %0-3r, %12-15r"},
 156   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 157     0x0e280010, 0x0fff0ff0,
 158     "miaph%c\tacc0, %0-3r, %12-15r"},
 159   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 160     0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 161   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 162     0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 163   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 164     0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 165
 166   /* Intel Wireless MMX technology instructions.  */
 167   {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
 168   {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
 169     0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 170   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 171     0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 172   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 173     0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 174   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 175     0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 176   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 177     0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 178   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 179     0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 180   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 181     0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 182   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 183     0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 184   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 185     0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 186   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 187     0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 188   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 189     0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 190   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 191     0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 192   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 193     0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 194   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 195     0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 196   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 197     0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 198   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 199     0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 200   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 201     0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 202   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 203     0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 204   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 205     0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 206   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 207     0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 208   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 209     0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 210   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 211     0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 212   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 213     0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 214   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 215     0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 216   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 217     0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 218   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 219     0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 220   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 221     0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 222   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 223     0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 224   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 225     0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 226   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 227     0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 228   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 229     0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 230   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 231     0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 232   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 233     0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 234   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 235     0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 236   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 237     0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
 238   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 239     0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 240   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 241     0x0e800120, 0x0f800ff0,
 242     "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 243   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 244     0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 245   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 246     0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 247   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 248     0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 249   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 250     0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 251   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 252     0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 253   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 254     0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 255   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 256     0x0e8000a0, 0x0f800ff0,
 257     "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 258   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 259     0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 260   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 261     0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 262   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 263     0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 264   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 265     0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 266   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 267     0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
 268   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 269     0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 270   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 271     0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 272   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 273     0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 274   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 275     0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 276   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 277     0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
 278   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 279     0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 280   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 281     0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 282   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 283     0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
 284   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 285     0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 286   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 287     0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 288   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 289     0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
 290   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 291     0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 292   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 293     0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 294   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 295     0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 296   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 297     0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 298   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 299     0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 300   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 301     0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 302   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 303     0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 304   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 305     0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 306   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 307     0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 308   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 309     0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 310   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 311     0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 312   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 313     0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 314   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 315     0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 316   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 317     0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 318   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 319     0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 320   {ARM_FEATURE_CORE_LOW (0),
 321     SENTINEL_IWMMXT_END, 0, "" },
 322
 323   /* Floating point coprocessor (FPA) instructions.  */
 324   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 325     0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 326   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 327     0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 328   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 329     0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 330   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 331     0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 332   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 333     0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 334   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 335     0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 336   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 337     0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 338   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 339     0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 340   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 341     0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 342   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 343     0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 344   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 345     0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 346   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 347     0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 348   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 349     0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 350   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 351     0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 352   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 353     0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 354   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 355     0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 356   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 357     0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 358   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 359     0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 360   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 361     0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 362   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 363     0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 364   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 365     0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 366   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 367     0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 368   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 369     0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 370   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 371     0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 372   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 373     0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 374   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 375     0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 376   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 377     0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 378   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 379     0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 380   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 381     0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 382   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 383     0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 384   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 385     0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 386   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 387     0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 388   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 389     0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 390   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 391     0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 392   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 393     0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 394   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 395     0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 396   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 397     0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 398   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 399     0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 400   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 401     0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 402   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 403     0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 404   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 405     0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 406   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 407     0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 408   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 409     0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 410
 411   /* ARMv8-M Mainline Security Extensions instructions.  */
 412   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 413     0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
 414   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 415     0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
 416
 417   /* Register load/store.  */
 418   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 419     0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 420   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 421     0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 422   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 423     0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 424   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 425     0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 426   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 427     0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 428   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 429     0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 430   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 431     0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 432   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 433     0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 434   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 435     0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 436   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 437     0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 438   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 439     0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 440   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 441     0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 442   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 443     0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 444   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 445     0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 446   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 447     0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 448   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 449     0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 450
 451   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 452     0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 453   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 454     0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 455   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 456     0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 457   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 458     0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 459
 460   /* Data transfer between ARM and NEON registers.  */
 461   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 462     0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
 463   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 464     0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
 465   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 466     0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
 467   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 468     0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
 469   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 470     0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
 471   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 472     0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
 473   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 474     0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 475   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 476     0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 477   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 478     0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
 479   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 480     0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
 481   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 482     0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
 483   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 484     0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
 485   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 486     0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
 487   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 488     0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 489   /* Half-precision conversion instructions.  */
 490   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 491     0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
 492   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 493     0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
 494   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 495     0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 496   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 497     0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 498
 499   /* Floating point coprocessor (VFP) instructions.  */
 500   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 501     0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
 502   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 503     0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
 504   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 505     0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
 506   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 507     0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
 508   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 509     0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
 510   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 511     0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
 512   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 513     0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
 514   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 515     0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
 516   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 517     0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
 518   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 519     0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
 520   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 521     0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
 522   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 523     0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
 524   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 525     0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
 526   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 527     0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
 528   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 529     0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
 530   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 531     0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
 532   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 533     0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
 534   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 535     0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
 536   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 537     0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
 538   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 539     0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 540   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 541     0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 542   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 543     0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 544   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 545     0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 546   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 547     0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
 548   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 549     0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
 550   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 551     0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 552   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 553     0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 554   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 555     0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 556   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 557     0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 558   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 559     0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 560   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 561     0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 562   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 563     0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 564   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 565     0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 566   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 567     0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 568   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 569     0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 570   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 571     0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 572   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 573     0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 574   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 575     0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 576   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 577     0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 578   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 579     0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 580   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 581     0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
 582   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 583     0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 584   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 585     0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 586   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 587     0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
 588   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 589     0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
 590   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 591     0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 592   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 593     0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
 594   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 595     0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
 596   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 597     0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
 598   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 599     0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
 600   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 601     0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
 602   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 603     0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
 604   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 605     0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
 606   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 607     0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
 608   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 609     0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
 610   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 611     0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
 612   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 613     0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
 614   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 615     0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
 616   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 617     0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
 618   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 619     0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
 620   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 621     0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
 622   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 623     0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
 624   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 625     0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
 626   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 627     0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
 628   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 629     0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
 630   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 631     0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
 632   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 633     0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
 634   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 635     0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
 636   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 637     0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
 638
 639   /* Cirrus coprocessor instructions.  */
 640   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 641     0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 642   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 643     0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 644   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 645     0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 646   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 647     0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 648   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 649     0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 650   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 651     0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 652   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 653     0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 654   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 655     0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 656   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 657     0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 658   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 659     0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 660   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 661     0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 662   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 663     0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 664   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 665     0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 666   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 667     0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 668   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 669     0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 670   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 671     0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 672   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 673     0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
 674   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 675     0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
 676   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 677     0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
 678   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 679     0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
 680   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 681     0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
 682   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 683     0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
 684   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 685     0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
 686   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 687     0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
 688   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 689     0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
 690   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 691     0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
 692   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 693     0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
 694   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 695     0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
 696   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 697     0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
 698   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 699     0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
 700   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 701     0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
 702   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 703     0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
 704   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 705     0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
 706   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 707     0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
 708   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 709     0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
 710   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 711     0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
 712   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 713     0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
 714   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 715     0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
 716   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 717     0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
 718   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 719     0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
 720   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 721     0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
 722   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 723     0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
 724   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 725     0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
 726   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 727     0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
 728   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 729     0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
 730   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 731     0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
 732   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 733     0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
 734   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 735     0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
 736   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 737     0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
 738   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 739     0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
 740   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 741     0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
 742   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 743     0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
 744   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 745     0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
 746   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 747     0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
 748   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 749     0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
 750   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 751     0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
 752   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 753     0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
 754   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 755     0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
 756   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 757     0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
 758   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 759     0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
 760   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 761     0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
 762   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 763     0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
 764   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 765     0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 766   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 767     0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 768   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 769     0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 770   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 771     0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 772   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 773     0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 774   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 775     0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 776   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 777     0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
 778   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 779     0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
 780   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 781     0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
 782   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 783     0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
 784   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 785     0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 786   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 787     0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 788   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 789     0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 790   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 791     0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 792   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 793     0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 794   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 795     0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 796   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 797     0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 798   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 799     0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 800   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 801     0x0e000600, 0x0ff00f10,
 802     "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 803   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 804     0x0e100600, 0x0ff00f10,
 805     "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 806   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 807     0x0e200600, 0x0ff00f10,
 808     "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 809   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 810     0x0e300600, 0x0ff00f10,
 811     "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 812
 813   /* VFP Fused multiply add instructions.  */
 814   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 815     0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
 816   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 817     0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
 818   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 819     0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
 820   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 821     0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
 822   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 823     0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
 824   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 825     0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
 826   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 827     0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
 828   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 829     0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
 830
 831   /* FP v5.  */
 832   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 833     0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
 834   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 835     0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
 836   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 837     0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
 838   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 839     0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
 840   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 841     0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
 842   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 843     0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
 844   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 845     0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
 846   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 847     0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
 848   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 849     0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
 850   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 851     0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
 852   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 853     0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
 854   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 855     0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
 856
 857   /* Generic coprocessor instructions.  */
 858   {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
 859   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 860     0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
 861   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 862     0x0c500000, 0x0ff00000,
 863     "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 864   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 865     0x0e000000, 0x0f000010,
 866     "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 867   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 868     0x0e10f010, 0x0f10f010,
 869     "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
 870   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 871     0x0e100010, 0x0f100010,
 872     "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 873   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 874     0x0e000010, 0x0f100010,
 875     "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 877     0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
 878   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 879     0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
 880
 881   /* V6 coprocessor instructions.  */
 882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 883     0xfc500000, 0xfff00000,
 884     "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 885   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 886     0xfc400000, 0xfff00000,
 887     "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
 888
 889   /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8.  */
 890   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 891     0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 892   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 893     0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 894   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 895     0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 896   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 897     0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 898   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 899     0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 900   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 901     0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 902   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 903     0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
 904   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 905     0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
 906   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 907     0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
 908   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 909     0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
 910
 911   /* Dot Product instructions in the space of coprocessor 13.  */
 912   {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
 913     0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
 914   {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
 915     0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
 916
 917   /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8.  */
 918   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 919     0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
 920   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 921     0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
 922   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 923     0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
 924   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 925     0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
 926   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 927     0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
 928   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 929     0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
 930   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 931     0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
 932   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 933     0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
 934
 935   /* V5 coprocessor instructions.  */
 936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 937     0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 939     0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 940   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 941     0xfe000000, 0xff000010,
 942     "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 943   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 944     0xfe000010, 0xff100010,
 945     "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 947     0xfe100010, 0xff100010,
 948     "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 949
 950   /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
 951      cp_num: bit <11:8> == 0b1001.
 952      cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
 953   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 954     0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
 955   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 956     0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
 957   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 958     0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
 959   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 960     0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
 961   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 962     0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 963   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 964     0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
 965   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 966     0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
 967   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 968     0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
 969   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 970     0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
 971   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 972     0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
 973   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 974     0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
 975   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 976     0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
 977   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 978     0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
 979   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 980     0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
 981   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 982     0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
 983   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 984     0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
 985   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 986     0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
 987   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 988     0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
 989   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 990     0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
 991   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 992     0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
 993   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 994     0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
 995   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 996     0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
 997   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 998     0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
 999   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1000     0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1001   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1002     0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1003   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1004     0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1005   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1006     0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1007   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1008     0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1009   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1010     0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1011   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1012     0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1013   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1014     0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1015   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1016     0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1017   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1018     0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1019   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1020     0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1021   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1022     0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1023
1024   /* ARMv8.3 javascript conversion instruction.  */
1025   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1026     0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1027
1028   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1029 };
1030
1031 /* Neon opcode table:  This does not encode the top byte -- that is
1032    checked by the print_insn_neon routine, as it depends on whether we are
1033    doing thumb32 or arm32 disassembly.  */
1034
1035 /* print_insn_neon recognizes the following format control codes:
1036
1037    %%                   %
1038
1039    %c                   print condition code
1040    %u                   print condition code (unconditional in ARM mode,
1041                           UNPREDICTABLE if not AL in Thumb)
1042    %A                   print v{st,ld}[1234] operands
1043    %B                   print v{st,ld}[1234] any one operands
1044    %C                   print v{st,ld}[1234] single->all operands
1045    %D                   print scalar
1046    %E                   print vmov, vmvn, vorr, vbic encoded constant
1047    %F                   print vtbl,vtbx register list
1048
1049    %<bitfield>r         print as an ARM register
1050    %<bitfield>d         print the bitfield in decimal
1051    %<bitfield>e         print the 2^N - bitfield in decimal
1052    %<bitfield>D         print as a NEON D register
1053    %<bitfield>Q         print as a NEON Q register
1054    %<bitfield>R         print as a NEON D or Q register
1055    %<bitfield>Sn        print byte scaled width limited by n
1056    %<bitfield>Tn        print short scaled width limited by n
1057    %<bitfield>Un        print long scaled width limited by n
1058
1059    %<bitfield>'c        print specified char iff bitfield is all ones
1060    %<bitfield>`c        print specified char iff bitfield is all zeroes
1061    %<bitfield>?ab...    select from array of values in big endian order.  */
1062
1063 static const struct opcode32 neon_opcodes[] =
1064 {
1065   /* Extract.  */
1066   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1067     0xf2b00840, 0xffb00850,
1068     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1069   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1070     0xf2b00000, 0xffb00810,
1071     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1072
1073   /* Move data element to all lanes.  */
1074   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075     0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1076   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077     0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1078   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1079     0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1080
1081   /* Table lookup.  */
1082   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083     0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1084   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1085     0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1086
1087   /* Half-precision conversions.  */
1088   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1089     0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1090   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1091     0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1092
1093   /* NEON fused multiply add instructions.  */
1094   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1095     0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1096   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1097     0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1098   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1099     0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1100   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1101     0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1102
1103   /* Two registers, miscellaneous.  */
1104   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1105     0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1106   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1107     0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1108   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1109     0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1110   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1111     0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1112   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1113     0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1114   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1115     0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1116   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1117     0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1118   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1119     0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1120   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1121     0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1122   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1123     0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1124   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1125     0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1126   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127     0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1128   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1129     0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1130   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1131     0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1132   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1133     0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1134   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1135     0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1136   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1137     0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1138   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1139     0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1140   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1141     0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1142   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1143     0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1144   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1145     0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1146   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1147     0xf3b20300, 0xffb30fd0,
1148     "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1149   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1150     0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1151   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1152     0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1153   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1154     0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1155   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1156     0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1157   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158     0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1159   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1160     0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1161   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162     0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1163   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164     0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1165   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1166     0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1167   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1168     0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1169   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170     0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1171   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1172     0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1173   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174     0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1175   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176     0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1177   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1178     0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1179   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1180     0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1181   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1182     0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1183   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1184     0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1185   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1186     0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1187   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1188     0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1189   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1190     0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1191   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1192     0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1193   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1194     0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1195   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1196     0xf3bb0600, 0xffbf0e10,
1197     "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1198   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1199     0xf3b70600, 0xffbf0e10,
1200     "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1201
1202   /* Three registers of the same length.  */
1203   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1204     0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1205   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1206     0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1207   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1208     0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1209   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1210     0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1211   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1212     0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1213   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1214     0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1215   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1216     0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1217   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1218     0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1219   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1220     0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1221   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1222     0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1223   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1224     0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1225   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226     0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1227   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1228     0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1229   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230     0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1231   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1232     0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1233   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1234     0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1235   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1236     0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1237   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238     0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1239   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1240     0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1241   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1242     0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1243   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1244     0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1245   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1246     0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1247   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1248     0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1249   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1250     0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1251   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1252     0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1253   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1254     0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1255   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1256     0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1257   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1258     0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1259   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1260     0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1261   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1262     0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1263   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1264     0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1265   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1266     0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1267   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1268     0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1269   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1270     0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1271   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1272     0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1273   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274     0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1275   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1276     0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1277   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278     0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1279   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1280     0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1281   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282     0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1283   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1284     0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1285   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286     0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1287   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1288     0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1289   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290     0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1291   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1292     0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1293   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294     0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1295   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1296     0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1297   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298     0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1299   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1300     0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1301   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302     0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1303   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1304     0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1305   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306     0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1307   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1308     0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1309   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310     0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1311   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1312     0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1313   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314     0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1315   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1316     0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1317   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318     0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1319   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320     0xf2000b00, 0xff800f10,
1321     "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1322   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323     0xf2000b10, 0xff800f10,
1324     "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1325   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326     0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1327   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1328     0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1329   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1330     0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1331   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1332     0xf3000b00, 0xff800f10,
1333     "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1334   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335     0xf2000000, 0xfe800f10,
1336     "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1337   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1338     0xf2000010, 0xfe800f10,
1339     "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1340   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341     0xf2000100, 0xfe800f10,
1342     "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1343   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344     0xf2000200, 0xfe800f10,
1345     "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1346   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347     0xf2000210, 0xfe800f10,
1348     "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1349   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350     0xf2000300, 0xfe800f10,
1351     "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1352   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353     0xf2000310, 0xfe800f10,
1354     "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1355   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1356     0xf2000400, 0xfe800f10,
1357     "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1358   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1359     0xf2000410, 0xfe800f10,
1360     "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1361   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362     0xf2000500, 0xfe800f10,
1363     "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1364   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365     0xf2000510, 0xfe800f10,
1366     "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1367   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368     0xf2000600, 0xfe800f10,
1369     "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1370   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371     0xf2000610, 0xfe800f10,
1372     "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1373   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374     0xf2000700, 0xfe800f10,
1375     "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1376   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377     0xf2000710, 0xfe800f10,
1378     "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1379   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380     0xf2000910, 0xfe800f10,
1381     "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1382   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383     0xf2000a00, 0xfe800f10,
1384     "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1385   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386     0xf2000a10, 0xfe800f10,
1387     "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1388   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1389     0xf3000b10, 0xff800f10,
1390     "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1391   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1392     0xf3000c10, 0xff800f10,
1393     "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1394
1395   /* One register and an immediate value.  */
1396   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397     0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1398   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399     0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1400   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401     0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1402   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403     0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1404   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405     0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1406   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407     0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1408   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409     0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1410   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411     0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1412   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413     0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1414   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415     0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1416   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417     0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1418   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419     0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1420   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421     0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1422
1423   /* Two registers and a shift amount.  */
1424   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425     0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1426   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427     0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1428   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429     0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1430   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431     0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1432   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433     0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1434   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435     0xf2880950, 0xfeb80fd0,
1436     "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1437   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438     0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1439   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440     0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1441   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442     0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1443   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444     0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1445   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446     0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1447   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448     0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1449   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450     0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1451   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452     0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1453   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454     0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1455   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456     0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1457   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1458     0xf2900950, 0xfeb00fd0,
1459     "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1460   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461     0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1462   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463     0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1464   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465     0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1466   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467     0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1468   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469     0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1470   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471     0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1472   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473     0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1474   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475     0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1476   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477     0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1478   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479     0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1480   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481     0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1482   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483     0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1484   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485     0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1486   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487     0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1488   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489     0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1490   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491     0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1492   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493     0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1494   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495     0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1496   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497     0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1498   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499     0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1500   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501     0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1502   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503     0xf2a00950, 0xfea00fd0,
1504     "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1505   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506     0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1507   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508     0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1509   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510     0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1511   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512     0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1513   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514     0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1515   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516     0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1517   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518     0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1519   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520     0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1521   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522     0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1523   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524     0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1525   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526     0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1527   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528     0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1529   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530     0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1531   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532     0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1533   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534     0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1535   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536     0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1537   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538     0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1539   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540     0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1541   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542     0xf2a00e10, 0xfea00e90,
1543     "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1544   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1545     0xf2a00c10, 0xfea00e90,
1546     "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1547
1548   /* Three registers of different lengths.  */
1549   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1550     0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1551   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552     0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1553   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554     0xf2800400, 0xff800f50,
1555     "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1556   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557     0xf2800600, 0xff800f50,
1558     "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1559   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560     0xf2800900, 0xff800f50,
1561     "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1562   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1563     0xf2800b00, 0xff800f50,
1564     "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1565   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566     0xf2800d00, 0xff800f50,
1567     "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1568   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569     0xf3800400, 0xff800f50,
1570     "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1571   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572     0xf3800600, 0xff800f50,
1573     "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1574   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1575     0xf2800000, 0xfe800f50,
1576     "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1577   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578     0xf2800100, 0xfe800f50,
1579     "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1580   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1581     0xf2800200, 0xfe800f50,
1582     "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1583   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584     0xf2800300, 0xfe800f50,
1585     "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1586   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587     0xf2800500, 0xfe800f50,
1588     "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1589   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590     0xf2800700, 0xfe800f50,
1591     "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1592   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593     0xf2800800, 0xfe800f50,
1594     "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1595   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596     0xf2800a00, 0xfe800f50,
1597     "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1598   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599     0xf2800c00, 0xfe800f50,
1600     "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1601
1602   /* Two registers and a scalar.  */
1603   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604     0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1605   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606     0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1607   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1608     0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1609   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610     0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1611   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612     0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1613   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614     0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1615   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1616     0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1617   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618     0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1619   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620     0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1621   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622     0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1623   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1624     0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1625   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626     0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1627   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628     0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1629   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630     0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1631   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632     0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1633   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634     0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1635   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1636     0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1637   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638     0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1639   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640     0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1641   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1642     0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1643   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644     0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1645   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646     0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1647   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1648     0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1649   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650     0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1651   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652     0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1653   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654     0xf2800240, 0xfe800f50,
1655     "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1656   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1657     0xf2800640, 0xfe800f50,
1658     "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1659   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660     0xf2800a40, 0xfe800f50,
1661     "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1662   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1663     0xf2800e40, 0xff800f50,
1664    "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1665   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1666     0xf2800f40, 0xff800f50,
1667    "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1668   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1669     0xf3800e40, 0xff800f50,
1670    "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1671   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1672     0xf3800f40, 0xff800f50,
1673    "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1674   },
1675
1676   /* Element and structure load/store.  */
1677   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678     0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1679   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680     0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1681   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682     0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1683   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684     0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1685   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686     0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1687   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688     0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1689   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690     0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1691   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692     0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1693   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694     0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1695   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696     0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1697   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698     0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1699   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700     0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1701   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702     0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1703   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704     0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1705   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706     0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1707   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708     0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1709   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710     0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1711   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712     0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1713   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714     0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1715
1716   {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1717 };
1718
1719 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
1720    ordered: they must be searched linearly from the top to obtain a correct
1721    match.  */
1722
1723 /* print_insn_arm recognizes the following format control codes:
1724
1725    %%                   %
1726
1727    %a                   print address for ldr/str instruction
1728    %s                   print address for ldr/str halfword/signextend instruction
1729    %S                   like %s but allow UNPREDICTABLE addressing
1730    %b                   print branch destination
1731    %c                   print condition code (always bits 28-31)
1732    %m                   print register mask for ldm/stm instruction
1733    %o                   print operand2 (immediate or register + shift)
1734    %p                   print 'p' iff bits 12-15 are 15
1735    %t                   print 't' iff bit 21 set and bit 24 clear
1736    %B                   print arm BLX(1) destination
1737    %C                   print the PSR sub type.
1738    %U                   print barrier type.
1739    %P                   print address for pli instruction.
1740
1741    %<bitfield>r         print as an ARM register
1742    %<bitfield>T         print as an ARM register + 1
1743    %<bitfield>R         as %r but r15 is UNPREDICTABLE
1744    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1745    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1746    %<bitfield>d         print the bitfield in decimal
1747    %<bitfield>W         print the bitfield plus one in decimal
1748    %<bitfield>x         print the bitfield in hex
1749    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
1750
1751    %<bitfield>'c        print specified char iff bitfield is all ones
1752    %<bitfield>`c        print specified char iff bitfield is all zeroes
1753    %<bitfield>?ab...    select from array of values in big endian order
1754
1755    %e                   print arm SMI operand (bits 0..7,8..19).
1756    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
1757    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
1758    %R                   print the SPSR/CPSR or banked register of an MRS.  */
1759
1760 static const struct opcode32 arm_opcodes[] =
1761 {
1762   /* ARM instructions.  */
1763   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1764     0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1765   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1766     0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1767
1768   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1769     0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1770   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1771     0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1772   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1773     0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1774   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1775     0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1776   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1777     0x00800090, 0x0fa000f0,
1778     "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1779   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1780     0x00a00090, 0x0fa000f0,
1781     "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1782
1783   /* V8.2 RAS extension instructions.  */
1784   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
1785     0xe320f010, 0xffffffff, "esb"},
1786
1787   /* V8 instructions.  */
1788   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1789     0x0320f005, 0x0fffffff, "sevl"},
1790   /* Defined in V8 but is in NOP space so available to all arch.  */
1791   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1792     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1793   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
1794     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1795   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1796     0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1797   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1798     0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1799   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1800     0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1801   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1802     0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1803   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1804     0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1805   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1806     0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1807   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1808     0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1809   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1810     0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1811   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1812     0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1813   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1814     0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1815   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1816     0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1817   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1818     0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1819   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1820     0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
1821   /* CRC32 instructions.  */
1822   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1823     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1824   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1825     0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1826   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1827     0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1828   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1829     0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1830   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1831     0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1832   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1833     0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
1834
1835   /* Privileged Access Never extension instructions.  */
1836   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1837     0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1838
1839   /* Virtualization Extension instructions.  */
1840   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1841   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
1842
1843   /* Integer Divide Extension instructions.  */
1844   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1845     0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1846   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1847     0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
1848
1849   /* MP Extension instructions.  */
1850   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
1851
1852   /* Speculation Barriers.  */
1853   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
1854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
1855   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
1856
1857   /* V7 instructions.  */
1858   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1859   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1860   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1861   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1862   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1863   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1864   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
1865    {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1866     0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
1867
1868   /* ARM V6T2 instructions.  */
1869   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1870     0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1871   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1872     0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1873   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1874     0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1875   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1876     0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1877
1878   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1879     0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1881     0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1882
1883   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1884     0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1885   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1886     0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1887   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1888     0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1889   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1890     0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
1891
1892   /* ARM Security extension instructions.  */
1893   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1894     0x01600070, 0x0ff000f0, "smc%c\t%e"},
1895
1896   /* ARM V6K instructions.  */
1897   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1898     0xf57ff01f, 0xffffffff, "clrex"},
1899   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1900     0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1901   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1902     0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1903   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1904     0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1905   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1906     0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1907   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1908     0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1909   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1910     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
1911
1912   /* ARMv8.5-A instructions.  */
1913   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
1914
1915   /* ARM V6K NOP hints.  */
1916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1917     0x0320f001, 0x0fffffff, "yield%c"},
1918   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1919     0x0320f002, 0x0fffffff, "wfe%c"},
1920   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1921     0x0320f003, 0x0fffffff, "wfi%c"},
1922   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1923     0x0320f004, 0x0fffffff, "sev%c"},
1924   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1925     0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
1926
1927   /* ARM V6 instructions.  */
1928   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1929     0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1930   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1931     0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1932   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1933     0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1934   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1935     0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1937     0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1939     0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1940   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1941     0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1942   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1943     0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1944   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1945     0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1947     0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1948   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1949     0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1950   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1951     0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1952   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1953     0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1954   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1955     0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1956   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1957     0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1958   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1959     0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1960   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1961     0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1962   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1963     0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1964   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1965     0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1966   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1967     0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1968   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1969     0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1970   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1971     0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1972   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1973     0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1974   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1975     0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1976   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1977     0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1978   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1979     0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1980   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1981     0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1982   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1983     0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1984   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1985     0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1986   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1987     0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1988   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1989     0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1990   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1991     0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1992   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1993     0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1994   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1995     0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1996   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1997     0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1998   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1999     0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2000   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2001     0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2002   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2003     0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2004   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2005     0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2006   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2007     0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2008   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2009     0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2010   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2011     0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2012   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2013     0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2014   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2015     0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2016   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2017     0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2018   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2019     0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2020   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2021     0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2022   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2023     0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2024   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2025     0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2026   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2027     0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2028   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2029     0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2030   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2031     0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2032   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2033     0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2034   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2035     0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2036   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2037     0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2038   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2039     0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2040   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2041     0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2042   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2043     0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2044   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2045     0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2046   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2047     0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2048   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2049     0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2050   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2051     0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2052   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2053     0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2054   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2055     0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2056   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2057     0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2058   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2059     0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2060   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2061     0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2062   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2063     0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2064   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2065     0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2066   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2067     0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2068   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2069     0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2070   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2071     0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2072   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2073     0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2074   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2075     0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2076   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2077     0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2078   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2079     0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2080   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2081     0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2082   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2083     0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2084   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2085     0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2086   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2087     0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2088   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2089     0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2090   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2091     0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2092   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2093     0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2094   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2095     0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2096   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2097     0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2098   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2099     0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2100   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2101     0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2102   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2103     0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2105     0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2106   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2107     0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2108   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2109     0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2110   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2111     0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2112   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2113     0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2114   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2115     0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2116   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2117     0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2118   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2119     0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2120   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2121     0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2122   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2123     0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2124   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2125     0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2126   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2127     0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2128   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2129     0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2130   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2131     0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2132   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2133     0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2134   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2135     0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2136   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2137     0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2138   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2139     0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2140   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2141     0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2142   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2143     0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2144   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2145     0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2146   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2147     0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2148   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2149     0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2150   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2151     0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2152   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2153     0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2154   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2155     0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2156   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2157     0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2158   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2159     0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2160   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2161     0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2162   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2163     0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2164   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2165     0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2166   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2167     0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2168   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2169     0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2170   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2171     0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
2172
2173   /* V5J instruction.  */
2174   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2175     0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
2176
2177   /* V5 Instructions.  */
2178   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2179     0xe1200070, 0xfff000f0,
2180     "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2181   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2182     0xfa000000, 0xfe000000, "blx\t%B"},
2183   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2184     0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2185   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2186     0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2187
2188   /* V5E "El Segundo" Instructions.  */
2189   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2190     0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2191   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2192     0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2193   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2194     0xf450f000, 0xfc70f000, "pld\t%a"},
2195   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2196     0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2197   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2198     0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2199   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2200     0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2201   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2202     0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2203
2204   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2205     0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2206   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2207     0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2208
2209   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2210     0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2211   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2212     0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2213   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2214     0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2215   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2216     0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2217
2218   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2219     0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2220   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2221     0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2222   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2223     0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2224   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2225     0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2226
2227   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2228     0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2229   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2230     0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2231
2232   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2233     0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
2234   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2235     0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2236   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2237     0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
2238   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2239     0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2240
2241   /* ARM Instructions.  */
2242   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2243     0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2244
2245   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2246     0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2247   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2248     0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2249   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2250     0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2251   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2252     0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2253   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2254     0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2255   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2256     0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2257
2258   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259     0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2260   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2261     0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2262   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2263     0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2264   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2265     0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2266
2267   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2268     0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2269   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2270     0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2271   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2272     0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2273   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2274     0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2275
2276   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2277     0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2278   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2279     0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2280   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2281     0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2282
2283   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2284     0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2285   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2286     0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2287   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2288     0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2289
2290   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2291     0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2292   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2293     0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2294   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2295     0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2296
2297   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2298     0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2299   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2300     0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2301   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2302     0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2303
2304   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2305     0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2306   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2307     0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2308   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2309     0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2310
2311   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2312     0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2313   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2314     0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2315   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2316     0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2317
2318   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2319     0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2320   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2321     0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2322   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2323     0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2324
2325   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2326     0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2327   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2328     0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2329   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2330     0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2331
2332   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2333     0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2334   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2335     0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2336   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2337     0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2338
2339   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2340     0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2341   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2342     0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2343   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2344     0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2345
2346   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2347     0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2348   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2349     0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2350   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2351     0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2352
2353   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2354     0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2355   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2356     0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2357   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2358     0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2359
2360   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2361     0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2362   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2363     0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2364   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2365     0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2366
2367   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2368     0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2369   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2370     0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2371   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2372     0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2373
2374   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2375     0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2376   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2377     0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2378   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2379     0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2380   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2381     0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2382   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2383     0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2384   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2385     0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2386   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2387     0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2388
2389   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2390     0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2391   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2392     0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2393   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2394     0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2395
2396   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2397     0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2398   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2399     0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2400   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2401     0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2402
2403   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2404     0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2405   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2406     0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2407
2408   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2409     0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2410
2411   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2412     0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2413   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2414     0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2415
2416   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2417     0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2418   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2419     0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2420   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2421     0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2422   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2423     0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2424   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2425     0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2426   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2427     0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2428   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2429     0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2430   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2431     0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2432   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2433     0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2434   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2435     0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2436   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2437     0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2438   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2439     0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2440   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2441     0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2442   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2443     0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2444   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2445     0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2446   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2447     0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2448   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2449     0x092d0000, 0x0fff0000, "push%c\t%m"},
2450   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2451     0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2452   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2453     0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2454
2455   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2456     0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2457   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2458     0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2459   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2460     0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2461   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2462     0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2463   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2464     0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2465   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2466     0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2467   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2468     0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2469   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2470     0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2471   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2472     0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2473   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2474     0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2475   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2476     0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2477   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2478     0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2479   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2480     0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2481   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2482     0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2483   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2484     0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2485   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2486     0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2487   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2488     0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2489   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2490     0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2491   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2492     0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2493
2494   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2495     0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2496   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2497     0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2498
2499   /* The rest.  */
2500   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2501     0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
2502   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2503     0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2504   {ARM_FEATURE_CORE_LOW (0),
2505     0x00000000, 0x00000000, 0}
2506 };
2507
2508 /* print_insn_thumb16 recognizes the following format control codes:
2509
2510    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
2511    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
2512    %<bitfield>I         print bitfield as a signed decimal
2513                                 (top bit of range being the sign bit)
2514    %N                   print Thumb register mask (with LR)
2515    %O                   print Thumb register mask (with PC)
2516    %M                   print Thumb register mask
2517    %b                   print CZB's 6-bit unsigned branch destination
2518    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
2519    %c                   print the condition code
2520    %C                   print the condition code, or "s" if not conditional
2521    %x                   print warning if conditional an not at end of IT block"
2522    %X                   print "\t; unpredictable <IT:code>" if conditional
2523    %I                   print IT instruction suffix and operands
2524    %W                   print Thumb Writeback indicator for LDMIA
2525    %<bitfield>r         print bitfield as an ARM register
2526    %<bitfield>d         print bitfield as a decimal
2527    %<bitfield>H         print (bitfield * 2) as a decimal
2528    %<bitfield>W         print (bitfield * 4) as a decimal
2529    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
2530    %<bitfield>B         print Thumb branch destination (signed displacement)
2531    %<bitfield>c         print bitfield as a condition code
2532    %<bitnum>'c          print specified char iff bit is one
2533    %<bitnum>?ab         print a if bit is one else print b.  */
2534
2535 static const struct opcode16 thumb_opcodes[] =
2536 {
2537   /* Thumb instructions.  */
2538
2539   /* ARMv8-M Security Extensions instructions.  */
2540   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
2541   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
2542
2543   /* ARM V8 instructions.  */
2544   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
2545   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
2546   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t#%3-3d"},
2547
2548   /* ARM V6K no-argument instructions.  */
2549   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2550   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2551   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2552   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2553   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2554   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2555
2556   /* ARM V6T2 instructions.  */
2557   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2558     0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2559   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2560     0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2561   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
2562
2563   /* ARM V6.  */
2564   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2565   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2566   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2567   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2568   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2569   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2570   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2571   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2572   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2573   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2574   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2575
2576   /* ARM V5 ISA extends Thumb.  */
2577   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2578     0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
2579   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
2580   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2581     0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
2582   /* ARM V4T ISA (Thumb v1).  */
2583   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2584     0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2585   /* Format 4.  */
2586   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2587   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2588   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2589   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2590   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2591   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2592   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2593   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2594   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2595   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2596   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2597   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2598   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2599   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2600   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2601   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2602   /* format 13 */
2603   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2604   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2605   /* format 5 */
2606   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2607   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2608   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2609   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2610   /* format 14 */
2611   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2612   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
2613   /* format 2 */
2614   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2615     0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2616   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2617     0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2618   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2619     0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2620   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2621     0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2622   /* format 8 */
2623   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2624     0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2625   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2626     0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2627   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2628     0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2629   /* format 7 */
2630   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2631     0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2632   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2633     0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2634   /* format 1 */
2635   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2636   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2637     0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2638   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2639   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2640   /* format 3 */
2641   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2642   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2643   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2644   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2645   /* format 6 */
2646   /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2647   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2648     0x4800, 0xF800,
2649     "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2650   /* format 9 */
2651   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2652     0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2653   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2654     0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2655   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2656     0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2657   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2658     0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2659   /* format 10 */
2660   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2661     0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2662   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2663     0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2664   /* format 11 */
2665   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2666     0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2667   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2668     0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2669   /* format 12 */
2670   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2671     0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2672   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2673     0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2674   /* format 15 */
2675   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2676   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2677   /* format 17 */
2678   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2679   /* format 16 */
2680   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2681   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2682   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2683   /* format 18 */
2684   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2685
2686   /* The E800 .. FFFF range is unconditionally redirected to the
2687      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2688      are processed via that table.  Thus, we can never encounter a
2689      bare "second half of BL/BLX(1)" instruction here.  */
2690   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2691   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2692 };
2693
2694 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2695    We adopt the convention that hw1 is the high 16 bits of .value and
2696    .mask, hw2 the low 16 bits.
2697
2698    print_insn_thumb32 recognizes the following format control codes:
2699
2700        %%               %
2701
2702        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2703        %M               print a modified 12-bit immediate (same location)
2704        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2705        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2706        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
2707        %S               print a possibly-shifted Rm
2708
2709        %L               print address for a ldrd/strd instruction
2710        %a               print the address of a plain load/store
2711        %w               print the width and signedness of a core load/store
2712        %m               print register mask for ldm/stm
2713
2714        %E               print the lsb and width fields of a bfc/bfi instruction
2715        %F               print the lsb and width fields of a sbfx/ubfx instruction
2716        %G               print a fallback offset for Branch Future instructions
2717        %W               print an offset for BF instruction
2718        %b               print a conditional branch offset
2719        %B               print an unconditional branch offset
2720        %s               print the shift field of an SSAT instruction
2721        %R               print the rotation field of an SXT instruction
2722        %U               print barrier type.
2723        %P               print address for pli instruction.
2724        %c               print the condition code
2725        %x               print warning if conditional an not at end of IT block"
2726        %X               print "\t; unpredictable <IT:code>" if conditional
2727
2728        %<bitfield>d     print bitfield in decimal
2729        %<bitfield>D     print bitfield plus one in decimal
2730        %<bitfield>W     print bitfield*4 in decimal
2731        %<bitfield>r     print bitfield as an ARM register
2732        %<bitfield>R     as %<>r but r15 is UNPREDICTABLE
2733        %<bitfield>c     print bitfield as a condition code
2734
2735        %<bitfield>'c    print specified char iff bitfield is all ones
2736        %<bitfield>`c    print specified char iff bitfield is all zeroes
2737        %<bitfield>?ab... select from array of values in big endian order
2738
2739    With one exception at the bottom (done because BL and BLX(1) need
2740    to come dead last), this table was machine-sorted first in
2741    decreasing order of number of bits set in the mask, then in
2742    increasing numeric order of mask, then in increasing numeric order
2743    of opcode.  This order is not the clearest for a human reader, but
2744    is guaranteed never to catch a special-case bit pattern with a more
2745    general mask, which is important, because this instruction encoding
2746    makes heavy use of special-case bit patterns.  */
2747 static const struct opcode32 thumb32_opcodes[] =
2748 {
2749   /* Armv8.1-M Mainline instructions.  */
2750   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2751     0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
2752
2753
2754   /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
2755   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
2756   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2757     0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2758   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2759     0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2760   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2761     0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2762   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2763     0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
2764
2765   /* ARM V8.2 RAS extension instructions.  */
2766   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
2767     0xf3af8010, 0xffffffff, "esb"},
2768
2769   /* V8 instructions.  */
2770   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2771     0xf3af8005, 0xffffffff, "sevl%c.w"},
2772   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2773     0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2774   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2775     0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2776   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2777     0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2778   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2779     0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2780   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2781     0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2782   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2783     0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2784   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2785     0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2786   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2787     0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2788   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2789     0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2790   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2791     0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2792   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2793     0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2794   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2795     0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2796   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2797     0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2798   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2799     0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2800   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2801     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
2802
2803   /* CRC32 instructions.  */
2804   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2805     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
2806   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2807     0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
2808   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2809     0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
2810   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2811     0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
2812   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2813     0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
2814   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2815     0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
2816
2817   /* Speculation Barriers.  */
2818   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
2819   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
2820   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
2821
2822   /* V7 instructions.  */
2823   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2824   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2825   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2826   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2827   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2828   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2829   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2830   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2831     0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2832   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2833     0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
2834
2835   /* Virtualization Extension instructions.  */
2836   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
2837   /* We skip ERET as that is SUBS pc, lr, #0.  */
2838
2839   /* MP Extension instructions.  */
2840   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
2841
2842   /* Security extension instructions.  */
2843   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
2844
2845   /* ARMv8.5-A instructions.  */
2846   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
2847
2848   /* Instructions defined in the basic V6T2 set.  */
2849   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2850   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2851   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2852   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2853   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2855     0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2856   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2857
2858   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2859     0xf3bf8f2f, 0xffffffff, "clrex%c"},
2860   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861     0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2862   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2863     0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2864   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2865     0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2866   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2867     0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2868   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2869     0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2870   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871     0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2872   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2873     0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2874   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2875     0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2877     0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2878   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2879     0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881     0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2883     0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2884   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2885     0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2886   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2887     0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2888   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2889     0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2890   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891     0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2892   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2893     0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2894   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895     0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2896   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2897     0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2898   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899     0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2900   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2901     0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2902   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903     0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2904   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905     0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2906   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2907     0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2908   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909     0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2910   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911     0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2912   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2913     0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2914   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2915     0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917     0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2918   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919     0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2920   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921     0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2922   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923     0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2924   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925     0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2926   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927     0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2928   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929     0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2930   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931     0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2932   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933     0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2934   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935     0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937     0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939     0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2940   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941     0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2942   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943     0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2944   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945     0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947     0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2948   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949     0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2950   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2951     0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2952   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953     0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2954   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955     0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2956   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2957     0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2958   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2959     0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2960   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2961     0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2962   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2963     0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2964   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2965     0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2966   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2967     0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2968   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969     0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2970   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2971     0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2972   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2973     0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2974   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2975     0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2976   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2977     0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2978   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2979     0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2980   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2981     0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2982   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2983     0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2984   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2985     0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2986   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2987     0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2988   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2989     0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2990   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2991     0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2992   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2993     0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2994   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2995     0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2996   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2997     0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2998   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2999     0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3000   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3001     0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3002   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3003     0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3004   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3005     0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3006   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3007     0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3008   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3009     0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3010   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3011     0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3012   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3013     0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
3014   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3015     0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3016   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3017     0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
3018   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3019     0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3020   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3021     0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3022   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3023     0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3024   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3025     0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3026   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3027     0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3028   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3029     0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3030   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3031     0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3032   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3033     0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3034   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3035     0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3036   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3037     0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3038   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3039     0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3040   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3041     0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3042   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3043     0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3044   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3045     0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3046   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3047     0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3048   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3049     0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3050   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3051     0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3052   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3053     0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3054   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3055     0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3056   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3057     0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3058   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3059     0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3060   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3061     0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3062   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3063     0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3064   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3065     0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3066   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3067     0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3068   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3069     0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3070   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3071     0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3072   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3073     0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3074   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3075     0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3076   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3077     0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3078   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3079     0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3080   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3081     0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3082   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3083     0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3084   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3085     0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3086   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3087     0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3088   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3089     0xf810f000, 0xff70f000, "pld%c\t%a"},
3090   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3091     0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3092   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3093     0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3094   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3095     0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3096   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3097     0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3098   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3099     0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3100   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3101     0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3102   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3103     0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3105     0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3106   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3107     0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3108   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3109     0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3110   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3111     0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3112   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3113     0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3114   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3115     0xfb100000, 0xfff000c0,
3116     "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3117   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3118     0xfbc00080, 0xfff000c0,
3119     "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3120   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3121     0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3122   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3123     0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3124   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3125     0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
3126   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3127     0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3128   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3129     0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3130   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3131     0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3132   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3133     0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3134   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3135     0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3136   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3137     0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3138   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3139     0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3140   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3141     0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3142   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3143     0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3144   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3145     0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3146   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3147     0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3148   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3149     0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3150   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3151     0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3152   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3153     0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3154   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3155     0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3156   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3157     0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3158   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3159     0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3160   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3161     0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3162   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3163     0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3164   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3165     0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3166   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3167     0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3168   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3169     0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3170   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3171     0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3172   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3173     0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3174   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3175     0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3176   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3177     0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3178   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3179     0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3180   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3181     0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3182   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3183     0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3184   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3185     0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3186   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3187     0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3188   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3189     0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3190   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3191     0xe9400000, 0xff500000,
3192     "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3193   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3194     0xe9500000, 0xff500000,
3195     "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3196   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3197     0xe8600000, 0xff700000,
3198     "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3199   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3200     0xe8700000, 0xff700000,
3201     "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3202   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3203     0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3204   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3205     0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3206
3207   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
3208   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3209     0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3210   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3211     0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3212   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3213     0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3214   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3215     0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3216
3217   /* These have been 32-bit since the invention of Thumb.  */
3218   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3219      0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3220   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3221      0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3222
3223   /* Fallback.  */
3224   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3225       0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3226   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3227 };
3228
3229 static const char *const arm_conditional[] =
3230 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3231  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3232
3233 static const char *const arm_fp_const[] =
3234 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3235
3236 static const char *const arm_shift[] =
3237 {"lsl", "lsr", "asr", "ror"};
3238
3239 typedef struct
3240 {
3241   const char *name;
3242   const char *description;
3243   const char *reg_names[16];
3244 }
3245 arm_regname;
3246
3247 static const arm_regname regnames[] =
3248 {
3249   { "reg-names-raw", N_("Select raw register names"),
3250     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3251   { "reg-names-gcc", N_("Select register names used by GCC"),
3252     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3253   { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
3254     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
3255   { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3256   { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3257   { "reg-names-apcs", N_("Select register names used in the APCS"),
3258     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3259   { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
3260     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
3261   { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3262     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }}
3263 };
3264
3265 static const char *const iwmmxt_wwnames[] =
3266 {"b", "h", "w", "d"};
3267
3268 static const char *const iwmmxt_wwssnames[] =
3269 {"b", "bus", "bc", "bss",
3270  "h", "hus", "hc", "hss",
3271  "w", "wus", "wc", "wss",
3272  "d", "dus", "dc", "dss"
3273 };
3274
3275 static const char *const iwmmxt_regnames[] =
3276 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3277   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3278 };
3279
3280 static const char *const iwmmxt_cregnames[] =
3281 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3282   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3283 };
3284
3285 /* Default to GCC register name set.  */
3286 static unsigned int regname_selected = 1;
3287
3288 #define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
3289 #define arm_regnames      regnames[regname_selected].reg_names
3290
3291 static bfd_boolean force_thumb = FALSE;
3292
3293 /* Current IT instruction state.  This contains the same state as the IT
3294    bits in the CPSR.  */
3295 static unsigned int ifthen_state;
3296 /* IT state for the next instruction.  */
3297 static unsigned int ifthen_next_state;
3298 /* The address of the insn for which the IT state is valid.  */
3299 static bfd_vma ifthen_address;
3300 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3301 /* Indicates that the current Conditional state is unconditional or outside
3302    an IT block.  */
3303 #define COND_UNCOND 16
3304
3305 \f
3306 /* Functions.  */
3307
3308 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3309    Returns pointer to following character of the format string and
3310    fills in *VALUEP and *WIDTHP with the extracted value and number of
3311    bits extracted.  WIDTHP can be NULL.  */
3312
3313 static const char *
3314 arm_decode_bitfield (const char *ptr,
3315                      unsigned long insn,
3316                      unsigned long *valuep,
3317                      int *widthp)
3318 {
3319   unsigned long value = 0;
3320   int width = 0;
3321
3322   do
3323     {
3324       int start, end;
3325       int bits;
3326
3327       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3328         start = start * 10 + *ptr - '0';
3329       if (*ptr == '-')
3330         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3331           end = end * 10 + *ptr - '0';
3332       else
3333         end = start;
3334       bits = end - start;
3335       if (bits < 0)
3336         abort ();
3337       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3338       width += bits + 1;
3339     }
3340   while (*ptr++ == ',');
3341   *valuep = value;
3342   if (widthp)
3343     *widthp = width;
3344   return ptr - 1;
3345 }
3346
3347 static void
3348 arm_decode_shift (long given, fprintf_ftype func, void *stream,
3349                   bfd_boolean print_shift)
3350 {
3351   func (stream, "%s", arm_regnames[given & 0xf]);
3352
3353   if ((given & 0xff0) != 0)
3354     {
3355       if ((given & 0x10) == 0)
3356         {
3357           int amount = (given & 0xf80) >> 7;
3358           int shift = (given & 0x60) >> 5;
3359
3360           if (amount == 0)
3361             {
3362               if (shift == 3)
3363                 {
3364                   func (stream, ", rrx");
3365                   return;
3366                 }
3367
3368               amount = 32;
3369             }
3370
3371           if (print_shift)
3372             func (stream, ", %s #%d", arm_shift[shift], amount);
3373           else
3374             func (stream, ", #%d", amount);
3375         }
3376       else if ((given & 0x80) == 0x80)
3377         func (stream, "\t; <illegal shifter operand>");
3378       else if (print_shift)
3379         func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3380               arm_regnames[(given & 0xf00) >> 8]);
3381       else
3382         func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3383     }
3384 }
3385
3386 #define W_BIT 21
3387 #define I_BIT 22
3388 #define U_BIT 23
3389 #define P_BIT 24
3390
3391 #define WRITEBACK_BIT_SET   (given & (1 << W_BIT))
3392 #define IMMEDIATE_BIT_SET   (given & (1 << I_BIT))
3393 #define NEGATIVE_BIT_SET   ((given & (1 << U_BIT)) == 0)
3394 #define PRE_BIT_SET         (given & (1 << P_BIT))
3395
3396 /* Print one coprocessor instruction on INFO->STREAM.
3397    Return TRUE if the instuction matched, FALSE if this is not a
3398    recognised coprocessor instruction.  */
3399
3400 static bfd_boolean
3401 print_insn_coprocessor (bfd_vma pc,
3402                         struct disassemble_info *info,
3403                         long given,
3404                         bfd_boolean thumb)
3405 {
3406   const struct opcode32 *insn;
3407   void *stream = info->stream;
3408   fprintf_ftype func = info->fprintf_func;
3409   unsigned long mask;
3410   unsigned long value = 0;
3411   int cond;
3412   int cp_num;
3413   struct arm_private_data *private_data = info->private_data;
3414   arm_feature_set allowed_arches = ARM_ARCH_NONE;
3415
3416   allowed_arches = private_data->features;
3417
3418   for (insn = coprocessor_opcodes; insn->assembler; insn++)
3419     {
3420       unsigned long u_reg = 16;
3421       bfd_boolean is_unpredictable = FALSE;
3422       signed long value_in_comment = 0;
3423       const char *c;
3424
3425       if (ARM_FEATURE_ZERO (insn->arch))
3426         switch (insn->value)
3427           {
3428           case SENTINEL_IWMMXT_START:
3429             if (info->mach != bfd_mach_arm_XScale
3430                 && info->mach != bfd_mach_arm_iWMMXt
3431                 && info->mach != bfd_mach_arm_iWMMXt2)
3432               do
3433                 insn++;
3434               while ((! ARM_FEATURE_ZERO (insn->arch))
3435                      && insn->value != SENTINEL_IWMMXT_END);
3436             continue;
3437
3438           case SENTINEL_IWMMXT_END:
3439             continue;
3440
3441           case SENTINEL_GENERIC_START:
3442             allowed_arches = private_data->features;
3443             continue;
3444
3445           default:
3446             abort ();
3447           }
3448
3449       mask = insn->mask;
3450       value = insn->value;
3451       cp_num = (given >> 8) & 0xf;
3452
3453       if (thumb)
3454         {
3455           /* The high 4 bits are 0xe for Arm conditional instructions, and
3456              0xe for arm unconditional instructions.  The rest of the
3457              encoding is the same.  */
3458           mask |= 0xf0000000;
3459           value |= 0xe0000000;
3460           if (ifthen_state)
3461             cond = IFTHEN_COND;
3462           else
3463             cond = COND_UNCOND;
3464         }
3465       else
3466         {
3467           /* Only match unconditional instuctions against unconditional
3468              patterns.  */
3469           if ((given & 0xf0000000) == 0xf0000000)
3470             {
3471               mask |= 0xf0000000;
3472               cond = COND_UNCOND;
3473             }
3474           else
3475             {
3476               cond = (given >> 28) & 0xf;
3477               if (cond == 0xe)
3478                 cond = COND_UNCOND;
3479             }
3480         }
3481
3482       if ((given & mask) != value)
3483         continue;
3484
3485       if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
3486         continue;
3487
3488       if (insn->value == 0xfe000010     /* mcr2  */
3489           || insn->value == 0xfe100010  /* mrc2  */
3490           || insn->value == 0xfc100000  /* ldc2  */
3491           || insn->value == 0xfc000000) /* stc2  */
3492         {
3493           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3494             is_unpredictable = TRUE;
3495         }
3496       else if (insn->value == 0x0e000000     /* cdp  */
3497                || insn->value == 0xfe000000  /* cdp2  */
3498                || insn->value == 0x0e000010  /* mcr  */
3499                || insn->value == 0x0e100010  /* mrc  */
3500                || insn->value == 0x0c100000  /* ldc  */
3501                || insn->value == 0x0c000000) /* stc  */
3502         {
3503           /* Floating-point instructions.  */
3504           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3505             continue;
3506         }
3507
3508       for (c = insn->assembler; *c; c++)
3509         {
3510           if (*c == '%')
3511             {
3512               switch (*++c)
3513                 {
3514                 case '%':
3515                   func (stream, "%%");
3516                   break;
3517
3518                 case 'A':
3519                   {
3520                     int rn = (given >> 16) & 0xf;
3521                     bfd_vma offset = given & 0xff;
3522
3523                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3524
3525                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3526                       {
3527                         /* Not unindexed.  The offset is scaled.  */
3528                         if (cp_num == 9)
3529                           /* vldr.16/vstr.16 will shift the address
3530                              left by 1 bit only.  */
3531                           offset = offset * 2;
3532                         else
3533                           offset = offset * 4;
3534
3535                         if (NEGATIVE_BIT_SET)
3536                           offset = - offset;
3537                         if (rn != 15)
3538                           value_in_comment = offset;
3539                       }
3540
3541                     if (PRE_BIT_SET)
3542                       {
3543                         if (offset)
3544                           func (stream, ", #%d]%s",
3545                                 (int) offset,
3546                                 WRITEBACK_BIT_SET ? "!" : "");
3547                         else if (NEGATIVE_BIT_SET)
3548                           func (stream, ", #-0]");
3549                         else
3550                           func (stream, "]");
3551                       }
3552                     else
3553                       {
3554                         func (stream, "]");
3555
3556                         if (WRITEBACK_BIT_SET)
3557                           {
3558                             if (offset)
3559                               func (stream, ", #%d", (int) offset);
3560                             else if (NEGATIVE_BIT_SET)
3561                               func (stream, ", #-0");
3562                           }
3563                         else
3564                           {
3565                             func (stream, ", {%s%d}",
3566                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
3567                                   (int) offset);
3568                             value_in_comment = offset;
3569                           }
3570                       }
3571                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3572                       {
3573                         func (stream, "\t; ");
3574                         /* For unaligned PCs, apply off-by-alignment
3575                            correction.  */
3576                         info->print_address_func (offset + pc
3577                                                   + info->bytes_per_chunk * 2
3578                                                   - (pc & 3),
3579                                                   info);
3580                       }
3581                   }
3582                   break;
3583
3584                 case 'B':
3585                   {
3586                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3587                     int offset = (given >> 1) & 0x3f;
3588
3589                     if (offset == 1)
3590                       func (stream, "{d%d}", regno);
3591                     else if (regno + offset > 32)
3592                       func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3593                     else
3594                       func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3595                   }
3596                   break;
3597
3598                 case 'u':
3599                   if (cond != COND_UNCOND)
3600                     is_unpredictable = TRUE;
3601
3602                   /* Fall through.  */
3603                 case 'c':
3604                   if (cond != COND_UNCOND && cp_num == 9)
3605                     is_unpredictable = TRUE;
3606
3607                   func (stream, "%s", arm_conditional[cond]);
3608                   break;
3609
3610                 case 'I':
3611                   /* Print a Cirrus/DSP shift immediate.  */
3612                   /* Immediates are 7bit signed ints with bits 0..3 in
3613                      bits 0..3 of opcode and bits 4..6 in bits 5..7
3614                      of opcode.  */
3615                   {
3616                     int imm;
3617
3618                     imm = (given & 0xf) | ((given & 0xe0) >> 1);
3619
3620                     /* Is ``imm'' a negative number?  */
3621                     if (imm & 0x40)
3622                       imm -= 0x80;
3623
3624                     func (stream, "%d", imm);
3625                   }
3626
3627                   break;
3628
3629                 case 'F':
3630                   switch (given & 0x00408000)
3631                     {
3632                     case 0:
3633                       func (stream, "4");
3634                       break;
3635                     case 0x8000:
3636                       func (stream, "1");
3637                       break;
3638                     case 0x00400000:
3639                       func (stream, "2");
3640                       break;
3641                     default:
3642                       func (stream, "3");
3643                     }
3644                   break;
3645
3646                 case 'P':
3647                   switch (given & 0x00080080)
3648                     {
3649                     case 0:
3650                       func (stream, "s");
3651                       break;
3652                     case 0x80:
3653                       func (stream, "d");
3654                       break;
3655                     case 0x00080000:
3656                       func (stream, "e");
3657                       break;
3658                     default:
3659                       func (stream, _("<illegal precision>"));
3660                       break;
3661                     }
3662                   break;
3663
3664                 case 'Q':
3665                   switch (given & 0x00408000)
3666                     {
3667                     case 0:
3668                       func (stream, "s");
3669                       break;
3670                     case 0x8000:
3671                       func (stream, "d");
3672                       break;
3673                     case 0x00400000:
3674                       func (stream, "e");
3675                       break;
3676                     default:
3677                       func (stream, "p");
3678                       break;
3679                     }
3680                   break;
3681
3682                 case 'R':
3683                   switch (given & 0x60)
3684                     {
3685                     case 0:
3686                       break;
3687                     case 0x20:
3688                       func (stream, "p");
3689                       break;
3690                     case 0x40:
3691                       func (stream, "m");
3692                       break;
3693                     default:
3694                       func (stream, "z");
3695                       break;
3696                     }
3697                   break;
3698
3699                 case '0': case '1': case '2': case '3': case '4':
3700                 case '5': case '6': case '7': case '8': case '9':
3701                   {
3702                     int width;
3703
3704                     c = arm_decode_bitfield (c, given, &value, &width);
3705
3706                     switch (*c)
3707                       {
3708                       case 'R':
3709                         if (value == 15)
3710                           is_unpredictable = TRUE;
3711                         /* Fall through.  */
3712                       case 'r':
3713                         if (c[1] == 'u')
3714                           {
3715                             /* Eat the 'u' character.  */
3716                             ++ c;
3717
3718                             if (u_reg == value)
3719                               is_unpredictable = TRUE;
3720                             u_reg = value;
3721                           }
3722                         func (stream, "%s", arm_regnames[value]);
3723                         break;
3724                       case 'V':
3725                         if (given & (1 << 6))
3726                           goto Q;
3727                         /* FALLTHROUGH */
3728                       case 'D':
3729                         func (stream, "d%ld", value);
3730                         break;
3731                       case 'Q':
3732                       Q:
3733                         if (value & 1)
3734                           func (stream, "<illegal reg q%ld.5>", value >> 1);
3735                         else
3736                           func (stream, "q%ld", value >> 1);
3737                         break;
3738                       case 'd':
3739                         func (stream, "%ld", value);
3740                         value_in_comment = value;
3741                         break;
3742                       case 'E':
3743                         {
3744                           /* Converts immediate 8 bit back to float value.  */
3745                           unsigned floatVal = (value & 0x80) << 24
3746                             | (value & 0x3F) << 19
3747                             | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3748
3749                           /* Quarter float have a maximum value of 31.0.
3750                              Get floating point value multiplied by 1e7.
3751                              The maximum value stays in limit of a 32-bit int.  */
3752                           unsigned decVal =
3753                             (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3754                             (16 + (value & 0xF));
3755
3756                           if (!(decVal % 1000000))
3757                             func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3758                                   floatVal, value & 0x80 ? '-' : ' ',
3759                                   decVal / 10000000,
3760                                   decVal % 10000000 / 1000000);
3761                           else if (!(decVal % 10000))
3762                             func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3763                                   floatVal, value & 0x80 ? '-' : ' ',
3764                                   decVal / 10000000,
3765                                   decVal % 10000000 / 10000);
3766                           else
3767                             func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3768                                   floatVal, value & 0x80 ? '-' : ' ',
3769                                   decVal / 10000000, decVal % 10000000);
3770                           break;
3771                         }
3772                       case 'k':
3773                         {
3774                           int from = (given & (1 << 7)) ? 32 : 16;
3775                           func (stream, "%ld", from - value);
3776                         }
3777                         break;
3778
3779                       case 'f':
3780                         if (value > 7)
3781                           func (stream, "#%s", arm_fp_const[value & 7]);
3782                         else
3783                           func (stream, "f%ld", value);
3784                         break;
3785
3786                       case 'w':
3787                         if (width == 2)
3788                           func (stream, "%s", iwmmxt_wwnames[value]);
3789                         else
3790                           func (stream, "%s", iwmmxt_wwssnames[value]);
3791                         break;
3792
3793                       case 'g':
3794                         func (stream, "%s", iwmmxt_regnames[value]);
3795                         break;
3796                       case 'G':
3797                         func (stream, "%s", iwmmxt_cregnames[value]);
3798                         break;
3799
3800                       case 'x':
3801                         func (stream, "0x%lx", (value & 0xffffffffUL));
3802                         break;
3803
3804                       case 'c':
3805                         switch (value)
3806                           {
3807                           case 0:
3808                             func (stream, "eq");
3809                             break;
3810
3811                           case 1:
3812                             func (stream, "vs");
3813                             break;
3814
3815                           case 2:
3816                             func (stream, "ge");
3817                             break;
3818
3819                           case 3:
3820                             func (stream, "gt");
3821                             break;
3822
3823                           default:
3824                             func (stream, "??");
3825                             break;
3826                           }
3827                         break;
3828
3829                       case '`':
3830                         c++;
3831                         if (value == 0)
3832                           func (stream, "%c", *c);
3833                         break;
3834                       case '\'':
3835                         c++;
3836                         if (value == ((1ul << width) - 1))
3837                           func (stream, "%c", *c);
3838                         break;
3839                       case '?':
3840                         func (stream, "%c", c[(1 << width) - (int) value]);
3841                         c += 1 << width;
3842                         break;
3843                       default:
3844                         abort ();
3845                       }
3846                   }
3847                   break;
3848
3849                 case 'y':
3850                 case 'z':
3851                   {
3852                     int single = *c++ == 'y';
3853                     int regno;
3854
3855                     switch (*c)
3856                       {
3857                       case '4': /* Sm pair */
3858                       case '0': /* Sm, Dm */
3859                         regno = given & 0x0000000f;
3860                         if (single)
3861                           {
3862                             regno <<= 1;
3863                             regno += (given >> 5) & 1;
3864                           }
3865                         else
3866                           regno += ((given >> 5) & 1) << 4;
3867                         break;
3868
3869                       case '1': /* Sd, Dd */
3870                         regno = (given >> 12) & 0x0000000f;
3871                         if (single)
3872                           {
3873                             regno <<= 1;
3874                             regno += (given >> 22) & 1;
3875                           }
3876                         else
3877                           regno += ((given >> 22) & 1) << 4;
3878                         break;
3879
3880                       case '2': /* Sn, Dn */
3881                         regno = (given >> 16) & 0x0000000f;
3882                         if (single)
3883                           {
3884                             regno <<= 1;
3885                             regno += (given >> 7) & 1;
3886                           }
3887                         else
3888                           regno += ((given >> 7) & 1) << 4;
3889                         break;
3890
3891                       case '3': /* List */
3892                         func (stream, "{");
3893                         regno = (given >> 12) & 0x0000000f;
3894                         if (single)
3895                           {
3896                             regno <<= 1;
3897                             regno += (given >> 22) & 1;
3898                           }
3899                         else
3900                           regno += ((given >> 22) & 1) << 4;
3901                         break;
3902
3903                       default:
3904                         abort ();
3905                       }
3906
3907                     func (stream, "%c%d", single ? 's' : 'd', regno);
3908
3909                     if (*c == '3')
3910                       {
3911                         int count = given & 0xff;
3912
3913                         if (single == 0)
3914                           count >>= 1;
3915
3916                         if (--count)
3917                           {
3918                             func (stream, "-%c%d",
3919                                   single ? 's' : 'd',
3920                                   regno + count);
3921                           }
3922
3923                         func (stream, "}");
3924                       }
3925                     else if (*c == '4')
3926                       func (stream, ", %c%d", single ? 's' : 'd',
3927                             regno + 1);
3928                   }
3929                   break;
3930
3931                 case 'L':
3932                   switch (given & 0x00400100)
3933                     {
3934                     case 0x00000000: func (stream, "b"); break;
3935                     case 0x00400000: func (stream, "h"); break;
3936                     case 0x00000100: func (stream, "w"); break;
3937                     case 0x00400100: func (stream, "d"); break;
3938                     default:
3939                       break;
3940                     }
3941                   break;
3942
3943                 case 'Z':
3944                   {
3945                     /* given (20, 23) | given (0, 3) */
3946                     value = ((given >> 16) & 0xf0) | (given & 0xf);
3947                     func (stream, "%d", (int) value);
3948                   }
3949                   break;
3950
3951                 case 'l':
3952                   /* This is like the 'A' operator, except that if
3953                      the width field "M" is zero, then the offset is
3954                      *not* multiplied by four.  */
3955                   {
3956                     int offset = given & 0xff;
3957                     int multiplier = (given & 0x00000100) ? 4 : 1;
3958
3959                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3960
3961                     if (multiplier > 1)
3962                       {
3963                         value_in_comment = offset * multiplier;
3964                         if (NEGATIVE_BIT_SET)
3965                           value_in_comment = - value_in_comment;
3966                       }
3967
3968                     if (offset)
3969                       {
3970                         if (PRE_BIT_SET)
3971                           func (stream, ", #%s%d]%s",
3972                                 NEGATIVE_BIT_SET ? "-" : "",
3973                                 offset * multiplier,
3974                                 WRITEBACK_BIT_SET ? "!" : "");
3975                         else
3976                           func (stream, "], #%s%d",
3977                                 NEGATIVE_BIT_SET ? "-" : "",
3978                                 offset * multiplier);
3979                       }
3980                     else
3981                       func (stream, "]");
3982                   }
3983                   break;
3984
3985                 case 'r':
3986                   {
3987                     int imm4 = (given >> 4) & 0xf;
3988                     int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3989                     int ubit = ! NEGATIVE_BIT_SET;
3990                     const char *rm = arm_regnames [given & 0xf];
3991                     const char *rn = arm_regnames [(given >> 16) & 0xf];
3992
3993                     switch (puw_bits)
3994                       {
3995                       case 1:
3996                       case 3:
3997                         func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3998                         if (imm4)
3999                           func (stream, ", lsl #%d", imm4);
4000                         break;
4001
4002                       case 4:
4003                       case 5:
4004                       case 6:
4005                       case 7:
4006                         func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
4007                         if (imm4 > 0)
4008                           func (stream, ", lsl #%d", imm4);
4009                         func (stream, "]");
4010                         if (puw_bits == 5 || puw_bits == 7)
4011                           func (stream, "!");
4012                         break;
4013
4014                       default:
4015                         func (stream, "INVALID");
4016                       }
4017                   }
4018                   break;
4019
4020                 case 'i':
4021                   {
4022                     long imm5;
4023                     imm5 = ((given & 0x100) >> 4) | (given & 0xf);
4024                     func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
4025                   }
4026                   break;
4027
4028                 default:
4029                   abort ();
4030                 }
4031             }
4032           else
4033             func (stream, "%c", *c);
4034         }
4035
4036       if (value_in_comment > 32 || value_in_comment < -16)
4037         func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
4038
4039       if (is_unpredictable)
4040         func (stream, UNPREDICTABLE_INSTRUCTION);
4041
4042       return TRUE;
4043     }
4044   return FALSE;
4045 }
4046
4047 /* Decodes and prints ARM addressing modes.  Returns the offset
4048    used in the address, if any, if it is worthwhile printing the
4049    offset as a hexadecimal value in a comment at the end of the
4050    line of disassembly.  */
4051
4052 static signed long
4053 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4054 {
4055   void *stream = info->stream;
4056   fprintf_ftype func = info->fprintf_func;
4057   bfd_vma offset = 0;
4058
4059   if (((given & 0x000f0000) == 0x000f0000)
4060       && ((given & 0x02000000) == 0))
4061     {
4062       offset = given & 0xfff;
4063
4064       func (stream, "[pc");
4065
4066       if (PRE_BIT_SET)
4067         {
4068           /* Pre-indexed.  Elide offset of positive zero when
4069              non-writeback.  */
4070           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
4071             func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4072
4073           if (NEGATIVE_BIT_SET)
4074             offset = -offset;
4075
4076           offset += pc + 8;
4077
4078           /* Cope with the possibility of write-back
4079              being used.  Probably a very dangerous thing
4080              for the programmer to do, but who are we to
4081              argue ?  */
4082           func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
4083         }
4084       else  /* Post indexed.  */
4085         {
4086           func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4087
4088           /* Ie ignore the offset.  */
4089           offset = pc + 8;
4090         }
4091
4092       func (stream, "\t; ");
4093       info->print_address_func (offset, info);
4094       offset = 0;
4095     }
4096   else
4097     {
4098       func (stream, "[%s",
4099             arm_regnames[(given >> 16) & 0xf]);
4100
4101       if (PRE_BIT_SET)
4102         {
4103           if ((given & 0x02000000) == 0)
4104             {
4105               /* Elide offset of positive zero when non-writeback.  */
4106               offset = given & 0xfff;
4107               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
4108                 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4109             }
4110           else
4111             {
4112               func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
4113               arm_decode_shift (given, func, stream, TRUE);
4114             }
4115
4116           func (stream, "]%s",
4117                 WRITEBACK_BIT_SET ? "!" : "");
4118         }
4119       else
4120         {
4121           if ((given & 0x02000000) == 0)
4122             {
4123               /* Always show offset.  */
4124               offset = given & 0xfff;
4125               func (stream, "], #%s%d",
4126                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4127             }
4128           else
4129             {
4130               func (stream, "], %s",
4131                     NEGATIVE_BIT_SET ? "-" : "");
4132               arm_decode_shift (given, func, stream, TRUE);
4133             }
4134         }
4135       if (NEGATIVE_BIT_SET)
4136         offset = -offset;
4137     }
4138
4139   return (signed long) offset;
4140 }
4141
4142 /* Print one neon instruction on INFO->STREAM.
4143    Return TRUE if the instuction matched, FALSE if this is not a
4144    recognised neon instruction.  */
4145
4146 static bfd_boolean
4147 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4148 {
4149   const struct opcode32 *insn;
4150   void *stream = info->stream;
4151   fprintf_ftype func = info->fprintf_func;
4152
4153   if (thumb)
4154     {
4155       if ((given & 0xef000000) == 0xef000000)
4156         {
4157           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
4158           unsigned long bit28 = given & (1 << 28);
4159
4160           given &= 0x00ffffff;
4161           if (bit28)
4162             given |= 0xf3000000;
4163           else
4164             given |= 0xf2000000;
4165         }
4166       else if ((given & 0xff000000) == 0xf9000000)
4167         given ^= 0xf9000000 ^ 0xf4000000;
4168       else
4169         return FALSE;
4170     }
4171
4172   for (insn = neon_opcodes; insn->assembler; insn++)
4173     {
4174       if ((given & insn->mask) == insn->value)
4175         {
4176           signed long value_in_comment = 0;
4177           bfd_boolean is_unpredictable = FALSE;
4178           const char *c;
4179
4180           for (c = insn->assembler; *c; c++)
4181             {
4182               if (*c == '%')
4183                 {
4184                   switch (*++c)
4185                     {
4186                     case '%':
4187                       func (stream, "%%");
4188                       break;
4189
4190                     case 'u':
4191                       if (thumb && ifthen_state)
4192                         is_unpredictable = TRUE;
4193
4194                       /* Fall through.  */
4195                     case 'c':
4196                       if (thumb && ifthen_state)
4197                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
4198                       break;
4199
4200                     case 'A':
4201                       {
4202                         static const unsigned char enc[16] =
4203                         {
4204                           0x4, 0x14, /* st4 0,1 */
4205                           0x4, /* st1 2 */
4206                           0x4, /* st2 3 */
4207                           0x3, /* st3 4 */
4208                           0x13, /* st3 5 */
4209                           0x3, /* st1 6 */
4210                           0x1, /* st1 7 */
4211                           0x2, /* st2 8 */
4212                           0x12, /* st2 9 */
4213                           0x2, /* st1 10 */
4214                           0, 0, 0, 0, 0
4215                         };
4216                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4217                         int rn = ((given >> 16) & 0xf);
4218                         int rm = ((given >> 0) & 0xf);
4219                         int align = ((given >> 4) & 0x3);
4220                         int type = ((given >> 8) & 0xf);
4221                         int n = enc[type] & 0xf;
4222                         int stride = (enc[type] >> 4) + 1;
4223                         int ix;
4224
4225                         func (stream, "{");
4226                         if (stride > 1)
4227                           for (ix = 0; ix != n; ix++)
4228                             func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4229                         else if (n == 1)
4230                           func (stream, "d%d", rd);
4231                         else
4232                           func (stream, "d%d-d%d", rd, rd + n - 1);
4233                         func (stream, "}, [%s", arm_regnames[rn]);
4234                         if (align)
4235                           func (stream, " :%d", 32 << align);
4236                         func (stream, "]");
4237                         if (rm == 0xd)
4238                           func (stream, "!");
4239                         else if (rm != 0xf)
4240                           func (stream, ", %s", arm_regnames[rm]);
4241                       }
4242                       break;
4243
4244                     case 'B':
4245                       {
4246                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4247                         int rn = ((given >> 16) & 0xf);
4248                         int rm = ((given >> 0) & 0xf);
4249                         int idx_align = ((given >> 4) & 0xf);
4250                         int align = 0;
4251                         int size = ((given >> 10) & 0x3);
4252                         int idx = idx_align >> (size + 1);
4253                         int length = ((given >> 8) & 3) + 1;
4254                         int stride = 1;
4255                         int i;
4256
4257                         if (length > 1 && size > 0)
4258                           stride = (idx_align & (1 << size)) ? 2 : 1;
4259
4260                         switch (length)
4261                           {
4262                           case 1:
4263                             {
4264                               int amask = (1 << size) - 1;
4265                               if ((idx_align & (1 << size)) != 0)
4266                                 return FALSE;
4267                               if (size > 0)
4268                                 {
4269                                   if ((idx_align & amask) == amask)
4270                                     align = 8 << size;
4271                                   else if ((idx_align & amask) != 0)
4272                                     return FALSE;
4273                                 }
4274                               }
4275                             break;
4276
4277                           case 2:
4278                             if (size == 2 && (idx_align & 2) != 0)
4279                               return FALSE;
4280                             align = (idx_align & 1) ? 16 << size : 0;
4281                             break;
4282
4283                           case 3:
4284                             if ((size == 2 && (idx_align & 3) != 0)
4285                                 || (idx_align & 1) != 0)
4286                               return FALSE;
4287                             break;
4288
4289                           case 4:
4290                             if (size == 2)
4291                               {
4292                                 if ((idx_align & 3) == 3)
4293                                   return FALSE;
4294                                 align = (idx_align & 3) * 64;
4295                               }
4296                             else
4297                               align = (idx_align & 1) ? 32 << size : 0;
4298                             break;
4299
4300                           default:
4301                             abort ();
4302                           }
4303
4304                         func (stream, "{");
4305                         for (i = 0; i < length; i++)
4306                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4307                             rd + i * stride, idx);
4308                         func (stream, "}, [%s", arm_regnames[rn]);
4309                         if (align)
4310                           func (stream, " :%d", align);
4311                         func (stream, "]");
4312                         if (rm == 0xd)
4313                           func (stream, "!");
4314                         else if (rm != 0xf)
4315                           func (stream, ", %s", arm_regnames[rm]);
4316                       }
4317                       break;
4318
4319                     case 'C':
4320                       {
4321                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4322                         int rn = ((given >> 16) & 0xf);
4323                         int rm = ((given >> 0) & 0xf);
4324                         int align = ((given >> 4) & 0x1);
4325                         int size = ((given >> 6) & 0x3);
4326                         int type = ((given >> 8) & 0x3);
4327                         int n = type + 1;
4328                         int stride = ((given >> 5) & 0x1);
4329                         int ix;
4330
4331                         if (stride && (n == 1))
4332                           n++;
4333                         else
4334                           stride++;
4335
4336                         func (stream, "{");
4337                         if (stride > 1)
4338                           for (ix = 0; ix != n; ix++)
4339                             func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4340                         else if (n == 1)
4341                           func (stream, "d%d[]", rd);
4342                         else
4343                           func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4344                         func (stream, "}, [%s", arm_regnames[rn]);
4345                         if (align)
4346                           {
4347                             align = (8 * (type + 1)) << size;
4348                             if (type == 3)
4349                               align = (size > 1) ? align >> 1 : align;
4350                             if (type == 2 || (type == 0 && !size))
4351                               func (stream, " :<bad align %d>", align);
4352                             else
4353                               func (stream, " :%d", align);
4354                           }
4355                         func (stream, "]");
4356                         if (rm == 0xd)
4357                           func (stream, "!");
4358                         else if (rm != 0xf)
4359                           func (stream, ", %s", arm_regnames[rm]);
4360                       }
4361                       break;
4362
4363                     case 'D':
4364                       {
4365                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4366                         int size = (given >> 20) & 3;
4367                         int reg = raw_reg & ((4 << size) - 1);
4368                         int ix = raw_reg >> size >> 2;
4369
4370                         func (stream, "d%d[%d]", reg, ix);
4371                       }
4372                       break;
4373
4374                     case 'E':
4375                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
4376                       {
4377                         int bits = 0;
4378                         int cmode = (given >> 8) & 0xf;
4379                         int op = (given >> 5) & 0x1;
4380                         unsigned long value = 0, hival = 0;
4381                         unsigned shift;
4382                         int size = 0;
4383                         int isfloat = 0;
4384
4385                         bits |= ((given >> 24) & 1) << 7;
4386                         bits |= ((given >> 16) & 7) << 4;
4387                         bits |= ((given >> 0) & 15) << 0;
4388
4389                         if (cmode < 8)
4390                           {
4391                             shift = (cmode >> 1) & 3;
4392                             value = (unsigned long) bits << (8 * shift);
4393                             size = 32;
4394                           }
4395                         else if (cmode < 12)
4396                           {
4397                             shift = (cmode >> 1) & 1;
4398                             value = (unsigned long) bits << (8 * shift);
4399                             size = 16;
4400                           }
4401                         else if (cmode < 14)
4402                           {
4403                             shift = (cmode & 1) + 1;
4404                             value = (unsigned long) bits << (8 * shift);
4405                             value |= (1ul << (8 * shift)) - 1;
4406                             size = 32;
4407                           }
4408                         else if (cmode == 14)
4409                           {
4410                             if (op)
4411                               {
4412                                 /* Bit replication into bytes.  */
4413                                 int ix;
4414                                 unsigned long mask;
4415
4416                                 value = 0;
4417                                 hival = 0;
4418                                 for (ix = 7; ix >= 0; ix--)
4419                                   {
4420                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
4421                                     if (ix <= 3)
4422                                       value = (value << 8) | mask;
4423                                     else
4424                                       hival = (hival << 8) | mask;
4425                                   }
4426                                 size = 64;
4427                               }
4428                             else
4429                               {
4430                                 /* Byte replication.  */
4431                                 value = (unsigned long) bits;
4432                                 size = 8;
4433                               }
4434                           }
4435                         else if (!op)
4436                           {
4437                             /* Floating point encoding.  */
4438                             int tmp;
4439
4440                             value = (unsigned long)  (bits & 0x7f) << 19;
4441                             value |= (unsigned long) (bits & 0x80) << 24;
4442                             tmp = bits & 0x40 ? 0x3c : 0x40;
4443                             value |= (unsigned long) tmp << 24;
4444                             size = 32;
4445                             isfloat = 1;
4446                           }
4447                         else
4448                           {
4449                             func (stream, "<illegal constant %.8x:%x:%x>",
4450                                   bits, cmode, op);
4451                             size = 32;
4452                             break;
4453                           }
4454                         switch (size)
4455                           {
4456                           case 8:
4457                             func (stream, "#%ld\t; 0x%.2lx", value, value);
4458                             break;
4459
4460                           case 16:
4461                             func (stream, "#%ld\t; 0x%.4lx", value, value);
4462                             break;
4463
4464                           case 32:
4465                             if (isfloat)
4466                               {
4467                                 unsigned char valbytes[4];
4468                                 double fvalue;
4469
4470                                 /* Do this a byte at a time so we don't have to
4471                                    worry about the host's endianness.  */
4472                                 valbytes[0] = value & 0xff;
4473                                 valbytes[1] = (value >> 8) & 0xff;
4474                                 valbytes[2] = (value >> 16) & 0xff;
4475                                 valbytes[3] = (value >> 24) & 0xff;
4476
4477                                 floatformat_to_double
4478                                   (& floatformat_ieee_single_little, valbytes,
4479                                   & fvalue);
4480
4481                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4482                                       value);
4483                               }
4484                             else
4485                               func (stream, "#%ld\t; 0x%.8lx",
4486                                     (long) (((value & 0x80000000L) != 0)
4487                                             ? value | ~0xffffffffL : value),
4488                                     value);
4489                             break;
4490
4491                           case 64:
4492                             func (stream, "#0x%.8lx%.8lx", hival, value);
4493                             break;
4494
4495                           default:
4496                             abort ();
4497                           }
4498                       }
4499                       break;
4500
4501                     case 'F':
4502                       {
4503                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4504                         int num = (given >> 8) & 0x3;
4505
4506                         if (!num)
4507                           func (stream, "{d%d}", regno);
4508                         else if (num + regno >= 32)
4509                           func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4510                         else
4511                           func (stream, "{d%d-d%d}", regno, regno + num);
4512                       }
4513                       break;
4514
4515
4516                     case '0': case '1': case '2': case '3': case '4':
4517                     case '5': case '6': case '7': case '8': case '9':
4518                       {
4519                         int width;
4520                         unsigned long value;
4521
4522                         c = arm_decode_bitfield (c, given, &value, &width);
4523
4524                         switch (*c)
4525                           {
4526                           case 'r':
4527                             func (stream, "%s", arm_regnames[value]);
4528                             break;
4529                           case 'd':
4530                             func (stream, "%ld", value);
4531                             value_in_comment = value;
4532                             break;
4533                           case 'e':
4534                             func (stream, "%ld", (1ul << width) - value);
4535                             break;
4536
4537                           case 'S':
4538                           case 'T':
4539                           case 'U':
4540                             /* Various width encodings.  */
4541                             {
4542                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4543                               int limit;
4544                               unsigned low, high;
4545
4546                               c++;
4547                               if (*c >= '0' && *c <= '9')
4548                                 limit = *c - '0';
4549                               else if (*c >= 'a' && *c <= 'f')
4550                                 limit = *c - 'a' + 10;
4551                               else
4552                                 abort ();
4553                               low = limit >> 2;
4554                               high = limit & 3;
4555
4556                               if (value < low || value > high)
4557                                 func (stream, "<illegal width %d>", base << value);
4558                               else
4559                                 func (stream, "%d", base << value);
4560                             }
4561                             break;
4562                           case 'R':
4563                             if (given & (1 << 6))
4564                               goto Q;
4565                             /* FALLTHROUGH */
4566                           case 'D':
4567                             func (stream, "d%ld", value);
4568                             break;
4569                           case 'Q':
4570                           Q:
4571                             if (value & 1)
4572                               func (stream, "<illegal reg q%ld.5>", value >> 1);
4573                             else
4574                               func (stream, "q%ld", value >> 1);
4575                             break;
4576
4577                           case '`':
4578                             c++;
4579                             if (value == 0)
4580                               func (stream, "%c", *c);
4581                             break;
4582                           case '\'':
4583                             c++;
4584                             if (value == ((1ul << width) - 1))
4585                               func (stream, "%c", *c);
4586                             break;
4587                           case '?':
4588                             func (stream, "%c", c[(1 << width) - (int) value]);
4589                             c += 1 << width;
4590                             break;
4591                           default:
4592                             abort ();
4593                           }
4594                       }
4595                       break;
4596
4597                     default:
4598                       abort ();
4599                     }
4600                 }
4601               else
4602                 func (stream, "%c", *c);
4603             }
4604
4605           if (value_in_comment > 32 || value_in_comment < -16)
4606             func (stream, "\t; 0x%lx", value_in_comment);
4607
4608           if (is_unpredictable)
4609             func (stream, UNPREDICTABLE_INSTRUCTION);
4610
4611           return TRUE;
4612         }
4613     }
4614   return FALSE;
4615 }
4616
4617 /* Return the name of a v7A special register.  */
4618
4619 static const char *
4620 banked_regname (unsigned reg)
4621 {
4622   switch (reg)
4623     {
4624       case 15: return "CPSR";
4625       case 32: return "R8_usr";
4626       case 33: return "R9_usr";
4627       case 34: return "R10_usr";
4628       case 35: return "R11_usr";
4629       case 36: return "R12_usr";
4630       case 37: return "SP_usr";
4631       case 38: return "LR_usr";
4632       case 40: return "R8_fiq";
4633       case 41: return "R9_fiq";
4634       case 42: return "R10_fiq";
4635       case 43: return "R11_fiq";
4636       case 44: return "R12_fiq";
4637       case 45: return "SP_fiq";
4638       case 46: return "LR_fiq";
4639       case 48: return "LR_irq";
4640       case 49: return "SP_irq";
4641       case 50: return "LR_svc";
4642       case 51: return "SP_svc";
4643       case 52: return "LR_abt";
4644       case 53: return "SP_abt";
4645       case 54: return "LR_und";
4646       case 55: return "SP_und";
4647       case 60: return "LR_mon";
4648       case 61: return "SP_mon";
4649       case 62: return "ELR_hyp";
4650       case 63: return "SP_hyp";
4651       case 79: return "SPSR";
4652       case 110: return "SPSR_fiq";
4653       case 112: return "SPSR_irq";
4654       case 114: return "SPSR_svc";
4655       case 116: return "SPSR_abt";
4656       case 118: return "SPSR_und";
4657       case 124: return "SPSR_mon";
4658       case 126: return "SPSR_hyp";
4659       default: return NULL;
4660     }
4661 }
4662
4663 /* Return the name of the DMB/DSB option.  */
4664 static const char *
4665 data_barrier_option (unsigned option)
4666 {
4667   switch (option & 0xf)
4668     {
4669     case 0xf: return "sy";
4670     case 0xe: return "st";
4671     case 0xd: return "ld";
4672     case 0xb: return "ish";
4673     case 0xa: return "ishst";
4674     case 0x9: return "ishld";
4675     case 0x7: return "un";
4676     case 0x6: return "unst";
4677     case 0x5: return "nshld";
4678     case 0x3: return "osh";
4679     case 0x2: return "oshst";
4680     case 0x1: return "oshld";
4681     default:  return NULL;
4682     }
4683 }
4684
4685 /* Print one ARM instruction from PC on INFO->STREAM.  */
4686
4687 static void
4688 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
4689 {
4690   const struct opcode32 *insn;
4691   void *stream = info->stream;
4692   fprintf_ftype func = info->fprintf_func;
4693   struct arm_private_data *private_data = info->private_data;
4694
4695   if (print_insn_coprocessor (pc, info, given, FALSE))
4696     return;
4697
4698   if (print_insn_neon (info, given, FALSE))
4699     return;
4700
4701   for (insn = arm_opcodes; insn->assembler; insn++)
4702     {
4703       if ((given & insn->mask) != insn->value)
4704         continue;
4705
4706       if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
4707         continue;
4708
4709       /* Special case: an instruction with all bits set in the condition field
4710          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4711          or by the catchall at the end of the table.  */
4712       if ((given & 0xF0000000) != 0xF0000000
4713           || (insn->mask & 0xF0000000) == 0xF0000000
4714           || (insn->mask == 0 && insn->value == 0))
4715         {
4716           unsigned long u_reg = 16;
4717           unsigned long U_reg = 16;
4718           bfd_boolean is_unpredictable = FALSE;
4719           signed long value_in_comment = 0;
4720           const char *c;
4721
4722           for (c = insn->assembler; *c; c++)
4723             {
4724               if (*c == '%')
4725                 {
4726                   bfd_boolean allow_unpredictable = FALSE;
4727
4728                   switch (*++c)
4729                     {
4730                     case '%':
4731                       func (stream, "%%");
4732                       break;
4733
4734                     case 'a':
4735                       value_in_comment = print_arm_address (pc, info, given);
4736                       break;
4737
4738                     case 'P':
4739                       /* Set P address bit and use normal address
4740                          printing routine.  */
4741                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
4742                       break;
4743
4744                     case 'S':
4745                       allow_unpredictable = TRUE;
4746                       /* Fall through.  */
4747                     case 's':
4748                       if ((given & 0x004f0000) == 0x004f0000)
4749                         {
4750                           /* PC relative with immediate offset.  */
4751                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
4752
4753                           if (PRE_BIT_SET)
4754                             {
4755                               /* Elide positive zero offset.  */
4756                               if (offset || NEGATIVE_BIT_SET)
4757                                 func (stream, "[pc, #%s%d]\t; ",
4758                                       NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4759                               else
4760                                 func (stream, "[pc]\t; ");
4761                               if (NEGATIVE_BIT_SET)
4762                                 offset = -offset;
4763                               info->print_address_func (offset + pc + 8, info);
4764                             }
4765                           else
4766                             {
4767                               /* Always show the offset.  */
4768                               func (stream, "[pc], #%s%d",
4769                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4770                               if (! allow_unpredictable)
4771                                 is_unpredictable = TRUE;
4772                             }
4773                         }
4774                       else
4775                         {
4776                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4777
4778                           func (stream, "[%s",
4779                                 arm_regnames[(given >> 16) & 0xf]);
4780
4781                           if (PRE_BIT_SET)
4782                             {
4783                               if (IMMEDIATE_BIT_SET)
4784                                 {
4785                                   /* Elide offset for non-writeback
4786                                      positive zero.  */
4787                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4788                                       || offset)
4789                                     func (stream, ", #%s%d",
4790                                           NEGATIVE_BIT_SET ? "-" : "", offset);
4791
4792                                   if (NEGATIVE_BIT_SET)
4793                                     offset = -offset;
4794
4795                                   value_in_comment = offset;
4796                                 }
4797                               else
4798                                 {
4799                                   /* Register Offset or Register Pre-Indexed.  */
4800                                   func (stream, ", %s%s",
4801                                         NEGATIVE_BIT_SET ? "-" : "",
4802                                         arm_regnames[given & 0xf]);
4803
4804                                   /* Writing back to the register that is the source/
4805                                      destination of the load/store is unpredictable.  */
4806                                   if (! allow_unpredictable
4807                                       && WRITEBACK_BIT_SET
4808                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
4809                                     is_unpredictable = TRUE;
4810                                 }
4811
4812                               func (stream, "]%s",
4813                                     WRITEBACK_BIT_SET ? "!" : "");
4814                             }
4815                           else
4816                             {
4817                               if (IMMEDIATE_BIT_SET)
4818                                 {
4819                                   /* Immediate Post-indexed.  */
4820                                   /* PR 10924: Offset must be printed, even if it is zero.  */
4821                                   func (stream, "], #%s%d",
4822                                         NEGATIVE_BIT_SET ? "-" : "", offset);
4823                                   if (NEGATIVE_BIT_SET)
4824                                     offset = -offset;
4825                                   value_in_comment = offset;
4826                                 }
4827                               else
4828                                 {
4829                                   /* Register Post-indexed.  */
4830                                   func (stream, "], %s%s",
4831                                         NEGATIVE_BIT_SET ? "-" : "",
4832                                         arm_regnames[given & 0xf]);
4833
4834                                   /* Writing back to the register that is the source/
4835                                      destination of the load/store is unpredictable.  */
4836                                   if (! allow_unpredictable
4837                                       && (given & 0xf) == ((given >> 12) & 0xf))
4838                                     is_unpredictable = TRUE;
4839                                 }
4840
4841                               if (! allow_unpredictable)
4842                                 {
4843                                   /* Writeback is automatically implied by post- addressing.
4844                                      Setting the W bit is unnecessary and ARM specify it as
4845                                      being unpredictable.  */
4846                                   if (WRITEBACK_BIT_SET
4847                                       /* Specifying the PC register as the post-indexed
4848                                          registers is also unpredictable.  */
4849                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4850                                     is_unpredictable = TRUE;
4851                                 }
4852                             }
4853                         }
4854                       break;
4855
4856                     case 'b':
4857                       {
4858                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
4859                         info->print_address_func (disp * 4 + pc + 8, info);
4860                       }
4861                       break;
4862
4863                     case 'c':
4864                       if (((given >> 28) & 0xf) != 0xe)
4865                         func (stream, "%s",
4866                               arm_conditional [(given >> 28) & 0xf]);
4867                       break;
4868
4869                     case 'm':
4870                       {
4871                         int started = 0;
4872                         int reg;
4873
4874                         func (stream, "{");
4875                         for (reg = 0; reg < 16; reg++)
4876                           if ((given & (1 << reg)) != 0)
4877                             {
4878                               if (started)
4879                                 func (stream, ", ");
4880                               started = 1;
4881                               func (stream, "%s", arm_regnames[reg]);
4882                             }
4883                         func (stream, "}");
4884                         if (! started)
4885                           is_unpredictable = TRUE;
4886                       }
4887                       break;
4888
4889                     case 'q':
4890                       arm_decode_shift (given, func, stream, FALSE);
4891                       break;
4892
4893                     case 'o':
4894                       if ((given & 0x02000000) != 0)
4895                         {
4896                           unsigned int rotate = (given & 0xf00) >> 7;
4897                           unsigned int immed = (given & 0xff);
4898                           unsigned int a, i;
4899
4900                           a = (((immed << (32 - rotate))
4901                                 | (immed >> rotate)) & 0xffffffff);
4902                           /* If there is another encoding with smaller rotate,
4903                              the rotate should be specified directly.  */
4904                           for (i = 0; i < 32; i += 2)
4905                             if ((a << i | a >> (32 - i)) <= 0xff)
4906                               break;
4907
4908                           if (i != rotate)
4909                             func (stream, "#%d, %d", immed, rotate);
4910                           else
4911                             func (stream, "#%d", a);
4912                           value_in_comment = a;
4913                         }
4914                       else
4915                         arm_decode_shift (given, func, stream, TRUE);
4916                       break;
4917
4918                     case 'p':
4919                       if ((given & 0x0000f000) == 0x0000f000)
4920                         {
4921                           arm_feature_set arm_ext_v6 =
4922                             ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4923
4924                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4925                              mechanism for setting PSR flag bits.  They are
4926                              obsolete in V6 onwards.  */
4927                           if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4928                                                      arm_ext_v6))
4929                             func (stream, "p");
4930                           else
4931                             is_unpredictable = TRUE;
4932                         }
4933                       break;
4934
4935                     case 't':
4936                       if ((given & 0x01200000) == 0x00200000)
4937                         func (stream, "t");
4938                       break;
4939
4940                     case 'A':
4941                       {
4942                         int offset = given & 0xff;
4943
4944                         value_in_comment = offset * 4;
4945                         if (NEGATIVE_BIT_SET)
4946                           value_in_comment = - value_in_comment;
4947
4948                         func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
4949
4950                         if (PRE_BIT_SET)
4951                           {
4952                             if (offset)
4953                               func (stream, ", #%d]%s",
4954                                     (int) value_in_comment,
4955                                     WRITEBACK_BIT_SET ? "!" : "");
4956                             else
4957                               func (stream, "]");
4958                           }
4959                         else
4960                           {
4961                             func (stream, "]");
4962
4963                             if (WRITEBACK_BIT_SET)
4964                               {
4965                                 if (offset)
4966                                   func (stream, ", #%d", (int) value_in_comment);
4967                               }
4968                             else
4969                               {
4970                                 func (stream, ", {%d}", (int) offset);
4971                                 value_in_comment = offset;
4972                               }
4973                           }
4974                       }
4975                       break;
4976
4977                     case 'B':
4978                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
4979                       {
4980                         bfd_vma address;
4981                         bfd_vma offset = 0;
4982
4983                         if (! NEGATIVE_BIT_SET)
4984                           /* Is signed, hi bits should be ones.  */
4985                           offset = (-1) ^ 0x00ffffff;
4986
4987                         /* Offset is (SignExtend(offset field)<<2).  */
4988                         offset += given & 0x00ffffff;
4989                         offset <<= 2;
4990                         address = offset + pc + 8;
4991
4992                         if (given & 0x01000000)
4993                           /* H bit allows addressing to 2-byte boundaries.  */
4994                           address += 2;
4995
4996                         info->print_address_func (address, info);
4997                       }
4998                       break;
4999
5000                     case 'C':
5001                       if ((given & 0x02000200) == 0x200)
5002                         {
5003                           const char * name;
5004                           unsigned sysm = (given & 0x004f0000) >> 16;
5005
5006                           sysm |= (given & 0x300) >> 4;
5007                           name = banked_regname (sysm);
5008
5009                           if (name != NULL)
5010                             func (stream, "%s", name);
5011                           else
5012                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5013                         }
5014                       else
5015                         {
5016                           func (stream, "%cPSR_",
5017                                 (given & 0x00400000) ? 'S' : 'C');
5018                           if (given & 0x80000)
5019                             func (stream, "f");
5020                           if (given & 0x40000)
5021                             func (stream, "s");
5022                           if (given & 0x20000)
5023                             func (stream, "x");
5024                           if (given & 0x10000)
5025                             func (stream, "c");
5026                         }
5027                       break;
5028
5029                     case 'U':
5030                       if ((given & 0xf0) == 0x60)
5031                         {
5032                           switch (given & 0xf)
5033                             {
5034                             case 0xf: func (stream, "sy"); break;
5035                             default:
5036                               func (stream, "#%d", (int) given & 0xf);
5037                               break;
5038                             }
5039                         }
5040                       else
5041                         {
5042                           const char * opt = data_barrier_option (given & 0xf);
5043                           if (opt != NULL)
5044                             func (stream, "%s", opt);
5045                           else
5046                               func (stream, "#%d", (int) given & 0xf);
5047                         }
5048                       break;
5049
5050                     case '0': case '1': case '2': case '3': case '4':
5051                     case '5': case '6': case '7': case '8': case '9':
5052                       {
5053                         int width;
5054                         unsigned long value;
5055
5056                         c = arm_decode_bitfield (c, given, &value, &width);
5057
5058                         switch (*c)
5059                           {
5060                           case 'R':
5061                             if (value == 15)
5062                               is_unpredictable = TRUE;
5063                             /* Fall through.  */
5064                           case 'r':
5065                           case 'T':
5066                             /* We want register + 1 when decoding T.  */
5067                             if (*c == 'T')
5068                               ++value;
5069
5070                             if (c[1] == 'u')
5071                               {
5072                                 /* Eat the 'u' character.  */
5073                                 ++ c;
5074
5075                                 if (u_reg == value)
5076                                   is_unpredictable = TRUE;
5077                                 u_reg = value;
5078                               }
5079                             if (c[1] == 'U')
5080                               {
5081                                 /* Eat the 'U' character.  */
5082                                 ++ c;
5083
5084                                 if (U_reg == value)
5085                                   is_unpredictable = TRUE;
5086                                 U_reg = value;
5087                               }
5088                             func (stream, "%s", arm_regnames[value]);
5089                             break;
5090                           case 'd':
5091                             func (stream, "%ld", value);
5092                             value_in_comment = value;
5093                             break;
5094                           case 'b':
5095                             func (stream, "%ld", value * 8);
5096                             value_in_comment = value * 8;
5097                             break;
5098                           case 'W':
5099                             func (stream, "%ld", value + 1);
5100                             value_in_comment = value + 1;
5101                             break;
5102                           case 'x':
5103                             func (stream, "0x%08lx", value);
5104
5105                             /* Some SWI instructions have special
5106                                meanings.  */
5107                             if ((given & 0x0fffffff) == 0x0FF00000)
5108                               func (stream, "\t; IMB");
5109                             else if ((given & 0x0fffffff) == 0x0FF00001)
5110                               func (stream, "\t; IMBRange");
5111                             break;
5112                           case 'X':
5113                             func (stream, "%01lx", value & 0xf);
5114                             value_in_comment = value;
5115                             break;
5116                           case '`':
5117                             c++;
5118                             if (value == 0)
5119                               func (stream, "%c", *c);
5120                             break;
5121                           case '\'':
5122                             c++;
5123                             if (value == ((1ul << width) - 1))
5124                               func (stream, "%c", *c);
5125                             break;
5126                           case '?':
5127                             func (stream, "%c", c[(1 << width) - (int) value]);
5128                             c += 1 << width;
5129                             break;
5130                           default:
5131                             abort ();
5132                           }
5133                       }
5134                       break;
5135
5136                     case 'e':
5137                       {
5138                         int imm;
5139
5140                         imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5141                         func (stream, "%d", imm);
5142                         value_in_comment = imm;
5143                       }
5144                       break;
5145
5146                     case 'E':
5147                       /* LSB and WIDTH fields of BFI or BFC.  The machine-
5148                          language instruction encodes LSB and MSB.  */
5149                       {
5150                         long msb = (given & 0x001f0000) >> 16;
5151                         long lsb = (given & 0x00000f80) >> 7;
5152                         long w = msb - lsb + 1;
5153
5154                         if (w > 0)
5155                           func (stream, "#%lu, #%lu", lsb, w);
5156                         else
5157                           func (stream, "(invalid: %lu:%lu)", lsb, msb);
5158                       }
5159                       break;
5160
5161                     case 'R':
5162                       /* Get the PSR/banked register name.  */
5163                       {
5164                         const char * name;
5165                         unsigned sysm = (given & 0x004f0000) >> 16;
5166
5167                         sysm |= (given & 0x300) >> 4;
5168                         name = banked_regname (sysm);
5169
5170                         if (name != NULL)
5171                           func (stream, "%s", name);
5172                         else
5173                           func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5174                       }
5175                       break;
5176
5177                     case 'V':
5178                       /* 16-bit unsigned immediate from a MOVT or MOVW
5179                          instruction, encoded in bits 0:11 and 15:19.  */
5180                       {
5181                         long hi = (given & 0x000f0000) >> 4;
5182                         long lo = (given & 0x00000fff);
5183                         long imm16 = hi | lo;
5184
5185                         func (stream, "#%lu", imm16);
5186                         value_in_comment = imm16;
5187                       }
5188                       break;
5189
5190                     default:
5191                       abort ();
5192                     }
5193                 }
5194               else
5195                 func (stream, "%c", *c);
5196             }
5197
5198           if (value_in_comment > 32 || value_in_comment < -16)
5199             func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
5200
5201           if (is_unpredictable)
5202             func (stream, UNPREDICTABLE_INSTRUCTION);
5203
5204           return;
5205         }
5206     }
5207   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
5208   return;
5209 }
5210
5211 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
5212
5213 static void
5214 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
5215 {
5216   const struct opcode16 *insn;
5217   void *stream = info->stream;
5218   fprintf_ftype func = info->fprintf_func;
5219
5220   for (insn = thumb_opcodes; insn->assembler; insn++)
5221     if ((given & insn->mask) == insn->value)
5222       {
5223         signed long value_in_comment = 0;
5224         const char *c = insn->assembler;
5225
5226         for (; *c; c++)
5227           {
5228             int domaskpc = 0;
5229             int domasklr = 0;
5230
5231             if (*c != '%')
5232               {
5233                 func (stream, "%c", *c);
5234                 continue;
5235               }
5236
5237             switch (*++c)
5238               {
5239               case '%':
5240                 func (stream, "%%");
5241                 break;
5242
5243               case 'c':
5244                 if (ifthen_state)
5245                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5246                 break;
5247
5248               case 'C':
5249                 if (ifthen_state)
5250                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5251                 else
5252                   func (stream, "s");
5253                 break;
5254
5255               case 'I':
5256                 {
5257                   unsigned int tmp;
5258
5259                   ifthen_next_state = given & 0xff;
5260                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5261                     func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5262                   func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5263                 }
5264                 break;
5265
5266               case 'x':
5267                 if (ifthen_next_state)
5268                   func (stream, "\t; unpredictable branch in IT block\n");
5269                 break;
5270
5271               case 'X':
5272                 if (ifthen_state)
5273                   func (stream, "\t; unpredictable <IT:%s>",
5274                         arm_conditional[IFTHEN_COND]);
5275                 break;
5276
5277               case 'S':
5278                 {
5279                   long reg;
5280
5281                   reg = (given >> 3) & 0x7;
5282                   if (given & (1 << 6))
5283                     reg += 8;
5284
5285                   func (stream, "%s", arm_regnames[reg]);
5286                 }
5287                 break;
5288
5289               case 'D':
5290                 {
5291                   long reg;
5292
5293                   reg = given & 0x7;
5294                   if (given & (1 << 7))
5295                     reg += 8;
5296
5297                   func (stream, "%s", arm_regnames[reg]);
5298                 }
5299                 break;
5300
5301               case 'N':
5302                 if (given & (1 << 8))
5303                   domasklr = 1;
5304                 /* Fall through.  */
5305               case 'O':
5306                 if (*c == 'O' && (given & (1 << 8)))
5307                   domaskpc = 1;
5308                 /* Fall through.  */
5309               case 'M':
5310                 {
5311                   int started = 0;
5312                   int reg;
5313
5314                   func (stream, "{");
5315
5316                   /* It would be nice if we could spot
5317                      ranges, and generate the rS-rE format: */
5318                   for (reg = 0; (reg < 8); reg++)
5319                     if ((given & (1 << reg)) != 0)
5320                       {
5321                         if (started)
5322                           func (stream, ", ");
5323                         started = 1;
5324                         func (stream, "%s", arm_regnames[reg]);
5325                       }
5326
5327                   if (domasklr)
5328                     {
5329                       if (started)
5330                         func (stream, ", ");
5331                       started = 1;
5332                       func (stream, "%s", arm_regnames[14] /* "lr" */);
5333                     }
5334
5335                   if (domaskpc)
5336                     {
5337                       if (started)
5338                         func (stream, ", ");
5339                       func (stream, "%s", arm_regnames[15] /* "pc" */);
5340                     }
5341
5342                   func (stream, "}");
5343                 }
5344                 break;
5345
5346               case 'W':
5347                 /* Print writeback indicator for a LDMIA.  We are doing a
5348                    writeback if the base register is not in the register
5349                    mask.  */
5350                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5351                   func (stream, "!");
5352                 break;
5353
5354               case 'b':
5355                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
5356                 {
5357                   bfd_vma address = (pc + 4
5358                                      + ((given & 0x00f8) >> 2)
5359                                      + ((given & 0x0200) >> 3));
5360                   info->print_address_func (address, info);
5361                 }
5362                 break;
5363
5364               case 's':
5365                 /* Right shift immediate -- bits 6..10; 1-31 print
5366                    as themselves, 0 prints as 32.  */
5367                 {
5368                   long imm = (given & 0x07c0) >> 6;
5369                   if (imm == 0)
5370                     imm = 32;
5371                   func (stream, "#%ld", imm);
5372                 }
5373                 break;
5374
5375               case '0': case '1': case '2': case '3': case '4':
5376               case '5': case '6': case '7': case '8': case '9':
5377                 {
5378                   int bitstart = *c++ - '0';
5379                   int bitend = 0;
5380
5381                   while (*c >= '0' && *c <= '9')
5382                     bitstart = (bitstart * 10) + *c++ - '0';
5383
5384                   switch (*c)
5385                     {
5386                     case '-':
5387                       {
5388                         bfd_vma reg;
5389
5390                         c++;
5391                         while (*c >= '0' && *c <= '9')
5392                           bitend = (bitend * 10) + *c++ - '0';
5393                         if (!bitend)
5394                           abort ();
5395                         reg = given >> bitstart;
5396                         reg &= (2 << (bitend - bitstart)) - 1;
5397
5398                         switch (*c)
5399                           {
5400                           case 'r':
5401                             func (stream, "%s", arm_regnames[reg]);
5402                             break;
5403
5404                           case 'd':
5405                             func (stream, "%ld", (long) reg);
5406                             value_in_comment = reg;
5407                             break;
5408
5409                           case 'H':
5410                             func (stream, "%ld", (long) (reg << 1));
5411                             value_in_comment = reg << 1;
5412                             break;
5413
5414                           case 'W':
5415                             func (stream, "%ld", (long) (reg << 2));
5416                             value_in_comment = reg << 2;
5417                             break;
5418
5419                           case 'a':
5420                             /* PC-relative address -- the bottom two
5421                                bits of the address are dropped
5422                                before the calculation.  */
5423                             info->print_address_func
5424                               (((pc + 4) & ~3) + (reg << 2), info);
5425                             value_in_comment = 0;
5426                             break;
5427
5428                           case 'x':
5429                             func (stream, "0x%04lx", (long) reg);
5430                             break;
5431
5432                           case 'B':
5433                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
5434                             info->print_address_func (reg * 2 + pc + 4, info);
5435                             value_in_comment = 0;
5436                             break;
5437
5438                           case 'c':
5439                             func (stream, "%s", arm_conditional [reg]);
5440                             break;
5441
5442                           default:
5443                             abort ();
5444                           }
5445                       }
5446                       break;
5447
5448                     case '\'':
5449                       c++;
5450                       if ((given & (1 << bitstart)) != 0)
5451                         func (stream, "%c", *c);
5452                       break;
5453
5454                     case '?':
5455                       ++c;
5456                       if ((given & (1 << bitstart)) != 0)
5457                         func (stream, "%c", *c++);
5458                       else
5459                         func (stream, "%c", *++c);
5460                       break;
5461
5462                     default:
5463                       abort ();
5464                     }
5465                 }
5466                 break;
5467
5468               default:
5469                 abort ();
5470               }
5471           }
5472
5473         if (value_in_comment > 32 || value_in_comment < -16)
5474           func (stream, "\t; 0x%lx", value_in_comment);
5475         return;
5476       }
5477
5478   /* No match.  */
5479   func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
5480   return;
5481 }
5482
5483 /* Return the name of an V7M special register.  */
5484
5485 static const char *
5486 psr_name (int regno)
5487 {
5488   switch (regno)
5489     {
5490     case 0x0: return "APSR";
5491     case 0x1: return "IAPSR";
5492     case 0x2: return "EAPSR";
5493     case 0x3: return "PSR";
5494     case 0x5: return "IPSR";
5495     case 0x6: return "EPSR";
5496     case 0x7: return "IEPSR";
5497     case 0x8: return "MSP";
5498     case 0x9: return "PSP";
5499     case 0xa: return "MSPLIM";
5500     case 0xb: return "PSPLIM";
5501     case 0x10: return "PRIMASK";
5502     case 0x11: return "BASEPRI";
5503     case 0x12: return "BASEPRI_MAX";
5504     case 0x13: return "FAULTMASK";
5505     case 0x14: return "CONTROL";
5506     case 0x88: return "MSP_NS";
5507     case 0x89: return "PSP_NS";
5508     case 0x8a: return "MSPLIM_NS";
5509     case 0x8b: return "PSPLIM_NS";
5510     case 0x90: return "PRIMASK_NS";
5511     case 0x91: return "BASEPRI_NS";
5512     case 0x93: return "FAULTMASK_NS";
5513     case 0x94: return "CONTROL_NS";
5514     case 0x98: return "SP_NS";
5515     default: return "<unknown>";
5516     }
5517 }
5518
5519 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
5520
5521 static void
5522 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
5523 {
5524   const struct opcode32 *insn;
5525   void *stream = info->stream;
5526   fprintf_ftype func = info->fprintf_func;
5527
5528   if (print_insn_coprocessor (pc, info, given, TRUE))
5529     return;
5530
5531   if (print_insn_neon (info, given, TRUE))
5532     return;
5533
5534   for (insn = thumb32_opcodes; insn->assembler; insn++)
5535     if ((given & insn->mask) == insn->value)
5536       {
5537         bfd_boolean is_unpredictable = FALSE;
5538         signed long value_in_comment = 0;
5539         const char *c = insn->assembler;
5540
5541         for (; *c; c++)
5542           {
5543             if (*c != '%')
5544               {
5545                 func (stream, "%c", *c);
5546                 continue;
5547               }
5548
5549             switch (*++c)
5550               {
5551               case '%':
5552                 func (stream, "%%");
5553                 break;
5554
5555               case 'c':
5556                 if (ifthen_state)
5557                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5558                 break;
5559
5560               case 'x':
5561                 if (ifthen_next_state)
5562                   func (stream, "\t; unpredictable branch in IT block\n");
5563                 break;
5564
5565               case 'X':
5566                 if (ifthen_state)
5567                   func (stream, "\t; unpredictable <IT:%s>",
5568                         arm_conditional[IFTHEN_COND]);
5569                 break;
5570
5571               case 'I':
5572                 {
5573                   unsigned int imm12 = 0;
5574
5575                   imm12 |= (given & 0x000000ffu);
5576                   imm12 |= (given & 0x00007000u) >> 4;
5577                   imm12 |= (given & 0x04000000u) >> 15;
5578                   func (stream, "#%u", imm12);
5579                   value_in_comment = imm12;
5580                 }
5581                 break;
5582
5583               case 'M':
5584                 {
5585                   unsigned int bits = 0, imm, imm8, mod;
5586
5587                   bits |= (given & 0x000000ffu);
5588                   bits |= (given & 0x00007000u) >> 4;
5589                   bits |= (given & 0x04000000u) >> 15;
5590                   imm8 = (bits & 0x0ff);
5591                   mod = (bits & 0xf00) >> 8;
5592                   switch (mod)
5593                     {
5594                     case 0: imm = imm8; break;
5595                     case 1: imm = ((imm8 << 16) | imm8); break;
5596                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5597                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
5598                     default:
5599                       mod  = (bits & 0xf80) >> 7;
5600                       imm8 = (bits & 0x07f) | 0x80;
5601                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5602                     }
5603                   func (stream, "#%u", imm);
5604                   value_in_comment = imm;
5605                 }
5606                 break;
5607
5608               case 'J':
5609                 {
5610                   unsigned int imm = 0;
5611
5612                   imm |= (given & 0x000000ffu);
5613                   imm |= (given & 0x00007000u) >> 4;
5614                   imm |= (given & 0x04000000u) >> 15;
5615                   imm |= (given & 0x000f0000u) >> 4;
5616                   func (stream, "#%u", imm);
5617                   value_in_comment = imm;
5618                 }
5619                 break;
5620
5621               case 'K':
5622                 {
5623                   unsigned int imm = 0;
5624
5625                   imm |= (given & 0x000f0000u) >> 16;
5626                   imm |= (given & 0x00000ff0u) >> 0;
5627                   imm |= (given & 0x0000000fu) << 12;
5628                   func (stream, "#%u", imm);
5629                   value_in_comment = imm;
5630                 }
5631                 break;
5632
5633               case 'H':
5634                 {
5635                   unsigned int imm = 0;
5636
5637                   imm |= (given & 0x000f0000u) >> 4;
5638                   imm |= (given & 0x00000fffu) >> 0;
5639                   func (stream, "#%u", imm);
5640                   value_in_comment = imm;
5641                 }
5642                 break;
5643
5644               case 'V':
5645                 {
5646                   unsigned int imm = 0;
5647
5648                   imm |= (given & 0x00000fffu);
5649                   imm |= (given & 0x000f0000u) >> 4;
5650                   func (stream, "#%u", imm);
5651                   value_in_comment = imm;
5652                 }
5653                 break;
5654
5655               case 'S':
5656                 {
5657                   unsigned int reg = (given & 0x0000000fu);
5658                   unsigned int stp = (given & 0x00000030u) >> 4;
5659                   unsigned int imm = 0;
5660                   imm |= (given & 0x000000c0u) >> 6;
5661                   imm |= (given & 0x00007000u) >> 10;
5662
5663                   func (stream, "%s", arm_regnames[reg]);
5664                   switch (stp)
5665                     {
5666                     case 0:
5667                       if (imm > 0)
5668                         func (stream, ", lsl #%u", imm);
5669                       break;
5670
5671                     case 1:
5672                       if (imm == 0)
5673                         imm = 32;
5674                       func (stream, ", lsr #%u", imm);
5675                       break;
5676
5677                     case 2:
5678                       if (imm == 0)
5679                         imm = 32;
5680                       func (stream, ", asr #%u", imm);
5681                       break;
5682
5683                     case 3:
5684                       if (imm == 0)
5685                         func (stream, ", rrx");
5686                       else
5687                         func (stream, ", ror #%u", imm);
5688                     }
5689                 }
5690                 break;
5691
5692               case 'a':
5693                 {
5694                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5695                   unsigned int U   = ! NEGATIVE_BIT_SET;
5696                   unsigned int op  = (given & 0x00000f00) >> 8;
5697                   unsigned int i12 = (given & 0x00000fff);
5698                   unsigned int i8  = (given & 0x000000ff);
5699                   bfd_boolean writeback = FALSE, postind = FALSE;
5700                   bfd_vma offset = 0;
5701
5702                   func (stream, "[%s", arm_regnames[Rn]);
5703                   if (U) /* 12-bit positive immediate offset.  */
5704                     {
5705                       offset = i12;
5706                       if (Rn != 15)
5707                         value_in_comment = offset;
5708                     }
5709                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
5710                     offset = - (int) i12;
5711                   else if (op == 0x0) /* Shifted register offset.  */
5712                     {
5713                       unsigned int Rm = (i8 & 0x0f);
5714                       unsigned int sh = (i8 & 0x30) >> 4;
5715
5716                       func (stream, ", %s", arm_regnames[Rm]);
5717                       if (sh)
5718                         func (stream, ", lsl #%u", sh);
5719                       func (stream, "]");
5720                       break;
5721                     }
5722                   else switch (op)
5723                     {
5724                     case 0xE:  /* 8-bit positive immediate offset.  */
5725                       offset = i8;
5726                       break;
5727
5728                     case 0xC:  /* 8-bit negative immediate offset.  */
5729                       offset = -i8;
5730                       break;
5731
5732                     case 0xF:  /* 8-bit + preindex with wb.  */
5733                       offset = i8;
5734                       writeback = TRUE;
5735                       break;
5736
5737                     case 0xD:  /* 8-bit - preindex with wb.  */
5738                       offset = -i8;
5739                       writeback = TRUE;
5740                       break;
5741
5742                     case 0xB:  /* 8-bit + postindex.  */
5743                       offset = i8;
5744                       postind = TRUE;
5745                       break;
5746
5747                     case 0x9:  /* 8-bit - postindex.  */
5748                       offset = -i8;
5749                       postind = TRUE;
5750                       break;
5751
5752                     default:
5753                       func (stream, ", <undefined>]");
5754                       goto skip;
5755                     }
5756
5757                   if (postind)
5758                     func (stream, "], #%d", (int) offset);
5759                   else
5760                     {
5761                       if (offset)
5762                         func (stream, ", #%d", (int) offset);
5763                       func (stream, writeback ? "]!" : "]");
5764                     }
5765
5766                   if (Rn == 15)
5767                     {
5768                       func (stream, "\t; ");
5769                       info->print_address_func (((pc + 4) & ~3) + offset, info);
5770                     }
5771                 }
5772               skip:
5773                 break;
5774
5775               case 'A':
5776                 {
5777                   unsigned int U   = ! NEGATIVE_BIT_SET;
5778                   unsigned int W   = WRITEBACK_BIT_SET;
5779                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5780                   unsigned int off = (given & 0x000000ff);
5781
5782                   func (stream, "[%s", arm_regnames[Rn]);
5783
5784                   if (PRE_BIT_SET)
5785                     {
5786                       if (off || !U)
5787                         {
5788                           func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5789                           value_in_comment = off * 4 * (U ? 1 : -1);
5790                         }
5791                       func (stream, "]");
5792                       if (W)
5793                         func (stream, "!");
5794                     }
5795                   else
5796                     {
5797                       func (stream, "], ");
5798                       if (W)
5799                         {
5800                           func (stream, "#%c%u", U ? '+' : '-', off * 4);
5801                           value_in_comment = off * 4 * (U ? 1 : -1);
5802                         }
5803                       else
5804                         {
5805                           func (stream, "{%u}", off);
5806                           value_in_comment = off;
5807                         }
5808                     }
5809                 }
5810                 break;
5811
5812               case 'w':
5813                 {
5814                   unsigned int Sbit = (given & 0x01000000) >> 24;
5815                   unsigned int type = (given & 0x00600000) >> 21;
5816
5817                   switch (type)
5818                     {
5819                     case 0: func (stream, Sbit ? "sb" : "b"); break;
5820                     case 1: func (stream, Sbit ? "sh" : "h"); break;
5821                     case 2:
5822                       if (Sbit)
5823                         func (stream, "??");
5824                       break;
5825                     case 3:
5826                       func (stream, "??");
5827                       break;
5828                     }
5829                 }
5830                 break;
5831
5832               case 'm':
5833                 {
5834                   int started = 0;
5835                   int reg;
5836
5837                   func (stream, "{");
5838                   for (reg = 0; reg < 16; reg++)
5839                     if ((given & (1 << reg)) != 0)
5840                       {
5841                         if (started)
5842                           func (stream, ", ");
5843                         started = 1;
5844                         func (stream, "%s", arm_regnames[reg]);
5845                       }
5846                   func (stream, "}");
5847                 }
5848                 break;
5849
5850               case 'E':
5851                 {
5852                   unsigned int msb = (given & 0x0000001f);
5853                   unsigned int lsb = 0;
5854
5855                   lsb |= (given & 0x000000c0u) >> 6;
5856                   lsb |= (given & 0x00007000u) >> 10;
5857                   func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5858                 }
5859                 break;
5860
5861               case 'F':
5862                 {
5863                   unsigned int width = (given & 0x0000001f) + 1;
5864                   unsigned int lsb = 0;
5865
5866                   lsb |= (given & 0x000000c0u) >> 6;
5867                   lsb |= (given & 0x00007000u) >> 10;
5868                   func (stream, "#%u, #%u", lsb, width);
5869                 }
5870                 break;
5871
5872               case 'G':
5873                 {
5874                   unsigned int boff = (((given & 0x07800000) >> 23) << 1);
5875                   func (stream, "%x", boff);
5876                 }
5877                 break;
5878
5879               case 'W':
5880                 {
5881                   unsigned int immA = (given & 0x001f0000u) >> 16;
5882                   unsigned int immB = (given & 0x000007feu) >> 1;
5883                   unsigned int immC = (given & 0x00000800u) >> 11;
5884                   bfd_vma offset = 0;
5885
5886                   offset |= immA << 12;
5887                   offset |= immB << 2;
5888                   offset |= immC << 1;
5889                   /* Sign extend.  */
5890                   offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
5891
5892                   info->print_address_func (pc + 4 + offset, info);
5893                 }
5894                 break;
5895
5896               case 'b':
5897                 {
5898                   unsigned int S = (given & 0x04000000u) >> 26;
5899                   unsigned int J1 = (given & 0x00002000u) >> 13;
5900                   unsigned int J2 = (given & 0x00000800u) >> 11;
5901                   bfd_vma offset = 0;
5902
5903                   offset |= !S << 20;
5904                   offset |= J2 << 19;
5905                   offset |= J1 << 18;
5906                   offset |= (given & 0x003f0000) >> 4;
5907                   offset |= (given & 0x000007ff) << 1;
5908                   offset -= (1 << 20);
5909
5910                   info->print_address_func (pc + 4 + offset, info);
5911                 }
5912                 break;
5913
5914               case 'B':
5915                 {
5916                   unsigned int S = (given & 0x04000000u) >> 26;
5917                   unsigned int I1 = (given & 0x00002000u) >> 13;
5918                   unsigned int I2 = (given & 0x00000800u) >> 11;
5919                   bfd_vma offset = 0;
5920
5921                   offset |= !S << 24;
5922                   offset |= !(I1 ^ S) << 23;
5923                   offset |= !(I2 ^ S) << 22;
5924                   offset |= (given & 0x03ff0000u) >> 4;
5925                   offset |= (given & 0x000007ffu) << 1;
5926                   offset -= (1 << 24);
5927                   offset += pc + 4;
5928
5929                   /* BLX target addresses are always word aligned.  */
5930                   if ((given & 0x00001000u) == 0)
5931                       offset &= ~2u;
5932
5933                   info->print_address_func (offset, info);
5934                 }
5935                 break;
5936
5937               case 's':
5938                 {
5939                   unsigned int shift = 0;
5940
5941                   shift |= (given & 0x000000c0u) >> 6;
5942                   shift |= (given & 0x00007000u) >> 10;
5943                   if (WRITEBACK_BIT_SET)
5944                     func (stream, ", asr #%u", shift);
5945                   else if (shift)
5946                     func (stream, ", lsl #%u", shift);
5947                   /* else print nothing - lsl #0 */
5948                 }
5949                 break;
5950
5951               case 'R':
5952                 {
5953                   unsigned int rot = (given & 0x00000030) >> 4;
5954
5955                   if (rot)
5956                     func (stream, ", ror #%u", rot * 8);
5957                 }
5958                 break;
5959
5960               case 'U':
5961                 if ((given & 0xf0) == 0x60)
5962                   {
5963                     switch (given & 0xf)
5964                       {
5965                         case 0xf: func (stream, "sy"); break;
5966                         default:
5967                           func (stream, "#%d", (int) given & 0xf);
5968                               break;
5969                       }
5970                   }
5971                 else
5972                   {
5973                     const char * opt = data_barrier_option (given & 0xf);
5974                     if (opt != NULL)
5975                       func (stream, "%s", opt);
5976                     else
5977                       func (stream, "#%d", (int) given & 0xf);
5978                    }
5979                 break;
5980
5981               case 'C':
5982                 if ((given & 0xff) == 0)
5983                   {
5984                     func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5985                     if (given & 0x800)
5986                       func (stream, "f");
5987                     if (given & 0x400)
5988                       func (stream, "s");
5989                     if (given & 0x200)
5990                       func (stream, "x");
5991                     if (given & 0x100)
5992                       func (stream, "c");
5993                   }
5994                 else if ((given & 0x20) == 0x20)
5995                   {
5996                     char const* name;
5997                     unsigned sysm = (given & 0xf00) >> 8;
5998
5999                     sysm |= (given & 0x30);
6000                     sysm |= (given & 0x00100000) >> 14;
6001                     name = banked_regname (sysm);
6002
6003                     if (name != NULL)
6004                       func (stream, "%s", name);
6005                     else
6006                       func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
6007                   }
6008                 else
6009                   {
6010                     func (stream, "%s", psr_name (given & 0xff));
6011                   }
6012                 break;
6013
6014               case 'D':
6015                 if (((given & 0xff) == 0)
6016                     || ((given & 0x20) == 0x20))
6017                   {
6018                     char const* name;
6019                     unsigned sm = (given & 0xf0000) >> 16;
6020
6021                     sm |= (given & 0x30);
6022                     sm |= (given & 0x00100000) >> 14;
6023                     name = banked_regname (sm);
6024
6025                     if (name != NULL)
6026                       func (stream, "%s", name);
6027                     else
6028                       func (stream, "(UNDEF: %lu)", (unsigned long) sm);
6029                   }
6030                 else
6031                   func (stream, "%s", psr_name (given & 0xff));
6032                 break;
6033
6034               case '0': case '1': case '2': case '3': case '4':
6035               case '5': case '6': case '7': case '8': case '9':
6036                 {
6037                   int width;
6038                   unsigned long val;
6039
6040                   c = arm_decode_bitfield (c, given, &val, &width);
6041
6042                   switch (*c)
6043                     {
6044                     case 'd':
6045                       func (stream, "%lu", val);
6046                       value_in_comment = val;
6047                       break;
6048
6049                     case 'D':
6050                       func (stream, "%lu", val + 1);
6051                       value_in_comment = val + 1;
6052                       break;
6053
6054                     case 'W':
6055                       func (stream, "%lu", val * 4);
6056                       value_in_comment = val * 4;
6057                       break;
6058
6059                     case 'R':
6060                       if (val == 15)
6061                         is_unpredictable = TRUE;
6062                       /* Fall through.  */
6063                     case 'r':
6064                       func (stream, "%s", arm_regnames[val]);
6065                       break;
6066
6067                     case 'c':
6068                       func (stream, "%s", arm_conditional[val]);
6069                       break;
6070
6071                     case '\'':
6072                       c++;
6073                       if (val == ((1ul << width) - 1))
6074                         func (stream, "%c", *c);
6075                       break;
6076
6077                     case '`':
6078                       c++;
6079                       if (val == 0)
6080                         func (stream, "%c", *c);
6081                       break;
6082
6083                     case '?':
6084                       func (stream, "%c", c[(1 << width) - (int) val]);
6085                       c += 1 << width;
6086                       break;
6087
6088                     case 'x':
6089                       func (stream, "0x%lx", val & 0xffffffffUL);
6090                       break;
6091
6092                     default:
6093                       abort ();
6094                     }
6095                 }
6096                 break;
6097
6098               case 'L':
6099                 /* PR binutils/12534
6100                    If we have a PC relative offset in an LDRD or STRD
6101                    instructions then display the decoded address.  */
6102                 if (((given >> 16) & 0xf) == 0xf)
6103                   {
6104                     bfd_vma offset = (given & 0xff) * 4;
6105
6106                     if ((given & (1 << 23)) == 0)
6107                       offset = - offset;
6108                     func (stream, "\t; ");
6109                     info->print_address_func ((pc & ~3) + 4 + offset, info);
6110                   }
6111                 break;
6112
6113               default:
6114                 abort ();
6115               }
6116           }
6117
6118         if (value_in_comment > 32 || value_in_comment < -16)
6119           func (stream, "\t; 0x%lx", value_in_comment);
6120
6121         if (is_unpredictable)
6122           func (stream, UNPREDICTABLE_INSTRUCTION);
6123
6124         return;
6125       }
6126
6127   /* No match.  */
6128   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
6129   return;
6130 }
6131
6132 /* Print data bytes on INFO->STREAM.  */
6133
6134 static void
6135 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6136                  struct disassemble_info *info,
6137                  long given)
6138 {
6139   switch (info->bytes_per_chunk)
6140     {
6141     case 1:
6142       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6143       break;
6144     case 2:
6145       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6146       break;
6147     case 4:
6148       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6149       break;
6150     default:
6151       abort ();
6152     }
6153 }
6154
6155 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
6156    being displayed in symbol relative addresses.
6157
6158    Also disallow private symbol, with __tagsym$$ prefix,
6159    from ARM RVCT toolchain being displayed.  */
6160
6161 bfd_boolean
6162 arm_symbol_is_valid (asymbol * sym,
6163                      struct disassemble_info * info ATTRIBUTE_UNUSED)
6164 {
6165   const char * name;
6166
6167   if (sym == NULL)
6168     return FALSE;
6169
6170   name = bfd_asymbol_name (sym);
6171
6172   return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
6173 }
6174
6175 /* Parse the string of disassembler options.  */
6176
6177 static void
6178 parse_arm_disassembler_options (const char *options)
6179 {
6180   const char *opt;
6181
6182   FOR_EACH_DISASSEMBLER_OPTION (opt, options)
6183     {
6184       if (CONST_STRNEQ (opt, "reg-names-"))
6185         {
6186           unsigned int i;
6187           for (i = 0; i < NUM_ARM_OPTIONS; i++)
6188             if (disassembler_options_cmp (opt, regnames[i].name) == 0)
6189               {
6190                 regname_selected = i;
6191                 break;
6192               }
6193
6194           if (i >= NUM_ARM_OPTIONS)
6195             /* xgettext: c-format */
6196             opcodes_error_handler (_("unrecognised register name set: %s"),
6197                                    opt);
6198         }
6199       else if (CONST_STRNEQ (opt, "force-thumb"))
6200         force_thumb = 1;
6201       else if (CONST_STRNEQ (opt, "no-force-thumb"))
6202         force_thumb = 0;
6203       else
6204         /* xgettext: c-format */
6205         opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
6206     }
6207
6208   return;
6209 }
6210
6211 static bfd_boolean
6212 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6213                          enum map_type *map_symbol);
6214
6215 /* Search back through the insn stream to determine if this instruction is
6216    conditionally executed.  */
6217
6218 static void
6219 find_ifthen_state (bfd_vma pc,
6220                    struct disassemble_info *info,
6221                    bfd_boolean little)
6222 {
6223   unsigned char b[2];
6224   unsigned int insn;
6225   int status;
6226   /* COUNT is twice the number of instructions seen.  It will be odd if we
6227      just crossed an instruction boundary.  */
6228   int count;
6229   int it_count;
6230   unsigned int seen_it;
6231   bfd_vma addr;
6232
6233   ifthen_address = pc;
6234   ifthen_state = 0;
6235
6236   addr = pc;
6237   count = 1;
6238   it_count = 0;
6239   seen_it = 0;
6240   /* Scan backwards looking for IT instructions, keeping track of where
6241      instruction boundaries are.  We don't know if something is actually an
6242      IT instruction until we find a definite instruction boundary.  */
6243   for (;;)
6244     {
6245       if (addr == 0 || info->symbol_at_address_func (addr, info))
6246         {
6247           /* A symbol must be on an instruction boundary, and will not
6248              be within an IT block.  */
6249           if (seen_it && (count & 1))
6250             break;
6251
6252           return;
6253         }
6254       addr -= 2;
6255       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
6256       if (status)
6257         return;
6258
6259       if (little)
6260         insn = (b[0]) | (b[1] << 8);
6261       else
6262         insn = (b[1]) | (b[0] << 8);
6263       if (seen_it)
6264         {
6265           if ((insn & 0xf800) < 0xe800)
6266             {
6267               /* Addr + 2 is an instruction boundary.  See if this matches
6268                  the expected boundary based on the position of the last
6269                  IT candidate.  */
6270               if (count & 1)
6271                 break;
6272               seen_it = 0;
6273             }
6274         }
6275       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6276         {
6277           enum map_type type = MAP_ARM;
6278           bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6279
6280           if (!found || (found && type == MAP_THUMB))
6281             {
6282               /* This could be an IT instruction.  */
6283               seen_it = insn;
6284               it_count = count >> 1;
6285             }
6286         }
6287       if ((insn & 0xf800) >= 0xe800)
6288         count++;
6289       else
6290         count = (count + 2) | 1;
6291       /* IT blocks contain at most 4 instructions.  */
6292       if (count >= 8 && !seen_it)
6293         return;
6294     }
6295   /* We found an IT instruction.  */
6296   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6297   if ((ifthen_state & 0xf) == 0)
6298     ifthen_state = 0;
6299 }
6300
6301 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6302    mapping symbol.  */
6303
6304 static int
6305 is_mapping_symbol (struct disassemble_info *info, int n,
6306                    enum map_type *map_type)
6307 {
6308   const char *name;
6309
6310   name = bfd_asymbol_name (info->symtab[n]);
6311   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6312       && (name[2] == 0 || name[2] == '.'))
6313     {
6314       *map_type = ((name[1] == 'a') ? MAP_ARM
6315                    : (name[1] == 't') ? MAP_THUMB
6316                    : MAP_DATA);
6317       return TRUE;
6318     }
6319
6320   return FALSE;
6321 }
6322
6323 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6324    Returns nonzero if *MAP_TYPE was set.  */
6325
6326 static int
6327 get_map_sym_type (struct disassemble_info *info,
6328                   int n,
6329                   enum map_type *map_type)
6330 {
6331   /* If the symbol is in a different section, ignore it.  */
6332   if (info->section != NULL && info->section != info->symtab[n]->section)
6333     return FALSE;
6334
6335   return is_mapping_symbol (info, n, map_type);
6336 }
6337
6338 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
6339    Returns nonzero if *MAP_TYPE was set.  */
6340
6341 static int
6342 get_sym_code_type (struct disassemble_info *info,
6343                    int n,
6344                    enum map_type *map_type)
6345 {
6346   elf_symbol_type *es;
6347   unsigned int type;
6348
6349   /* If the symbol is in a different section, ignore it.  */
6350   if (info->section != NULL && info->section != info->symtab[n]->section)
6351     return FALSE;
6352
6353   es = *(elf_symbol_type **)(info->symtab + n);
6354   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6355
6356   /* If the symbol has function type then use that.  */
6357   if (type == STT_FUNC || type == STT_GNU_IFUNC)
6358     {
6359       if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6360           == ST_BRANCH_TO_THUMB)
6361         *map_type = MAP_THUMB;
6362       else
6363         *map_type = MAP_ARM;
6364       return TRUE;
6365     }
6366
6367   return FALSE;
6368 }
6369
6370 /* Search the mapping symbol state for instruction at pc.  This is only
6371    applicable for elf target.
6372
6373    There is an assumption Here, info->private_data contains the correct AND
6374    up-to-date information about current scan process.  The information will be
6375    used to speed this search process.
6376
6377    Return TRUE if the mapping state can be determined, and map_symbol
6378    will be updated accordingly.  Otherwise, return FALSE.  */
6379
6380 static bfd_boolean
6381 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6382                          enum map_type *map_symbol)
6383 {
6384   bfd_vma addr, section_vma = 0;
6385   int n, last_sym = -1;
6386   bfd_boolean found = FALSE;
6387   bfd_boolean can_use_search_opt_p = FALSE;
6388
6389   /* Default to DATA.  A text section is required by the ABI to contain an
6390      INSN mapping symbol at the start.  A data section has no such
6391      requirement, hence if no mapping symbol is found the section must
6392      contain only data.  This however isn't very useful if the user has
6393      fully stripped the binaries.  If this is the case use the section
6394      attributes to determine the default.  If we have no section default to
6395      INSN as well, as we may be disassembling some raw bytes on a baremetal
6396      HEX file or similar.  */
6397   enum map_type type = MAP_DATA;
6398   if ((info->section && info->section->flags & SEC_CODE) || !info->section)
6399     type = MAP_ARM;
6400   struct arm_private_data *private_data;
6401
6402   if (info->private_data == NULL
6403       || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6404     return FALSE;
6405
6406   private_data = info->private_data;
6407
6408   /* First, look for mapping symbols.  */
6409   if (info->symtab_size != 0)
6410   {
6411     if (pc <= private_data->last_mapping_addr)
6412       private_data->last_mapping_sym = -1;
6413
6414     /* Start scanning at the start of the function, or wherever
6415        we finished last time.  */
6416     n = info->symtab_pos + 1;
6417
6418     /* If the last stop offset is different from the current one it means we
6419        are disassembling a different glob of bytes.  As such the optimization
6420        would not be safe and we should start over.  */
6421     can_use_search_opt_p
6422       = private_data->last_mapping_sym >= 0
6423         && info->stop_offset == private_data->last_stop_offset;
6424
6425     if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
6426       n = private_data->last_mapping_sym;
6427
6428     /* Look down while we haven't passed the location being disassembled.
6429        The reason for this is that there's no defined order between a symbol
6430        and an mapping symbol that may be at the same address.  We may have to
6431        look at least one position ahead.  */
6432     for (; n < info->symtab_size; n++)
6433       {
6434         addr = bfd_asymbol_value (info->symtab[n]);
6435         if (addr > pc)
6436           break;
6437         if (get_map_sym_type (info, n, &type))
6438           {
6439             last_sym = n;
6440             found = TRUE;
6441           }
6442       }
6443
6444     if (!found)
6445       {
6446         n = info->symtab_pos;
6447         if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
6448           n = private_data->last_mapping_sym;
6449
6450         /* No mapping symbol found at this address.  Look backwards
6451            for a preceeding one, but don't go pass the section start
6452            otherwise a data section with no mapping symbol can pick up
6453            a text mapping symbol of a preceeding section.  The documentation
6454            says section can be NULL, in which case we will seek up all the
6455            way to the top.  */
6456         if (info->section)
6457           section_vma = info->section->vma;
6458
6459         for (; n >= 0; n--)
6460           {
6461             addr = bfd_asymbol_value (info->symtab[n]);
6462             if (addr < section_vma)
6463               break;
6464
6465             if (get_map_sym_type (info, n, &type))
6466               {
6467                 last_sym = n;
6468                 found = TRUE;
6469                 break;
6470               }
6471           }
6472       }
6473   }
6474
6475   /* If no mapping symbol was found, try looking up without a mapping
6476      symbol.  This is done by walking up from the current PC to the nearest
6477      symbol.  We don't actually have to loop here since symtab_pos will
6478      contain the nearest symbol already.  */
6479   if (!found)
6480     {
6481       n = info->symtab_pos;
6482       if (n >= 0 && get_sym_code_type (info, n, &type))
6483         {
6484           last_sym = n;
6485           found = TRUE;
6486         }
6487     }
6488
6489   private_data->last_mapping_sym = last_sym;
6490   private_data->last_type = type;
6491   private_data->last_stop_offset = info->stop_offset;
6492
6493   *map_symbol = type;
6494   return found;
6495 }
6496
6497 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
6498    of the supplied arm_feature_set structure with bitmasks indicating
6499    the supported base architectures and coprocessor extensions.
6500
6501    FIXME: This could more efficiently implemented as a constant array,
6502    although it would also be less robust.  */
6503
6504 static void
6505 select_arm_features (unsigned long mach,
6506                      arm_feature_set * features)
6507 {
6508   arm_feature_set arch_fset;
6509   const arm_feature_set fpu_any = FPU_ANY;
6510
6511 #undef ARM_SET_FEATURES
6512 #define ARM_SET_FEATURES(FSET) \
6513   {                                                     \
6514     const arm_feature_set fset = FSET;                  \
6515     arch_fset = fset;                                   \
6516   }
6517
6518   /* When several architecture versions share the same bfd_mach_arm_XXX value
6519      the most featureful is chosen.  */
6520   switch (mach)
6521     {
6522     case bfd_mach_arm_2:         ARM_SET_FEATURES (ARM_ARCH_V2); break;
6523     case bfd_mach_arm_2a:        ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6524     case bfd_mach_arm_3:         ARM_SET_FEATURES (ARM_ARCH_V3); break;
6525     case bfd_mach_arm_3M:        ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6526     case bfd_mach_arm_4:         ARM_SET_FEATURES (ARM_ARCH_V4); break;
6527     case bfd_mach_arm_4T:        ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6528     case bfd_mach_arm_5:         ARM_SET_FEATURES (ARM_ARCH_V5); break;
6529     case bfd_mach_arm_5T:        ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6530     case bfd_mach_arm_5TE:       ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6531     case bfd_mach_arm_XScale:    ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6532     case bfd_mach_arm_ep9312:
6533         ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6534                                            ARM_CEXT_MAVERICK | FPU_MAVERICK));
6535        break;
6536     case bfd_mach_arm_iWMMXt:    ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6537     case bfd_mach_arm_iWMMXt2:   ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6538     case bfd_mach_arm_5TEJ:      ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
6539     case bfd_mach_arm_6:         ARM_SET_FEATURES (ARM_ARCH_V6); break;
6540     case bfd_mach_arm_6KZ:       ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
6541     case bfd_mach_arm_6T2:       ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
6542     case bfd_mach_arm_6K:        ARM_SET_FEATURES (ARM_ARCH_V6K); break;
6543     case bfd_mach_arm_7:         ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
6544     case bfd_mach_arm_6M:        ARM_SET_FEATURES (ARM_ARCH_V6M); break;
6545     case bfd_mach_arm_6SM:       ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
6546     case bfd_mach_arm_7EM:       ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
6547     case bfd_mach_arm_8:
6548         {
6549           /* Add bits for extensions that Armv8.5-A recognizes.  */
6550           arm_feature_set armv8_5_ext_fset
6551             = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
6552           ARM_SET_FEATURES (ARM_ARCH_V8_5A);
6553           ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
6554           break;
6555         }
6556     case bfd_mach_arm_8R:        ARM_SET_FEATURES (ARM_ARCH_V8R); break;
6557     case bfd_mach_arm_8M_BASE:   ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
6558     case bfd_mach_arm_8M_MAIN:   ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
6559     case bfd_mach_arm_8_1M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN); break;
6560       /* If the machine type is unknown allow all architecture types and all
6561          extensions.  */
6562     case bfd_mach_arm_unknown:   ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
6563     default:
6564       abort ();
6565     }
6566 #undef ARM_SET_FEATURES
6567
6568   /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
6569      and thus on bfd_mach_arm_XXX value.  Therefore for a given
6570      bfd_mach_arm_XXX value all coprocessor feature bits should be allowed.  */
6571   ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
6572 }
6573
6574
6575 /* NOTE: There are no checks in these routines that
6576    the relevant number of data bytes exist.  */
6577
6578 static int
6579 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
6580 {
6581   unsigned char b[4];
6582   long          given;
6583   int           status;
6584   int           is_thumb = FALSE;
6585   int           is_data = FALSE;
6586   int           little_code;
6587   unsigned int  size = 4;
6588   void          (*printer) (bfd_vma, struct disassemble_info *, long);
6589   bfd_boolean   found = FALSE;
6590   struct arm_private_data *private_data;
6591
6592   if (info->disassembler_options)
6593     {
6594       parse_arm_disassembler_options (info->disassembler_options);
6595
6596       /* To avoid repeated parsing of these options, we remove them here.  */
6597       info->disassembler_options = NULL;
6598     }
6599
6600   /* PR 10288: Control which instructions will be disassembled.  */
6601   if (info->private_data == NULL)
6602     {
6603       static struct arm_private_data private;
6604
6605       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6606         /* If the user did not use the -m command line switch then default to
6607            disassembling all types of ARM instruction.
6608
6609            The info->mach value has to be ignored as this will be based on
6610            the default archictecture for the target and/or hints in the notes
6611            section, but it will never be greater than the current largest arm
6612            machine value (iWMMXt2), which is only equivalent to the V5TE
6613            architecture.  ARM architectures have advanced beyond the machine
6614            value encoding, and these newer architectures would be ignored if
6615            the machine value was used.
6616
6617            Ie the -m switch is used to restrict which instructions will be
6618            disassembled.  If it is necessary to use the -m switch to tell
6619            objdump that an ARM binary is being disassembled, eg because the
6620            input is a raw binary file, but it is also desired to disassemble
6621            all ARM instructions then use "-marm".  This will select the
6622            "unknown" arm architecture which is compatible with any ARM
6623            instruction.  */
6624           info->mach = bfd_mach_arm_unknown;
6625
6626       /* Compute the architecture bitmask from the machine number.
6627          Note: This assumes that the machine number will not change
6628          during disassembly....  */
6629       select_arm_features (info->mach, & private.features);
6630
6631       private.last_mapping_sym = -1;
6632       private.last_mapping_addr = 0;
6633       private.last_stop_offset = 0;
6634
6635       info->private_data = & private;
6636     }
6637
6638   private_data = info->private_data;
6639
6640   /* Decide if our code is going to be little-endian, despite what the
6641      function argument might say.  */
6642   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6643
6644   /* For ELF, consult the symbol table to determine what kind of code
6645      or data we have.  */
6646   if (info->symtab_size != 0
6647       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6648     {
6649       bfd_vma addr;
6650       int n;
6651       int last_sym = -1;
6652       enum map_type type = MAP_ARM;
6653
6654       found = mapping_symbol_for_insn (pc, info, &type);
6655       last_sym = private_data->last_mapping_sym;
6656
6657       is_thumb = (private_data->last_type == MAP_THUMB);
6658       is_data = (private_data->last_type == MAP_DATA);
6659
6660       /* Look a little bit ahead to see if we should print out
6661          two or four bytes of data.  If there's a symbol,
6662          mapping or otherwise, after two bytes then don't
6663          print more.  */
6664       if (is_data)
6665         {
6666           size = 4 - (pc & 3);
6667           for (n = last_sym + 1; n < info->symtab_size; n++)
6668             {
6669               addr = bfd_asymbol_value (info->symtab[n]);
6670               if (addr > pc
6671                   && (info->section == NULL
6672                       || info->section == info->symtab[n]->section))
6673                 {
6674                   if (addr - pc < size)
6675                     size = addr - pc;
6676                   break;
6677                 }
6678             }
6679           /* If the next symbol is after three bytes, we need to
6680              print only part of the data, so that we can use either
6681              .byte or .short.  */
6682           if (size == 3)
6683             size = (pc & 1) ? 1 : 2;
6684         }
6685     }
6686
6687   if (info->symbols != NULL)
6688     {
6689       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6690         {
6691           coff_symbol_type * cs;
6692
6693           cs = coffsymbol (*info->symbols);
6694           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
6695                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
6696                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
6697                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6698                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6699         }
6700       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6701                && !found)
6702         {
6703           /* If no mapping symbol has been found then fall back to the type
6704              of the function symbol.  */
6705           elf_symbol_type *  es;
6706           unsigned int       type;
6707
6708           es = *(elf_symbol_type **)(info->symbols);
6709           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6710
6711           is_thumb =
6712             ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6713               == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
6714         }
6715       else if (bfd_asymbol_flavour (*info->symbols)
6716                == bfd_target_mach_o_flavour)
6717         {
6718           bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6719
6720           is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6721         }
6722     }
6723
6724   if (force_thumb)
6725     is_thumb = TRUE;
6726
6727   if (is_data)
6728     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6729   else
6730     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6731
6732   info->bytes_per_line = 4;
6733
6734   /* PR 10263: Disassemble data if requested to do so by the user.  */
6735   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
6736     {
6737       int i;
6738
6739       /* Size was already set above.  */
6740       info->bytes_per_chunk = size;
6741       printer = print_insn_data;
6742
6743       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
6744       given = 0;
6745       if (little)
6746         for (i = size - 1; i >= 0; i--)
6747           given = b[i] | (given << 8);
6748       else
6749         for (i = 0; i < (int) size; i++)
6750           given = b[i] | (given << 8);
6751     }
6752   else if (!is_thumb)
6753     {
6754       /* In ARM mode endianness is a straightforward issue: the instruction
6755          is four bytes long and is either ordered 0123 or 3210.  */
6756       printer = print_insn_arm;
6757       info->bytes_per_chunk = 4;
6758       size = 4;
6759
6760       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
6761       if (little_code)
6762         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6763       else
6764         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
6765     }
6766   else
6767     {
6768       /* In Thumb mode we have the additional wrinkle of two
6769          instruction lengths.  Fortunately, the bits that determine
6770          the length of the current instruction are always to be found
6771          in the first two bytes.  */
6772       printer = print_insn_thumb16;
6773       info->bytes_per_chunk = 2;
6774       size = 2;
6775
6776       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
6777       if (little_code)
6778         given = (b[0]) | (b[1] << 8);
6779       else
6780         given = (b[1]) | (b[0] << 8);
6781
6782       if (!status)
6783         {
6784           /* These bit patterns signal a four-byte Thumb
6785              instruction.  */
6786           if ((given & 0xF800) == 0xF800
6787               || (given & 0xF800) == 0xF000
6788               || (given & 0xF800) == 0xE800)
6789             {
6790               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
6791               if (little_code)
6792                 given = (b[0]) | (b[1] << 8) | (given << 16);
6793               else
6794                 given = (b[1]) | (b[0] << 8) | (given << 16);
6795
6796               printer = print_insn_thumb32;
6797               size = 4;
6798             }
6799         }
6800
6801       if (ifthen_address != pc)
6802         find_ifthen_state (pc, info, little_code);
6803
6804       if (ifthen_state)
6805         {
6806           if ((ifthen_state & 0xf) == 0x8)
6807             ifthen_next_state = 0;
6808           else
6809             ifthen_next_state = (ifthen_state & 0xe0)
6810                                 | ((ifthen_state & 0xf) << 1);
6811         }
6812     }
6813
6814   if (status)
6815     {
6816       info->memory_error_func (status, pc, info);
6817       return -1;
6818     }
6819   if (info->flags & INSN_HAS_RELOC)
6820     /* If the instruction has a reloc associated with it, then
6821        the offset field in the instruction will actually be the
6822        addend for the reloc.  (We are using REL type relocs).
6823        In such cases, we can ignore the pc when computing
6824        addresses, since the addend is not currently pc-relative.  */
6825     pc = 0;
6826
6827   printer (pc, info, given);
6828
6829   if (is_thumb)
6830     {
6831       ifthen_state = ifthen_next_state;
6832       ifthen_address += size;
6833     }
6834   return size;
6835 }
6836
6837 int
6838 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
6839 {
6840   /* Detect BE8-ness and record it in the disassembler info.  */
6841   if (info->flavour == bfd_target_elf_flavour
6842       && info->section != NULL
6843       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6844     info->endian_code = BFD_ENDIAN_LITTLE;
6845
6846   return print_insn (pc, info, FALSE);
6847 }
6848
6849 int
6850 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
6851 {
6852   return print_insn (pc, info, TRUE);
6853 }
6854
6855 const disasm_options_and_args_t *
6856 disassembler_options_arm (void)
6857 {
6858   static disasm_options_and_args_t *opts_and_args;
6859
6860   if (opts_and_args == NULL)
6861     {
6862       disasm_options_t *opts;
6863       unsigned int i;
6864
6865       opts_and_args = XNEW (disasm_options_and_args_t);
6866       opts_and_args->args = NULL;
6867
6868       opts = &opts_and_args->options;
6869       opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6870       opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6871       opts->arg = NULL;
6872       for (i = 0; i < NUM_ARM_OPTIONS; i++)
6873         {
6874           opts->name[i] = regnames[i].name;
6875           if (regnames[i].description != NULL)
6876             opts->description[i] = _(regnames[i].description);
6877           else
6878             opts->description[i] = NULL;
6879         }
6880       /* The array we return must be NULL terminated.  */
6881       opts->name[i] = NULL;
6882       opts->description[i] = NULL;
6883     }
6884
6885   return opts_and_args;
6886 }
6887
6888 void
6889 print_arm_disassembler_options (FILE *stream)
6890 {
6891   unsigned int i, max_len = 0;
6892   fprintf (stream, _("\n\
6893 The following ARM specific disassembler options are supported for use with\n\
6894 the -M switch:\n"));
6895
6896   for (i = 0; i < NUM_ARM_OPTIONS; i++)
6897     {
6898       unsigned int len = strlen (regnames[i].name);
6899       if (max_len < len)
6900         max_len = len;
6901     }
6902
6903   for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
6904     fprintf (stream, "  %s%*c %s\n",
6905              regnames[i].name,
6906              (int)(max_len - strlen (regnames[i].name)), ' ',
6907              _(regnames[i].description));
6908 }