1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
26 #include "disassemble.h"
27 #include "opcode/arm.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
38 #include "elf/internal.h"
42 /* FIXME: Belongs in global header. */
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
47 /* Cached mapping symbol state. */
55 struct arm_private_data
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features
;
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type
;
63 /* Tracking symbol table information */
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset
;
68 bfd_vma last_mapping_addr
;
121 MVE_VSTRB_SCATTER_T1
,
122 MVE_VSTRH_SCATTER_T2
,
123 MVE_VSTRW_SCATTER_T3
,
124 MVE_VSTRD_SCATTER_T4
,
125 MVE_VSTRW_SCATTER_T5
,
126 MVE_VSTRD_SCATTER_T6
,
128 MVE_VCVT_BETWEEN_FP_INT
,
130 MVE_VCVT_FROM_FP_TO_INT
,
133 MVE_VMOV_GP_TO_VEC_LANE
,
136 MVE_VMOV2_VEC_LANE_TO_GP
,
137 MVE_VMOV2_GP_TO_VEC_LANE
,
138 MVE_VMOV_VEC_LANE_TO_GP
,
185 enum mve_unpredictable
187 UNPRED_IT_BLOCK
, /* Unpredictable because mve insn in it block.
189 UNPRED_FCA_0_FCB_1
, /* Unpredictable because fcA = 0 and
191 UNPRED_R13
, /* Unpredictable because r13 (sp) or
193 UNPRED_R15
, /* Unpredictable because r15 (pc) is used. */
194 UNPRED_Q_GT_4
, /* Unpredictable because
195 vec reg start > 4 (vld4/st4). */
196 UNPRED_Q_GT_6
, /* Unpredictable because
197 vec reg start > 6 (vld2/st2). */
198 UNPRED_R13_AND_WB
, /* Unpredictable becase gp reg = r13
200 UNPRED_Q_REGS_EQUAL
, /* Unpredictable because vector registers are
202 UNPRED_OS
, /* Unpredictable because offset scaled == 1. */
203 UNPRED_GP_REGS_EQUAL
, /* Unpredictable because gp registers are the
205 UNPRED_Q_REGS_EQ_AND_SIZE_1
, /* Unpredictable because q regs equal and
207 UNPRED_Q_REGS_EQ_AND_SIZE_2
, /* Unpredictable because q regs equal and
209 UNPRED_NONE
/* No unpredictable behavior. */
214 UNDEF_SIZE_0
, /* undefined because size == 0. */
215 UNDEF_SIZE_2
, /* undefined because size == 2. */
216 UNDEF_SIZE_3
, /* undefined because size == 3. */
217 UNDEF_SIZE_LE_1
, /* undefined because size <= 1. */
218 UNDEF_SIZE_NOT_2
, /* undefined because size != 2. */
219 UNDEF_SIZE_NOT_3
, /* undefined because size != 3. */
220 UNDEF_NOT_UNS_SIZE_0
, /* undefined because U == 0 and
222 UNDEF_NOT_UNS_SIZE_1
, /* undefined because U == 0 and
224 UNDEF_NOT_UNSIGNED
, /* undefined because U == 0. */
225 UNDEF_VCVT_IMM6
, /* imm6 < 32. */
226 UNDEF_VCVT_FSI_IMM6
, /* fsi = 0 and 32 >= imm6 <= 47. */
227 UNDEF_BAD_OP1_OP2
, /* undefined with op2 = 2 and
229 UNDEF_BAD_U_OP1_OP2
, /* undefined with U = 1 and
230 op2 == 0 and op1 == (0 or 1). */
231 UNDEF_OP_0_BAD_CMODE
, /* undefined because op == 0 and cmode
233 UNDEF_XCHG_UNS
, /* undefined because X == 1 and U == 1. */
234 UNDEF_NONE
/* no undefined behavior. */
239 arm_feature_set arch
; /* Architecture defining this insn. */
240 unsigned long value
; /* If arch is 0 then value is a sentinel. */
241 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
242 const char * assembler
; /* How to disassemble this insn. */
249 arm_feature_set arch
; /* Architecture defining this insn. */
250 enum mve_instructions mve_op
; /* Specific mve instruction for faster
252 unsigned long value
; /* If arch is 0 then value is a sentinel. */
253 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
254 const char * assembler
; /* How to disassemble this insn. */
264 /* Shared (between Arm and Thumb mode) opcode. */
267 enum isa isa
; /* Execution mode instruction availability. */
268 arm_feature_set arch
; /* Architecture defining this insn. */
269 unsigned long value
; /* If arch is 0 then value is a sentinel. */
270 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
271 const char * assembler
; /* How to disassemble this insn. */
276 arm_feature_set arch
; /* Architecture defining this insn. */
277 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
278 const char *assembler
; /* How to disassemble this insn. */
281 /* print_insn_coprocessor recognizes the following format control codes:
285 %c print condition code (always bits 28-31 in ARM mode)
286 %q print shifter argument
287 %u print condition code (unconditional in ARM mode,
288 UNPREDICTABLE if not AL in Thumb)
289 %A print address for ldc/stc/ldf/stf instruction
290 %B print vstm/vldm register list
291 %C print vscclrm register list
292 %I print cirrus signed shift immediate: bits 0..3|4..6
293 %J print register for VLDR instruction
294 %K print address for VLDR instruction
295 %F print the COUNT field of a LFM/SFM instruction.
296 %P print floating point precision in arithmetic insn
297 %Q print floating point precision in ldf/stf insn
298 %R print floating point rounding mode
300 %<bitfield>c print as a condition code (for vsel)
301 %<bitfield>r print as an ARM register
302 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
303 %<bitfield>ru as %<>r but each u register must be unique.
304 %<bitfield>d print the bitfield in decimal
305 %<bitfield>k print immediate for VFPv3 conversion instruction
306 %<bitfield>x print the bitfield in hex
307 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
308 %<bitfield>f print a floating point constant if >7 else a
309 floating point register
310 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
311 %<bitfield>g print as an iWMMXt 64-bit register
312 %<bitfield>G print as an iWMMXt general purpose or control register
313 %<bitfield>D print as a NEON D register
314 %<bitfield>Q print as a NEON Q register
315 %<bitfield>V print as a NEON D or Q register
316 %<bitfield>E print a quarter-float immediate value
318 %y<code> print a single precision VFP reg.
319 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
320 %z<code> print a double precision VFP reg
321 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
323 %<bitfield>'c print specified char iff bitfield is all ones
324 %<bitfield>`c print specified char iff bitfield is all zeroes
325 %<bitfield>?ab... select from array of values in big endian order
327 %L print as an iWMMXt N/M width field.
328 %Z print the Immediate of a WSHUFH instruction.
329 %l like 'A' except use byte offsets for 'B' & 'H'
331 %i print 5-bit immediate in bits 8,3..0
333 %r print register offset address for wldt/wstr instruction. */
335 enum opcode_sentinel_enum
337 SENTINEL_IWMMXT_START
= 1,
339 SENTINEL_GENERIC_START
342 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
343 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
344 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
345 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
347 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
349 static const struct sopcode32 coprocessor_opcodes
[] =
351 /* XScale instructions. */
352 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
353 0x0e200010, 0x0fff0ff0,
354 "mia%c\tacc0, %0-3r, %12-15r"},
355 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
356 0x0e280010, 0x0fff0ff0,
357 "miaph%c\tacc0, %0-3r, %12-15r"},
358 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
359 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
360 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
361 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
362 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
363 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
365 /* Intel Wireless MMX technology instructions. */
366 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START
, 0, "" },
367 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
368 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
369 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
370 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
371 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
372 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
373 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
374 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
375 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
376 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
377 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
378 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
379 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
380 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
381 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
382 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
383 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
384 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
385 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
386 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
387 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
388 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
389 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
390 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
391 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
392 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
393 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
394 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
395 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
396 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
397 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
398 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
399 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
400 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
401 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
402 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
403 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
404 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
405 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
406 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
407 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
408 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
409 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
410 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
411 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
412 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
413 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
414 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
415 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
416 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
417 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
418 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
419 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
420 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
421 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
422 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
423 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
424 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
425 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
426 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
427 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
428 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
429 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
430 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
431 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
432 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
433 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
434 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
435 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
436 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
437 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
438 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
439 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
440 0x0e800120, 0x0f800ff0,
441 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
442 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
443 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
444 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
445 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
446 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
447 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
448 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
449 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
450 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
451 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
452 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
453 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
454 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
455 0x0e8000a0, 0x0f800ff0,
456 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
457 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
458 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
459 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
460 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
461 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
462 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
463 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
464 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
465 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
466 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
467 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
468 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
469 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
470 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
471 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
472 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
473 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
474 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
475 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
476 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
477 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
478 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
479 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
480 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
481 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
482 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
483 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
484 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
485 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
486 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
487 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
488 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
489 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
490 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
491 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
492 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
493 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
494 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
495 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
496 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
497 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
498 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
499 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
500 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
501 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
502 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
503 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
504 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
505 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
506 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
507 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
508 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
509 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
510 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
511 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
512 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
513 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
514 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
515 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
516 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
517 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
518 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
519 {ANY
, ARM_FEATURE_CORE_LOW (0),
520 SENTINEL_IWMMXT_END
, 0, "" },
522 /* Floating point coprocessor (FPA) instructions. */
523 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
524 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
525 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
526 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
527 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
528 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
529 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
530 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
531 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
532 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
533 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
534 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
535 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
536 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
537 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
538 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
539 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
540 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
541 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
542 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
543 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
544 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
545 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
546 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
547 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
548 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
549 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
550 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
551 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
552 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
553 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
554 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
555 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
556 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
557 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
558 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
559 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
560 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
561 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
562 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
563 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
564 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
565 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
566 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
567 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
568 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
569 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
570 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
571 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
572 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
573 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
574 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
575 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
576 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
577 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
578 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
579 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
580 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
581 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
582 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
583 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
584 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
585 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
586 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
587 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
588 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
589 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
590 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
591 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
592 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
593 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
594 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
595 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
596 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
597 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
598 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
599 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
600 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
601 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
602 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
603 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
604 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
605 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
606 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
607 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
608 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
610 /* Armv8.1-M Mainline instructions. */
611 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
612 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
613 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
614 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
616 /* ARMv8-M Mainline Security Extensions instructions. */
617 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
618 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
619 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
620 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
622 /* Register load/store. */
623 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
624 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
625 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
626 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
627 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
628 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
629 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
630 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
631 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
632 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
633 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
634 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
635 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
636 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
637 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
638 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
639 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
640 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
641 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
642 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
643 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
644 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
645 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
646 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
647 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
648 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
649 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
650 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
651 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
652 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
653 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
654 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
655 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
656 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
657 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
658 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
660 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
661 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
662 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
663 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
664 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
665 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
666 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
667 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
669 /* Data transfer between ARM and NEON registers. */
670 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
671 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
672 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
673 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
674 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
675 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
676 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
677 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
678 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
679 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
680 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
681 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
682 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
683 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
684 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
685 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
686 /* Half-precision conversion instructions. */
687 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
688 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
689 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
690 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
691 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
692 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
693 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
694 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
696 /* Floating point coprocessor (VFP) instructions. */
697 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
698 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
699 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
700 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
701 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
702 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
703 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
704 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
705 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
706 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
707 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
708 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
709 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
710 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
711 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
712 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
713 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
714 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
715 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
716 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
717 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
718 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
719 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
720 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
721 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
722 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
723 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
724 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
725 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
726 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
727 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
728 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
729 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
730 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
731 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
732 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
733 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
734 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
735 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
736 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
737 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
738 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
739 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
740 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
741 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
742 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
743 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
744 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
745 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
746 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
747 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
748 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
749 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
750 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
751 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
752 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
753 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
754 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
755 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
756 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
757 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
758 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
759 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
760 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
761 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
762 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
763 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
764 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
765 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
766 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
767 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
768 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
769 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
770 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
771 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
772 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
773 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
774 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
775 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
776 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
777 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
778 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
779 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
780 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
781 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
782 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
783 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
784 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
785 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
786 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
787 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
788 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
789 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
790 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
791 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
792 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
793 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
794 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
795 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
796 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
797 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
798 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
799 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
800 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
801 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
802 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
803 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
804 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
805 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
806 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
807 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
808 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
809 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
810 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
811 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
812 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
813 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
814 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
815 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
816 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
817 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
818 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
819 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
820 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
821 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
822 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
823 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
824 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
825 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
826 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
827 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
828 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
829 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
830 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
831 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
832 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
833 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
834 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
836 /* Cirrus coprocessor instructions. */
837 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
838 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
839 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
840 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
841 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
842 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
843 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
844 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
845 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
846 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
847 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
848 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
849 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
850 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
851 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
852 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
853 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
854 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
855 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
856 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
857 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
858 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
859 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
860 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
861 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
862 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
863 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
864 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
865 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
866 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
867 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
868 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
869 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
870 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
871 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
872 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
873 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
874 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
875 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
876 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
877 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
878 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
879 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
880 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
881 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
882 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
883 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
884 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
885 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
886 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
887 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
888 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
889 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
890 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
891 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
892 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
893 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
894 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
895 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
896 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
897 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
898 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
899 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
900 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
901 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
902 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
903 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
904 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
905 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
906 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
907 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
908 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
909 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
910 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
911 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
912 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
913 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
914 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
915 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
916 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
917 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
918 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
919 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
920 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
921 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
922 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
923 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
924 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
925 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
926 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
927 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
928 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
929 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
930 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
931 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
932 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
933 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
934 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
935 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
936 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
937 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
938 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
939 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
940 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
941 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
942 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
943 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
944 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
945 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
946 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
947 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
948 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
949 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
950 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
951 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
952 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
953 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
954 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
955 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
956 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
957 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
958 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
959 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
960 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
961 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
962 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
963 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
964 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
965 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
966 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
967 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
968 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
969 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
970 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
971 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
972 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
973 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
974 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
975 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
976 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
977 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
978 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
979 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
980 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
981 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
982 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
983 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
984 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
985 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
986 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
987 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
988 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
989 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
990 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
991 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
992 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
993 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
994 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
995 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
996 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
997 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
998 0x0e000600, 0x0ff00f10,
999 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1000 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1001 0x0e100600, 0x0ff00f10,
1002 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1003 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1004 0x0e200600, 0x0ff00f10,
1005 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1006 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1007 0x0e300600, 0x0ff00f10,
1008 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1010 /* VFP Fused multiply add instructions. */
1011 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1012 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1013 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1014 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1015 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1016 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1017 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1018 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1019 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1020 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1021 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1022 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1023 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1024 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1025 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1026 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1029 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1030 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1031 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1032 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1033 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1034 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1035 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1036 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1037 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1038 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1039 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1040 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1041 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1042 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1043 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1044 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1045 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1046 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1047 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1048 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1049 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1050 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1051 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1052 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1054 /* Generic coprocessor instructions. */
1055 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START
, 0, "" },
1056 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1057 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1058 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1059 0x0c500000, 0x0ff00000,
1060 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1061 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1062 0x0e000000, 0x0f000010,
1063 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1064 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1065 0x0e10f010, 0x0f10f010,
1066 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1067 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1068 0x0e100010, 0x0f100010,
1069 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1070 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1071 0x0e000010, 0x0f100010,
1072 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1073 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1074 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1075 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1076 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1078 /* V6 coprocessor instructions. */
1079 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1080 0xfc500000, 0xfff00000,
1081 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1082 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1083 0xfc400000, 0xfff00000,
1084 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1086 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1087 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1088 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1089 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1090 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1091 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1092 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1093 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1094 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1095 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1096 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1097 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1098 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1099 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1100 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1101 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1102 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1103 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1104 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1105 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1106 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1108 /* Dot Product instructions in the space of coprocessor 13. */
1109 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1110 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1111 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1112 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1114 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1115 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1116 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1117 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1118 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1119 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1120 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1121 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1122 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1123 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1124 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1125 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1126 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1127 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1128 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1129 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1130 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1132 /* V5 coprocessor instructions. */
1133 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1134 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1135 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1136 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1137 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1138 0xfe000000, 0xff000010,
1139 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1140 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1141 0xfe000010, 0xff100010,
1142 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1143 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1144 0xfe100010, 0xff100010,
1145 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1147 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1148 cp_num: bit <11:8> == 0b1001.
1149 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1150 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1151 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1152 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1153 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1154 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1155 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1156 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1157 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1158 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1159 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1160 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1161 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1162 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1163 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1164 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1165 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1166 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1167 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1168 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1169 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1170 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1171 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1172 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1173 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1174 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1175 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1176 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1177 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1178 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1179 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1180 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1181 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1182 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1183 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1184 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1185 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1186 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1187 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1188 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1189 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1190 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1191 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1192 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1193 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1194 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1195 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1196 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1197 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1198 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1199 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1200 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1201 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1202 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1203 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1204 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1205 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1206 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1207 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1208 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1209 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1210 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1211 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1212 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1213 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1214 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1215 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1216 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1217 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1218 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1219 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1221 /* ARMv8.3 javascript conversion instruction. */
1222 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1223 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1225 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1228 /* Neon opcode table: This does not encode the top byte -- that is
1229 checked by the print_insn_neon routine, as it depends on whether we are
1230 doing thumb32 or arm32 disassembly. */
1232 /* print_insn_neon recognizes the following format control codes:
1236 %c print condition code
1237 %u print condition code (unconditional in ARM mode,
1238 UNPREDICTABLE if not AL in Thumb)
1239 %A print v{st,ld}[1234] operands
1240 %B print v{st,ld}[1234] any one operands
1241 %C print v{st,ld}[1234] single->all operands
1243 %E print vmov, vmvn, vorr, vbic encoded constant
1244 %F print vtbl,vtbx register list
1246 %<bitfield>r print as an ARM register
1247 %<bitfield>d print the bitfield in decimal
1248 %<bitfield>e print the 2^N - bitfield in decimal
1249 %<bitfield>D print as a NEON D register
1250 %<bitfield>Q print as a NEON Q register
1251 %<bitfield>R print as a NEON D or Q register
1252 %<bitfield>Sn print byte scaled width limited by n
1253 %<bitfield>Tn print short scaled width limited by n
1254 %<bitfield>Un print long scaled width limited by n
1256 %<bitfield>'c print specified char iff bitfield is all ones
1257 %<bitfield>`c print specified char iff bitfield is all zeroes
1258 %<bitfield>?ab... select from array of values in big endian order. */
1260 static const struct opcode32 neon_opcodes
[] =
1263 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1264 0xf2b00840, 0xffb00850,
1265 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1266 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1267 0xf2b00000, 0xffb00810,
1268 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1270 /* Data transfer between ARM and NEON registers. */
1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1272 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1274 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1276 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1278 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1279 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1280 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1282 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1284 /* Move data element to all lanes. */
1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1286 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1287 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1288 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1290 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1294 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1296 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1298 /* Half-precision conversions. */
1299 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1300 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1301 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1302 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1304 /* NEON fused multiply add instructions. */
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1306 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1307 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1308 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1310 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1311 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1312 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1314 /* Two registers, miscellaneous. */
1315 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1316 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1317 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1318 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1320 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1321 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1322 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1323 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1324 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1325 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1326 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1327 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1328 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1329 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1330 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1331 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1332 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1333 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1334 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1335 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1336 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1337 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1338 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1339 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1340 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1341 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1342 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1343 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1344 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1345 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1346 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1348 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1349 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1350 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1351 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1352 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1354 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1355 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1356 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1357 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1358 0xf3b20300, 0xffb30fd0,
1359 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1361 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1362 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1363 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1365 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1367 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1369 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1371 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1372 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1373 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1375 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1377 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1378 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1379 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1381 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1383 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1384 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1385 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1387 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1389 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1391 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1392 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1393 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1395 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1397 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1399 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1401 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1403 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1405 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1407 0xf3bb0600, 0xffbf0e10,
1408 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1409 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1410 0xf3b70600, 0xffbf0e10,
1411 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1413 /* Three registers of the same length. */
1414 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1415 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1416 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1417 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1418 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1419 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1420 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1421 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1422 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1423 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1424 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1425 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1426 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1427 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1429 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1430 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1431 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1433 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1435 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1437 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1439 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1441 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1443 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1445 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1447 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1449 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1451 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1453 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1454 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1455 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1457 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1458 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1459 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1461 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1463 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1465 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1466 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1467 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1469 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1470 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1471 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1473 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1475 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1477 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1478 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1479 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1481 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1482 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1483 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1485 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1486 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1487 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1489 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1491 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1493 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1494 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1495 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1497 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1498 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1499 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1501 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1502 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1503 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1505 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1506 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1507 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1509 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1511 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1513 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1514 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1515 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1516 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1517 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1518 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1519 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1521 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1522 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1523 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1525 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1527 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1528 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1529 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1531 0xf2000b00, 0xff800f10,
1532 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1534 0xf2000b10, 0xff800f10,
1535 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1537 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1539 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1540 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1541 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1543 0xf3000b00, 0xff800f10,
1544 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1546 0xf2000000, 0xfe800f10,
1547 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1548 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1549 0xf2000010, 0xfe800f10,
1550 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1552 0xf2000100, 0xfe800f10,
1553 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1555 0xf2000200, 0xfe800f10,
1556 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1558 0xf2000210, 0xfe800f10,
1559 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1561 0xf2000300, 0xfe800f10,
1562 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1564 0xf2000310, 0xfe800f10,
1565 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1567 0xf2000400, 0xfe800f10,
1568 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1570 0xf2000410, 0xfe800f10,
1571 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1573 0xf2000500, 0xfe800f10,
1574 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1576 0xf2000510, 0xfe800f10,
1577 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1579 0xf2000600, 0xfe800f10,
1580 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1582 0xf2000610, 0xfe800f10,
1583 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1584 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1585 0xf2000700, 0xfe800f10,
1586 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1588 0xf2000710, 0xfe800f10,
1589 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1591 0xf2000910, 0xfe800f10,
1592 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1594 0xf2000a00, 0xfe800f10,
1595 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1597 0xf2000a10, 0xfe800f10,
1598 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1600 0xf3000b10, 0xff800f10,
1601 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1603 0xf3000c10, 0xff800f10,
1604 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1606 /* One register and an immediate value. */
1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1608 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1610 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1612 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1614 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1615 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1616 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1618 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1620 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1622 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1624 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1626 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1628 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1630 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1632 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1634 /* Two registers and a shift amount. */
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1636 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1638 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1640 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1642 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1644 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1646 0xf2880950, 0xfeb80fd0,
1647 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1649 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1651 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1653 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1655 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1656 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1657 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1659 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1661 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1663 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1665 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1667 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1669 0xf2900950, 0xfeb00fd0,
1670 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1672 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1674 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1676 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1678 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1680 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1682 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1684 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1686 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1688 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1690 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1692 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1694 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1696 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1698 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1700 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1702 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1704 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1706 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1708 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1710 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1712 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1714 0xf2a00950, 0xfea00fd0,
1715 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1717 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1718 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1719 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1721 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1722 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1723 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1725 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1727 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1729 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1730 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1731 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1733 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1734 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1735 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1737 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1738 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1739 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1741 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1742 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1743 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1745 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1747 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1749 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1751 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1753 0xf2a00e10, 0xfea00e90,
1754 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1755 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1756 0xf2a00c10, 0xfea00e90,
1757 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1759 /* Three registers of different lengths. */
1760 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1761 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1763 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1765 0xf2800400, 0xff800f50,
1766 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1768 0xf2800600, 0xff800f50,
1769 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1771 0xf2800900, 0xff800f50,
1772 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1774 0xf2800b00, 0xff800f50,
1775 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1777 0xf2800d00, 0xff800f50,
1778 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1779 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1780 0xf3800400, 0xff800f50,
1781 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1782 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1783 0xf3800600, 0xff800f50,
1784 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1786 0xf2800000, 0xfe800f50,
1787 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1789 0xf2800100, 0xfe800f50,
1790 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1792 0xf2800200, 0xfe800f50,
1793 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1794 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1795 0xf2800300, 0xfe800f50,
1796 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1798 0xf2800500, 0xfe800f50,
1799 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1800 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1801 0xf2800700, 0xfe800f50,
1802 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1803 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1804 0xf2800800, 0xfe800f50,
1805 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1806 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1807 0xf2800a00, 0xfe800f50,
1808 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1810 0xf2800c00, 0xfe800f50,
1811 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1813 /* Two registers and a scalar. */
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1815 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1817 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1818 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1819 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1821 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1823 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1825 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1826 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1827 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1829 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1831 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1833 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1834 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1835 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1837 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1839 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1841 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1842 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1843 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1845 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1846 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1847 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1848 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1849 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1851 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1852 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1853 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1854 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1855 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1856 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1857 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1858 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1859 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1860 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1861 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1862 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1863 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1864 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1865 0xf2800240, 0xfe800f50,
1866 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1868 0xf2800640, 0xfe800f50,
1869 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1870 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1871 0xf2800a40, 0xfe800f50,
1872 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1874 0xf2800e40, 0xff800f50,
1875 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1876 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1877 0xf2800f40, 0xff800f50,
1878 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1880 0xf3800e40, 0xff800f50,
1881 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1882 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1883 0xf3800f40, 0xff800f50,
1884 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1887 /* Element and structure load/store. */
1888 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1889 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1891 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1893 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1895 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1897 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1899 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1901 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1902 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1903 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1905 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1907 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1908 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1909 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1911 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1913 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1915 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1916 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1917 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1919 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1920 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1921 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1922 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1923 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1925 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1927 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1930 /* mve opcode table. */
1932 /* print_insn_mve recognizes the following format control codes:
1936 %a print '+' or '-' or imm offset in vldr[bhwd] and
1938 %c print condition code
1939 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1940 %u print 'U' (unsigned) or 'S' for various mve instructions
1941 %i print MVE predicate(s) for vpt and vpst
1942 %m print rounding mode for vcvt and vrint
1943 %n print vector comparison code for predicated instruction
1944 %s print size for various vcvt instructions
1945 %v print vector predicate for instruction in predicated
1947 %o print offset scaled for vldr[hwd] and vstr[hwd]
1948 %w print writeback mode for MVE v{st,ld}[24]
1949 %B print v{st,ld}[24] any one operands
1950 %E print vmov, vmvn, vorr, vbic encoded constant
1951 %N print generic index for vmov
1952 %T print bottom ('b') or top ('t') of source register
1953 %X print exchange field in vmla* instructions
1955 %<bitfield>r print as an ARM register
1956 %<bitfield>d print the bitfield in decimal
1957 %<bitfield>A print accumulate or not
1958 %<bitfield>Q print as a MVE Q register
1959 %<bitfield>F print as a MVE S register
1960 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
1962 %<bitfield>s print size for vector predicate & non VMOV instructions
1963 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1964 %<bitfield>h print high half of 64-bit destination reg
1965 %<bitfield>k print immediate for vector conversion instruction
1966 %<bitfield>l print low half of 64-bit destination reg
1967 %<bitfield>u print immediate value for vddup/vdwdup
1968 %<bitfield>x print the bitfield in hex.
1971 static const struct mopcode32 mve_opcodes
[] =
1975 {ARM_FEATURE_COPROC (FPU_MVE
),
1977 0xfe310f4d, 0xffbf1fff,
1981 /* Floating point VPT T1. */
1982 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1984 0xee310f00, 0xefb10f50,
1985 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
1986 /* Floating point VPT T2. */
1987 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1989 0xee310f40, 0xefb10f50,
1990 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
1992 /* Vector VPT T1. */
1993 {ARM_FEATURE_COPROC (FPU_MVE
),
1995 0xfe010f00, 0xff811f51,
1996 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1997 /* Vector VPT T2. */
1998 {ARM_FEATURE_COPROC (FPU_MVE
),
2000 0xfe010f01, 0xff811f51,
2001 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2002 /* Vector VPT T3. */
2003 {ARM_FEATURE_COPROC (FPU_MVE
),
2005 0xfe011f00, 0xff811f50,
2006 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2007 /* Vector VPT T4. */
2008 {ARM_FEATURE_COPROC (FPU_MVE
),
2010 0xfe010f40, 0xff811f70,
2011 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2012 /* Vector VPT T5. */
2013 {ARM_FEATURE_COPROC (FPU_MVE
),
2015 0xfe010f60, 0xff811f70,
2016 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2017 /* Vector VPT T6. */
2018 {ARM_FEATURE_COPROC (FPU_MVE
),
2020 0xfe011f40, 0xff811f50,
2021 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2023 /* Vector VBIC immediate. */
2024 {ARM_FEATURE_COPROC (FPU_MVE
),
2026 0xef800070, 0xefb81070,
2027 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2029 /* Vector VBIC register. */
2030 {ARM_FEATURE_COPROC (FPU_MVE
),
2032 0xef100150, 0xffb11f51,
2033 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2035 /* Vector VADDLV. */
2036 {ARM_FEATURE_COPROC (FPU_MVE
),
2038 0xee890f00, 0xef8f1fd1,
2039 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2042 {ARM_FEATURE_COPROC (FPU_MVE
),
2044 0xeef10f00, 0xeff31fd1,
2045 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2047 /* Vector VCMP floating point T1. */
2048 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2050 0xee310f00, 0xeff1ef50,
2051 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2053 /* Vector VCMP floating point T2. */
2054 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2056 0xee310f40, 0xeff1ef50,
2057 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2059 /* Vector VCMP T1. */
2060 {ARM_FEATURE_COPROC (FPU_MVE
),
2062 0xfe010f00, 0xffc1ff51,
2063 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2064 /* Vector VCMP T2. */
2065 {ARM_FEATURE_COPROC (FPU_MVE
),
2067 0xfe010f01, 0xffc1ff51,
2068 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2069 /* Vector VCMP T3. */
2070 {ARM_FEATURE_COPROC (FPU_MVE
),
2072 0xfe011f00, 0xffc1ff50,
2073 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2074 /* Vector VCMP T4. */
2075 {ARM_FEATURE_COPROC (FPU_MVE
),
2077 0xfe010f40, 0xffc1ff70,
2078 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2079 /* Vector VCMP T5. */
2080 {ARM_FEATURE_COPROC (FPU_MVE
),
2082 0xfe010f60, 0xffc1ff70,
2083 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2084 /* Vector VCMP T6. */
2085 {ARM_FEATURE_COPROC (FPU_MVE
),
2087 0xfe011f40, 0xffc1ff50,
2088 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2091 {ARM_FEATURE_COPROC (FPU_MVE
),
2093 0xeea00b10, 0xffb10f5f,
2094 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2097 {ARM_FEATURE_COPROC (FPU_MVE
),
2099 0xff000150, 0xffd11f51,
2100 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2102 /* Vector VFMA, vector * scalar. */
2103 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2105 0xee310e40, 0xefb11f70,
2106 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2108 /* Vector VFMA floating point. */
2109 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2111 0xef000c50, 0xffa11f51,
2112 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2114 /* Vector VFMS floating point. */
2115 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2117 0xef200c50, 0xffa11f51,
2118 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2120 /* Vector VFMAS, vector * scalar. */
2121 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2122 MVE_VFMAS_FP_SCALAR
,
2123 0xee311e40, 0xefb11f70,
2124 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2126 /* Vector VHADD T1. */
2127 {ARM_FEATURE_COPROC (FPU_MVE
),
2129 0xef000040, 0xef811f51,
2130 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2132 /* Vector VHADD T2. */
2133 {ARM_FEATURE_COPROC (FPU_MVE
),
2135 0xee000f40, 0xef811f70,
2136 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2138 /* Vector VHSUB T1. */
2139 {ARM_FEATURE_COPROC (FPU_MVE
),
2141 0xef000240, 0xef811f51,
2142 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2144 /* Vector VHSUB T2. */
2145 {ARM_FEATURE_COPROC (FPU_MVE
),
2147 0xee001f40, 0xef811f70,
2148 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2151 {ARM_FEATURE_COPROC (FPU_MVE
),
2153 0xeea00b10, 0xffb10f5f,
2154 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2156 /* Vector VRHADD. */
2157 {ARM_FEATURE_COPROC (FPU_MVE
),
2159 0xef000140, 0xef811f51,
2160 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2163 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2164 MVE_VCVT_FP_FIX_VEC
,
2165 0xef800c50, 0xef801cd1,
2166 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2169 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2170 MVE_VCVT_BETWEEN_FP_INT
,
2171 0xffb30640, 0xffb31e51,
2172 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2174 /* Vector VCVT between single and half-precision float, bottom half. */
2175 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2176 MVE_VCVT_FP_HALF_FP
,
2177 0xee3f0e01, 0xefbf1fd1,
2178 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2180 /* Vector VCVT between single and half-precision float, top half. */
2181 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2182 MVE_VCVT_FP_HALF_FP
,
2183 0xee3f1e01, 0xefbf1fd1,
2184 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2187 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2188 MVE_VCVT_FROM_FP_TO_INT
,
2189 0xffb30040, 0xffb31c51,
2190 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2193 {ARM_FEATURE_COPROC (FPU_MVE
),
2195 0xee011f6e, 0xff811f7e,
2196 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2198 /* Vector VDWDUP. */
2199 {ARM_FEATURE_COPROC (FPU_MVE
),
2201 0xee011f60, 0xff811f70,
2202 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2204 /* Vector VIWDUP. */
2205 {ARM_FEATURE_COPROC (FPU_MVE
),
2207 0xee010f60, 0xff811f70,
2208 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2211 {ARM_FEATURE_COPROC (FPU_MVE
),
2213 0xee010f6e, 0xff811f7e,
2214 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2217 {ARM_FEATURE_COPROC (FPU_MVE
),
2219 0xfc901e00, 0xff901e5f,
2220 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2223 {ARM_FEATURE_COPROC (FPU_MVE
),
2225 0xfc901e01, 0xff901e1f,
2226 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2228 /* Vector VLDRB gather load. */
2229 {ARM_FEATURE_COPROC (FPU_MVE
),
2230 MVE_VLDRB_GATHER_T1
,
2231 0xec900e00, 0xefb01e50,
2232 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2234 /* Vector VLDRH gather load. */
2235 {ARM_FEATURE_COPROC (FPU_MVE
),
2236 MVE_VLDRH_GATHER_T2
,
2237 0xec900e10, 0xefb01e50,
2238 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2240 /* Vector VLDRW gather load. */
2241 {ARM_FEATURE_COPROC (FPU_MVE
),
2242 MVE_VLDRW_GATHER_T3
,
2243 0xfc900f40, 0xffb01fd0,
2244 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2246 /* Vector VLDRD gather load. */
2247 {ARM_FEATURE_COPROC (FPU_MVE
),
2248 MVE_VLDRD_GATHER_T4
,
2249 0xec900fd0, 0xefb01fd0,
2250 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2252 /* Vector VLDRW gather load. */
2253 {ARM_FEATURE_COPROC (FPU_MVE
),
2254 MVE_VLDRW_GATHER_T5
,
2255 0xfd101e00, 0xff111f00,
2256 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2258 /* Vector VLDRD gather load, variant T6. */
2259 {ARM_FEATURE_COPROC (FPU_MVE
),
2260 MVE_VLDRD_GATHER_T6
,
2261 0xfd101f00, 0xff111f00,
2262 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2265 {ARM_FEATURE_COPROC (FPU_MVE
),
2267 0xec100e00, 0xee581e00,
2268 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2271 {ARM_FEATURE_COPROC (FPU_MVE
),
2273 0xec180e00, 0xee581e00,
2274 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2276 /* Vector VLDRB unsigned, variant T5. */
2277 {ARM_FEATURE_COPROC (FPU_MVE
),
2279 0xec101e00, 0xfe101f80,
2280 "vldrb%v.u8\t%13-15,22Q, %d"},
2282 /* Vector VLDRH unsigned, variant T6. */
2283 {ARM_FEATURE_COPROC (FPU_MVE
),
2285 0xec101e80, 0xfe101f80,
2286 "vldrh%v.u16\t%13-15,22Q, %d"},
2288 /* Vector VLDRW unsigned, variant T7. */
2289 {ARM_FEATURE_COPROC (FPU_MVE
),
2291 0xec101f00, 0xfe101f80,
2292 "vldrw%v.u32\t%13-15,22Q, %d"},
2294 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2296 {ARM_FEATURE_COPROC (FPU_MVE
),
2298 0xee801e00, 0xef801f51,
2299 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2301 {ARM_FEATURE_COPROC (FPU_MVE
),
2303 0xee800e00, 0xef801f51,
2304 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2306 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2307 {ARM_FEATURE_COPROC (FPU_MVE
),
2309 0xeef00e00, 0xeff01f51,
2310 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2312 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2313 {ARM_FEATURE_COPROC (FPU_MVE
),
2315 0xeef00f00, 0xeff11f51,
2316 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2318 /* Vector VMLADAV T1 variant. */
2319 {ARM_FEATURE_COPROC (FPU_MVE
),
2321 0xeef01e00, 0xeff01f51,
2322 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2324 /* Vector VMLADAV T2 variant. */
2325 {ARM_FEATURE_COPROC (FPU_MVE
),
2327 0xeef01f00, 0xeff11f51,
2328 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2331 {ARM_FEATURE_COPROC (FPU_MVE
),
2333 0xee011e40, 0xef811f70,
2334 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2336 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2338 {ARM_FEATURE_COPROC (FPU_MVE
),
2340 0xfe800e01, 0xff810f51,
2341 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2343 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2345 {ARM_FEATURE_COPROC (FPU_MVE
),
2347 0xee800e01, 0xff800f51,
2348 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2350 /* Vector VMLSDAV T1 Variant. */
2351 {ARM_FEATURE_COPROC (FPU_MVE
),
2353 0xeef00e01, 0xfff00f51,
2354 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2356 /* Vector VMLSDAV T2 Variant. */
2357 {ARM_FEATURE_COPROC (FPU_MVE
),
2359 0xfef00e01, 0xfff10f51,
2360 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2362 /* Vector VMOV between gpr and half precision register, op == 0. */
2363 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2365 0xee000910, 0xfff00f7f,
2366 "vmov.f16\t%7,16-19F, %12-15r"},
2368 /* Vector VMOV between gpr and half precision register, op == 1. */
2369 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2371 0xee100910, 0xfff00f7f,
2372 "vmov.f16\t%12-15r, %7,16-19F"},
2374 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2375 MVE_VMOV_GP_TO_VEC_LANE
,
2376 0xee000b10, 0xff900f1f,
2377 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2379 /* Vector VORR immediate to vector.
2380 NOTE: MVE_VORR_IMM must appear in the table
2381 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2382 {ARM_FEATURE_COPROC (FPU_MVE
),
2384 0xef800050, 0xefb810f0,
2385 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2387 /* Vector VMOV immediate to vector,
2388 cmode == 11x1 -> VMVN which is UNDEFINED
2389 for such a cmode. */
2390 {ARM_FEATURE_COPROC (FPU_MVE
),
2391 MVE_VMVN_IMM
, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION
},
2393 /* Vector VMOV immediate to vector. */
2394 {ARM_FEATURE_COPROC (FPU_MVE
),
2395 MVE_VMOV_IMM_TO_VEC
,
2396 0xef800050, 0xefb810d0,
2397 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2399 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2400 {ARM_FEATURE_COPROC (FPU_MVE
),
2401 MVE_VMOV2_VEC_LANE_TO_GP
,
2402 0xec000f00, 0xffb01ff0,
2403 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2405 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2406 {ARM_FEATURE_COPROC (FPU_MVE
),
2407 MVE_VMOV2_VEC_LANE_TO_GP
,
2408 0xec000f10, 0xffb01ff0,
2409 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2411 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2412 {ARM_FEATURE_COPROC (FPU_MVE
),
2413 MVE_VMOV2_GP_TO_VEC_LANE
,
2414 0xec100f00, 0xffb01ff0,
2415 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2417 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2418 {ARM_FEATURE_COPROC (FPU_MVE
),
2419 MVE_VMOV2_GP_TO_VEC_LANE
,
2420 0xec100f10, 0xffb01ff0,
2421 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2423 /* Vector VMOV Vector lane to gpr. */
2424 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2425 MVE_VMOV_VEC_LANE_TO_GP
,
2426 0xee100b10, 0xff100f1f,
2427 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2429 /* Vector VMOVL long. */
2430 {ARM_FEATURE_COPROC (FPU_MVE
),
2432 0xeea00f40, 0xefa70fd1,
2433 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2435 /* Vector VMOV and narrow. */
2436 {ARM_FEATURE_COPROC (FPU_MVE
),
2438 0xfe310e81, 0xffb30fd1,
2439 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2441 /* Floating point move extract. */
2442 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2444 0xfeb00a40, 0xffbf0fd0,
2445 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2447 /* Vector VMULL integer. */
2448 {ARM_FEATURE_COPROC (FPU_MVE
),
2450 0xee010e00, 0xef810f51,
2451 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2453 /* Vector VMULL polynomial. */
2454 {ARM_FEATURE_COPROC (FPU_MVE
),
2456 0xee310e00, 0xefb10f51,
2457 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2459 /* Vector VMVN immediate to vector. */
2460 {ARM_FEATURE_COPROC (FPU_MVE
),
2462 0xef800070, 0xefb810f0,
2463 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2465 /* Vector VMVN register. */
2466 {ARM_FEATURE_COPROC (FPU_MVE
),
2468 0xffb005c0, 0xffbf1fd1,
2469 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2471 /* Vector VORN, vector bitwise or not. */
2472 {ARM_FEATURE_COPROC (FPU_MVE
),
2474 0xef300150, 0xffb11f51,
2475 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2477 /* Vector VORR register. */
2478 {ARM_FEATURE_COPROC (FPU_MVE
),
2480 0xef200150, 0xffb11f51,
2481 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2483 /* Vector VQDMULL T1 variant. */
2484 {ARM_FEATURE_COPROC (FPU_MVE
),
2486 0xee300f01, 0xefb10f51,
2487 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2489 /* Vector VQDMULL T2 variant. */
2490 {ARM_FEATURE_COPROC (FPU_MVE
),
2492 0xee300f60, 0xefb10f70,
2493 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2495 /* Vector VQMOVN. */
2496 {ARM_FEATURE_COPROC (FPU_MVE
),
2498 0xee330e01, 0xefb30fd1,
2499 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2501 /* Vector VQMOVUN. */
2502 {ARM_FEATURE_COPROC (FPU_MVE
),
2504 0xee310e81, 0xffb30fd1,
2505 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2507 /* Vector VQDMLADH. */
2508 {ARM_FEATURE_COPROC (FPU_MVE
),
2510 0xee000e00, 0xff810f51,
2511 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2513 /* Vector VQRDMLADH. */
2514 {ARM_FEATURE_COPROC (FPU_MVE
),
2516 0xee000e01, 0xff810f51,
2517 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2519 /* Vector VQDMLAH. */
2520 {ARM_FEATURE_COPROC (FPU_MVE
),
2522 0xee000e60, 0xef811f70,
2523 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2525 /* Vector VQRDMLAH. */
2526 {ARM_FEATURE_COPROC (FPU_MVE
),
2528 0xee000e40, 0xef811f70,
2529 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2531 /* Vector VQDMLASH. */
2532 {ARM_FEATURE_COPROC (FPU_MVE
),
2534 0xee001e60, 0xef811f70,
2535 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2537 /* Vector VQRDMLASH. */
2538 {ARM_FEATURE_COPROC (FPU_MVE
),
2540 0xee001e40, 0xef811f70,
2541 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2543 /* Vector VQDMLSDH. */
2544 {ARM_FEATURE_COPROC (FPU_MVE
),
2546 0xfe000e00, 0xff810f51,
2547 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2549 /* Vector VQRDMLSDH. */
2550 {ARM_FEATURE_COPROC (FPU_MVE
),
2552 0xfe000e01, 0xff810f51,
2553 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2555 /* Vector VQDMULH T1 variant. */
2556 {ARM_FEATURE_COPROC (FPU_MVE
),
2558 0xef000b40, 0xff811f51,
2559 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2561 /* Vector VQRDMULH T2 variant. */
2562 {ARM_FEATURE_COPROC (FPU_MVE
),
2564 0xff000b40, 0xff811f51,
2565 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2567 /* Vector VQDMULH T3 variant. */
2568 {ARM_FEATURE_COPROC (FPU_MVE
),
2570 0xee010e60, 0xff811f70,
2571 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2573 /* Vector VQRDMULH T4 variant. */
2574 {ARM_FEATURE_COPROC (FPU_MVE
),
2576 0xfe010e60, 0xff811f70,
2577 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2579 /* Vector VRINT floating point. */
2580 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2582 0xffb20440, 0xffb31c51,
2583 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2585 /* Vector VRMLALDAVH. */
2586 {ARM_FEATURE_COPROC (FPU_MVE
),
2588 0xee800f00, 0xef811f51,
2589 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2591 /* Vector VRMLALDAVH. */
2592 {ARM_FEATURE_COPROC (FPU_MVE
),
2594 0xee801f00, 0xef811f51,
2595 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2597 /* Vector VST2 no writeback. */
2598 {ARM_FEATURE_COPROC (FPU_MVE
),
2600 0xfc801e00, 0xffb01e5f,
2601 "vst2%5d.%7-8s\t%B, [%16-19r]"},
2603 /* Vector VST2 writeback. */
2604 {ARM_FEATURE_COPROC (FPU_MVE
),
2606 0xfca01e00, 0xffb01e5f,
2607 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2609 /* Vector VST4 no writeback. */
2610 {ARM_FEATURE_COPROC (FPU_MVE
),
2612 0xfc801e01, 0xffb01e1f,
2613 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2615 /* Vector VST4 writeback. */
2616 {ARM_FEATURE_COPROC (FPU_MVE
),
2618 0xfca01e01, 0xffb01e1f,
2619 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2621 /* Vector VSTRB scatter store, T1 variant. */
2622 {ARM_FEATURE_COPROC (FPU_MVE
),
2623 MVE_VSTRB_SCATTER_T1
,
2624 0xec800e00, 0xffb01e50,
2625 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2627 /* Vector VSTRH scatter store, T2 variant. */
2628 {ARM_FEATURE_COPROC (FPU_MVE
),
2629 MVE_VSTRH_SCATTER_T2
,
2630 0xec800e10, 0xffb01e50,
2631 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2633 /* Vector VSTRW scatter store, T3 variant. */
2634 {ARM_FEATURE_COPROC (FPU_MVE
),
2635 MVE_VSTRW_SCATTER_T3
,
2636 0xec800e40, 0xffb01e50,
2637 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2639 /* Vector VSTRD scatter store, T4 variant. */
2640 {ARM_FEATURE_COPROC (FPU_MVE
),
2641 MVE_VSTRD_SCATTER_T4
,
2642 0xec800fd0, 0xffb01fd0,
2643 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2645 /* Vector VSTRW scatter store, T5 variant. */
2646 {ARM_FEATURE_COPROC (FPU_MVE
),
2647 MVE_VSTRW_SCATTER_T5
,
2648 0xfd001e00, 0xff111f00,
2649 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2651 /* Vector VSTRD scatter store, T6 variant. */
2652 {ARM_FEATURE_COPROC (FPU_MVE
),
2653 MVE_VSTRD_SCATTER_T6
,
2654 0xfd001f00, 0xff111f00,
2655 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2658 {ARM_FEATURE_COPROC (FPU_MVE
),
2660 0xec000e00, 0xfe581e00,
2661 "vstrb%v.%7-8s\t%13-15Q, %d"},
2664 {ARM_FEATURE_COPROC (FPU_MVE
),
2666 0xec080e00, 0xfe581e00,
2667 "vstrh%v.%7-8s\t%13-15Q, %d"},
2669 /* Vector VSTRB variant T5. */
2670 {ARM_FEATURE_COPROC (FPU_MVE
),
2672 0xec001e00, 0xfe101f80,
2673 "vstrb%v.8\t%13-15,22Q, %d"},
2675 /* Vector VSTRH variant T6. */
2676 {ARM_FEATURE_COPROC (FPU_MVE
),
2678 0xec001e80, 0xfe101f80,
2679 "vstrh%v.16\t%13-15,22Q, %d"},
2681 /* Vector VSTRW variant T7. */
2682 {ARM_FEATURE_COPROC (FPU_MVE
),
2684 0xec001f00, 0xfe101f80,
2685 "vstrw%v.32\t%13-15,22Q, %d"},
2687 {ARM_FEATURE_CORE_LOW (0),
2689 0x00000000, 0x00000000, 0}
2692 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
2693 ordered: they must be searched linearly from the top to obtain a correct
2696 /* print_insn_arm recognizes the following format control codes:
2700 %a print address for ldr/str instruction
2701 %s print address for ldr/str halfword/signextend instruction
2702 %S like %s but allow UNPREDICTABLE addressing
2703 %b print branch destination
2704 %c print condition code (always bits 28-31)
2705 %m print register mask for ldm/stm instruction
2706 %o print operand2 (immediate or register + shift)
2707 %p print 'p' iff bits 12-15 are 15
2708 %t print 't' iff bit 21 set and bit 24 clear
2709 %B print arm BLX(1) destination
2710 %C print the PSR sub type.
2711 %U print barrier type.
2712 %P print address for pli instruction.
2714 %<bitfield>r print as an ARM register
2715 %<bitfield>T print as an ARM register + 1
2716 %<bitfield>R as %r but r15 is UNPREDICTABLE
2717 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
2718 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
2719 %<bitfield>d print the bitfield in decimal
2720 %<bitfield>W print the bitfield plus one in decimal
2721 %<bitfield>x print the bitfield in hex
2722 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2724 %<bitfield>'c print specified char iff bitfield is all ones
2725 %<bitfield>`c print specified char iff bitfield is all zeroes
2726 %<bitfield>?ab... select from array of values in big endian order
2728 %e print arm SMI operand (bits 0..7,8..19).
2729 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
2730 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
2731 %R print the SPSR/CPSR or banked register of an MRS. */
2733 static const struct opcode32 arm_opcodes
[] =
2735 /* ARM instructions. */
2736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2737 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
2738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2739 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
2741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
),
2742 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
2743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
2744 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
2745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
2746 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
),
2748 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
2749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
2750 0x00800090, 0x0fa000f0,
2751 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
2753 0x00a00090, 0x0fa000f0,
2754 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2756 /* V8.2 RAS extension instructions. */
2757 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
2758 0xe320f010, 0xffffffff, "esb"},
2760 /* V8 instructions. */
2761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2762 0x0320f005, 0x0fffffff, "sevl"},
2763 /* Defined in V8 but is in NOP space so available to all arch. */
2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2765 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
2766 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
),
2767 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
2768 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2769 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2771 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2773 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2775 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
2776 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2777 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2779 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
2780 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2781 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2782 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2783 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
2784 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2785 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2787 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2789 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2791 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2793 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2794 /* CRC32 instructions. */
2795 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2796 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
2797 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2798 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
2799 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2800 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
2801 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2802 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
2803 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2804 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
2805 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2806 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
2808 /* Privileged Access Never extension instructions. */
2809 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
2810 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
2812 /* Virtualization Extension instructions. */
2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x0160006e, 0x0fffffff, "eret%c"},
2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
2816 /* Integer Divide Extension instructions. */
2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
2818 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
2820 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
2822 /* MP Extension instructions. */
2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf410f000, 0xfc70f000, "pldw\t%a"},
2825 /* Speculation Barriers. */
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xe320f014, 0xffffffff, "csdb"},
2827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff040, 0xffffffff, "ssbb"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff044, 0xffffffff, "pssbb"},
2830 /* V7 instructions. */
2831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf450f000, 0xfd70f000, "pli\t%P"},
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
2833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
2835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
2837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff060, 0xfffffff0, "isb\t%U"},
2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
2839 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
2841 /* ARM V6T2 instructions. */
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2843 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2845 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2847 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2849 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
2851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2852 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
2853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2854 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
2856 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2857 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
2858 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2859 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2861 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2863 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
2865 /* ARM Security extension instructions. */
2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
2867 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2869 /* ARM V6K instructions. */
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2871 0xf57ff01f, 0xffffffff, "clrex"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2873 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2875 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2877 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2879 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2881 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2883 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
2885 /* ARMv8.5-A instructions. */
2886 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf57ff070, 0xffffffff, "sb"},
2888 /* ARM V6K NOP hints. */
2889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2890 0x0320f001, 0x0fffffff, "yield%c"},
2891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2892 0x0320f002, 0x0fffffff, "wfe%c"},
2893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2894 0x0320f003, 0x0fffffff, "wfi%c"},
2895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2896 0x0320f004, 0x0fffffff, "sev%c"},
2897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2898 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
2900 /* ARM V6 instructions. */
2901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2902 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
2903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2904 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
2905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2906 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
2907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2908 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
2909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2910 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
2911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2912 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
2913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2914 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
2915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2916 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
2917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2918 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
2919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2920 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
2921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2922 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
2923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2924 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
2925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2926 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2928 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
2929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2930 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
2931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2932 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
2933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2934 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
2935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2936 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
2937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2938 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
2939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2940 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
2941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2942 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
2943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2944 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
2945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2946 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
2947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2948 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2950 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2952 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2954 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2956 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2958 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2960 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2962 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2964 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2966 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2968 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
2969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2970 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
2971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2972 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2974 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2976 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2978 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2980 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2982 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2984 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2986 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2988 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2990 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2992 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2994 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2996 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2998 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3000 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3002 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3004 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3006 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3008 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3010 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3012 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3014 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3016 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3018 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3020 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3022 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3024 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3026 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3028 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3030 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3032 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3034 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3036 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3038 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3040 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3042 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3044 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3046 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3048 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3050 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3052 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3054 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3056 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3058 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3060 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3062 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3064 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3066 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3068 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3070 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3072 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3074 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3076 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3078 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3080 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3082 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3084 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3086 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3088 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3090 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3092 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3094 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3096 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3098 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3100 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3102 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3104 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3106 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3108 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3110 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3112 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3114 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3116 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3118 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3120 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3122 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3124 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3126 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3128 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3130 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3132 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3134 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3136 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3138 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3140 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3142 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3144 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
3146 /* V5J instruction. */
3147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
),
3148 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3150 /* V5 Instructions. */
3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3152 0xe1200070, 0xfff000f0,
3153 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3155 0xfa000000, 0xfe000000, "blx\t%B"},
3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3157 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3159 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3161 /* V5E "El Segundo" Instructions. */
3162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3163 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3165 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3167 0xf450f000, 0xfc70f000, "pld\t%a"},
3168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3169 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3171 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3173 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3175 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3178 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3180 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3183 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3185 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3187 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3189 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3192 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3194 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3196 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3198 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3201 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3203 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3206 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3208 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3210 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3212 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
3214 /* ARM Instructions. */
3215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3216 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3219 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3221 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3223 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3225 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3227 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3229 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3232 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3234 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3236 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3238 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3241 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
3242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3243 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3245 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
3246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3247 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3250 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3252 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3254 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3257 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3259 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3261 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3264 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3266 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3268 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3271 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3273 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3275 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3278 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3280 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3282 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3285 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3287 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3289 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3292 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3294 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3296 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3299 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3301 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3303 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3305 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
3306 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
3308 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
3310 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3313 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3315 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3317 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3320 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
3321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3322 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
3323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3324 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
3326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3327 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3329 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3331 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3334 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3336 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3338 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3341 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3343 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3345 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3348 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3350 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3352 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3354 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3356 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3358 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3360 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3363 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3365 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3367 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3370 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3372 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3374 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3377 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
3378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3379 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3382 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3385 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3387 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3390 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3392 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3394 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3396 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3398 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3400 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3402 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3404 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3406 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3408 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3410 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3412 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3414 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3416 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3418 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3420 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3422 0x092d0000, 0x0fff0000, "push%c\t%m"},
3423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3424 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3426 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3429 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3431 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3433 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3435 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3437 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3439 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3441 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3443 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3445 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3447 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3449 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3451 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3453 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3455 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3457 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3459 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3461 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3463 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3465 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3468 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3470 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
3473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
3474 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION
},
3475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3476 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
3477 {ARM_FEATURE_CORE_LOW (0),
3478 0x00000000, 0x00000000, 0}
3481 /* print_insn_thumb16 recognizes the following format control codes:
3483 %S print Thumb register (bits 3..5 as high number if bit 6 set)
3484 %D print Thumb register (bits 0..2 as high number if bit 7 set)
3485 %<bitfield>I print bitfield as a signed decimal
3486 (top bit of range being the sign bit)
3487 %N print Thumb register mask (with LR)
3488 %O print Thumb register mask (with PC)
3489 %M print Thumb register mask
3490 %b print CZB's 6-bit unsigned branch destination
3491 %s print Thumb right-shift immediate (6..10; 0 == 32).
3492 %c print the condition code
3493 %C print the condition code, or "s" if not conditional
3494 %x print warning if conditional an not at end of IT block"
3495 %X print "\t; unpredictable <IT:code>" if conditional
3496 %I print IT instruction suffix and operands
3497 %W print Thumb Writeback indicator for LDMIA
3498 %<bitfield>r print bitfield as an ARM register
3499 %<bitfield>d print bitfield as a decimal
3500 %<bitfield>H print (bitfield * 2) as a decimal
3501 %<bitfield>W print (bitfield * 4) as a decimal
3502 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3503 %<bitfield>B print Thumb branch destination (signed displacement)
3504 %<bitfield>c print bitfield as a condition code
3505 %<bitnum>'c print specified char iff bit is one
3506 %<bitnum>?ab print a if bit is one else print b. */
3508 static const struct opcode16 thumb_opcodes
[] =
3510 /* Thumb instructions. */
3512 /* ARMv8-M Security Extensions instructions. */
3513 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4784, 0xff87, "blxns\t%3-6r"},
3514 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4704, 0xff87, "bxns\t%3-6r"},
3516 /* ARM V8 instructions. */
3517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xbf50, 0xffff, "sevl%c"},
3518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xba80, 0xffc0, "hlt\t%0-5x"},
3519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
), 0xb610, 0xfff7, "setpan\t#%3-3d"},
3521 /* ARM V6K no-argument instructions. */
3522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xffff, "nop%c"},
3523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf10, 0xffff, "yield%c"},
3524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf20, 0xffff, "wfe%c"},
3525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf30, 0xffff, "wfi%c"},
3526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf40, 0xffff, "sev%c"},
3527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
3529 /* ARM V6T2 instructions. */
3530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3531 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
3532 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3533 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
3534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xbf00, 0xff00, "it%I%X"},
3537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
3538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
3539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
3540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
3541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
3543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb650, 0xfff7, "setend\t%3?ble%X"},
3544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
3545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
3546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
3547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
3549 /* ARM V5 ISA extends Thumb. */
3550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
3551 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
3552 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
3553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
3554 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
3555 /* ARM V4T ISA (Thumb v1). */
3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3557 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
3559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
3561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
3562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
3579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4700, 0xFF80, "bx%c\t%S%x"},
3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4400, 0xFF00, "add%c\t%D, %S"},
3581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4600, 0xFF00, "mov%c\t%D, %S"},
3584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB400, 0xFE00, "push%c\t%N"},
3585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xBC00, 0xFE00, "pop%c\t%O"},
3587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3588 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3590 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3592 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3594 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
3596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3597 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3599 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3601 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
3603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3604 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3606 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3610 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
3619 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3622 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
3624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3625 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3627 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3629 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3631 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
3633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3634 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3636 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
3638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3639 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3641 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
3643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3644 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3646 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
3648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
3654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
3655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
3657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
3659 /* The E800 .. FFFF range is unconditionally redirected to the
3660 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3661 are processed via that table. Thus, we can never encounter a
3662 bare "second half of BL/BLX(1)" instruction here. */
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
), 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
3664 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3667 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
3668 We adopt the convention that hw1 is the high 16 bits of .value and
3669 .mask, hw2 the low 16 bits.
3671 print_insn_thumb32 recognizes the following format control codes:
3675 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3676 %M print a modified 12-bit immediate (same location)
3677 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
3678 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
3679 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
3680 %S print a possibly-shifted Rm
3682 %L print address for a ldrd/strd instruction
3683 %a print the address of a plain load/store
3684 %w print the width and signedness of a core load/store
3685 %m print register mask for ldm/stm
3686 %n print register mask for clrm
3688 %E print the lsb and width fields of a bfc/bfi instruction
3689 %F print the lsb and width fields of a sbfx/ubfx instruction
3690 %G print a fallback offset for Branch Future instructions
3691 %W print an offset for BF instruction
3692 %Y print an offset for BFL instruction
3693 %Z print an offset for BFCSEL instruction
3694 %Q print an offset for Low Overhead Loop instructions
3695 %P print an offset for Low Overhead Loop end instructions
3696 %b print a conditional branch offset
3697 %B print an unconditional branch offset
3698 %s print the shift field of an SSAT instruction
3699 %R print the rotation field of an SXT instruction
3700 %U print barrier type.
3701 %P print address for pli instruction.
3702 %c print the condition code
3703 %x print warning if conditional an not at end of IT block"
3704 %X print "\t; unpredictable <IT:code>" if conditional
3706 %<bitfield>d print bitfield in decimal
3707 %<bitfield>D print bitfield plus one in decimal
3708 %<bitfield>W print bitfield*4 in decimal
3709 %<bitfield>r print bitfield as an ARM register
3710 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
3711 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
3712 %<bitfield>c print bitfield as a condition code
3714 %<bitfield>'c print specified char iff bitfield is all ones
3715 %<bitfield>`c print specified char iff bitfield is all zeroes
3716 %<bitfield>?ab... select from array of values in big endian order
3718 With one exception at the bottom (done because BL and BLX(1) need
3719 to come dead last), this table was machine-sorted first in
3720 decreasing order of number of bits set in the mask, then in
3721 increasing numeric order of mask, then in increasing numeric order
3722 of opcode. This order is not the clearest for a human reader, but
3723 is guaranteed never to catch a special-case bit pattern with a more
3724 general mask, which is important, because this instruction encoding
3725 makes heavy use of special-case bit patterns. */
3726 static const struct opcode32 thumb32_opcodes
[] =
3728 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
3730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3731 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
3732 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3733 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
3734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3735 0xf02fc001, 0xfffff001, "le\t%P"},
3736 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3737 0xf00fc001, 0xfffff001, "le\tlr, %P"},
3739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3740 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
3741 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3742 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
3743 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3744 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
3745 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3746 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
3747 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3748 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
3750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3751 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
3753 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
3754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0xe97fe97f, 0xffffffff, "sg"},
3755 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3756 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
3757 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3758 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
3759 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3760 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
3761 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3762 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
3764 /* ARM V8.2 RAS extension instructions. */
3765 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
3766 0xf3af8010, 0xffffffff, "esb"},
3768 /* V8 instructions. */
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3770 0xf3af8005, 0xffffffff, "sevl%c.w"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3772 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3774 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3776 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3778 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3780 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3782 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3784 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3786 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3788 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3790 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3792 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3794 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3796 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3798 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3800 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
3802 /* CRC32 instructions. */
3803 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3804 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
3805 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3806 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
3807 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3808 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
3809 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3810 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
3811 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3812 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
3813 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3814 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
3816 /* Speculation Barriers. */
3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8014, 0xffffffff, "csdb"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f40, 0xffffffff, "ssbb"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f44, 0xffffffff, "pssbb"},
3821 /* V7 instructions. */
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf910f000, 0xff70f000, "pli%c\t%a"},
3823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
3825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
3827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
3830 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
3831 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
3832 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
3834 /* Virtualization Extension instructions. */
3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
3836 /* We skip ERET as that is SUBS pc, lr, #0. */
3838 /* MP Extension instructions. */
3839 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
3841 /* Security extension instructions. */
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
3844 /* ARMv8.5-A instructions. */
3845 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf3bf8f70, 0xffffffff, "sb"},
3847 /* Instructions defined in the basic V6T2 set. */
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8000, 0xffffffff, "nop%c.w"},
3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8001, 0xffffffff, "yield%c.w"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8002, 0xffffffff, "wfe%c.w"},
3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8003, 0xffffffff, "wfi%c.w"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8004, 0xffffffff, "sev%c.w"},
3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3854 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
3857 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3858 0xf3bf8f2f, 0xffffffff, "clrex%c"},
3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3860 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3862 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3864 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3866 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3868 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3870 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
3871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3872 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
3873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3874 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3876 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
3877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3878 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
3879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3880 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
3881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3882 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
3883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3884 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
3885 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3886 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
3887 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3888 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
3889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3890 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3892 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
3893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3894 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3896 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3898 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3900 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
3901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3902 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
3903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3904 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
3905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3906 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3908 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3910 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3912 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3914 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
3915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3916 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
3917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3918 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3920 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
3921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3922 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3924 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3926 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3928 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
3929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3930 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3932 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
3933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3934 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3936 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3938 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3940 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
3941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3942 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3944 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3946 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3948 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3950 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3952 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3954 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3956 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3958 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3960 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3962 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3964 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3966 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3968 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3970 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3972 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3974 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3976 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3978 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3980 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3982 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3984 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3986 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3988 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3990 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3992 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3994 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3996 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3998 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4000 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4002 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4004 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4006 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4008 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4010 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4012 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4013 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4014 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4016 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4018 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4020 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4022 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4024 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4026 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4028 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4030 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4032 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4034 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4036 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4038 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4040 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4042 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4044 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4046 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4048 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4050 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4052 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4054 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4056 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4058 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4060 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4062 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4064 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4066 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4068 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4070 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4072 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4074 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4076 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4078 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4080 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4081 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4082 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4084 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4086 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4088 0xf810f000, 0xff70f000, "pld%c\t%a"},
4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4090 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4092 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4094 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4096 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4098 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4100 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4102 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4104 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4106 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4108 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4110 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4112 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4114 0xfb100000, 0xfff000c0,
4115 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4117 0xfbc00080, 0xfff000c0,
4118 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4120 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4122 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4124 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4126 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4128 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4129 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4130 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4132 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4133 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4134 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4136 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4138 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4140 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4142 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4144 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4146 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4148 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4150 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4152 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4154 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4155 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4156 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4158 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4160 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4162 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4164 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4166 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4168 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4170 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4172 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4174 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4176 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4178 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4180 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4182 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4184 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4186 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4188 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4190 0xe9400000, 0xff500000,
4191 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4193 0xe9500000, 0xff500000,
4194 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4196 0xe8600000, 0xff700000,
4197 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4199 0xe8700000, 0xff700000,
4200 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4202 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4204 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
4206 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
4207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4208 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4210 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4212 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4214 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
4216 /* These have been 32-bit since the invention of Thumb. */
4217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4218 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4220 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
4223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4224 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
4225 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4228 static const char *const arm_conditional
[] =
4229 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
4230 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
4232 static const char *const arm_fp_const
[] =
4233 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
4235 static const char *const arm_shift
[] =
4236 {"lsl", "lsr", "asr", "ror"};
4241 const char *description
;
4242 const char *reg_names
[16];
4246 static const arm_regname regnames
[] =
4248 { "reg-names-raw", N_("Select raw register names"),
4249 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
4250 { "reg-names-gcc", N_("Select register names used by GCC"),
4251 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
4252 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
4253 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
4254 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL
} },
4255 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL
} },
4256 { "reg-names-apcs", N_("Select register names used in the APCS"),
4257 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
4258 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
4259 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
4260 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4261 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
4264 static const char *const iwmmxt_wwnames
[] =
4265 {"b", "h", "w", "d"};
4267 static const char *const iwmmxt_wwssnames
[] =
4268 {"b", "bus", "bc", "bss",
4269 "h", "hus", "hc", "hss",
4270 "w", "wus", "wc", "wss",
4271 "d", "dus", "dc", "dss"
4274 static const char *const iwmmxt_regnames
[] =
4275 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4276 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4279 static const char *const iwmmxt_cregnames
[] =
4280 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4281 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4284 static const char *const vec_condnames
[] =
4285 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4288 static const char *const mve_predicatenames
[] =
4289 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4290 "eee", "ee", "eet", "e", "ett", "et", "ete"
4293 /* Names for 2-bit size field for mve vector isntructions. */
4294 static const char *const mve_vec_sizename
[] =
4295 { "8", "16", "32", "64"};
4297 /* Indicates whether we are processing a then predicate,
4298 else predicate or none at all. */
4306 /* Information used to process a vpt block and subsequent instructions. */
4309 /* Are we in a vpt block. */
4310 bfd_boolean in_vpt_block
;
4312 /* Next predicate state if in vpt block. */
4313 enum vpt_pred_state next_pred_state
;
4315 /* Mask from vpt/vpst instruction. */
4316 long predicate_mask
;
4318 /* Instruction number in vpt block. */
4319 long current_insn_num
;
4321 /* Number of instructions in vpt block.. */
4325 static struct vpt_block vpt_block_state
=
4334 /* Default to GCC register name set. */
4335 static unsigned int regname_selected
= 1;
4337 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
4338 #define arm_regnames regnames[regname_selected].reg_names
4340 static bfd_boolean force_thumb
= FALSE
;
4342 /* Current IT instruction state. This contains the same state as the IT
4343 bits in the CPSR. */
4344 static unsigned int ifthen_state
;
4345 /* IT state for the next instruction. */
4346 static unsigned int ifthen_next_state
;
4347 /* The address of the insn for which the IT state is valid. */
4348 static bfd_vma ifthen_address
;
4349 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
4350 /* Indicates that the current Conditional state is unconditional or outside
4352 #define COND_UNCOND 16
4356 /* Extract the predicate mask for a VPT or VPST instruction.
4357 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
4360 mve_extract_pred_mask (long given
)
4362 return ((given
& 0x00400000) >> 19) | ((given
& 0xe000) >> 13);
4365 /* Return the number of instructions in a MVE predicate block. */
4367 num_instructions_vpt_block (long given
)
4369 long mask
= mve_extract_pred_mask (given
);
4376 if ((mask
& 7) == 4)
4379 if ((mask
& 3) == 2)
4382 if ((mask
& 1) == 1)
4389 mark_outside_vpt_block (void)
4391 vpt_block_state
.in_vpt_block
= FALSE
;
4392 vpt_block_state
.next_pred_state
= PRED_NONE
;
4393 vpt_block_state
.predicate_mask
= 0;
4394 vpt_block_state
.current_insn_num
= 0;
4395 vpt_block_state
.num_pred_insn
= 0;
4399 mark_inside_vpt_block (long given
)
4401 vpt_block_state
.in_vpt_block
= TRUE
;
4402 vpt_block_state
.next_pred_state
= PRED_THEN
;
4403 vpt_block_state
.predicate_mask
= mve_extract_pred_mask (given
);
4404 vpt_block_state
.current_insn_num
= 0;
4405 vpt_block_state
.num_pred_insn
= num_instructions_vpt_block (given
);
4406 assert (vpt_block_state
.num_pred_insn
>= 1);
4409 static enum vpt_pred_state
4410 invert_next_predicate_state (enum vpt_pred_state astate
)
4412 if (astate
== PRED_THEN
)
4414 else if (astate
== PRED_ELSE
)
4420 static enum vpt_pred_state
4421 update_next_predicate_state (void)
4423 long pred_mask
= vpt_block_state
.predicate_mask
;
4424 long mask_for_insn
= 0;
4426 switch (vpt_block_state
.current_insn_num
)
4444 if (pred_mask
& mask_for_insn
)
4445 return invert_next_predicate_state (vpt_block_state
.next_pred_state
);
4447 return vpt_block_state
.next_pred_state
;
4451 update_vpt_block_state (void)
4453 vpt_block_state
.current_insn_num
++;
4454 if (vpt_block_state
.current_insn_num
== vpt_block_state
.num_pred_insn
)
4456 /* No more instructions to process in vpt block. */
4457 mark_outside_vpt_block ();
4461 vpt_block_state
.next_pred_state
= update_next_predicate_state ();
4464 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
4465 Returns pointer to following character of the format string and
4466 fills in *VALUEP and *WIDTHP with the extracted value and number of
4467 bits extracted. WIDTHP can be NULL. */
4470 arm_decode_bitfield (const char *ptr
,
4472 unsigned long *valuep
,
4475 unsigned long value
= 0;
4483 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
4484 start
= start
* 10 + *ptr
- '0';
4486 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
4487 end
= end
* 10 + *ptr
- '0';
4493 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
4496 while (*ptr
++ == ',');
4504 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
4505 bfd_boolean print_shift
)
4507 func (stream
, "%s", arm_regnames
[given
& 0xf]);
4509 if ((given
& 0xff0) != 0)
4511 if ((given
& 0x10) == 0)
4513 int amount
= (given
& 0xf80) >> 7;
4514 int shift
= (given
& 0x60) >> 5;
4520 func (stream
, ", rrx");
4528 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
4530 func (stream
, ", #%d", amount
);
4532 else if ((given
& 0x80) == 0x80)
4533 func (stream
, "\t; <illegal shifter operand>");
4534 else if (print_shift
)
4535 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
4536 arm_regnames
[(given
& 0xf00) >> 8]);
4538 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
4542 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
4545 is_mve_okay_in_it (enum mve_instructions matched_insn
)
4547 switch (matched_insn
)
4549 case MVE_VMOV_GP_TO_VEC_LANE
:
4550 case MVE_VMOV2_VEC_LANE_TO_GP
:
4551 case MVE_VMOV2_GP_TO_VEC_LANE
:
4552 case MVE_VMOV_VEC_LANE_TO_GP
:
4560 is_mve_architecture (struct disassemble_info
*info
)
4562 struct arm_private_data
*private_data
= info
->private_data
;
4563 arm_feature_set allowed_arches
= private_data
->features
;
4565 arm_feature_set arm_ext_v8_1m_main
4566 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
4568 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
4569 && !ARM_CPU_IS_ANY (allowed_arches
))
4576 is_vpt_instruction (long given
)
4579 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
4580 if ((given
& 0x0040e000) == 0)
4583 /* VPT floating point T1 variant. */
4584 if (((given
& 0xefb10f50) == 0xee310f00 && ((given
& 0x1001) != 0x1))
4585 /* VPT floating point T2 variant. */
4586 || ((given
& 0xefb10f50) == 0xee310f40)
4587 /* VPT vector T1 variant. */
4588 || ((given
& 0xff811f51) == 0xfe010f00)
4589 /* VPT vector T2 variant. */
4590 || ((given
& 0xff811f51) == 0xfe010f01
4591 && ((given
& 0x300000) != 0x300000))
4592 /* VPT vector T3 variant. */
4593 || ((given
& 0xff811f50) == 0xfe011f00)
4594 /* VPT vector T4 variant. */
4595 || ((given
& 0xff811f70) == 0xfe010f40)
4596 /* VPT vector T5 variant. */
4597 || ((given
& 0xff811f70) == 0xfe010f60)
4598 /* VPT vector T6 variant. */
4599 || ((given
& 0xff811f50) == 0xfe011f40)
4600 /* VPST vector T variant. */
4601 || ((given
& 0xffbf1fff) == 0xfe310f4d))
4607 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
4608 and ending bitfield = END. END must be greater than START. */
4610 static unsigned long
4611 arm_decode_field (unsigned long given
, unsigned int start
, unsigned int end
)
4613 int bits
= end
- start
;
4618 return ((given
>> start
) & ((2ul << bits
) - 1));
4621 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
4622 START:END and START2:END2. END/END2 must be greater than
4625 static unsigned long
4626 arm_decode_field_multiple (unsigned long given
, unsigned int start
,
4627 unsigned int end
, unsigned int start2
,
4630 int bits
= end
- start
;
4631 int bits2
= end2
- start2
;
4632 unsigned long value
= 0;
4638 value
= arm_decode_field (given
, start
, end
);
4641 value
|= ((given
>> start2
) & ((2ul << bits2
) - 1)) << width
;
4645 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
4646 This helps us decode instructions that change mnemonic depending on specific
4647 operand values/encodings. */
4650 is_mve_encoding_conflict (unsigned long given
,
4651 enum mve_instructions matched_insn
)
4653 switch (matched_insn
)
4656 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4662 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4664 if ((arm_decode_field (given
, 12, 12) == 0)
4665 && (arm_decode_field (given
, 0, 0) == 1))
4670 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4672 if (arm_decode_field (given
, 0, 3) == 0xd)
4676 case MVE_VPT_VEC_T1
:
4677 case MVE_VPT_VEC_T2
:
4678 case MVE_VPT_VEC_T3
:
4679 case MVE_VPT_VEC_T4
:
4680 case MVE_VPT_VEC_T5
:
4681 case MVE_VPT_VEC_T6
:
4682 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4684 if (arm_decode_field (given
, 20, 21) == 3)
4688 case MVE_VCMP_FP_T1
:
4689 if ((arm_decode_field (given
, 12, 12) == 0)
4690 && (arm_decode_field (given
, 0, 0) == 1))
4695 case MVE_VCMP_FP_T2
:
4696 if (arm_decode_field (given
, 0, 3) == 0xd)
4710 case MVE_VQDMULH_T3
:
4711 case MVE_VQRDMULH_T4
:
4717 case MVE_VCMP_VEC_T1
:
4718 case MVE_VCMP_VEC_T2
:
4719 case MVE_VCMP_VEC_T3
:
4720 case MVE_VCMP_VEC_T4
:
4721 case MVE_VCMP_VEC_T5
:
4722 case MVE_VCMP_VEC_T6
:
4723 if (arm_decode_field (given
, 20, 21) == 3)
4732 if (arm_decode_field (given
, 7, 8) == 3)
4739 if ((arm_decode_field (given
, 24, 24) == 0)
4740 && (arm_decode_field (given
, 21, 21) == 0))
4744 else if ((arm_decode_field (given
, 7, 8) == 3))
4752 if ((arm_decode_field (given
, 24, 24) == 0)
4753 && (arm_decode_field (given
, 21, 21) == 0))
4760 case MVE_VCVT_FP_FIX_VEC
:
4761 return (arm_decode_field (given
, 16, 21) & 0x38) == 0;
4766 unsigned long cmode
= arm_decode_field (given
, 8, 11);
4768 if ((cmode
& 1) == 0)
4770 else if ((cmode
& 0xc) == 0xc)
4778 unsigned long cmode
= arm_decode_field (given
, 8, 11);
4780 if ((cmode
& 9) == 1)
4782 else if ((cmode
& 5) == 1)
4784 else if ((cmode
& 0xe) == 0xe)
4790 case MVE_VMOV_IMM_TO_VEC
:
4791 if ((arm_decode_field (given
, 5, 5) == 1)
4792 && (arm_decode_field (given
, 8, 11) != 0xe))
4799 unsigned long size
= arm_decode_field (given
, 19, 20);
4800 if ((size
== 0) || (size
== 3))
4810 if (arm_decode_field (given
, 18, 19) == 3)
4816 case MVE_VRMLSLDAVH
:
4819 if (arm_decode_field (given
, 20, 22) == 7)
4824 case MVE_VRMLALDAVH
:
4825 if ((arm_decode_field (given
, 20, 22) & 6) == 6)
4832 if ((arm_decode_field (given
, 20, 21) == 3)
4833 || (arm_decode_field (given
, 1, 3) == 7))
4845 print_mve_vld_str_addr (struct disassemble_info
*info
,
4846 unsigned long given
,
4847 enum mve_instructions matched_insn
)
4849 void *stream
= info
->stream
;
4850 fprintf_ftype func
= info
->fprintf_func
;
4852 unsigned long p
, w
, gpr
, imm
, add
, mod_imm
;
4854 imm
= arm_decode_field (given
, 0, 6);
4857 switch (matched_insn
)
4861 gpr
= arm_decode_field (given
, 16, 18);
4866 gpr
= arm_decode_field (given
, 16, 18);
4872 gpr
= arm_decode_field (given
, 16, 19);
4878 gpr
= arm_decode_field (given
, 16, 19);
4884 gpr
= arm_decode_field (given
, 16, 19);
4891 p
= arm_decode_field (given
, 24, 24);
4892 w
= arm_decode_field (given
, 21, 21);
4894 add
= arm_decode_field (given
, 23, 23);
4898 /* Don't print anything for '+' as it is implied. */
4908 func (stream
, "[%s, #%s%lu]", arm_regnames
[gpr
], add_sub
, mod_imm
);
4909 /* Pre-indexed mode. */
4911 func (stream
, "[%s, #%s%lu]!", arm_regnames
[gpr
], add_sub
, mod_imm
);
4913 else if ((p
== 0) && (w
== 1))
4914 /* Post-index mode. */
4915 func (stream
, "[%s], #%s%lu", arm_regnames
[gpr
], add_sub
, mod_imm
);
4918 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
4919 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
4920 this encoding is undefined. */
4923 is_mve_undefined (unsigned long given
, enum mve_instructions matched_insn
,
4924 enum mve_undefined
*undefined_code
)
4926 *undefined_code
= UNDEF_NONE
;
4928 switch (matched_insn
)
4931 if (arm_decode_field_multiple (given
, 5, 5, 22, 22) == 3)
4933 *undefined_code
= UNDEF_SIZE_3
;
4939 case MVE_VQDMULH_T1
:
4940 case MVE_VQRDMULH_T2
:
4944 if (arm_decode_field (given
, 20, 21) == 3)
4946 *undefined_code
= UNDEF_SIZE_3
;
4953 if (arm_decode_field (given
, 7, 8) == 3)
4955 *undefined_code
= UNDEF_SIZE_3
;
4962 if (arm_decode_field (given
, 7, 8) <= 1)
4964 *undefined_code
= UNDEF_SIZE_LE_1
;
4971 if ((arm_decode_field (given
, 7, 8) == 0))
4973 *undefined_code
= UNDEF_SIZE_0
;
4980 if ((arm_decode_field (given
, 7, 8) <= 1))
4982 *undefined_code
= UNDEF_SIZE_LE_1
;
4988 case MVE_VLDRB_GATHER_T1
:
4989 if (arm_decode_field (given
, 7, 8) == 3)
4991 *undefined_code
= UNDEF_SIZE_3
;
4994 else if ((arm_decode_field (given
, 28, 28) == 0)
4995 && (arm_decode_field (given
, 7, 8) == 0))
4997 *undefined_code
= UNDEF_NOT_UNS_SIZE_0
;
5003 case MVE_VLDRH_GATHER_T2
:
5004 if (arm_decode_field (given
, 7, 8) == 3)
5006 *undefined_code
= UNDEF_SIZE_3
;
5009 else if ((arm_decode_field (given
, 28, 28) == 0)
5010 && (arm_decode_field (given
, 7, 8) == 1))
5012 *undefined_code
= UNDEF_NOT_UNS_SIZE_1
;
5015 else if (arm_decode_field (given
, 7, 8) == 0)
5017 *undefined_code
= UNDEF_SIZE_0
;
5023 case MVE_VLDRW_GATHER_T3
:
5024 if (arm_decode_field (given
, 7, 8) != 2)
5026 *undefined_code
= UNDEF_SIZE_NOT_2
;
5029 else if (arm_decode_field (given
, 28, 28) == 0)
5031 *undefined_code
= UNDEF_NOT_UNSIGNED
;
5037 case MVE_VLDRD_GATHER_T4
:
5038 if (arm_decode_field (given
, 7, 8) != 3)
5040 *undefined_code
= UNDEF_SIZE_NOT_3
;
5043 else if (arm_decode_field (given
, 28, 28) == 0)
5045 *undefined_code
= UNDEF_NOT_UNSIGNED
;
5051 case MVE_VSTRB_SCATTER_T1
:
5052 if (arm_decode_field (given
, 7, 8) == 3)
5054 *undefined_code
= UNDEF_SIZE_3
;
5060 case MVE_VSTRH_SCATTER_T2
:
5062 unsigned long size
= arm_decode_field (given
, 7, 8);
5065 *undefined_code
= UNDEF_SIZE_3
;
5070 *undefined_code
= UNDEF_SIZE_0
;
5077 case MVE_VSTRW_SCATTER_T3
:
5078 if (arm_decode_field (given
, 7, 8) != 2)
5080 *undefined_code
= UNDEF_SIZE_NOT_2
;
5086 case MVE_VSTRD_SCATTER_T4
:
5087 if (arm_decode_field (given
, 7, 8) != 3)
5089 *undefined_code
= UNDEF_SIZE_NOT_3
;
5095 case MVE_VCVT_FP_FIX_VEC
:
5097 unsigned long imm6
= arm_decode_field (given
, 16, 21);
5098 if ((imm6
& 0x20) == 0)
5100 *undefined_code
= UNDEF_VCVT_IMM6
;
5104 if ((arm_decode_field (given
, 9, 9) == 0)
5105 && ((imm6
& 0x30) == 0x20))
5107 *undefined_code
= UNDEF_VCVT_FSI_IMM6
;
5114 case MVE_VCVT_BETWEEN_FP_INT
:
5115 case MVE_VCVT_FROM_FP_TO_INT
:
5117 unsigned long size
= arm_decode_field (given
, 18, 19);
5120 *undefined_code
= UNDEF_SIZE_0
;
5125 *undefined_code
= UNDEF_SIZE_3
;
5132 case MVE_VMOV_VEC_LANE_TO_GP
:
5134 unsigned long op1
= arm_decode_field (given
, 21, 22);
5135 unsigned long op2
= arm_decode_field (given
, 5, 6);
5136 unsigned long u
= arm_decode_field (given
, 23, 23);
5138 if ((op2
== 0) && (u
== 1))
5140 if ((op1
== 0) || (op1
== 1))
5142 *undefined_code
= UNDEF_BAD_U_OP1_OP2
;
5150 if ((op1
== 0) || (op1
== 1))
5152 *undefined_code
= UNDEF_BAD_OP1_OP2
;
5162 case MVE_VMOV_GP_TO_VEC_LANE
:
5163 if (arm_decode_field (given
, 5, 6) == 2)
5165 unsigned long op1
= arm_decode_field (given
, 21, 22);
5166 if ((op1
== 0) || (op1
== 1))
5168 *undefined_code
= UNDEF_BAD_OP1_OP2
;
5177 case MVE_VMOV_IMM_TO_VEC
:
5178 if (arm_decode_field (given
, 5, 5) == 0)
5180 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5182 if (((cmode
& 9) == 1) || ((cmode
& 5) == 1))
5184 *undefined_code
= UNDEF_OP_0_BAD_CMODE
;
5194 if (arm_decode_field (given
, 18, 19) == 2)
5196 *undefined_code
= UNDEF_SIZE_2
;
5202 case MVE_VRMLALDAVH
:
5203 case MVE_VMLADAV_T1
:
5204 case MVE_VMLADAV_T2
:
5206 if ((arm_decode_field (given
, 28, 28) == 1)
5207 && (arm_decode_field (given
, 12, 12) == 1))
5209 *undefined_code
= UNDEF_XCHG_UNS
;
5220 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
5221 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
5222 why this encoding is unpredictable. */
5225 is_mve_unpredictable (unsigned long given
, enum mve_instructions matched_insn
,
5226 enum mve_unpredictable
*unpredictable_code
)
5228 *unpredictable_code
= UNPRED_NONE
;
5230 switch (matched_insn
)
5232 case MVE_VCMP_FP_T2
:
5234 if ((arm_decode_field (given
, 12, 12) == 0)
5235 && (arm_decode_field (given
, 5, 5) == 1))
5237 *unpredictable_code
= UNPRED_FCA_0_FCB_1
;
5243 case MVE_VPT_VEC_T4
:
5244 case MVE_VPT_VEC_T5
:
5245 case MVE_VPT_VEC_T6
:
5246 case MVE_VCMP_VEC_T4
:
5247 case MVE_VCMP_VEC_T5
:
5248 case MVE_VCMP_VEC_T6
:
5249 if (arm_decode_field (given
, 0, 3) == 0xd)
5251 *unpredictable_code
= UNPRED_R13
;
5259 unsigned long gpr
= arm_decode_field (given
, 12, 15);
5262 *unpredictable_code
= UNPRED_R13
;
5265 else if (gpr
== 0xf)
5267 *unpredictable_code
= UNPRED_R15
;
5278 case MVE_VQDMULH_T3
:
5279 case MVE_VQRDMULH_T4
:
5281 case MVE_VFMA_FP_SCALAR
:
5282 case MVE_VFMAS_FP_SCALAR
:
5286 unsigned long gpr
= arm_decode_field (given
, 0, 3);
5289 *unpredictable_code
= UNPRED_R13
;
5292 else if (gpr
== 0xf)
5294 *unpredictable_code
= UNPRED_R15
;
5304 unsigned long rn
= arm_decode_field (given
, 16, 19);
5306 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
5308 *unpredictable_code
= UNPRED_R13_AND_WB
;
5314 *unpredictable_code
= UNPRED_R15
;
5318 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 6)
5320 *unpredictable_code
= UNPRED_Q_GT_6
;
5330 unsigned long rn
= arm_decode_field (given
, 16, 19);
5332 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
5334 *unpredictable_code
= UNPRED_R13_AND_WB
;
5340 *unpredictable_code
= UNPRED_R15
;
5344 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 4)
5346 *unpredictable_code
= UNPRED_Q_GT_4
;
5360 unsigned long rn
= arm_decode_field (given
, 16, 19);
5362 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
5364 *unpredictable_code
= UNPRED_R13_AND_WB
;
5369 *unpredictable_code
= UNPRED_R15
;
5376 case MVE_VLDRB_GATHER_T1
:
5377 if (arm_decode_field (given
, 0, 0) == 1)
5379 *unpredictable_code
= UNPRED_OS
;
5384 /* To handle common code with T2-T4 variants. */
5385 case MVE_VLDRH_GATHER_T2
:
5386 case MVE_VLDRW_GATHER_T3
:
5387 case MVE_VLDRD_GATHER_T4
:
5389 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5390 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5394 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
5398 if (arm_decode_field (given
, 16, 19) == 0xf)
5400 *unpredictable_code
= UNPRED_R15
;
5407 case MVE_VLDRW_GATHER_T5
:
5408 case MVE_VLDRD_GATHER_T6
:
5410 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5411 unsigned long qm
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5415 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
5422 case MVE_VSTRB_SCATTER_T1
:
5423 if (arm_decode_field (given
, 16, 19) == 0xf)
5425 *unpredictable_code
= UNPRED_R15
;
5428 else if (arm_decode_field (given
, 0, 0) == 1)
5430 *unpredictable_code
= UNPRED_OS
;
5436 case MVE_VSTRH_SCATTER_T2
:
5437 case MVE_VSTRW_SCATTER_T3
:
5438 case MVE_VSTRD_SCATTER_T4
:
5439 if (arm_decode_field (given
, 16, 19) == 0xf)
5441 *unpredictable_code
= UNPRED_R15
;
5447 case MVE_VMOV2_VEC_LANE_TO_GP
:
5448 case MVE_VMOV2_GP_TO_VEC_LANE
:
5449 case MVE_VCVT_BETWEEN_FP_INT
:
5450 case MVE_VCVT_FROM_FP_TO_INT
:
5452 unsigned long rt
= arm_decode_field (given
, 0, 3);
5453 unsigned long rt2
= arm_decode_field (given
, 16, 19);
5455 if ((rt
== 0xd) || (rt2
== 0xd))
5457 *unpredictable_code
= UNPRED_R13
;
5460 else if ((rt
== 0xf) || (rt2
== 0xf))
5462 *unpredictable_code
= UNPRED_R15
;
5467 *unpredictable_code
= UNPRED_GP_REGS_EQUAL
;
5474 case MVE_VMOV_HFP_TO_GP
:
5475 case MVE_VMOV_GP_TO_VEC_LANE
:
5476 case MVE_VMOV_VEC_LANE_TO_GP
:
5478 unsigned long rda
= arm_decode_field (given
, 12, 15);
5481 *unpredictable_code
= UNPRED_R13
;
5484 else if (rda
== 0xf)
5486 *unpredictable_code
= UNPRED_R15
;
5503 if (arm_decode_field (given
, 20, 21) == 2)
5505 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5506 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5507 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5509 if ((Qd
== Qn
) || (Qd
== Qm
))
5511 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
5521 case MVE_VQDMULL_T1
:
5527 if (arm_decode_field (given
, 28, 28) == 1)
5529 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5530 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5531 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5533 if ((Qd
== Qn
) || (Qd
== Qm
))
5535 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
5545 case MVE_VQDMULL_T2
:
5547 unsigned long gpr
= arm_decode_field (given
, 0, 3);
5550 *unpredictable_code
= UNPRED_R13
;
5553 else if (gpr
== 0xf)
5555 *unpredictable_code
= UNPRED_R15
;
5559 if (arm_decode_field (given
, 28, 28) == 1)
5562 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
5563 unsigned long Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5567 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
5578 case MVE_VRMLSLDAVH
:
5581 if (arm_decode_field (given
, 20, 22) == 6)
5583 *unpredictable_code
= UNPRED_R13
;
5591 if (arm_decode_field (given
, 1, 3) == 6)
5593 *unpredictable_code
= UNPRED_R13
;
5605 print_mve_vmov_index (struct disassemble_info
*info
, unsigned long given
)
5607 unsigned long op1
= arm_decode_field (given
, 21, 22);
5608 unsigned long op2
= arm_decode_field (given
, 5, 6);
5609 unsigned long h
= arm_decode_field (given
, 16, 16);
5610 unsigned long index
, esize
, targetBeat
, idx
;
5611 void *stream
= info
->stream
;
5612 fprintf_ftype func
= info
->fprintf_func
;
5614 if ((op1
& 0x2) == 0x2)
5619 else if (((op1
& 0x2) == 0x0) && ((op2
& 0x1) == 0x1))
5624 else if (((op1
& 0x2) == 0) && ((op2
& 0x3) == 0))
5631 func (stream
, "<undefined index>");
5635 targetBeat
= (op1
& 0x1) | (h
<< 1);
5636 idx
= index
+ targetBeat
* (32/esize
);
5638 func (stream
, "%lu", idx
);
5641 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
5642 in length and integer of floating-point type. */
5644 print_simd_imm8 (struct disassemble_info
*info
, unsigned long given
,
5645 unsigned int ibit_loc
, const struct mopcode32
*insn
)
5648 int cmode
= (given
>> 8) & 0xf;
5649 int op
= (given
>> 5) & 0x1;
5650 unsigned long value
= 0, hival
= 0;
5654 void *stream
= info
->stream
;
5655 fprintf_ftype func
= info
->fprintf_func
;
5657 /* On Neon the 'i' bit is at bit 24, on mve it is
5659 bits
|= ((given
>> ibit_loc
) & 1) << 7;
5660 bits
|= ((given
>> 16) & 7) << 4;
5661 bits
|= ((given
>> 0) & 15) << 0;
5665 shift
= (cmode
>> 1) & 3;
5666 value
= (unsigned long) bits
<< (8 * shift
);
5669 else if (cmode
< 12)
5671 shift
= (cmode
>> 1) & 1;
5672 value
= (unsigned long) bits
<< (8 * shift
);
5675 else if (cmode
< 14)
5677 shift
= (cmode
& 1) + 1;
5678 value
= (unsigned long) bits
<< (8 * shift
);
5679 value
|= (1ul << (8 * shift
)) - 1;
5682 else if (cmode
== 14)
5686 /* Bit replication into bytes. */
5692 for (ix
= 7; ix
>= 0; ix
--)
5694 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
5696 value
= (value
<< 8) | mask
;
5698 hival
= (hival
<< 8) | mask
;
5704 /* Byte replication. */
5705 value
= (unsigned long) bits
;
5711 /* Floating point encoding. */
5714 value
= (unsigned long) (bits
& 0x7f) << 19;
5715 value
|= (unsigned long) (bits
& 0x80) << 24;
5716 tmp
= bits
& 0x40 ? 0x3c : 0x40;
5717 value
|= (unsigned long) tmp
<< 24;
5723 func (stream
, "<illegal constant %.8x:%x:%x>",
5729 // printU determines whether the immediate value should be printed as
5731 unsigned printU
= 0;
5732 switch (insn
->mve_op
)
5736 // We want this for instructions that don't have a 'signed' type
5740 case MVE_VMOV_IMM_TO_VEC
:
5747 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
5754 : "#%ld\t; 0x%.4lx", value
, value
);
5760 unsigned char valbytes
[4];
5763 /* Do this a byte at a time so we don't have to
5764 worry about the host's endianness. */
5765 valbytes
[0] = value
& 0xff;
5766 valbytes
[1] = (value
>> 8) & 0xff;
5767 valbytes
[2] = (value
>> 16) & 0xff;
5768 valbytes
[3] = (value
>> 24) & 0xff;
5770 floatformat_to_double
5771 (& floatformat_ieee_single_little
, valbytes
,
5774 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
5781 : "#%ld\t; 0x%.8lx",
5782 (long) (((value
& 0x80000000L
) != 0)
5784 ? value
| ~0xffffffffL
: value
),
5789 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
5799 print_mve_undefined (struct disassemble_info
*info
,
5800 enum mve_undefined undefined_code
)
5802 void *stream
= info
->stream
;
5803 fprintf_ftype func
= info
->fprintf_func
;
5805 func (stream
, "\t\tundefined instruction: ");
5807 switch (undefined_code
)
5810 func (stream
, "size equals zero");
5814 func (stream
, "size equals two");
5818 func (stream
, "size equals three");
5821 case UNDEF_SIZE_LE_1
:
5822 func (stream
, "size <= 1");
5825 case UNDEF_SIZE_NOT_2
:
5826 func (stream
, "size not equal to 2");
5829 case UNDEF_SIZE_NOT_3
:
5830 func (stream
, "size not equal to 3");
5833 case UNDEF_NOT_UNS_SIZE_0
:
5834 func (stream
, "not unsigned and size = zero");
5837 case UNDEF_NOT_UNS_SIZE_1
:
5838 func (stream
, "not unsigned and size = one");
5841 case UNDEF_NOT_UNSIGNED
:
5842 func (stream
, "not unsigned");
5845 case UNDEF_VCVT_IMM6
:
5846 func (stream
, "invalid imm6");
5849 case UNDEF_VCVT_FSI_IMM6
:
5850 func (stream
, "fsi = 0 and invalid imm6");
5853 case UNDEF_BAD_OP1_OP2
:
5854 func (stream
, "bad size with op2 = 2 and op1 = 0 or 1");
5857 case UNDEF_BAD_U_OP1_OP2
:
5858 func (stream
, "unsigned with op2 = 0 and op1 = 0 or 1");
5861 case UNDEF_OP_0_BAD_CMODE
:
5862 func (stream
, "op field equal 0 and bad cmode");
5865 case UNDEF_XCHG_UNS
:
5866 func (stream
, "exchange and unsigned together");
5876 print_mve_unpredictable (struct disassemble_info
*info
,
5877 enum mve_unpredictable unpredict_code
)
5879 void *stream
= info
->stream
;
5880 fprintf_ftype func
= info
->fprintf_func
;
5882 func (stream
, "%s: ", UNPREDICTABLE_INSTRUCTION
);
5884 switch (unpredict_code
)
5886 case UNPRED_IT_BLOCK
:
5887 func (stream
, "mve instruction in it block");
5890 case UNPRED_FCA_0_FCB_1
:
5891 func (stream
, "condition bits, fca = 0 and fcb = 1");
5895 func (stream
, "use of r13 (sp)");
5899 func (stream
, "use of r15 (pc)");
5903 func (stream
, "start register block > r4");
5907 func (stream
, "start register block > r6");
5910 case UNPRED_R13_AND_WB
:
5911 func (stream
, "use of r13 and write back");
5914 case UNPRED_Q_REGS_EQUAL
:
5916 "same vector register used for destination and other operand");
5920 func (stream
, "use of offset scaled");
5923 case UNPRED_GP_REGS_EQUAL
:
5924 func (stream
, "same general-purpose register used for both operands");
5927 case UNPRED_Q_REGS_EQ_AND_SIZE_1
:
5928 func (stream
, "use of identical q registers and size = 1");
5931 case UNPRED_Q_REGS_EQ_AND_SIZE_2
:
5932 func (stream
, "use of identical q registers and size = 1");
5940 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
5943 print_mve_register_blocks (struct disassemble_info
*info
,
5944 unsigned long given
,
5945 enum mve_instructions matched_insn
)
5947 void *stream
= info
->stream
;
5948 fprintf_ftype func
= info
->fprintf_func
;
5950 unsigned long q_reg_start
= arm_decode_field_multiple (given
,
5953 switch (matched_insn
)
5957 if (q_reg_start
<= 6)
5958 func (stream
, "{q%ld, q%ld}", q_reg_start
, q_reg_start
+ 1);
5960 func (stream
, "<illegal reg q%ld>", q_reg_start
);
5965 if (q_reg_start
<= 4)
5966 func (stream
, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start
,
5967 q_reg_start
+ 1, q_reg_start
+ 2,
5970 func (stream
, "<illegal reg q%ld>", q_reg_start
);
5979 print_mve_rounding_mode (struct disassemble_info
*info
,
5980 unsigned long given
,
5981 enum mve_instructions matched_insn
)
5983 void *stream
= info
->stream
;
5984 fprintf_ftype func
= info
->fprintf_func
;
5986 switch (matched_insn
)
5988 case MVE_VCVT_FROM_FP_TO_INT
:
5990 switch (arm_decode_field (given
, 8, 9))
6016 switch (arm_decode_field (given
, 7, 9))
6055 print_mve_vcvt_size (struct disassemble_info
*info
,
6056 unsigned long given
,
6057 enum mve_instructions matched_insn
)
6059 unsigned long mode
= 0;
6060 void *stream
= info
->stream
;
6061 fprintf_ftype func
= info
->fprintf_func
;
6063 switch (matched_insn
)
6065 case MVE_VCVT_FP_FIX_VEC
:
6067 mode
= (((given
& 0x200) >> 7)
6068 | ((given
& 0x10000000) >> 27)
6069 | ((given
& 0x100) >> 8));
6074 func (stream
, "f16.s16");
6078 func (stream
, "s16.f16");
6082 func (stream
, "f16.u16");
6086 func (stream
, "u16.f16");
6090 func (stream
, "f32.s32");
6094 func (stream
, "s32.f32");
6098 func (stream
, "f32.u32");
6102 func (stream
, "u32.f32");
6110 case MVE_VCVT_BETWEEN_FP_INT
:
6112 unsigned long size
= arm_decode_field (given
, 18, 19);
6113 unsigned long op
= arm_decode_field (given
, 7, 8);
6120 func (stream
, "f16.s16");
6124 func (stream
, "f16.u16");
6128 func (stream
, "s16.f16");
6132 func (stream
, "u16.f16");
6144 func (stream
, "f32.s32");
6148 func (stream
, "f32.u32");
6152 func (stream
, "s32.f32");
6156 func (stream
, "u32.f32");
6163 case MVE_VCVT_FP_HALF_FP
:
6165 unsigned long op
= arm_decode_field (given
, 28, 28);
6167 func (stream
, "f16.f32");
6169 func (stream
, "f32.f16");
6173 case MVE_VCVT_FROM_FP_TO_INT
:
6175 unsigned long size
= arm_decode_field_multiple (given
, 7, 7, 18, 19);
6180 func (stream
, "s16.f16");
6184 func (stream
, "u16.f16");
6188 func (stream
, "s32.f32");
6192 func (stream
, "u32.f32");
6207 print_instruction_predicate (struct disassemble_info
*info
)
6209 void *stream
= info
->stream
;
6210 fprintf_ftype func
= info
->fprintf_func
;
6212 if (vpt_block_state
.next_pred_state
== PRED_THEN
)
6214 else if (vpt_block_state
.next_pred_state
== PRED_ELSE
)
6219 print_mve_size (struct disassemble_info
*info
,
6221 enum mve_instructions matched_insn
)
6223 void *stream
= info
->stream
;
6224 fprintf_ftype func
= info
->fprintf_func
;
6226 switch (matched_insn
)
6229 case MVE_VCMP_VEC_T1
:
6230 case MVE_VCMP_VEC_T2
:
6231 case MVE_VCMP_VEC_T3
:
6232 case MVE_VCMP_VEC_T4
:
6233 case MVE_VCMP_VEC_T5
:
6234 case MVE_VCMP_VEC_T6
:
6245 case MVE_VLDRB_GATHER_T1
:
6246 case MVE_VLDRH_GATHER_T2
:
6247 case MVE_VLDRW_GATHER_T3
:
6248 case MVE_VLDRD_GATHER_T4
:
6252 case MVE_VPT_VEC_T1
:
6253 case MVE_VPT_VEC_T2
:
6254 case MVE_VPT_VEC_T3
:
6255 case MVE_VPT_VEC_T4
:
6256 case MVE_VPT_VEC_T5
:
6257 case MVE_VPT_VEC_T6
:
6266 case MVE_VQDMULH_T1
:
6267 case MVE_VQRDMULH_T2
:
6268 case MVE_VQDMULH_T3
:
6269 case MVE_VQRDMULH_T4
:
6274 case MVE_VSTRB_SCATTER_T1
:
6275 case MVE_VSTRH_SCATTER_T2
:
6276 case MVE_VSTRW_SCATTER_T3
:
6280 func (stream
, "%s", mve_vec_sizename
[size
]);
6282 func (stream
, "<undef size>");
6285 case MVE_VCMP_FP_T1
:
6286 case MVE_VCMP_FP_T2
:
6287 case MVE_VFMA_FP_SCALAR
:
6290 case MVE_VFMAS_FP_SCALAR
:
6294 func (stream
, "32");
6296 func (stream
, "16");
6299 case MVE_VMLADAV_T1
:
6301 case MVE_VMLSDAV_T1
:
6304 case MVE_VQDMULL_T1
:
6305 case MVE_VQDMULL_T2
:
6309 func (stream
, "16");
6311 func (stream
, "32");
6318 func (stream
, "16");
6325 func (stream
, "32");
6328 func (stream
, "16");
6338 case MVE_VMOV_GP_TO_VEC_LANE
:
6339 case MVE_VMOV_VEC_LANE_TO_GP
:
6343 func (stream
, "32");
6348 func (stream
, "16");
6351 case 8: case 9: case 10: case 11:
6352 case 12: case 13: case 14: case 15:
6361 case MVE_VMOV_IMM_TO_VEC
:
6364 case 0: case 4: case 8:
6365 case 12: case 24: case 26:
6366 func (stream
, "i32");
6369 func (stream
, "i16");
6372 func (stream
, "i8");
6375 func (stream
, "i64");
6378 func (stream
, "f32");
6385 case MVE_VMULL_POLY
:
6387 func (stream
, "p8");
6389 func (stream
, "p16");
6395 case 0: case 2: case 4:
6396 case 6: case 12: case 13:
6397 func (stream
, "32");
6401 func (stream
, "16");
6415 func (stream
, "32");
6419 func (stream
, "16");
6433 print_vec_condition (struct disassemble_info
*info
, long given
,
6434 enum mve_instructions matched_insn
)
6436 void *stream
= info
->stream
;
6437 fprintf_ftype func
= info
->fprintf_func
;
6440 switch (matched_insn
)
6443 case MVE_VCMP_FP_T1
:
6444 vec_cond
= (((given
& 0x1000) >> 10)
6445 | ((given
& 1) << 1)
6446 | ((given
& 0x0080) >> 7));
6447 func (stream
, "%s",vec_condnames
[vec_cond
]);
6451 case MVE_VCMP_FP_T2
:
6452 vec_cond
= (((given
& 0x1000) >> 10)
6453 | ((given
& 0x0020) >> 4)
6454 | ((given
& 0x0080) >> 7));
6455 func (stream
, "%s",vec_condnames
[vec_cond
]);
6458 case MVE_VPT_VEC_T1
:
6459 case MVE_VCMP_VEC_T1
:
6460 vec_cond
= (given
& 0x0080) >> 7;
6461 func (stream
, "%s",vec_condnames
[vec_cond
]);
6464 case MVE_VPT_VEC_T2
:
6465 case MVE_VCMP_VEC_T2
:
6466 vec_cond
= 2 | ((given
& 0x0080) >> 7);
6467 func (stream
, "%s",vec_condnames
[vec_cond
]);
6470 case MVE_VPT_VEC_T3
:
6471 case MVE_VCMP_VEC_T3
:
6472 vec_cond
= 4 | ((given
& 1) << 1) | ((given
& 0x0080) >> 7);
6473 func (stream
, "%s",vec_condnames
[vec_cond
]);
6476 case MVE_VPT_VEC_T4
:
6477 case MVE_VCMP_VEC_T4
:
6478 vec_cond
= (given
& 0x0080) >> 7;
6479 func (stream
, "%s",vec_condnames
[vec_cond
]);
6482 case MVE_VPT_VEC_T5
:
6483 case MVE_VCMP_VEC_T5
:
6484 vec_cond
= 2 | ((given
& 0x0080) >> 7);
6485 func (stream
, "%s",vec_condnames
[vec_cond
]);
6488 case MVE_VPT_VEC_T6
:
6489 case MVE_VCMP_VEC_T6
:
6490 vec_cond
= 4 | ((given
& 0x0020) >> 4) | ((given
& 0x0080) >> 7);
6491 func (stream
, "%s",vec_condnames
[vec_cond
]);
6506 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
6507 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
6508 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
6509 #define PRE_BIT_SET (given & (1 << P_BIT))
6512 /* Print one coprocessor instruction on INFO->STREAM.
6513 Return TRUE if the instuction matched, FALSE if this is not a
6514 recognised coprocessor instruction. */
6517 print_insn_coprocessor (bfd_vma pc
,
6518 struct disassemble_info
*info
,
6522 const struct sopcode32
*insn
;
6523 void *stream
= info
->stream
;
6524 fprintf_ftype func
= info
->fprintf_func
;
6526 unsigned long value
= 0;
6529 struct arm_private_data
*private_data
= info
->private_data
;
6530 arm_feature_set allowed_arches
= ARM_ARCH_NONE
;
6531 arm_feature_set arm_ext_v8_1m_main
=
6532 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
6534 allowed_arches
= private_data
->features
;
6536 for (insn
= coprocessor_opcodes
; insn
->assembler
; insn
++)
6538 unsigned long u_reg
= 16;
6539 bfd_boolean is_unpredictable
= FALSE
;
6540 signed long value_in_comment
= 0;
6543 if (ARM_FEATURE_ZERO (insn
->arch
))
6544 switch (insn
->value
)
6546 case SENTINEL_IWMMXT_START
:
6547 if (info
->mach
!= bfd_mach_arm_XScale
6548 && info
->mach
!= bfd_mach_arm_iWMMXt
6549 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
6552 while ((! ARM_FEATURE_ZERO (insn
->arch
))
6553 && insn
->value
!= SENTINEL_IWMMXT_END
);
6556 case SENTINEL_IWMMXT_END
:
6559 case SENTINEL_GENERIC_START
:
6560 allowed_arches
= private_data
->features
;
6568 value
= insn
->value
;
6569 cp_num
= (given
>> 8) & 0xf;
6573 /* The high 4 bits are 0xe for Arm conditional instructions, and
6574 0xe for arm unconditional instructions. The rest of the
6575 encoding is the same. */
6577 value
|= 0xe0000000;
6585 /* Only match unconditional instuctions against unconditional
6587 if ((given
& 0xf0000000) == 0xf0000000)
6594 cond
= (given
>> 28) & 0xf;
6600 if ((insn
->isa
== T32
&& !thumb
)
6601 || (insn
->isa
== ARM
&& thumb
))
6604 if ((given
& mask
) != value
)
6607 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, allowed_arches
))
6610 if (insn
->value
== 0xfe000010 /* mcr2 */
6611 || insn
->value
== 0xfe100010 /* mrc2 */
6612 || insn
->value
== 0xfc100000 /* ldc2 */
6613 || insn
->value
== 0xfc000000) /* stc2 */
6615 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
6616 is_unpredictable
= TRUE
;
6618 /* Armv8.1-M Mainline FP & MVE instructions. */
6619 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
6620 && !ARM_CPU_IS_ANY (allowed_arches
)
6621 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
6625 else if (insn
->value
== 0x0e000000 /* cdp */
6626 || insn
->value
== 0xfe000000 /* cdp2 */
6627 || insn
->value
== 0x0e000010 /* mcr */
6628 || insn
->value
== 0x0e100010 /* mrc */
6629 || insn
->value
== 0x0c100000 /* ldc */
6630 || insn
->value
== 0x0c000000) /* stc */
6632 /* Floating-point instructions. */
6633 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
6636 /* Armv8.1-M Mainline FP & MVE instructions. */
6637 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
6638 && !ARM_CPU_IS_ANY (allowed_arches
)
6639 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
6642 else if ((insn
->value
== 0xec100f80 /* vldr (system register) */
6643 || insn
->value
== 0xec000f80) /* vstr (system register) */
6644 && arm_decode_field (given
, 24, 24) == 0
6645 && arm_decode_field (given
, 21, 21) == 0)
6646 /* If the P and W bits are both 0 then these encodings match the MVE
6647 VLDR and VSTR instructions, these are in a different table, so we
6648 don't let it match here. */
6651 for (c
= insn
->assembler
; *c
; c
++)
6655 const char mod
= *++c
;
6659 func (stream
, "%%");
6665 int rn
= (given
>> 16) & 0xf;
6666 bfd_vma offset
= given
& 0xff;
6669 offset
= given
& 0x7f;
6671 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
6673 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
6675 /* Not unindexed. The offset is scaled. */
6677 /* vldr.16/vstr.16 will shift the address
6678 left by 1 bit only. */
6679 offset
= offset
* 2;
6681 offset
= offset
* 4;
6683 if (NEGATIVE_BIT_SET
)
6686 value_in_comment
= offset
;
6692 func (stream
, ", #%d]%s",
6694 WRITEBACK_BIT_SET
? "!" : "");
6695 else if (NEGATIVE_BIT_SET
)
6696 func (stream
, ", #-0]");
6704 if (WRITEBACK_BIT_SET
)
6707 func (stream
, ", #%d", (int) offset
);
6708 else if (NEGATIVE_BIT_SET
)
6709 func (stream
, ", #-0");
6713 func (stream
, ", {%s%d}",
6714 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
6716 value_in_comment
= offset
;
6719 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
6721 func (stream
, "\t; ");
6722 /* For unaligned PCs, apply off-by-alignment
6724 info
->print_address_func (offset
+ pc
6725 + info
->bytes_per_chunk
* 2
6734 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
6735 int offset
= (given
>> 1) & 0x3f;
6738 func (stream
, "{d%d}", regno
);
6739 else if (regno
+ offset
> 32)
6740 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
6742 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
6748 bfd_boolean single
= ((given
>> 8) & 1) == 0;
6749 char reg_prefix
= single
? 's' : 'd';
6750 int Dreg
= (given
>> 22) & 0x1;
6751 int Vdreg
= (given
>> 12) & 0xf;
6752 int reg
= single
? ((Vdreg
<< 1) | Dreg
)
6753 : ((Dreg
<< 4) | Vdreg
);
6754 int num
= (given
>> (single
? 0 : 1)) & 0x7f;
6755 int maxreg
= single
? 31 : 15;
6756 int topreg
= reg
+ num
- 1;
6759 func (stream
, "{VPR}");
6761 func (stream
, "{%c%d, VPR}", reg_prefix
, reg
);
6762 else if (topreg
> maxreg
)
6763 func (stream
, "{%c%d-<overflow reg d%d, VPR}",
6764 reg_prefix
, reg
, single
? topreg
>> 1 : topreg
);
6766 func (stream
, "{%c%d-%c%d, VPR}", reg_prefix
, reg
,
6767 reg_prefix
, topreg
);
6772 if (cond
!= COND_UNCOND
)
6773 is_unpredictable
= TRUE
;
6777 if (cond
!= COND_UNCOND
&& cp_num
== 9)
6778 is_unpredictable
= TRUE
;
6780 func (stream
, "%s", arm_conditional
[cond
]);
6784 /* Print a Cirrus/DSP shift immediate. */
6785 /* Immediates are 7bit signed ints with bits 0..3 in
6786 bits 0..3 of opcode and bits 4..6 in bits 5..7
6791 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
6793 /* Is ``imm'' a negative number? */
6797 func (stream
, "%d", imm
);
6805 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
6810 func (stream
, "FPSCR");
6813 func (stream
, "FPSCR_nzcvqc");
6816 func (stream
, "VPR");
6819 func (stream
, "P0");
6822 func (stream
, "FPCXTNS");
6825 func (stream
, "FPCXTS");
6828 func (stream
, "<invalid reg %lu>", regno
);
6835 switch (given
& 0x00408000)
6852 switch (given
& 0x00080080)
6864 func (stream
, _("<illegal precision>"));
6870 switch (given
& 0x00408000)
6888 switch (given
& 0x60)
6904 case '0': case '1': case '2': case '3': case '4':
6905 case '5': case '6': case '7': case '8': case '9':
6909 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
6915 is_unpredictable
= TRUE
;
6920 /* Eat the 'u' character. */
6924 is_unpredictable
= TRUE
;
6927 func (stream
, "%s", arm_regnames
[value
]);
6930 if (given
& (1 << 6))
6934 func (stream
, "d%ld", value
);
6939 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
6941 func (stream
, "q%ld", value
>> 1);
6944 func (stream
, "%ld", value
);
6945 value_in_comment
= value
;
6949 /* Converts immediate 8 bit back to float value. */
6950 unsigned floatVal
= (value
& 0x80) << 24
6951 | (value
& 0x3F) << 19
6952 | ((value
& 0x40) ? (0xF8 << 22) : (1 << 30));
6954 /* Quarter float have a maximum value of 31.0.
6955 Get floating point value multiplied by 1e7.
6956 The maximum value stays in limit of a 32-bit int. */
6958 (78125 << (((floatVal
>> 23) & 0xFF) - 124)) *
6959 (16 + (value
& 0xF));
6961 if (!(decVal
% 1000000))
6962 func (stream
, "%ld\t; 0x%08x %c%u.%01u", value
,
6963 floatVal
, value
& 0x80 ? '-' : ' ',
6965 decVal
% 10000000 / 1000000);
6966 else if (!(decVal
% 10000))
6967 func (stream
, "%ld\t; 0x%08x %c%u.%03u", value
,
6968 floatVal
, value
& 0x80 ? '-' : ' ',
6970 decVal
% 10000000 / 10000);
6972 func (stream
, "%ld\t; 0x%08x %c%u.%07u", value
,
6973 floatVal
, value
& 0x80 ? '-' : ' ',
6974 decVal
/ 10000000, decVal
% 10000000);
6979 int from
= (given
& (1 << 7)) ? 32 : 16;
6980 func (stream
, "%ld", from
- value
);
6986 func (stream
, "#%s", arm_fp_const
[value
& 7]);
6988 func (stream
, "f%ld", value
);
6993 func (stream
, "%s", iwmmxt_wwnames
[value
]);
6995 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
6999 func (stream
, "%s", iwmmxt_regnames
[value
]);
7002 func (stream
, "%s", iwmmxt_cregnames
[value
]);
7006 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
7013 func (stream
, "eq");
7017 func (stream
, "vs");
7021 func (stream
, "ge");
7025 func (stream
, "gt");
7029 func (stream
, "??");
7037 func (stream
, "%c", *c
);
7041 if (value
== ((1ul << width
) - 1))
7042 func (stream
, "%c", *c
);
7045 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
7057 int single
= *c
++ == 'y';
7062 case '4': /* Sm pair */
7063 case '0': /* Sm, Dm */
7064 regno
= given
& 0x0000000f;
7068 regno
+= (given
>> 5) & 1;
7071 regno
+= ((given
>> 5) & 1) << 4;
7074 case '1': /* Sd, Dd */
7075 regno
= (given
>> 12) & 0x0000000f;
7079 regno
+= (given
>> 22) & 1;
7082 regno
+= ((given
>> 22) & 1) << 4;
7085 case '2': /* Sn, Dn */
7086 regno
= (given
>> 16) & 0x0000000f;
7090 regno
+= (given
>> 7) & 1;
7093 regno
+= ((given
>> 7) & 1) << 4;
7096 case '3': /* List */
7098 regno
= (given
>> 12) & 0x0000000f;
7102 regno
+= (given
>> 22) & 1;
7105 regno
+= ((given
>> 22) & 1) << 4;
7112 func (stream
, "%c%d", single
? 's' : 'd', regno
);
7116 int count
= given
& 0xff;
7123 func (stream
, "-%c%d",
7131 func (stream
, ", %c%d", single
? 's' : 'd',
7137 switch (given
& 0x00400100)
7139 case 0x00000000: func (stream
, "b"); break;
7140 case 0x00400000: func (stream
, "h"); break;
7141 case 0x00000100: func (stream
, "w"); break;
7142 case 0x00400100: func (stream
, "d"); break;
7150 /* given (20, 23) | given (0, 3) */
7151 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
7152 func (stream
, "%d", (int) value
);
7157 /* This is like the 'A' operator, except that if
7158 the width field "M" is zero, then the offset is
7159 *not* multiplied by four. */
7161 int offset
= given
& 0xff;
7162 int multiplier
= (given
& 0x00000100) ? 4 : 1;
7164 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
7168 value_in_comment
= offset
* multiplier
;
7169 if (NEGATIVE_BIT_SET
)
7170 value_in_comment
= - value_in_comment
;
7176 func (stream
, ", #%s%d]%s",
7177 NEGATIVE_BIT_SET
? "-" : "",
7178 offset
* multiplier
,
7179 WRITEBACK_BIT_SET
? "!" : "");
7181 func (stream
, "], #%s%d",
7182 NEGATIVE_BIT_SET
? "-" : "",
7183 offset
* multiplier
);
7192 int imm4
= (given
>> 4) & 0xf;
7193 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
7194 int ubit
= ! NEGATIVE_BIT_SET
;
7195 const char *rm
= arm_regnames
[given
& 0xf];
7196 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
7202 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
7204 func (stream
, ", lsl #%d", imm4
);
7211 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
7213 func (stream
, ", lsl #%d", imm4
);
7215 if (puw_bits
== 5 || puw_bits
== 7)
7220 func (stream
, "INVALID");
7228 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
7229 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
7238 func (stream
, "%c", *c
);
7241 if (value_in_comment
> 32 || value_in_comment
< -16)
7242 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
7244 if (is_unpredictable
)
7245 func (stream
, UNPREDICTABLE_INSTRUCTION
);
7252 /* Decodes and prints ARM addressing modes. Returns the offset
7253 used in the address, if any, if it is worthwhile printing the
7254 offset as a hexadecimal value in a comment at the end of the
7255 line of disassembly. */
7258 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
7260 void *stream
= info
->stream
;
7261 fprintf_ftype func
= info
->fprintf_func
;
7264 if (((given
& 0x000f0000) == 0x000f0000)
7265 && ((given
& 0x02000000) == 0))
7267 offset
= given
& 0xfff;
7269 func (stream
, "[pc");
7273 /* Pre-indexed. Elide offset of positive zero when
7275 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
7276 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7278 if (NEGATIVE_BIT_SET
)
7283 /* Cope with the possibility of write-back
7284 being used. Probably a very dangerous thing
7285 for the programmer to do, but who are we to
7287 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
7289 else /* Post indexed. */
7291 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7293 /* Ie ignore the offset. */
7297 func (stream
, "\t; ");
7298 info
->print_address_func (offset
, info
);
7303 func (stream
, "[%s",
7304 arm_regnames
[(given
>> 16) & 0xf]);
7308 if ((given
& 0x02000000) == 0)
7310 /* Elide offset of positive zero when non-writeback. */
7311 offset
= given
& 0xfff;
7312 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
7313 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7317 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
7318 arm_decode_shift (given
, func
, stream
, TRUE
);
7321 func (stream
, "]%s",
7322 WRITEBACK_BIT_SET
? "!" : "");
7326 if ((given
& 0x02000000) == 0)
7328 /* Always show offset. */
7329 offset
= given
& 0xfff;
7330 func (stream
, "], #%s%d",
7331 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7335 func (stream
, "], %s",
7336 NEGATIVE_BIT_SET
? "-" : "");
7337 arm_decode_shift (given
, func
, stream
, TRUE
);
7340 if (NEGATIVE_BIT_SET
)
7344 return (signed long) offset
;
7347 /* Print one neon instruction on INFO->STREAM.
7348 Return TRUE if the instuction matched, FALSE if this is not a
7349 recognised neon instruction. */
7352 print_insn_neon (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
7354 const struct opcode32
*insn
;
7355 void *stream
= info
->stream
;
7356 fprintf_ftype func
= info
->fprintf_func
;
7360 if ((given
& 0xef000000) == 0xef000000)
7362 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
7363 unsigned long bit28
= given
& (1 << 28);
7365 given
&= 0x00ffffff;
7367 given
|= 0xf3000000;
7369 given
|= 0xf2000000;
7371 else if ((given
& 0xff000000) == 0xf9000000)
7372 given
^= 0xf9000000 ^ 0xf4000000;
7373 /* vdup is also a valid neon instruction. */
7374 else if ((given
& 0xff910f5f) != 0xee800b10)
7378 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
7380 if ((given
& insn
->mask
) == insn
->value
)
7382 signed long value_in_comment
= 0;
7383 bfd_boolean is_unpredictable
= FALSE
;
7386 for (c
= insn
->assembler
; *c
; c
++)
7393 func (stream
, "%%");
7397 if (thumb
&& ifthen_state
)
7398 is_unpredictable
= TRUE
;
7402 if (thumb
&& ifthen_state
)
7403 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
7408 static const unsigned char enc
[16] =
7410 0x4, 0x14, /* st4 0,1 */
7422 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
7423 int rn
= ((given
>> 16) & 0xf);
7424 int rm
= ((given
>> 0) & 0xf);
7425 int align
= ((given
>> 4) & 0x3);
7426 int type
= ((given
>> 8) & 0xf);
7427 int n
= enc
[type
] & 0xf;
7428 int stride
= (enc
[type
] >> 4) + 1;
7433 for (ix
= 0; ix
!= n
; ix
++)
7434 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
7436 func (stream
, "d%d", rd
);
7438 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
7439 func (stream
, "}, [%s", arm_regnames
[rn
]);
7441 func (stream
, " :%d", 32 << align
);
7446 func (stream
, ", %s", arm_regnames
[rm
]);
7452 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
7453 int rn
= ((given
>> 16) & 0xf);
7454 int rm
= ((given
>> 0) & 0xf);
7455 int idx_align
= ((given
>> 4) & 0xf);
7457 int size
= ((given
>> 10) & 0x3);
7458 int idx
= idx_align
>> (size
+ 1);
7459 int length
= ((given
>> 8) & 3) + 1;
7463 if (length
> 1 && size
> 0)
7464 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
7470 int amask
= (1 << size
) - 1;
7471 if ((idx_align
& (1 << size
)) != 0)
7475 if ((idx_align
& amask
) == amask
)
7477 else if ((idx_align
& amask
) != 0)
7484 if (size
== 2 && (idx_align
& 2) != 0)
7486 align
= (idx_align
& 1) ? 16 << size
: 0;
7490 if ((size
== 2 && (idx_align
& 3) != 0)
7491 || (idx_align
& 1) != 0)
7498 if ((idx_align
& 3) == 3)
7500 align
= (idx_align
& 3) * 64;
7503 align
= (idx_align
& 1) ? 32 << size
: 0;
7511 for (i
= 0; i
< length
; i
++)
7512 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
7513 rd
+ i
* stride
, idx
);
7514 func (stream
, "}, [%s", arm_regnames
[rn
]);
7516 func (stream
, " :%d", align
);
7521 func (stream
, ", %s", arm_regnames
[rm
]);
7527 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
7528 int rn
= ((given
>> 16) & 0xf);
7529 int rm
= ((given
>> 0) & 0xf);
7530 int align
= ((given
>> 4) & 0x1);
7531 int size
= ((given
>> 6) & 0x3);
7532 int type
= ((given
>> 8) & 0x3);
7534 int stride
= ((given
>> 5) & 0x1);
7537 if (stride
&& (n
== 1))
7544 for (ix
= 0; ix
!= n
; ix
++)
7545 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
7547 func (stream
, "d%d[]", rd
);
7549 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
7550 func (stream
, "}, [%s", arm_regnames
[rn
]);
7553 align
= (8 * (type
+ 1)) << size
;
7555 align
= (size
> 1) ? align
>> 1 : align
;
7556 if (type
== 2 || (type
== 0 && !size
))
7557 func (stream
, " :<bad align %d>", align
);
7559 func (stream
, " :%d", align
);
7565 func (stream
, ", %s", arm_regnames
[rm
]);
7571 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
7572 int size
= (given
>> 20) & 3;
7573 int reg
= raw_reg
& ((4 << size
) - 1);
7574 int ix
= raw_reg
>> size
>> 2;
7576 func (stream
, "d%d[%d]", reg
, ix
);
7581 /* Neon encoded constant for mov, mvn, vorr, vbic. */
7584 int cmode
= (given
>> 8) & 0xf;
7585 int op
= (given
>> 5) & 0x1;
7586 unsigned long value
= 0, hival
= 0;
7591 bits
|= ((given
>> 24) & 1) << 7;
7592 bits
|= ((given
>> 16) & 7) << 4;
7593 bits
|= ((given
>> 0) & 15) << 0;
7597 shift
= (cmode
>> 1) & 3;
7598 value
= (unsigned long) bits
<< (8 * shift
);
7601 else if (cmode
< 12)
7603 shift
= (cmode
>> 1) & 1;
7604 value
= (unsigned long) bits
<< (8 * shift
);
7607 else if (cmode
< 14)
7609 shift
= (cmode
& 1) + 1;
7610 value
= (unsigned long) bits
<< (8 * shift
);
7611 value
|= (1ul << (8 * shift
)) - 1;
7614 else if (cmode
== 14)
7618 /* Bit replication into bytes. */
7624 for (ix
= 7; ix
>= 0; ix
--)
7626 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
7628 value
= (value
<< 8) | mask
;
7630 hival
= (hival
<< 8) | mask
;
7636 /* Byte replication. */
7637 value
= (unsigned long) bits
;
7643 /* Floating point encoding. */
7646 value
= (unsigned long) (bits
& 0x7f) << 19;
7647 value
|= (unsigned long) (bits
& 0x80) << 24;
7648 tmp
= bits
& 0x40 ? 0x3c : 0x40;
7649 value
|= (unsigned long) tmp
<< 24;
7655 func (stream
, "<illegal constant %.8x:%x:%x>",
7663 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
7667 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
7673 unsigned char valbytes
[4];
7676 /* Do this a byte at a time so we don't have to
7677 worry about the host's endianness. */
7678 valbytes
[0] = value
& 0xff;
7679 valbytes
[1] = (value
>> 8) & 0xff;
7680 valbytes
[2] = (value
>> 16) & 0xff;
7681 valbytes
[3] = (value
>> 24) & 0xff;
7683 floatformat_to_double
7684 (& floatformat_ieee_single_little
, valbytes
,
7687 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
7691 func (stream
, "#%ld\t; 0x%.8lx",
7692 (long) (((value
& 0x80000000L
) != 0)
7693 ? value
| ~0xffffffffL
: value
),
7698 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
7709 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
7710 int num
= (given
>> 8) & 0x3;
7713 func (stream
, "{d%d}", regno
);
7714 else if (num
+ regno
>= 32)
7715 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
7717 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
7722 case '0': case '1': case '2': case '3': case '4':
7723 case '5': case '6': case '7': case '8': case '9':
7726 unsigned long value
;
7728 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
7733 func (stream
, "%s", arm_regnames
[value
]);
7736 func (stream
, "%ld", value
);
7737 value_in_comment
= value
;
7740 func (stream
, "%ld", (1ul << width
) - value
);
7746 /* Various width encodings. */
7748 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
7753 if (*c
>= '0' && *c
<= '9')
7755 else if (*c
>= 'a' && *c
<= 'f')
7756 limit
= *c
- 'a' + 10;
7762 if (value
< low
|| value
> high
)
7763 func (stream
, "<illegal width %d>", base
<< value
);
7765 func (stream
, "%d", base
<< value
);
7769 if (given
& (1 << 6))
7773 func (stream
, "d%ld", value
);
7778 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
7780 func (stream
, "q%ld", value
>> 1);
7786 func (stream
, "%c", *c
);
7790 if (value
== ((1ul << width
) - 1))
7791 func (stream
, "%c", *c
);
7794 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
7808 func (stream
, "%c", *c
);
7811 if (value_in_comment
> 32 || value_in_comment
< -16)
7812 func (stream
, "\t; 0x%lx", value_in_comment
);
7814 if (is_unpredictable
)
7815 func (stream
, UNPREDICTABLE_INSTRUCTION
);
7823 /* Print one mve instruction on INFO->STREAM.
7824 Return TRUE if the instuction matched, FALSE if this is not a
7825 recognised mve instruction. */
7828 print_insn_mve (struct disassemble_info
*info
, long given
)
7830 const struct mopcode32
*insn
;
7831 void *stream
= info
->stream
;
7832 fprintf_ftype func
= info
->fprintf_func
;
7834 for (insn
= mve_opcodes
; insn
->assembler
; insn
++)
7836 if (((given
& insn
->mask
) == insn
->value
)
7837 && !is_mve_encoding_conflict (given
, insn
->mve_op
))
7839 signed long value_in_comment
= 0;
7840 bfd_boolean is_unpredictable
= FALSE
;
7841 bfd_boolean is_undefined
= FALSE
;
7843 enum mve_unpredictable unpredictable_cond
= UNPRED_NONE
;
7844 enum mve_undefined undefined_cond
= UNDEF_NONE
;
7846 /* Most vector mve instruction are illegal in a it block.
7847 There are a few exceptions; check for them. */
7848 if (ifthen_state
&& !is_mve_okay_in_it (insn
->mve_op
))
7850 is_unpredictable
= TRUE
;
7851 unpredictable_cond
= UNPRED_IT_BLOCK
;
7853 else if (is_mve_unpredictable (given
, insn
->mve_op
,
7854 &unpredictable_cond
))
7855 is_unpredictable
= TRUE
;
7857 if (is_mve_undefined (given
, insn
->mve_op
, &undefined_cond
))
7858 is_undefined
= TRUE
;
7860 for (c
= insn
->assembler
; *c
; c
++)
7867 func (stream
, "%%");
7871 /* Don't print anything for '+' as it is implied. */
7872 if (arm_decode_field (given
, 23, 23) == 0)
7878 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
7882 print_mve_vld_str_addr (info
, given
, insn
->mve_op
);
7887 long mve_mask
= mve_extract_pred_mask (given
);
7888 func (stream
, "%s", mve_predicatenames
[mve_mask
]);
7893 print_vec_condition (info
, given
, insn
->mve_op
);
7897 if (arm_decode_field (given
, 0, 0) == 1)
7900 = arm_decode_field (given
, 4, 4)
7901 | (arm_decode_field (given
, 6, 6) << 1);
7903 func (stream
, ", uxtw #%lu", size
);
7908 print_mve_rounding_mode (info
, given
, insn
->mve_op
);
7912 print_mve_vcvt_size (info
, given
, insn
->mve_op
);
7917 unsigned long op1
= arm_decode_field (given
, 21, 22);
7919 if ((insn
->mve_op
== MVE_VMOV_VEC_LANE_TO_GP
))
7921 /* Check for signed. */
7922 if (arm_decode_field (given
, 23, 23) == 0)
7924 /* We don't print 's' for S32. */
7925 if ((arm_decode_field (given
, 5, 6) == 0)
7926 && ((op1
== 0) || (op1
== 1)))
7936 if (arm_decode_field (given
, 28, 28) == 0)
7945 print_instruction_predicate (info
);
7949 if (arm_decode_field (given
, 21, 21) == 1)
7954 print_mve_register_blocks (info
, given
, insn
->mve_op
);
7958 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
7960 print_simd_imm8 (info
, given
, 28, insn
);
7964 print_mve_vmov_index (info
, given
);
7968 if (arm_decode_field (given
, 12, 12) == 0)
7975 if (arm_decode_field (given
, 12, 12) == 1)
7979 case '0': case '1': case '2': case '3': case '4':
7980 case '5': case '6': case '7': case '8': case '9':
7983 unsigned long value
;
7985 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
7991 is_unpredictable
= TRUE
;
7992 else if (value
== 15)
7993 func (stream
, "zr");
7995 func (stream
, "%s", arm_regnames
[value
]);
7998 print_mve_size (info
,
8008 unsigned int odd_reg
= (value
<< 1) | 1;
8009 func (stream
, "%s", arm_regnames
[odd_reg
]);
8015 = arm_decode_field (given
, 0, 6);
8016 unsigned long mod_imm
= imm
;
8018 switch (insn
->mve_op
)
8020 case MVE_VLDRW_GATHER_T5
:
8021 case MVE_VSTRW_SCATTER_T5
:
8022 mod_imm
= mod_imm
<< 2;
8024 case MVE_VSTRD_SCATTER_T6
:
8025 case MVE_VLDRD_GATHER_T6
:
8026 mod_imm
= mod_imm
<< 3;
8033 func (stream
, "%lu", mod_imm
);
8037 func (stream
, "%lu", 64 - value
);
8041 unsigned int even_reg
= value
<< 1;
8042 func (stream
, "%s", arm_regnames
[even_reg
]);
8065 func (stream
, "%s", arm_regnames
[value
]);
8068 func (stream
, "%ld", value
);
8069 value_in_comment
= value
;
8072 func (stream
, "s%ld", value
);
8076 func (stream
, "<illegal reg q%ld.5>", value
);
8078 func (stream
, "q%ld", value
);
8081 func (stream
, "0x%08lx", value
);
8093 func (stream
, "%c", *c
);
8096 if (value_in_comment
> 32 || value_in_comment
< -16)
8097 func (stream
, "\t; 0x%lx", value_in_comment
);
8099 if (is_unpredictable
)
8100 print_mve_unpredictable (info
, unpredictable_cond
);
8103 print_mve_undefined (info
, undefined_cond
);
8105 if ((vpt_block_state
.in_vpt_block
== FALSE
)
8107 && (is_vpt_instruction (given
) == TRUE
))
8108 mark_inside_vpt_block (given
);
8109 else if (vpt_block_state
.in_vpt_block
== TRUE
)
8110 update_vpt_block_state ();
8119 /* Return the name of a v7A special register. */
8122 banked_regname (unsigned reg
)
8126 case 15: return "CPSR";
8127 case 32: return "R8_usr";
8128 case 33: return "R9_usr";
8129 case 34: return "R10_usr";
8130 case 35: return "R11_usr";
8131 case 36: return "R12_usr";
8132 case 37: return "SP_usr";
8133 case 38: return "LR_usr";
8134 case 40: return "R8_fiq";
8135 case 41: return "R9_fiq";
8136 case 42: return "R10_fiq";
8137 case 43: return "R11_fiq";
8138 case 44: return "R12_fiq";
8139 case 45: return "SP_fiq";
8140 case 46: return "LR_fiq";
8141 case 48: return "LR_irq";
8142 case 49: return "SP_irq";
8143 case 50: return "LR_svc";
8144 case 51: return "SP_svc";
8145 case 52: return "LR_abt";
8146 case 53: return "SP_abt";
8147 case 54: return "LR_und";
8148 case 55: return "SP_und";
8149 case 60: return "LR_mon";
8150 case 61: return "SP_mon";
8151 case 62: return "ELR_hyp";
8152 case 63: return "SP_hyp";
8153 case 79: return "SPSR";
8154 case 110: return "SPSR_fiq";
8155 case 112: return "SPSR_irq";
8156 case 114: return "SPSR_svc";
8157 case 116: return "SPSR_abt";
8158 case 118: return "SPSR_und";
8159 case 124: return "SPSR_mon";
8160 case 126: return "SPSR_hyp";
8161 default: return NULL
;
8165 /* Return the name of the DMB/DSB option. */
8167 data_barrier_option (unsigned option
)
8169 switch (option
& 0xf)
8171 case 0xf: return "sy";
8172 case 0xe: return "st";
8173 case 0xd: return "ld";
8174 case 0xb: return "ish";
8175 case 0xa: return "ishst";
8176 case 0x9: return "ishld";
8177 case 0x7: return "un";
8178 case 0x6: return "unst";
8179 case 0x5: return "nshld";
8180 case 0x3: return "osh";
8181 case 0x2: return "oshst";
8182 case 0x1: return "oshld";
8183 default: return NULL
;
8187 /* Print one ARM instruction from PC on INFO->STREAM. */
8190 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8192 const struct opcode32
*insn
;
8193 void *stream
= info
->stream
;
8194 fprintf_ftype func
= info
->fprintf_func
;
8195 struct arm_private_data
*private_data
= info
->private_data
;
8197 if (print_insn_coprocessor (pc
, info
, given
, FALSE
))
8200 if (print_insn_neon (info
, given
, FALSE
))
8203 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
8205 if ((given
& insn
->mask
) != insn
->value
)
8208 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, private_data
->features
))
8211 /* Special case: an instruction with all bits set in the condition field
8212 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
8213 or by the catchall at the end of the table. */
8214 if ((given
& 0xF0000000) != 0xF0000000
8215 || (insn
->mask
& 0xF0000000) == 0xF0000000
8216 || (insn
->mask
== 0 && insn
->value
== 0))
8218 unsigned long u_reg
= 16;
8219 unsigned long U_reg
= 16;
8220 bfd_boolean is_unpredictable
= FALSE
;
8221 signed long value_in_comment
= 0;
8224 for (c
= insn
->assembler
; *c
; c
++)
8228 bfd_boolean allow_unpredictable
= FALSE
;
8233 func (stream
, "%%");
8237 value_in_comment
= print_arm_address (pc
, info
, given
);
8241 /* Set P address bit and use normal address
8242 printing routine. */
8243 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
8247 allow_unpredictable
= TRUE
;
8250 if ((given
& 0x004f0000) == 0x004f0000)
8252 /* PC relative with immediate offset. */
8253 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
8257 /* Elide positive zero offset. */
8258 if (offset
|| NEGATIVE_BIT_SET
)
8259 func (stream
, "[pc, #%s%d]\t; ",
8260 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8262 func (stream
, "[pc]\t; ");
8263 if (NEGATIVE_BIT_SET
)
8265 info
->print_address_func (offset
+ pc
+ 8, info
);
8269 /* Always show the offset. */
8270 func (stream
, "[pc], #%s%d",
8271 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8272 if (! allow_unpredictable
)
8273 is_unpredictable
= TRUE
;
8278 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
8280 func (stream
, "[%s",
8281 arm_regnames
[(given
>> 16) & 0xf]);
8285 if (IMMEDIATE_BIT_SET
)
8287 /* Elide offset for non-writeback
8289 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
8291 func (stream
, ", #%s%d",
8292 NEGATIVE_BIT_SET
? "-" : "", offset
);
8294 if (NEGATIVE_BIT_SET
)
8297 value_in_comment
= offset
;
8301 /* Register Offset or Register Pre-Indexed. */
8302 func (stream
, ", %s%s",
8303 NEGATIVE_BIT_SET
? "-" : "",
8304 arm_regnames
[given
& 0xf]);
8306 /* Writing back to the register that is the source/
8307 destination of the load/store is unpredictable. */
8308 if (! allow_unpredictable
8309 && WRITEBACK_BIT_SET
8310 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
8311 is_unpredictable
= TRUE
;
8314 func (stream
, "]%s",
8315 WRITEBACK_BIT_SET
? "!" : "");
8319 if (IMMEDIATE_BIT_SET
)
8321 /* Immediate Post-indexed. */
8322 /* PR 10924: Offset must be printed, even if it is zero. */
8323 func (stream
, "], #%s%d",
8324 NEGATIVE_BIT_SET
? "-" : "", offset
);
8325 if (NEGATIVE_BIT_SET
)
8327 value_in_comment
= offset
;
8331 /* Register Post-indexed. */
8332 func (stream
, "], %s%s",
8333 NEGATIVE_BIT_SET
? "-" : "",
8334 arm_regnames
[given
& 0xf]);
8336 /* Writing back to the register that is the source/
8337 destination of the load/store is unpredictable. */
8338 if (! allow_unpredictable
8339 && (given
& 0xf) == ((given
>> 12) & 0xf))
8340 is_unpredictable
= TRUE
;
8343 if (! allow_unpredictable
)
8345 /* Writeback is automatically implied by post- addressing.
8346 Setting the W bit is unnecessary and ARM specify it as
8347 being unpredictable. */
8348 if (WRITEBACK_BIT_SET
8349 /* Specifying the PC register as the post-indexed
8350 registers is also unpredictable. */
8351 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
8352 is_unpredictable
= TRUE
;
8360 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
8361 info
->print_address_func (disp
* 4 + pc
+ 8, info
);
8366 if (((given
>> 28) & 0xf) != 0xe)
8368 arm_conditional
[(given
>> 28) & 0xf]);
8377 for (reg
= 0; reg
< 16; reg
++)
8378 if ((given
& (1 << reg
)) != 0)
8381 func (stream
, ", ");
8383 func (stream
, "%s", arm_regnames
[reg
]);
8387 is_unpredictable
= TRUE
;
8392 arm_decode_shift (given
, func
, stream
, FALSE
);
8396 if ((given
& 0x02000000) != 0)
8398 unsigned int rotate
= (given
& 0xf00) >> 7;
8399 unsigned int immed
= (given
& 0xff);
8402 a
= (((immed
<< (32 - rotate
))
8403 | (immed
>> rotate
)) & 0xffffffff);
8404 /* If there is another encoding with smaller rotate,
8405 the rotate should be specified directly. */
8406 for (i
= 0; i
< 32; i
+= 2)
8407 if ((a
<< i
| a
>> (32 - i
)) <= 0xff)
8411 func (stream
, "#%d, %d", immed
, rotate
);
8413 func (stream
, "#%d", a
);
8414 value_in_comment
= a
;
8417 arm_decode_shift (given
, func
, stream
, TRUE
);
8421 if ((given
& 0x0000f000) == 0x0000f000)
8423 arm_feature_set arm_ext_v6
=
8424 ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
8426 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
8427 mechanism for setting PSR flag bits. They are
8428 obsolete in V6 onwards. */
8429 if (! ARM_CPU_HAS_FEATURE (private_data
->features
, \
8433 is_unpredictable
= TRUE
;
8438 if ((given
& 0x01200000) == 0x00200000)
8444 int offset
= given
& 0xff;
8446 value_in_comment
= offset
* 4;
8447 if (NEGATIVE_BIT_SET
)
8448 value_in_comment
= - value_in_comment
;
8450 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
8455 func (stream
, ", #%d]%s",
8456 (int) value_in_comment
,
8457 WRITEBACK_BIT_SET
? "!" : "");
8465 if (WRITEBACK_BIT_SET
)
8468 func (stream
, ", #%d", (int) value_in_comment
);
8472 func (stream
, ", {%d}", (int) offset
);
8473 value_in_comment
= offset
;
8480 /* Print ARM V5 BLX(1) address: pc+25 bits. */
8485 if (! NEGATIVE_BIT_SET
)
8486 /* Is signed, hi bits should be ones. */
8487 offset
= (-1) ^ 0x00ffffff;
8489 /* Offset is (SignExtend(offset field)<<2). */
8490 offset
+= given
& 0x00ffffff;
8492 address
= offset
+ pc
+ 8;
8494 if (given
& 0x01000000)
8495 /* H bit allows addressing to 2-byte boundaries. */
8498 info
->print_address_func (address
, info
);
8503 if ((given
& 0x02000200) == 0x200)
8506 unsigned sysm
= (given
& 0x004f0000) >> 16;
8508 sysm
|= (given
& 0x300) >> 4;
8509 name
= banked_regname (sysm
);
8512 func (stream
, "%s", name
);
8514 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
8518 func (stream
, "%cPSR_",
8519 (given
& 0x00400000) ? 'S' : 'C');
8520 if (given
& 0x80000)
8522 if (given
& 0x40000)
8524 if (given
& 0x20000)
8526 if (given
& 0x10000)
8532 if ((given
& 0xf0) == 0x60)
8534 switch (given
& 0xf)
8536 case 0xf: func (stream
, "sy"); break;
8538 func (stream
, "#%d", (int) given
& 0xf);
8544 const char * opt
= data_barrier_option (given
& 0xf);
8546 func (stream
, "%s", opt
);
8548 func (stream
, "#%d", (int) given
& 0xf);
8552 case '0': case '1': case '2': case '3': case '4':
8553 case '5': case '6': case '7': case '8': case '9':
8556 unsigned long value
;
8558 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8564 is_unpredictable
= TRUE
;
8568 /* We want register + 1 when decoding T. */
8574 /* Eat the 'u' character. */
8578 is_unpredictable
= TRUE
;
8583 /* Eat the 'U' character. */
8587 is_unpredictable
= TRUE
;
8590 func (stream
, "%s", arm_regnames
[value
]);
8593 func (stream
, "%ld", value
);
8594 value_in_comment
= value
;
8597 func (stream
, "%ld", value
* 8);
8598 value_in_comment
= value
* 8;
8601 func (stream
, "%ld", value
+ 1);
8602 value_in_comment
= value
+ 1;
8605 func (stream
, "0x%08lx", value
);
8607 /* Some SWI instructions have special
8609 if ((given
& 0x0fffffff) == 0x0FF00000)
8610 func (stream
, "\t; IMB");
8611 else if ((given
& 0x0fffffff) == 0x0FF00001)
8612 func (stream
, "\t; IMBRange");
8615 func (stream
, "%01lx", value
& 0xf);
8616 value_in_comment
= value
;
8621 func (stream
, "%c", *c
);
8625 if (value
== ((1ul << width
) - 1))
8626 func (stream
, "%c", *c
);
8629 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
8642 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
8643 func (stream
, "%d", imm
);
8644 value_in_comment
= imm
;
8649 /* LSB and WIDTH fields of BFI or BFC. The machine-
8650 language instruction encodes LSB and MSB. */
8652 long msb
= (given
& 0x001f0000) >> 16;
8653 long lsb
= (given
& 0x00000f80) >> 7;
8654 long w
= msb
- lsb
+ 1;
8657 func (stream
, "#%lu, #%lu", lsb
, w
);
8659 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
8664 /* Get the PSR/banked register name. */
8667 unsigned sysm
= (given
& 0x004f0000) >> 16;
8669 sysm
|= (given
& 0x300) >> 4;
8670 name
= banked_regname (sysm
);
8673 func (stream
, "%s", name
);
8675 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
8680 /* 16-bit unsigned immediate from a MOVT or MOVW
8681 instruction, encoded in bits 0:11 and 15:19. */
8683 long hi
= (given
& 0x000f0000) >> 4;
8684 long lo
= (given
& 0x00000fff);
8685 long imm16
= hi
| lo
;
8687 func (stream
, "#%lu", imm16
);
8688 value_in_comment
= imm16
;
8697 func (stream
, "%c", *c
);
8700 if (value_in_comment
> 32 || value_in_comment
< -16)
8701 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
8703 if (is_unpredictable
)
8704 func (stream
, UNPREDICTABLE_INSTRUCTION
);
8709 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
8713 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
8716 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8718 const struct opcode16
*insn
;
8719 void *stream
= info
->stream
;
8720 fprintf_ftype func
= info
->fprintf_func
;
8722 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
8723 if ((given
& insn
->mask
) == insn
->value
)
8725 signed long value_in_comment
= 0;
8726 const char *c
= insn
->assembler
;
8735 func (stream
, "%c", *c
);
8742 func (stream
, "%%");
8747 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
8752 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
8761 ifthen_next_state
= given
& 0xff;
8762 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
8763 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
8764 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
8769 if (ifthen_next_state
)
8770 func (stream
, "\t; unpredictable branch in IT block\n");
8775 func (stream
, "\t; unpredictable <IT:%s>",
8776 arm_conditional
[IFTHEN_COND
]);
8783 reg
= (given
>> 3) & 0x7;
8784 if (given
& (1 << 6))
8787 func (stream
, "%s", arm_regnames
[reg
]);
8796 if (given
& (1 << 7))
8799 func (stream
, "%s", arm_regnames
[reg
]);
8804 if (given
& (1 << 8))
8808 if (*c
== 'O' && (given
& (1 << 8)))
8818 /* It would be nice if we could spot
8819 ranges, and generate the rS-rE format: */
8820 for (reg
= 0; (reg
< 8); reg
++)
8821 if ((given
& (1 << reg
)) != 0)
8824 func (stream
, ", ");
8826 func (stream
, "%s", arm_regnames
[reg
]);
8832 func (stream
, ", ");
8834 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
8840 func (stream
, ", ");
8841 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
8849 /* Print writeback indicator for a LDMIA. We are doing a
8850 writeback if the base register is not in the register
8852 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
8857 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
8859 bfd_vma address
= (pc
+ 4
8860 + ((given
& 0x00f8) >> 2)
8861 + ((given
& 0x0200) >> 3));
8862 info
->print_address_func (address
, info
);
8867 /* Right shift immediate -- bits 6..10; 1-31 print
8868 as themselves, 0 prints as 32. */
8870 long imm
= (given
& 0x07c0) >> 6;
8873 func (stream
, "#%ld", imm
);
8877 case '0': case '1': case '2': case '3': case '4':
8878 case '5': case '6': case '7': case '8': case '9':
8880 int bitstart
= *c
++ - '0';
8883 while (*c
>= '0' && *c
<= '9')
8884 bitstart
= (bitstart
* 10) + *c
++ - '0';
8893 while (*c
>= '0' && *c
<= '9')
8894 bitend
= (bitend
* 10) + *c
++ - '0';
8897 reg
= given
>> bitstart
;
8898 reg
&= (2 << (bitend
- bitstart
)) - 1;
8903 func (stream
, "%s", arm_regnames
[reg
]);
8907 func (stream
, "%ld", (long) reg
);
8908 value_in_comment
= reg
;
8912 func (stream
, "%ld", (long) (reg
<< 1));
8913 value_in_comment
= reg
<< 1;
8917 func (stream
, "%ld", (long) (reg
<< 2));
8918 value_in_comment
= reg
<< 2;
8922 /* PC-relative address -- the bottom two
8923 bits of the address are dropped
8924 before the calculation. */
8925 info
->print_address_func
8926 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
8927 value_in_comment
= 0;
8931 func (stream
, "0x%04lx", (long) reg
);
8935 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
8936 info
->print_address_func (reg
* 2 + pc
+ 4, info
);
8937 value_in_comment
= 0;
8941 func (stream
, "%s", arm_conditional
[reg
]);
8952 if ((given
& (1 << bitstart
)) != 0)
8953 func (stream
, "%c", *c
);
8958 if ((given
& (1 << bitstart
)) != 0)
8959 func (stream
, "%c", *c
++);
8961 func (stream
, "%c", *++c
);
8975 if (value_in_comment
> 32 || value_in_comment
< -16)
8976 func (stream
, "\t; 0x%lx", value_in_comment
);
8981 func (stream
, UNKNOWN_INSTRUCTION_16BIT
, (unsigned)given
);
8985 /* Return the name of an V7M special register. */
8988 psr_name (int regno
)
8992 case 0x0: return "APSR";
8993 case 0x1: return "IAPSR";
8994 case 0x2: return "EAPSR";
8995 case 0x3: return "PSR";
8996 case 0x5: return "IPSR";
8997 case 0x6: return "EPSR";
8998 case 0x7: return "IEPSR";
8999 case 0x8: return "MSP";
9000 case 0x9: return "PSP";
9001 case 0xa: return "MSPLIM";
9002 case 0xb: return "PSPLIM";
9003 case 0x10: return "PRIMASK";
9004 case 0x11: return "BASEPRI";
9005 case 0x12: return "BASEPRI_MAX";
9006 case 0x13: return "FAULTMASK";
9007 case 0x14: return "CONTROL";
9008 case 0x88: return "MSP_NS";
9009 case 0x89: return "PSP_NS";
9010 case 0x8a: return "MSPLIM_NS";
9011 case 0x8b: return "PSPLIM_NS";
9012 case 0x90: return "PRIMASK_NS";
9013 case 0x91: return "BASEPRI_NS";
9014 case 0x93: return "FAULTMASK_NS";
9015 case 0x94: return "CONTROL_NS";
9016 case 0x98: return "SP_NS";
9017 default: return "<unknown>";
9021 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
9024 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
9026 const struct opcode32
*insn
;
9027 void *stream
= info
->stream
;
9028 fprintf_ftype func
= info
->fprintf_func
;
9029 bfd_boolean is_mve
= is_mve_architecture (info
);
9031 if (print_insn_coprocessor (pc
, info
, given
, TRUE
))
9034 if ((is_mve
== FALSE
) && print_insn_neon (info
, given
, TRUE
))
9037 if (is_mve
&& print_insn_mve (info
, given
))
9040 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
9041 if ((given
& insn
->mask
) == insn
->value
)
9043 bfd_boolean is_clrm
= FALSE
;
9044 bfd_boolean is_unpredictable
= FALSE
;
9045 signed long value_in_comment
= 0;
9046 const char *c
= insn
->assembler
;
9052 func (stream
, "%c", *c
);
9059 func (stream
, "%%");
9064 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
9068 if (ifthen_next_state
)
9069 func (stream
, "\t; unpredictable branch in IT block\n");
9074 func (stream
, "\t; unpredictable <IT:%s>",
9075 arm_conditional
[IFTHEN_COND
]);
9080 unsigned int imm12
= 0;
9082 imm12
|= (given
& 0x000000ffu
);
9083 imm12
|= (given
& 0x00007000u
) >> 4;
9084 imm12
|= (given
& 0x04000000u
) >> 15;
9085 func (stream
, "#%u", imm12
);
9086 value_in_comment
= imm12
;
9092 unsigned int bits
= 0, imm
, imm8
, mod
;
9094 bits
|= (given
& 0x000000ffu
);
9095 bits
|= (given
& 0x00007000u
) >> 4;
9096 bits
|= (given
& 0x04000000u
) >> 15;
9097 imm8
= (bits
& 0x0ff);
9098 mod
= (bits
& 0xf00) >> 8;
9101 case 0: imm
= imm8
; break;
9102 case 1: imm
= ((imm8
<< 16) | imm8
); break;
9103 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
9104 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
9106 mod
= (bits
& 0xf80) >> 7;
9107 imm8
= (bits
& 0x07f) | 0x80;
9108 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
9110 func (stream
, "#%u", imm
);
9111 value_in_comment
= imm
;
9117 unsigned int imm
= 0;
9119 imm
|= (given
& 0x000000ffu
);
9120 imm
|= (given
& 0x00007000u
) >> 4;
9121 imm
|= (given
& 0x04000000u
) >> 15;
9122 imm
|= (given
& 0x000f0000u
) >> 4;
9123 func (stream
, "#%u", imm
);
9124 value_in_comment
= imm
;
9130 unsigned int imm
= 0;
9132 imm
|= (given
& 0x000f0000u
) >> 16;
9133 imm
|= (given
& 0x00000ff0u
) >> 0;
9134 imm
|= (given
& 0x0000000fu
) << 12;
9135 func (stream
, "#%u", imm
);
9136 value_in_comment
= imm
;
9142 unsigned int imm
= 0;
9144 imm
|= (given
& 0x000f0000u
) >> 4;
9145 imm
|= (given
& 0x00000fffu
) >> 0;
9146 func (stream
, "#%u", imm
);
9147 value_in_comment
= imm
;
9153 unsigned int imm
= 0;
9155 imm
|= (given
& 0x00000fffu
);
9156 imm
|= (given
& 0x000f0000u
) >> 4;
9157 func (stream
, "#%u", imm
);
9158 value_in_comment
= imm
;
9164 unsigned int reg
= (given
& 0x0000000fu
);
9165 unsigned int stp
= (given
& 0x00000030u
) >> 4;
9166 unsigned int imm
= 0;
9167 imm
|= (given
& 0x000000c0u
) >> 6;
9168 imm
|= (given
& 0x00007000u
) >> 10;
9170 func (stream
, "%s", arm_regnames
[reg
]);
9175 func (stream
, ", lsl #%u", imm
);
9181 func (stream
, ", lsr #%u", imm
);
9187 func (stream
, ", asr #%u", imm
);
9192 func (stream
, ", rrx");
9194 func (stream
, ", ror #%u", imm
);
9201 unsigned int Rn
= (given
& 0x000f0000) >> 16;
9202 unsigned int U
= ! NEGATIVE_BIT_SET
;
9203 unsigned int op
= (given
& 0x00000f00) >> 8;
9204 unsigned int i12
= (given
& 0x00000fff);
9205 unsigned int i8
= (given
& 0x000000ff);
9206 bfd_boolean writeback
= FALSE
, postind
= FALSE
;
9209 func (stream
, "[%s", arm_regnames
[Rn
]);
9210 if (U
) /* 12-bit positive immediate offset. */
9214 value_in_comment
= offset
;
9216 else if (Rn
== 15) /* 12-bit negative immediate offset. */
9217 offset
= - (int) i12
;
9218 else if (op
== 0x0) /* Shifted register offset. */
9220 unsigned int Rm
= (i8
& 0x0f);
9221 unsigned int sh
= (i8
& 0x30) >> 4;
9223 func (stream
, ", %s", arm_regnames
[Rm
]);
9225 func (stream
, ", lsl #%u", sh
);
9231 case 0xE: /* 8-bit positive immediate offset. */
9235 case 0xC: /* 8-bit negative immediate offset. */
9239 case 0xF: /* 8-bit + preindex with wb. */
9244 case 0xD: /* 8-bit - preindex with wb. */
9249 case 0xB: /* 8-bit + postindex. */
9254 case 0x9: /* 8-bit - postindex. */
9260 func (stream
, ", <undefined>]");
9265 func (stream
, "], #%d", (int) offset
);
9269 func (stream
, ", #%d", (int) offset
);
9270 func (stream
, writeback
? "]!" : "]");
9275 func (stream
, "\t; ");
9276 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
9284 unsigned int U
= ! NEGATIVE_BIT_SET
;
9285 unsigned int W
= WRITEBACK_BIT_SET
;
9286 unsigned int Rn
= (given
& 0x000f0000) >> 16;
9287 unsigned int off
= (given
& 0x000000ff);
9289 func (stream
, "[%s", arm_regnames
[Rn
]);
9295 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
9296 value_in_comment
= off
* 4 * (U
? 1 : -1);
9304 func (stream
, "], ");
9307 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
9308 value_in_comment
= off
* 4 * (U
? 1 : -1);
9312 func (stream
, "{%u}", off
);
9313 value_in_comment
= off
;
9321 unsigned int Sbit
= (given
& 0x01000000) >> 24;
9322 unsigned int type
= (given
& 0x00600000) >> 21;
9326 case 0: func (stream
, Sbit
? "sb" : "b"); break;
9327 case 1: func (stream
, Sbit
? "sh" : "h"); break;
9330 func (stream
, "??");
9333 func (stream
, "??");
9348 for (reg
= 0; reg
< 16; reg
++)
9349 if ((given
& (1 << reg
)) != 0)
9352 func (stream
, ", ");
9354 if (is_clrm
&& reg
== 13)
9355 func (stream
, "(invalid: %s)", arm_regnames
[reg
]);
9356 else if (is_clrm
&& reg
== 15)
9357 func (stream
, "%s", "APSR");
9359 func (stream
, "%s", arm_regnames
[reg
]);
9367 unsigned int msb
= (given
& 0x0000001f);
9368 unsigned int lsb
= 0;
9370 lsb
|= (given
& 0x000000c0u
) >> 6;
9371 lsb
|= (given
& 0x00007000u
) >> 10;
9372 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
9378 unsigned int width
= (given
& 0x0000001f) + 1;
9379 unsigned int lsb
= 0;
9381 lsb
|= (given
& 0x000000c0u
) >> 6;
9382 lsb
|= (given
& 0x00007000u
) >> 10;
9383 func (stream
, "#%u, #%u", lsb
, width
);
9389 unsigned int boff
= (((given
& 0x07800000) >> 23) << 1);
9390 func (stream
, "%x", boff
);
9396 unsigned int immA
= (given
& 0x001f0000u
) >> 16;
9397 unsigned int immB
= (given
& 0x000007feu
) >> 1;
9398 unsigned int immC
= (given
& 0x00000800u
) >> 11;
9401 offset
|= immA
<< 12;
9402 offset
|= immB
<< 2;
9403 offset
|= immC
<< 1;
9405 offset
= (offset
& 0x10000) ? offset
- (1 << 17) : offset
;
9407 info
->print_address_func (pc
+ 4 + offset
, info
);
9413 unsigned int immA
= (given
& 0x007f0000u
) >> 16;
9414 unsigned int immB
= (given
& 0x000007feu
) >> 1;
9415 unsigned int immC
= (given
& 0x00000800u
) >> 11;
9418 offset
|= immA
<< 12;
9419 offset
|= immB
<< 2;
9420 offset
|= immC
<< 1;
9422 offset
= (offset
& 0x40000) ? offset
- (1 << 19) : offset
;
9424 info
->print_address_func (pc
+ 4 + offset
, info
);
9430 unsigned int immA
= (given
& 0x00010000u
) >> 16;
9431 unsigned int immB
= (given
& 0x000007feu
) >> 1;
9432 unsigned int immC
= (given
& 0x00000800u
) >> 11;
9435 offset
|= immA
<< 12;
9436 offset
|= immB
<< 2;
9437 offset
|= immC
<< 1;
9439 offset
= (offset
& 0x1000) ? offset
- (1 << 13) : offset
;
9441 info
->print_address_func (pc
+ 4 + offset
, info
);
9443 unsigned int T
= (given
& 0x00020000u
) >> 17;
9444 unsigned int endoffset
= (((given
& 0x07800000) >> 23) << 1);
9445 unsigned int boffset
= (T
== 1) ? 4 : 2;
9446 func (stream
, ", ");
9447 func (stream
, "%x", endoffset
+ boffset
);
9453 unsigned int immh
= (given
& 0x000007feu
) >> 1;
9454 unsigned int imml
= (given
& 0x00000800u
) >> 11;
9460 info
->print_address_func (pc
+ 4 + imm32
, info
);
9466 unsigned int immh
= (given
& 0x000007feu
) >> 1;
9467 unsigned int imml
= (given
& 0x00000800u
) >> 11;
9473 info
->print_address_func (pc
+ 4 - imm32
, info
);
9479 unsigned int S
= (given
& 0x04000000u
) >> 26;
9480 unsigned int J1
= (given
& 0x00002000u
) >> 13;
9481 unsigned int J2
= (given
& 0x00000800u
) >> 11;
9487 offset
|= (given
& 0x003f0000) >> 4;
9488 offset
|= (given
& 0x000007ff) << 1;
9489 offset
-= (1 << 20);
9491 info
->print_address_func (pc
+ 4 + offset
, info
);
9497 unsigned int S
= (given
& 0x04000000u
) >> 26;
9498 unsigned int I1
= (given
& 0x00002000u
) >> 13;
9499 unsigned int I2
= (given
& 0x00000800u
) >> 11;
9503 offset
|= !(I1
^ S
) << 23;
9504 offset
|= !(I2
^ S
) << 22;
9505 offset
|= (given
& 0x03ff0000u
) >> 4;
9506 offset
|= (given
& 0x000007ffu
) << 1;
9507 offset
-= (1 << 24);
9510 /* BLX target addresses are always word aligned. */
9511 if ((given
& 0x00001000u
) == 0)
9514 info
->print_address_func (offset
, info
);
9520 unsigned int shift
= 0;
9522 shift
|= (given
& 0x000000c0u
) >> 6;
9523 shift
|= (given
& 0x00007000u
) >> 10;
9524 if (WRITEBACK_BIT_SET
)
9525 func (stream
, ", asr #%u", shift
);
9527 func (stream
, ", lsl #%u", shift
);
9528 /* else print nothing - lsl #0 */
9534 unsigned int rot
= (given
& 0x00000030) >> 4;
9537 func (stream
, ", ror #%u", rot
* 8);
9542 if ((given
& 0xf0) == 0x60)
9544 switch (given
& 0xf)
9546 case 0xf: func (stream
, "sy"); break;
9548 func (stream
, "#%d", (int) given
& 0xf);
9554 const char * opt
= data_barrier_option (given
& 0xf);
9556 func (stream
, "%s", opt
);
9558 func (stream
, "#%d", (int) given
& 0xf);
9563 if ((given
& 0xff) == 0)
9565 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
9575 else if ((given
& 0x20) == 0x20)
9578 unsigned sysm
= (given
& 0xf00) >> 8;
9580 sysm
|= (given
& 0x30);
9581 sysm
|= (given
& 0x00100000) >> 14;
9582 name
= banked_regname (sysm
);
9585 func (stream
, "%s", name
);
9587 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
9591 func (stream
, "%s", psr_name (given
& 0xff));
9596 if (((given
& 0xff) == 0)
9597 || ((given
& 0x20) == 0x20))
9600 unsigned sm
= (given
& 0xf0000) >> 16;
9602 sm
|= (given
& 0x30);
9603 sm
|= (given
& 0x00100000) >> 14;
9604 name
= banked_regname (sm
);
9607 func (stream
, "%s", name
);
9609 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
9612 func (stream
, "%s", psr_name (given
& 0xff));
9615 case '0': case '1': case '2': case '3': case '4':
9616 case '5': case '6': case '7': case '8': case '9':
9621 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
9626 func (stream
, "%lu", val
);
9627 value_in_comment
= val
;
9631 func (stream
, "%lu", val
+ 1);
9632 value_in_comment
= val
+ 1;
9636 func (stream
, "%lu", val
* 4);
9637 value_in_comment
= val
* 4;
9642 is_unpredictable
= TRUE
;
9646 is_unpredictable
= TRUE
;
9649 func (stream
, "%s", arm_regnames
[val
]);
9653 func (stream
, "%s", arm_conditional
[val
]);
9658 if (val
== ((1ul << width
) - 1))
9659 func (stream
, "%c", *c
);
9665 func (stream
, "%c", *c
);
9669 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
9674 func (stream
, "0x%lx", val
& 0xffffffffUL
);
9684 /* PR binutils/12534
9685 If we have a PC relative offset in an LDRD or STRD
9686 instructions then display the decoded address. */
9687 if (((given
>> 16) & 0xf) == 0xf)
9689 bfd_vma offset
= (given
& 0xff) * 4;
9691 if ((given
& (1 << 23)) == 0)
9693 func (stream
, "\t; ");
9694 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
9703 if (value_in_comment
> 32 || value_in_comment
< -16)
9704 func (stream
, "\t; 0x%lx", value_in_comment
);
9706 if (is_unpredictable
)
9707 func (stream
, UNPREDICTABLE_INSTRUCTION
);
9713 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
9717 /* Print data bytes on INFO->STREAM. */
9720 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
9721 struct disassemble_info
*info
,
9724 switch (info
->bytes_per_chunk
)
9727 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
9730 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
9733 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
9740 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
9741 being displayed in symbol relative addresses.
9743 Also disallow private symbol, with __tagsym$$ prefix,
9744 from ARM RVCT toolchain being displayed. */
9747 arm_symbol_is_valid (asymbol
* sym
,
9748 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
9755 name
= bfd_asymbol_name (sym
);
9757 return (name
&& *name
!= '$' && strncmp (name
, "__tagsym$$", 10));
9760 /* Parse the string of disassembler options. */
9763 parse_arm_disassembler_options (const char *options
)
9767 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
9769 if (CONST_STRNEQ (opt
, "reg-names-"))
9772 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
9773 if (disassembler_options_cmp (opt
, regnames
[i
].name
) == 0)
9775 regname_selected
= i
;
9779 if (i
>= NUM_ARM_OPTIONS
)
9780 /* xgettext: c-format */
9781 opcodes_error_handler (_("unrecognised register name set: %s"),
9784 else if (CONST_STRNEQ (opt
, "force-thumb"))
9786 else if (CONST_STRNEQ (opt
, "no-force-thumb"))
9789 /* xgettext: c-format */
9790 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt
);
9797 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
9798 enum map_type
*map_symbol
);
9800 /* Search back through the insn stream to determine if this instruction is
9801 conditionally executed. */
9804 find_ifthen_state (bfd_vma pc
,
9805 struct disassemble_info
*info
,
9811 /* COUNT is twice the number of instructions seen. It will be odd if we
9812 just crossed an instruction boundary. */
9815 unsigned int seen_it
;
9818 ifthen_address
= pc
;
9825 /* Scan backwards looking for IT instructions, keeping track of where
9826 instruction boundaries are. We don't know if something is actually an
9827 IT instruction until we find a definite instruction boundary. */
9830 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
9832 /* A symbol must be on an instruction boundary, and will not
9833 be within an IT block. */
9834 if (seen_it
&& (count
& 1))
9840 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
9845 insn
= (b
[0]) | (b
[1] << 8);
9847 insn
= (b
[1]) | (b
[0] << 8);
9850 if ((insn
& 0xf800) < 0xe800)
9852 /* Addr + 2 is an instruction boundary. See if this matches
9853 the expected boundary based on the position of the last
9860 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
9862 enum map_type type
= MAP_ARM
;
9863 bfd_boolean found
= mapping_symbol_for_insn (addr
, info
, &type
);
9865 if (!found
|| (found
&& type
== MAP_THUMB
))
9867 /* This could be an IT instruction. */
9869 it_count
= count
>> 1;
9872 if ((insn
& 0xf800) >= 0xe800)
9875 count
= (count
+ 2) | 1;
9876 /* IT blocks contain at most 4 instructions. */
9877 if (count
>= 8 && !seen_it
)
9880 /* We found an IT instruction. */
9881 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
9882 if ((ifthen_state
& 0xf) == 0)
9886 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
9890 is_mapping_symbol (struct disassemble_info
*info
, int n
,
9891 enum map_type
*map_type
)
9895 name
= bfd_asymbol_name (info
->symtab
[n
]);
9896 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
9897 && (name
[2] == 0 || name
[2] == '.'))
9899 *map_type
= ((name
[1] == 'a') ? MAP_ARM
9900 : (name
[1] == 't') ? MAP_THUMB
9908 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
9909 Returns nonzero if *MAP_TYPE was set. */
9912 get_map_sym_type (struct disassemble_info
*info
,
9914 enum map_type
*map_type
)
9916 /* If the symbol is in a different section, ignore it. */
9917 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
9920 return is_mapping_symbol (info
, n
, map_type
);
9923 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
9924 Returns nonzero if *MAP_TYPE was set. */
9927 get_sym_code_type (struct disassemble_info
*info
,
9929 enum map_type
*map_type
)
9931 elf_symbol_type
*es
;
9934 /* If the symbol is in a different section, ignore it. */
9935 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
9938 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
9939 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
9941 /* If the symbol has function type then use that. */
9942 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
9944 if (ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
9945 == ST_BRANCH_TO_THUMB
)
9946 *map_type
= MAP_THUMB
;
9948 *map_type
= MAP_ARM
;
9955 /* Search the mapping symbol state for instruction at pc. This is only
9956 applicable for elf target.
9958 There is an assumption Here, info->private_data contains the correct AND
9959 up-to-date information about current scan process. The information will be
9960 used to speed this search process.
9962 Return TRUE if the mapping state can be determined, and map_symbol
9963 will be updated accordingly. Otherwise, return FALSE. */
9966 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
9967 enum map_type
*map_symbol
)
9969 bfd_vma addr
, section_vma
= 0;
9970 int n
, last_sym
= -1;
9971 bfd_boolean found
= FALSE
;
9972 bfd_boolean can_use_search_opt_p
= FALSE
;
9974 /* Default to DATA. A text section is required by the ABI to contain an
9975 INSN mapping symbol at the start. A data section has no such
9976 requirement, hence if no mapping symbol is found the section must
9977 contain only data. This however isn't very useful if the user has
9978 fully stripped the binaries. If this is the case use the section
9979 attributes to determine the default. If we have no section default to
9980 INSN as well, as we may be disassembling some raw bytes on a baremetal
9981 HEX file or similar. */
9982 enum map_type type
= MAP_DATA
;
9983 if ((info
->section
&& info
->section
->flags
& SEC_CODE
) || !info
->section
)
9985 struct arm_private_data
*private_data
;
9987 if (info
->private_data
== NULL
9988 || bfd_asymbol_flavour (*info
->symtab
) != bfd_target_elf_flavour
)
9991 private_data
= info
->private_data
;
9993 /* First, look for mapping symbols. */
9994 if (info
->symtab_size
!= 0)
9996 if (pc
<= private_data
->last_mapping_addr
)
9997 private_data
->last_mapping_sym
= -1;
9999 /* Start scanning at the start of the function, or wherever
10000 we finished last time. */
10001 n
= info
->symtab_pos
+ 1;
10003 /* If the last stop offset is different from the current one it means we
10004 are disassembling a different glob of bytes. As such the optimization
10005 would not be safe and we should start over. */
10006 can_use_search_opt_p
10007 = private_data
->last_mapping_sym
>= 0
10008 && info
->stop_offset
== private_data
->last_stop_offset
;
10010 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
10011 n
= private_data
->last_mapping_sym
;
10013 /* Look down while we haven't passed the location being disassembled.
10014 The reason for this is that there's no defined order between a symbol
10015 and an mapping symbol that may be at the same address. We may have to
10016 look at least one position ahead. */
10017 for (; n
< info
->symtab_size
; n
++)
10019 addr
= bfd_asymbol_value (info
->symtab
[n
]);
10022 if (get_map_sym_type (info
, n
, &type
))
10031 n
= info
->symtab_pos
;
10032 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
10033 n
= private_data
->last_mapping_sym
;
10035 /* No mapping symbol found at this address. Look backwards
10036 for a preceeding one, but don't go pass the section start
10037 otherwise a data section with no mapping symbol can pick up
10038 a text mapping symbol of a preceeding section. The documentation
10039 says section can be NULL, in which case we will seek up all the
10042 section_vma
= info
->section
->vma
;
10044 for (; n
>= 0; n
--)
10046 addr
= bfd_asymbol_value (info
->symtab
[n
]);
10047 if (addr
< section_vma
)
10050 if (get_map_sym_type (info
, n
, &type
))
10060 /* If no mapping symbol was found, try looking up without a mapping
10061 symbol. This is done by walking up from the current PC to the nearest
10062 symbol. We don't actually have to loop here since symtab_pos will
10063 contain the nearest symbol already. */
10066 n
= info
->symtab_pos
;
10067 if (n
>= 0 && get_sym_code_type (info
, n
, &type
))
10074 private_data
->last_mapping_sym
= last_sym
;
10075 private_data
->last_type
= type
;
10076 private_data
->last_stop_offset
= info
->stop_offset
;
10078 *map_symbol
= type
;
10082 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
10083 of the supplied arm_feature_set structure with bitmasks indicating
10084 the supported base architectures and coprocessor extensions.
10086 FIXME: This could more efficiently implemented as a constant array,
10087 although it would also be less robust. */
10090 select_arm_features (unsigned long mach
,
10091 arm_feature_set
* features
)
10093 arm_feature_set arch_fset
;
10094 const arm_feature_set fpu_any
= FPU_ANY
;
10096 #undef ARM_SET_FEATURES
10097 #define ARM_SET_FEATURES(FSET) \
10099 const arm_feature_set fset = FSET; \
10100 arch_fset = fset; \
10103 /* When several architecture versions share the same bfd_mach_arm_XXX value
10104 the most featureful is chosen. */
10107 case bfd_mach_arm_2
: ARM_SET_FEATURES (ARM_ARCH_V2
); break;
10108 case bfd_mach_arm_2a
: ARM_SET_FEATURES (ARM_ARCH_V2S
); break;
10109 case bfd_mach_arm_3
: ARM_SET_FEATURES (ARM_ARCH_V3
); break;
10110 case bfd_mach_arm_3M
: ARM_SET_FEATURES (ARM_ARCH_V3M
); break;
10111 case bfd_mach_arm_4
: ARM_SET_FEATURES (ARM_ARCH_V4
); break;
10112 case bfd_mach_arm_4T
: ARM_SET_FEATURES (ARM_ARCH_V4T
); break;
10113 case bfd_mach_arm_5
: ARM_SET_FEATURES (ARM_ARCH_V5
); break;
10114 case bfd_mach_arm_5T
: ARM_SET_FEATURES (ARM_ARCH_V5T
); break;
10115 case bfd_mach_arm_5TE
: ARM_SET_FEATURES (ARM_ARCH_V5TE
); break;
10116 case bfd_mach_arm_XScale
: ARM_SET_FEATURES (ARM_ARCH_XSCALE
); break;
10117 case bfd_mach_arm_ep9312
:
10118 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T
,
10119 ARM_CEXT_MAVERICK
| FPU_MAVERICK
));
10121 case bfd_mach_arm_iWMMXt
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT
); break;
10122 case bfd_mach_arm_iWMMXt2
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2
); break;
10123 case bfd_mach_arm_5TEJ
: ARM_SET_FEATURES (ARM_ARCH_V5TEJ
); break;
10124 case bfd_mach_arm_6
: ARM_SET_FEATURES (ARM_ARCH_V6
); break;
10125 case bfd_mach_arm_6KZ
: ARM_SET_FEATURES (ARM_ARCH_V6KZ
); break;
10126 case bfd_mach_arm_6T2
: ARM_SET_FEATURES (ARM_ARCH_V6KZT2
); break;
10127 case bfd_mach_arm_6K
: ARM_SET_FEATURES (ARM_ARCH_V6K
); break;
10128 case bfd_mach_arm_7
: ARM_SET_FEATURES (ARM_ARCH_V7VE
); break;
10129 case bfd_mach_arm_6M
: ARM_SET_FEATURES (ARM_ARCH_V6M
); break;
10130 case bfd_mach_arm_6SM
: ARM_SET_FEATURES (ARM_ARCH_V6SM
); break;
10131 case bfd_mach_arm_7EM
: ARM_SET_FEATURES (ARM_ARCH_V7EM
); break;
10132 case bfd_mach_arm_8
:
10134 /* Add bits for extensions that Armv8.5-A recognizes. */
10135 arm_feature_set armv8_5_ext_fset
10136 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
10137 ARM_SET_FEATURES (ARM_ARCH_V8_5A
);
10138 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, armv8_5_ext_fset
);
10141 case bfd_mach_arm_8R
: ARM_SET_FEATURES (ARM_ARCH_V8R
); break;
10142 case bfd_mach_arm_8M_BASE
: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE
); break;
10143 case bfd_mach_arm_8M_MAIN
: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN
); break;
10144 case bfd_mach_arm_8_1M_MAIN
:
10145 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN
);
10148 /* If the machine type is unknown allow all architecture types and all
10150 case bfd_mach_arm_unknown
: ARM_SET_FEATURES (ARM_FEATURE_ALL
); break;
10154 #undef ARM_SET_FEATURES
10156 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
10157 and thus on bfd_mach_arm_XXX value. Therefore for a given
10158 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
10159 ARM_MERGE_FEATURE_SETS (*features
, arch_fset
, fpu_any
);
10163 /* NOTE: There are no checks in these routines that
10164 the relevant number of data bytes exist. */
10167 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bfd_boolean little
)
10169 unsigned char b
[4];
10172 int is_thumb
= FALSE
;
10173 int is_data
= FALSE
;
10175 unsigned int size
= 4;
10176 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
10177 bfd_boolean found
= FALSE
;
10178 struct arm_private_data
*private_data
;
10180 if (info
->disassembler_options
)
10182 parse_arm_disassembler_options (info
->disassembler_options
);
10184 /* To avoid repeated parsing of these options, we remove them here. */
10185 info
->disassembler_options
= NULL
;
10188 /* PR 10288: Control which instructions will be disassembled. */
10189 if (info
->private_data
== NULL
)
10191 static struct arm_private_data
private;
10193 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
10194 /* If the user did not use the -m command line switch then default to
10195 disassembling all types of ARM instruction.
10197 The info->mach value has to be ignored as this will be based on
10198 the default archictecture for the target and/or hints in the notes
10199 section, but it will never be greater than the current largest arm
10200 machine value (iWMMXt2), which is only equivalent to the V5TE
10201 architecture. ARM architectures have advanced beyond the machine
10202 value encoding, and these newer architectures would be ignored if
10203 the machine value was used.
10205 Ie the -m switch is used to restrict which instructions will be
10206 disassembled. If it is necessary to use the -m switch to tell
10207 objdump that an ARM binary is being disassembled, eg because the
10208 input is a raw binary file, but it is also desired to disassemble
10209 all ARM instructions then use "-marm". This will select the
10210 "unknown" arm architecture which is compatible with any ARM
10212 info
->mach
= bfd_mach_arm_unknown
;
10214 /* Compute the architecture bitmask from the machine number.
10215 Note: This assumes that the machine number will not change
10216 during disassembly.... */
10217 select_arm_features (info
->mach
, & private.features
);
10219 private.last_mapping_sym
= -1;
10220 private.last_mapping_addr
= 0;
10221 private.last_stop_offset
= 0;
10223 info
->private_data
= & private;
10226 private_data
= info
->private_data
;
10228 /* Decide if our code is going to be little-endian, despite what the
10229 function argument might say. */
10230 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
10232 /* For ELF, consult the symbol table to determine what kind of code
10233 or data we have. */
10234 if (info
->symtab_size
!= 0
10235 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
10240 enum map_type type
= MAP_ARM
;
10242 found
= mapping_symbol_for_insn (pc
, info
, &type
);
10243 last_sym
= private_data
->last_mapping_sym
;
10245 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
10246 is_data
= (private_data
->last_type
== MAP_DATA
);
10248 /* Look a little bit ahead to see if we should print out
10249 two or four bytes of data. If there's a symbol,
10250 mapping or otherwise, after two bytes then don't
10254 size
= 4 - (pc
& 3);
10255 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
10257 addr
= bfd_asymbol_value (info
->symtab
[n
]);
10259 && (info
->section
== NULL
10260 || info
->section
== info
->symtab
[n
]->section
))
10262 if (addr
- pc
< size
)
10267 /* If the next symbol is after three bytes, we need to
10268 print only part of the data, so that we can use either
10269 .byte or .short. */
10271 size
= (pc
& 1) ? 1 : 2;
10275 if (info
->symbols
!= NULL
)
10277 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
10279 coff_symbol_type
* cs
;
10281 cs
= coffsymbol (*info
->symbols
);
10282 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
10283 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
10284 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
10285 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
10286 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
10288 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
10291 /* If no mapping symbol has been found then fall back to the type
10292 of the function symbol. */
10293 elf_symbol_type
* es
;
10296 es
= *(elf_symbol_type
**)(info
->symbols
);
10297 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
10300 ((ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
10301 == ST_BRANCH_TO_THUMB
) || type
== STT_ARM_16BIT
);
10303 else if (bfd_asymbol_flavour (*info
->symbols
)
10304 == bfd_target_mach_o_flavour
)
10306 bfd_mach_o_asymbol
*asym
= (bfd_mach_o_asymbol
*)*info
->symbols
;
10308 is_thumb
= (asym
->n_desc
& BFD_MACH_O_N_ARM_THUMB_DEF
);
10316 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
10318 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
10320 info
->bytes_per_line
= 4;
10322 /* PR 10263: Disassemble data if requested to do so by the user. */
10323 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
10327 /* Size was already set above. */
10328 info
->bytes_per_chunk
= size
;
10329 printer
= print_insn_data
;
10331 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
10334 for (i
= size
- 1; i
>= 0; i
--)
10335 given
= b
[i
] | (given
<< 8);
10337 for (i
= 0; i
< (int) size
; i
++)
10338 given
= b
[i
] | (given
<< 8);
10340 else if (!is_thumb
)
10342 /* In ARM mode endianness is a straightforward issue: the instruction
10343 is four bytes long and is either ordered 0123 or 3210. */
10344 printer
= print_insn_arm
;
10345 info
->bytes_per_chunk
= 4;
10348 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
10350 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | (b
[3] << 24);
10352 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | (b
[0] << 24);
10356 /* In Thumb mode we have the additional wrinkle of two
10357 instruction lengths. Fortunately, the bits that determine
10358 the length of the current instruction are always to be found
10359 in the first two bytes. */
10360 printer
= print_insn_thumb16
;
10361 info
->bytes_per_chunk
= 2;
10364 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
10366 given
= (b
[0]) | (b
[1] << 8);
10368 given
= (b
[1]) | (b
[0] << 8);
10372 /* These bit patterns signal a four-byte Thumb
10374 if ((given
& 0xF800) == 0xF800
10375 || (given
& 0xF800) == 0xF000
10376 || (given
& 0xF800) == 0xE800)
10378 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
10380 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
10382 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
10384 printer
= print_insn_thumb32
;
10389 if (ifthen_address
!= pc
)
10390 find_ifthen_state (pc
, info
, little_code
);
10394 if ((ifthen_state
& 0xf) == 0x8)
10395 ifthen_next_state
= 0;
10397 ifthen_next_state
= (ifthen_state
& 0xe0)
10398 | ((ifthen_state
& 0xf) << 1);
10404 info
->memory_error_func (status
, pc
, info
);
10407 if (info
->flags
& INSN_HAS_RELOC
)
10408 /* If the instruction has a reloc associated with it, then
10409 the offset field in the instruction will actually be the
10410 addend for the reloc. (We are using REL type relocs).
10411 In such cases, we can ignore the pc when computing
10412 addresses, since the addend is not currently pc-relative. */
10415 printer (pc
, info
, given
);
10419 ifthen_state
= ifthen_next_state
;
10420 ifthen_address
+= size
;
10426 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
10428 /* Detect BE8-ness and record it in the disassembler info. */
10429 if (info
->flavour
== bfd_target_elf_flavour
10430 && info
->section
!= NULL
10431 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
10432 info
->endian_code
= BFD_ENDIAN_LITTLE
;
10434 return print_insn (pc
, info
, FALSE
);
10438 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
10440 return print_insn (pc
, info
, TRUE
);
10443 const disasm_options_and_args_t
*
10444 disassembler_options_arm (void)
10446 static disasm_options_and_args_t
*opts_and_args
;
10448 if (opts_and_args
== NULL
)
10450 disasm_options_t
*opts
;
10453 opts_and_args
= XNEW (disasm_options_and_args_t
);
10454 opts_and_args
->args
= NULL
;
10456 opts
= &opts_and_args
->options
;
10457 opts
->name
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
10458 opts
->description
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
10460 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
10462 opts
->name
[i
] = regnames
[i
].name
;
10463 if (regnames
[i
].description
!= NULL
)
10464 opts
->description
[i
] = _(regnames
[i
].description
);
10466 opts
->description
[i
] = NULL
;
10468 /* The array we return must be NULL terminated. */
10469 opts
->name
[i
] = NULL
;
10470 opts
->description
[i
] = NULL
;
10473 return opts_and_args
;
10477 print_arm_disassembler_options (FILE *stream
)
10479 unsigned int i
, max_len
= 0;
10480 fprintf (stream
, _("\n\
10481 The following ARM specific disassembler options are supported for use with\n\
10482 the -M switch:\n"));
10484 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
10486 unsigned int len
= strlen (regnames
[i
].name
);
10491 for (i
= 0, max_len
++; i
< NUM_ARM_OPTIONS
; i
++)
10492 fprintf (stream
, " %s%*c %s\n",
10494 (int)(max_len
- strlen (regnames
[i
].name
)), ' ',
10495 _(regnames
[i
].description
));