projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
[Patch][binutils][arm] Create a new generic coprocessor array [3/10]
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23 #include "sysdep.h"
24 #include <assert.h>
25
26 #include "disassemble.h"
27 #include "opcode/arm.h"
28 #include "opintl.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
32
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
35 #include "libcoff.h"
36 #include "bfd.h"
37 #include "elf-bfd.h"
38 #include "elf/internal.h"
39 #include "elf/arm.h"
40 #include "mach-o.h"
41
42 /* FIXME: Belongs in global header. */
43 #ifndef strneq
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45 #endif
46
47 /* Cached mapping symbol state. */
48 enum map_type
49 {
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53 };
54
55 struct arm_private_data
56 {
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
68 bfd_vma last_mapping_addr;
69 };
70
71 enum mve_instructions
72 {
73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
211 MVE_VADC,
212 MVE_VABAV,
213 MVE_VABD_FP,
214 MVE_VABD_VEC,
215 MVE_VABS_FP,
216 MVE_VABS_VEC,
217 MVE_VADD_FP_T1,
218 MVE_VADD_FP_T2,
219 MVE_VADD_VEC_T1,
220 MVE_VADD_VEC_T2,
221 MVE_VSBC,
222 MVE_VSUB_FP_T1,
223 MVE_VSUB_FP_T2,
224 MVE_VSUB_VEC_T1,
225 MVE_VSUB_VEC_T2,
226 MVE_VAND,
227 MVE_VBRSR,
228 MVE_VCLS,
229 MVE_VCLZ,
230 MVE_VCTP,
231 MVE_VMAX,
232 MVE_VMAXA,
233 MVE_VMAXNM_FP,
234 MVE_VMAXNMA_FP,
235 MVE_VMAXNMV_FP,
236 MVE_VMAXNMAV_FP,
237 MVE_VMAXV,
238 MVE_VMAXAV,
239 MVE_VMIN,
240 MVE_VMINA,
241 MVE_VMINNM_FP,
242 MVE_VMINNMA_FP,
243 MVE_VMINNMV_FP,
244 MVE_VMINNMAV_FP,
245 MVE_VMINV,
246 MVE_VMINAV,
247 MVE_VMLA,
248 MVE_VMUL_FP_T1,
249 MVE_VMUL_FP_T2,
250 MVE_VMUL_VEC_T1,
251 MVE_VMUL_VEC_T2,
252 MVE_VMULH,
253 MVE_VRMULH,
254 MVE_VNEG_FP,
255 MVE_VNEG_VEC,
256 MVE_VPNOT,
257 MVE_VPSEL,
258 MVE_VQABS,
259 MVE_VQADD_T1,
260 MVE_VQADD_T2,
261 MVE_VQSUB_T1,
262 MVE_VQSUB_T2,
263 MVE_VQNEG,
264 MVE_VREV16,
265 MVE_VREV32,
266 MVE_VREV64,
267 MVE_LSLL,
268 MVE_LSLLI,
269 MVE_LSRL,
270 MVE_ASRL,
271 MVE_ASRLI,
272 MVE_SQRSHRL,
273 MVE_SQRSHR,
274 MVE_UQRSHL,
275 MVE_UQRSHLL,
276 MVE_UQSHL,
277 MVE_UQSHLL,
278 MVE_URSHRL,
279 MVE_URSHR,
280 MVE_SRSHRL,
281 MVE_SRSHR,
282 MVE_SQSHLL,
283 MVE_SQSHL,
284 MVE_CINC,
285 MVE_CINV,
286 MVE_CNEG,
287 MVE_CSINC,
288 MVE_CSINV,
289 MVE_CSET,
290 MVE_CSETM,
291 MVE_CSNEG,
292 MVE_CSEL,
293 MVE_NONE
294 };
295
296 enum mve_unpredictable
297 {
298 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
299 */
300 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
301 fcB = 1 (vpt). */
302 UNPRED_R13, /* Unpredictable because r13 (sp) or
303 r15 (sp) used. */
304 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
305 UNPRED_Q_GT_4, /* Unpredictable because
306 vec reg start > 4 (vld4/st4). */
307 UNPRED_Q_GT_6, /* Unpredictable because
308 vec reg start > 6 (vld2/st2). */
309 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
310 and WB bit = 1. */
311 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
312 equal. */
313 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
314 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
315 same. */
316 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
317 size = 1. */
318 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
319 size = 2. */
320 UNPRED_NONE /* No unpredictable behavior. */
321 };
322
323 enum mve_undefined
324 {
325 UNDEF_SIZE, /* undefined size. */
326 UNDEF_SIZE_0, /* undefined because size == 0. */
327 UNDEF_SIZE_2, /* undefined because size == 2. */
328 UNDEF_SIZE_3, /* undefined because size == 3. */
329 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
330 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
331 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
332 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
333 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
334 size == 0. */
335 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
336 size == 1. */
337 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
338 UNDEF_VCVT_IMM6, /* imm6 < 32. */
339 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
340 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
341 op1 == (0 or 1). */
342 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
343 op2 == 0 and op1 == (0 or 1). */
344 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
345 in {0xx1, x0x1}. */
346 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
347 UNDEF_NONE /* no undefined behavior. */
348 };
349
350 struct opcode32
351 {
352 arm_feature_set arch; /* Architecture defining this insn. */
353 unsigned long value; /* If arch is 0 then value is a sentinel. */
354 unsigned long mask; /* Recognise insn if (op & mask) == value. */
355 const char * assembler; /* How to disassemble this insn. */
356 };
357
358 /* MVE opcodes. */
359
360 struct mopcode32
361 {
362 arm_feature_set arch; /* Architecture defining this insn. */
363 enum mve_instructions mve_op; /* Specific mve instruction for faster
364 decoding. */
365 unsigned long value; /* If arch is 0 then value is a sentinel. */
366 unsigned long mask; /* Recognise insn if (op & mask) == value. */
367 const char * assembler; /* How to disassemble this insn. */
368 };
369
370 enum isa {
371 ANY,
372 T32,
373 ARM
374 };
375
376
377 /* Shared (between Arm and Thumb mode) opcode. */
378 struct sopcode32
379 {
380 enum isa isa; /* Execution mode instruction availability. */
381 arm_feature_set arch; /* Architecture defining this insn. */
382 unsigned long value; /* If arch is 0 then value is a sentinel. */
383 unsigned long mask; /* Recognise insn if (op & mask) == value. */
384 const char * assembler; /* How to disassemble this insn. */
385 };
386
387 struct opcode16
388 {
389 arm_feature_set arch; /* Architecture defining this insn. */
390 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
391 const char *assembler; /* How to disassemble this insn. */
392 };
393
394 /* print_insn_coprocessor recognizes the following format control codes:
395
396 %% %
397
398 %c print condition code (always bits 28-31 in ARM mode)
399 %q print shifter argument
400 %u print condition code (unconditional in ARM mode,
401 UNPREDICTABLE if not AL in Thumb)
402 %A print address for ldc/stc/ldf/stf instruction
403 %B print vstm/vldm register list
404 %C print vscclrm register list
405 %I print cirrus signed shift immediate: bits 0..3|4..6
406 %J print register for VLDR instruction
407 %K print address for VLDR instruction
408 %F print the COUNT field of a LFM/SFM instruction.
409 %P print floating point precision in arithmetic insn
410 %Q print floating point precision in ldf/stf insn
411 %R print floating point rounding mode
412
413 %<bitfield>c print as a condition code (for vsel)
414 %<bitfield>r print as an ARM register
415 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
416 %<bitfield>ru as %<>r but each u register must be unique.
417 %<bitfield>d print the bitfield in decimal
418 %<bitfield>k print immediate for VFPv3 conversion instruction
419 %<bitfield>x print the bitfield in hex
420 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
421 %<bitfield>f print a floating point constant if >7 else a
422 floating point register
423 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
424 %<bitfield>g print as an iWMMXt 64-bit register
425 %<bitfield>G print as an iWMMXt general purpose or control register
426 %<bitfield>D print as a NEON D register
427 %<bitfield>Q print as a NEON Q register
428 %<bitfield>V print as a NEON D or Q register
429 %<bitfield>E print a quarter-float immediate value
430
431 %y<code> print a single precision VFP reg.
432 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
433 %z<code> print a double precision VFP reg
434 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
435
436 %<bitfield>'c print specified char iff bitfield is all ones
437 %<bitfield>`c print specified char iff bitfield is all zeroes
438 %<bitfield>?ab... select from array of values in big endian order
439
440 %L print as an iWMMXt N/M width field.
441 %Z print the Immediate of a WSHUFH instruction.
442 %l like 'A' except use byte offsets for 'B' & 'H'
443 versions.
444 %i print 5-bit immediate in bits 8,3..0
445 (print "32" when 0)
446 %r print register offset address for wldt/wstr instruction. */
447
448 enum opcode_sentinel_enum
449 {
450 SENTINEL_IWMMXT_START = 1,
451 SENTINEL_IWMMXT_END,
452 SENTINEL_GENERIC_START
453 } opcode_sentinels;
454
455 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
456 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
457 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
458 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
459
460 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
461
462 static const struct sopcode32 coprocessor_opcodes[] =
463 {
464 /* XScale instructions. */
465 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
466 0x0e200010, 0x0fff0ff0,
467 "mia%c\tacc0, %0-3r, %12-15r"},
468 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
469 0x0e280010, 0x0fff0ff0,
470 "miaph%c\tacc0, %0-3r, %12-15r"},
471 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
472 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
473 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
474 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
475 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
476 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
477
478 /* Intel Wireless MMX technology instructions. */
479 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
480 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
481 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
482 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
483 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
484 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
485 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
486 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
487 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
488 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
489 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
490 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
491 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
492 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
493 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
494 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
495 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
496 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
497 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
498 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
499 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
500 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
501 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
502 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
503 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
504 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
505 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
506 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
507 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
508 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
509 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
510 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
511 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
512 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
513 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
514 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
515 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
516 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
517 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
518 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
519 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
520 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
521 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
522 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
523 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
524 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
525 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
526 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
527 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
528 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
529 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
530 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
531 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
532 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
533 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
534 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
535 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
536 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
537 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
538 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
539 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
540 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
541 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
542 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
543 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
544 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
545 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
546 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
547 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
549 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
551 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
552 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
553 0x0e800120, 0x0f800ff0,
554 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
555 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
556 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
557 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
558 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
559 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
560 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
561 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
562 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
563 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
564 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
565 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
566 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
567 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
568 0x0e8000a0, 0x0f800ff0,
569 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
570 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
571 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
572 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
573 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
574 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
575 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
576 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
577 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
578 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
579 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
580 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
581 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
582 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
583 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
584 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
585 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
586 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
587 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
588 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
589 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
590 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
591 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
592 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
593 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
594 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
595 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
596 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
597 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
598 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
599 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
600 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
601 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
602 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
603 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
604 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
605 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
606 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
607 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
608 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
609 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
610 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
611 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
612 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
613 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
614 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
615 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
616 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
617 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
618 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
619 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
620 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
621 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
622 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
623 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
624 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
625 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
626 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
627 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
628 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
629 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
630 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
631 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
632 {ANY, ARM_FEATURE_CORE_LOW (0),
633 SENTINEL_IWMMXT_END, 0, "" },
634
635 /* Floating point coprocessor (FPA) instructions. */
636 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
637 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
638 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
639 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
640 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
641 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
642 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
643 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
644 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
645 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
646 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
647 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
648 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
649 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
650 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
651 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
652 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
653 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
654 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
655 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
656 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
657 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
658 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
659 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
660 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
661 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
662 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
663 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
664 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
665 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
666 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
667 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
668 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
669 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
670 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
671 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
672 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
673 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
674 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
675 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
676 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
677 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
678 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
679 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
680 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
681 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
682 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
683 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
684 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
685 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
686 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
687 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
688 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
689 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
690 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
691 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
692 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
693 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
694 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
695 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
696 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
697 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
698 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
699 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
700 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
701 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
702 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
703 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
704 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
705 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
706 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
707 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
708 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
709 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
710 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
711 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
712 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
713 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
714 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
715 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
716 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
717 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
718 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
719 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
720 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
721 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
722
723 /* Armv8.1-M Mainline instructions. */
724 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
725 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
726 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
727 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
728
729 /* ARMv8-M Mainline Security Extensions instructions. */
730 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
731 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
732 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
733 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
734
735 /* Register load/store. */
736 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
737 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
738 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
739 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
740 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
741 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
742 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
743 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
744 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
745 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
746 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
747 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
748 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
749 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
750 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
751 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
752 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
753 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
754 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
755 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
756 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
757 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
758 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
759 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
760 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
761 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
762 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
763 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
764 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
765 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
766 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
767 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
768 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
769 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
770 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
771 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
772
773 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
774 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
775 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
776 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
777 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
778 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
779 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
780 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
781
782 /* Data transfer between ARM and NEON registers. */
783 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
784 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
785 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
786 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
787 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
788 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
789 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
790 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
791 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
792 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
793 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
794 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
795 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
796 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
797 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
798 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
799 /* Half-precision conversion instructions. */
800 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
801 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
802 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
803 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
804 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
805 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
806 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
807 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
808
809 /* Floating point coprocessor (VFP) instructions. */
810 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
811 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
812 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
813 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
814 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
815 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
816 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
817 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
818 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
819 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
820 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
821 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
822 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
824 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
825 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
826 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
827 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
828 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
829 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
830 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
831 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
832 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
833 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
834 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
835 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
836 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
837 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
838 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
839 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
840 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
841 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
842 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
843 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
844 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
845 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
846 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
847 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
849 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
851 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
853 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
854 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
855 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
856 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
857 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
858 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
859 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
860 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
861 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
862 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
863 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
864 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
865 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
866 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
867 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
868 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
869 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
870 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
871 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
872 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
873 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
874 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
875 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
876 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
877 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
878 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
879 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
880 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
881 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
882 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
883 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
884 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
885 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
886 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
887 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
888 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
889 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
890 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
891 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
892 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
893 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
894 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
895 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
896 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
897 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
898 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
899 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
900 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
901 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
902 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
903 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
904 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
905 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
906 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
907 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
908 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
909 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
910 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
911 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
912 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
913 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
914 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
915 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
916 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
917 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
918 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
919 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
920 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
921 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
922 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
923 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
924 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
925 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
926 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
927 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
928 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
929 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
930 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
931 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
932 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
933 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
934 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
935 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
936 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
937 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
938 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
939 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
940 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
941 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
942 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
943 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
944 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
945 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
946 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
947 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
948 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
949 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
950 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
951 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
952 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
953 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
954 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
955 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
956 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
957 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
958 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
959 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
960 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
961 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
962 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
963 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
964 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
965 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
966 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
967 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
968
969 /* Cirrus coprocessor instructions. */
970 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
971 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
972 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
973 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
974 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
975 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
976 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
977 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
978 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
979 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
980 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
981 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
982 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
983 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
984 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
985 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
986 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
987 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
988 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
989 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
990 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
991 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
992 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
993 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
994 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
995 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
996 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
997 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
998 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
999 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1000 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1001 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1002 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1003 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
1004 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1005 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
1006 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1007 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
1008 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1009 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
1010 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1011 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
1012 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1013 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
1014 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1015 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
1016 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1017 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
1018 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1019 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
1020 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1021 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
1022 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1023 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
1024 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1025 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
1026 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1027 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
1028 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1029 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
1030 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1031 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
1032 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1033 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
1034 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1035 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
1036 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1037 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
1038 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1039 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
1040 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1041 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
1042 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1043 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
1044 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1045 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
1046 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1047 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
1048 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1049 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
1050 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1051 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
1052 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1053 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
1054 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1055 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
1056 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1057 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
1058 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1059 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
1060 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1061 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
1062 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1063 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
1064 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1065 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
1066 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1067 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
1068 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1069 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
1070 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1071 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
1072 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1073 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
1074 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1075 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
1076 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1077 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
1078 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1079 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
1080 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1081 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
1082 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1083 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
1084 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1085 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
1086 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1087 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1088 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1089 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1090 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1091 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1092 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1093 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1094 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1095 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1096 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1097 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1098 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1099 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1100 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1101 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1102 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1103 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1104 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1105 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1106 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1107 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1108 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1109 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1110 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1111 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1112 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1113 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1114 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1115 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1116 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1117 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1118 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1119 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1120 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1121 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1122 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1123 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1124 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1125 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1126 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1127 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1128 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1129 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1130 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1131 0x0e000600, 0x0ff00f10,
1132 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1133 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1134 0x0e100600, 0x0ff00f10,
1135 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1136 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1137 0x0e200600, 0x0ff00f10,
1138 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1139 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1140 0x0e300600, 0x0ff00f10,
1141 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1142
1143 /* VFP Fused multiply add instructions. */
1144 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1145 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1146 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1147 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1148 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1149 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1150 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1151 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1152 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1153 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1154 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1155 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1156 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1157 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1158 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1159 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1160
1161 /* FP v5. */
1162 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1163 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1164 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1165 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1166 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1167 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1168 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1169 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1170 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1171 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1172 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1173 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1174 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1175 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1176 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1177 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1178 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1179 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1180 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1181 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1182 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1183 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1184 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1185 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1186
1187 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1188 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1189 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1190 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1191 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1192 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1193 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1194 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1195 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1196 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1197 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1198 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1199 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1200 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1201 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1202 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1203 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1204 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1205 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1206 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1207 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1208 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1209
1210 /* Dot Product instructions in the space of coprocessor 13. */
1211 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1212 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1213 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1214 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1215
1216 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1217 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1218 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1219 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1220 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1221 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1222 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1223 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1224 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1225 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1226 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1227 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1228 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1229 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1230 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1231 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1232 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1233
1234 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1235 cp_num: bit <11:8> == 0b1001.
1236 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1237 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1238 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1239 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1240 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1241 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1242 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1243 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1244 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1245 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1246 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1247 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1248 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1249 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1250 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1251 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1252 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1253 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1254 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1255 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1256 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1257 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1258 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1259 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1260 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1261 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1262 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1263 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1264 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1265 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1266 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1267 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1268 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1269 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1270 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1271 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1272 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1273 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1274 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1275 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1276 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1277 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1278 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1279 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1280 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1281 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1282 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1283 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1284 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1285 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1286 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1287 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1288 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1289 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1290 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1291 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1292 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1293 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1294 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1295 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1296 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1297 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1298 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1299 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1300 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1301 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1302 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1303 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1304 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1305 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1306 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1307
1308 /* ARMv8.3 javascript conversion instruction. */
1309 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1310 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1311
1312 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1313 };
1314
1315 /* Generic coprocessor instructions. These are only matched if a more specific
1316 SIMD or co-processor instruction does not match first. */
1317
1318 static const struct sopcode32 generic_coprocessor_opcodes[] =
1319 {
1320 /* Generic coprocessor instructions. */
1321 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1322 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1323 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1324 0x0c500000, 0x0ff00000,
1325 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1326 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1327 0x0e000000, 0x0f000010,
1328 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1329 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1330 0x0e10f010, 0x0f10f010,
1331 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1332 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1333 0x0e100010, 0x0f100010,
1334 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1335 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1336 0x0e000010, 0x0f100010,
1337 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1338 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1339 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1340 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1341 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1342
1343 /* V6 coprocessor instructions. */
1344 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1345 0xfc500000, 0xfff00000,
1346 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1347 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1348 0xfc400000, 0xfff00000,
1349 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1350
1351 /* V5 coprocessor instructions. */
1352 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1353 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1354 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1355 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1356 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1357 0xfe000000, 0xff000010,
1358 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1359 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1360 0xfe000010, 0xff100010,
1361 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1362 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1363 0xfe100010, 0xff100010,
1364 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1365
1366 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1367 };
1368
1369 /* Neon opcode table: This does not encode the top byte -- that is
1370 checked by the print_insn_neon routine, as it depends on whether we are
1371 doing thumb32 or arm32 disassembly. */
1372
1373 /* print_insn_neon recognizes the following format control codes:
1374
1375 %% %
1376
1377 %c print condition code
1378 %u print condition code (unconditional in ARM mode,
1379 UNPREDICTABLE if not AL in Thumb)
1380 %A print v{st,ld}[1234] operands
1381 %B print v{st,ld}[1234] any one operands
1382 %C print v{st,ld}[1234] single->all operands
1383 %D print scalar
1384 %E print vmov, vmvn, vorr, vbic encoded constant
1385 %F print vtbl,vtbx register list
1386
1387 %<bitfield>r print as an ARM register
1388 %<bitfield>d print the bitfield in decimal
1389 %<bitfield>e print the 2^N - bitfield in decimal
1390 %<bitfield>D print as a NEON D register
1391 %<bitfield>Q print as a NEON Q register
1392 %<bitfield>R print as a NEON D or Q register
1393 %<bitfield>Sn print byte scaled width limited by n
1394 %<bitfield>Tn print short scaled width limited by n
1395 %<bitfield>Un print long scaled width limited by n
1396
1397 %<bitfield>'c print specified char iff bitfield is all ones
1398 %<bitfield>`c print specified char iff bitfield is all zeroes
1399 %<bitfield>?ab... select from array of values in big endian order. */
1400
1401 static const struct opcode32 neon_opcodes[] =
1402 {
1403 /* Extract. */
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0xf2b00840, 0xffb00850,
1406 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1407 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1408 0xf2b00000, 0xffb00810,
1409 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1410
1411 /* Data transfer between ARM and NEON registers. */
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1424
1425 /* Move data element to all lanes. */
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1432
1433 /* Table lookup. */
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1437 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1438
1439 /* Half-precision conversions. */
1440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1441 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1443 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1444
1445 /* NEON fused multiply add instructions. */
1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1447 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1448 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1449 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1451 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1452 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1453 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1454
1455 /* Two registers, miscellaneous. */
1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1457 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1458 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1459 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1461 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1463 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1464 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1465 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1466 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1467 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1468 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1469 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1470 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1471 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1472 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1473 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1474 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1475 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1476 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1477 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499 0xf3b20300, 0xffb30fd0,
1500 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1503 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1504 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1507 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1508 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1543 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1544 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1548 0xf3bb0600, 0xffbf0e10,
1549 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1551 0xf3b70600, 0xffbf0e10,
1552 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1553
1554 /* Three registers of the same length. */
1555 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1556 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1557 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1558 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1559 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1560 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1561 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1562 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1563 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1564 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1565 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1566 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1567 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1568 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1570 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1571 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1572 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1574 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1575 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1576 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1580 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1592 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1596 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1599 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1600 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1603 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1604 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1608 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1611 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1612 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1615 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1616 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1620 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1623 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1624 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1627 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1628 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1632 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1635 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1636 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1639 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1640 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1643 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1644 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1647 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1648 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1651 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1652 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1655 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1656 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1659 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1660 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1663 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1664 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1665 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1666 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1670 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672 0xf2000b00, 0xff800f10,
1673 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1674 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1675 0xf2000b10, 0xff800f10,
1676 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684 0xf3000b00, 0xff800f10,
1685 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687 0xf2000000, 0xfe800f10,
1688 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690 0xf2000010, 0xfe800f10,
1691 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693 0xf2000100, 0xfe800f10,
1694 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696 0xf2000200, 0xfe800f10,
1697 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699 0xf2000210, 0xfe800f10,
1700 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702 0xf2000300, 0xfe800f10,
1703 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1705 0xf2000310, 0xfe800f10,
1706 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708 0xf2000400, 0xfe800f10,
1709 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1711 0xf2000410, 0xfe800f10,
1712 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714 0xf2000500, 0xfe800f10,
1715 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1717 0xf2000510, 0xfe800f10,
1718 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1719 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1720 0xf2000600, 0xfe800f10,
1721 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1722 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1723 0xf2000610, 0xfe800f10,
1724 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1726 0xf2000700, 0xfe800f10,
1727 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1729 0xf2000710, 0xfe800f10,
1730 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1732 0xf2000910, 0xfe800f10,
1733 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1734 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1735 0xf2000a00, 0xfe800f10,
1736 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1738 0xf2000a10, 0xfe800f10,
1739 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1741 0xf3000b10, 0xff800f10,
1742 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1744 0xf3000c10, 0xff800f10,
1745 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1746
1747 /* One register and an immediate value. */
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1751 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1755 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1763 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1766 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1767 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1774
1775 /* Two registers and a shift amount. */
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1780 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1781 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1782 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1783 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1785 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787 0xf2880950, 0xfeb80fd0,
1788 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1790 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1792 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1798 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1803 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1804 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1807 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1808 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1810 0xf2900950, 0xfeb00fd0,
1811 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1813 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1817 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1819 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1823 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1825 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1829 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1831 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1835 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1837 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1841 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1842 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1843 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1847 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1848 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1849 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1851 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1852 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1853 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1854 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1855 0xf2a00950, 0xfea00fd0,
1856 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1880 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1881 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1882 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1886 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1888 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1889 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1890 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1891 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1892 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1893 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1894 0xf2a00e10, 0xfea00e90,
1895 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1896 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1897 0xf2a00c10, 0xfea00e90,
1898 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1899
1900 /* Three registers of different lengths. */
1901 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1902 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1904 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1905 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1906 0xf2800400, 0xff800f50,
1907 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1908 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1909 0xf2800600, 0xff800f50,
1910 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1911 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1912 0xf2800900, 0xff800f50,
1913 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1915 0xf2800b00, 0xff800f50,
1916 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1917 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1918 0xf2800d00, 0xff800f50,
1919 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1920 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1921 0xf3800400, 0xff800f50,
1922 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1923 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1924 0xf3800600, 0xff800f50,
1925 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1926 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1927 0xf2800000, 0xfe800f50,
1928 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1929 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1930 0xf2800100, 0xfe800f50,
1931 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1932 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1933 0xf2800200, 0xfe800f50,
1934 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1936 0xf2800300, 0xfe800f50,
1937 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1938 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1939 0xf2800500, 0xfe800f50,
1940 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1942 0xf2800700, 0xfe800f50,
1943 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1945 0xf2800800, 0xfe800f50,
1946 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1948 0xf2800a00, 0xfe800f50,
1949 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1951 0xf2800c00, 0xfe800f50,
1952 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1953
1954 /* Two registers and a scalar. */
1955 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1956 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1958 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1959 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1960 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1962 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1963 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1964 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1965 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1966 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1967 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1968 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1969 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1970 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1971 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1972 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1973 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1974 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1975 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1976 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1977 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1978 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1979 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1980 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1981 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1982 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1984 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1985 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1986 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1987 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1988 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1989 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1990 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1991 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1992 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1993 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1994 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1995 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1996 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1997 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1998 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1999 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2000 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2001 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2002 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2003 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2004 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2005 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2006 0xf2800240, 0xfe800f50,
2007 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2008 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2009 0xf2800640, 0xfe800f50,
2010 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2011 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2012 0xf2800a40, 0xfe800f50,
2013 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2014 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2015 0xf2800e40, 0xff800f50,
2016 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2017 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2018 0xf2800f40, 0xff800f50,
2019 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2020 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2021 0xf3800e40, 0xff800f50,
2022 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2024 0xf3800f40, 0xff800f50,
2025 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2026 },
2027
2028 /* Element and structure load/store. */
2029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2030 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2031 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2032 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2034 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2036 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2037 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2038 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2040 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2042 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2043 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2044 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2046 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2048 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2049 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2050 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2051 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2052 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2053 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2054 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2055 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2056 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2057 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2058 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2059 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2060 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2061 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2062 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2063 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2064 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2065 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2066 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2067
2068 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
2069 };
2070
2071 /* mve opcode table. */
2072
2073 /* print_insn_mve recognizes the following format control codes:
2074
2075 %% %
2076
2077 %a print '+' or '-' or imm offset in vldr[bhwd] and
2078 vstr[bhwd]
2079 %c print condition code
2080 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2081 %u print 'U' (unsigned) or 'S' for various mve instructions
2082 %i print MVE predicate(s) for vpt and vpst
2083 %j print a 5-bit immediate from hw2[14:12,7:6]
2084 %k print 48 if the 7th position bit is set else print 64.
2085 %m print rounding mode for vcvt and vrint
2086 %n print vector comparison code for predicated instruction
2087 %s print size for various vcvt instructions
2088 %v print vector predicate for instruction in predicated
2089 block
2090 %o print offset scaled for vldr[hwd] and vstr[hwd]
2091 %w print writeback mode for MVE v{st,ld}[24]
2092 %B print v{st,ld}[24] any one operands
2093 %E print vmov, vmvn, vorr, vbic encoded constant
2094 %N print generic index for vmov
2095 %T print bottom ('b') or top ('t') of source register
2096 %X print exchange field in vmla* instructions
2097
2098 %<bitfield>r print as an ARM register
2099 %<bitfield>d print the bitfield in decimal
2100 %<bitfield>A print accumulate or not
2101 %<bitfield>c print bitfield as a condition code
2102 %<bitfield>C print bitfield as an inverted condition code
2103 %<bitfield>Q print as a MVE Q register
2104 %<bitfield>F print as a MVE S register
2105 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2106 UNPREDICTABLE
2107
2108 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
2109 %<bitfield>s print size for vector predicate & non VMOV instructions
2110 %<bitfield>I print carry flag or not
2111 %<bitfield>i print immediate for vstr/vldr reg +/- imm
2112 %<bitfield>h print high half of 64-bit destination reg
2113 %<bitfield>k print immediate for vector conversion instruction
2114 %<bitfield>l print low half of 64-bit destination reg
2115 %<bitfield>o print rotate value for vcmul
2116 %<bitfield>u print immediate value for vddup/vdwdup
2117 %<bitfield>x print the bitfield in hex.
2118 */
2119
2120 static const struct mopcode32 mve_opcodes[] =
2121 {
2122 /* MVE. */
2123
2124 {ARM_FEATURE_COPROC (FPU_MVE),
2125 MVE_VPST,
2126 0xfe310f4d, 0xffbf1fff,
2127 "vpst%i"
2128 },
2129
2130 /* Floating point VPT T1. */
2131 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2132 MVE_VPT_FP_T1,
2133 0xee310f00, 0xefb10f50,
2134 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2135 /* Floating point VPT T2. */
2136 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2137 MVE_VPT_FP_T2,
2138 0xee310f40, 0xefb10f50,
2139 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2140
2141 /* Vector VPT T1. */
2142 {ARM_FEATURE_COPROC (FPU_MVE),
2143 MVE_VPT_VEC_T1,
2144 0xfe010f00, 0xff811f51,
2145 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2146 /* Vector VPT T2. */
2147 {ARM_FEATURE_COPROC (FPU_MVE),
2148 MVE_VPT_VEC_T2,
2149 0xfe010f01, 0xff811f51,
2150 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2151 /* Vector VPT T3. */
2152 {ARM_FEATURE_COPROC (FPU_MVE),
2153 MVE_VPT_VEC_T3,
2154 0xfe011f00, 0xff811f50,
2155 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2156 /* Vector VPT T4. */
2157 {ARM_FEATURE_COPROC (FPU_MVE),
2158 MVE_VPT_VEC_T4,
2159 0xfe010f40, 0xff811f70,
2160 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2161 /* Vector VPT T5. */
2162 {ARM_FEATURE_COPROC (FPU_MVE),
2163 MVE_VPT_VEC_T5,
2164 0xfe010f60, 0xff811f70,
2165 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2166 /* Vector VPT T6. */
2167 {ARM_FEATURE_COPROC (FPU_MVE),
2168 MVE_VPT_VEC_T6,
2169 0xfe011f40, 0xff811f50,
2170 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2171
2172 /* Vector VBIC immediate. */
2173 {ARM_FEATURE_COPROC (FPU_MVE),
2174 MVE_VBIC_IMM,
2175 0xef800070, 0xefb81070,
2176 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2177
2178 /* Vector VBIC register. */
2179 {ARM_FEATURE_COPROC (FPU_MVE),
2180 MVE_VBIC_REG,
2181 0xef100150, 0xffb11f51,
2182 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2183
2184 /* Vector VABAV. */
2185 {ARM_FEATURE_COPROC (FPU_MVE),
2186 MVE_VABAV,
2187 0xee800f01, 0xefc10f51,
2188 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2189
2190 /* Vector VABD floating point. */
2191 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2192 MVE_VABD_FP,
2193 0xff200d40, 0xffa11f51,
2194 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2195
2196 /* Vector VABD. */
2197 {ARM_FEATURE_COPROC (FPU_MVE),
2198 MVE_VABD_VEC,
2199 0xef000740, 0xef811f51,
2200 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2201
2202 /* Vector VABS floating point. */
2203 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2204 MVE_VABS_FP,
2205 0xFFB10740, 0xFFB31FD1,
2206 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2207 /* Vector VABS. */
2208 {ARM_FEATURE_COPROC (FPU_MVE),
2209 MVE_VABS_VEC,
2210 0xffb10340, 0xffb31fd1,
2211 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2212
2213 /* Vector VADD floating point T1. */
2214 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2215 MVE_VADD_FP_T1,
2216 0xef000d40, 0xffa11f51,
2217 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2218 /* Vector VADD floating point T2. */
2219 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2220 MVE_VADD_FP_T2,
2221 0xee300f40, 0xefb11f70,
2222 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2223 /* Vector VADD T1. */
2224 {ARM_FEATURE_COPROC (FPU_MVE),
2225 MVE_VADD_VEC_T1,
2226 0xef000840, 0xff811f51,
2227 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2228 /* Vector VADD T2. */
2229 {ARM_FEATURE_COPROC (FPU_MVE),
2230 MVE_VADD_VEC_T2,
2231 0xee010f40, 0xff811f70,
2232 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2233
2234 /* Vector VADDLV. */
2235 {ARM_FEATURE_COPROC (FPU_MVE),
2236 MVE_VADDLV,
2237 0xee890f00, 0xef8f1fd1,
2238 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2239
2240 /* Vector VADDV. */
2241 {ARM_FEATURE_COPROC (FPU_MVE),
2242 MVE_VADDV,
2243 0xeef10f00, 0xeff31fd1,
2244 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2245
2246 /* Vector VADC. */
2247 {ARM_FEATURE_COPROC (FPU_MVE),
2248 MVE_VADC,
2249 0xee300f00, 0xffb10f51,
2250 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2251
2252 /* Vector VAND. */
2253 {ARM_FEATURE_COPROC (FPU_MVE),
2254 MVE_VAND,
2255 0xef000150, 0xffb11f51,
2256 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2257
2258 /* Vector VBRSR register. */
2259 {ARM_FEATURE_COPROC (FPU_MVE),
2260 MVE_VBRSR,
2261 0xfe011e60, 0xff811f70,
2262 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2263
2264 /* Vector VCADD floating point. */
2265 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2266 MVE_VCADD_FP,
2267 0xfc800840, 0xfea11f51,
2268 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2269
2270 /* Vector VCADD. */
2271 {ARM_FEATURE_COPROC (FPU_MVE),
2272 MVE_VCADD_VEC,
2273 0xfe000f00, 0xff810f51,
2274 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2275
2276 /* Vector VCLS. */
2277 {ARM_FEATURE_COPROC (FPU_MVE),
2278 MVE_VCLS,
2279 0xffb00440, 0xffb31fd1,
2280 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2281
2282 /* Vector VCLZ. */
2283 {ARM_FEATURE_COPROC (FPU_MVE),
2284 MVE_VCLZ,
2285 0xffb004c0, 0xffb31fd1,
2286 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2287
2288 /* Vector VCMLA. */
2289 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2290 MVE_VCMLA_FP,
2291 0xfc200840, 0xfe211f51,
2292 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2293
2294 /* Vector VCMP floating point T1. */
2295 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2296 MVE_VCMP_FP_T1,
2297 0xee310f00, 0xeff1ef50,
2298 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2299
2300 /* Vector VCMP floating point T2. */
2301 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2302 MVE_VCMP_FP_T2,
2303 0xee310f40, 0xeff1ef50,
2304 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2305
2306 /* Vector VCMP T1. */
2307 {ARM_FEATURE_COPROC (FPU_MVE),
2308 MVE_VCMP_VEC_T1,
2309 0xfe010f00, 0xffc1ff51,
2310 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2311 /* Vector VCMP T2. */
2312 {ARM_FEATURE_COPROC (FPU_MVE),
2313 MVE_VCMP_VEC_T2,
2314 0xfe010f01, 0xffc1ff51,
2315 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2316 /* Vector VCMP T3. */
2317 {ARM_FEATURE_COPROC (FPU_MVE),
2318 MVE_VCMP_VEC_T3,
2319 0xfe011f00, 0xffc1ff50,
2320 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2321 /* Vector VCMP T4. */
2322 {ARM_FEATURE_COPROC (FPU_MVE),
2323 MVE_VCMP_VEC_T4,
2324 0xfe010f40, 0xffc1ff70,
2325 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2326 /* Vector VCMP T5. */
2327 {ARM_FEATURE_COPROC (FPU_MVE),
2328 MVE_VCMP_VEC_T5,
2329 0xfe010f60, 0xffc1ff70,
2330 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2331 /* Vector VCMP T6. */
2332 {ARM_FEATURE_COPROC (FPU_MVE),
2333 MVE_VCMP_VEC_T6,
2334 0xfe011f40, 0xffc1ff50,
2335 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2336
2337 /* Vector VDUP. */
2338 {ARM_FEATURE_COPROC (FPU_MVE),
2339 MVE_VDUP,
2340 0xeea00b10, 0xffb10f5f,
2341 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2342
2343 /* Vector VEOR. */
2344 {ARM_FEATURE_COPROC (FPU_MVE),
2345 MVE_VEOR,
2346 0xff000150, 0xffd11f51,
2347 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2348
2349 /* Vector VFMA, vector * scalar. */
2350 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2351 MVE_VFMA_FP_SCALAR,
2352 0xee310e40, 0xefb11f70,
2353 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2354
2355 /* Vector VFMA floating point. */
2356 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2357 MVE_VFMA_FP,
2358 0xef000c50, 0xffa11f51,
2359 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2360
2361 /* Vector VFMS floating point. */
2362 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2363 MVE_VFMS_FP,
2364 0xef200c50, 0xffa11f51,
2365 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2366
2367 /* Vector VFMAS, vector * scalar. */
2368 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2369 MVE_VFMAS_FP_SCALAR,
2370 0xee311e40, 0xefb11f70,
2371 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2372
2373 /* Vector VHADD T1. */
2374 {ARM_FEATURE_COPROC (FPU_MVE),
2375 MVE_VHADD_T1,
2376 0xef000040, 0xef811f51,
2377 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2378
2379 /* Vector VHADD T2. */
2380 {ARM_FEATURE_COPROC (FPU_MVE),
2381 MVE_VHADD_T2,
2382 0xee000f40, 0xef811f70,
2383 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2384
2385 /* Vector VHSUB T1. */
2386 {ARM_FEATURE_COPROC (FPU_MVE),
2387 MVE_VHSUB_T1,
2388 0xef000240, 0xef811f51,
2389 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2390
2391 /* Vector VHSUB T2. */
2392 {ARM_FEATURE_COPROC (FPU_MVE),
2393 MVE_VHSUB_T2,
2394 0xee001f40, 0xef811f70,
2395 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2396
2397 /* Vector VCMUL. */
2398 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2399 MVE_VCMUL_FP,
2400 0xee300e00, 0xefb10f50,
2401 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2402
2403 /* Vector VCTP. */
2404 {ARM_FEATURE_COPROC (FPU_MVE),
2405 MVE_VCTP,
2406 0xf000e801, 0xffc0ffff,
2407 "vctp%v.%20-21s\t%16-19r"},
2408
2409 /* Vector VDUP. */
2410 {ARM_FEATURE_COPROC (FPU_MVE),
2411 MVE_VDUP,
2412 0xeea00b10, 0xffb10f5f,
2413 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2414
2415 /* Vector VRHADD. */
2416 {ARM_FEATURE_COPROC (FPU_MVE),
2417 MVE_VRHADD,
2418 0xef000140, 0xef811f51,
2419 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2420
2421 /* Vector VCVT. */
2422 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2423 MVE_VCVT_FP_FIX_VEC,
2424 0xef800c50, 0xef801cd1,
2425 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2426
2427 /* Vector VCVT. */
2428 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2429 MVE_VCVT_BETWEEN_FP_INT,
2430 0xffb30640, 0xffb31e51,
2431 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2432
2433 /* Vector VCVT between single and half-precision float, bottom half. */
2434 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2435 MVE_VCVT_FP_HALF_FP,
2436 0xee3f0e01, 0xefbf1fd1,
2437 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2438
2439 /* Vector VCVT between single and half-precision float, top half. */
2440 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2441 MVE_VCVT_FP_HALF_FP,
2442 0xee3f1e01, 0xefbf1fd1,
2443 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2444
2445 /* Vector VCVT. */
2446 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2447 MVE_VCVT_FROM_FP_TO_INT,
2448 0xffb30040, 0xffb31c51,
2449 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2450
2451 /* Vector VDDUP. */
2452 {ARM_FEATURE_COPROC (FPU_MVE),
2453 MVE_VDDUP,
2454 0xee011f6e, 0xff811f7e,
2455 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2456
2457 /* Vector VDWDUP. */
2458 {ARM_FEATURE_COPROC (FPU_MVE),
2459 MVE_VDWDUP,
2460 0xee011f60, 0xff811f70,
2461 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2462
2463 /* Vector VHCADD. */
2464 {ARM_FEATURE_COPROC (FPU_MVE),
2465 MVE_VHCADD,
2466 0xee000f00, 0xff810f51,
2467 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2468
2469 /* Vector VIWDUP. */
2470 {ARM_FEATURE_COPROC (FPU_MVE),
2471 MVE_VIWDUP,
2472 0xee010f60, 0xff811f70,
2473 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2474
2475 /* Vector VIDUP. */
2476 {ARM_FEATURE_COPROC (FPU_MVE),
2477 MVE_VIDUP,
2478 0xee010f6e, 0xff811f7e,
2479 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2480
2481 /* Vector VLD2. */
2482 {ARM_FEATURE_COPROC (FPU_MVE),
2483 MVE_VLD2,
2484 0xfc901e00, 0xff901e5f,
2485 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2486
2487 /* Vector VLD4. */
2488 {ARM_FEATURE_COPROC (FPU_MVE),
2489 MVE_VLD4,
2490 0xfc901e01, 0xff901e1f,
2491 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2492
2493 /* Vector VLDRB gather load. */
2494 {ARM_FEATURE_COPROC (FPU_MVE),
2495 MVE_VLDRB_GATHER_T1,
2496 0xec900e00, 0xefb01e50,
2497 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2498
2499 /* Vector VLDRH gather load. */
2500 {ARM_FEATURE_COPROC (FPU_MVE),
2501 MVE_VLDRH_GATHER_T2,
2502 0xec900e10, 0xefb01e50,
2503 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2504
2505 /* Vector VLDRW gather load. */
2506 {ARM_FEATURE_COPROC (FPU_MVE),
2507 MVE_VLDRW_GATHER_T3,
2508 0xfc900f40, 0xffb01fd0,
2509 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2510
2511 /* Vector VLDRD gather load. */
2512 {ARM_FEATURE_COPROC (FPU_MVE),
2513 MVE_VLDRD_GATHER_T4,
2514 0xec900fd0, 0xefb01fd0,
2515 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2516
2517 /* Vector VLDRW gather load. */
2518 {ARM_FEATURE_COPROC (FPU_MVE),
2519 MVE_VLDRW_GATHER_T5,
2520 0xfd101e00, 0xff111f00,
2521 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2522
2523 /* Vector VLDRD gather load, variant T6. */
2524 {ARM_FEATURE_COPROC (FPU_MVE),
2525 MVE_VLDRD_GATHER_T6,
2526 0xfd101f00, 0xff111f00,
2527 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2528
2529 /* Vector VLDRB. */
2530 {ARM_FEATURE_COPROC (FPU_MVE),
2531 MVE_VLDRB_T1,
2532 0xec100e00, 0xee581e00,
2533 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2534
2535 /* Vector VLDRH. */
2536 {ARM_FEATURE_COPROC (FPU_MVE),
2537 MVE_VLDRH_T2,
2538 0xec180e00, 0xee581e00,
2539 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2540
2541 /* Vector VLDRB unsigned, variant T5. */
2542 {ARM_FEATURE_COPROC (FPU_MVE),
2543 MVE_VLDRB_T5,
2544 0xec101e00, 0xfe101f80,
2545 "vldrb%v.u8\t%13-15,22Q, %d"},
2546
2547 /* Vector VLDRH unsigned, variant T6. */
2548 {ARM_FEATURE_COPROC (FPU_MVE),
2549 MVE_VLDRH_T6,
2550 0xec101e80, 0xfe101f80,
2551 "vldrh%v.u16\t%13-15,22Q, %d"},
2552
2553 /* Vector VLDRW unsigned, variant T7. */
2554 {ARM_FEATURE_COPROC (FPU_MVE),
2555 MVE_VLDRW_T7,
2556 0xec101f00, 0xfe101f80,
2557 "vldrw%v.u32\t%13-15,22Q, %d"},
2558
2559 /* Vector VMAX. */
2560 {ARM_FEATURE_COPROC (FPU_MVE),
2561 MVE_VMAX,
2562 0xef000640, 0xef811f51,
2563 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2564
2565 /* Vector VMAXA. */
2566 {ARM_FEATURE_COPROC (FPU_MVE),
2567 MVE_VMAXA,
2568 0xee330e81, 0xffb31fd1,
2569 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2570
2571 /* Vector VMAXNM floating point. */
2572 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2573 MVE_VMAXNM_FP,
2574 0xff000f50, 0xffa11f51,
2575 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2576
2577 /* Vector VMAXNMA floating point. */
2578 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2579 MVE_VMAXNMA_FP,
2580 0xee3f0e81, 0xefbf1fd1,
2581 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2582
2583 /* Vector VMAXNMV floating point. */
2584 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2585 MVE_VMAXNMV_FP,
2586 0xeeee0f00, 0xefff0fd1,
2587 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2588
2589 /* Vector VMAXNMAV floating point. */
2590 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2591 MVE_VMAXNMAV_FP,
2592 0xeeec0f00, 0xefff0fd1,
2593 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2594
2595 /* Vector VMAXV. */
2596 {ARM_FEATURE_COPROC (FPU_MVE),
2597 MVE_VMAXV,
2598 0xeee20f00, 0xeff30fd1,
2599 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2600
2601 /* Vector VMAXAV. */
2602 {ARM_FEATURE_COPROC (FPU_MVE),
2603 MVE_VMAXAV,
2604 0xeee00f00, 0xfff30fd1,
2605 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2606
2607 /* Vector VMIN. */
2608 {ARM_FEATURE_COPROC (FPU_MVE),
2609 MVE_VMIN,
2610 0xef000650, 0xef811f51,
2611 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2612
2613 /* Vector VMINA. */
2614 {ARM_FEATURE_COPROC (FPU_MVE),
2615 MVE_VMINA,
2616 0xee331e81, 0xffb31fd1,
2617 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2618
2619 /* Vector VMINNM floating point. */
2620 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2621 MVE_VMINNM_FP,
2622 0xff200f50, 0xffa11f51,
2623 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2624
2625 /* Vector VMINNMA floating point. */
2626 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2627 MVE_VMINNMA_FP,
2628 0xee3f1e81, 0xefbf1fd1,
2629 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2630
2631 /* Vector VMINNMV floating point. */
2632 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2633 MVE_VMINNMV_FP,
2634 0xeeee0f80, 0xefff0fd1,
2635 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2636
2637 /* Vector VMINNMAV floating point. */
2638 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2639 MVE_VMINNMAV_FP,
2640 0xeeec0f80, 0xefff0fd1,
2641 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2642
2643 /* Vector VMINV. */
2644 {ARM_FEATURE_COPROC (FPU_MVE),
2645 MVE_VMINV,
2646 0xeee20f80, 0xeff30fd1,
2647 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2648
2649 /* Vector VMINAV. */
2650 {ARM_FEATURE_COPROC (FPU_MVE),
2651 MVE_VMINAV,
2652 0xeee00f80, 0xfff30fd1,
2653 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2654
2655 /* Vector VMLA. */
2656 {ARM_FEATURE_COPROC (FPU_MVE),
2657 MVE_VMLA,
2658 0xee010e40, 0xef811f70,
2659 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2660
2661 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2662 opcode aliasing. */
2663 {ARM_FEATURE_COPROC (FPU_MVE),
2664 MVE_VMLALDAV,
2665 0xee801e00, 0xef801f51,
2666 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2667
2668 {ARM_FEATURE_COPROC (FPU_MVE),
2669 MVE_VMLALDAV,
2670 0xee800e00, 0xef801f51,
2671 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2672
2673 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2674 {ARM_FEATURE_COPROC (FPU_MVE),
2675 MVE_VMLADAV_T1,
2676 0xeef00e00, 0xeff01f51,
2677 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2678
2679 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2680 {ARM_FEATURE_COPROC (FPU_MVE),
2681 MVE_VMLADAV_T2,
2682 0xeef00f00, 0xeff11f51,
2683 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2684
2685 /* Vector VMLADAV T1 variant. */
2686 {ARM_FEATURE_COPROC (FPU_MVE),
2687 MVE_VMLADAV_T1,
2688 0xeef01e00, 0xeff01f51,
2689 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2690
2691 /* Vector VMLADAV T2 variant. */
2692 {ARM_FEATURE_COPROC (FPU_MVE),
2693 MVE_VMLADAV_T2,
2694 0xeef01f00, 0xeff11f51,
2695 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2696
2697 /* Vector VMLAS. */
2698 {ARM_FEATURE_COPROC (FPU_MVE),
2699 MVE_VMLAS,
2700 0xee011e40, 0xef811f70,
2701 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2702
2703 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2704 opcode aliasing. */
2705 {ARM_FEATURE_COPROC (FPU_MVE),
2706 MVE_VRMLSLDAVH,
2707 0xfe800e01, 0xff810f51,
2708 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2709
2710 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2711 opcdoe aliasing. */
2712 {ARM_FEATURE_COPROC (FPU_MVE),
2713 MVE_VMLSLDAV,
2714 0xee800e01, 0xff800f51,
2715 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2716
2717 /* Vector VMLSDAV T1 Variant. */
2718 {ARM_FEATURE_COPROC (FPU_MVE),
2719 MVE_VMLSDAV_T1,
2720 0xeef00e01, 0xfff00f51,
2721 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2722
2723 /* Vector VMLSDAV T2 Variant. */
2724 {ARM_FEATURE_COPROC (FPU_MVE),
2725 MVE_VMLSDAV_T2,
2726 0xfef00e01, 0xfff10f51,
2727 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2728
2729 /* Vector VMOV between gpr and half precision register, op == 0. */
2730 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2731 MVE_VMOV_HFP_TO_GP,
2732 0xee000910, 0xfff00f7f,
2733 "vmov.f16\t%7,16-19F, %12-15r"},
2734
2735 /* Vector VMOV between gpr and half precision register, op == 1. */
2736 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2737 MVE_VMOV_HFP_TO_GP,
2738 0xee100910, 0xfff00f7f,
2739 "vmov.f16\t%12-15r, %7,16-19F"},
2740
2741 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2742 MVE_VMOV_GP_TO_VEC_LANE,
2743 0xee000b10, 0xff900f1f,
2744 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2745
2746 /* Vector VORR immediate to vector.
2747 NOTE: MVE_VORR_IMM must appear in the table
2748 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2749 {ARM_FEATURE_COPROC (FPU_MVE),
2750 MVE_VORR_IMM,
2751 0xef800050, 0xefb810f0,
2752 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2753
2754 /* Vector VQSHL T2 Variant.
2755 NOTE: MVE_VQSHL_T2 must appear in the table before
2756 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2757 {ARM_FEATURE_COPROC (FPU_MVE),
2758 MVE_VQSHL_T2,
2759 0xef800750, 0xef801fd1,
2760 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2761
2762 /* Vector VQSHLU T3 Variant
2763 NOTE: MVE_VQSHL_T2 must appear in the table before
2764 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2765
2766 {ARM_FEATURE_COPROC (FPU_MVE),
2767 MVE_VQSHLU_T3,
2768 0xff800650, 0xff801fd1,
2769 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2770
2771 /* Vector VRSHR
2772 NOTE: MVE_VRSHR must appear in the table before
2773 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2774 {ARM_FEATURE_COPROC (FPU_MVE),
2775 MVE_VRSHR,
2776 0xef800250, 0xef801fd1,
2777 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2778
2779 /* Vector VSHL.
2780 NOTE: MVE_VSHL must appear in the table before
2781 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2782 {ARM_FEATURE_COPROC (FPU_MVE),
2783 MVE_VSHL_T1,
2784 0xef800550, 0xff801fd1,
2785 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2786
2787 /* Vector VSHR
2788 NOTE: MVE_VSHR must appear in the table before
2789 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2790 {ARM_FEATURE_COPROC (FPU_MVE),
2791 MVE_VSHR,
2792 0xef800050, 0xef801fd1,
2793 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2794
2795 /* Vector VSLI
2796 NOTE: MVE_VSLI must appear in the table before
2797 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2798 {ARM_FEATURE_COPROC (FPU_MVE),
2799 MVE_VSLI,
2800 0xff800550, 0xff801fd1,
2801 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2802
2803 /* Vector VSRI
2804 NOTE: MVE_VSRI must appear in the table before
2805 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2806 {ARM_FEATURE_COPROC (FPU_MVE),
2807 MVE_VSRI,
2808 0xff800450, 0xff801fd1,
2809 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2810
2811 /* Vector VMOV immediate to vector,
2812 cmode == 11x1 -> VMVN which is UNDEFINED
2813 for such a cmode. */
2814 {ARM_FEATURE_COPROC (FPU_MVE),
2815 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2816
2817 /* Vector VMOV immediate to vector. */
2818 {ARM_FEATURE_COPROC (FPU_MVE),
2819 MVE_VMOV_IMM_TO_VEC,
2820 0xef800050, 0xefb810d0,
2821 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2822
2823 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2824 {ARM_FEATURE_COPROC (FPU_MVE),
2825 MVE_VMOV2_VEC_LANE_TO_GP,
2826 0xec000f00, 0xffb01ff0,
2827 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2828
2829 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2830 {ARM_FEATURE_COPROC (FPU_MVE),
2831 MVE_VMOV2_VEC_LANE_TO_GP,
2832 0xec000f10, 0xffb01ff0,
2833 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2834
2835 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2836 {ARM_FEATURE_COPROC (FPU_MVE),
2837 MVE_VMOV2_GP_TO_VEC_LANE,
2838 0xec100f00, 0xffb01ff0,
2839 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2840
2841 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2842 {ARM_FEATURE_COPROC (FPU_MVE),
2843 MVE_VMOV2_GP_TO_VEC_LANE,
2844 0xec100f10, 0xffb01ff0,
2845 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2846
2847 /* Vector VMOV Vector lane to gpr. */
2848 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2849 MVE_VMOV_VEC_LANE_TO_GP,
2850 0xee100b10, 0xff100f1f,
2851 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2852
2853 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2854 to instruction opcode aliasing. */
2855 {ARM_FEATURE_COPROC (FPU_MVE),
2856 MVE_VSHLL_T1,
2857 0xeea00f40, 0xefa00fd1,
2858 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2859
2860 /* Vector VMOVL long. */
2861 {ARM_FEATURE_COPROC (FPU_MVE),
2862 MVE_VMOVL,
2863 0xeea00f40, 0xefa70fd1,
2864 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2865
2866 /* Vector VMOV and narrow. */
2867 {ARM_FEATURE_COPROC (FPU_MVE),
2868 MVE_VMOVN,
2869 0xfe310e81, 0xffb30fd1,
2870 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2871
2872 /* Floating point move extract. */
2873 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2874 MVE_VMOVX,
2875 0xfeb00a40, 0xffbf0fd0,
2876 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2877
2878 /* Vector VMUL floating-point T1 variant. */
2879 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2880 MVE_VMUL_FP_T1,
2881 0xff000d50, 0xffa11f51,
2882 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2883
2884 /* Vector VMUL floating-point T2 variant. */
2885 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2886 MVE_VMUL_FP_T2,
2887 0xee310e60, 0xefb11f70,
2888 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2889
2890 /* Vector VMUL T1 variant. */
2891 {ARM_FEATURE_COPROC (FPU_MVE),
2892 MVE_VMUL_VEC_T1,
2893 0xef000950, 0xff811f51,
2894 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2895
2896 /* Vector VMUL T2 variant. */
2897 {ARM_FEATURE_COPROC (FPU_MVE),
2898 MVE_VMUL_VEC_T2,
2899 0xee011e60, 0xff811f70,
2900 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2901
2902 /* Vector VMULH. */
2903 {ARM_FEATURE_COPROC (FPU_MVE),
2904 MVE_VMULH,
2905 0xee010e01, 0xef811f51,
2906 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2907
2908 /* Vector VRMULH. */
2909 {ARM_FEATURE_COPROC (FPU_MVE),
2910 MVE_VRMULH,
2911 0xee011e01, 0xef811f51,
2912 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2913
2914 /* Vector VMULL integer. */
2915 {ARM_FEATURE_COPROC (FPU_MVE),
2916 MVE_VMULL_INT,
2917 0xee010e00, 0xef810f51,
2918 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2919
2920 /* Vector VMULL polynomial. */
2921 {ARM_FEATURE_COPROC (FPU_MVE),
2922 MVE_VMULL_POLY,
2923 0xee310e00, 0xefb10f51,
2924 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2925
2926 /* Vector VMVN immediate to vector. */
2927 {ARM_FEATURE_COPROC (FPU_MVE),
2928 MVE_VMVN_IMM,
2929 0xef800070, 0xefb810f0,
2930 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2931
2932 /* Vector VMVN register. */
2933 {ARM_FEATURE_COPROC (FPU_MVE),
2934 MVE_VMVN_REG,
2935 0xffb005c0, 0xffbf1fd1,
2936 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2937
2938 /* Vector VNEG floating point. */
2939 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2940 MVE_VNEG_FP,
2941 0xffb107c0, 0xffb31fd1,
2942 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2943
2944 /* Vector VNEG. */
2945 {ARM_FEATURE_COPROC (FPU_MVE),
2946 MVE_VNEG_VEC,
2947 0xffb103c0, 0xffb31fd1,
2948 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2949
2950 /* Vector VORN, vector bitwise or not. */
2951 {ARM_FEATURE_COPROC (FPU_MVE),
2952 MVE_VORN,
2953 0xef300150, 0xffb11f51,
2954 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2955
2956 /* Vector VORR register. */
2957 {ARM_FEATURE_COPROC (FPU_MVE),
2958 MVE_VORR_REG,
2959 0xef200150, 0xffb11f51,
2960 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2961
2962 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
2963 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
2964 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
2965 array. */
2966
2967 {ARM_FEATURE_COPROC (FPU_MVE),
2968 MVE_VMOV_VEC_TO_VEC,
2969 0xef200150, 0xffb11f51,
2970 "vmov%v\t%13-15,22Q, %17-19,7Q"},
2971
2972 /* Vector VQDMULL T1 variant. */
2973 {ARM_FEATURE_COPROC (FPU_MVE),
2974 MVE_VQDMULL_T1,
2975 0xee300f01, 0xefb10f51,
2976 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2977
2978 /* Vector VPNOT. */
2979 {ARM_FEATURE_COPROC (FPU_MVE),
2980 MVE_VPNOT,
2981 0xfe310f4d, 0xffffffff,
2982 "vpnot%v"},
2983
2984 /* Vector VPSEL. */
2985 {ARM_FEATURE_COPROC (FPU_MVE),
2986 MVE_VPSEL,
2987 0xfe310f01, 0xffb11f51,
2988 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2989
2990 /* Vector VQABS. */
2991 {ARM_FEATURE_COPROC (FPU_MVE),
2992 MVE_VQABS,
2993 0xffb00740, 0xffb31fd1,
2994 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2995
2996 /* Vector VQADD T1 variant. */
2997 {ARM_FEATURE_COPROC (FPU_MVE),
2998 MVE_VQADD_T1,
2999 0xef000050, 0xef811f51,
3000 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3001
3002 /* Vector VQADD T2 variant. */
3003 {ARM_FEATURE_COPROC (FPU_MVE),
3004 MVE_VQADD_T2,
3005 0xee000f60, 0xef811f70,
3006 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3007
3008 /* Vector VQDMULL T2 variant. */
3009 {ARM_FEATURE_COPROC (FPU_MVE),
3010 MVE_VQDMULL_T2,
3011 0xee300f60, 0xefb10f70,
3012 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3013
3014 /* Vector VQMOVN. */
3015 {ARM_FEATURE_COPROC (FPU_MVE),
3016 MVE_VQMOVN,
3017 0xee330e01, 0xefb30fd1,
3018 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3019
3020 /* Vector VQMOVUN. */
3021 {ARM_FEATURE_COPROC (FPU_MVE),
3022 MVE_VQMOVUN,
3023 0xee310e81, 0xffb30fd1,
3024 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3025
3026 /* Vector VQDMLADH. */
3027 {ARM_FEATURE_COPROC (FPU_MVE),
3028 MVE_VQDMLADH,
3029 0xee000e00, 0xff810f51,
3030 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3031
3032 /* Vector VQRDMLADH. */
3033 {ARM_FEATURE_COPROC (FPU_MVE),
3034 MVE_VQRDMLADH,
3035 0xee000e01, 0xff810f51,
3036 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3037
3038 /* Vector VQDMLAH. */
3039 {ARM_FEATURE_COPROC (FPU_MVE),
3040 MVE_VQDMLAH,
3041 0xee000e60, 0xff811f70,
3042 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3043
3044 /* Vector VQRDMLAH. */
3045 {ARM_FEATURE_COPROC (FPU_MVE),
3046 MVE_VQRDMLAH,
3047 0xee000e40, 0xff811f70,
3048 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3049
3050 /* Vector VQDMLASH. */
3051 {ARM_FEATURE_COPROC (FPU_MVE),
3052 MVE_VQDMLASH,
3053 0xee001e60, 0xff811f70,
3054 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3055
3056 /* Vector VQRDMLASH. */
3057 {ARM_FEATURE_COPROC (FPU_MVE),
3058 MVE_VQRDMLASH,
3059 0xee001e40, 0xff811f70,
3060 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3061
3062 /* Vector VQDMLSDH. */
3063 {ARM_FEATURE_COPROC (FPU_MVE),
3064 MVE_VQDMLSDH,
3065 0xfe000e00, 0xff810f51,
3066 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3067
3068 /* Vector VQRDMLSDH. */
3069 {ARM_FEATURE_COPROC (FPU_MVE),
3070 MVE_VQRDMLSDH,
3071 0xfe000e01, 0xff810f51,
3072 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3073
3074 /* Vector VQDMULH T1 variant. */
3075 {ARM_FEATURE_COPROC (FPU_MVE),
3076 MVE_VQDMULH_T1,
3077 0xef000b40, 0xff811f51,
3078 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3079
3080 /* Vector VQRDMULH T2 variant. */
3081 {ARM_FEATURE_COPROC (FPU_MVE),
3082 MVE_VQRDMULH_T2,
3083 0xff000b40, 0xff811f51,
3084 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3085
3086 /* Vector VQDMULH T3 variant. */
3087 {ARM_FEATURE_COPROC (FPU_MVE),
3088 MVE_VQDMULH_T3,
3089 0xee010e60, 0xff811f70,
3090 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3091
3092 /* Vector VQRDMULH T4 variant. */
3093 {ARM_FEATURE_COPROC (FPU_MVE),
3094 MVE_VQRDMULH_T4,
3095 0xfe010e60, 0xff811f70,
3096 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3097
3098 /* Vector VQNEG. */
3099 {ARM_FEATURE_COPROC (FPU_MVE),
3100 MVE_VQNEG,
3101 0xffb007c0, 0xffb31fd1,
3102 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3103
3104 /* Vector VQRSHL T1 variant. */
3105 {ARM_FEATURE_COPROC (FPU_MVE),
3106 MVE_VQRSHL_T1,
3107 0xef000550, 0xef811f51,
3108 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3109
3110 /* Vector VQRSHL T2 variant. */
3111 {ARM_FEATURE_COPROC (FPU_MVE),
3112 MVE_VQRSHL_T2,
3113 0xee331ee0, 0xefb31ff0,
3114 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3115
3116 /* Vector VQRSHRN. */
3117 {ARM_FEATURE_COPROC (FPU_MVE),
3118 MVE_VQRSHRN,
3119 0xee800f41, 0xefa00fd1,
3120 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3121
3122 /* Vector VQRSHRUN. */
3123 {ARM_FEATURE_COPROC (FPU_MVE),
3124 MVE_VQRSHRUN,
3125 0xfe800fc0, 0xffa00fd1,
3126 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3127
3128 /* Vector VQSHL T1 Variant. */
3129 {ARM_FEATURE_COPROC (FPU_MVE),
3130 MVE_VQSHL_T1,
3131 0xee311ee0, 0xefb31ff0,
3132 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3133
3134 /* Vector VQSHL T4 Variant. */
3135 {ARM_FEATURE_COPROC (FPU_MVE),
3136 MVE_VQSHL_T4,
3137 0xef000450, 0xef811f51,
3138 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3139
3140 /* Vector VQSHRN. */
3141 {ARM_FEATURE_COPROC (FPU_MVE),
3142 MVE_VQSHRN,
3143 0xee800f40, 0xefa00fd1,
3144 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3145
3146 /* Vector VQSHRUN. */
3147 {ARM_FEATURE_COPROC (FPU_MVE),
3148 MVE_VQSHRUN,
3149 0xee800fc0, 0xffa00fd1,
3150 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3151
3152 /* Vector VQSUB T1 Variant. */
3153 {ARM_FEATURE_COPROC (FPU_MVE),
3154 MVE_VQSUB_T1,
3155 0xef000250, 0xef811f51,
3156 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3157
3158 /* Vector VQSUB T2 Variant. */
3159 {ARM_FEATURE_COPROC (FPU_MVE),
3160 MVE_VQSUB_T2,
3161 0xee001f60, 0xef811f70,
3162 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3163
3164 /* Vector VREV16. */
3165 {ARM_FEATURE_COPROC (FPU_MVE),
3166 MVE_VREV16,
3167 0xffb00140, 0xffb31fd1,
3168 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3169
3170 /* Vector VREV32. */
3171 {ARM_FEATURE_COPROC (FPU_MVE),
3172 MVE_VREV32,
3173 0xffb000c0, 0xffb31fd1,
3174 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3175
3176 /* Vector VREV64. */
3177 {ARM_FEATURE_COPROC (FPU_MVE),
3178 MVE_VREV64,
3179 0xffb00040, 0xffb31fd1,
3180 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3181
3182 /* Vector VRINT floating point. */
3183 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3184 MVE_VRINT_FP,
3185 0xffb20440, 0xffb31c51,
3186 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3187
3188 /* Vector VRMLALDAVH. */
3189 {ARM_FEATURE_COPROC (FPU_MVE),
3190 MVE_VRMLALDAVH,
3191 0xee800f00, 0xef811f51,
3192 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3193
3194 /* Vector VRMLALDAVH. */
3195 {ARM_FEATURE_COPROC (FPU_MVE),
3196 MVE_VRMLALDAVH,
3197 0xee801f00, 0xef811f51,
3198 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3199
3200 /* Vector VRSHL T1 Variant. */
3201 {ARM_FEATURE_COPROC (FPU_MVE),
3202 MVE_VRSHL_T1,
3203 0xef000540, 0xef811f51,
3204 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3205
3206 /* Vector VRSHL T2 Variant. */
3207 {ARM_FEATURE_COPROC (FPU_MVE),
3208 MVE_VRSHL_T2,
3209 0xee331e60, 0xefb31ff0,
3210 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3211
3212 /* Vector VRSHRN. */
3213 {ARM_FEATURE_COPROC (FPU_MVE),
3214 MVE_VRSHRN,
3215 0xfe800fc1, 0xffa00fd1,
3216 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3217
3218 /* Vector VSBC. */
3219 {ARM_FEATURE_COPROC (FPU_MVE),
3220 MVE_VSBC,
3221 0xfe300f00, 0xffb10f51,
3222 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3223
3224 /* Vector VSHL T2 Variant. */
3225 {ARM_FEATURE_COPROC (FPU_MVE),
3226 MVE_VSHL_T2,
3227 0xee311e60, 0xefb31ff0,
3228 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3229
3230 /* Vector VSHL T3 Variant. */
3231 {ARM_FEATURE_COPROC (FPU_MVE),
3232 MVE_VSHL_T3,
3233 0xef000440, 0xef811f51,
3234 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3235
3236 /* Vector VSHLC. */
3237 {ARM_FEATURE_COPROC (FPU_MVE),
3238 MVE_VSHLC,
3239 0xeea00fc0, 0xffa01ff0,
3240 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3241
3242 /* Vector VSHLL T2 Variant. */
3243 {ARM_FEATURE_COPROC (FPU_MVE),
3244 MVE_VSHLL_T2,
3245 0xee310e01, 0xefb30fd1,
3246 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3247
3248 /* Vector VSHRN. */
3249 {ARM_FEATURE_COPROC (FPU_MVE),
3250 MVE_VSHRN,
3251 0xee800fc1, 0xffa00fd1,
3252 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3253
3254 /* Vector VST2 no writeback. */
3255 {ARM_FEATURE_COPROC (FPU_MVE),
3256 MVE_VST2,
3257 0xfc801e00, 0xffb01e5f,
3258 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3259
3260 /* Vector VST2 writeback. */
3261 {ARM_FEATURE_COPROC (FPU_MVE),
3262 MVE_VST2,
3263 0xfca01e00, 0xffb01e5f,
3264 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3265
3266 /* Vector VST4 no writeback. */
3267 {ARM_FEATURE_COPROC (FPU_MVE),
3268 MVE_VST4,
3269 0xfc801e01, 0xffb01e1f,
3270 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3271
3272 /* Vector VST4 writeback. */
3273 {ARM_FEATURE_COPROC (FPU_MVE),
3274 MVE_VST4,
3275 0xfca01e01, 0xffb01e1f,
3276 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3277
3278 /* Vector VSTRB scatter store, T1 variant. */
3279 {ARM_FEATURE_COPROC (FPU_MVE),
3280 MVE_VSTRB_SCATTER_T1,
3281 0xec800e00, 0xffb01e50,
3282 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3283
3284 /* Vector VSTRH scatter store, T2 variant. */
3285 {ARM_FEATURE_COPROC (FPU_MVE),
3286 MVE_VSTRH_SCATTER_T2,
3287 0xec800e10, 0xffb01e50,
3288 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3289
3290 /* Vector VSTRW scatter store, T3 variant. */
3291 {ARM_FEATURE_COPROC (FPU_MVE),
3292 MVE_VSTRW_SCATTER_T3,
3293 0xec800e40, 0xffb01e50,
3294 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3295
3296 /* Vector VSTRD scatter store, T4 variant. */
3297 {ARM_FEATURE_COPROC (FPU_MVE),
3298 MVE_VSTRD_SCATTER_T4,
3299 0xec800fd0, 0xffb01fd0,
3300 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3301
3302 /* Vector VSTRW scatter store, T5 variant. */
3303 {ARM_FEATURE_COPROC (FPU_MVE),
3304 MVE_VSTRW_SCATTER_T5,
3305 0xfd001e00, 0xff111f00,
3306 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3307
3308 /* Vector VSTRD scatter store, T6 variant. */
3309 {ARM_FEATURE_COPROC (FPU_MVE),
3310 MVE_VSTRD_SCATTER_T6,
3311 0xfd001f00, 0xff111f00,
3312 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3313
3314 /* Vector VSTRB. */
3315 {ARM_FEATURE_COPROC (FPU_MVE),
3316 MVE_VSTRB_T1,
3317 0xec000e00, 0xfe581e00,
3318 "vstrb%v.%7-8s\t%13-15Q, %d"},
3319
3320 /* Vector VSTRH. */
3321 {ARM_FEATURE_COPROC (FPU_MVE),
3322 MVE_VSTRH_T2,
3323 0xec080e00, 0xfe581e00,
3324 "vstrh%v.%7-8s\t%13-15Q, %d"},
3325
3326 /* Vector VSTRB variant T5. */
3327 {ARM_FEATURE_COPROC (FPU_MVE),
3328 MVE_VSTRB_T5,
3329 0xec001e00, 0xfe101f80,
3330 "vstrb%v.8\t%13-15,22Q, %d"},
3331
3332 /* Vector VSTRH variant T6. */
3333 {ARM_FEATURE_COPROC (FPU_MVE),
3334 MVE_VSTRH_T6,
3335 0xec001e80, 0xfe101f80,
3336 "vstrh%v.16\t%13-15,22Q, %d"},
3337
3338 /* Vector VSTRW variant T7. */
3339 {ARM_FEATURE_COPROC (FPU_MVE),
3340 MVE_VSTRW_T7,
3341 0xec001f00, 0xfe101f80,
3342 "vstrw%v.32\t%13-15,22Q, %d"},
3343
3344 /* Vector VSUB floating point T1 variant. */
3345 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3346 MVE_VSUB_FP_T1,
3347 0xef200d40, 0xffa11f51,
3348 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3349
3350 /* Vector VSUB floating point T2 variant. */
3351 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3352 MVE_VSUB_FP_T2,
3353 0xee301f40, 0xefb11f70,
3354 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3355
3356 /* Vector VSUB T1 variant. */
3357 {ARM_FEATURE_COPROC (FPU_MVE),
3358 MVE_VSUB_VEC_T1,
3359 0xff000840, 0xff811f51,
3360 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3361
3362 /* Vector VSUB T2 variant. */
3363 {ARM_FEATURE_COPROC (FPU_MVE),
3364 MVE_VSUB_VEC_T2,
3365 0xee011f40, 0xff811f70,
3366 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3367
3368 {ARM_FEATURE_COPROC (FPU_MVE),
3369 MVE_ASRLI,
3370 0xea50012f, 0xfff1813f,
3371 "asrl%c\t%17-19l, %9-11h, %j"},
3372
3373 {ARM_FEATURE_COPROC (FPU_MVE),
3374 MVE_ASRL,
3375 0xea50012d, 0xfff101ff,
3376 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3377
3378 {ARM_FEATURE_COPROC (FPU_MVE),
3379 MVE_LSLLI,
3380 0xea50010f, 0xfff1813f,
3381 "lsll%c\t%17-19l, %9-11h, %j"},
3382
3383 {ARM_FEATURE_COPROC (FPU_MVE),
3384 MVE_LSLL,
3385 0xea50010d, 0xfff101ff,
3386 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3387
3388 {ARM_FEATURE_COPROC (FPU_MVE),
3389 MVE_LSRL,
3390 0xea50011f, 0xfff1813f,
3391 "lsrl%c\t%17-19l, %9-11h, %j"},
3392
3393 {ARM_FEATURE_COPROC (FPU_MVE),
3394 MVE_SQRSHRL,
3395 0xea51012d, 0xfff1017f,
3396 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
3397
3398 {ARM_FEATURE_COPROC (FPU_MVE),
3399 MVE_SQRSHR,
3400 0xea500f2d, 0xfff00fff,
3401 "sqrshr%c\t%16-19S, %12-15S"},
3402
3403 {ARM_FEATURE_COPROC (FPU_MVE),
3404 MVE_SQSHLL,
3405 0xea51013f, 0xfff1813f,
3406 "sqshll%c\t%17-19l, %9-11h, %j"},
3407
3408 {ARM_FEATURE_COPROC (FPU_MVE),
3409 MVE_SQSHL,
3410 0xea500f3f, 0xfff08f3f,
3411 "sqshl%c\t%16-19S, %j"},
3412
3413 {ARM_FEATURE_COPROC (FPU_MVE),
3414 MVE_SRSHRL,
3415 0xea51012f, 0xfff1813f,
3416 "srshrl%c\t%17-19l, %9-11h, %j"},
3417
3418 {ARM_FEATURE_COPROC (FPU_MVE),
3419 MVE_SRSHR,
3420 0xea500f2f, 0xfff08f3f,
3421 "srshr%c\t%16-19S, %j"},
3422
3423 {ARM_FEATURE_COPROC (FPU_MVE),
3424 MVE_UQRSHLL,
3425 0xea51010d, 0xfff1017f,
3426 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
3427
3428 {ARM_FEATURE_COPROC (FPU_MVE),
3429 MVE_UQRSHL,
3430 0xea500f0d, 0xfff00fff,
3431 "uqrshl%c\t%16-19S, %12-15S"},
3432
3433 {ARM_FEATURE_COPROC (FPU_MVE),
3434 MVE_UQSHLL,
3435 0xea51010f, 0xfff1813f,
3436 "uqshll%c\t%17-19l, %9-11h, %j"},
3437
3438 {ARM_FEATURE_COPROC (FPU_MVE),
3439 MVE_UQSHL,
3440 0xea500f0f, 0xfff08f3f,
3441 "uqshl%c\t%16-19S, %j"},
3442
3443 {ARM_FEATURE_COPROC (FPU_MVE),
3444 MVE_URSHRL,
3445 0xea51011f, 0xfff1813f,
3446 "urshrl%c\t%17-19l, %9-11h, %j"},
3447
3448 {ARM_FEATURE_COPROC (FPU_MVE),
3449 MVE_URSHR,
3450 0xea500f1f, 0xfff08f3f,
3451 "urshr%c\t%16-19S, %j"},
3452
3453 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3454 MVE_CSINC,
3455 0xea509000, 0xfff0f000,
3456 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3457
3458 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3459 MVE_CSINV,
3460 0xea50a000, 0xfff0f000,
3461 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3462
3463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3464 MVE_CSET,
3465 0xea5f900f, 0xfffff00f,
3466 "cset\t%8-11S, %4-7C"},
3467
3468 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3469 MVE_CSETM,
3470 0xea5fa00f, 0xfffff00f,
3471 "csetm\t%8-11S, %4-7C"},
3472
3473 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3474 MVE_CSEL,
3475 0xea508000, 0xfff0f000,
3476 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3477
3478 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3479 MVE_CSNEG,
3480 0xea50b000, 0xfff0f000,
3481 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3482
3483 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3484 MVE_CINC,
3485 0xea509000, 0xfff0f000,
3486 "cinc\t%8-11S, %16-19Z, %4-7C"},
3487
3488 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3489 MVE_CINV,
3490 0xea50a000, 0xfff0f000,
3491 "cinv\t%8-11S, %16-19Z, %4-7C"},
3492
3493 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3494 MVE_CNEG,
3495 0xea50b000, 0xfff0f000,
3496 "cneg\t%8-11S, %16-19Z, %4-7C"},
3497
3498 {ARM_FEATURE_CORE_LOW (0),
3499 MVE_NONE,
3500 0x00000000, 0x00000000, 0}
3501 };
3502
3503 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3504 ordered: they must be searched linearly from the top to obtain a correct
3505 match. */
3506
3507 /* print_insn_arm recognizes the following format control codes:
3508
3509 %% %
3510
3511 %a print address for ldr/str instruction
3512 %s print address for ldr/str halfword/signextend instruction
3513 %S like %s but allow UNPREDICTABLE addressing
3514 %b print branch destination
3515 %c print condition code (always bits 28-31)
3516 %m print register mask for ldm/stm instruction
3517 %o print operand2 (immediate or register + shift)
3518 %p print 'p' iff bits 12-15 are 15
3519 %t print 't' iff bit 21 set and bit 24 clear
3520 %B print arm BLX(1) destination
3521 %C print the PSR sub type.
3522 %U print barrier type.
3523 %P print address for pli instruction.
3524
3525 %<bitfield>r print as an ARM register
3526 %<bitfield>T print as an ARM register + 1
3527 %<bitfield>R as %r but r15 is UNPREDICTABLE
3528 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3529 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3530 %<bitfield>d print the bitfield in decimal
3531 %<bitfield>W print the bitfield plus one in decimal
3532 %<bitfield>x print the bitfield in hex
3533 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
3534
3535 %<bitfield>'c print specified char iff bitfield is all ones
3536 %<bitfield>`c print specified char iff bitfield is all zeroes
3537 %<bitfield>?ab... select from array of values in big endian order
3538
3539 %e print arm SMI operand (bits 0..7,8..19).
3540 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
3541 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3542 %R print the SPSR/CPSR or banked register of an MRS. */
3543
3544 static const struct opcode32 arm_opcodes[] =
3545 {
3546 /* ARM instructions. */
3547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3548 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3550 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3551
3552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3553 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3555 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3557 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3559 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3561 0x00800090, 0x0fa000f0,
3562 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3564 0x00a00090, 0x0fa000f0,
3565 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3566
3567 /* V8.2 RAS extension instructions. */
3568 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3569 0xe320f010, 0xffffffff, "esb"},
3570
3571 /* V8 instructions. */
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3573 0x0320f005, 0x0fffffff, "sevl"},
3574 /* Defined in V8 but is in NOP space so available to all arch. */
3575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3576 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
3577 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
3578 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3579 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3580 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3582 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3584 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3585 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3586 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3587 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3588 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3589 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3590 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3591 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3592 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3593 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3594 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3595 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3596 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3597 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3598 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3599 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3600 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3601 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3602 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3603 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3604 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3605 /* CRC32 instructions. */
3606 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3607 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3608 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3609 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3610 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3611 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3612 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3613 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3614 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3615 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3616 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3617 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3618
3619 /* Privileged Access Never extension instructions. */
3620 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3621 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3622
3623 /* Virtualization Extension instructions. */
3624 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3625 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3626
3627 /* Integer Divide Extension instructions. */
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3629 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3631 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3632
3633 /* MP Extension instructions. */
3634 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3635
3636 /* Speculation Barriers. */
3637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3640
3641 /* V7 instructions. */
3642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3650 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3651
3652 /* ARM V6T2 instructions. */
3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3654 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3656 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3658 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3660 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3661
3662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3663 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3665 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3666
3667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3668 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3669 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3670 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3672 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3674 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3675
3676 /* ARM Security extension instructions. */
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3678 0x01600070, 0x0ff000f0, "smc%c\t%e"},
3679
3680 /* ARM V6K instructions. */
3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3682 0xf57ff01f, 0xffffffff, "clrex"},
3683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3684 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3686 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3688 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3690 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3692 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3694 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3695
3696 /* ARMv8.5-A instructions. */
3697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3698
3699 /* ARM V6K NOP hints. */
3700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3701 0x0320f001, 0x0fffffff, "yield%c"},
3702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3703 0x0320f002, 0x0fffffff, "wfe%c"},
3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3705 0x0320f003, 0x0fffffff, "wfi%c"},
3706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3707 0x0320f004, 0x0fffffff, "sev%c"},
3708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3709 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3710
3711 /* ARM V6 instructions. */
3712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3713 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3715 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3717 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3719 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3721 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3723 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3725 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3727 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3729 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3731 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3733 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3735 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3737 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3739 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3741 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3743 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3745 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3747 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3749 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3751 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3753 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3755 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3757 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3759 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3761 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3763 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3765 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3767 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3769 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3771 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3773 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3775 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3777 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3779 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3781 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3783 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3785 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3787 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3789 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3791 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3793 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3795 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3797 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3799 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3801 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3803 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3805 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3807 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3809 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3811 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3813 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3815 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3817 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3819 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3821 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3823 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3825 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3827 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3829 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3831 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3833 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3835 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3837 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3839 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3841 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3843 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3845 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3847 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3849 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3851 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3853 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3855 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3857 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3859 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3861 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3863 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3865 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3867 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3869 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3871 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3873 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3875 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3877 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3879 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3881 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3883 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3885 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3887 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3889 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3891 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3893 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3895 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3897 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3899 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3901 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3903 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3905 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3907 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3909 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3911 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3913 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3915 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3917 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3919 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3921 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3923 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3925 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3927 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3929 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3931 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3933 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3935 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3937 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3939 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3941 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3943 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3945 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3947 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3949 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3951 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3953 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3955 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
3956
3957 /* V5J instruction. */
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3959 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3960
3961 /* V5 Instructions. */
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3963 0xe1200070, 0xfff000f0,
3964 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3966 0xfa000000, 0xfe000000, "blx\t%B"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3968 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3970 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3971
3972 /* V5E "El Segundo" Instructions. */
3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3974 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3976 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3978 0xf450f000, 0xfc70f000, "pld\t%a"},
3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3980 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3982 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3984 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3986 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3987
3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3989 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3991 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3992
3993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3994 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3996 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3998 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4000 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4001
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4003 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4005 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4007 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4009 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4010
4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4012 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4014 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4015
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4017 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4019 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4021 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4023 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
4024
4025 /* ARM Instructions. */
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4027 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4028
4029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4030 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4032 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4034 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4036 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4038 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4040 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4041
4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4043 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4045 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4047 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4049 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4050
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4052 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4054 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4056 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4058 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4059
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4061 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4063 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4065 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4066
4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4068 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4070 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4072 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4073
4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4075 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4077 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4079 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4080
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4082 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4084 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4086 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4087
4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4089 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4091 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4093 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4094
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4096 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4098 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4100 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4101
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4103 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4105 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4107 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4108
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4110 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4112 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4114 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4115
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4117 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4119 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4121 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4122
4123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4124 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4126 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4128 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4129
4130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4131 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4133 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4135 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
4136
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4138 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4140 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4142 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4143
4144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4145 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4147 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4149 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4150
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4152 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4154 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4156 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4157
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4161 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4163 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4165 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4167 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4169 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4171 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4172
4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4174 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4176 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4178 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4179
4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4181 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4183 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4185 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4186
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4188 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4190 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4191
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4193 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4194
4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4196 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4198 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4199
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4201 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4203 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4205 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4207 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4209 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4211 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4213 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4215 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4217 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4219 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4221 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4223 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4225 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4227 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4229 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4231 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4233 0x092d0000, 0x0fff0000, "push%c\t%m"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4235 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4237 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4238
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4240 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4242 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4244 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4246 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4248 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4250 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4252 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4254 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4256 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4258 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4260 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4262 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4264 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4266 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4268 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4270 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4272 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4274 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4276 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4277
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4279 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4281 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4282
4283 /* The rest. */
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4285 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4287 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4288 {ARM_FEATURE_CORE_LOW (0),
4289 0x00000000, 0x00000000, 0}
4290 };
4291
4292 /* print_insn_thumb16 recognizes the following format control codes:
4293
4294 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4295 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4296 %<bitfield>I print bitfield as a signed decimal
4297 (top bit of range being the sign bit)
4298 %N print Thumb register mask (with LR)
4299 %O print Thumb register mask (with PC)
4300 %M print Thumb register mask
4301 %b print CZB's 6-bit unsigned branch destination
4302 %s print Thumb right-shift immediate (6..10; 0 == 32).
4303 %c print the condition code
4304 %C print the condition code, or "s" if not conditional
4305 %x print warning if conditional an not at end of IT block"
4306 %X print "\t; unpredictable <IT:code>" if conditional
4307 %I print IT instruction suffix and operands
4308 %W print Thumb Writeback indicator for LDMIA
4309 %<bitfield>r print bitfield as an ARM register
4310 %<bitfield>d print bitfield as a decimal
4311 %<bitfield>H print (bitfield * 2) as a decimal
4312 %<bitfield>W print (bitfield * 4) as a decimal
4313 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4314 %<bitfield>B print Thumb branch destination (signed displacement)
4315 %<bitfield>c print bitfield as a condition code
4316 %<bitnum>'c print specified char iff bit is one
4317 %<bitnum>?ab print a if bit is one else print b. */
4318
4319 static const struct opcode16 thumb_opcodes[] =
4320 {
4321 /* Thumb instructions. */
4322
4323 /* ARMv8-M Security Extensions instructions. */
4324 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
4325 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
4326
4327 /* ARM V8 instructions. */
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
4330 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
4331
4332 /* ARM V6K no-argument instructions. */
4333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4339
4340 /* ARM V6T2 instructions. */
4341 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4342 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4343 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4344 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
4346
4347 /* ARM V6. */
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4359
4360 /* ARM V5 ISA extends Thumb. */
4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4362 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
4363 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4365 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
4366 /* ARM V4T ISA (Thumb v1). */
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4368 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
4369 /* Format 4. */
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4386 /* format 13 */
4387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
4389 /* format 5 */
4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4394 /* format 14 */
4395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
4397 /* format 2 */
4398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4399 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4401 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4403 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4405 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
4406 /* format 8 */
4407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4408 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4410 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4412 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4413 /* format 7 */
4414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4415 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4417 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4418 /* format 1 */
4419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4421 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4424 /* format 3 */
4425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
4429 /* format 6 */
4430 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4432 0x4800, 0xF800,
4433 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
4434 /* format 9 */
4435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4436 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4438 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4440 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4442 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
4443 /* format 10 */
4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4445 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4447 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
4448 /* format 11 */
4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4450 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4452 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
4453 /* format 12 */
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4455 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4457 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
4458 /* format 15 */
4459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4461 /* format 17 */
4462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4463 /* format 16 */
4464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4467 /* format 18 */
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4469
4470 /* The E800 .. FFFF range is unconditionally redirected to the
4471 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4472 are processed via that table. Thus, we can never encounter a
4473 bare "second half of BL/BLX(1)" instruction here. */
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4475 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4476 };
4477
4478 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
4479 We adopt the convention that hw1 is the high 16 bits of .value and
4480 .mask, hw2 the low 16 bits.
4481
4482 print_insn_thumb32 recognizes the following format control codes:
4483
4484 %% %
4485
4486 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4487 %M print a modified 12-bit immediate (same location)
4488 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4489 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4490 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
4491 %S print a possibly-shifted Rm
4492
4493 %L print address for a ldrd/strd instruction
4494 %a print the address of a plain load/store
4495 %w print the width and signedness of a core load/store
4496 %m print register mask for ldm/stm
4497 %n print register mask for clrm
4498
4499 %E print the lsb and width fields of a bfc/bfi instruction
4500 %F print the lsb and width fields of a sbfx/ubfx instruction
4501 %G print a fallback offset for Branch Future instructions
4502 %W print an offset for BF instruction
4503 %Y print an offset for BFL instruction
4504 %Z print an offset for BFCSEL instruction
4505 %Q print an offset for Low Overhead Loop instructions
4506 %P print an offset for Low Overhead Loop end instructions
4507 %b print a conditional branch offset
4508 %B print an unconditional branch offset
4509 %s print the shift field of an SSAT instruction
4510 %R print the rotation field of an SXT instruction
4511 %U print barrier type.
4512 %P print address for pli instruction.
4513 %c print the condition code
4514 %x print warning if conditional an not at end of IT block"
4515 %X print "\t; unpredictable <IT:code>" if conditional
4516
4517 %<bitfield>d print bitfield in decimal
4518 %<bitfield>D print bitfield plus one in decimal
4519 %<bitfield>W print bitfield*4 in decimal
4520 %<bitfield>r print bitfield as an ARM register
4521 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4522 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4523 %<bitfield>c print bitfield as a condition code
4524
4525 %<bitfield>'c print specified char iff bitfield is all ones
4526 %<bitfield>`c print specified char iff bitfield is all zeroes
4527 %<bitfield>?ab... select from array of values in big endian order
4528
4529 With one exception at the bottom (done because BL and BLX(1) need
4530 to come dead last), this table was machine-sorted first in
4531 decreasing order of number of bits set in the mask, then in
4532 increasing numeric order of mask, then in increasing numeric order
4533 of opcode. This order is not the clearest for a human reader, but
4534 is guaranteed never to catch a special-case bit pattern with a more
4535 general mask, which is important, because this instruction encoding
4536 makes heavy use of special-case bit patterns. */
4537 static const struct opcode32 thumb32_opcodes[] =
4538 {
4539 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4540 instructions. */
4541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4542 0xf00fe001, 0xffffffff, "lctp%c"},
4543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4544 0xf02fc001, 0xfffff001, "le\t%P"},
4545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4546 0xf00fc001, 0xfffff001, "le\tlr, %P"},
4547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4548 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4550 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4551 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4552 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4554 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4556 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
4557
4558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4559 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4561 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4562 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4563 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4564 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4565 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4566 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4567 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4568
4569 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4570 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4571
4572 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4573 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4575 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4576 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4577 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4578 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4579 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4581 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4582
4583 /* ARM V8.2 RAS extension instructions. */
4584 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
4585 0xf3af8010, 0xffffffff, "esb"},
4586
4587 /* V8 instructions. */
4588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4589 0xf3af8005, 0xffffffff, "sevl%c.w"},
4590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4591 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4593 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4595 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4597 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4599 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4601 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4603 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4605 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4607 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4609 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4611 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4613 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4615 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4617 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4619 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4620
4621 /* CRC32 instructions. */
4622 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4623 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4624 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4625 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4626 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4627 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4628 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4629 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4630 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4631 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4632 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4633 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4634
4635 /* Speculation Barriers. */
4636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4639
4640 /* V7 instructions. */
4641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4648 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4649 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4650 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4651 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4652
4653 /* Virtualization Extension instructions. */
4654 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4655 /* We skip ERET as that is SUBS pc, lr, #0. */
4656
4657 /* MP Extension instructions. */
4658 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
4659
4660 /* Security extension instructions. */
4661 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4662
4663 /* ARMv8.5-A instructions. */
4664 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4665
4666 /* Instructions defined in the basic V6T2 set. */
4667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4673 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4675
4676 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4677 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4679 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4681 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4683 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4685 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4687 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4689 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4691 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4693 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4695 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4697 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4699 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4701 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4703 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4704 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4705 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4707 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4709 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4711 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4713 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4715 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4717 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4719 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4721 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4723 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4724 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4725 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4727 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4729 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4731 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4733 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4735 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4737 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4739 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4741 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4743 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4745 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4747 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4749 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4751 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4753 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4755 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4757 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4759 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4761 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4763 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4765 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4767 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4769 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4771 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4773 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4775 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4777 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4779 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4781 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4783 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4785 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4787 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4789 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4791 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4793 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4795 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4797 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4799 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4801 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4803 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4805 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4807 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4809 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4811 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4813 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4815 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4817 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4819 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4821 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4823 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4825 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4827 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4829 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4831 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4832 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4833 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4835 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4837 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4839 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4841 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4843 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4845 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4847 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4849 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4851 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4853 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4855 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4857 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4859 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4861 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4863 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4865 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4867 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4869 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4871 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4873 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4875 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4877 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4879 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4881 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4883 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4885 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4887 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4889 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4891 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4893 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4895 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4897 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4899 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4900 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4901 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4903 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4905 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4907 0xf810f000, 0xff70f000, "pld%c\t%a"},
4908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4909 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4911 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4913 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4915 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4917 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4919 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4921 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4923 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4925 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4927 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4929 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4931 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4933 0xfb100000, 0xfff000c0,
4934 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4936 0xfbc00080, 0xfff000c0,
4937 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4939 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4941 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4943 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
4944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4945 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4947 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4948 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4949 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4951 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4952 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4953 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4955 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4957 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4959 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4961 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4963 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4965 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4967 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4969 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4971 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4973 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4974 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4975 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4977 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4979 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4981 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4983 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4985 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4987 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4989 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4991 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4993 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4995 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4997 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4999 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5001 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5003 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5005 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5007 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5009 0xe9400000, 0xff500000,
5010 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5012 0xe9500000, 0xff500000,
5013 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5015 0xe8600000, 0xff700000,
5016 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5018 0xe8700000, 0xff700000,
5019 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5021 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5023 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
5024
5025 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
5026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5027 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5029 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5031 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5033 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
5034
5035 /* These have been 32-bit since the invention of Thumb. */
5036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5037 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5039 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
5040
5041 /* Fallback. */
5042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5043 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5044 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
5045 };
5046
5047 static const char *const arm_conditional[] =
5048 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
5049 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
5050
5051 static const char *const arm_fp_const[] =
5052 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5053
5054 static const char *const arm_shift[] =
5055 {"lsl", "lsr", "asr", "ror"};
5056
5057 typedef struct
5058 {
5059 const char *name;
5060 const char *description;
5061 const char *reg_names[16];
5062 }
5063 arm_regname;
5064
5065 static const arm_regname regnames[] =
5066 {
5067 { "reg-names-raw", N_("Select raw register names"),
5068 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
5069 { "reg-names-gcc", N_("Select register names used by GCC"),
5070 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
5071 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
5072 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
5073 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5074 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5075 { "reg-names-apcs", N_("Select register names used in the APCS"),
5076 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
5077 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
5078 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
5079 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5080 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
5081 };
5082
5083 static const char *const iwmmxt_wwnames[] =
5084 {"b", "h", "w", "d"};
5085
5086 static const char *const iwmmxt_wwssnames[] =
5087 {"b", "bus", "bc", "bss",
5088 "h", "hus", "hc", "hss",
5089 "w", "wus", "wc", "wss",
5090 "d", "dus", "dc", "dss"
5091 };
5092
5093 static const char *const iwmmxt_regnames[] =
5094 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5095 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5096 };
5097
5098 static const char *const iwmmxt_cregnames[] =
5099 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5100 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5101 };
5102
5103 static const char *const vec_condnames[] =
5104 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5105 };
5106
5107 static const char *const mve_predicatenames[] =
5108 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5109 "eee", "ee", "eet", "e", "ett", "et", "ete"
5110 };
5111
5112 /* Names for 2-bit size field for mve vector isntructions. */
5113 static const char *const mve_vec_sizename[] =
5114 { "8", "16", "32", "64"};
5115
5116 /* Indicates whether we are processing a then predicate,
5117 else predicate or none at all. */
5118 enum vpt_pred_state
5119 {
5120 PRED_NONE,
5121 PRED_THEN,
5122 PRED_ELSE
5123 };
5124
5125 /* Information used to process a vpt block and subsequent instructions. */
5126 struct vpt_block
5127 {
5128 /* Are we in a vpt block. */
5129 bfd_boolean in_vpt_block;
5130
5131 /* Next predicate state if in vpt block. */
5132 enum vpt_pred_state next_pred_state;
5133
5134 /* Mask from vpt/vpst instruction. */
5135 long predicate_mask;
5136
5137 /* Instruction number in vpt block. */
5138 long current_insn_num;
5139
5140 /* Number of instructions in vpt block.. */
5141 long num_pred_insn;
5142 };
5143
5144 static struct vpt_block vpt_block_state =
5145 {
5146 FALSE,
5147 PRED_NONE,
5148 0,
5149 0,
5150 0
5151 };
5152
5153 /* Default to GCC register name set. */
5154 static unsigned int regname_selected = 1;
5155
5156 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
5157 #define arm_regnames regnames[regname_selected].reg_names
5158
5159 static bfd_boolean force_thumb = FALSE;
5160
5161 /* Current IT instruction state. This contains the same state as the IT
5162 bits in the CPSR. */
5163 static unsigned int ifthen_state;
5164 /* IT state for the next instruction. */
5165 static unsigned int ifthen_next_state;
5166 /* The address of the insn for which the IT state is valid. */
5167 static bfd_vma ifthen_address;
5168 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5169 /* Indicates that the current Conditional state is unconditional or outside
5170 an IT block. */
5171 #define COND_UNCOND 16
5172
5173 \f
5174 /* Functions. */
5175 /* Extract the predicate mask for a VPT or VPST instruction.
5176 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5177
5178 static long
5179 mve_extract_pred_mask (long given)
5180 {
5181 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5182 }
5183
5184 /* Return the number of instructions in a MVE predicate block. */
5185 static long
5186 num_instructions_vpt_block (long given)
5187 {
5188 long mask = mve_extract_pred_mask (given);
5189 if (mask == 0)
5190 return 0;
5191
5192 if (mask == 8)
5193 return 1;
5194
5195 if ((mask & 7) == 4)
5196 return 2;
5197
5198 if ((mask & 3) == 2)
5199 return 3;
5200
5201 if ((mask & 1) == 1)
5202 return 4;
5203
5204 return 0;
5205 }
5206
5207 static void
5208 mark_outside_vpt_block (void)
5209 {
5210 vpt_block_state.in_vpt_block = FALSE;
5211 vpt_block_state.next_pred_state = PRED_NONE;
5212 vpt_block_state.predicate_mask = 0;
5213 vpt_block_state.current_insn_num = 0;
5214 vpt_block_state.num_pred_insn = 0;
5215 }
5216
5217 static void
5218 mark_inside_vpt_block (long given)
5219 {
5220 vpt_block_state.in_vpt_block = TRUE;
5221 vpt_block_state.next_pred_state = PRED_THEN;
5222 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5223 vpt_block_state.current_insn_num = 0;
5224 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5225 assert (vpt_block_state.num_pred_insn >= 1);
5226 }
5227
5228 static enum vpt_pred_state
5229 invert_next_predicate_state (enum vpt_pred_state astate)
5230 {
5231 if (astate == PRED_THEN)
5232 return PRED_ELSE;
5233 else if (astate == PRED_ELSE)
5234 return PRED_THEN;
5235 else
5236 return PRED_NONE;
5237 }
5238
5239 static enum vpt_pred_state
5240 update_next_predicate_state (void)
5241 {
5242 long pred_mask = vpt_block_state.predicate_mask;
5243 long mask_for_insn = 0;
5244
5245 switch (vpt_block_state.current_insn_num)
5246 {
5247 case 1:
5248 mask_for_insn = 8;
5249 break;
5250
5251 case 2:
5252 mask_for_insn = 4;
5253 break;
5254
5255 case 3:
5256 mask_for_insn = 2;
5257 break;
5258
5259 case 4:
5260 return PRED_NONE;
5261 }
5262
5263 if (pred_mask & mask_for_insn)
5264 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5265 else
5266 return vpt_block_state.next_pred_state;
5267 }
5268
5269 static void
5270 update_vpt_block_state (void)
5271 {
5272 vpt_block_state.current_insn_num++;
5273 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5274 {
5275 /* No more instructions to process in vpt block. */
5276 mark_outside_vpt_block ();
5277 return;
5278 }
5279
5280 vpt_block_state.next_pred_state = update_next_predicate_state ();
5281 }
5282
5283 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5284 Returns pointer to following character of the format string and
5285 fills in *VALUEP and *WIDTHP with the extracted value and number of
5286 bits extracted. WIDTHP can be NULL. */
5287
5288 static const char *
5289 arm_decode_bitfield (const char *ptr,
5290 unsigned long insn,
5291 unsigned long *valuep,
5292 int *widthp)
5293 {
5294 unsigned long value = 0;
5295 int width = 0;
5296
5297 do
5298 {
5299 int start, end;
5300 int bits;
5301
5302 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5303 start = start * 10 + *ptr - '0';
5304 if (*ptr == '-')
5305 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5306 end = end * 10 + *ptr - '0';
5307 else
5308 end = start;
5309 bits = end - start;
5310 if (bits < 0)
5311 abort ();
5312 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5313 width += bits + 1;
5314 }
5315 while (*ptr++ == ',');
5316 *valuep = value;
5317 if (widthp)
5318 *widthp = width;
5319 return ptr - 1;
5320 }
5321
5322 static void
5323 arm_decode_shift (long given, fprintf_ftype func, void *stream,
5324 bfd_boolean print_shift)
5325 {
5326 func (stream, "%s", arm_regnames[given & 0xf]);
5327
5328 if ((given & 0xff0) != 0)
5329 {
5330 if ((given & 0x10) == 0)
5331 {
5332 int amount = (given & 0xf80) >> 7;
5333 int shift = (given & 0x60) >> 5;
5334
5335 if (amount == 0)
5336 {
5337 if (shift == 3)
5338 {
5339 func (stream, ", rrx");
5340 return;
5341 }
5342
5343 amount = 32;
5344 }
5345
5346 if (print_shift)
5347 func (stream, ", %s #%d", arm_shift[shift], amount);
5348 else
5349 func (stream, ", #%d", amount);
5350 }
5351 else if ((given & 0x80) == 0x80)
5352 func (stream, "\t; <illegal shifter operand>");
5353 else if (print_shift)
5354 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5355 arm_regnames[(given & 0xf00) >> 8]);
5356 else
5357 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
5358 }
5359 }
5360
5361 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5362
5363 static bfd_boolean
5364 is_mve_okay_in_it (enum mve_instructions matched_insn)
5365 {
5366 switch (matched_insn)
5367 {
5368 case MVE_VMOV_GP_TO_VEC_LANE:
5369 case MVE_VMOV2_VEC_LANE_TO_GP:
5370 case MVE_VMOV2_GP_TO_VEC_LANE:
5371 case MVE_VMOV_VEC_LANE_TO_GP:
5372 case MVE_LSLL:
5373 case MVE_LSLLI:
5374 case MVE_LSRL:
5375 case MVE_ASRL:
5376 case MVE_ASRLI:
5377 case MVE_SQRSHRL:
5378 case MVE_SQRSHR:
5379 case MVE_UQRSHL:
5380 case MVE_UQRSHLL:
5381 case MVE_UQSHL:
5382 case MVE_UQSHLL:
5383 case MVE_URSHRL:
5384 case MVE_URSHR:
5385 case MVE_SRSHRL:
5386 case MVE_SRSHR:
5387 case MVE_SQSHLL:
5388 case MVE_SQSHL:
5389 return TRUE;
5390 default:
5391 return FALSE;
5392 }
5393 }
5394
5395 static bfd_boolean
5396 is_mve_architecture (struct disassemble_info *info)
5397 {
5398 struct arm_private_data *private_data = info->private_data;
5399 arm_feature_set allowed_arches = private_data->features;
5400
5401 arm_feature_set arm_ext_v8_1m_main
5402 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5403
5404 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5405 && !ARM_CPU_IS_ANY (allowed_arches))
5406 return TRUE;
5407 else
5408 return FALSE;
5409 }
5410
5411 static bfd_boolean
5412 is_vpt_instruction (long given)
5413 {
5414
5415 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5416 if ((given & 0x0040e000) == 0)
5417 return FALSE;
5418
5419 /* VPT floating point T1 variant. */
5420 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5421 /* VPT floating point T2 variant. */
5422 || ((given & 0xefb10f50) == 0xee310f40)
5423 /* VPT vector T1 variant. */
5424 || ((given & 0xff811f51) == 0xfe010f00)
5425 /* VPT vector T2 variant. */
5426 || ((given & 0xff811f51) == 0xfe010f01
5427 && ((given & 0x300000) != 0x300000))
5428 /* VPT vector T3 variant. */
5429 || ((given & 0xff811f50) == 0xfe011f00)
5430 /* VPT vector T4 variant. */
5431 || ((given & 0xff811f70) == 0xfe010f40)
5432 /* VPT vector T5 variant. */
5433 || ((given & 0xff811f70) == 0xfe010f60)
5434 /* VPT vector T6 variant. */
5435 || ((given & 0xff811f50) == 0xfe011f40)
5436 /* VPST vector T variant. */
5437 || ((given & 0xffbf1fff) == 0xfe310f4d))
5438 return TRUE;
5439 else
5440 return FALSE;
5441 }
5442
5443 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5444 and ending bitfield = END. END must be greater than START. */
5445
5446 static unsigned long
5447 arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5448 {
5449 int bits = end - start;
5450
5451 if (bits < 0)
5452 abort ();
5453
5454 return ((given >> start) & ((2ul << bits) - 1));
5455 }
5456
5457 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5458 START:END and START2:END2. END/END2 must be greater than
5459 START/START2. */
5460
5461 static unsigned long
5462 arm_decode_field_multiple (unsigned long given, unsigned int start,
5463 unsigned int end, unsigned int start2,
5464 unsigned int end2)
5465 {
5466 int bits = end - start;
5467 int bits2 = end2 - start2;
5468 unsigned long value = 0;
5469 int width = 0;
5470
5471 if (bits2 < 0)
5472 abort ();
5473
5474 value = arm_decode_field (given, start, end);
5475 width += bits + 1;
5476
5477 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5478 return value;
5479 }
5480
5481 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5482 This helps us decode instructions that change mnemonic depending on specific
5483 operand values/encodings. */
5484
5485 static bfd_boolean
5486 is_mve_encoding_conflict (unsigned long given,
5487 enum mve_instructions matched_insn)
5488 {
5489 switch (matched_insn)
5490 {
5491 case MVE_VPST:
5492 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5493 return TRUE;
5494 else
5495 return FALSE;
5496
5497 case MVE_VPT_FP_T1:
5498 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5499 return TRUE;
5500 if ((arm_decode_field (given, 12, 12) == 0)
5501 && (arm_decode_field (given, 0, 0) == 1))
5502 return TRUE;
5503 return FALSE;
5504
5505 case MVE_VPT_FP_T2:
5506 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5507 return TRUE;
5508 if (arm_decode_field (given, 0, 3) == 0xd)
5509 return TRUE;
5510 return FALSE;
5511
5512 case MVE_VPT_VEC_T1:
5513 case MVE_VPT_VEC_T2:
5514 case MVE_VPT_VEC_T3:
5515 case MVE_VPT_VEC_T4:
5516 case MVE_VPT_VEC_T5:
5517 case MVE_VPT_VEC_T6:
5518 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5519 return TRUE;
5520 if (arm_decode_field (given, 20, 21) == 3)
5521 return TRUE;
5522 return FALSE;
5523
5524 case MVE_VCMP_FP_T1:
5525 if ((arm_decode_field (given, 12, 12) == 0)
5526 && (arm_decode_field (given, 0, 0) == 1))
5527 return TRUE;
5528 else
5529 return FALSE;
5530
5531 case MVE_VCMP_FP_T2:
5532 if (arm_decode_field (given, 0, 3) == 0xd)
5533 return TRUE;
5534 else
5535 return FALSE;
5536
5537 case MVE_VQADD_T2:
5538 case MVE_VQSUB_T2:
5539 case MVE_VMUL_VEC_T2:
5540 case MVE_VMULH:
5541 case MVE_VRMULH:
5542 case MVE_VMLA:
5543 case MVE_VMAX:
5544 case MVE_VMIN:
5545 case MVE_VBRSR:
5546 case MVE_VADD_VEC_T2:
5547 case MVE_VSUB_VEC_T2:
5548 case MVE_VABAV:
5549 case MVE_VQRSHL_T1:
5550 case MVE_VQSHL_T4:
5551 case MVE_VRSHL_T1:
5552 case MVE_VSHL_T3:
5553 case MVE_VCADD_VEC:
5554 case MVE_VHCADD:
5555 case MVE_VDDUP:
5556 case MVE_VIDUP:
5557 case MVE_VQRDMLADH:
5558 case MVE_VQDMLAH:
5559 case MVE_VQRDMLAH:
5560 case MVE_VQDMLASH:
5561 case MVE_VQRDMLASH:
5562 case MVE_VQDMLSDH:
5563 case MVE_VQRDMLSDH:
5564 case MVE_VQDMULH_T3:
5565 case MVE_VQRDMULH_T4:
5566 case MVE_VQDMLADH:
5567 case MVE_VMLAS:
5568 case MVE_VMULL_INT:
5569 case MVE_VHADD_T2:
5570 case MVE_VHSUB_T2:
5571 case MVE_VCMP_VEC_T1:
5572 case MVE_VCMP_VEC_T2:
5573 case MVE_VCMP_VEC_T3:
5574 case MVE_VCMP_VEC_T4:
5575 case MVE_VCMP_VEC_T5:
5576 case MVE_VCMP_VEC_T6:
5577 if (arm_decode_field (given, 20, 21) == 3)
5578 return TRUE;
5579 else
5580 return FALSE;
5581
5582 case MVE_VLD2:
5583 case MVE_VLD4:
5584 case MVE_VST2:
5585 case MVE_VST4:
5586 if (arm_decode_field (given, 7, 8) == 3)
5587 return TRUE;
5588 else
5589 return FALSE;
5590
5591 case MVE_VSTRB_T1:
5592 case MVE_VSTRH_T2:
5593 if ((arm_decode_field (given, 24, 24) == 0)
5594 && (arm_decode_field (given, 21, 21) == 0))
5595 {
5596 return TRUE;
5597 }
5598 else if ((arm_decode_field (given, 7, 8) == 3))
5599 return TRUE;
5600 else
5601 return FALSE;
5602
5603 case MVE_VSTRB_T5:
5604 case MVE_VSTRH_T6:
5605 case MVE_VSTRW_T7:
5606 if ((arm_decode_field (given, 24, 24) == 0)
5607 && (arm_decode_field (given, 21, 21) == 0))
5608 {
5609 return TRUE;
5610 }
5611 else
5612 return FALSE;
5613
5614 case MVE_VCVT_FP_FIX_VEC:
5615 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5616
5617 case MVE_VBIC_IMM:
5618 case MVE_VORR_IMM:
5619 {
5620 unsigned long cmode = arm_decode_field (given, 8, 11);
5621
5622 if ((cmode & 1) == 0)
5623 return TRUE;
5624 else if ((cmode & 0xc) == 0xc)
5625 return TRUE;
5626 else
5627 return FALSE;
5628 }
5629
5630 case MVE_VMVN_IMM:
5631 {
5632 unsigned long cmode = arm_decode_field (given, 8, 11);
5633
5634 if ((cmode & 9) == 1)
5635 return TRUE;
5636 else if ((cmode & 5) == 1)
5637 return TRUE;
5638 else if ((cmode & 0xe) == 0xe)
5639 return TRUE;
5640 else
5641 return FALSE;
5642 }
5643
5644 case MVE_VMOV_IMM_TO_VEC:
5645 if ((arm_decode_field (given, 5, 5) == 1)
5646 && (arm_decode_field (given, 8, 11) != 0xe))
5647 return TRUE;
5648 else
5649 return FALSE;
5650
5651 case MVE_VMOVL:
5652 {
5653 unsigned long size = arm_decode_field (given, 19, 20);
5654 if ((size == 0) || (size == 3))
5655 return TRUE;
5656 else
5657 return FALSE;
5658 }
5659
5660 case MVE_VMAXA:
5661 case MVE_VMINA:
5662 case MVE_VMAXV:
5663 case MVE_VMAXAV:
5664 case MVE_VMINV:
5665 case MVE_VMINAV:
5666 case MVE_VQRSHL_T2:
5667 case MVE_VQSHL_T1:
5668 case MVE_VRSHL_T2:
5669 case MVE_VSHL_T2:
5670 case MVE_VSHLL_T2:
5671 case MVE_VADDV:
5672 case MVE_VMOVN:
5673 case MVE_VQMOVUN:
5674 case MVE_VQMOVN:
5675 if (arm_decode_field (given, 18, 19) == 3)
5676 return TRUE;
5677 else
5678 return FALSE;
5679
5680 case MVE_VMLSLDAV:
5681 case MVE_VRMLSLDAVH:
5682 case MVE_VMLALDAV:
5683 case MVE_VADDLV:
5684 if (arm_decode_field (given, 20, 22) == 7)
5685 return TRUE;
5686 else
5687 return FALSE;
5688
5689 case MVE_VRMLALDAVH:
5690 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5691 return TRUE;
5692 else
5693 return FALSE;
5694
5695 case MVE_VDWDUP:
5696 case MVE_VIWDUP:
5697 if ((arm_decode_field (given, 20, 21) == 3)
5698 || (arm_decode_field (given, 1, 3) == 7))
5699 return TRUE;
5700 else
5701 return FALSE;
5702
5703
5704 case MVE_VSHLL_T1:
5705 if (arm_decode_field (given, 16, 18) == 0)
5706 {
5707 unsigned long sz = arm_decode_field (given, 19, 20);
5708
5709 if ((sz == 1) || (sz == 2))
5710 return TRUE;
5711 else
5712 return FALSE;
5713 }
5714 else
5715 return FALSE;
5716
5717 case MVE_VQSHL_T2:
5718 case MVE_VQSHLU_T3:
5719 case MVE_VRSHR:
5720 case MVE_VSHL_T1:
5721 case MVE_VSHR:
5722 case MVE_VSLI:
5723 case MVE_VSRI:
5724 if (arm_decode_field (given, 19, 21) == 0)
5725 return TRUE;
5726 else
5727 return FALSE;
5728
5729 case MVE_VCTP:
5730 if (arm_decode_field (given, 16, 19) == 0xf)
5731 return TRUE;
5732 else
5733 return FALSE;
5734
5735 case MVE_ASRLI:
5736 case MVE_ASRL:
5737 case MVE_LSLLI:
5738 case MVE_LSLL:
5739 case MVE_LSRL:
5740 case MVE_SQRSHRL:
5741 case MVE_SQSHLL:
5742 case MVE_SRSHRL:
5743 case MVE_UQRSHLL:
5744 case MVE_UQSHLL:
5745 case MVE_URSHRL:
5746 if (arm_decode_field (given, 9, 11) == 0x7)
5747 return TRUE;
5748 else
5749 return FALSE;
5750
5751 case MVE_CSINC:
5752 case MVE_CSINV:
5753 {
5754 unsigned long rm, rn;
5755 rm = arm_decode_field (given, 0, 3);
5756 rn = arm_decode_field (given, 16, 19);
5757 /* CSET/CSETM. */
5758 if (rm == 0xf && rn == 0xf)
5759 return TRUE;
5760 /* CINC/CINV. */
5761 else if (rn == rm && rn != 0xf)
5762 return TRUE;
5763 }
5764 /* Fall through. */
5765 case MVE_CSEL:
5766 case MVE_CSNEG:
5767 if (arm_decode_field (given, 0, 3) == 0xd)
5768 return TRUE;
5769 /* CNEG. */
5770 else if (matched_insn == MVE_CSNEG)
5771 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5772 return TRUE;
5773 return FALSE;
5774
5775 default:
5776 case MVE_VADD_FP_T1:
5777 case MVE_VADD_FP_T2:
5778 case MVE_VADD_VEC_T1:
5779 return FALSE;
5780
5781 }
5782 }
5783
5784 static void
5785 print_mve_vld_str_addr (struct disassemble_info *info,
5786 unsigned long given,
5787 enum mve_instructions matched_insn)
5788 {
5789 void *stream = info->stream;
5790 fprintf_ftype func = info->fprintf_func;
5791
5792 unsigned long p, w, gpr, imm, add, mod_imm;
5793
5794 imm = arm_decode_field (given, 0, 6);
5795 mod_imm = imm;
5796
5797 switch (matched_insn)
5798 {
5799 case MVE_VLDRB_T1:
5800 case MVE_VSTRB_T1:
5801 gpr = arm_decode_field (given, 16, 18);
5802 break;
5803
5804 case MVE_VLDRH_T2:
5805 case MVE_VSTRH_T2:
5806 gpr = arm_decode_field (given, 16, 18);
5807 mod_imm = imm << 1;
5808 break;
5809
5810 case MVE_VLDRH_T6:
5811 case MVE_VSTRH_T6:
5812 gpr = arm_decode_field (given, 16, 19);
5813 mod_imm = imm << 1;
5814 break;
5815
5816 case MVE_VLDRW_T7:
5817 case MVE_VSTRW_T7:
5818 gpr = arm_decode_field (given, 16, 19);
5819 mod_imm = imm << 2;
5820 break;
5821
5822 case MVE_VLDRB_T5:
5823 case MVE_VSTRB_T5:
5824 gpr = arm_decode_field (given, 16, 19);
5825 break;
5826
5827 default:
5828 return;
5829 }
5830
5831 p = arm_decode_field (given, 24, 24);
5832 w = arm_decode_field (given, 21, 21);
5833
5834 add = arm_decode_field (given, 23, 23);
5835
5836 char * add_sub;
5837
5838 /* Don't print anything for '+' as it is implied. */
5839 if (add == 1)
5840 add_sub = "";
5841 else
5842 add_sub = "-";
5843
5844 if (p == 1)
5845 {
5846 /* Offset mode. */
5847 if (w == 0)
5848 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5849 /* Pre-indexed mode. */
5850 else
5851 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5852 }
5853 else if ((p == 0) && (w == 1))
5854 /* Post-index mode. */
5855 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5856 }
5857
5858 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5859 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5860 this encoding is undefined. */
5861
5862 static bfd_boolean
5863 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5864 enum mve_undefined *undefined_code)
5865 {
5866 *undefined_code = UNDEF_NONE;
5867
5868 switch (matched_insn)
5869 {
5870 case MVE_VDUP:
5871 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5872 {
5873 *undefined_code = UNDEF_SIZE_3;
5874 return TRUE;
5875 }
5876 else
5877 return FALSE;
5878
5879 case MVE_VQADD_T1:
5880 case MVE_VQSUB_T1:
5881 case MVE_VMUL_VEC_T1:
5882 case MVE_VABD_VEC:
5883 case MVE_VADD_VEC_T1:
5884 case MVE_VSUB_VEC_T1:
5885 case MVE_VQDMULH_T1:
5886 case MVE_VQRDMULH_T2:
5887 case MVE_VRHADD:
5888 case MVE_VHADD_T1:
5889 case MVE_VHSUB_T1:
5890 if (arm_decode_field (given, 20, 21) == 3)
5891 {
5892 *undefined_code = UNDEF_SIZE_3;
5893 return TRUE;
5894 }
5895 else
5896 return FALSE;
5897
5898 case MVE_VLDRB_T1:
5899 if (arm_decode_field (given, 7, 8) == 3)
5900 {
5901 *undefined_code = UNDEF_SIZE_3;
5902 return TRUE;
5903 }
5904 else
5905 return FALSE;
5906
5907 case MVE_VLDRH_T2:
5908 if (arm_decode_field (given, 7, 8) <= 1)
5909 {
5910 *undefined_code = UNDEF_SIZE_LE_1;
5911 return TRUE;
5912 }
5913 else
5914 return FALSE;
5915
5916 case MVE_VSTRB_T1:
5917 if ((arm_decode_field (given, 7, 8) == 0))
5918 {
5919 *undefined_code = UNDEF_SIZE_0;
5920 return TRUE;
5921 }
5922 else
5923 return FALSE;
5924
5925 case MVE_VSTRH_T2:
5926 if ((arm_decode_field (given, 7, 8) <= 1))
5927 {
5928 *undefined_code = UNDEF_SIZE_LE_1;
5929 return TRUE;
5930 }
5931 else
5932 return FALSE;
5933
5934 case MVE_VLDRB_GATHER_T1:
5935 if (arm_decode_field (given, 7, 8) == 3)
5936 {
5937 *undefined_code = UNDEF_SIZE_3;
5938 return TRUE;
5939 }
5940 else if ((arm_decode_field (given, 28, 28) == 0)
5941 && (arm_decode_field (given, 7, 8) == 0))
5942 {
5943 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5944 return TRUE;
5945 }
5946 else
5947 return FALSE;
5948
5949 case MVE_VLDRH_GATHER_T2:
5950 if (arm_decode_field (given, 7, 8) == 3)
5951 {
5952 *undefined_code = UNDEF_SIZE_3;
5953 return TRUE;
5954 }
5955 else if ((arm_decode_field (given, 28, 28) == 0)
5956 && (arm_decode_field (given, 7, 8) == 1))
5957 {
5958 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5959 return TRUE;
5960 }
5961 else if (arm_decode_field (given, 7, 8) == 0)
5962 {
5963 *undefined_code = UNDEF_SIZE_0;
5964 return TRUE;
5965 }
5966 else
5967 return FALSE;
5968
5969 case MVE_VLDRW_GATHER_T3:
5970 if (arm_decode_field (given, 7, 8) != 2)
5971 {
5972 *undefined_code = UNDEF_SIZE_NOT_2;
5973 return TRUE;
5974 }
5975 else if (arm_decode_field (given, 28, 28) == 0)
5976 {
5977 *undefined_code = UNDEF_NOT_UNSIGNED;
5978 return TRUE;
5979 }
5980 else
5981 return FALSE;
5982
5983 case MVE_VLDRD_GATHER_T4:
5984 if (arm_decode_field (given, 7, 8) != 3)
5985 {
5986 *undefined_code = UNDEF_SIZE_NOT_3;
5987 return TRUE;
5988 }
5989 else if (arm_decode_field (given, 28, 28) == 0)
5990 {
5991 *undefined_code = UNDEF_NOT_UNSIGNED;
5992 return TRUE;
5993 }
5994 else
5995 return FALSE;
5996
5997 case MVE_VSTRB_SCATTER_T1:
5998 if (arm_decode_field (given, 7, 8) == 3)
5999 {
6000 *undefined_code = UNDEF_SIZE_3;
6001 return TRUE;
6002 }
6003 else
6004 return FALSE;
6005
6006 case MVE_VSTRH_SCATTER_T2:
6007 {
6008 unsigned long size = arm_decode_field (given, 7, 8);
6009 if (size == 3)
6010 {
6011 *undefined_code = UNDEF_SIZE_3;
6012 return TRUE;
6013 }
6014 else if (size == 0)
6015 {
6016 *undefined_code = UNDEF_SIZE_0;
6017 return TRUE;
6018 }
6019 else
6020 return FALSE;
6021 }
6022
6023 case MVE_VSTRW_SCATTER_T3:
6024 if (arm_decode_field (given, 7, 8) != 2)
6025 {
6026 *undefined_code = UNDEF_SIZE_NOT_2;
6027 return TRUE;
6028 }
6029 else
6030 return FALSE;
6031
6032 case MVE_VSTRD_SCATTER_T4:
6033 if (arm_decode_field (given, 7, 8) != 3)
6034 {
6035 *undefined_code = UNDEF_SIZE_NOT_3;
6036 return TRUE;
6037 }
6038 else
6039 return FALSE;
6040
6041 case MVE_VCVT_FP_FIX_VEC:
6042 {
6043 unsigned long imm6 = arm_decode_field (given, 16, 21);
6044 if ((imm6 & 0x20) == 0)
6045 {
6046 *undefined_code = UNDEF_VCVT_IMM6;
6047 return TRUE;
6048 }
6049
6050 if ((arm_decode_field (given, 9, 9) == 0)
6051 && ((imm6 & 0x30) == 0x20))
6052 {
6053 *undefined_code = UNDEF_VCVT_FSI_IMM6;
6054 return TRUE;
6055 }
6056
6057 return FALSE;
6058 }
6059
6060 case MVE_VNEG_FP:
6061 case MVE_VABS_FP:
6062 case MVE_VCVT_BETWEEN_FP_INT:
6063 case MVE_VCVT_FROM_FP_TO_INT:
6064 {
6065 unsigned long size = arm_decode_field (given, 18, 19);
6066 if (size == 0)
6067 {
6068 *undefined_code = UNDEF_SIZE_0;
6069 return TRUE;
6070 }
6071 else if (size == 3)
6072 {
6073 *undefined_code = UNDEF_SIZE_3;
6074 return TRUE;
6075 }
6076 else
6077 return FALSE;
6078 }
6079
6080 case MVE_VMOV_VEC_LANE_TO_GP:
6081 {
6082 unsigned long op1 = arm_decode_field (given, 21, 22);
6083 unsigned long op2 = arm_decode_field (given, 5, 6);
6084 unsigned long u = arm_decode_field (given, 23, 23);
6085
6086 if ((op2 == 0) && (u == 1))
6087 {
6088 if ((op1 == 0) || (op1 == 1))
6089 {
6090 *undefined_code = UNDEF_BAD_U_OP1_OP2;
6091 return TRUE;
6092 }
6093 else
6094 return FALSE;
6095 }
6096 else if (op2 == 2)
6097 {
6098 if ((op1 == 0) || (op1 == 1))
6099 {
6100 *undefined_code = UNDEF_BAD_OP1_OP2;
6101 return TRUE;
6102 }
6103 else
6104 return FALSE;
6105 }
6106
6107 return FALSE;
6108 }
6109
6110 case MVE_VMOV_GP_TO_VEC_LANE:
6111 if (arm_decode_field (given, 5, 6) == 2)
6112 {
6113 unsigned long op1 = arm_decode_field (given, 21, 22);
6114 if ((op1 == 0) || (op1 == 1))
6115 {
6116 *undefined_code = UNDEF_BAD_OP1_OP2;
6117 return TRUE;
6118 }
6119 else
6120 return FALSE;
6121 }
6122 else
6123 return FALSE;
6124
6125 case MVE_VMOV_VEC_TO_VEC:
6126 if ((arm_decode_field (given, 5, 5) == 1)
6127 || (arm_decode_field (given, 22, 22) == 1))
6128 return TRUE;
6129 return FALSE;
6130
6131 case MVE_VMOV_IMM_TO_VEC:
6132 if (arm_decode_field (given, 5, 5) == 0)
6133 {
6134 unsigned long cmode = arm_decode_field (given, 8, 11);
6135
6136 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6137 {
6138 *undefined_code = UNDEF_OP_0_BAD_CMODE;
6139 return TRUE;
6140 }
6141 else
6142 return FALSE;
6143 }
6144 else
6145 return FALSE;
6146
6147 case MVE_VSHLL_T2:
6148 case MVE_VMOVN:
6149 if (arm_decode_field (given, 18, 19) == 2)
6150 {
6151 *undefined_code = UNDEF_SIZE_2;
6152 return TRUE;
6153 }
6154 else
6155 return FALSE;
6156
6157 case MVE_VRMLALDAVH:
6158 case MVE_VMLADAV_T1:
6159 case MVE_VMLADAV_T2:
6160 case MVE_VMLALDAV:
6161 if ((arm_decode_field (given, 28, 28) == 1)
6162 && (arm_decode_field (given, 12, 12) == 1))
6163 {
6164 *undefined_code = UNDEF_XCHG_UNS;
6165 return TRUE;
6166 }
6167 else
6168 return FALSE;
6169
6170 case MVE_VQSHRN:
6171 case MVE_VQSHRUN:
6172 case MVE_VSHLL_T1:
6173 case MVE_VSHRN:
6174 {
6175 unsigned long sz = arm_decode_field (given, 19, 20);
6176 if (sz == 1)
6177 return FALSE;
6178 else if ((sz & 2) == 2)
6179 return FALSE;
6180 else
6181 {
6182 *undefined_code = UNDEF_SIZE;
6183 return TRUE;
6184 }
6185 }
6186 break;
6187
6188 case MVE_VQSHL_T2:
6189 case MVE_VQSHLU_T3:
6190 case MVE_VRSHR:
6191 case MVE_VSHL_T1:
6192 case MVE_VSHR:
6193 case MVE_VSLI:
6194 case MVE_VSRI:
6195 {
6196 unsigned long sz = arm_decode_field (given, 19, 21);
6197 if ((sz & 7) == 1)
6198 return FALSE;
6199 else if ((sz & 6) == 2)
6200 return FALSE;
6201 else if ((sz & 4) == 4)
6202 return FALSE;
6203 else
6204 {
6205 *undefined_code = UNDEF_SIZE;
6206 return TRUE;
6207 }
6208 }
6209
6210 case MVE_VQRSHRN:
6211 case MVE_VQRSHRUN:
6212 if (arm_decode_field (given, 19, 20) == 0)
6213 {
6214 *undefined_code = UNDEF_SIZE_0;
6215 return TRUE;
6216 }
6217 else
6218 return FALSE;
6219
6220 case MVE_VABS_VEC:
6221 if (arm_decode_field (given, 18, 19) == 3)
6222 {
6223 *undefined_code = UNDEF_SIZE_3;
6224 return TRUE;
6225 }
6226 else
6227 return FALSE;
6228
6229 case MVE_VQNEG:
6230 case MVE_VQABS:
6231 case MVE_VNEG_VEC:
6232 case MVE_VCLS:
6233 case MVE_VCLZ:
6234 if (arm_decode_field (given, 18, 19) == 3)
6235 {
6236 *undefined_code = UNDEF_SIZE_3;
6237 return TRUE;
6238 }
6239 else
6240 return FALSE;
6241
6242 case MVE_VREV16:
6243 if (arm_decode_field (given, 18, 19) == 0)
6244 return FALSE;
6245 else
6246 {
6247 *undefined_code = UNDEF_SIZE_NOT_0;
6248 return TRUE;
6249 }
6250
6251 case MVE_VREV32:
6252 {
6253 unsigned long size = arm_decode_field (given, 18, 19);
6254 if ((size & 2) == 2)
6255 {
6256 *undefined_code = UNDEF_SIZE_2;
6257 return TRUE;
6258 }
6259 else
6260 return FALSE;
6261 }
6262
6263 case MVE_VREV64:
6264 if (arm_decode_field (given, 18, 19) != 3)
6265 return FALSE;
6266 else
6267 {
6268 *undefined_code = UNDEF_SIZE_3;
6269 return TRUE;
6270 }
6271
6272 default:
6273 return FALSE;
6274 }
6275 }
6276
6277 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6278 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6279 why this encoding is unpredictable. */
6280
6281 static bfd_boolean
6282 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6283 enum mve_unpredictable *unpredictable_code)
6284 {
6285 *unpredictable_code = UNPRED_NONE;
6286
6287 switch (matched_insn)
6288 {
6289 case MVE_VCMP_FP_T2:
6290 case MVE_VPT_FP_T2:
6291 if ((arm_decode_field (given, 12, 12) == 0)
6292 && (arm_decode_field (given, 5, 5) == 1))
6293 {
6294 *unpredictable_code = UNPRED_FCA_0_FCB_1;
6295 return TRUE;
6296 }
6297 else
6298 return FALSE;
6299
6300 case MVE_VPT_VEC_T4:
6301 case MVE_VPT_VEC_T5:
6302 case MVE_VPT_VEC_T6:
6303 case MVE_VCMP_VEC_T4:
6304 case MVE_VCMP_VEC_T5:
6305 case MVE_VCMP_VEC_T6:
6306 if (arm_decode_field (given, 0, 3) == 0xd)
6307 {
6308 *unpredictable_code = UNPRED_R13;
6309 return TRUE;
6310 }
6311 else
6312 return FALSE;
6313
6314 case MVE_VDUP:
6315 {
6316 unsigned long gpr = arm_decode_field (given, 12, 15);
6317 if (gpr == 0xd)
6318 {
6319 *unpredictable_code = UNPRED_R13;
6320 return TRUE;
6321 }
6322 else if (gpr == 0xf)
6323 {
6324 *unpredictable_code = UNPRED_R15;
6325 return TRUE;
6326 }
6327
6328 return FALSE;
6329 }
6330
6331 case MVE_VQADD_T2:
6332 case MVE_VQSUB_T2:
6333 case MVE_VMUL_FP_T2:
6334 case MVE_VMUL_VEC_T2:
6335 case MVE_VMLA:
6336 case MVE_VBRSR:
6337 case MVE_VADD_FP_T2:
6338 case MVE_VSUB_FP_T2:
6339 case MVE_VADD_VEC_T2:
6340 case MVE_VSUB_VEC_T2:
6341 case MVE_VQRSHL_T2:
6342 case MVE_VQSHL_T1:
6343 case MVE_VRSHL_T2:
6344 case MVE_VSHL_T2:
6345 case MVE_VSHLC:
6346 case MVE_VQDMLAH:
6347 case MVE_VQRDMLAH:
6348 case MVE_VQDMLASH:
6349 case MVE_VQRDMLASH:
6350 case MVE_VQDMULH_T3:
6351 case MVE_VQRDMULH_T4:
6352 case MVE_VMLAS:
6353 case MVE_VFMA_FP_SCALAR:
6354 case MVE_VFMAS_FP_SCALAR:
6355 case MVE_VHADD_T2:
6356 case MVE_VHSUB_T2:
6357 {
6358 unsigned long gpr = arm_decode_field (given, 0, 3);
6359 if (gpr == 0xd)
6360 {
6361 *unpredictable_code = UNPRED_R13;
6362 return TRUE;
6363 }
6364 else if (gpr == 0xf)
6365 {
6366 *unpredictable_code = UNPRED_R15;
6367 return TRUE;
6368 }
6369
6370 return FALSE;
6371 }
6372
6373 case MVE_VLD2:
6374 case MVE_VST2:
6375 {
6376 unsigned long rn = arm_decode_field (given, 16, 19);
6377
6378 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6379 {
6380 *unpredictable_code = UNPRED_R13_AND_WB;
6381 return TRUE;
6382 }
6383
6384 if (rn == 0xf)
6385 {
6386 *unpredictable_code = UNPRED_R15;
6387 return TRUE;
6388 }
6389
6390 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6391 {
6392 *unpredictable_code = UNPRED_Q_GT_6;
6393 return TRUE;
6394 }
6395 else
6396 return FALSE;
6397 }
6398
6399 case MVE_VLD4:
6400 case MVE_VST4:
6401 {
6402 unsigned long rn = arm_decode_field (given, 16, 19);
6403
6404 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6405 {
6406 *unpredictable_code = UNPRED_R13_AND_WB;
6407 return TRUE;
6408 }
6409
6410 if (rn == 0xf)
6411 {
6412 *unpredictable_code = UNPRED_R15;
6413 return TRUE;
6414 }
6415
6416 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6417 {
6418 *unpredictable_code = UNPRED_Q_GT_4;
6419 return TRUE;
6420 }
6421 else
6422 return FALSE;
6423 }
6424
6425 case MVE_VLDRB_T5:
6426 case MVE_VLDRH_T6:
6427 case MVE_VLDRW_T7:
6428 case MVE_VSTRB_T5:
6429 case MVE_VSTRH_T6:
6430 case MVE_VSTRW_T7:
6431 {
6432 unsigned long rn = arm_decode_field (given, 16, 19);
6433
6434 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6435 {
6436 *unpredictable_code = UNPRED_R13_AND_WB;
6437 return TRUE;
6438 }
6439 else if (rn == 0xf)
6440 {
6441 *unpredictable_code = UNPRED_R15;
6442 return TRUE;
6443 }
6444 else
6445 return FALSE;
6446 }
6447
6448 case MVE_VLDRB_GATHER_T1:
6449 if (arm_decode_field (given, 0, 0) == 1)
6450 {
6451 *unpredictable_code = UNPRED_OS;
6452 return TRUE;
6453 }
6454
6455 /* fall through. */
6456 /* To handle common code with T2-T4 variants. */
6457 case MVE_VLDRH_GATHER_T2:
6458 case MVE_VLDRW_GATHER_T3:
6459 case MVE_VLDRD_GATHER_T4:
6460 {
6461 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6462 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6463
6464 if (qd == qm)
6465 {
6466 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6467 return TRUE;
6468 }
6469
6470 if (arm_decode_field (given, 16, 19) == 0xf)
6471 {
6472 *unpredictable_code = UNPRED_R15;
6473 return TRUE;
6474 }
6475
6476 return FALSE;
6477 }
6478
6479 case MVE_VLDRW_GATHER_T5:
6480 case MVE_VLDRD_GATHER_T6:
6481 {
6482 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6483 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6484
6485 if (qd == qm)
6486 {
6487 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6488 return TRUE;
6489 }
6490 else
6491 return FALSE;
6492 }
6493
6494 case MVE_VSTRB_SCATTER_T1:
6495 if (arm_decode_field (given, 16, 19) == 0xf)
6496 {
6497 *unpredictable_code = UNPRED_R15;
6498 return TRUE;
6499 }
6500 else if (arm_decode_field (given, 0, 0) == 1)
6501 {
6502 *unpredictable_code = UNPRED_OS;
6503 return TRUE;
6504 }
6505 else
6506 return FALSE;
6507
6508 case MVE_VSTRH_SCATTER_T2:
6509 case MVE_VSTRW_SCATTER_T3:
6510 case MVE_VSTRD_SCATTER_T4:
6511 if (arm_decode_field (given, 16, 19) == 0xf)
6512 {
6513 *unpredictable_code = UNPRED_R15;
6514 return TRUE;
6515 }
6516 else
6517 return FALSE;
6518
6519 case MVE_VMOV2_VEC_LANE_TO_GP:
6520 case MVE_VMOV2_GP_TO_VEC_LANE:
6521 case MVE_VCVT_BETWEEN_FP_INT:
6522 case MVE_VCVT_FROM_FP_TO_INT:
6523 {
6524 unsigned long rt = arm_decode_field (given, 0, 3);
6525 unsigned long rt2 = arm_decode_field (given, 16, 19);
6526
6527 if ((rt == 0xd) || (rt2 == 0xd))
6528 {
6529 *unpredictable_code = UNPRED_R13;
6530 return TRUE;
6531 }
6532 else if ((rt == 0xf) || (rt2 == 0xf))
6533 {
6534 *unpredictable_code = UNPRED_R15;
6535 return TRUE;
6536 }
6537 else if (rt == rt2)
6538 {
6539 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6540 return TRUE;
6541 }
6542
6543 return FALSE;
6544 }
6545
6546 case MVE_VMAXV:
6547 case MVE_VMAXAV:
6548 case MVE_VMAXNMV_FP:
6549 case MVE_VMAXNMAV_FP:
6550 case MVE_VMINNMV_FP:
6551 case MVE_VMINNMAV_FP:
6552 case MVE_VMINV:
6553 case MVE_VMINAV:
6554 case MVE_VABAV:
6555 case MVE_VMOV_HFP_TO_GP:
6556 case MVE_VMOV_GP_TO_VEC_LANE:
6557 case MVE_VMOV_VEC_LANE_TO_GP:
6558 {
6559 unsigned long rda = arm_decode_field (given, 12, 15);
6560 if (rda == 0xd)
6561 {
6562 *unpredictable_code = UNPRED_R13;
6563 return TRUE;
6564 }
6565 else if (rda == 0xf)
6566 {
6567 *unpredictable_code = UNPRED_R15;
6568 return TRUE;
6569 }
6570
6571 return FALSE;
6572 }
6573
6574 case MVE_VMULL_INT:
6575 {
6576 unsigned long Qd;
6577 unsigned long Qm;
6578 unsigned long Qn;
6579
6580 if (arm_decode_field (given, 20, 21) == 2)
6581 {
6582 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6583 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6584 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6585
6586 if ((Qd == Qn) || (Qd == Qm))
6587 {
6588 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6589 return TRUE;
6590 }
6591 else
6592 return FALSE;
6593 }
6594 else
6595 return FALSE;
6596 }
6597
6598 case MVE_VCMUL_FP:
6599 case MVE_VQDMULL_T1:
6600 {
6601 unsigned long Qd;
6602 unsigned long Qm;
6603 unsigned long Qn;
6604
6605 if (arm_decode_field (given, 28, 28) == 1)
6606 {
6607 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6608 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6609 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6610
6611 if ((Qd == Qn) || (Qd == Qm))
6612 {
6613 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6614 return TRUE;
6615 }
6616 else
6617 return FALSE;
6618 }
6619 else
6620 return FALSE;
6621 }
6622
6623 case MVE_VQDMULL_T2:
6624 {
6625 unsigned long gpr = arm_decode_field (given, 0, 3);
6626 if (gpr == 0xd)
6627 {
6628 *unpredictable_code = UNPRED_R13;
6629 return TRUE;
6630 }
6631 else if (gpr == 0xf)
6632 {
6633 *unpredictable_code = UNPRED_R15;
6634 return TRUE;
6635 }
6636
6637 if (arm_decode_field (given, 28, 28) == 1)
6638 {
6639 unsigned long Qd
6640 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6641 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6642
6643 if (Qd == Qn)
6644 {
6645 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6646 return TRUE;
6647 }
6648 else
6649 return FALSE;
6650 }
6651
6652 return FALSE;
6653 }
6654
6655 case MVE_VMLSLDAV:
6656 case MVE_VRMLSLDAVH:
6657 case MVE_VMLALDAV:
6658 case MVE_VADDLV:
6659 if (arm_decode_field (given, 20, 22) == 6)
6660 {
6661 *unpredictable_code = UNPRED_R13;
6662 return TRUE;
6663 }
6664 else
6665 return FALSE;
6666
6667 case MVE_VDWDUP:
6668 case MVE_VIWDUP:
6669 if (arm_decode_field (given, 1, 3) == 6)
6670 {
6671 *unpredictable_code = UNPRED_R13;
6672 return TRUE;
6673 }
6674 else
6675 return FALSE;
6676
6677 case MVE_VCADD_VEC:
6678 case MVE_VHCADD:
6679 {
6680 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6681 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6682 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6683 {
6684 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6685 return TRUE;
6686 }
6687 else
6688 return FALSE;
6689 }
6690
6691 case MVE_VCADD_FP:
6692 {
6693 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6694 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6695 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6696 {
6697 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6698 return TRUE;
6699 }
6700 else
6701 return FALSE;
6702 }
6703
6704 case MVE_VCMLA_FP:
6705 {
6706 unsigned long Qda;
6707 unsigned long Qm;
6708 unsigned long Qn;
6709
6710 if (arm_decode_field (given, 20, 20) == 1)
6711 {
6712 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6713 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6714 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6715
6716 if ((Qda == Qn) || (Qda == Qm))
6717 {
6718 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6719 return TRUE;
6720 }
6721 else
6722 return FALSE;
6723 }
6724 else
6725 return FALSE;
6726
6727 }
6728
6729 case MVE_VCTP:
6730 if (arm_decode_field (given, 16, 19) == 0xd)
6731 {
6732 *unpredictable_code = UNPRED_R13;
6733 return TRUE;
6734 }
6735 else
6736 return FALSE;
6737
6738 case MVE_VREV64:
6739 {
6740 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6741 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6742
6743 if (qd == qm)
6744 {
6745 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6746 return TRUE;
6747 }
6748 else
6749 return FALSE;
6750 }
6751
6752 case MVE_LSLL:
6753 case MVE_LSLLI:
6754 case MVE_LSRL:
6755 case MVE_ASRL:
6756 case MVE_ASRLI:
6757 case MVE_UQSHLL:
6758 case MVE_UQRSHLL:
6759 case MVE_URSHRL:
6760 case MVE_SRSHRL:
6761 case MVE_SQSHLL:
6762 case MVE_SQRSHRL:
6763 {
6764 unsigned long gpr = arm_decode_field (given, 9, 11);
6765 gpr = ((gpr << 1) | 1);
6766 if (gpr == 0xd)
6767 {
6768 *unpredictable_code = UNPRED_R13;
6769 return TRUE;
6770 }
6771 else if (gpr == 0xf)
6772 {
6773 *unpredictable_code = UNPRED_R15;
6774 return TRUE;
6775 }
6776
6777 return FALSE;
6778 }
6779
6780 default:
6781 return FALSE;
6782 }
6783 }
6784
6785 static void
6786 print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6787 {
6788 unsigned long op1 = arm_decode_field (given, 21, 22);
6789 unsigned long op2 = arm_decode_field (given, 5, 6);
6790 unsigned long h = arm_decode_field (given, 16, 16);
6791 unsigned long index_operand, esize, targetBeat, idx;
6792 void *stream = info->stream;
6793 fprintf_ftype func = info->fprintf_func;
6794
6795 if ((op1 & 0x2) == 0x2)
6796 {
6797 index_operand = op2;
6798 esize = 8;
6799 }
6800 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6801 {
6802 index_operand = op2 >> 1;
6803 esize = 16;
6804 }
6805 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6806 {
6807 index_operand = 0;
6808 esize = 32;
6809 }
6810 else
6811 {
6812 func (stream, "<undefined index>");
6813 return;
6814 }
6815
6816 targetBeat = (op1 & 0x1) | (h << 1);
6817 idx = index_operand + targetBeat * (32/esize);
6818
6819 func (stream, "%lu", idx);
6820 }
6821
6822 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6823 in length and integer of floating-point type. */
6824 static void
6825 print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6826 unsigned int ibit_loc, const struct mopcode32 *insn)
6827 {
6828 int bits = 0;
6829 int cmode = (given >> 8) & 0xf;
6830 int op = (given >> 5) & 0x1;
6831 unsigned long value = 0, hival = 0;
6832 unsigned shift;
6833 int size = 0;
6834 int isfloat = 0;
6835 void *stream = info->stream;
6836 fprintf_ftype func = info->fprintf_func;
6837
6838 /* On Neon the 'i' bit is at bit 24, on mve it is
6839 at bit 28. */
6840 bits |= ((given >> ibit_loc) & 1) << 7;
6841 bits |= ((given >> 16) & 7) << 4;
6842 bits |= ((given >> 0) & 15) << 0;
6843
6844 if (cmode < 8)
6845 {
6846 shift = (cmode >> 1) & 3;
6847 value = (unsigned long) bits << (8 * shift);
6848 size = 32;
6849 }
6850 else if (cmode < 12)
6851 {
6852 shift = (cmode >> 1) & 1;
6853 value = (unsigned long) bits << (8 * shift);
6854 size = 16;
6855 }
6856 else if (cmode < 14)
6857 {
6858 shift = (cmode & 1) + 1;
6859 value = (unsigned long) bits << (8 * shift);
6860 value |= (1ul << (8 * shift)) - 1;
6861 size = 32;
6862 }
6863 else if (cmode == 14)
6864 {
6865 if (op)
6866 {
6867 /* Bit replication into bytes. */
6868 int ix;
6869 unsigned long mask;
6870
6871 value = 0;
6872 hival = 0;
6873 for (ix = 7; ix >= 0; ix--)
6874 {
6875 mask = ((bits >> ix) & 1) ? 0xff : 0;
6876 if (ix <= 3)
6877 value = (value << 8) | mask;
6878 else
6879 hival = (hival << 8) | mask;
6880 }
6881 size = 64;
6882 }
6883 else
6884 {
6885 /* Byte replication. */
6886 value = (unsigned long) bits;
6887 size = 8;
6888 }
6889 }
6890 else if (!op)
6891 {
6892 /* Floating point encoding. */
6893 int tmp;
6894
6895 value = (unsigned long) (bits & 0x7f) << 19;
6896 value |= (unsigned long) (bits & 0x80) << 24;
6897 tmp = bits & 0x40 ? 0x3c : 0x40;
6898 value |= (unsigned long) tmp << 24;
6899 size = 32;
6900 isfloat = 1;
6901 }
6902 else
6903 {
6904 func (stream, "<illegal constant %.8x:%x:%x>",
6905 bits, cmode, op);
6906 size = 32;
6907 return;
6908 }
6909
6910 // printU determines whether the immediate value should be printed as
6911 // unsigned.
6912 unsigned printU = 0;
6913 switch (insn->mve_op)
6914 {
6915 default:
6916 break;
6917 // We want this for instructions that don't have a 'signed' type
6918 case MVE_VBIC_IMM:
6919 case MVE_VORR_IMM:
6920 case MVE_VMVN_IMM:
6921 case MVE_VMOV_IMM_TO_VEC:
6922 printU = 1;
6923 break;
6924 }
6925 switch (size)
6926 {
6927 case 8:
6928 func (stream, "#%ld\t; 0x%.2lx", value, value);
6929 break;
6930
6931 case 16:
6932 func (stream,
6933 printU
6934 ? "#%lu\t; 0x%.4lx"
6935 : "#%ld\t; 0x%.4lx", value, value);
6936 break;
6937
6938 case 32:
6939 if (isfloat)
6940 {
6941 unsigned char valbytes[4];
6942 double fvalue;
6943
6944 /* Do this a byte at a time so we don't have to
6945 worry about the host's endianness. */
6946 valbytes[0] = value & 0xff;
6947 valbytes[1] = (value >> 8) & 0xff;
6948 valbytes[2] = (value >> 16) & 0xff;
6949 valbytes[3] = (value >> 24) & 0xff;
6950
6951 floatformat_to_double
6952 (& floatformat_ieee_single_little, valbytes,
6953 & fvalue);
6954
6955 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
6956 value);
6957 }
6958 else
6959 func (stream,
6960 printU
6961 ? "#%lu\t; 0x%.8lx"
6962 : "#%ld\t; 0x%.8lx",
6963 (long) (((value & 0x80000000L) != 0)
6964 && !printU
6965 ? value | ~0xffffffffL : value),
6966 value);
6967 break;
6968
6969 case 64:
6970 func (stream, "#0x%.8lx%.8lx", hival, value);
6971 break;
6972
6973 default:
6974 abort ();
6975 }
6976
6977 }
6978
6979 static void
6980 print_mve_undefined (struct disassemble_info *info,
6981 enum mve_undefined undefined_code)
6982 {
6983 void *stream = info->stream;
6984 fprintf_ftype func = info->fprintf_func;
6985
6986 func (stream, "\t\tundefined instruction: ");
6987
6988 switch (undefined_code)
6989 {
6990 case UNDEF_SIZE:
6991 func (stream, "illegal size");
6992 break;
6993
6994 case UNDEF_SIZE_0:
6995 func (stream, "size equals zero");
6996 break;
6997
6998 case UNDEF_SIZE_2:
6999 func (stream, "size equals two");
7000 break;
7001
7002 case UNDEF_SIZE_3:
7003 func (stream, "size equals three");
7004 break;
7005
7006 case UNDEF_SIZE_LE_1:
7007 func (stream, "size <= 1");
7008 break;
7009
7010 case UNDEF_SIZE_NOT_0:
7011 func (stream, "size not equal to 0");
7012 break;
7013
7014 case UNDEF_SIZE_NOT_2:
7015 func (stream, "size not equal to 2");
7016 break;
7017
7018 case UNDEF_SIZE_NOT_3:
7019 func (stream, "size not equal to 3");
7020 break;
7021
7022 case UNDEF_NOT_UNS_SIZE_0:
7023 func (stream, "not unsigned and size = zero");
7024 break;
7025
7026 case UNDEF_NOT_UNS_SIZE_1:
7027 func (stream, "not unsigned and size = one");
7028 break;
7029
7030 case UNDEF_NOT_UNSIGNED:
7031 func (stream, "not unsigned");
7032 break;
7033
7034 case UNDEF_VCVT_IMM6:
7035 func (stream, "invalid imm6");
7036 break;
7037
7038 case UNDEF_VCVT_FSI_IMM6:
7039 func (stream, "fsi = 0 and invalid imm6");
7040 break;
7041
7042 case UNDEF_BAD_OP1_OP2:
7043 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
7044 break;
7045
7046 case UNDEF_BAD_U_OP1_OP2:
7047 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
7048 break;
7049
7050 case UNDEF_OP_0_BAD_CMODE:
7051 func (stream, "op field equal 0 and bad cmode");
7052 break;
7053
7054 case UNDEF_XCHG_UNS:
7055 func (stream, "exchange and unsigned together");
7056 break;
7057
7058 case UNDEF_NONE:
7059 break;
7060 }
7061
7062 }
7063
7064 static void
7065 print_mve_unpredictable (struct disassemble_info *info,
7066 enum mve_unpredictable unpredict_code)
7067 {
7068 void *stream = info->stream;
7069 fprintf_ftype func = info->fprintf_func;
7070
7071 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
7072
7073 switch (unpredict_code)
7074 {
7075 case UNPRED_IT_BLOCK:
7076 func (stream, "mve instruction in it block");
7077 break;
7078
7079 case UNPRED_FCA_0_FCB_1:
7080 func (stream, "condition bits, fca = 0 and fcb = 1");
7081 break;
7082
7083 case UNPRED_R13:
7084 func (stream, "use of r13 (sp)");
7085 break;
7086
7087 case UNPRED_R15:
7088 func (stream, "use of r15 (pc)");
7089 break;
7090
7091 case UNPRED_Q_GT_4:
7092 func (stream, "start register block > r4");
7093 break;
7094
7095 case UNPRED_Q_GT_6:
7096 func (stream, "start register block > r6");
7097 break;
7098
7099 case UNPRED_R13_AND_WB:
7100 func (stream, "use of r13 and write back");
7101 break;
7102
7103 case UNPRED_Q_REGS_EQUAL:
7104 func (stream,
7105 "same vector register used for destination and other operand");
7106 break;
7107
7108 case UNPRED_OS:
7109 func (stream, "use of offset scaled");
7110 break;
7111
7112 case UNPRED_GP_REGS_EQUAL:
7113 func (stream, "same general-purpose register used for both operands");
7114 break;
7115
7116 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7117 func (stream, "use of identical q registers and size = 1");
7118 break;
7119
7120 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7121 func (stream, "use of identical q registers and size = 1");
7122 break;
7123
7124 case UNPRED_NONE:
7125 break;
7126 }
7127 }
7128
7129 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
7130
7131 static void
7132 print_mve_register_blocks (struct disassemble_info *info,
7133 unsigned long given,
7134 enum mve_instructions matched_insn)
7135 {
7136 void *stream = info->stream;
7137 fprintf_ftype func = info->fprintf_func;
7138
7139 unsigned long q_reg_start = arm_decode_field_multiple (given,
7140 13, 15,
7141 22, 22);
7142 switch (matched_insn)
7143 {
7144 case MVE_VLD2:
7145 case MVE_VST2:
7146 if (q_reg_start <= 6)
7147 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
7148 else
7149 func (stream, "<illegal reg q%ld>", q_reg_start);
7150 break;
7151
7152 case MVE_VLD4:
7153 case MVE_VST4:
7154 if (q_reg_start <= 4)
7155 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
7156 q_reg_start + 1, q_reg_start + 2,
7157 q_reg_start + 3);
7158 else
7159 func (stream, "<illegal reg q%ld>", q_reg_start);
7160 break;
7161
7162 default:
7163 break;
7164 }
7165 }
7166
7167 static void
7168 print_mve_rounding_mode (struct disassemble_info *info,
7169 unsigned long given,
7170 enum mve_instructions matched_insn)
7171 {
7172 void *stream = info->stream;
7173 fprintf_ftype func = info->fprintf_func;
7174
7175 switch (matched_insn)
7176 {
7177 case MVE_VCVT_FROM_FP_TO_INT:
7178 {
7179 switch (arm_decode_field (given, 8, 9))
7180 {
7181 case 0:
7182 func (stream, "a");
7183 break;
7184
7185 case 1:
7186 func (stream, "n");
7187 break;
7188
7189 case 2:
7190 func (stream, "p");
7191 break;
7192
7193 case 3:
7194 func (stream, "m");
7195 break;
7196
7197 default:
7198 break;
7199 }
7200 }
7201 break;
7202
7203 case MVE_VRINT_FP:
7204 {
7205 switch (arm_decode_field (given, 7, 9))
7206 {
7207 case 0:
7208 func (stream, "n");
7209 break;
7210
7211 case 1:
7212 func (stream, "x");
7213 break;
7214
7215 case 2:
7216 func (stream, "a");
7217 break;
7218
7219 case 3:
7220 func (stream, "z");
7221 break;
7222
7223 case 5:
7224 func (stream, "m");
7225 break;
7226
7227 case 7:
7228 func (stream, "p");
7229
7230 case 4:
7231 case 6:
7232 default:
7233 break;
7234 }
7235 }
7236 break;
7237
7238 default:
7239 break;
7240 }
7241 }
7242
7243 static void
7244 print_mve_vcvt_size (struct disassemble_info *info,
7245 unsigned long given,
7246 enum mve_instructions matched_insn)
7247 {
7248 unsigned long mode = 0;
7249 void *stream = info->stream;
7250 fprintf_ftype func = info->fprintf_func;
7251
7252 switch (matched_insn)
7253 {
7254 case MVE_VCVT_FP_FIX_VEC:
7255 {
7256 mode = (((given & 0x200) >> 7)
7257 | ((given & 0x10000000) >> 27)
7258 | ((given & 0x100) >> 8));
7259
7260 switch (mode)
7261 {
7262 case 0:
7263 func (stream, "f16.s16");
7264 break;
7265
7266 case 1:
7267 func (stream, "s16.f16");
7268 break;
7269
7270 case 2:
7271 func (stream, "f16.u16");
7272 break;
7273
7274 case 3:
7275 func (stream, "u16.f16");
7276 break;
7277
7278 case 4:
7279 func (stream, "f32.s32");
7280 break;
7281
7282 case 5:
7283 func (stream, "s32.f32");
7284 break;
7285
7286 case 6:
7287 func (stream, "f32.u32");
7288 break;
7289
7290 case 7:
7291 func (stream, "u32.f32");
7292 break;
7293
7294 default:
7295 break;
7296 }
7297 break;
7298 }
7299 case MVE_VCVT_BETWEEN_FP_INT:
7300 {
7301 unsigned long size = arm_decode_field (given, 18, 19);
7302 unsigned long op = arm_decode_field (given, 7, 8);
7303
7304 if (size == 1)
7305 {
7306 switch (op)
7307 {
7308 case 0:
7309 func (stream, "f16.s16");
7310 break;
7311
7312 case 1:
7313 func (stream, "f16.u16");
7314 break;
7315
7316 case 2:
7317 func (stream, "s16.f16");
7318 break;
7319
7320 case 3:
7321 func (stream, "u16.f16");
7322 break;
7323
7324 default:
7325 break;
7326 }
7327 }
7328 else if (size == 2)
7329 {
7330 switch (op)
7331 {
7332 case 0:
7333 func (stream, "f32.s32");
7334 break;
7335
7336 case 1:
7337 func (stream, "f32.u32");
7338 break;
7339
7340 case 2:
7341 func (stream, "s32.f32");
7342 break;
7343
7344 case 3:
7345 func (stream, "u32.f32");
7346 break;
7347 }
7348 }
7349 }
7350 break;
7351
7352 case MVE_VCVT_FP_HALF_FP:
7353 {
7354 unsigned long op = arm_decode_field (given, 28, 28);
7355 if (op == 0)
7356 func (stream, "f16.f32");
7357 else if (op == 1)
7358 func (stream, "f32.f16");
7359 }
7360 break;
7361
7362 case MVE_VCVT_FROM_FP_TO_INT:
7363 {
7364 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7365
7366 switch (size)
7367 {
7368 case 2:
7369 func (stream, "s16.f16");
7370 break;
7371
7372 case 3:
7373 func (stream, "u16.f16");
7374 break;
7375
7376 case 4:
7377 func (stream, "s32.f32");
7378 break;
7379
7380 case 5:
7381 func (stream, "u32.f32");
7382 break;
7383
7384 default:
7385 break;
7386 }
7387 }
7388 break;
7389
7390 default:
7391 break;
7392 }
7393 }
7394
7395 static void
7396 print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7397 unsigned long rot_width)
7398 {
7399 void *stream = info->stream;
7400 fprintf_ftype func = info->fprintf_func;
7401
7402 if (rot_width == 1)
7403 {
7404 switch (rot)
7405 {
7406 case 0:
7407 func (stream, "90");
7408 break;
7409 case 1:
7410 func (stream, "270");
7411 break;
7412 default:
7413 break;
7414 }
7415 }
7416 else if (rot_width == 2)
7417 {
7418 switch (rot)
7419 {
7420 case 0:
7421 func (stream, "0");
7422 break;
7423 case 1:
7424 func (stream, "90");
7425 break;
7426 case 2:
7427 func (stream, "180");
7428 break;
7429 case 3:
7430 func (stream, "270");
7431 break;
7432 default:
7433 break;
7434 }
7435 }
7436 }
7437
7438 static void
7439 print_instruction_predicate (struct disassemble_info *info)
7440 {
7441 void *stream = info->stream;
7442 fprintf_ftype func = info->fprintf_func;
7443
7444 if (vpt_block_state.next_pred_state == PRED_THEN)
7445 func (stream, "t");
7446 else if (vpt_block_state.next_pred_state == PRED_ELSE)
7447 func (stream, "e");
7448 }
7449
7450 static void
7451 print_mve_size (struct disassemble_info *info,
7452 unsigned long size,
7453 enum mve_instructions matched_insn)
7454 {
7455 void *stream = info->stream;
7456 fprintf_ftype func = info->fprintf_func;
7457
7458 switch (matched_insn)
7459 {
7460 case MVE_VABAV:
7461 case MVE_VABD_VEC:
7462 case MVE_VABS_FP:
7463 case MVE_VABS_VEC:
7464 case MVE_VADD_VEC_T1:
7465 case MVE_VADD_VEC_T2:
7466 case MVE_VADDV:
7467 case MVE_VBRSR:
7468 case MVE_VCADD_VEC:
7469 case MVE_VCLS:
7470 case MVE_VCLZ:
7471 case MVE_VCMP_VEC_T1:
7472 case MVE_VCMP_VEC_T2:
7473 case MVE_VCMP_VEC_T3:
7474 case MVE_VCMP_VEC_T4:
7475 case MVE_VCMP_VEC_T5:
7476 case MVE_VCMP_VEC_T6:
7477 case MVE_VCTP:
7478 case MVE_VDDUP:
7479 case MVE_VDWDUP:
7480 case MVE_VHADD_T1:
7481 case MVE_VHADD_T2:
7482 case MVE_VHCADD:
7483 case MVE_VHSUB_T1:
7484 case MVE_VHSUB_T2:
7485 case MVE_VIDUP:
7486 case MVE_VIWDUP:
7487 case MVE_VLD2:
7488 case MVE_VLD4:
7489 case MVE_VLDRB_GATHER_T1:
7490 case MVE_VLDRH_GATHER_T2:
7491 case MVE_VLDRW_GATHER_T3:
7492 case MVE_VLDRD_GATHER_T4:
7493 case MVE_VLDRB_T1:
7494 case MVE_VLDRH_T2:
7495 case MVE_VMAX:
7496 case MVE_VMAXA:
7497 case MVE_VMAXV:
7498 case MVE_VMAXAV:
7499 case MVE_VMIN:
7500 case MVE_VMINA:
7501 case MVE_VMINV:
7502 case MVE_VMINAV:
7503 case MVE_VMLA:
7504 case MVE_VMLAS:
7505 case MVE_VMUL_VEC_T1:
7506 case MVE_VMUL_VEC_T2:
7507 case MVE_VMULH:
7508 case MVE_VRMULH:
7509 case MVE_VMULL_INT:
7510 case MVE_VNEG_FP:
7511 case MVE_VNEG_VEC:
7512 case MVE_VPT_VEC_T1:
7513 case MVE_VPT_VEC_T2:
7514 case MVE_VPT_VEC_T3:
7515 case MVE_VPT_VEC_T4:
7516 case MVE_VPT_VEC_T5:
7517 case MVE_VPT_VEC_T6:
7518 case MVE_VQABS:
7519 case MVE_VQADD_T1:
7520 case MVE_VQADD_T2:
7521 case MVE_VQDMLADH:
7522 case MVE_VQRDMLADH:
7523 case MVE_VQDMLAH:
7524 case MVE_VQRDMLAH:
7525 case MVE_VQDMLASH:
7526 case MVE_VQRDMLASH:
7527 case MVE_VQDMLSDH:
7528 case MVE_VQRDMLSDH:
7529 case MVE_VQDMULH_T1:
7530 case MVE_VQRDMULH_T2:
7531 case MVE_VQDMULH_T3:
7532 case MVE_VQRDMULH_T4:
7533 case MVE_VQNEG:
7534 case MVE_VQRSHL_T1:
7535 case MVE_VQRSHL_T2:
7536 case MVE_VQSHL_T1:
7537 case MVE_VQSHL_T4:
7538 case MVE_VQSUB_T1:
7539 case MVE_VQSUB_T2:
7540 case MVE_VREV32:
7541 case MVE_VREV64:
7542 case MVE_VRHADD:
7543 case MVE_VRINT_FP:
7544 case MVE_VRSHL_T1:
7545 case MVE_VRSHL_T2:
7546 case MVE_VSHL_T2:
7547 case MVE_VSHL_T3:
7548 case MVE_VSHLL_T2:
7549 case MVE_VST2:
7550 case MVE_VST4:
7551 case MVE_VSTRB_SCATTER_T1:
7552 case MVE_VSTRH_SCATTER_T2:
7553 case MVE_VSTRW_SCATTER_T3:
7554 case MVE_VSTRB_T1:
7555 case MVE_VSTRH_T2:
7556 case MVE_VSUB_VEC_T1:
7557 case MVE_VSUB_VEC_T2:
7558 if (size <= 3)
7559 func (stream, "%s", mve_vec_sizename[size]);
7560 else
7561 func (stream, "<undef size>");
7562 break;
7563
7564 case MVE_VABD_FP:
7565 case MVE_VADD_FP_T1:
7566 case MVE_VADD_FP_T2:
7567 case MVE_VSUB_FP_T1:
7568 case MVE_VSUB_FP_T2:
7569 case MVE_VCMP_FP_T1:
7570 case MVE_VCMP_FP_T2:
7571 case MVE_VFMA_FP_SCALAR:
7572 case MVE_VFMA_FP:
7573 case MVE_VFMS_FP:
7574 case MVE_VFMAS_FP_SCALAR:
7575 case MVE_VMAXNM_FP:
7576 case MVE_VMAXNMA_FP:
7577 case MVE_VMAXNMV_FP:
7578 case MVE_VMAXNMAV_FP:
7579 case MVE_VMINNM_FP:
7580 case MVE_VMINNMA_FP:
7581 case MVE_VMINNMV_FP:
7582 case MVE_VMINNMAV_FP:
7583 case MVE_VMUL_FP_T1:
7584 case MVE_VMUL_FP_T2:
7585 case MVE_VPT_FP_T1:
7586 case MVE_VPT_FP_T2:
7587 if (size == 0)
7588 func (stream, "32");
7589 else if (size == 1)
7590 func (stream, "16");
7591 break;
7592
7593 case MVE_VCADD_FP:
7594 case MVE_VCMLA_FP:
7595 case MVE_VCMUL_FP:
7596 case MVE_VMLADAV_T1:
7597 case MVE_VMLALDAV:
7598 case MVE_VMLSDAV_T1:
7599 case MVE_VMLSLDAV:
7600 case MVE_VMOVN:
7601 case MVE_VQDMULL_T1:
7602 case MVE_VQDMULL_T2:
7603 case MVE_VQMOVN:
7604 case MVE_VQMOVUN:
7605 if (size == 0)
7606 func (stream, "16");
7607 else if (size == 1)
7608 func (stream, "32");
7609 break;
7610
7611 case MVE_VMOVL:
7612 if (size == 1)
7613 func (stream, "8");
7614 else if (size == 2)
7615 func (stream, "16");
7616 break;
7617
7618 case MVE_VDUP:
7619 switch (size)
7620 {
7621 case 0:
7622 func (stream, "32");
7623 break;
7624 case 1:
7625 func (stream, "16");
7626 break;
7627 case 2:
7628 func (stream, "8");
7629 break;
7630 default:
7631 break;
7632 }
7633 break;
7634
7635 case MVE_VMOV_GP_TO_VEC_LANE:
7636 case MVE_VMOV_VEC_LANE_TO_GP:
7637 switch (size)
7638 {
7639 case 0: case 4:
7640 func (stream, "32");
7641 break;
7642
7643 case 1: case 3:
7644 case 5: case 7:
7645 func (stream, "16");
7646 break;
7647
7648 case 8: case 9: case 10: case 11:
7649 case 12: case 13: case 14: case 15:
7650 func (stream, "8");
7651 break;
7652
7653 default:
7654 break;
7655 }
7656 break;
7657
7658 case MVE_VMOV_IMM_TO_VEC:
7659 switch (size)
7660 {
7661 case 0: case 4: case 8:
7662 case 12: case 24: case 26:
7663 func (stream, "i32");
7664 break;
7665 case 16: case 20:
7666 func (stream, "i16");
7667 break;
7668 case 28:
7669 func (stream, "i8");
7670 break;
7671 case 29:
7672 func (stream, "i64");
7673 break;
7674 case 30:
7675 func (stream, "f32");
7676 break;
7677 default:
7678 break;
7679 }
7680 break;
7681
7682 case MVE_VMULL_POLY:
7683 if (size == 0)
7684 func (stream, "p8");
7685 else if (size == 1)
7686 func (stream, "p16");
7687 break;
7688
7689 case MVE_VMVN_IMM:
7690 switch (size)
7691 {
7692 case 0: case 2: case 4:
7693 case 6: case 12: case 13:
7694 func (stream, "32");
7695 break;
7696
7697 case 8: case 10:
7698 func (stream, "16");
7699 break;
7700
7701 default:
7702 break;
7703 }
7704 break;
7705
7706 case MVE_VBIC_IMM:
7707 case MVE_VORR_IMM:
7708 switch (size)
7709 {
7710 case 1: case 3:
7711 case 5: case 7:
7712 func (stream, "32");
7713 break;
7714
7715 case 9: case 11:
7716 func (stream, "16");
7717 break;
7718
7719 default:
7720 break;
7721 }
7722 break;
7723
7724 case MVE_VQSHRN:
7725 case MVE_VQSHRUN:
7726 case MVE_VQRSHRN:
7727 case MVE_VQRSHRUN:
7728 case MVE_VRSHRN:
7729 case MVE_VSHRN:
7730 {
7731 switch (size)
7732 {
7733 case 1:
7734 func (stream, "16");
7735 break;
7736
7737 case 2: case 3:
7738 func (stream, "32");
7739 break;
7740
7741 default:
7742 break;
7743 }
7744 }
7745 break;
7746
7747 case MVE_VQSHL_T2:
7748 case MVE_VQSHLU_T3:
7749 case MVE_VRSHR:
7750 case MVE_VSHL_T1:
7751 case MVE_VSHLL_T1:
7752 case MVE_VSHR:
7753 case MVE_VSLI:
7754 case MVE_VSRI:
7755 {
7756 switch (size)
7757 {
7758 case 1:
7759 func (stream, "8");
7760 break;
7761
7762 case 2: case 3:
7763 func (stream, "16");
7764 break;
7765
7766 case 4: case 5: case 6: case 7:
7767 func (stream, "32");
7768 break;
7769
7770 default:
7771 break;
7772 }
7773 }
7774 break;
7775
7776 default:
7777 break;
7778 }
7779 }
7780
7781 static void
7782 print_mve_shift_n (struct disassemble_info *info, long given,
7783 enum mve_instructions matched_insn)
7784 {
7785 void *stream = info->stream;
7786 fprintf_ftype func = info->fprintf_func;
7787
7788 int startAt0
7789 = matched_insn == MVE_VQSHL_T2
7790 || matched_insn == MVE_VQSHLU_T3
7791 || matched_insn == MVE_VSHL_T1
7792 || matched_insn == MVE_VSHLL_T1
7793 || matched_insn == MVE_VSLI;
7794
7795 unsigned imm6 = (given & 0x3f0000) >> 16;
7796
7797 if (matched_insn == MVE_VSHLL_T1)
7798 imm6 &= 0x1f;
7799
7800 unsigned shiftAmount = 0;
7801 if ((imm6 & 0x20) != 0)
7802 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7803 else if ((imm6 & 0x10) != 0)
7804 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7805 else if ((imm6 & 0x08) != 0)
7806 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7807 else
7808 print_mve_undefined (info, UNDEF_SIZE_0);
7809
7810 func (stream, "%u", shiftAmount);
7811 }
7812
7813 static void
7814 print_vec_condition (struct disassemble_info *info, long given,
7815 enum mve_instructions matched_insn)
7816 {
7817 void *stream = info->stream;
7818 fprintf_ftype func = info->fprintf_func;
7819 long vec_cond = 0;
7820
7821 switch (matched_insn)
7822 {
7823 case MVE_VPT_FP_T1:
7824 case MVE_VCMP_FP_T1:
7825 vec_cond = (((given & 0x1000) >> 10)
7826 | ((given & 1) << 1)
7827 | ((given & 0x0080) >> 7));
7828 func (stream, "%s",vec_condnames[vec_cond]);
7829 break;
7830
7831 case MVE_VPT_FP_T2:
7832 case MVE_VCMP_FP_T2:
7833 vec_cond = (((given & 0x1000) >> 10)
7834 | ((given & 0x0020) >> 4)
7835 | ((given & 0x0080) >> 7));
7836 func (stream, "%s",vec_condnames[vec_cond]);
7837 break;
7838
7839 case MVE_VPT_VEC_T1:
7840 case MVE_VCMP_VEC_T1:
7841 vec_cond = (given & 0x0080) >> 7;
7842 func (stream, "%s",vec_condnames[vec_cond]);
7843 break;
7844
7845 case MVE_VPT_VEC_T2:
7846 case MVE_VCMP_VEC_T2:
7847 vec_cond = 2 | ((given & 0x0080) >> 7);
7848 func (stream, "%s",vec_condnames[vec_cond]);
7849 break;
7850
7851 case MVE_VPT_VEC_T3:
7852 case MVE_VCMP_VEC_T3:
7853 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7854 func (stream, "%s",vec_condnames[vec_cond]);
7855 break;
7856
7857 case MVE_VPT_VEC_T4:
7858 case MVE_VCMP_VEC_T4:
7859 vec_cond = (given & 0x0080) >> 7;
7860 func (stream, "%s",vec_condnames[vec_cond]);
7861 break;
7862
7863 case MVE_VPT_VEC_T5:
7864 case MVE_VCMP_VEC_T5:
7865 vec_cond = 2 | ((given & 0x0080) >> 7);
7866 func (stream, "%s",vec_condnames[vec_cond]);
7867 break;
7868
7869 case MVE_VPT_VEC_T6:
7870 case MVE_VCMP_VEC_T6:
7871 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7872 func (stream, "%s",vec_condnames[vec_cond]);
7873 break;
7874
7875 case MVE_NONE:
7876 case MVE_VPST:
7877 default:
7878 break;
7879 }
7880 }
7881
7882 #define W_BIT 21
7883 #define I_BIT 22
7884 #define U_BIT 23
7885 #define P_BIT 24
7886
7887 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7888 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7889 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7890 #define PRE_BIT_SET (given & (1 << P_BIT))
7891
7892
7893 /* Print one coprocessor instruction on INFO->STREAM.
7894 Return TRUE if the instuction matched, FALSE if this is not a
7895 recognised coprocessor instruction. */
7896
7897 static bfd_boolean
7898 print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
7899 bfd_vma pc,
7900 struct disassemble_info *info,
7901 long given,
7902 bfd_boolean thumb)
7903 {
7904 const struct sopcode32 *insn;
7905 void *stream = info->stream;
7906 fprintf_ftype func = info->fprintf_func;
7907 unsigned long mask;
7908 unsigned long value = 0;
7909 int cond;
7910 int cp_num;
7911 struct arm_private_data *private_data = info->private_data;
7912 arm_feature_set allowed_arches = ARM_ARCH_NONE;
7913 arm_feature_set arm_ext_v8_1m_main =
7914 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
7915
7916 allowed_arches = private_data->features;
7917
7918 for (insn = opcodes; insn->assembler; insn++)
7919 {
7920 unsigned long u_reg = 16;
7921 bfd_boolean is_unpredictable = FALSE;
7922 signed long value_in_comment = 0;
7923 const char *c;
7924
7925 if (ARM_FEATURE_ZERO (insn->arch))
7926 switch (insn->value)
7927 {
7928 case SENTINEL_IWMMXT_START:
7929 if (info->mach != bfd_mach_arm_XScale
7930 && info->mach != bfd_mach_arm_iWMMXt
7931 && info->mach != bfd_mach_arm_iWMMXt2)
7932 do
7933 insn++;
7934 while ((! ARM_FEATURE_ZERO (insn->arch))
7935 && insn->value != SENTINEL_IWMMXT_END);
7936 continue;
7937
7938 case SENTINEL_IWMMXT_END:
7939 continue;
7940
7941 case SENTINEL_GENERIC_START:
7942 allowed_arches = private_data->features;
7943 continue;
7944
7945 default:
7946 abort ();
7947 }
7948
7949 mask = insn->mask;
7950 value = insn->value;
7951 cp_num = (given >> 8) & 0xf;
7952
7953 if (thumb)
7954 {
7955 /* The high 4 bits are 0xe for Arm conditional instructions, and
7956 0xe for arm unconditional instructions. The rest of the
7957 encoding is the same. */
7958 mask |= 0xf0000000;
7959 value |= 0xe0000000;
7960 if (ifthen_state)
7961 cond = IFTHEN_COND;
7962 else
7963 cond = COND_UNCOND;
7964 }
7965 else
7966 {
7967 /* Only match unconditional instuctions against unconditional
7968 patterns. */
7969 if ((given & 0xf0000000) == 0xf0000000)
7970 {
7971 mask |= 0xf0000000;
7972 cond = COND_UNCOND;
7973 }
7974 else
7975 {
7976 cond = (given >> 28) & 0xf;
7977 if (cond == 0xe)
7978 cond = COND_UNCOND;
7979 }
7980 }
7981
7982 if ((insn->isa == T32 && !thumb)
7983 || (insn->isa == ARM && thumb))
7984 continue;
7985
7986 if ((given & mask) != value)
7987 continue;
7988
7989 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
7990 continue;
7991
7992 if (insn->value == 0xfe000010 /* mcr2 */
7993 || insn->value == 0xfe100010 /* mrc2 */
7994 || insn->value == 0xfc100000 /* ldc2 */
7995 || insn->value == 0xfc000000) /* stc2 */
7996 {
7997 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
7998 is_unpredictable = TRUE;
7999
8000 /* Armv8.1-M Mainline FP & MVE instructions. */
8001 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8002 && !ARM_CPU_IS_ANY (allowed_arches)
8003 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8004 continue;
8005
8006 }
8007 else if (insn->value == 0x0e000000 /* cdp */
8008 || insn->value == 0xfe000000 /* cdp2 */
8009 || insn->value == 0x0e000010 /* mcr */
8010 || insn->value == 0x0e100010 /* mrc */
8011 || insn->value == 0x0c100000 /* ldc */
8012 || insn->value == 0x0c000000) /* stc */
8013 {
8014 /* Floating-point instructions. */
8015 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8016 continue;
8017
8018 /* Armv8.1-M Mainline FP & MVE instructions. */
8019 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8020 && !ARM_CPU_IS_ANY (allowed_arches)
8021 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8022 continue;
8023 }
8024 else if ((insn->value == 0xec100f80 /* vldr (system register) */
8025 || insn->value == 0xec000f80) /* vstr (system register) */
8026 && arm_decode_field (given, 24, 24) == 0
8027 && arm_decode_field (given, 21, 21) == 0)
8028 /* If the P and W bits are both 0 then these encodings match the MVE
8029 VLDR and VSTR instructions, these are in a different table, so we
8030 don't let it match here. */
8031 continue;
8032
8033 for (c = insn->assembler; *c; c++)
8034 {
8035 if (*c == '%')
8036 {
8037 const char mod = *++c;
8038 switch (mod)
8039 {
8040 case '%':
8041 func (stream, "%%");
8042 break;
8043
8044 case 'A':
8045 case 'K':
8046 {
8047 int rn = (given >> 16) & 0xf;
8048 bfd_vma offset = given & 0xff;
8049
8050 if (mod == 'K')
8051 offset = given & 0x7f;
8052
8053 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8054
8055 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8056 {
8057 /* Not unindexed. The offset is scaled. */
8058 if (cp_num == 9)
8059 /* vldr.16/vstr.16 will shift the address
8060 left by 1 bit only. */
8061 offset = offset * 2;
8062 else
8063 offset = offset * 4;
8064
8065 if (NEGATIVE_BIT_SET)
8066 offset = - offset;
8067 if (rn != 15)
8068 value_in_comment = offset;
8069 }
8070
8071 if (PRE_BIT_SET)
8072 {
8073 if (offset)
8074 func (stream, ", #%d]%s",
8075 (int) offset,
8076 WRITEBACK_BIT_SET ? "!" : "");
8077 else if (NEGATIVE_BIT_SET)
8078 func (stream, ", #-0]");
8079 else
8080 func (stream, "]");
8081 }
8082 else
8083 {
8084 func (stream, "]");
8085
8086 if (WRITEBACK_BIT_SET)
8087 {
8088 if (offset)
8089 func (stream, ", #%d", (int) offset);
8090 else if (NEGATIVE_BIT_SET)
8091 func (stream, ", #-0");
8092 }
8093 else
8094 {
8095 func (stream, ", {%s%d}",
8096 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
8097 (int) offset);
8098 value_in_comment = offset;
8099 }
8100 }
8101 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8102 {
8103 func (stream, "\t; ");
8104 /* For unaligned PCs, apply off-by-alignment
8105 correction. */
8106 info->print_address_func (offset + pc
8107 + info->bytes_per_chunk * 2
8108 - (pc & 3),
8109 info);
8110 }
8111 }
8112 break;
8113
8114 case 'B':
8115 {
8116 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8117 int offset = (given >> 1) & 0x3f;
8118
8119 if (offset == 1)
8120 func (stream, "{d%d}", regno);
8121 else if (regno + offset > 32)
8122 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
8123 else
8124 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
8125 }
8126 break;
8127
8128 case 'C':
8129 {
8130 bfd_boolean single = ((given >> 8) & 1) == 0;
8131 char reg_prefix = single ? 's' : 'd';
8132 int Dreg = (given >> 22) & 0x1;
8133 int Vdreg = (given >> 12) & 0xf;
8134 int reg = single ? ((Vdreg << 1) | Dreg)
8135 : ((Dreg << 4) | Vdreg);
8136 int num = (given >> (single ? 0 : 1)) & 0x7f;
8137 int maxreg = single ? 31 : 15;
8138 int topreg = reg + num - 1;
8139
8140 if (!num)
8141 func (stream, "{VPR}");
8142 else if (num == 1)
8143 func (stream, "{%c%d, VPR}", reg_prefix, reg);
8144 else if (topreg > maxreg)
8145 func (stream, "{%c%d-<overflow reg d%d, VPR}",
8146 reg_prefix, reg, single ? topreg >> 1 : topreg);
8147 else
8148 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
8149 reg_prefix, topreg);
8150 }
8151 break;
8152
8153 case 'u':
8154 if (cond != COND_UNCOND)
8155 is_unpredictable = TRUE;
8156
8157 /* Fall through. */
8158 case 'c':
8159 if (cond != COND_UNCOND && cp_num == 9)
8160 is_unpredictable = TRUE;
8161
8162 func (stream, "%s", arm_conditional[cond]);
8163 break;
8164
8165 case 'I':
8166 /* Print a Cirrus/DSP shift immediate. */
8167 /* Immediates are 7bit signed ints with bits 0..3 in
8168 bits 0..3 of opcode and bits 4..6 in bits 5..7
8169 of opcode. */
8170 {
8171 int imm;
8172
8173 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8174
8175 /* Is ``imm'' a negative number? */
8176 if (imm & 0x40)
8177 imm -= 0x80;
8178
8179 func (stream, "%d", imm);
8180 }
8181
8182 break;
8183
8184 case 'J':
8185 {
8186 unsigned long regno
8187 = arm_decode_field_multiple (given, 13, 15, 22, 22);
8188
8189 switch (regno)
8190 {
8191 case 0x1:
8192 func (stream, "FPSCR");
8193 break;
8194 case 0x2:
8195 func (stream, "FPSCR_nzcvqc");
8196 break;
8197 case 0xc:
8198 func (stream, "VPR");
8199 break;
8200 case 0xd:
8201 func (stream, "P0");
8202 break;
8203 case 0xe:
8204 func (stream, "FPCXTNS");
8205 break;
8206 case 0xf:
8207 func (stream, "FPCXTS");
8208 break;
8209 default:
8210 func (stream, "<invalid reg %lu>", regno);
8211 break;
8212 }
8213 }
8214 break;
8215
8216 case 'F':
8217 switch (given & 0x00408000)
8218 {
8219 case 0:
8220 func (stream, "4");
8221 break;
8222 case 0x8000:
8223 func (stream, "1");
8224 break;
8225 case 0x00400000:
8226 func (stream, "2");
8227 break;
8228 default:
8229 func (stream, "3");
8230 }
8231 break;
8232
8233 case 'P':
8234 switch (given & 0x00080080)
8235 {
8236 case 0:
8237 func (stream, "s");
8238 break;
8239 case 0x80:
8240 func (stream, "d");
8241 break;
8242 case 0x00080000:
8243 func (stream, "e");
8244 break;
8245 default:
8246 func (stream, _("<illegal precision>"));
8247 break;
8248 }
8249 break;
8250
8251 case 'Q':
8252 switch (given & 0x00408000)
8253 {
8254 case 0:
8255 func (stream, "s");
8256 break;
8257 case 0x8000:
8258 func (stream, "d");
8259 break;
8260 case 0x00400000:
8261 func (stream, "e");
8262 break;
8263 default:
8264 func (stream, "p");
8265 break;
8266 }
8267 break;
8268
8269 case 'R':
8270 switch (given & 0x60)
8271 {
8272 case 0:
8273 break;
8274 case 0x20:
8275 func (stream, "p");
8276 break;
8277 case 0x40:
8278 func (stream, "m");
8279 break;
8280 default:
8281 func (stream, "z");
8282 break;
8283 }
8284 break;
8285
8286 case '0': case '1': case '2': case '3': case '4':
8287 case '5': case '6': case '7': case '8': case '9':
8288 {
8289 int width;
8290
8291 c = arm_decode_bitfield (c, given, &value, &width);
8292
8293 switch (*c)
8294 {
8295 case 'R':
8296 if (value == 15)
8297 is_unpredictable = TRUE;
8298 /* Fall through. */
8299 case 'r':
8300 if (c[1] == 'u')
8301 {
8302 /* Eat the 'u' character. */
8303 ++ c;
8304
8305 if (u_reg == value)
8306 is_unpredictable = TRUE;
8307 u_reg = value;
8308 }
8309 func (stream, "%s", arm_regnames[value]);
8310 break;
8311 case 'V':
8312 if (given & (1 << 6))
8313 goto Q;
8314 /* FALLTHROUGH */
8315 case 'D':
8316 func (stream, "d%ld", value);
8317 break;
8318 case 'Q':
8319 Q:
8320 if (value & 1)
8321 func (stream, "<illegal reg q%ld.5>", value >> 1);
8322 else
8323 func (stream, "q%ld", value >> 1);
8324 break;
8325 case 'd':
8326 func (stream, "%ld", value);
8327 value_in_comment = value;
8328 break;
8329 case 'E':
8330 {
8331 /* Converts immediate 8 bit back to float value. */
8332 unsigned floatVal = (value & 0x80) << 24
8333 | (value & 0x3F) << 19
8334 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8335
8336 /* Quarter float have a maximum value of 31.0.
8337 Get floating point value multiplied by 1e7.
8338 The maximum value stays in limit of a 32-bit int. */
8339 unsigned decVal =
8340 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8341 (16 + (value & 0xF));
8342
8343 if (!(decVal % 1000000))
8344 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
8345 floatVal, value & 0x80 ? '-' : ' ',
8346 decVal / 10000000,
8347 decVal % 10000000 / 1000000);
8348 else if (!(decVal % 10000))
8349 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
8350 floatVal, value & 0x80 ? '-' : ' ',
8351 decVal / 10000000,
8352 decVal % 10000000 / 10000);
8353 else
8354 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
8355 floatVal, value & 0x80 ? '-' : ' ',
8356 decVal / 10000000, decVal % 10000000);
8357 break;
8358 }
8359 case 'k':
8360 {
8361 int from = (given & (1 << 7)) ? 32 : 16;
8362 func (stream, "%ld", from - value);
8363 }
8364 break;
8365
8366 case 'f':
8367 if (value > 7)
8368 func (stream, "#%s", arm_fp_const[value & 7]);
8369 else
8370 func (stream, "f%ld", value);
8371 break;
8372
8373 case 'w':
8374 if (width == 2)
8375 func (stream, "%s", iwmmxt_wwnames[value]);
8376 else
8377 func (stream, "%s", iwmmxt_wwssnames[value]);
8378 break;
8379
8380 case 'g':
8381 func (stream, "%s", iwmmxt_regnames[value]);
8382 break;
8383 case 'G':
8384 func (stream, "%s", iwmmxt_cregnames[value]);
8385 break;
8386
8387 case 'x':
8388 func (stream, "0x%lx", (value & 0xffffffffUL));
8389 break;
8390
8391 case 'c':
8392 switch (value)
8393 {
8394 case 0:
8395 func (stream, "eq");
8396 break;
8397
8398 case 1:
8399 func (stream, "vs");
8400 break;
8401
8402 case 2:
8403 func (stream, "ge");
8404 break;
8405
8406 case 3:
8407 func (stream, "gt");
8408 break;
8409
8410 default:
8411 func (stream, "??");
8412 break;
8413 }
8414 break;
8415
8416 case '`':
8417 c++;
8418 if (value == 0)
8419 func (stream, "%c", *c);
8420 break;
8421 case '\'':
8422 c++;
8423 if (value == ((1ul << width) - 1))
8424 func (stream, "%c", *c);
8425 break;
8426 case '?':
8427 func (stream, "%c", c[(1 << width) - (int) value]);
8428 c += 1 << width;
8429 break;
8430 default:
8431 abort ();
8432 }
8433 }
8434 break;
8435
8436 case 'y':
8437 case 'z':
8438 {
8439 int single = *c++ == 'y';
8440 int regno;
8441
8442 switch (*c)
8443 {
8444 case '4': /* Sm pair */
8445 case '0': /* Sm, Dm */
8446 regno = given & 0x0000000f;
8447 if (single)
8448 {
8449 regno <<= 1;
8450 regno += (given >> 5) & 1;
8451 }
8452 else
8453 regno += ((given >> 5) & 1) << 4;
8454 break;
8455
8456 case '1': /* Sd, Dd */
8457 regno = (given >> 12) & 0x0000000f;
8458 if (single)
8459 {
8460 regno <<= 1;
8461 regno += (given >> 22) & 1;
8462 }
8463 else
8464 regno += ((given >> 22) & 1) << 4;
8465 break;
8466
8467 case '2': /* Sn, Dn */
8468 regno = (given >> 16) & 0x0000000f;
8469 if (single)
8470 {
8471 regno <<= 1;
8472 regno += (given >> 7) & 1;
8473 }
8474 else
8475 regno += ((given >> 7) & 1) << 4;
8476 break;
8477
8478 case '3': /* List */
8479 func (stream, "{");
8480 regno = (given >> 12) & 0x0000000f;
8481 if (single)
8482 {
8483 regno <<= 1;
8484 regno += (given >> 22) & 1;
8485 }
8486 else
8487 regno += ((given >> 22) & 1) << 4;
8488 break;
8489
8490 default:
8491 abort ();
8492 }
8493
8494 func (stream, "%c%d", single ? 's' : 'd', regno);
8495
8496 if (*c == '3')
8497 {
8498 int count = given & 0xff;
8499
8500 if (single == 0)
8501 count >>= 1;
8502
8503 if (--count)
8504 {
8505 func (stream, "-%c%d",
8506 single ? 's' : 'd',
8507 regno + count);
8508 }
8509
8510 func (stream, "}");
8511 }
8512 else if (*c == '4')
8513 func (stream, ", %c%d", single ? 's' : 'd',
8514 regno + 1);
8515 }
8516 break;
8517
8518 case 'L':
8519 switch (given & 0x00400100)
8520 {
8521 case 0x00000000: func (stream, "b"); break;
8522 case 0x00400000: func (stream, "h"); break;
8523 case 0x00000100: func (stream, "w"); break;
8524 case 0x00400100: func (stream, "d"); break;
8525 default:
8526 break;
8527 }
8528 break;
8529
8530 case 'Z':
8531 {
8532 /* given (20, 23) | given (0, 3) */
8533 value = ((given >> 16) & 0xf0) | (given & 0xf);
8534 func (stream, "%d", (int) value);
8535 }
8536 break;
8537
8538 case 'l':
8539 /* This is like the 'A' operator, except that if
8540 the width field "M" is zero, then the offset is
8541 *not* multiplied by four. */
8542 {
8543 int offset = given & 0xff;
8544 int multiplier = (given & 0x00000100) ? 4 : 1;
8545
8546 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8547
8548 if (multiplier > 1)
8549 {
8550 value_in_comment = offset * multiplier;
8551 if (NEGATIVE_BIT_SET)
8552 value_in_comment = - value_in_comment;
8553 }
8554
8555 if (offset)
8556 {
8557 if (PRE_BIT_SET)
8558 func (stream, ", #%s%d]%s",
8559 NEGATIVE_BIT_SET ? "-" : "",
8560 offset * multiplier,
8561 WRITEBACK_BIT_SET ? "!" : "");
8562 else
8563 func (stream, "], #%s%d",
8564 NEGATIVE_BIT_SET ? "-" : "",
8565 offset * multiplier);
8566 }
8567 else
8568 func (stream, "]");
8569 }
8570 break;
8571
8572 case 'r':
8573 {
8574 int imm4 = (given >> 4) & 0xf;
8575 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8576 int ubit = ! NEGATIVE_BIT_SET;
8577 const char *rm = arm_regnames [given & 0xf];
8578 const char *rn = arm_regnames [(given >> 16) & 0xf];
8579
8580 switch (puw_bits)
8581 {
8582 case 1:
8583 case 3:
8584 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8585 if (imm4)
8586 func (stream, ", lsl #%d", imm4);
8587 break;
8588
8589 case 4:
8590 case 5:
8591 case 6:
8592 case 7:
8593 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8594 if (imm4 > 0)
8595 func (stream, ", lsl #%d", imm4);
8596 func (stream, "]");
8597 if (puw_bits == 5 || puw_bits == 7)
8598 func (stream, "!");
8599 break;
8600
8601 default:
8602 func (stream, "INVALID");
8603 }
8604 }
8605 break;
8606
8607 case 'i':
8608 {
8609 long imm5;
8610 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8611 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8612 }
8613 break;
8614
8615 default:
8616 abort ();
8617 }
8618 }
8619 else
8620 func (stream, "%c", *c);
8621 }
8622
8623 if (value_in_comment > 32 || value_in_comment < -16)
8624 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
8625
8626 if (is_unpredictable)
8627 func (stream, UNPREDICTABLE_INSTRUCTION);
8628
8629 return TRUE;
8630 }
8631 return FALSE;
8632 }
8633
8634 static bfd_boolean
8635 print_insn_coprocessor (bfd_vma pc,
8636 struct disassemble_info *info,
8637 long given,
8638 bfd_boolean thumb)
8639 {
8640 return print_insn_coprocessor_1 (coprocessor_opcodes,
8641 pc, info, given, thumb);
8642 }
8643
8644 static bfd_boolean
8645 print_insn_generic_coprocessor (bfd_vma pc,
8646 struct disassemble_info *info,
8647 long given,
8648 bfd_boolean thumb)
8649 {
8650 return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
8651 pc, info, given, thumb);
8652 }
8653
8654 /* Decodes and prints ARM addressing modes. Returns the offset
8655 used in the address, if any, if it is worthwhile printing the
8656 offset as a hexadecimal value in a comment at the end of the
8657 line of disassembly. */
8658
8659 static signed long
8660 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8661 {
8662 void *stream = info->stream;
8663 fprintf_ftype func = info->fprintf_func;
8664 bfd_vma offset = 0;
8665
8666 if (((given & 0x000f0000) == 0x000f0000)
8667 && ((given & 0x02000000) == 0))
8668 {
8669 offset = given & 0xfff;
8670
8671 func (stream, "[pc");
8672
8673 if (PRE_BIT_SET)
8674 {
8675 /* Pre-indexed. Elide offset of positive zero when
8676 non-writeback. */
8677 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8678 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8679
8680 if (NEGATIVE_BIT_SET)
8681 offset = -offset;
8682
8683 offset += pc + 8;
8684
8685 /* Cope with the possibility of write-back
8686 being used. Probably a very dangerous thing
8687 for the programmer to do, but who are we to
8688 argue ? */
8689 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
8690 }
8691 else /* Post indexed. */
8692 {
8693 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8694
8695 /* Ie ignore the offset. */
8696 offset = pc + 8;
8697 }
8698
8699 func (stream, "\t; ");
8700 info->print_address_func (offset, info);
8701 offset = 0;
8702 }
8703 else
8704 {
8705 func (stream, "[%s",
8706 arm_regnames[(given >> 16) & 0xf]);
8707
8708 if (PRE_BIT_SET)
8709 {
8710 if ((given & 0x02000000) == 0)
8711 {
8712 /* Elide offset of positive zero when non-writeback. */
8713 offset = given & 0xfff;
8714 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8715 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8716 }
8717 else
8718 {
8719 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
8720 arm_decode_shift (given, func, stream, TRUE);
8721 }
8722
8723 func (stream, "]%s",
8724 WRITEBACK_BIT_SET ? "!" : "");
8725 }
8726 else
8727 {
8728 if ((given & 0x02000000) == 0)
8729 {
8730 /* Always show offset. */
8731 offset = given & 0xfff;
8732 func (stream, "], #%s%d",
8733 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8734 }
8735 else
8736 {
8737 func (stream, "], %s",
8738 NEGATIVE_BIT_SET ? "-" : "");
8739 arm_decode_shift (given, func, stream, TRUE);
8740 }
8741 }
8742 if (NEGATIVE_BIT_SET)
8743 offset = -offset;
8744 }
8745
8746 return (signed long) offset;
8747 }
8748
8749 /* Print one neon instruction on INFO->STREAM.
8750 Return TRUE if the instuction matched, FALSE if this is not a
8751 recognised neon instruction. */
8752
8753 static bfd_boolean
8754 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
8755 {
8756 const struct opcode32 *insn;
8757 void *stream = info->stream;
8758 fprintf_ftype func = info->fprintf_func;
8759
8760 if (thumb)
8761 {
8762 if ((given & 0xef000000) == 0xef000000)
8763 {
8764 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
8765 unsigned long bit28 = given & (1 << 28);
8766
8767 given &= 0x00ffffff;
8768 if (bit28)
8769 given |= 0xf3000000;
8770 else
8771 given |= 0xf2000000;
8772 }
8773 else if ((given & 0xff000000) == 0xf9000000)
8774 given ^= 0xf9000000 ^ 0xf4000000;
8775 /* vdup is also a valid neon instruction. */
8776 else if ((given & 0xff910f5f) != 0xee800b10)
8777 return FALSE;
8778 }
8779
8780 for (insn = neon_opcodes; insn->assembler; insn++)
8781 {
8782 if ((given & insn->mask) == insn->value)
8783 {
8784 signed long value_in_comment = 0;
8785 bfd_boolean is_unpredictable = FALSE;
8786 const char *c;
8787
8788 for (c = insn->assembler; *c; c++)
8789 {
8790 if (*c == '%')
8791 {
8792 switch (*++c)
8793 {
8794 case '%':
8795 func (stream, "%%");
8796 break;
8797
8798 case 'u':
8799 if (thumb && ifthen_state)
8800 is_unpredictable = TRUE;
8801
8802 /* Fall through. */
8803 case 'c':
8804 if (thumb && ifthen_state)
8805 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8806 break;
8807
8808 case 'A':
8809 {
8810 static const unsigned char enc[16] =
8811 {
8812 0x4, 0x14, /* st4 0,1 */
8813 0x4, /* st1 2 */
8814 0x4, /* st2 3 */
8815 0x3, /* st3 4 */
8816 0x13, /* st3 5 */
8817 0x3, /* st1 6 */
8818 0x1, /* st1 7 */
8819 0x2, /* st2 8 */
8820 0x12, /* st2 9 */
8821 0x2, /* st1 10 */
8822 0, 0, 0, 0, 0
8823 };
8824 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8825 int rn = ((given >> 16) & 0xf);
8826 int rm = ((given >> 0) & 0xf);
8827 int align = ((given >> 4) & 0x3);
8828 int type = ((given >> 8) & 0xf);
8829 int n = enc[type] & 0xf;
8830 int stride = (enc[type] >> 4) + 1;
8831 int ix;
8832
8833 func (stream, "{");
8834 if (stride > 1)
8835 for (ix = 0; ix != n; ix++)
8836 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
8837 else if (n == 1)
8838 func (stream, "d%d", rd);
8839 else
8840 func (stream, "d%d-d%d", rd, rd + n - 1);
8841 func (stream, "}, [%s", arm_regnames[rn]);
8842 if (align)
8843 func (stream, " :%d", 32 << align);
8844 func (stream, "]");
8845 if (rm == 0xd)
8846 func (stream, "!");
8847 else if (rm != 0xf)
8848 func (stream, ", %s", arm_regnames[rm]);
8849 }
8850 break;
8851
8852 case 'B':
8853 {
8854 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8855 int rn = ((given >> 16) & 0xf);
8856 int rm = ((given >> 0) & 0xf);
8857 int idx_align = ((given >> 4) & 0xf);
8858 int align = 0;
8859 int size = ((given >> 10) & 0x3);
8860 int idx = idx_align >> (size + 1);
8861 int length = ((given >> 8) & 3) + 1;
8862 int stride = 1;
8863 int i;
8864
8865 if (length > 1 && size > 0)
8866 stride = (idx_align & (1 << size)) ? 2 : 1;
8867
8868 switch (length)
8869 {
8870 case 1:
8871 {
8872 int amask = (1 << size) - 1;
8873 if ((idx_align & (1 << size)) != 0)
8874 return FALSE;
8875 if (size > 0)
8876 {
8877 if ((idx_align & amask) == amask)
8878 align = 8 << size;
8879 else if ((idx_align & amask) != 0)
8880 return FALSE;
8881 }
8882 }
8883 break;
8884
8885 case 2:
8886 if (size == 2 && (idx_align & 2) != 0)
8887 return FALSE;
8888 align = (idx_align & 1) ? 16 << size : 0;
8889 break;
8890
8891 case 3:
8892 if ((size == 2 && (idx_align & 3) != 0)
8893 || (idx_align & 1) != 0)
8894 return FALSE;
8895 break;
8896
8897 case 4:
8898 if (size == 2)
8899 {
8900 if ((idx_align & 3) == 3)
8901 return FALSE;
8902 align = (idx_align & 3) * 64;
8903 }
8904 else
8905 align = (idx_align & 1) ? 32 << size : 0;
8906 break;
8907
8908 default:
8909 abort ();
8910 }
8911
8912 func (stream, "{");
8913 for (i = 0; i < length; i++)
8914 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
8915 rd + i * stride, idx);
8916 func (stream, "}, [%s", arm_regnames[rn]);
8917 if (align)
8918 func (stream, " :%d", align);
8919 func (stream, "]");
8920 if (rm == 0xd)
8921 func (stream, "!");
8922 else if (rm != 0xf)
8923 func (stream, ", %s", arm_regnames[rm]);
8924 }
8925 break;
8926
8927 case 'C':
8928 {
8929 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8930 int rn = ((given >> 16) & 0xf);
8931 int rm = ((given >> 0) & 0xf);
8932 int align = ((given >> 4) & 0x1);
8933 int size = ((given >> 6) & 0x3);
8934 int type = ((given >> 8) & 0x3);
8935 int n = type + 1;
8936 int stride = ((given >> 5) & 0x1);
8937 int ix;
8938
8939 if (stride && (n == 1))
8940 n++;
8941 else
8942 stride++;
8943
8944 func (stream, "{");
8945 if (stride > 1)
8946 for (ix = 0; ix != n; ix++)
8947 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
8948 else if (n == 1)
8949 func (stream, "d%d[]", rd);
8950 else
8951 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
8952 func (stream, "}, [%s", arm_regnames[rn]);
8953 if (align)
8954 {
8955 align = (8 * (type + 1)) << size;
8956 if (type == 3)
8957 align = (size > 1) ? align >> 1 : align;
8958 if (type == 2 || (type == 0 && !size))
8959 func (stream, " :<bad align %d>", align);
8960 else
8961 func (stream, " :%d", align);
8962 }
8963 func (stream, "]");
8964 if (rm == 0xd)
8965 func (stream, "!");
8966 else if (rm != 0xf)
8967 func (stream, ", %s", arm_regnames[rm]);
8968 }
8969 break;
8970
8971 case 'D':
8972 {
8973 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
8974 int size = (given >> 20) & 3;
8975 int reg = raw_reg & ((4 << size) - 1);
8976 int ix = raw_reg >> size >> 2;
8977
8978 func (stream, "d%d[%d]", reg, ix);
8979 }
8980 break;
8981
8982 case 'E':
8983 /* Neon encoded constant for mov, mvn, vorr, vbic. */
8984 {
8985 int bits = 0;
8986 int cmode = (given >> 8) & 0xf;
8987 int op = (given >> 5) & 0x1;
8988 unsigned long value = 0, hival = 0;
8989 unsigned shift;
8990 int size = 0;
8991 int isfloat = 0;
8992
8993 bits |= ((given >> 24) & 1) << 7;
8994 bits |= ((given >> 16) & 7) << 4;
8995 bits |= ((given >> 0) & 15) << 0;
8996
8997 if (cmode < 8)
8998 {
8999 shift = (cmode >> 1) & 3;
9000 value = (unsigned long) bits << (8 * shift);
9001 size = 32;
9002 }
9003 else if (cmode < 12)
9004 {
9005 shift = (cmode >> 1) & 1;
9006 value = (unsigned long) bits << (8 * shift);
9007 size = 16;
9008 }
9009 else if (cmode < 14)
9010 {
9011 shift = (cmode & 1) + 1;
9012 value = (unsigned long) bits << (8 * shift);
9013 value |= (1ul << (8 * shift)) - 1;
9014 size = 32;
9015 }
9016 else if (cmode == 14)
9017 {
9018 if (op)
9019 {
9020 /* Bit replication into bytes. */
9021 int ix;
9022 unsigned long mask;
9023
9024 value = 0;
9025 hival = 0;
9026 for (ix = 7; ix >= 0; ix--)
9027 {
9028 mask = ((bits >> ix) & 1) ? 0xff : 0;
9029 if (ix <= 3)
9030 value = (value << 8) | mask;
9031 else
9032 hival = (hival << 8) | mask;
9033 }
9034 size = 64;
9035 }
9036 else
9037 {
9038 /* Byte replication. */
9039 value = (unsigned long) bits;
9040 size = 8;
9041 }
9042 }
9043 else if (!op)
9044 {
9045 /* Floating point encoding. */
9046 int tmp;
9047
9048 value = (unsigned long) (bits & 0x7f) << 19;
9049 value |= (unsigned long) (bits & 0x80) << 24;
9050 tmp = bits & 0x40 ? 0x3c : 0x40;
9051 value |= (unsigned long) tmp << 24;
9052 size = 32;
9053 isfloat = 1;
9054 }
9055 else
9056 {
9057 func (stream, "<illegal constant %.8x:%x:%x>",
9058 bits, cmode, op);
9059 size = 32;
9060 break;
9061 }
9062 switch (size)
9063 {
9064 case 8:
9065 func (stream, "#%ld\t; 0x%.2lx", value, value);
9066 break;
9067
9068 case 16:
9069 func (stream, "#%ld\t; 0x%.4lx", value, value);
9070 break;
9071
9072 case 32:
9073 if (isfloat)
9074 {
9075 unsigned char valbytes[4];
9076 double fvalue;
9077
9078 /* Do this a byte at a time so we don't have to
9079 worry about the host's endianness. */
9080 valbytes[0] = value & 0xff;
9081 valbytes[1] = (value >> 8) & 0xff;
9082 valbytes[2] = (value >> 16) & 0xff;
9083 valbytes[3] = (value >> 24) & 0xff;
9084
9085 floatformat_to_double
9086 (& floatformat_ieee_single_little, valbytes,
9087 & fvalue);
9088
9089 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
9090 value);
9091 }
9092 else
9093 func (stream, "#%ld\t; 0x%.8lx",
9094 (long) (((value & 0x80000000L) != 0)
9095 ? value | ~0xffffffffL : value),
9096 value);
9097 break;
9098
9099 case 64:
9100 func (stream, "#0x%.8lx%.8lx", hival, value);
9101 break;
9102
9103 default:
9104 abort ();
9105 }
9106 }
9107 break;
9108
9109 case 'F':
9110 {
9111 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9112 int num = (given >> 8) & 0x3;
9113
9114 if (!num)
9115 func (stream, "{d%d}", regno);
9116 else if (num + regno >= 32)
9117 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
9118 else
9119 func (stream, "{d%d-d%d}", regno, regno + num);
9120 }
9121 break;
9122
9123
9124 case '0': case '1': case '2': case '3': case '4':
9125 case '5': case '6': case '7': case '8': case '9':
9126 {
9127 int width;
9128 unsigned long value;
9129
9130 c = arm_decode_bitfield (c, given, &value, &width);
9131
9132 switch (*c)
9133 {
9134 case 'r':
9135 func (stream, "%s", arm_regnames[value]);
9136 break;
9137 case 'd':
9138 func (stream, "%ld", value);
9139 value_in_comment = value;
9140 break;
9141 case 'e':
9142 func (stream, "%ld", (1ul << width) - value);
9143 break;
9144
9145 case 'S':
9146 case 'T':
9147 case 'U':
9148 /* Various width encodings. */
9149 {
9150 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9151 int limit;
9152 unsigned low, high;
9153
9154 c++;
9155 if (*c >= '0' && *c <= '9')
9156 limit = *c - '0';
9157 else if (*c >= 'a' && *c <= 'f')
9158 limit = *c - 'a' + 10;
9159 else
9160 abort ();
9161 low = limit >> 2;
9162 high = limit & 3;
9163
9164 if (value < low || value > high)
9165 func (stream, "<illegal width %d>", base << value);
9166 else
9167 func (stream, "%d", base << value);
9168 }
9169 break;
9170 case 'R':
9171 if (given & (1 << 6))
9172 goto Q;
9173 /* FALLTHROUGH */
9174 case 'D':
9175 func (stream, "d%ld", value);
9176 break;
9177 case 'Q':
9178 Q:
9179 if (value & 1)
9180 func (stream, "<illegal reg q%ld.5>", value >> 1);
9181 else
9182 func (stream, "q%ld", value >> 1);
9183 break;
9184
9185 case '`':
9186 c++;
9187 if (value == 0)
9188 func (stream, "%c", *c);
9189 break;
9190 case '\'':
9191 c++;
9192 if (value == ((1ul << width) - 1))
9193 func (stream, "%c", *c);
9194 break;
9195 case '?':
9196 func (stream, "%c", c[(1 << width) - (int) value]);
9197 c += 1 << width;
9198 break;
9199 default:
9200 abort ();
9201 }
9202 }
9203 break;
9204
9205 default:
9206 abort ();
9207 }
9208 }
9209 else
9210 func (stream, "%c", *c);
9211 }
9212
9213 if (value_in_comment > 32 || value_in_comment < -16)
9214 func (stream, "\t; 0x%lx", value_in_comment);
9215
9216 if (is_unpredictable)
9217 func (stream, UNPREDICTABLE_INSTRUCTION);
9218
9219 return TRUE;
9220 }
9221 }
9222 return FALSE;
9223 }
9224
9225 /* Print one mve instruction on INFO->STREAM.
9226 Return TRUE if the instuction matched, FALSE if this is not a
9227 recognised mve instruction. */
9228
9229 static bfd_boolean
9230 print_insn_mve (struct disassemble_info *info, long given)
9231 {
9232 const struct mopcode32 *insn;
9233 void *stream = info->stream;
9234 fprintf_ftype func = info->fprintf_func;
9235
9236 for (insn = mve_opcodes; insn->assembler; insn++)
9237 {
9238 if (((given & insn->mask) == insn->value)
9239 && !is_mve_encoding_conflict (given, insn->mve_op))
9240 {
9241 signed long value_in_comment = 0;
9242 bfd_boolean is_unpredictable = FALSE;
9243 bfd_boolean is_undefined = FALSE;
9244 const char *c;
9245 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9246 enum mve_undefined undefined_cond = UNDEF_NONE;
9247
9248 /* Most vector mve instruction are illegal in a it block.
9249 There are a few exceptions; check for them. */
9250 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9251 {
9252 is_unpredictable = TRUE;
9253 unpredictable_cond = UNPRED_IT_BLOCK;
9254 }
9255 else if (is_mve_unpredictable (given, insn->mve_op,
9256 &unpredictable_cond))
9257 is_unpredictable = TRUE;
9258
9259 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9260 is_undefined = TRUE;
9261
9262 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9263 i.e "VMOV Qd, Qm". */
9264 if ((insn->mve_op == MVE_VORR_REG)
9265 && (arm_decode_field (given, 1, 3)
9266 == arm_decode_field (given, 17, 19)))
9267 continue;
9268
9269 for (c = insn->assembler; *c; c++)
9270 {
9271 if (*c == '%')
9272 {
9273 switch (*++c)
9274 {
9275 case '%':
9276 func (stream, "%%");
9277 break;
9278
9279 case 'a':
9280 /* Don't print anything for '+' as it is implied. */
9281 if (arm_decode_field (given, 23, 23) == 0)
9282 func (stream, "-");
9283 break;
9284
9285 case 'c':
9286 if (ifthen_state)
9287 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9288 break;
9289
9290 case 'd':
9291 print_mve_vld_str_addr (info, given, insn->mve_op);
9292 break;
9293
9294 case 'i':
9295 {
9296 long mve_mask = mve_extract_pred_mask (given);
9297 func (stream, "%s", mve_predicatenames[mve_mask]);
9298 }
9299 break;
9300
9301 case 'j':
9302 {
9303 unsigned int imm5 = 0;
9304 imm5 |= arm_decode_field (given, 6, 7);
9305 imm5 |= (arm_decode_field (given, 12, 14) << 2);
9306 func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
9307 }
9308 break;
9309
9310 case 'k':
9311 func (stream, "#%u",
9312 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9313 break;
9314
9315 case 'n':
9316 print_vec_condition (info, given, insn->mve_op);
9317 break;
9318
9319 case 'o':
9320 if (arm_decode_field (given, 0, 0) == 1)
9321 {
9322 unsigned long size
9323 = arm_decode_field (given, 4, 4)
9324 | (arm_decode_field (given, 6, 6) << 1);
9325
9326 func (stream, ", uxtw #%lu", size);
9327 }
9328 break;
9329
9330 case 'm':
9331 print_mve_rounding_mode (info, given, insn->mve_op);
9332 break;
9333
9334 case 's':
9335 print_mve_vcvt_size (info, given, insn->mve_op);
9336 break;
9337
9338 case 'u':
9339 {
9340 unsigned long op1 = arm_decode_field (given, 21, 22);
9341
9342 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9343 {
9344 /* Check for signed. */
9345 if (arm_decode_field (given, 23, 23) == 0)
9346 {
9347 /* We don't print 's' for S32. */
9348 if ((arm_decode_field (given, 5, 6) == 0)
9349 && ((op1 == 0) || (op1 == 1)))
9350 ;
9351 else
9352 func (stream, "s");
9353 }
9354 else
9355 func (stream, "u");
9356 }
9357 else
9358 {
9359 if (arm_decode_field (given, 28, 28) == 0)
9360 func (stream, "s");
9361 else
9362 func (stream, "u");
9363 }
9364 }
9365 break;
9366
9367 case 'v':
9368 print_instruction_predicate (info);
9369 break;
9370
9371 case 'w':
9372 if (arm_decode_field (given, 21, 21) == 1)
9373 func (stream, "!");
9374 break;
9375
9376 case 'B':
9377 print_mve_register_blocks (info, given, insn->mve_op);
9378 break;
9379
9380 case 'E':
9381 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9382
9383 print_simd_imm8 (info, given, 28, insn);
9384 break;
9385
9386 case 'N':
9387 print_mve_vmov_index (info, given);
9388 break;
9389
9390 case 'T':
9391 if (arm_decode_field (given, 12, 12) == 0)
9392 func (stream, "b");
9393 else
9394 func (stream, "t");
9395 break;
9396
9397 case 'X':
9398 if (arm_decode_field (given, 12, 12) == 1)
9399 func (stream, "x");
9400 break;
9401
9402 case '0': case '1': case '2': case '3': case '4':
9403 case '5': case '6': case '7': case '8': case '9':
9404 {
9405 int width;
9406 unsigned long value;
9407
9408 c = arm_decode_bitfield (c, given, &value, &width);
9409
9410 switch (*c)
9411 {
9412 case 'Z':
9413 if (value == 13)
9414 is_unpredictable = TRUE;
9415 else if (value == 15)
9416 func (stream, "zr");
9417 else
9418 func (stream, "%s", arm_regnames[value]);
9419 break;
9420
9421 case 'c':
9422 func (stream, "%s", arm_conditional[value]);
9423 break;
9424
9425 case 'C':
9426 value ^= 1;
9427 func (stream, "%s", arm_conditional[value]);
9428 break;
9429
9430 case 'S':
9431 if (value == 13 || value == 15)
9432 is_unpredictable = TRUE;
9433 else
9434 func (stream, "%s", arm_regnames[value]);
9435 break;
9436
9437 case 's':
9438 print_mve_size (info,
9439 value,
9440 insn->mve_op);
9441 break;
9442 case 'I':
9443 if (value == 1)
9444 func (stream, "i");
9445 break;
9446 case 'A':
9447 if (value == 1)
9448 func (stream, "a");
9449 break;
9450 case 'h':
9451 {
9452 unsigned int odd_reg = (value << 1) | 1;
9453 func (stream, "%s", arm_regnames[odd_reg]);
9454 }
9455 break;
9456 case 'i':
9457 {
9458 unsigned long imm
9459 = arm_decode_field (given, 0, 6);
9460 unsigned long mod_imm = imm;
9461
9462 switch (insn->mve_op)
9463 {
9464 case MVE_VLDRW_GATHER_T5:
9465 case MVE_VSTRW_SCATTER_T5:
9466 mod_imm = mod_imm << 2;
9467 break;
9468 case MVE_VSTRD_SCATTER_T6:
9469 case MVE_VLDRD_GATHER_T6:
9470 mod_imm = mod_imm << 3;
9471 break;
9472
9473 default:
9474 break;
9475 }
9476
9477 func (stream, "%lu", mod_imm);
9478 }
9479 break;
9480 case 'k':
9481 func (stream, "%lu", 64 - value);
9482 break;
9483 case 'l':
9484 {
9485 unsigned int even_reg = value << 1;
9486 func (stream, "%s", arm_regnames[even_reg]);
9487 }
9488 break;
9489 case 'u':
9490 switch (value)
9491 {
9492 case 0:
9493 func (stream, "1");
9494 break;
9495 case 1:
9496 func (stream, "2");
9497 break;
9498 case 2:
9499 func (stream, "4");
9500 break;
9501 case 3:
9502 func (stream, "8");
9503 break;
9504 default:
9505 break;
9506 }
9507 break;
9508 case 'o':
9509 print_mve_rotate (info, value, width);
9510 break;
9511 case 'r':
9512 func (stream, "%s", arm_regnames[value]);
9513 break;
9514 case 'd':
9515 if (insn->mve_op == MVE_VQSHL_T2
9516 || insn->mve_op == MVE_VQSHLU_T3
9517 || insn->mve_op == MVE_VRSHR
9518 || insn->mve_op == MVE_VRSHRN
9519 || insn->mve_op == MVE_VSHL_T1
9520 || insn->mve_op == MVE_VSHLL_T1
9521 || insn->mve_op == MVE_VSHR
9522 || insn->mve_op == MVE_VSHRN
9523 || insn->mve_op == MVE_VSLI
9524 || insn->mve_op == MVE_VSRI)
9525 print_mve_shift_n (info, given, insn->mve_op);
9526 else if (insn->mve_op == MVE_VSHLL_T2)
9527 {
9528 switch (value)
9529 {
9530 case 0x00:
9531 func (stream, "8");
9532 break;
9533 case 0x01:
9534 func (stream, "16");
9535 break;
9536 case 0x10:
9537 print_mve_undefined (info, UNDEF_SIZE_0);
9538 break;
9539 default:
9540 assert (0);
9541 break;
9542 }
9543 }
9544 else
9545 {
9546 if (insn->mve_op == MVE_VSHLC && value == 0)
9547 value = 32;
9548 func (stream, "%ld", value);
9549 value_in_comment = value;
9550 }
9551 break;
9552 case 'F':
9553 func (stream, "s%ld", value);
9554 break;
9555 case 'Q':
9556 if (value & 0x8)
9557 func (stream, "<illegal reg q%ld.5>", value);
9558 else
9559 func (stream, "q%ld", value);
9560 break;
9561 case 'x':
9562 func (stream, "0x%08lx", value);
9563 break;
9564 default:
9565 abort ();
9566 }
9567 break;
9568 default:
9569 abort ();
9570 }
9571 }
9572 }
9573 else
9574 func (stream, "%c", *c);
9575 }
9576
9577 if (value_in_comment > 32 || value_in_comment < -16)
9578 func (stream, "\t; 0x%lx", value_in_comment);
9579
9580 if (is_unpredictable)
9581 print_mve_unpredictable (info, unpredictable_cond);
9582
9583 if (is_undefined)
9584 print_mve_undefined (info, undefined_cond);
9585
9586 if ((vpt_block_state.in_vpt_block == FALSE)
9587 && !ifthen_state
9588 && (is_vpt_instruction (given) == TRUE))
9589 mark_inside_vpt_block (given);
9590 else if (vpt_block_state.in_vpt_block == TRUE)
9591 update_vpt_block_state ();
9592
9593 return TRUE;
9594 }
9595 }
9596 return FALSE;
9597 }
9598
9599
9600 /* Return the name of a v7A special register. */
9601
9602 static const char *
9603 banked_regname (unsigned reg)
9604 {
9605 switch (reg)
9606 {
9607 case 15: return "CPSR";
9608 case 32: return "R8_usr";
9609 case 33: return "R9_usr";
9610 case 34: return "R10_usr";
9611 case 35: return "R11_usr";
9612 case 36: return "R12_usr";
9613 case 37: return "SP_usr";
9614 case 38: return "LR_usr";
9615 case 40: return "R8_fiq";
9616 case 41: return "R9_fiq";
9617 case 42: return "R10_fiq";
9618 case 43: return "R11_fiq";
9619 case 44: return "R12_fiq";
9620 case 45: return "SP_fiq";
9621 case 46: return "LR_fiq";
9622 case 48: return "LR_irq";
9623 case 49: return "SP_irq";
9624 case 50: return "LR_svc";
9625 case 51: return "SP_svc";
9626 case 52: return "LR_abt";
9627 case 53: return "SP_abt";
9628 case 54: return "LR_und";
9629 case 55: return "SP_und";
9630 case 60: return "LR_mon";
9631 case 61: return "SP_mon";
9632 case 62: return "ELR_hyp";
9633 case 63: return "SP_hyp";
9634 case 79: return "SPSR";
9635 case 110: return "SPSR_fiq";
9636 case 112: return "SPSR_irq";
9637 case 114: return "SPSR_svc";
9638 case 116: return "SPSR_abt";
9639 case 118: return "SPSR_und";
9640 case 124: return "SPSR_mon";
9641 case 126: return "SPSR_hyp";
9642 default: return NULL;
9643 }
9644 }
9645
9646 /* Return the name of the DMB/DSB option. */
9647 static const char *
9648 data_barrier_option (unsigned option)
9649 {
9650 switch (option & 0xf)
9651 {
9652 case 0xf: return "sy";
9653 case 0xe: return "st";
9654 case 0xd: return "ld";
9655 case 0xb: return "ish";
9656 case 0xa: return "ishst";
9657 case 0x9: return "ishld";
9658 case 0x7: return "un";
9659 case 0x6: return "unst";
9660 case 0x5: return "nshld";
9661 case 0x3: return "osh";
9662 case 0x2: return "oshst";
9663 case 0x1: return "oshld";
9664 default: return NULL;
9665 }
9666 }
9667
9668 /* Print one ARM instruction from PC on INFO->STREAM. */
9669
9670 static void
9671 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
9672 {
9673 const struct opcode32 *insn;
9674 void *stream = info->stream;
9675 fprintf_ftype func = info->fprintf_func;
9676 struct arm_private_data *private_data = info->private_data;
9677
9678 if (print_insn_coprocessor (pc, info, given, FALSE))
9679 return;
9680
9681 if (print_insn_neon (info, given, FALSE))
9682 return;
9683
9684 if (print_insn_generic_coprocessor (pc, info, given, FALSE))
9685 return;
9686
9687 for (insn = arm_opcodes; insn->assembler; insn++)
9688 {
9689 if ((given & insn->mask) != insn->value)
9690 continue;
9691
9692 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
9693 continue;
9694
9695 /* Special case: an instruction with all bits set in the condition field
9696 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9697 or by the catchall at the end of the table. */
9698 if ((given & 0xF0000000) != 0xF0000000
9699 || (insn->mask & 0xF0000000) == 0xF0000000
9700 || (insn->mask == 0 && insn->value == 0))
9701 {
9702 unsigned long u_reg = 16;
9703 unsigned long U_reg = 16;
9704 bfd_boolean is_unpredictable = FALSE;
9705 signed long value_in_comment = 0;
9706 const char *c;
9707
9708 for (c = insn->assembler; *c; c++)
9709 {
9710 if (*c == '%')
9711 {
9712 bfd_boolean allow_unpredictable = FALSE;
9713
9714 switch (*++c)
9715 {
9716 case '%':
9717 func (stream, "%%");
9718 break;
9719
9720 case 'a':
9721 value_in_comment = print_arm_address (pc, info, given);
9722 break;
9723
9724 case 'P':
9725 /* Set P address bit and use normal address
9726 printing routine. */
9727 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
9728 break;
9729
9730 case 'S':
9731 allow_unpredictable = TRUE;
9732 /* Fall through. */
9733 case 's':
9734 if ((given & 0x004f0000) == 0x004f0000)
9735 {
9736 /* PC relative with immediate offset. */
9737 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
9738
9739 if (PRE_BIT_SET)
9740 {
9741 /* Elide positive zero offset. */
9742 if (offset || NEGATIVE_BIT_SET)
9743 func (stream, "[pc, #%s%d]\t; ",
9744 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9745 else
9746 func (stream, "[pc]\t; ");
9747 if (NEGATIVE_BIT_SET)
9748 offset = -offset;
9749 info->print_address_func (offset + pc + 8, info);
9750 }
9751 else
9752 {
9753 /* Always show the offset. */
9754 func (stream, "[pc], #%s%d",
9755 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9756 if (! allow_unpredictable)
9757 is_unpredictable = TRUE;
9758 }
9759 }
9760 else
9761 {
9762 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
9763
9764 func (stream, "[%s",
9765 arm_regnames[(given >> 16) & 0xf]);
9766
9767 if (PRE_BIT_SET)
9768 {
9769 if (IMMEDIATE_BIT_SET)
9770 {
9771 /* Elide offset for non-writeback
9772 positive zero. */
9773 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
9774 || offset)
9775 func (stream, ", #%s%d",
9776 NEGATIVE_BIT_SET ? "-" : "", offset);
9777
9778 if (NEGATIVE_BIT_SET)
9779 offset = -offset;
9780
9781 value_in_comment = offset;
9782 }
9783 else
9784 {
9785 /* Register Offset or Register Pre-Indexed. */
9786 func (stream, ", %s%s",
9787 NEGATIVE_BIT_SET ? "-" : "",
9788 arm_regnames[given & 0xf]);
9789
9790 /* Writing back to the register that is the source/
9791 destination of the load/store is unpredictable. */
9792 if (! allow_unpredictable
9793 && WRITEBACK_BIT_SET
9794 && ((given & 0xf) == ((given >> 12) & 0xf)))
9795 is_unpredictable = TRUE;
9796 }
9797
9798 func (stream, "]%s",
9799 WRITEBACK_BIT_SET ? "!" : "");
9800 }
9801 else
9802 {
9803 if (IMMEDIATE_BIT_SET)
9804 {
9805 /* Immediate Post-indexed. */
9806 /* PR 10924: Offset must be printed, even if it is zero. */
9807 func (stream, "], #%s%d",
9808 NEGATIVE_BIT_SET ? "-" : "", offset);
9809 if (NEGATIVE_BIT_SET)
9810 offset = -offset;
9811 value_in_comment = offset;
9812 }
9813 else
9814 {
9815 /* Register Post-indexed. */
9816 func (stream, "], %s%s",
9817 NEGATIVE_BIT_SET ? "-" : "",
9818 arm_regnames[given & 0xf]);
9819
9820 /* Writing back to the register that is the source/
9821 destination of the load/store is unpredictable. */
9822 if (! allow_unpredictable
9823 && (given & 0xf) == ((given >> 12) & 0xf))
9824 is_unpredictable = TRUE;
9825 }
9826
9827 if (! allow_unpredictable)
9828 {
9829 /* Writeback is automatically implied by post- addressing.
9830 Setting the W bit is unnecessary and ARM specify it as
9831 being unpredictable. */
9832 if (WRITEBACK_BIT_SET
9833 /* Specifying the PC register as the post-indexed
9834 registers is also unpredictable. */
9835 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
9836 is_unpredictable = TRUE;
9837 }
9838 }
9839 }
9840 break;
9841
9842 case 'b':
9843 {
9844 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
9845 info->print_address_func (disp * 4 + pc + 8, info);
9846 }
9847 break;
9848
9849 case 'c':
9850 if (((given >> 28) & 0xf) != 0xe)
9851 func (stream, "%s",
9852 arm_conditional [(given >> 28) & 0xf]);
9853 break;
9854
9855 case 'm':
9856 {
9857 int started = 0;
9858 int reg;
9859
9860 func (stream, "{");
9861 for (reg = 0; reg < 16; reg++)
9862 if ((given & (1 << reg)) != 0)
9863 {
9864 if (started)
9865 func (stream, ", ");
9866 started = 1;
9867 func (stream, "%s", arm_regnames[reg]);
9868 }
9869 func (stream, "}");
9870 if (! started)
9871 is_unpredictable = TRUE;
9872 }
9873 break;
9874
9875 case 'q':
9876 arm_decode_shift (given, func, stream, FALSE);
9877 break;
9878
9879 case 'o':
9880 if ((given & 0x02000000) != 0)
9881 {
9882 unsigned int rotate = (given & 0xf00) >> 7;
9883 unsigned int immed = (given & 0xff);
9884 unsigned int a, i;
9885
9886 a = (((immed << (32 - rotate))
9887 | (immed >> rotate)) & 0xffffffff);
9888 /* If there is another encoding with smaller rotate,
9889 the rotate should be specified directly. */
9890 for (i = 0; i < 32; i += 2)
9891 if ((a << i | a >> (32 - i)) <= 0xff)
9892 break;
9893
9894 if (i != rotate)
9895 func (stream, "#%d, %d", immed, rotate);
9896 else
9897 func (stream, "#%d", a);
9898 value_in_comment = a;
9899 }
9900 else
9901 arm_decode_shift (given, func, stream, TRUE);
9902 break;
9903
9904 case 'p':
9905 if ((given & 0x0000f000) == 0x0000f000)
9906 {
9907 arm_feature_set arm_ext_v6 =
9908 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
9909
9910 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9911 mechanism for setting PSR flag bits. They are
9912 obsolete in V6 onwards. */
9913 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
9914 arm_ext_v6))
9915 func (stream, "p");
9916 else
9917 is_unpredictable = TRUE;
9918 }
9919 break;
9920
9921 case 't':
9922 if ((given & 0x01200000) == 0x00200000)
9923 func (stream, "t");
9924 break;
9925
9926 case 'A':
9927 {
9928 int offset = given & 0xff;
9929
9930 value_in_comment = offset * 4;
9931 if (NEGATIVE_BIT_SET)
9932 value_in_comment = - value_in_comment;
9933
9934 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
9935
9936 if (PRE_BIT_SET)
9937 {
9938 if (offset)
9939 func (stream, ", #%d]%s",
9940 (int) value_in_comment,
9941 WRITEBACK_BIT_SET ? "!" : "");
9942 else
9943 func (stream, "]");
9944 }
9945 else
9946 {
9947 func (stream, "]");
9948
9949 if (WRITEBACK_BIT_SET)
9950 {
9951 if (offset)
9952 func (stream, ", #%d", (int) value_in_comment);
9953 }
9954 else
9955 {
9956 func (stream, ", {%d}", (int) offset);
9957 value_in_comment = offset;
9958 }
9959 }
9960 }
9961 break;
9962
9963 case 'B':
9964 /* Print ARM V5 BLX(1) address: pc+25 bits. */
9965 {
9966 bfd_vma address;
9967 bfd_vma offset = 0;
9968
9969 if (! NEGATIVE_BIT_SET)
9970 /* Is signed, hi bits should be ones. */
9971 offset = (-1) ^ 0x00ffffff;
9972
9973 /* Offset is (SignExtend(offset field)<<2). */
9974 offset += given & 0x00ffffff;
9975 offset <<= 2;
9976 address = offset + pc + 8;
9977
9978 if (given & 0x01000000)
9979 /* H bit allows addressing to 2-byte boundaries. */
9980 address += 2;
9981
9982 info->print_address_func (address, info);
9983 }
9984 break;
9985
9986 case 'C':
9987 if ((given & 0x02000200) == 0x200)
9988 {
9989 const char * name;
9990 unsigned sysm = (given & 0x004f0000) >> 16;
9991
9992 sysm |= (given & 0x300) >> 4;
9993 name = banked_regname (sysm);
9994
9995 if (name != NULL)
9996 func (stream, "%s", name);
9997 else
9998 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
9999 }
10000 else
10001 {
10002 func (stream, "%cPSR_",
10003 (given & 0x00400000) ? 'S' : 'C');
10004 if (given & 0x80000)
10005 func (stream, "f");
10006 if (given & 0x40000)
10007 func (stream, "s");
10008 if (given & 0x20000)
10009 func (stream, "x");
10010 if (given & 0x10000)
10011 func (stream, "c");
10012 }
10013 break;
10014
10015 case 'U':
10016 if ((given & 0xf0) == 0x60)
10017 {
10018 switch (given & 0xf)
10019 {
10020 case 0xf: func (stream, "sy"); break;
10021 default:
10022 func (stream, "#%d", (int) given & 0xf);
10023 break;
10024 }
10025 }
10026 else
10027 {
10028 const char * opt = data_barrier_option (given & 0xf);
10029 if (opt != NULL)
10030 func (stream, "%s", opt);
10031 else
10032 func (stream, "#%d", (int) given & 0xf);
10033 }
10034 break;
10035
10036 case '0': case '1': case '2': case '3': case '4':
10037 case '5': case '6': case '7': case '8': case '9':
10038 {
10039 int width;
10040 unsigned long value;
10041
10042 c = arm_decode_bitfield (c, given, &value, &width);
10043
10044 switch (*c)
10045 {
10046 case 'R':
10047 if (value == 15)
10048 is_unpredictable = TRUE;
10049 /* Fall through. */
10050 case 'r':
10051 case 'T':
10052 /* We want register + 1 when decoding T. */
10053 if (*c == 'T')
10054 ++value;
10055
10056 if (c[1] == 'u')
10057 {
10058 /* Eat the 'u' character. */
10059 ++ c;
10060
10061 if (u_reg == value)
10062 is_unpredictable = TRUE;
10063 u_reg = value;
10064 }
10065 if (c[1] == 'U')
10066 {
10067 /* Eat the 'U' character. */
10068 ++ c;
10069
10070 if (U_reg == value)
10071 is_unpredictable = TRUE;
10072 U_reg = value;
10073 }
10074 func (stream, "%s", arm_regnames[value]);
10075 break;
10076 case 'd':
10077 func (stream, "%ld", value);
10078 value_in_comment = value;
10079 break;
10080 case 'b':
10081 func (stream, "%ld", value * 8);
10082 value_in_comment = value * 8;
10083 break;
10084 case 'W':
10085 func (stream, "%ld", value + 1);
10086 value_in_comment = value + 1;
10087 break;
10088 case 'x':
10089 func (stream, "0x%08lx", value);
10090
10091 /* Some SWI instructions have special
10092 meanings. */
10093 if ((given & 0x0fffffff) == 0x0FF00000)
10094 func (stream, "\t; IMB");
10095 else if ((given & 0x0fffffff) == 0x0FF00001)
10096 func (stream, "\t; IMBRange");
10097 break;
10098 case 'X':
10099 func (stream, "%01lx", value & 0xf);
10100 value_in_comment = value;
10101 break;
10102 case '`':
10103 c++;
10104 if (value == 0)
10105 func (stream, "%c", *c);
10106 break;
10107 case '\'':
10108 c++;
10109 if (value == ((1ul << width) - 1))
10110 func (stream, "%c", *c);
10111 break;
10112 case '?':
10113 func (stream, "%c", c[(1 << width) - (int) value]);
10114 c += 1 << width;
10115 break;
10116 default:
10117 abort ();
10118 }
10119 }
10120 break;
10121
10122 case 'e':
10123 {
10124 int imm;
10125
10126 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10127 func (stream, "%d", imm);
10128 value_in_comment = imm;
10129 }
10130 break;
10131
10132 case 'E':
10133 /* LSB and WIDTH fields of BFI or BFC. The machine-
10134 language instruction encodes LSB and MSB. */
10135 {
10136 long msb = (given & 0x001f0000) >> 16;
10137 long lsb = (given & 0x00000f80) >> 7;
10138 long w = msb - lsb + 1;
10139
10140 if (w > 0)
10141 func (stream, "#%lu, #%lu", lsb, w);
10142 else
10143 func (stream, "(invalid: %lu:%lu)", lsb, msb);
10144 }
10145 break;
10146
10147 case 'R':
10148 /* Get the PSR/banked register name. */
10149 {
10150 const char * name;
10151 unsigned sysm = (given & 0x004f0000) >> 16;
10152
10153 sysm |= (given & 0x300) >> 4;
10154 name = banked_regname (sysm);
10155
10156 if (name != NULL)
10157 func (stream, "%s", name);
10158 else
10159 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10160 }
10161 break;
10162
10163 case 'V':
10164 /* 16-bit unsigned immediate from a MOVT or MOVW
10165 instruction, encoded in bits 0:11 and 15:19. */
10166 {
10167 long hi = (given & 0x000f0000) >> 4;
10168 long lo = (given & 0x00000fff);
10169 long imm16 = hi | lo;
10170
10171 func (stream, "#%lu", imm16);
10172 value_in_comment = imm16;
10173 }
10174 break;
10175
10176 default:
10177 abort ();
10178 }
10179 }
10180 else
10181 func (stream, "%c", *c);
10182 }
10183
10184 if (value_in_comment > 32 || value_in_comment < -16)
10185 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
10186
10187 if (is_unpredictable)
10188 func (stream, UNPREDICTABLE_INSTRUCTION);
10189
10190 return;
10191 }
10192 }
10193 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10194 return;
10195 }
10196
10197 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
10198
10199 static void
10200 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
10201 {
10202 const struct opcode16 *insn;
10203 void *stream = info->stream;
10204 fprintf_ftype func = info->fprintf_func;
10205
10206 for (insn = thumb_opcodes; insn->assembler; insn++)
10207 if ((given & insn->mask) == insn->value)
10208 {
10209 signed long value_in_comment = 0;
10210 const char *c = insn->assembler;
10211
10212 for (; *c; c++)
10213 {
10214 int domaskpc = 0;
10215 int domasklr = 0;
10216
10217 if (*c != '%')
10218 {
10219 func (stream, "%c", *c);
10220 continue;
10221 }
10222
10223 switch (*++c)
10224 {
10225 case '%':
10226 func (stream, "%%");
10227 break;
10228
10229 case 'c':
10230 if (ifthen_state)
10231 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10232 break;
10233
10234 case 'C':
10235 if (ifthen_state)
10236 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10237 else
10238 func (stream, "s");
10239 break;
10240
10241 case 'I':
10242 {
10243 unsigned int tmp;
10244
10245 ifthen_next_state = given & 0xff;
10246 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10247 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
10248 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
10249 }
10250 break;
10251
10252 case 'x':
10253 if (ifthen_next_state)
10254 func (stream, "\t; unpredictable branch in IT block\n");
10255 break;
10256
10257 case 'X':
10258 if (ifthen_state)
10259 func (stream, "\t; unpredictable <IT:%s>",
10260 arm_conditional[IFTHEN_COND]);
10261 break;
10262
10263 case 'S':
10264 {
10265 long reg;
10266
10267 reg = (given >> 3) & 0x7;
10268 if (given & (1 << 6))
10269 reg += 8;
10270
10271 func (stream, "%s", arm_regnames[reg]);
10272 }
10273 break;
10274
10275 case 'D':
10276 {
10277 long reg;
10278
10279 reg = given & 0x7;
10280 if (given & (1 << 7))
10281 reg += 8;
10282
10283 func (stream, "%s", arm_regnames[reg]);
10284 }
10285 break;
10286
10287 case 'N':
10288 if (given & (1 << 8))
10289 domasklr = 1;
10290 /* Fall through. */
10291 case 'O':
10292 if (*c == 'O' && (given & (1 << 8)))
10293 domaskpc = 1;
10294 /* Fall through. */
10295 case 'M':
10296 {
10297 int started = 0;
10298 int reg;
10299
10300 func (stream, "{");
10301
10302 /* It would be nice if we could spot
10303 ranges, and generate the rS-rE format: */
10304 for (reg = 0; (reg < 8); reg++)
10305 if ((given & (1 << reg)) != 0)
10306 {
10307 if (started)
10308 func (stream, ", ");
10309 started = 1;
10310 func (stream, "%s", arm_regnames[reg]);
10311 }
10312
10313 if (domasklr)
10314 {
10315 if (started)
10316 func (stream, ", ");
10317 started = 1;
10318 func (stream, "%s", arm_regnames[14] /* "lr" */);
10319 }
10320
10321 if (domaskpc)
10322 {
10323 if (started)
10324 func (stream, ", ");
10325 func (stream, "%s", arm_regnames[15] /* "pc" */);
10326 }
10327
10328 func (stream, "}");
10329 }
10330 break;
10331
10332 case 'W':
10333 /* Print writeback indicator for a LDMIA. We are doing a
10334 writeback if the base register is not in the register
10335 mask. */
10336 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10337 func (stream, "!");
10338 break;
10339
10340 case 'b':
10341 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10342 {
10343 bfd_vma address = (pc + 4
10344 + ((given & 0x00f8) >> 2)
10345 + ((given & 0x0200) >> 3));
10346 info->print_address_func (address, info);
10347 }
10348 break;
10349
10350 case 's':
10351 /* Right shift immediate -- bits 6..10; 1-31 print
10352 as themselves, 0 prints as 32. */
10353 {
10354 long imm = (given & 0x07c0) >> 6;
10355 if (imm == 0)
10356 imm = 32;
10357 func (stream, "#%ld", imm);
10358 }
10359 break;
10360
10361 case '0': case '1': case '2': case '3': case '4':
10362 case '5': case '6': case '7': case '8': case '9':
10363 {
10364 int bitstart = *c++ - '0';
10365 int bitend = 0;
10366
10367 while (*c >= '0' && *c <= '9')
10368 bitstart = (bitstart * 10) + *c++ - '0';
10369
10370 switch (*c)
10371 {
10372 case '-':
10373 {
10374 bfd_vma reg;
10375
10376 c++;
10377 while (*c >= '0' && *c <= '9')
10378 bitend = (bitend * 10) + *c++ - '0';
10379 if (!bitend)
10380 abort ();
10381 reg = given >> bitstart;
10382 reg &= (2 << (bitend - bitstart)) - 1;
10383
10384 switch (*c)
10385 {
10386 case 'r':
10387 func (stream, "%s", arm_regnames[reg]);
10388 break;
10389
10390 case 'd':
10391 func (stream, "%ld", (long) reg);
10392 value_in_comment = reg;
10393 break;
10394
10395 case 'H':
10396 func (stream, "%ld", (long) (reg << 1));
10397 value_in_comment = reg << 1;
10398 break;
10399
10400 case 'W':
10401 func (stream, "%ld", (long) (reg << 2));
10402 value_in_comment = reg << 2;
10403 break;
10404
10405 case 'a':
10406 /* PC-relative address -- the bottom two
10407 bits of the address are dropped
10408 before the calculation. */
10409 info->print_address_func
10410 (((pc + 4) & ~3) + (reg << 2), info);
10411 value_in_comment = 0;
10412 break;
10413
10414 case 'x':
10415 func (stream, "0x%04lx", (long) reg);
10416 break;
10417
10418 case 'B':
10419 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
10420 info->print_address_func (reg * 2 + pc + 4, info);
10421 value_in_comment = 0;
10422 break;
10423
10424 case 'c':
10425 func (stream, "%s", arm_conditional [reg]);
10426 break;
10427
10428 default:
10429 abort ();
10430 }
10431 }
10432 break;
10433
10434 case '\'':
10435 c++;
10436 if ((given & (1 << bitstart)) != 0)
10437 func (stream, "%c", *c);
10438 break;
10439
10440 case '?':
10441 ++c;
10442 if ((given & (1 << bitstart)) != 0)
10443 func (stream, "%c", *c++);
10444 else
10445 func (stream, "%c", *++c);
10446 break;
10447
10448 default:
10449 abort ();
10450 }
10451 }
10452 break;
10453
10454 default:
10455 abort ();
10456 }
10457 }
10458
10459 if (value_in_comment > 32 || value_in_comment < -16)
10460 func (stream, "\t; 0x%lx", value_in_comment);
10461 return;
10462 }
10463
10464 /* No match. */
10465 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
10466 return;
10467 }
10468
10469 /* Return the name of an V7M special register. */
10470
10471 static const char *
10472 psr_name (int regno)
10473 {
10474 switch (regno)
10475 {
10476 case 0x0: return "APSR";
10477 case 0x1: return "IAPSR";
10478 case 0x2: return "EAPSR";
10479 case 0x3: return "PSR";
10480 case 0x5: return "IPSR";
10481 case 0x6: return "EPSR";
10482 case 0x7: return "IEPSR";
10483 case 0x8: return "MSP";
10484 case 0x9: return "PSP";
10485 case 0xa: return "MSPLIM";
10486 case 0xb: return "PSPLIM";
10487 case 0x10: return "PRIMASK";
10488 case 0x11: return "BASEPRI";
10489 case 0x12: return "BASEPRI_MAX";
10490 case 0x13: return "FAULTMASK";
10491 case 0x14: return "CONTROL";
10492 case 0x88: return "MSP_NS";
10493 case 0x89: return "PSP_NS";
10494 case 0x8a: return "MSPLIM_NS";
10495 case 0x8b: return "PSPLIM_NS";
10496 case 0x90: return "PRIMASK_NS";
10497 case 0x91: return "BASEPRI_NS";
10498 case 0x93: return "FAULTMASK_NS";
10499 case 0x94: return "CONTROL_NS";
10500 case 0x98: return "SP_NS";
10501 default: return "<unknown>";
10502 }
10503 }
10504
10505 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10506
10507 static void
10508 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
10509 {
10510 const struct opcode32 *insn;
10511 void *stream = info->stream;
10512 fprintf_ftype func = info->fprintf_func;
10513 bfd_boolean is_mve = is_mve_architecture (info);
10514
10515 if (print_insn_coprocessor (pc, info, given, TRUE))
10516 return;
10517
10518 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
10519 return;
10520
10521 if (is_mve && print_insn_mve (info, given))
10522 return;
10523
10524 if (print_insn_generic_coprocessor (pc, info, given, TRUE))
10525 return;
10526
10527 for (insn = thumb32_opcodes; insn->assembler; insn++)
10528 if ((given & insn->mask) == insn->value)
10529 {
10530 bfd_boolean is_clrm = FALSE;
10531 bfd_boolean is_unpredictable = FALSE;
10532 signed long value_in_comment = 0;
10533 const char *c = insn->assembler;
10534
10535 for (; *c; c++)
10536 {
10537 if (*c != '%')
10538 {
10539 func (stream, "%c", *c);
10540 continue;
10541 }
10542
10543 switch (*++c)
10544 {
10545 case '%':
10546 func (stream, "%%");
10547 break;
10548
10549 case 'c':
10550 if (ifthen_state)
10551 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10552 break;
10553
10554 case 'x':
10555 if (ifthen_next_state)
10556 func (stream, "\t; unpredictable branch in IT block\n");
10557 break;
10558
10559 case 'X':
10560 if (ifthen_state)
10561 func (stream, "\t; unpredictable <IT:%s>",
10562 arm_conditional[IFTHEN_COND]);
10563 break;
10564
10565 case 'I':
10566 {
10567 unsigned int imm12 = 0;
10568
10569 imm12 |= (given & 0x000000ffu);
10570 imm12 |= (given & 0x00007000u) >> 4;
10571 imm12 |= (given & 0x04000000u) >> 15;
10572 func (stream, "#%u", imm12);
10573 value_in_comment = imm12;
10574 }
10575 break;
10576
10577 case 'M':
10578 {
10579 unsigned int bits = 0, imm, imm8, mod;
10580
10581 bits |= (given & 0x000000ffu);
10582 bits |= (given & 0x00007000u) >> 4;
10583 bits |= (given & 0x04000000u) >> 15;
10584 imm8 = (bits & 0x0ff);
10585 mod = (bits & 0xf00) >> 8;
10586 switch (mod)
10587 {
10588 case 0: imm = imm8; break;
10589 case 1: imm = ((imm8 << 16) | imm8); break;
10590 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10591 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
10592 default:
10593 mod = (bits & 0xf80) >> 7;
10594 imm8 = (bits & 0x07f) | 0x80;
10595 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10596 }
10597 func (stream, "#%u", imm);
10598 value_in_comment = imm;
10599 }
10600 break;
10601
10602 case 'J':
10603 {
10604 unsigned int imm = 0;
10605
10606 imm |= (given & 0x000000ffu);
10607 imm |= (given & 0x00007000u) >> 4;
10608 imm |= (given & 0x04000000u) >> 15;
10609 imm |= (given & 0x000f0000u) >> 4;
10610 func (stream, "#%u", imm);
10611 value_in_comment = imm;
10612 }
10613 break;
10614
10615 case 'K':
10616 {
10617 unsigned int imm = 0;
10618
10619 imm |= (given & 0x000f0000u) >> 16;
10620 imm |= (given & 0x00000ff0u) >> 0;
10621 imm |= (given & 0x0000000fu) << 12;
10622 func (stream, "#%u", imm);
10623 value_in_comment = imm;
10624 }
10625 break;
10626
10627 case 'H':
10628 {
10629 unsigned int imm = 0;
10630
10631 imm |= (given & 0x000f0000u) >> 4;
10632 imm |= (given & 0x00000fffu) >> 0;
10633 func (stream, "#%u", imm);
10634 value_in_comment = imm;
10635 }
10636 break;
10637
10638 case 'V':
10639 {
10640 unsigned int imm = 0;
10641
10642 imm |= (given & 0x00000fffu);
10643 imm |= (given & 0x000f0000u) >> 4;
10644 func (stream, "#%u", imm);
10645 value_in_comment = imm;
10646 }
10647 break;
10648
10649 case 'S':
10650 {
10651 unsigned int reg = (given & 0x0000000fu);
10652 unsigned int stp = (given & 0x00000030u) >> 4;
10653 unsigned int imm = 0;
10654 imm |= (given & 0x000000c0u) >> 6;
10655 imm |= (given & 0x00007000u) >> 10;
10656
10657 func (stream, "%s", arm_regnames[reg]);
10658 switch (stp)
10659 {
10660 case 0:
10661 if (imm > 0)
10662 func (stream, ", lsl #%u", imm);
10663 break;
10664
10665 case 1:
10666 if (imm == 0)
10667 imm = 32;
10668 func (stream, ", lsr #%u", imm);
10669 break;
10670
10671 case 2:
10672 if (imm == 0)
10673 imm = 32;
10674 func (stream, ", asr #%u", imm);
10675 break;
10676
10677 case 3:
10678 if (imm == 0)
10679 func (stream, ", rrx");
10680 else
10681 func (stream, ", ror #%u", imm);
10682 }
10683 }
10684 break;
10685
10686 case 'a':
10687 {
10688 unsigned int Rn = (given & 0x000f0000) >> 16;
10689 unsigned int U = ! NEGATIVE_BIT_SET;
10690 unsigned int op = (given & 0x00000f00) >> 8;
10691 unsigned int i12 = (given & 0x00000fff);
10692 unsigned int i8 = (given & 0x000000ff);
10693 bfd_boolean writeback = FALSE, postind = FALSE;
10694 bfd_vma offset = 0;
10695
10696 func (stream, "[%s", arm_regnames[Rn]);
10697 if (U) /* 12-bit positive immediate offset. */
10698 {
10699 offset = i12;
10700 if (Rn != 15)
10701 value_in_comment = offset;
10702 }
10703 else if (Rn == 15) /* 12-bit negative immediate offset. */
10704 offset = - (int) i12;
10705 else if (op == 0x0) /* Shifted register offset. */
10706 {
10707 unsigned int Rm = (i8 & 0x0f);
10708 unsigned int sh = (i8 & 0x30) >> 4;
10709
10710 func (stream, ", %s", arm_regnames[Rm]);
10711 if (sh)
10712 func (stream, ", lsl #%u", sh);
10713 func (stream, "]");
10714 break;
10715 }
10716 else switch (op)
10717 {
10718 case 0xE: /* 8-bit positive immediate offset. */
10719 offset = i8;
10720 break;
10721
10722 case 0xC: /* 8-bit negative immediate offset. */
10723 offset = -i8;
10724 break;
10725
10726 case 0xF: /* 8-bit + preindex with wb. */
10727 offset = i8;
10728 writeback = TRUE;
10729 break;
10730
10731 case 0xD: /* 8-bit - preindex with wb. */
10732 offset = -i8;
10733 writeback = TRUE;
10734 break;
10735
10736 case 0xB: /* 8-bit + postindex. */
10737 offset = i8;
10738 postind = TRUE;
10739 break;
10740
10741 case 0x9: /* 8-bit - postindex. */
10742 offset = -i8;
10743 postind = TRUE;
10744 break;
10745
10746 default:
10747 func (stream, ", <undefined>]");
10748 goto skip;
10749 }
10750
10751 if (postind)
10752 func (stream, "], #%d", (int) offset);
10753 else
10754 {
10755 if (offset)
10756 func (stream, ", #%d", (int) offset);
10757 func (stream, writeback ? "]!" : "]");
10758 }
10759
10760 if (Rn == 15)
10761 {
10762 func (stream, "\t; ");
10763 info->print_address_func (((pc + 4) & ~3) + offset, info);
10764 }
10765 }
10766 skip:
10767 break;
10768
10769 case 'A':
10770 {
10771 unsigned int U = ! NEGATIVE_BIT_SET;
10772 unsigned int W = WRITEBACK_BIT_SET;
10773 unsigned int Rn = (given & 0x000f0000) >> 16;
10774 unsigned int off = (given & 0x000000ff);
10775
10776 func (stream, "[%s", arm_regnames[Rn]);
10777
10778 if (PRE_BIT_SET)
10779 {
10780 if (off || !U)
10781 {
10782 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
10783 value_in_comment = off * 4 * (U ? 1 : -1);
10784 }
10785 func (stream, "]");
10786 if (W)
10787 func (stream, "!");
10788 }
10789 else
10790 {
10791 func (stream, "], ");
10792 if (W)
10793 {
10794 func (stream, "#%c%u", U ? '+' : '-', off * 4);
10795 value_in_comment = off * 4 * (U ? 1 : -1);
10796 }
10797 else
10798 {
10799 func (stream, "{%u}", off);
10800 value_in_comment = off;
10801 }
10802 }
10803 }
10804 break;
10805
10806 case 'w':
10807 {
10808 unsigned int Sbit = (given & 0x01000000) >> 24;
10809 unsigned int type = (given & 0x00600000) >> 21;
10810
10811 switch (type)
10812 {
10813 case 0: func (stream, Sbit ? "sb" : "b"); break;
10814 case 1: func (stream, Sbit ? "sh" : "h"); break;
10815 case 2:
10816 if (Sbit)
10817 func (stream, "??");
10818 break;
10819 case 3:
10820 func (stream, "??");
10821 break;
10822 }
10823 }
10824 break;
10825
10826 case 'n':
10827 is_clrm = TRUE;
10828 /* Fall through. */
10829 case 'm':
10830 {
10831 int started = 0;
10832 int reg;
10833
10834 func (stream, "{");
10835 for (reg = 0; reg < 16; reg++)
10836 if ((given & (1 << reg)) != 0)
10837 {
10838 if (started)
10839 func (stream, ", ");
10840 started = 1;
10841 if (is_clrm && reg == 13)
10842 func (stream, "(invalid: %s)", arm_regnames[reg]);
10843 else if (is_clrm && reg == 15)
10844 func (stream, "%s", "APSR");
10845 else
10846 func (stream, "%s", arm_regnames[reg]);
10847 }
10848 func (stream, "}");
10849 }
10850 break;
10851
10852 case 'E':
10853 {
10854 unsigned int msb = (given & 0x0000001f);
10855 unsigned int lsb = 0;
10856
10857 lsb |= (given & 0x000000c0u) >> 6;
10858 lsb |= (given & 0x00007000u) >> 10;
10859 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
10860 }
10861 break;
10862
10863 case 'F':
10864 {
10865 unsigned int width = (given & 0x0000001f) + 1;
10866 unsigned int lsb = 0;
10867
10868 lsb |= (given & 0x000000c0u) >> 6;
10869 lsb |= (given & 0x00007000u) >> 10;
10870 func (stream, "#%u, #%u", lsb, width);
10871 }
10872 break;
10873
10874 case 'G':
10875 {
10876 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
10877 func (stream, "%x", boff);
10878 }
10879 break;
10880
10881 case 'W':
10882 {
10883 unsigned int immA = (given & 0x001f0000u) >> 16;
10884 unsigned int immB = (given & 0x000007feu) >> 1;
10885 unsigned int immC = (given & 0x00000800u) >> 11;
10886 bfd_vma offset = 0;
10887
10888 offset |= immA << 12;
10889 offset |= immB << 2;
10890 offset |= immC << 1;
10891 /* Sign extend. */
10892 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
10893
10894 info->print_address_func (pc + 4 + offset, info);
10895 }
10896 break;
10897
10898 case 'Y':
10899 {
10900 unsigned int immA = (given & 0x007f0000u) >> 16;
10901 unsigned int immB = (given & 0x000007feu) >> 1;
10902 unsigned int immC = (given & 0x00000800u) >> 11;
10903 bfd_vma offset = 0;
10904
10905 offset |= immA << 12;
10906 offset |= immB << 2;
10907 offset |= immC << 1;
10908 /* Sign extend. */
10909 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
10910
10911 info->print_address_func (pc + 4 + offset, info);
10912 }
10913 break;
10914
10915 case 'Z':
10916 {
10917 unsigned int immA = (given & 0x00010000u) >> 16;
10918 unsigned int immB = (given & 0x000007feu) >> 1;
10919 unsigned int immC = (given & 0x00000800u) >> 11;
10920 bfd_vma offset = 0;
10921
10922 offset |= immA << 12;
10923 offset |= immB << 2;
10924 offset |= immC << 1;
10925 /* Sign extend. */
10926 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
10927
10928 info->print_address_func (pc + 4 + offset, info);
10929
10930 unsigned int T = (given & 0x00020000u) >> 17;
10931 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
10932 unsigned int boffset = (T == 1) ? 4 : 2;
10933 func (stream, ", ");
10934 func (stream, "%x", endoffset + boffset);
10935 }
10936 break;
10937
10938 case 'Q':
10939 {
10940 unsigned int immh = (given & 0x000007feu) >> 1;
10941 unsigned int imml = (given & 0x00000800u) >> 11;
10942 bfd_vma imm32 = 0;
10943
10944 imm32 |= immh << 2;
10945 imm32 |= imml << 1;
10946
10947 info->print_address_func (pc + 4 + imm32, info);
10948 }
10949 break;
10950
10951 case 'P':
10952 {
10953 unsigned int immh = (given & 0x000007feu) >> 1;
10954 unsigned int imml = (given & 0x00000800u) >> 11;
10955 bfd_vma imm32 = 0;
10956
10957 imm32 |= immh << 2;
10958 imm32 |= imml << 1;
10959
10960 info->print_address_func (pc + 4 - imm32, info);
10961 }
10962 break;
10963
10964 case 'b':
10965 {
10966 unsigned int S = (given & 0x04000000u) >> 26;
10967 unsigned int J1 = (given & 0x00002000u) >> 13;
10968 unsigned int J2 = (given & 0x00000800u) >> 11;
10969 bfd_vma offset = 0;
10970
10971 offset |= !S << 20;
10972 offset |= J2 << 19;
10973 offset |= J1 << 18;
10974 offset |= (given & 0x003f0000) >> 4;
10975 offset |= (given & 0x000007ff) << 1;
10976 offset -= (1 << 20);
10977
10978 info->print_address_func (pc + 4 + offset, info);
10979 }
10980 break;
10981
10982 case 'B':
10983 {
10984 unsigned int S = (given & 0x04000000u) >> 26;
10985 unsigned int I1 = (given & 0x00002000u) >> 13;
10986 unsigned int I2 = (given & 0x00000800u) >> 11;
10987 bfd_vma offset = 0;
10988
10989 offset |= !S << 24;
10990 offset |= !(I1 ^ S) << 23;
10991 offset |= !(I2 ^ S) << 22;
10992 offset |= (given & 0x03ff0000u) >> 4;
10993 offset |= (given & 0x000007ffu) << 1;
10994 offset -= (1 << 24);
10995 offset += pc + 4;
10996
10997 /* BLX target addresses are always word aligned. */
10998 if ((given & 0x00001000u) == 0)
10999 offset &= ~2u;
11000
11001 info->print_address_func (offset, info);
11002 }
11003 break;
11004
11005 case 's':
11006 {
11007 unsigned int shift = 0;
11008
11009 shift |= (given & 0x000000c0u) >> 6;
11010 shift |= (given & 0x00007000u) >> 10;
11011 if (WRITEBACK_BIT_SET)
11012 func (stream, ", asr #%u", shift);
11013 else if (shift)
11014 func (stream, ", lsl #%u", shift);
11015 /* else print nothing - lsl #0 */
11016 }
11017 break;
11018
11019 case 'R':
11020 {
11021 unsigned int rot = (given & 0x00000030) >> 4;
11022
11023 if (rot)
11024 func (stream, ", ror #%u", rot * 8);
11025 }
11026 break;
11027
11028 case 'U':
11029 if ((given & 0xf0) == 0x60)
11030 {
11031 switch (given & 0xf)
11032 {
11033 case 0xf: func (stream, "sy"); break;
11034 default:
11035 func (stream, "#%d", (int) given & 0xf);
11036 break;
11037 }
11038 }
11039 else
11040 {
11041 const char * opt = data_barrier_option (given & 0xf);
11042 if (opt != NULL)
11043 func (stream, "%s", opt);
11044 else
11045 func (stream, "#%d", (int) given & 0xf);
11046 }
11047 break;
11048
11049 case 'C':
11050 if ((given & 0xff) == 0)
11051 {
11052 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
11053 if (given & 0x800)
11054 func (stream, "f");
11055 if (given & 0x400)
11056 func (stream, "s");
11057 if (given & 0x200)
11058 func (stream, "x");
11059 if (given & 0x100)
11060 func (stream, "c");
11061 }
11062 else if ((given & 0x20) == 0x20)
11063 {
11064 char const* name;
11065 unsigned sysm = (given & 0xf00) >> 8;
11066
11067 sysm |= (given & 0x30);
11068 sysm |= (given & 0x00100000) >> 14;
11069 name = banked_regname (sysm);
11070
11071 if (name != NULL)
11072 func (stream, "%s", name);
11073 else
11074 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
11075 }
11076 else
11077 {
11078 func (stream, "%s", psr_name (given & 0xff));
11079 }
11080 break;
11081
11082 case 'D':
11083 if (((given & 0xff) == 0)
11084 || ((given & 0x20) == 0x20))
11085 {
11086 char const* name;
11087 unsigned sm = (given & 0xf0000) >> 16;
11088
11089 sm |= (given & 0x30);
11090 sm |= (given & 0x00100000) >> 14;
11091 name = banked_regname (sm);
11092
11093 if (name != NULL)
11094 func (stream, "%s", name);
11095 else
11096 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
11097 }
11098 else
11099 func (stream, "%s", psr_name (given & 0xff));
11100 break;
11101
11102 case '0': case '1': case '2': case '3': case '4':
11103 case '5': case '6': case '7': case '8': case '9':
11104 {
11105 int width;
11106 unsigned long val;
11107
11108 c = arm_decode_bitfield (c, given, &val, &width);
11109
11110 switch (*c)
11111 {
11112 case 's':
11113 if (val <= 3)
11114 func (stream, "%s", mve_vec_sizename[val]);
11115 else
11116 func (stream, "<undef size>");
11117 break;
11118
11119 case 'd':
11120 func (stream, "%lu", val);
11121 value_in_comment = val;
11122 break;
11123
11124 case 'D':
11125 func (stream, "%lu", val + 1);
11126 value_in_comment = val + 1;
11127 break;
11128
11129 case 'W':
11130 func (stream, "%lu", val * 4);
11131 value_in_comment = val * 4;
11132 break;
11133
11134 case 'S':
11135 if (val == 13)
11136 is_unpredictable = TRUE;
11137 /* Fall through. */
11138 case 'R':
11139 if (val == 15)
11140 is_unpredictable = TRUE;
11141 /* Fall through. */
11142 case 'r':
11143 func (stream, "%s", arm_regnames[val]);
11144 break;
11145
11146 case 'c':
11147 func (stream, "%s", arm_conditional[val]);
11148 break;
11149
11150 case '\'':
11151 c++;
11152 if (val == ((1ul << width) - 1))
11153 func (stream, "%c", *c);
11154 break;
11155
11156 case '`':
11157 c++;
11158 if (val == 0)
11159 func (stream, "%c", *c);
11160 break;
11161
11162 case '?':
11163 func (stream, "%c", c[(1 << width) - (int) val]);
11164 c += 1 << width;
11165 break;
11166
11167 case 'x':
11168 func (stream, "0x%lx", val & 0xffffffffUL);
11169 break;
11170
11171 default:
11172 abort ();
11173 }
11174 }
11175 break;
11176
11177 case 'L':
11178 /* PR binutils/12534
11179 If we have a PC relative offset in an LDRD or STRD
11180 instructions then display the decoded address. */
11181 if (((given >> 16) & 0xf) == 0xf)
11182 {
11183 bfd_vma offset = (given & 0xff) * 4;
11184
11185 if ((given & (1 << 23)) == 0)
11186 offset = - offset;
11187 func (stream, "\t; ");
11188 info->print_address_func ((pc & ~3) + 4 + offset, info);
11189 }
11190 break;
11191
11192 default:
11193 abort ();
11194 }
11195 }
11196
11197 if (value_in_comment > 32 || value_in_comment < -16)
11198 func (stream, "\t; 0x%lx", value_in_comment);
11199
11200 if (is_unpredictable)
11201 func (stream, UNPREDICTABLE_INSTRUCTION);
11202
11203 return;
11204 }
11205
11206 /* No match. */
11207 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
11208 return;
11209 }
11210
11211 /* Print data bytes on INFO->STREAM. */
11212
11213 static void
11214 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11215 struct disassemble_info *info,
11216 long given)
11217 {
11218 switch (info->bytes_per_chunk)
11219 {
11220 case 1:
11221 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
11222 break;
11223 case 2:
11224 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
11225 break;
11226 case 4:
11227 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
11228 break;
11229 default:
11230 abort ();
11231 }
11232 }
11233
11234 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
11235 being displayed in symbol relative addresses.
11236
11237 Also disallow private symbol, with __tagsym$$ prefix,
11238 from ARM RVCT toolchain being displayed. */
11239
11240 bfd_boolean
11241 arm_symbol_is_valid (asymbol * sym,
11242 struct disassemble_info * info ATTRIBUTE_UNUSED)
11243 {
11244 const char * name;
11245
11246 if (sym == NULL)
11247 return FALSE;
11248
11249 name = bfd_asymbol_name (sym);
11250
11251 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
11252 }
11253
11254 /* Parse the string of disassembler options. */
11255
11256 static void
11257 parse_arm_disassembler_options (const char *options)
11258 {
11259 const char *opt;
11260
11261 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
11262 {
11263 if (CONST_STRNEQ (opt, "reg-names-"))
11264 {
11265 unsigned int i;
11266 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11267 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11268 {
11269 regname_selected = i;
11270 break;
11271 }
11272
11273 if (i >= NUM_ARM_OPTIONS)
11274 /* xgettext: c-format */
11275 opcodes_error_handler (_("unrecognised register name set: %s"),
11276 opt);
11277 }
11278 else if (CONST_STRNEQ (opt, "force-thumb"))
11279 force_thumb = 1;
11280 else if (CONST_STRNEQ (opt, "no-force-thumb"))
11281 force_thumb = 0;
11282 else
11283 /* xgettext: c-format */
11284 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
11285 }
11286
11287 return;
11288 }
11289
11290 static bfd_boolean
11291 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11292 enum map_type *map_symbol);
11293
11294 /* Search back through the insn stream to determine if this instruction is
11295 conditionally executed. */
11296
11297 static void
11298 find_ifthen_state (bfd_vma pc,
11299 struct disassemble_info *info,
11300 bfd_boolean little)
11301 {
11302 unsigned char b[2];
11303 unsigned int insn;
11304 int status;
11305 /* COUNT is twice the number of instructions seen. It will be odd if we
11306 just crossed an instruction boundary. */
11307 int count;
11308 int it_count;
11309 unsigned int seen_it;
11310 bfd_vma addr;
11311
11312 ifthen_address = pc;
11313 ifthen_state = 0;
11314
11315 addr = pc;
11316 count = 1;
11317 it_count = 0;
11318 seen_it = 0;
11319 /* Scan backwards looking for IT instructions, keeping track of where
11320 instruction boundaries are. We don't know if something is actually an
11321 IT instruction until we find a definite instruction boundary. */
11322 for (;;)
11323 {
11324 if (addr == 0 || info->symbol_at_address_func (addr, info))
11325 {
11326 /* A symbol must be on an instruction boundary, and will not
11327 be within an IT block. */
11328 if (seen_it && (count & 1))
11329 break;
11330
11331 return;
11332 }
11333 addr -= 2;
11334 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
11335 if (status)
11336 return;
11337
11338 if (little)
11339 insn = (b[0]) | (b[1] << 8);
11340 else
11341 insn = (b[1]) | (b[0] << 8);
11342 if (seen_it)
11343 {
11344 if ((insn & 0xf800) < 0xe800)
11345 {
11346 /* Addr + 2 is an instruction boundary. See if this matches
11347 the expected boundary based on the position of the last
11348 IT candidate. */
11349 if (count & 1)
11350 break;
11351 seen_it = 0;
11352 }
11353 }
11354 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
11355 {
11356 enum map_type type = MAP_ARM;
11357 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
11358
11359 if (!found || (found && type == MAP_THUMB))
11360 {
11361 /* This could be an IT instruction. */
11362 seen_it = insn;
11363 it_count = count >> 1;
11364 }
11365 }
11366 if ((insn & 0xf800) >= 0xe800)
11367 count++;
11368 else
11369 count = (count + 2) | 1;
11370 /* IT blocks contain at most 4 instructions. */
11371 if (count >= 8 && !seen_it)
11372 return;
11373 }
11374 /* We found an IT instruction. */
11375 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
11376 if ((ifthen_state & 0xf) == 0)
11377 ifthen_state = 0;
11378 }
11379
11380 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11381 mapping symbol. */
11382
11383 static int
11384 is_mapping_symbol (struct disassemble_info *info, int n,
11385 enum map_type *map_type)
11386 {
11387 const char *name;
11388
11389 name = bfd_asymbol_name (info->symtab[n]);
11390 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
11391 && (name[2] == 0 || name[2] == '.'))
11392 {
11393 *map_type = ((name[1] == 'a') ? MAP_ARM
11394 : (name[1] == 't') ? MAP_THUMB
11395 : MAP_DATA);
11396 return TRUE;
11397 }
11398
11399 return FALSE;
11400 }
11401
11402 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11403 Returns nonzero if *MAP_TYPE was set. */
11404
11405 static int
11406 get_map_sym_type (struct disassemble_info *info,
11407 int n,
11408 enum map_type *map_type)
11409 {
11410 /* If the symbol is in a different section, ignore it. */
11411 if (info->section != NULL && info->section != info->symtab[n]->section)
11412 return FALSE;
11413
11414 return is_mapping_symbol (info, n, map_type);
11415 }
11416
11417 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
11418 Returns nonzero if *MAP_TYPE was set. */
11419
11420 static int
11421 get_sym_code_type (struct disassemble_info *info,
11422 int n,
11423 enum map_type *map_type)
11424 {
11425 elf_symbol_type *es;
11426 unsigned int type;
11427
11428 /* If the symbol is in a different section, ignore it. */
11429 if (info->section != NULL && info->section != info->symtab[n]->section)
11430 return FALSE;
11431
11432 es = *(elf_symbol_type **)(info->symtab + n);
11433 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11434
11435 /* If the symbol has function type then use that. */
11436 if (type == STT_FUNC || type == STT_GNU_IFUNC)
11437 {
11438 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11439 == ST_BRANCH_TO_THUMB)
11440 *map_type = MAP_THUMB;
11441 else
11442 *map_type = MAP_ARM;
11443 return TRUE;
11444 }
11445
11446 return FALSE;
11447 }
11448
11449 /* Search the mapping symbol state for instruction at pc. This is only
11450 applicable for elf target.
11451
11452 There is an assumption Here, info->private_data contains the correct AND
11453 up-to-date information about current scan process. The information will be
11454 used to speed this search process.
11455
11456 Return TRUE if the mapping state can be determined, and map_symbol
11457 will be updated accordingly. Otherwise, return FALSE. */
11458
11459 static bfd_boolean
11460 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11461 enum map_type *map_symbol)
11462 {
11463 bfd_vma addr, section_vma = 0;
11464 int n, last_sym = -1;
11465 bfd_boolean found = FALSE;
11466 bfd_boolean can_use_search_opt_p = FALSE;
11467
11468 /* Default to DATA. A text section is required by the ABI to contain an
11469 INSN mapping symbol at the start. A data section has no such
11470 requirement, hence if no mapping symbol is found the section must
11471 contain only data. This however isn't very useful if the user has
11472 fully stripped the binaries. If this is the case use the section
11473 attributes to determine the default. If we have no section default to
11474 INSN as well, as we may be disassembling some raw bytes on a baremetal
11475 HEX file or similar. */
11476 enum map_type type = MAP_DATA;
11477 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
11478 type = MAP_ARM;
11479 struct arm_private_data *private_data;
11480
11481 if (info->private_data == NULL
11482 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
11483 return FALSE;
11484
11485 private_data = info->private_data;
11486
11487 /* First, look for mapping symbols. */
11488 if (info->symtab_size != 0)
11489 {
11490 if (pc <= private_data->last_mapping_addr)
11491 private_data->last_mapping_sym = -1;
11492
11493 /* Start scanning at the start of the function, or wherever
11494 we finished last time. */
11495 n = info->symtab_pos + 1;
11496
11497 /* If the last stop offset is different from the current one it means we
11498 are disassembling a different glob of bytes. As such the optimization
11499 would not be safe and we should start over. */
11500 can_use_search_opt_p
11501 = private_data->last_mapping_sym >= 0
11502 && info->stop_offset == private_data->last_stop_offset;
11503
11504 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11505 n = private_data->last_mapping_sym;
11506
11507 /* Look down while we haven't passed the location being disassembled.
11508 The reason for this is that there's no defined order between a symbol
11509 and an mapping symbol that may be at the same address. We may have to
11510 look at least one position ahead. */
11511 for (; n < info->symtab_size; n++)
11512 {
11513 addr = bfd_asymbol_value (info->symtab[n]);
11514 if (addr > pc)
11515 break;
11516 if (get_map_sym_type (info, n, &type))
11517 {
11518 last_sym = n;
11519 found = TRUE;
11520 }
11521 }
11522
11523 if (!found)
11524 {
11525 n = info->symtab_pos;
11526 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11527 n = private_data->last_mapping_sym;
11528
11529 /* No mapping symbol found at this address. Look backwards
11530 for a preceeding one, but don't go pass the section start
11531 otherwise a data section with no mapping symbol can pick up
11532 a text mapping symbol of a preceeding section. The documentation
11533 says section can be NULL, in which case we will seek up all the
11534 way to the top. */
11535 if (info->section)
11536 section_vma = info->section->vma;
11537
11538 for (; n >= 0; n--)
11539 {
11540 addr = bfd_asymbol_value (info->symtab[n]);
11541 if (addr < section_vma)
11542 break;
11543
11544 if (get_map_sym_type (info, n, &type))
11545 {
11546 last_sym = n;
11547 found = TRUE;
11548 break;
11549 }
11550 }
11551 }
11552 }
11553
11554 /* If no mapping symbol was found, try looking up without a mapping
11555 symbol. This is done by walking up from the current PC to the nearest
11556 symbol. We don't actually have to loop here since symtab_pos will
11557 contain the nearest symbol already. */
11558 if (!found)
11559 {
11560 n = info->symtab_pos;
11561 if (n >= 0 && get_sym_code_type (info, n, &type))
11562 {
11563 last_sym = n;
11564 found = TRUE;
11565 }
11566 }
11567
11568 private_data->last_mapping_sym = last_sym;
11569 private_data->last_type = type;
11570 private_data->last_stop_offset = info->stop_offset;
11571
11572 *map_symbol = type;
11573 return found;
11574 }
11575
11576 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
11577 of the supplied arm_feature_set structure with bitmasks indicating
11578 the supported base architectures and coprocessor extensions.
11579
11580 FIXME: This could more efficiently implemented as a constant array,
11581 although it would also be less robust. */
11582
11583 static void
11584 select_arm_features (unsigned long mach,
11585 arm_feature_set * features)
11586 {
11587 arm_feature_set arch_fset;
11588 const arm_feature_set fpu_any = FPU_ANY;
11589
11590 #undef ARM_SET_FEATURES
11591 #define ARM_SET_FEATURES(FSET) \
11592 { \
11593 const arm_feature_set fset = FSET; \
11594 arch_fset = fset; \
11595 }
11596
11597 /* When several architecture versions share the same bfd_mach_arm_XXX value
11598 the most featureful is chosen. */
11599 switch (mach)
11600 {
11601 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
11602 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11603 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
11604 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11605 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
11606 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11607 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
11608 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11609 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11610 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
11611 case bfd_mach_arm_ep9312:
11612 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11613 ARM_CEXT_MAVERICK | FPU_MAVERICK));
11614 break;
11615 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11616 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11617 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11618 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
11619 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11620 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11621 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11622 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11623 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11624 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
11625 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
11626 case bfd_mach_arm_8:
11627 {
11628 /* Add bits for extensions that Armv8.5-A recognizes. */
11629 arm_feature_set armv8_5_ext_fset
11630 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
11631 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
11632 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
11633 break;
11634 }
11635 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
11636 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
11637 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
11638 case bfd_mach_arm_8_1M_MAIN:
11639 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
11640 force_thumb = 1;
11641 break;
11642 /* If the machine type is unknown allow all architecture types and all
11643 extensions. */
11644 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
11645 default:
11646 abort ();
11647 }
11648 #undef ARM_SET_FEATURES
11649
11650 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
11651 and thus on bfd_mach_arm_XXX value. Therefore for a given
11652 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
11653 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
11654 }
11655
11656
11657 /* NOTE: There are no checks in these routines that
11658 the relevant number of data bytes exist. */
11659
11660 static int
11661 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
11662 {
11663 unsigned char b[4];
11664 long given;
11665 int status;
11666 int is_thumb = FALSE;
11667 int is_data = FALSE;
11668 int little_code;
11669 unsigned int size = 4;
11670 void (*printer) (bfd_vma, struct disassemble_info *, long);
11671 bfd_boolean found = FALSE;
11672 struct arm_private_data *private_data;
11673
11674 if (info->disassembler_options)
11675 {
11676 parse_arm_disassembler_options (info->disassembler_options);
11677
11678 /* To avoid repeated parsing of these options, we remove them here. */
11679 info->disassembler_options = NULL;
11680 }
11681
11682 /* PR 10288: Control which instructions will be disassembled. */
11683 if (info->private_data == NULL)
11684 {
11685 static struct arm_private_data private;
11686
11687 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
11688 /* If the user did not use the -m command line switch then default to
11689 disassembling all types of ARM instruction.
11690
11691 The info->mach value has to be ignored as this will be based on
11692 the default archictecture for the target and/or hints in the notes
11693 section, but it will never be greater than the current largest arm
11694 machine value (iWMMXt2), which is only equivalent to the V5TE
11695 architecture. ARM architectures have advanced beyond the machine
11696 value encoding, and these newer architectures would be ignored if
11697 the machine value was used.
11698
11699 Ie the -m switch is used to restrict which instructions will be
11700 disassembled. If it is necessary to use the -m switch to tell
11701 objdump that an ARM binary is being disassembled, eg because the
11702 input is a raw binary file, but it is also desired to disassemble
11703 all ARM instructions then use "-marm". This will select the
11704 "unknown" arm architecture which is compatible with any ARM
11705 instruction. */
11706 info->mach = bfd_mach_arm_unknown;
11707
11708 /* Compute the architecture bitmask from the machine number.
11709 Note: This assumes that the machine number will not change
11710 during disassembly.... */
11711 select_arm_features (info->mach, & private.features);
11712
11713 private.last_mapping_sym = -1;
11714 private.last_mapping_addr = 0;
11715 private.last_stop_offset = 0;
11716
11717 info->private_data = & private;
11718 }
11719
11720 private_data = info->private_data;
11721
11722 /* Decide if our code is going to be little-endian, despite what the
11723 function argument might say. */
11724 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
11725
11726 /* For ELF, consult the symbol table to determine what kind of code
11727 or data we have. */
11728 if (info->symtab_size != 0
11729 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
11730 {
11731 bfd_vma addr;
11732 int n;
11733 int last_sym = -1;
11734 enum map_type type = MAP_ARM;
11735
11736 found = mapping_symbol_for_insn (pc, info, &type);
11737 last_sym = private_data->last_mapping_sym;
11738
11739 is_thumb = (private_data->last_type == MAP_THUMB);
11740 is_data = (private_data->last_type == MAP_DATA);
11741
11742 /* Look a little bit ahead to see if we should print out
11743 two or four bytes of data. If there's a symbol,
11744 mapping or otherwise, after two bytes then don't
11745 print more. */
11746 if (is_data)
11747 {
11748 size = 4 - (pc & 3);
11749 for (n = last_sym + 1; n < info->symtab_size; n++)
11750 {
11751 addr = bfd_asymbol_value (info->symtab[n]);
11752 if (addr > pc
11753 && (info->section == NULL
11754 || info->section == info->symtab[n]->section))
11755 {
11756 if (addr - pc < size)
11757 size = addr - pc;
11758 break;
11759 }
11760 }
11761 /* If the next symbol is after three bytes, we need to
11762 print only part of the data, so that we can use either
11763 .byte or .short. */
11764 if (size == 3)
11765 size = (pc & 1) ? 1 : 2;
11766 }
11767 }
11768
11769 if (info->symbols != NULL)
11770 {
11771 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
11772 {
11773 coff_symbol_type * cs;
11774
11775 cs = coffsymbol (*info->symbols);
11776 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
11777 || cs->native->u.syment.n_sclass == C_THUMBSTAT
11778 || cs->native->u.syment.n_sclass == C_THUMBLABEL
11779 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
11780 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
11781 }
11782 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
11783 && !found)
11784 {
11785 /* If no mapping symbol has been found then fall back to the type
11786 of the function symbol. */
11787 elf_symbol_type * es;
11788 unsigned int type;
11789
11790 es = *(elf_symbol_type **)(info->symbols);
11791 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11792
11793 is_thumb =
11794 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11795 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
11796 }
11797 else if (bfd_asymbol_flavour (*info->symbols)
11798 == bfd_target_mach_o_flavour)
11799 {
11800 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
11801
11802 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
11803 }
11804 }
11805
11806 if (force_thumb)
11807 is_thumb = TRUE;
11808
11809 if (is_data)
11810 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11811 else
11812 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11813
11814 info->bytes_per_line = 4;
11815
11816 /* PR 10263: Disassemble data if requested to do so by the user. */
11817 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
11818 {
11819 int i;
11820
11821 /* Size was already set above. */
11822 info->bytes_per_chunk = size;
11823 printer = print_insn_data;
11824
11825 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
11826 given = 0;
11827 if (little)
11828 for (i = size - 1; i >= 0; i--)
11829 given = b[i] | (given << 8);
11830 else
11831 for (i = 0; i < (int) size; i++)
11832 given = b[i] | (given << 8);
11833 }
11834 else if (!is_thumb)
11835 {
11836 /* In ARM mode endianness is a straightforward issue: the instruction
11837 is four bytes long and is either ordered 0123 or 3210. */
11838 printer = print_insn_arm;
11839 info->bytes_per_chunk = 4;
11840 size = 4;
11841
11842 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
11843 if (little_code)
11844 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
11845 else
11846 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
11847 }
11848 else
11849 {
11850 /* In Thumb mode we have the additional wrinkle of two
11851 instruction lengths. Fortunately, the bits that determine
11852 the length of the current instruction are always to be found
11853 in the first two bytes. */
11854 printer = print_insn_thumb16;
11855 info->bytes_per_chunk = 2;
11856 size = 2;
11857
11858 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
11859 if (little_code)
11860 given = (b[0]) | (b[1] << 8);
11861 else
11862 given = (b[1]) | (b[0] << 8);
11863
11864 if (!status)
11865 {
11866 /* These bit patterns signal a four-byte Thumb
11867 instruction. */
11868 if ((given & 0xF800) == 0xF800
11869 || (given & 0xF800) == 0xF000
11870 || (given & 0xF800) == 0xE800)
11871 {
11872 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
11873 if (little_code)
11874 given = (b[0]) | (b[1] << 8) | (given << 16);
11875 else
11876 given = (b[1]) | (b[0] << 8) | (given << 16);
11877
11878 printer = print_insn_thumb32;
11879 size = 4;
11880 }
11881 }
11882
11883 if (ifthen_address != pc)
11884 find_ifthen_state (pc, info, little_code);
11885
11886 if (ifthen_state)
11887 {
11888 if ((ifthen_state & 0xf) == 0x8)
11889 ifthen_next_state = 0;
11890 else
11891 ifthen_next_state = (ifthen_state & 0xe0)
11892 | ((ifthen_state & 0xf) << 1);
11893 }
11894 }
11895
11896 if (status)
11897 {
11898 info->memory_error_func (status, pc, info);
11899 return -1;
11900 }
11901 if (info->flags & INSN_HAS_RELOC)
11902 /* If the instruction has a reloc associated with it, then
11903 the offset field in the instruction will actually be the
11904 addend for the reloc. (We are using REL type relocs).
11905 In such cases, we can ignore the pc when computing
11906 addresses, since the addend is not currently pc-relative. */
11907 pc = 0;
11908
11909 printer (pc, info, given);
11910
11911 if (is_thumb)
11912 {
11913 ifthen_state = ifthen_next_state;
11914 ifthen_address += size;
11915 }
11916 return size;
11917 }
11918
11919 int
11920 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
11921 {
11922 /* Detect BE8-ness and record it in the disassembler info. */
11923 if (info->flavour == bfd_target_elf_flavour
11924 && info->section != NULL
11925 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
11926 info->endian_code = BFD_ENDIAN_LITTLE;
11927
11928 return print_insn (pc, info, FALSE);
11929 }
11930
11931 int
11932 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
11933 {
11934 return print_insn (pc, info, TRUE);
11935 }
11936
11937 const disasm_options_and_args_t *
11938 disassembler_options_arm (void)
11939 {
11940 static disasm_options_and_args_t *opts_and_args;
11941
11942 if (opts_and_args == NULL)
11943 {
11944 disasm_options_t *opts;
11945 unsigned int i;
11946
11947 opts_and_args = XNEW (disasm_options_and_args_t);
11948 opts_and_args->args = NULL;
11949
11950 opts = &opts_and_args->options;
11951 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11952 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11953 opts->arg = NULL;
11954 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11955 {
11956 opts->name[i] = regnames[i].name;
11957 if (regnames[i].description != NULL)
11958 opts->description[i] = _(regnames[i].description);
11959 else
11960 opts->description[i] = NULL;
11961 }
11962 /* The array we return must be NULL terminated. */
11963 opts->name[i] = NULL;
11964 opts->description[i] = NULL;
11965 }
11966
11967 return opts_and_args;
11968 }
11969
11970 void
11971 print_arm_disassembler_options (FILE *stream)
11972 {
11973 unsigned int i, max_len = 0;
11974 fprintf (stream, _("\n\
11975 The following ARM specific disassembler options are supported for use with\n\
11976 the -M switch:\n"));
11977
11978 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11979 {
11980 unsigned int len = strlen (regnames[i].name);
11981 if (max_len < len)
11982 max_len = len;
11983 }
11984
11985 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
11986 fprintf (stream, " %s%*c %s\n",
11987 regnames[i].name,
11988 (int)(max_len - strlen (regnames[i].name)), ' ',
11989 _(regnames[i].description));
11990 }
GDB Binutils - Deliverables
This page took 0.316997 seconds and 5 git commands to generate.