opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
   3    2004, 2005, 2006, 2007, 2008, 2009, 2010, 2012
   4    Free Software Foundation, Inc.
   5    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   6    Modification by James G. Smith (jsmith@cygnus.co.uk)
   7
   8    This file is part of libopcodes.
   9
  10    This library is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 3 of the License, or
  13    (at your option) any later version.
  14
  15    It is distributed in the hope that it will be useful, but WITHOUT
  16    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  17    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  18    License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  23    MA 02110-1301, USA.  */
  24
  25 #include "sysdep.h"
  26
  27 #include "dis-asm.h"
  28 #include "opcode/arm.h"
  29 #include "opintl.h"
  30 #include "safe-ctype.h"
  31 #include "floatformat.h"
  32
  33 /* FIXME: This shouldn't be done here.  */
  34 #include "coff/internal.h"
  35 #include "libcoff.h"
  36 #include "elf-bfd.h"
  37 #include "elf/internal.h"
  38 #include "elf/arm.h"
  39
  40 /* FIXME: Belongs in global header.  */
  41 #ifndef strneq
  42 #define strneq(a,b,n)   (strncmp ((a), (b), (n)) == 0)
  43 #endif
  44
  45 #ifndef NUM_ELEM
  46 #define NUM_ELEM(a)     (sizeof (a) / sizeof (a)[0])
  47 #endif
  48
  49 /* Cached mapping symbol state.  */
  50 enum map_type
  51 {
  52   MAP_ARM,
  53   MAP_THUMB,
  54   MAP_DATA
  55 };
  56
  57 struct arm_private_data
  58 {
  59   /* The features to use when disassembling optional instructions.  */
  60   arm_feature_set features;
  61
  62   /* Whether any mapping symbols are present in the provided symbol
  63      table.  -1 if we do not know yet, otherwise 0 or 1.  */
  64   int has_mapping_symbols;
  65
  66   /* Track the last type (although this doesn't seem to be useful) */
  67   enum map_type last_type;
  68
  69   /* Tracking symbol table information */
  70   int last_mapping_sym;
  71   bfd_vma last_mapping_addr;
  72 };
  73
  74 struct opcode32
  75 {
  76   unsigned long arch;           /* Architecture defining this insn.  */
  77   unsigned long value;          /* If arch == 0 then value is a sentinel.  */
  78   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
  79   const char *  assembler;      /* How to disassemble this insn.  */
  80 };
  81
  82 struct opcode16
  83 {
  84   unsigned long arch;           /* Architecture defining this insn.  */
  85   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
  86   const char *assembler;        /* How to disassemble this insn.  */
  87 };
  88
  89 /* print_insn_coprocessor recognizes the following format control codes:
  90
  91    %%                   %
  92
  93    %c                   print condition code (always bits 28-31 in ARM mode)
  94    %q                   print shifter argument
  95    %u                   print condition code (unconditional in ARM mode,
  96                           UNPREDICTABLE if not AL in Thumb)
  97    %A                   print address for ldc/stc/ldf/stf instruction
  98    %B                   print vstm/vldm register list
  99    %I                   print cirrus signed shift immediate: bits 0..3|4..6
 100    %F                   print the COUNT field of a LFM/SFM instruction.
 101    %P                   print floating point precision in arithmetic insn
 102    %Q                   print floating point precision in ldf/stf insn
 103    %R                   print floating point rounding mode
 104
 105    %<bitfield>c         print as a condition code (for vsel)
 106    %<bitfield>r         print as an ARM register
 107    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 108    %<bitfield>ru        as %<>r but each u register must be unique.
 109    %<bitfield>d         print the bitfield in decimal
 110    %<bitfield>k         print immediate for VFPv3 conversion instruction
 111    %<bitfield>x         print the bitfield in hex
 112    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 113    %<bitfield>f         print a floating point constant if >7 else a
 114                         floating point register
 115    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 116    %<bitfield>g         print as an iWMMXt 64-bit register
 117    %<bitfield>G         print as an iWMMXt general purpose or control register
 118    %<bitfield>D         print as a NEON D register
 119    %<bitfield>Q         print as a NEON Q register
 120
 121    %y<code>             print a single precision VFP reg.
 122                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 123    %z<code>             print a double precision VFP reg
 124                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 125
 126    %<bitfield>'c        print specified char iff bitfield is all ones
 127    %<bitfield>`c        print specified char iff bitfield is all zeroes
 128    %<bitfield>?ab...    select from array of values in big endian order
 129
 130    %L                   print as an iWMMXt N/M width field.
 131    %Z                   print the Immediate of a WSHUFH instruction.
 132    %l                   like 'A' except use byte offsets for 'B' & 'H'
 133                         versions.
 134    %i                   print 5-bit immediate in bits 8,3..0
 135                         (print "32" when 0)
 136    %r                   print register offset address for wldt/wstr instruction.  */
 137
 138 enum opcode_sentinel_enum
 139 {
 140   SENTINEL_IWMMXT_START = 1,
 141   SENTINEL_IWMMXT_END,
 142   SENTINEL_GENERIC_START
 143 } opcode_sentinels;
 144
 145 #define UNDEFINED_INSTRUCTION      "\t\t; <UNDEFINED> instruction: %0-31x"
 146 #define UNPREDICTABLE_INSTRUCTION  "\t; <UNPREDICTABLE>"
 147
 148 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 149
 150 static const struct opcode32 coprocessor_opcodes[] =
 151 {
 152   /* XScale instructions.  */
 153   {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
 154   {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
 155   {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 156   {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 157   {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 158
 159   /* Intel Wireless MMX technology instructions.  */
 160   { 0, SENTINEL_IWMMXT_START, 0, "" },
 161   {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 162   {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 163   {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 164   {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 165   {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 166   {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 167   {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 168   {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 169   {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 170   {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 171   {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 172   {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 173   {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 174   {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 175   {ARM_CEXT_XSCALE, 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 176   {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 177   {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 178   {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 179   {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 180   {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 181   {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 182   {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 183   {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 184   {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 185   {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 186   {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 187   {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 188   {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 189   {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 190   {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 191   {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 192   {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 193   {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 194   {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 195   {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
 196   {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 197   {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 198   {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 199   {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 200   {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 201   {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 202   {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 203   {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 204   {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 205   {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 206   {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 207   {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 208   {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 209   {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
 210   {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 211   {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 212   {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 213   {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 214   {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
 215   {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 216   {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 217   {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
 218   {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 219   {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 220   {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
 221   {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 222   {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 223   {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 224   {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 225   {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 226   {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 227   {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 228   {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 229   {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 230   {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 231   {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 232   {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 233   {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 234   {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 235   {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 236   { 0, SENTINEL_IWMMXT_END, 0, "" },
 237
 238   /* Floating point coprocessor (FPA) instructions.  */
 239   {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 240   {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 241   {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 242   {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 243   {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 244   {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 245   {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 246   {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 247   {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 248   {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 249   {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 250   {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 251   {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 252   {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 253   {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 254   {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 255   {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 256   {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 257   {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 258   {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 259   {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 260   {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 261   {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 262   {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 263   {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 264   {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 265   {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 266   {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 267   {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 268   {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 269   {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 270   {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 271   {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 272   {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 273   {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 274   {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 275   {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 276   {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 277   {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 278   {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 279   {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 280   {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 281   {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 282
 283   /* Register load/store.  */
 284   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 285   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 286   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 287   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 288   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 289   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 290   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 291   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 292   {FPU_VFP_EXT_V1xD, 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 293   {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 294   {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 295   {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 296   {FPU_VFP_EXT_V1xD, 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 297   {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 298   {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 299   {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 300
 301   {FPU_VFP_EXT_V1xD, 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 302   {FPU_VFP_EXT_V1xD, 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 303   {FPU_VFP_EXT_V1xD, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 304   {FPU_VFP_EXT_V1xD, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 305
 306   /* Data transfer between ARM and NEON registers.  */
 307   {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
 308   {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
 309   {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
 310   {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
 311   {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
 312   {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
 313   {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 314   {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 315   {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
 316   {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
 317   {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
 318   {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
 319   {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
 320   {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 321   /* Half-precision conversion instructions.  */
 322   {FPU_VFP_EXT_ARMV8, 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
 323   {FPU_VFP_EXT_ARMV8, 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
 324   {FPU_VFP_EXT_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 325   {FPU_VFP_EXT_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 326
 327   /* Floating point coprocessor (VFP) instructions.  */
 328   {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
 329   {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
 330   {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
 331   {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
 332   {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
 333   {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
 334   {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
 335   {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
 336   {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
 337   {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
 338   {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
 339   {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
 340   {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
 341   {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
 342   {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
 343   {FPU_VFP_EXT_V1, 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
 344   {FPU_VFP_EXT_V1, 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
 345   {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 346   {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 347   {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 348   {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 349   {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
 350   {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
 351   {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 352   {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 353   {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 354   {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 355   {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 356   {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 357   {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 358   {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 359   {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 360   {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 361   {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 362   {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 363   {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 364   {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 365   {FPU_VFP_EXT_V3xD, 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 366   {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
 367   {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 368   {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 369   {FPU_VFP_EXT_V3xD, 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
 370   {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
 371   {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 372   {FPU_VFP_EXT_V3xD, 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"},
 373   {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"},
 374   {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
 375   {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
 376   {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
 377   {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
 378   {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
 379   {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
 380   {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
 381   {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
 382   {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
 383   {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
 384   {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
 385   {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
 386   {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
 387   {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
 388   {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
 389   {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
 390   {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
 391   {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
 392   {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
 393   {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
 394   {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
 395
 396   /* Cirrus coprocessor instructions.  */
 397   {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 398   {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 399   {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 400   {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 401   {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 402   {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 403   {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 404   {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 405   {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 406   {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 407   {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 408   {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 409   {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 410   {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 411   {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 412   {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 413   {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
 414   {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
 415   {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
 416   {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
 417   {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
 418   {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
 419   {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
 420   {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
 421   {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
 422   {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
 423   {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
 424   {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
 425   {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
 426   {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
 427   {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
 428   {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
 429   {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
 430   {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
 431   {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
 432   {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
 433   {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
 434   {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
 435   {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
 436   {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
 437   {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
 438   {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
 439   {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
 440   {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
 441   {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
 442   {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
 443   {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
 444   {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
 445   {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
 446   {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
 447   {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
 448   {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
 449   {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
 450   {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
 451   {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
 452   {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
 453   {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
 454   {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
 455   {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
 456   {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
 457   {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
 458   {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
 459   {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 460   {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 461   {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 462   {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 463   {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 464   {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 465   {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
 466   {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
 467   {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
 468   {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
 469   {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 470   {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 471   {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 472   {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 473   {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 474   {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 475   {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 476   {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 477   {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 478   {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 479   {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 480   {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 481
 482   /* VFP Fused multiply add instructions.  */
 483   {FPU_VFP_EXT_FMA, 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
 484   {FPU_VFP_EXT_FMA, 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
 485   {FPU_VFP_EXT_FMA, 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
 486   {FPU_VFP_EXT_FMA, 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
 487   {FPU_VFP_EXT_FMA, 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
 488   {FPU_VFP_EXT_FMA, 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
 489   {FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
 490   {FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
 491
 492   /* FP v5.  */
 493   {FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
 494   {FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
 495   {FPU_VFP_EXT_ARMV8, 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
 496   {FPU_VFP_EXT_ARMV8, 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
 497   {FPU_VFP_EXT_ARMV8, 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
 498   {FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
 499   {FPU_VFP_EXT_ARMV8, 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
 500   {FPU_VFP_EXT_ARMV8, 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
 501   {FPU_VFP_EXT_ARMV8, 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32.f32\t%y1, %y0"},
 502   {FPU_VFP_EXT_ARMV8, 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64.f64\t%z1, %z0"},
 503   {FPU_VFP_EXT_ARMV8, 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32.f32\t%y1, %y0"},
 504   {FPU_VFP_EXT_ARMV8, 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64.f64\t%z1, %z0"},
 505
 506   /* Generic coprocessor instructions.  */
 507   { 0, SENTINEL_GENERIC_START, 0, "" },
 508   {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
 509   {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 510   {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 511   {ARM_EXT_V2, 0x0e10f010, 0x0f10f010, "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
 512   {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 513   {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 514   {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
 515   {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
 516
 517   /* V6 coprocessor instructions.  */
 518   {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 519   {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
 520
 521   /* V5 coprocessor instructions.  */
 522   {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 523   {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 524   {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 525   {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 526   {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 527
 528   {0, 0, 0, 0}
 529 };
 530
 531 /* Neon opcode table:  This does not encode the top byte -- that is
 532    checked by the print_insn_neon routine, as it depends on whether we are
 533    doing thumb32 or arm32 disassembly.  */
 534
 535 /* print_insn_neon recognizes the following format control codes:
 536
 537    %%                   %
 538
 539    %c                   print condition code
 540    %u                   print condition code (unconditional in ARM mode,
 541                           UNPREDICTABLE if not AL in Thumb)
 542    %A                   print v{st,ld}[1234] operands
 543    %B                   print v{st,ld}[1234] any one operands
 544    %C                   print v{st,ld}[1234] single->all operands
 545    %D                   print scalar
 546    %E                   print vmov, vmvn, vorr, vbic encoded constant
 547    %F                   print vtbl,vtbx register list
 548
 549    %<bitfield>r         print as an ARM register
 550    %<bitfield>d         print the bitfield in decimal
 551    %<bitfield>e         print the 2^N - bitfield in decimal
 552    %<bitfield>D         print as a NEON D register
 553    %<bitfield>Q         print as a NEON Q register
 554    %<bitfield>R         print as a NEON D or Q register
 555    %<bitfield>Sn        print byte scaled width limited by n
 556    %<bitfield>Tn        print short scaled width limited by n
 557    %<bitfield>Un        print long scaled width limited by n
 558
 559    %<bitfield>'c        print specified char iff bitfield is all ones
 560    %<bitfield>`c        print specified char iff bitfield is all zeroes
 561    %<bitfield>?ab...    select from array of values in big endian order.  */
 562
 563 static const struct opcode32 neon_opcodes[] =
 564 {
 565   /* Extract.  */
 566   {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
 567   {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
 568
 569   /* Move data element to all lanes.  */
 570   {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
 571   {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
 572   {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
 573
 574   /* Table lookup.  */
 575   {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
 576   {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
 577
 578   /* Half-precision conversions.  */
 579   {FPU_VFP_EXT_FP16, 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
 580   {FPU_VFP_EXT_FP16, 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
 581
 582   /* NEON fused multiply add instructions.  */
 583   {FPU_NEON_EXT_FMA, 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 584   {FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 585
 586   /* Two registers, miscellaneous.  */
 587   {FPU_NEON_EXT_ARMV8, 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32.f32\t%12-15,22R, %0-3,5R"},
 588   {FPU_NEON_EXT_ARMV8, 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
 589   {FPU_CRYPTO_EXT_ARMV8, 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
 590   {FPU_CRYPTO_EXT_ARMV8, 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
 591   {FPU_CRYPTO_EXT_ARMV8, 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
 592   {FPU_CRYPTO_EXT_ARMV8, 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
 593   {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
 594   {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
 595   {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
 596   {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
 597   {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
 598   {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
 599   {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
 600   {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
 601   {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
 602   {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
 603   {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
 604   {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
 605   {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
 606   {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 607   {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 608   {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 609   {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
 610   {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
 611   {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
 612   {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
 613   {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 614   {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 615   {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 616   {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
 617   {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
 618   {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
 619   {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
 620   {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
 621   {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
 622   {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
 623   {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
 624   {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
 625   {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
 626
 627   /* Three registers of the same length.  */
 628   {FPU_NEON_EXT_ARMV8, 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 629   {FPU_NEON_EXT_ARMV8, 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 630   {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 631   {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 632   {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 633   {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 634   {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 635   {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 636   {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 637   {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 638   {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 639   {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 640   {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 641   {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 642   {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 643   {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 644   {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 645   {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 646   {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 647   {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 648   {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 649   {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 650   {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 651   {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 652   {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 653   {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 654   {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 655   {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 656   {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
 657   {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 658   {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 659   {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
 660   {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 661   {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
 662   {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 663   {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 664   {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
 665   {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 666   {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
 667   {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 668   {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 669   {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
 670   {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 671   {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 672   {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
 673   {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
 674   {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
 675   {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
 676   {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 677   {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 678   {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 679   {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 680   {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 681   {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 682   {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 683
 684   /* One register and an immediate value.  */
 685   {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
 686   {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
 687   {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
 688   {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
 689   {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
 690   {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
 691   {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
 692   {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
 693   {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
 694   {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
 695   {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
 696   {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
 697   {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
 698
 699   /* Two registers and a shift amount.  */
 700   {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 701   {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 702   {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 703   {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 704   {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 705   {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 706   {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"},
 707   {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 708   {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 709   {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
 710   {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
 711   {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
 712   {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
 713   {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 714   {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 715   {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 716   {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 717   {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"},
 718   {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
 719   {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
 720   {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
 721   {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
 722   {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
 723   {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 724   {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 725   {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
 726   {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
 727   {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
 728   {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
 729   {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"},
 730   {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
 731   {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
 732   {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
 733   {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
 734   {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
 735   {FPU_NEON_EXT_V1, 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 736   {FPU_NEON_EXT_V1, 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 737   {FPU_NEON_EXT_V1, 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 738   {FPU_NEON_EXT_V1, 0xf2a00950, 0xfea00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 739   {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
 740   {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
 741   {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
 742   {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
 743   {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
 744   {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
 745   {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
 746   {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
 747   {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
 748   {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
 749   {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
 750   {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
 751   {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
 752   {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
 753   {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
 754   {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
 755   {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
 756   {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
 757   {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
 758
 759   /* Three registers of different lengths.  */
 760   {FPU_CRYPTO_EXT_ARMV8, 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 761   {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 762   {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
 763   {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
 764   {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 765   {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 766   {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 767   {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
 768   {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
 769   {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 770   {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
 771   {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 772   {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
 773   {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 774   {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 775   {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 776   {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 777   {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 778
 779   /* Two registers and a scalar.  */
 780   {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 781   {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
 782   {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 783   {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 784   {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 785   {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 786   {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 787   {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
 788   {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 789   {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 790   {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 791   {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
 792   {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
 793   {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
 794   {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
 795   {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
 796   {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
 797   {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
 798   {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
 799   {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 800   {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 801   {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 802
 803   /* Element and structure load/store.  */
 804   {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
 805   {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
 806   {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
 807   {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
 808   {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
 809   {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
 810   {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
 811   {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
 812   {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
 813   {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
 814   {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
 815   {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
 816   {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
 817   {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
 818   {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
 819   {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
 820   {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
 821   {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
 822   {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
 823
 824   {0,0 ,0, 0}
 825 };
 826
 827 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
 828    ordered: they must be searched linearly from the top to obtain a correct
 829    match.  */
 830
 831 /* print_insn_arm recognizes the following format control codes:
 832
 833    %%                   %
 834
 835    %a                   print address for ldr/str instruction
 836    %s                   print address for ldr/str halfword/signextend instruction
 837    %S                   like %s but allow UNPREDICTABLE addressing
 838    %b                   print branch destination
 839    %c                   print condition code (always bits 28-31)
 840    %m                   print register mask for ldm/stm instruction
 841    %o                   print operand2 (immediate or register + shift)
 842    %p                   print 'p' iff bits 12-15 are 15
 843    %t                   print 't' iff bit 21 set and bit 24 clear
 844    %B                   print arm BLX(1) destination
 845    %C                   print the PSR sub type.
 846    %U                   print barrier type.
 847    %P                   print address for pli instruction.
 848
 849    %<bitfield>r         print as an ARM register
 850    %<bitfield>T         print as an ARM register + 1
 851    %<bitfield>R         as %r but r15 is UNPREDICTABLE
 852    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
 853    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
 854    %<bitfield>d         print the bitfield in decimal
 855    %<bitfield>W         print the bitfield plus one in decimal
 856    %<bitfield>x         print the bitfield in hex
 857    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 858
 859    %<bitfield>'c        print specified char iff bitfield is all ones
 860    %<bitfield>`c        print specified char iff bitfield is all zeroes
 861    %<bitfield>?ab...    select from array of values in big endian order
 862
 863    %e                   print arm SMI operand (bits 0..7,8..19).
 864    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
 865    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
 866    %R                   print the SPSR/CPSR or banked register of an MRS.  */
 867
 868 static const struct opcode32 arm_opcodes[] =
 869 {
 870   /* ARM instructions.  */
 871   {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
 872   {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
 873   {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
 874   {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
 875   {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
 876   {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
 877   {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
 878
 879   /* V8 instructions.  */
 880   {ARM_EXT_V8,   0x0320f005, 0x0fffffff, "sevl"},
 881   {ARM_EXT_V8,   0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
 882   {ARM_EXT_V8,   0x01800e90, 0x0ff00ff0, "strlex%c\t%12-15r, %0-3r, [%16-19R]"},
 883   {ARM_EXT_V8,   0x01900e9f, 0x0ff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
 884   {ARM_EXT_V8,   0x01a00e90, 0x0ff00ff0, "strlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
 885   {ARM_EXT_V8,   0x01b00e9f, 0x0ff00fff, "ldraexd%c\t%12-15r, %12-15T, [%16-19R]"},
 886   {ARM_EXT_V8,   0x01c00e90, 0x0ff00ff0, "strlexb%c\t%12-15r, %0-3r, [%16-19R]"},
 887   {ARM_EXT_V8,   0x01d00e9f, 0x0ff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
 888   {ARM_EXT_V8,   0x01e00e90, 0x0ff00ff0, "strlexh%c\t%12-15r, %0-3r, [%16-19R]"},
 889   {ARM_EXT_V8,   0x01f00e9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
 890   {ARM_EXT_V8,   0x0180fc90, 0x0ff0fff0, "strl%c\t%0-3r, [%16-19R]"},
 891   {ARM_EXT_V8,   0x01900c9f, 0x0ff00fff, "ldra%c\t%12-15r, [%16-19R]"},
 892   {ARM_EXT_V8,   0x01c0fc90, 0x0ff0fff0, "strlb%c\t%0-3r, [%16-19R]"},
 893   {ARM_EXT_V8,   0x01d00c9f, 0x0ff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
 894   {ARM_EXT_V8,   0x01e0fc90, 0x0ff0fff0, "strlh%c\t%0-3r, [%16-19R]"},
 895   {ARM_EXT_V8,   0x01f00c9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
 896
 897   /* Virtualization Extension instructions.  */
 898   {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
 899   {ARM_EXT_VIRT, 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
 900
 901   /* Integer Divide Extension instructions.  */
 902   {ARM_EXT_ADIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
 903   {ARM_EXT_ADIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
 904
 905   /* MP Extension instructions.  */
 906   {ARM_EXT_MP, 0xf410f000, 0xfc70f000, "pldw\t%a"},
 907
 908   /* V7 instructions.  */
 909   {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"},
 910   {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
 911   {ARM_EXT_V8, 0xf57ff051, 0xfffffff3, "dmb\t%U"},
 912   {ARM_EXT_V8, 0xf57ff041, 0xfffffff3, "dsb\t%U"},
 913   {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"},
 914   {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"},
 915   {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"},
 916
 917   /* ARM V6T2 instructions.  */
 918   {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
 919   {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
 920   {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
 921   {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15R, %S"},
 922
 923   {ARM_EXT_V6T2, 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
 924   {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
 925
 926   {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
 927   {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
 928   {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
 929   {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
 930
 931   /* ARM Security extension instructions.  */
 932   {ARM_EXT_SEC, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
 933
 934   /* ARM V6K instructions.  */
 935   {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
 936   {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
 937   {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
 938   {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
 939   {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
 940   {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
 941   {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
 942
 943   /* ARM V6K NOP hints.  */
 944   {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"},
 945   {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"},
 946   {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"},
 947   {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
 948   {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
 949
 950   /* ARM V6 instructions.  */
 951   {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
 952   {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
 953   {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
 954   {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
 955   {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
 956   {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
 957   {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
 958   {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
 959   {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
 960   {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
 961   {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
 962   {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
 963   {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
 964   {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
 965   {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
 966   {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
 967   {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
 968   {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
 969   {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
 970   {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
 971   {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
 972   {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
 973   {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
 974   {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
 975   {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
 976   {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
 977   {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
 978   {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
 979   {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
 980   {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
 981   {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
 982   {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
 983   {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
 984   {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
 985   {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
 986   {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
 987   {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
 988   {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
 989   {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
 990   {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
 991   {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
 992   {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
 993   {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
 994   {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
 995   {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
 996   {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
 997   {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
 998   {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
 999   {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1000   {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1001   {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1002   {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1003   {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1004   {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1005   {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1006   {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1007   {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1008   {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1009   {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1010   {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1011   {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1012   {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1013   {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1014   {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1015   {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1016   {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1017   {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1018   {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1019   {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1020   {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1021   {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1022   {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1023   {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1024   {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1025   {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1026   {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1027   {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1028   {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1029   {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1030   {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1031   {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1032   {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1033   {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1034   {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1035   {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1036   {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1037   {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1038   {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1039   {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1040   {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1041   {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1042   {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1043   {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1044   {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1045   {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1046   {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1047   {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1048   {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1049   {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
1050   {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
1051   {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1052   {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1053   {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1054   {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1055   {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1056   {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1057   {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
1058   {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1059   {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1060   {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
1061   {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
1062   {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
1063   {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
1064   {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
1065   {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
1066   {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
1067   {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
1068   {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1069   {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
1070   {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
1071   {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
1072   {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
1073
1074   /* V5J instruction.  */
1075   {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
1076
1077   /* V5 Instructions.  */
1078   {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1079   {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"},
1080   {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
1081   {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
1082
1083   /* V5E "El Segundo" Instructions.  */
1084   {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1085   {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
1086   {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"},
1087   {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1088   {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1089   {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1090   {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
1091
1092   {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1093   {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
1094
1095   {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1096   {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1097   {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1098   {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1099
1100   {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
1101   {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
1102   {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
1103   {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
1104
1105   {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
1106   {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
1107
1108   {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
1109   {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
1110   {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
1111   {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
1112
1113   /* ARM Instructions.  */
1114   {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
1115
1116   {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
1117   {ARM_EXT_V1, 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
1118   {ARM_EXT_V1, 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
1119   {ARM_EXT_V1, 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
1120   {ARM_EXT_V1, 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
1121   {ARM_EXT_V1, 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
1122
1123   {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
1124   {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
1125   {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
1126   {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
1127
1128   {ARM_EXT_V1, 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
1129   {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
1130   {ARM_EXT_V1, 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
1131   {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
1132
1133   {ARM_EXT_V1, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
1134   {ARM_EXT_V1, 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
1135   {ARM_EXT_V1, 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
1136
1137   {ARM_EXT_V1, 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
1138   {ARM_EXT_V1, 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
1139   {ARM_EXT_V1, 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
1140
1141   {ARM_EXT_V1, 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
1142   {ARM_EXT_V1, 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
1143   {ARM_EXT_V1, 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
1144
1145   {ARM_EXT_V1, 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
1146   {ARM_EXT_V1, 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
1147   {ARM_EXT_V1, 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
1148
1149   {ARM_EXT_V1, 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
1150   {ARM_EXT_V1, 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
1151   {ARM_EXT_V1, 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
1152
1153   {ARM_EXT_V1, 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
1154   {ARM_EXT_V1, 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
1155   {ARM_EXT_V1, 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
1156
1157   {ARM_EXT_V1, 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
1158   {ARM_EXT_V1, 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
1159   {ARM_EXT_V1, 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
1160
1161   {ARM_EXT_V1, 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
1162   {ARM_EXT_V1, 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
1163   {ARM_EXT_V1, 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
1164
1165   {ARM_EXT_VIRT, 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
1166   {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
1167   {ARM_EXT_V3, 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
1168
1169   {ARM_EXT_V1, 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
1170   {ARM_EXT_V1, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
1171   {ARM_EXT_V1, 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
1172
1173   {ARM_EXT_V1, 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"},
1174   {ARM_EXT_V1, 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"},
1175   {ARM_EXT_V1, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"},
1176
1177   {ARM_EXT_V1, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
1178   {ARM_EXT_V1, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
1179   {ARM_EXT_V1, 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
1180
1181   {ARM_EXT_V1, 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
1182   {ARM_EXT_V1, 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
1183   {ARM_EXT_V1, 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
1184
1185   {ARM_EXT_V1, 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
1186   {ARM_EXT_V1, 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
1187   {ARM_EXT_V1, 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
1188
1189   {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
1190   {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
1191   {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
1192   {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
1193   {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
1194   {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
1195   {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
1196
1197   {ARM_EXT_V1, 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
1198   {ARM_EXT_V1, 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
1199   {ARM_EXT_V1, 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
1200
1201   {ARM_EXT_V1, 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
1202   {ARM_EXT_V1, 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
1203   {ARM_EXT_V1, 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
1204
1205   {ARM_EXT_V1, 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
1206   {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
1207
1208   {ARM_EXT_V1, 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
1209
1210   {ARM_EXT_V1, 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
1211   {ARM_EXT_V1, 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
1212
1213   {ARM_EXT_V1, 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1214   {ARM_EXT_V1, 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1215   {ARM_EXT_V1, 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1216   {ARM_EXT_V1, 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1217   {ARM_EXT_V1, 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1218   {ARM_EXT_V1, 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1219   {ARM_EXT_V1, 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1220   {ARM_EXT_V1, 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1221   {ARM_EXT_V1, 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1222   {ARM_EXT_V1, 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1223   {ARM_EXT_V1, 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1224   {ARM_EXT_V1, 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1225   {ARM_EXT_V1, 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1226   {ARM_EXT_V1, 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1227   {ARM_EXT_V1, 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1228   {ARM_EXT_V1, 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1229   {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"},
1230   {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
1231   {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
1232
1233   {ARM_EXT_V1, 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1234   {ARM_EXT_V1, 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1235   {ARM_EXT_V1, 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1236   {ARM_EXT_V1, 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1237   {ARM_EXT_V1, 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1238   {ARM_EXT_V1, 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1239   {ARM_EXT_V1, 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1240   {ARM_EXT_V1, 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1241   {ARM_EXT_V1, 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1242   {ARM_EXT_V1, 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1243   {ARM_EXT_V1, 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1244   {ARM_EXT_V1, 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1245   {ARM_EXT_V1, 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1246   {ARM_EXT_V1, 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1247   {ARM_EXT_V1, 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1248   {ARM_EXT_V1, 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1249   {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
1250   {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
1251   {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
1252
1253   {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
1254   {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
1255
1256   /* The rest.  */
1257   {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
1258   {0, 0x00000000, 0x00000000, 0}
1259 };
1260
1261 /* print_insn_thumb16 recognizes the following format control codes:
1262
1263    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
1264    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
1265    %<bitfield>I         print bitfield as a signed decimal
1266                                 (top bit of range being the sign bit)
1267    %N                   print Thumb register mask (with LR)
1268    %O                   print Thumb register mask (with PC)
1269    %M                   print Thumb register mask
1270    %b                   print CZB's 6-bit unsigned branch destination
1271    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
1272    %c                   print the condition code
1273    %C                   print the condition code, or "s" if not conditional
1274    %x                   print warning if conditional an not at end of IT block"
1275    %X                   print "\t; unpredictable <IT:code>" if conditional
1276    %I                   print IT instruction suffix and operands
1277    %W                   print Thumb Writeback indicator for LDMIA
1278    %<bitfield>r         print bitfield as an ARM register
1279    %<bitfield>d         print bitfield as a decimal
1280    %<bitfield>H         print (bitfield * 2) as a decimal
1281    %<bitfield>W         print (bitfield * 4) as a decimal
1282    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
1283    %<bitfield>B         print Thumb branch destination (signed displacement)
1284    %<bitfield>c         print bitfield as a condition code
1285    %<bitnum>'c          print specified char iff bit is one
1286    %<bitnum>?ab         print a if bit is one else print b.  */
1287
1288 static const struct opcode16 thumb_opcodes[] =
1289 {
1290   /* Thumb instructions.  */
1291
1292   /* ARM V8 instructions.  */
1293   {ARM_EXT_V8,  0xbf50, 0xffff, "sevl%c"},
1294   {ARM_EXT_V8,  0xba80, 0xffc0, "hlt\t%0-5x"},
1295
1296   /* ARM V6K no-argument instructions.  */
1297   {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"},
1298   {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"},
1299   {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"},
1300   {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"},
1301   {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"},
1302   {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
1303
1304   /* ARM V6T2 instructions.  */
1305   {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
1306   {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
1307   {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"},
1308
1309   /* ARM V6.  */
1310   {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
1311   {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
1312   {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
1313   {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
1314   {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
1315   {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
1316   {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"},
1317   {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
1318   {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
1319   {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
1320   {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
1321
1322   /* ARM V5 ISA extends Thumb.  */
1323   {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
1324   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
1325   {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"},      /* note: 4 bit register number.  */
1326   /* ARM V4T ISA (Thumb v1).  */
1327   {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
1328   /* Format 4.  */
1329   {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
1330   {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
1331   {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
1332   {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
1333   {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
1334   {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
1335   {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
1336   {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
1337   {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
1338   {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
1339   {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
1340   {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
1341   {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
1342   {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
1343   {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
1344   {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
1345   /* format 13 */
1346   {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
1347   {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
1348   /* format 5 */
1349   {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"},
1350   {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"},
1351   {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"},
1352   {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"},
1353   /* format 14 */
1354   {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"},
1355   {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"},
1356   /* format 2 */
1357   {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
1358   {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
1359   {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
1360   {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
1361   /* format 8 */
1362   {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
1363   {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
1364   {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
1365   /* format 7 */
1366   {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1367   {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1368   /* format 1 */
1369   {ARM_EXT_V4T, 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
1370   {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
1371   {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
1372   {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
1373   /* format 3 */
1374   {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
1375   {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
1376   {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
1377   {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
1378   /* format 6 */
1379   {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
1380   /* format 9 */
1381   {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
1382   {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
1383   {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
1384   {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
1385   /* format 10 */
1386   {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
1387   {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
1388   /* format 11 */
1389   {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
1390   {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
1391   /* format 12 */
1392   {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
1393   {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
1394   /* format 15 */
1395   {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
1396   {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
1397   /* format 17 */
1398   {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
1399   /* format 16 */
1400   {ARM_EXT_V4T, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
1401   {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
1402   /* format 18 */
1403   {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
1404
1405   /* The E800 .. FFFF range is unconditionally redirected to the
1406      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
1407      are processed via that table.  Thus, we can never encounter a
1408      bare "second half of BL/BLX(1)" instruction here.  */
1409   {ARM_EXT_V1,  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
1410   {0, 0, 0, 0}
1411 };
1412
1413 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
1414    We adopt the convention that hw1 is the high 16 bits of .value and
1415    .mask, hw2 the low 16 bits.
1416
1417    print_insn_thumb32 recognizes the following format control codes:
1418
1419        %%               %
1420
1421        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
1422        %M               print a modified 12-bit immediate (same location)
1423        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
1424        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
1425        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
1426        %S               print a possibly-shifted Rm
1427
1428        %L               print address for a ldrd/strd instruction
1429        %a               print the address of a plain load/store
1430        %w               print the width and signedness of a core load/store
1431        %m               print register mask for ldm/stm
1432
1433        %E               print the lsb and width fields of a bfc/bfi instruction
1434        %F               print the lsb and width fields of a sbfx/ubfx instruction
1435        %b               print a conditional branch offset
1436        %B               print an unconditional branch offset
1437        %s               print the shift field of an SSAT instruction
1438        %R               print the rotation field of an SXT instruction
1439        %U               print barrier type.
1440        %P               print address for pli instruction.
1441        %c               print the condition code
1442        %x               print warning if conditional an not at end of IT block"
1443        %X               print "\t; unpredictable <IT:code>" if conditional
1444
1445        %<bitfield>d     print bitfield in decimal
1446        %<bitfield>W     print bitfield*4 in decimal
1447        %<bitfield>r     print bitfield as an ARM register
1448        %<bitfield>R     as %<>r bit r15 is UNPREDICTABLE
1449        %<bitfield>c     print bitfield as a condition code
1450
1451        %<bitfield>'c    print specified char iff bitfield is all ones
1452        %<bitfield>`c    print specified char iff bitfield is all zeroes
1453        %<bitfield>?ab... select from array of values in big endian order
1454
1455    With one exception at the bottom (done because BL and BLX(1) need
1456    to come dead last), this table was machine-sorted first in
1457    decreasing order of number of bits set in the mask, then in
1458    increasing numeric order of mask, then in increasing numeric order
1459    of opcode.  This order is not the clearest for a human reader, but
1460    is guaranteed never to catch a special-case bit pattern with a more
1461    general mask, which is important, because this instruction encoding
1462    makes heavy use of special-case bit patterns.  */
1463 static const struct opcode32 thumb32_opcodes[] =
1464 {
1465   /* V8 instructions.  */
1466   {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
1467   {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
1468   {ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "strlb%c\t%12-15r, [%16-19R]"},
1469   {ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "strlh%c\t%12-15r, [%16-19R]"},
1470   {ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "strl%c\t%12-15r, [%16-19R]"},
1471   {ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "strlexb%c\t%0-3r, %12-15r, [%16-19R]"},
1472   {ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "strlexh%c\t%0-3r, %12-15r, [%16-19R]"},
1473   {ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "strlex%c\t%0-3r, %12-15r, [%16-19R]"},
1474   {ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "strlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
1475   {ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
1476   {ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldrah%c\t%12-15r, [%16-19R]"},
1477   {ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "ldra%c\t%12-15r, [%16-19R]"},
1478   {ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
1479   {ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
1480   {ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
1481   {ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldraexd%c\t%12-15r, %8-11r, [%16-19R]"},
1482
1483   /* V7 instructions.  */
1484   {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
1485   {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
1486   {ARM_EXT_V8, 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
1487   {ARM_EXT_V8, 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
1488   {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
1489   {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
1490   {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
1491   {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
1492   {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
1493
1494   /* Virtualization Extension instructions.  */
1495   {ARM_EXT_VIRT, 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
1496   /* We skip ERET as that is SUBS pc, lr, #0.  */
1497
1498   /* MP Extension instructions.  */
1499   {ARM_EXT_MP,   0xf830f000, 0xff70f000, "pldw%c\t%a"},
1500
1501   /* Security extension instructions.  */
1502   {ARM_EXT_SEC,  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
1503
1504   /* Instructions defined in the basic V6T2 set.  */
1505   {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
1506   {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
1507   {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
1508   {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
1509   {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "sev%c.w"},
1510   {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
1511
1512   {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},
1513   {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
1514   {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
1515   {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
1516   {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
1517   {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
1518   {ARM_EXT_V6T2, 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
1519   {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
1520   {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
1521   {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
1522   {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
1523   {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
1524   {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
1525   {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
1526   {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
1527   {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
1528   {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
1529   {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
1530   {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
1531   {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
1532   {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
1533   {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
1534   {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
1535   {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
1536   {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
1537   {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
1538   {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
1539   {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
1540   {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
1541   {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
1542   {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
1543   {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
1544   {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
1545   {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
1546   {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
1547   {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
1548   {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
1549   {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
1550   {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
1551   {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
1552   {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
1553   {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
1554   {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
1555   {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
1556   {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
1557   {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
1558   {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
1559   {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
1560   {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
1561   {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
1562   {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
1563   {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
1564   {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
1565   {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
1566   {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
1567   {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
1568   {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
1569   {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
1570   {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
1571   {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
1572   {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
1573   {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
1574   {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
1575   {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
1576   {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
1577   {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
1578   {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
1579   {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
1580   {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
1581   {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
1582   {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
1583   {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
1584   {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
1585   {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
1586   {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1587   {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1588   {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1589   {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
1590   {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
1591   {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
1592   {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
1593   {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
1594   {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1595   {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
1596   {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
1597   {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1598   {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1599   {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1600   {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1601   {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1602   {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1603   {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1604   {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
1605   {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
1606   {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
1607   {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
1608   {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
1609   {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
1610   {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
1611   {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
1612   {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
1613   {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
1614   {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
1615   {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
1616   {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1617   {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1618   {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1619   {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1620   {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1621   {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1622   {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1623   {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1624   {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
1625   {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
1626   {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
1627   {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"},
1628   {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1629   {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1630   {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1631   {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1632   {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1633   {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1634   {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1635   {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
1636   {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
1637   {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
1638   {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
1639   {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
1640   {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1641   {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1642   {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
1643   {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
1644   {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
1645   {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
1646   {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
1647   {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
1648   {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
1649   {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
1650   {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
1651   {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
1652   {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
1653   {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
1654   {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
1655   {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
1656   {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
1657   {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
1658   {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
1659   {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
1660   {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
1661   {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
1662   {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
1663   {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
1664   {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
1665   {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
1666   {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
1667   {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
1668   {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
1669   {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
1670   {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
1671   {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
1672   {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
1673   {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
1674   {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
1675   {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
1676   {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
1677   {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
1678   {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
1679   {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
1680   {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
1681   {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
1682   {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
1683
1684   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
1685   {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
1686   {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
1687   {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
1688   {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
1689
1690   /* These have been 32-bit since the invention of Thumb.  */
1691   {ARM_EXT_V4T,  0xf000c000, 0xf800d001, "blx%c\t%B%x"},
1692   {ARM_EXT_V4T,  0xf000d000, 0xf800d000, "bl%c\t%B%x"},
1693
1694   /* Fallback.  */
1695   {ARM_EXT_V1,   0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
1696   {0, 0, 0, 0}
1697 };
1698
1699 static const char *const arm_conditional[] =
1700 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
1701  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
1702
1703 static const char *const arm_fp_const[] =
1704 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
1705
1706 static const char *const arm_shift[] =
1707 {"lsl", "lsr", "asr", "ror"};
1708
1709 typedef struct
1710 {
1711   const char *name;
1712   const char *description;
1713   const char *reg_names[16];
1714 }
1715 arm_regname;
1716
1717 static const arm_regname regnames[] =
1718 {
1719   { "raw" , "Select raw register names",
1720     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
1721   { "gcc",  "Select register names used by GCC",
1722     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
1723   { "std",  "Select register names used in ARM's ISA documentation",
1724     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
1725   { "apcs", "Select register names used in the APCS",
1726     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
1727   { "atpcs", "Select register names used in the ATPCS",
1728     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
1729   { "special-atpcs", "Select special register names used in the ATPCS",
1730     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }},
1731 };
1732
1733 static const char *const iwmmxt_wwnames[] =
1734 {"b", "h", "w", "d"};
1735
1736 static const char *const iwmmxt_wwssnames[] =
1737 {"b", "bus", "bc", "bss",
1738  "h", "hus", "hc", "hss",
1739  "w", "wus", "wc", "wss",
1740  "d", "dus", "dc", "dss"
1741 };
1742
1743 static const char *const iwmmxt_regnames[] =
1744 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
1745   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
1746 };
1747
1748 static const char *const iwmmxt_cregnames[] =
1749 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
1750   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
1751 };
1752
1753 /* Default to GCC register name set.  */
1754 static unsigned int regname_selected = 1;
1755
1756 #define NUM_ARM_REGNAMES  NUM_ELEM (regnames)
1757 #define arm_regnames      regnames[regname_selected].reg_names
1758
1759 static bfd_boolean force_thumb = FALSE;
1760
1761 /* Current IT instruction state.  This contains the same state as the IT
1762    bits in the CPSR.  */
1763 static unsigned int ifthen_state;
1764 /* IT state for the next instruction.  */
1765 static unsigned int ifthen_next_state;
1766 /* The address of the insn for which the IT state is valid.  */
1767 static bfd_vma ifthen_address;
1768 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
1769 /* Indicates that the current Conditional state is unconditional or outside
1770    an IT block.  */
1771 #define COND_UNCOND 16
1772
1773 \f
1774 /* Functions.  */
1775 int
1776 get_arm_regname_num_options (void)
1777 {
1778   return NUM_ARM_REGNAMES;
1779 }
1780
1781 int
1782 set_arm_regname_option (int option)
1783 {
1784   int old = regname_selected;
1785   regname_selected = option;
1786   return old;
1787 }
1788
1789 int
1790 get_arm_regnames (int option,
1791                   const char **setname,
1792                   const char **setdescription,
1793                   const char *const **register_names)
1794 {
1795   *setname = regnames[option].name;
1796   *setdescription = regnames[option].description;
1797   *register_names = regnames[option].reg_names;
1798   return 16;
1799 }
1800
1801 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
1802    Returns pointer to following character of the format string and
1803    fills in *VALUEP and *WIDTHP with the extracted value and number of
1804    bits extracted.  WIDTHP can be NULL.  */
1805
1806 static const char *
1807 arm_decode_bitfield (const char *ptr,
1808                      unsigned long insn,
1809                      unsigned long *valuep,
1810                      int *widthp)
1811 {
1812   unsigned long value = 0;
1813   int width = 0;
1814
1815   do
1816     {
1817       int start, end;
1818       int bits;
1819
1820       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
1821         start = start * 10 + *ptr - '0';
1822       if (*ptr == '-')
1823         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
1824           end = end * 10 + *ptr - '0';
1825       else
1826         end = start;
1827       bits = end - start;
1828       if (bits < 0)
1829         abort ();
1830       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
1831       width += bits + 1;
1832     }
1833   while (*ptr++ == ',');
1834   *valuep = value;
1835   if (widthp)
1836     *widthp = width;
1837   return ptr - 1;
1838 }
1839
1840 static void
1841 arm_decode_shift (long given, fprintf_ftype func, void *stream,
1842                   bfd_boolean print_shift)
1843 {
1844   func (stream, "%s", arm_regnames[given & 0xf]);
1845
1846   if ((given & 0xff0) != 0)
1847     {
1848       if ((given & 0x10) == 0)
1849         {
1850           int amount = (given & 0xf80) >> 7;
1851           int shift = (given & 0x60) >> 5;
1852
1853           if (amount == 0)
1854             {
1855               if (shift == 3)
1856                 {
1857                   func (stream, ", rrx");
1858                   return;
1859                 }
1860
1861               amount = 32;
1862             }
1863
1864           if (print_shift)
1865             func (stream, ", %s #%d", arm_shift[shift], amount);
1866           else
1867             func (stream, ", #%d", amount);
1868         }
1869       else if ((given & 0x80) == 0x80)
1870         func (stream, "\t; <illegal shifter operand>");
1871       else if (print_shift)
1872         func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
1873               arm_regnames[(given & 0xf00) >> 8]);
1874       else
1875         func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
1876     }
1877 }
1878
1879 #define W_BIT 21
1880 #define I_BIT 22
1881 #define U_BIT 23
1882 #define P_BIT 24
1883
1884 #define WRITEBACK_BIT_SET   (given & (1 << W_BIT))
1885 #define IMMEDIATE_BIT_SET   (given & (1 << I_BIT))
1886 #define NEGATIVE_BIT_SET   ((given & (1 << U_BIT)) == 0)
1887 #define PRE_BIT_SET         (given & (1 << P_BIT))
1888
1889 /* Print one coprocessor instruction on INFO->STREAM.
1890    Return TRUE if the instuction matched, FALSE if this is not a
1891    recognised coprocessor instruction.  */
1892
1893 static bfd_boolean
1894 print_insn_coprocessor (bfd_vma pc,
1895                         struct disassemble_info *info,
1896                         long given,
1897                         bfd_boolean thumb)
1898 {
1899   const struct opcode32 *insn;
1900   void *stream = info->stream;
1901   fprintf_ftype func = info->fprintf_func;
1902   unsigned long mask;
1903   unsigned long value = 0;
1904   struct arm_private_data *private_data = info->private_data;
1905   unsigned long allowed_arches = private_data->features.coproc;
1906   int cond;
1907
1908   for (insn = coprocessor_opcodes; insn->assembler; insn++)
1909     {
1910       unsigned long u_reg = 16;
1911       bfd_boolean is_unpredictable = FALSE;
1912       signed long value_in_comment = 0;
1913       const char *c;
1914
1915       if (insn->arch == 0)
1916         switch (insn->value)
1917           {
1918           case SENTINEL_IWMMXT_START:
1919             if (info->mach != bfd_mach_arm_XScale
1920                 && info->mach != bfd_mach_arm_iWMMXt
1921                 && info->mach != bfd_mach_arm_iWMMXt2)
1922               do
1923                 insn++;
1924               while (insn->arch != 0 && insn->value != SENTINEL_IWMMXT_END);
1925             continue;
1926
1927           case SENTINEL_IWMMXT_END:
1928             continue;
1929
1930           case SENTINEL_GENERIC_START:
1931             allowed_arches = private_data->features.core;
1932             continue;
1933
1934           default:
1935             abort ();
1936           }
1937
1938       mask = insn->mask;
1939       value = insn->value;
1940       if (thumb)
1941         {
1942           /* The high 4 bits are 0xe for Arm conditional instructions, and
1943              0xe for arm unconditional instructions.  The rest of the
1944              encoding is the same.  */
1945           mask |= 0xf0000000;
1946           value |= 0xe0000000;
1947           if (ifthen_state)
1948             cond = IFTHEN_COND;
1949           else
1950             cond = COND_UNCOND;
1951         }
1952       else
1953         {
1954           /* Only match unconditional instuctions against unconditional
1955              patterns.  */
1956           if ((given & 0xf0000000) == 0xf0000000)
1957             {
1958               mask |= 0xf0000000;
1959               cond = COND_UNCOND;
1960             }
1961           else
1962             {
1963               cond = (given >> 28) & 0xf;
1964               if (cond == 0xe)
1965                 cond = COND_UNCOND;
1966             }
1967         }
1968
1969       if ((given & mask) != value)
1970         continue;
1971
1972       if ((insn->arch & allowed_arches) == 0)
1973         continue;
1974
1975       for (c = insn->assembler; *c; c++)
1976         {
1977           if (*c == '%')
1978             {
1979               switch (*++c)
1980                 {
1981                 case '%':
1982                   func (stream, "%%");
1983                   break;
1984
1985                 case 'A':
1986                   {
1987                     int rn = (given >> 16) & 0xf;
1988                     bfd_vma offset = given & 0xff;
1989
1990                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
1991
1992                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
1993                       {
1994                         /* Not unindexed.  The offset is scaled.  */
1995                         offset = offset * 4;
1996                         if (NEGATIVE_BIT_SET)
1997                           offset = - offset;
1998                         if (rn != 15)
1999                           value_in_comment = offset;
2000                       }
2001
2002                     if (PRE_BIT_SET)
2003                       {
2004                         if (offset)
2005                           func (stream, ", #%d]%s",
2006                                 (int) offset,
2007                                 WRITEBACK_BIT_SET ? "!" : "");
2008                         else if (NEGATIVE_BIT_SET)
2009                           func (stream, ", #-0]");
2010                         else
2011                           func (stream, "]");
2012                       }
2013                     else
2014                       {
2015                         func (stream, "]");
2016
2017                         if (WRITEBACK_BIT_SET)
2018                           {
2019                             if (offset)
2020                               func (stream, ", #%d", (int) offset);
2021                             else if (NEGATIVE_BIT_SET)
2022                               func (stream, ", #-0");
2023                           }
2024                         else
2025                           {
2026                             func (stream, ", {%s%d}",
2027                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
2028                                   (int) offset);
2029                             value_in_comment = offset;
2030                           }
2031                       }
2032                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
2033                       {
2034                         func (stream, "\t; ");
2035                         /* For unaligned PCs, apply off-by-alignment
2036                            correction.  */
2037                         info->print_address_func (offset + pc
2038                                                   + info->bytes_per_chunk * 2
2039                                                   - (pc & 3),
2040                                                   info);
2041                       }
2042                   }
2043                   break;
2044
2045                 case 'B':
2046                   {
2047                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
2048                     int offset = (given >> 1) & 0x3f;
2049
2050                     if (offset == 1)
2051                       func (stream, "{d%d}", regno);
2052                     else if (regno + offset > 32)
2053                       func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
2054                     else
2055                       func (stream, "{d%d-d%d}", regno, regno + offset - 1);
2056                   }
2057                   break;
2058
2059                 case 'u':
2060                   if (cond != COND_UNCOND)
2061                     is_unpredictable = TRUE;
2062
2063                   /* Fall through.  */
2064                 case 'c':
2065                   func (stream, "%s", arm_conditional[cond]);
2066                   break;
2067
2068                 case 'I':
2069                   /* Print a Cirrus/DSP shift immediate.  */
2070                   /* Immediates are 7bit signed ints with bits 0..3 in
2071                      bits 0..3 of opcode and bits 4..6 in bits 5..7
2072                      of opcode.  */
2073                   {
2074                     int imm;
2075
2076                     imm = (given & 0xf) | ((given & 0xe0) >> 1);
2077
2078                     /* Is ``imm'' a negative number?  */
2079                     if (imm & 0x40)
2080                       imm |= (-1 << 7);
2081
2082                     func (stream, "%d", imm);
2083                   }
2084
2085                   break;
2086
2087                 case 'F':
2088                   switch (given & 0x00408000)
2089                     {
2090                     case 0:
2091                       func (stream, "4");
2092                       break;
2093                     case 0x8000:
2094                       func (stream, "1");
2095                       break;
2096                     case 0x00400000:
2097                       func (stream, "2");
2098                       break;
2099                     default:
2100                       func (stream, "3");
2101                     }
2102                   break;
2103
2104                 case 'P':
2105                   switch (given & 0x00080080)
2106                     {
2107                     case 0:
2108                       func (stream, "s");
2109                       break;
2110                     case 0x80:
2111                       func (stream, "d");
2112                       break;
2113                     case 0x00080000:
2114                       func (stream, "e");
2115                       break;
2116                     default:
2117                       func (stream, _("<illegal precision>"));
2118                       break;
2119                     }
2120                   break;
2121
2122                 case 'Q':
2123                   switch (given & 0x00408000)
2124                     {
2125                     case 0:
2126                       func (stream, "s");
2127                       break;
2128                     case 0x8000:
2129                       func (stream, "d");
2130                       break;
2131                     case 0x00400000:
2132                       func (stream, "e");
2133                       break;
2134                     default:
2135                       func (stream, "p");
2136                       break;
2137                     }
2138                   break;
2139
2140                 case 'R':
2141                   switch (given & 0x60)
2142                     {
2143                     case 0:
2144                       break;
2145                     case 0x20:
2146                       func (stream, "p");
2147                       break;
2148                     case 0x40:
2149                       func (stream, "m");
2150                       break;
2151                     default:
2152                       func (stream, "z");
2153                       break;
2154                     }
2155                   break;
2156
2157                 case '0': case '1': case '2': case '3': case '4':
2158                 case '5': case '6': case '7': case '8': case '9':
2159                   {
2160                     int width;
2161
2162                     c = arm_decode_bitfield (c, given, &value, &width);
2163
2164                     switch (*c)
2165                       {
2166                       case 'R':
2167                         if (value == 15)
2168                           is_unpredictable = TRUE;
2169                         /* Fall through.  */
2170                       case 'r':
2171                         if (c[1] == 'u')
2172                           {
2173                             /* Eat the 'u' character.  */
2174                             ++ c;
2175
2176                             if (u_reg == value)
2177                               is_unpredictable = TRUE;
2178                             u_reg = value;
2179                           }
2180                         func (stream, "%s", arm_regnames[value]);
2181                         break;
2182                       case 'D':
2183                         func (stream, "d%ld", value);
2184                         break;
2185                       case 'Q':
2186                         if (value & 1)
2187                           func (stream, "<illegal reg q%ld.5>", value >> 1);
2188                         else
2189                           func (stream, "q%ld", value >> 1);
2190                         break;
2191                       case 'd':
2192                         func (stream, "%ld", value);
2193                         value_in_comment = value;
2194                         break;
2195                       case 'k':
2196                         {
2197                           int from = (given & (1 << 7)) ? 32 : 16;
2198                           func (stream, "%ld", from - value);
2199                         }
2200                         break;
2201
2202                       case 'f':
2203                         if (value > 7)
2204                           func (stream, "#%s", arm_fp_const[value & 7]);
2205                         else
2206                           func (stream, "f%ld", value);
2207                         break;
2208
2209                       case 'w':
2210                         if (width == 2)
2211                           func (stream, "%s", iwmmxt_wwnames[value]);
2212                         else
2213                           func (stream, "%s", iwmmxt_wwssnames[value]);
2214                         break;
2215
2216                       case 'g':
2217                         func (stream, "%s", iwmmxt_regnames[value]);
2218                         break;
2219                       case 'G':
2220                         func (stream, "%s", iwmmxt_cregnames[value]);
2221                         break;
2222
2223                       case 'x':
2224                         func (stream, "0x%lx", (value & 0xffffffffUL));
2225                         break;
2226
2227                       case 'c':
2228                         switch (value)
2229                           {
2230                           case 0:
2231                             func (stream, "eq");
2232                             break;
2233
2234                           case 1:
2235                             func (stream, "vs");
2236                             break;
2237
2238                           case 2:
2239                             func (stream, "ge");
2240                             break;
2241
2242                           case 3:
2243                             func (stream, "gt");
2244                             break;
2245
2246                           default:
2247                             func (stream, "??");
2248                             break;
2249                           }
2250                         break;
2251
2252                       case '`':
2253                         c++;
2254                         if (value == 0)
2255                           func (stream, "%c", *c);
2256                         break;
2257                       case '\'':
2258                         c++;
2259                         if (value == ((1ul << width) - 1))
2260                           func (stream, "%c", *c);
2261                         break;
2262                       case '?':
2263                         func (stream, "%c", c[(1 << width) - (int) value]);
2264                         c += 1 << width;
2265                         break;
2266                       default:
2267                         abort ();
2268                       }
2269                     break;
2270
2271                   case 'y':
2272                   case 'z':
2273                     {
2274                       int single = *c++ == 'y';
2275                       int regno;
2276
2277                       switch (*c)
2278                         {
2279                         case '4': /* Sm pair */
2280                         case '0': /* Sm, Dm */
2281                           regno = given & 0x0000000f;
2282                           if (single)
2283                             {
2284                               regno <<= 1;
2285                               regno += (given >> 5) & 1;
2286                             }
2287                           else
2288                             regno += ((given >> 5) & 1) << 4;
2289                           break;
2290
2291                         case '1': /* Sd, Dd */
2292                           regno = (given >> 12) & 0x0000000f;
2293                           if (single)
2294                             {
2295                               regno <<= 1;
2296                               regno += (given >> 22) & 1;
2297                             }
2298                           else
2299                             regno += ((given >> 22) & 1) << 4;
2300                           break;
2301
2302                         case '2': /* Sn, Dn */
2303                           regno = (given >> 16) & 0x0000000f;
2304                           if (single)
2305                             {
2306                               regno <<= 1;
2307                               regno += (given >> 7) & 1;
2308                             }
2309                           else
2310                             regno += ((given >> 7) & 1) << 4;
2311                           break;
2312
2313                         case '3': /* List */
2314                           func (stream, "{");
2315                           regno = (given >> 12) & 0x0000000f;
2316                           if (single)
2317                             {
2318                               regno <<= 1;
2319                               regno += (given >> 22) & 1;
2320                             }
2321                           else
2322                             regno += ((given >> 22) & 1) << 4;
2323                           break;
2324
2325                         default:
2326                           abort ();
2327                         }
2328
2329                       func (stream, "%c%d", single ? 's' : 'd', regno);
2330
2331                       if (*c == '3')
2332                         {
2333                           int count = given & 0xff;
2334
2335                           if (single == 0)
2336                             count >>= 1;
2337
2338                           if (--count)
2339                             {
2340                               func (stream, "-%c%d",
2341                                     single ? 's' : 'd',
2342                                     regno + count);
2343                             }
2344
2345                           func (stream, "}");
2346                         }
2347                       else if (*c == '4')
2348                         func (stream, ", %c%d", single ? 's' : 'd',
2349                               regno + 1);
2350                     }
2351                     break;
2352
2353                   case 'L':
2354                     switch (given & 0x00400100)
2355                       {
2356                       case 0x00000000: func (stream, "b"); break;
2357                       case 0x00400000: func (stream, "h"); break;
2358                       case 0x00000100: func (stream, "w"); break;
2359                       case 0x00400100: func (stream, "d"); break;
2360                       default:
2361                         break;
2362                       }
2363                     break;
2364
2365                   case 'Z':
2366                     {
2367                       /* given (20, 23) | given (0, 3) */
2368                       value = ((given >> 16) & 0xf0) | (given & 0xf);
2369                       func (stream, "%d", (int) value);
2370                     }
2371                     break;
2372
2373                   case 'l':
2374                     /* This is like the 'A' operator, except that if
2375                        the width field "M" is zero, then the offset is
2376                        *not* multiplied by four.  */
2377                     {
2378                       int offset = given & 0xff;
2379                       int multiplier = (given & 0x00000100) ? 4 : 1;
2380
2381                       func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
2382
2383                       if (multiplier > 1)
2384                         {
2385                           value_in_comment = offset * multiplier;
2386                           if (NEGATIVE_BIT_SET)
2387                             value_in_comment = - value_in_comment;
2388                         }
2389
2390                       if (offset)
2391                         {
2392                           if (PRE_BIT_SET)
2393                             func (stream, ", #%s%d]%s",
2394                                   NEGATIVE_BIT_SET ? "-" : "",
2395                                   offset * multiplier,
2396                                   WRITEBACK_BIT_SET ? "!" : "");
2397                           else
2398                             func (stream, "], #%s%d",
2399                                   NEGATIVE_BIT_SET ? "-" : "",
2400                                   offset * multiplier);
2401                         }
2402                       else
2403                         func (stream, "]");
2404                     }
2405                     break;
2406
2407                   case 'r':
2408                     {
2409                       int imm4 = (given >> 4) & 0xf;
2410                       int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
2411                       int ubit = ! NEGATIVE_BIT_SET;
2412                       const char *rm = arm_regnames [given & 0xf];
2413                       const char *rn = arm_regnames [(given >> 16) & 0xf];
2414
2415                       switch (puw_bits)
2416                         {
2417                         case 1:
2418                         case 3:
2419                           func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
2420                           if (imm4)
2421                             func (stream, ", lsl #%d", imm4);
2422                           break;
2423
2424                         case 4:
2425                         case 5:
2426                         case 6:
2427                         case 7:
2428                           func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
2429                           if (imm4 > 0)
2430                             func (stream, ", lsl #%d", imm4);
2431                           func (stream, "]");
2432                           if (puw_bits == 5 || puw_bits == 7)
2433                             func (stream, "!");
2434                           break;
2435
2436                         default:
2437                           func (stream, "INVALID");
2438                         }
2439                     }
2440                     break;
2441
2442                   case 'i':
2443                     {
2444                       long imm5;
2445                       imm5 = ((given & 0x100) >> 4) | (given & 0xf);
2446                       func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
2447                     }
2448                     break;
2449
2450                   default:
2451                     abort ();
2452                   }
2453                 }
2454             }
2455           else
2456             func (stream, "%c", *c);
2457         }
2458
2459       if (value_in_comment > 32 || value_in_comment < -16)
2460         func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
2461
2462       if (is_unpredictable)
2463         func (stream, UNPREDICTABLE_INSTRUCTION);
2464
2465       return TRUE;
2466     }
2467   return FALSE;
2468 }
2469
2470 /* Decodes and prints ARM addressing modes.  Returns the offset
2471    used in the address, if any, if it is worthwhile printing the
2472    offset as a hexadecimal value in a comment at the end of the
2473    line of disassembly.  */
2474
2475 static signed long
2476 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
2477 {
2478   void *stream = info->stream;
2479   fprintf_ftype func = info->fprintf_func;
2480   bfd_vma offset = 0;
2481
2482   if (((given & 0x000f0000) == 0x000f0000)
2483       && ((given & 0x02000000) == 0))
2484     {
2485       offset = given & 0xfff;
2486
2487       func (stream, "[pc");
2488
2489       if (PRE_BIT_SET)
2490         {
2491           /* Pre-indexed.  Elide offset of positive zero when
2492              non-writeback.  */
2493           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
2494             func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
2495
2496           if (NEGATIVE_BIT_SET)
2497             offset = -offset;
2498
2499           offset += pc + 8;
2500
2501           /* Cope with the possibility of write-back
2502              being used.  Probably a very dangerous thing
2503              for the programmer to do, but who are we to
2504              argue ?  */
2505           func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
2506         }
2507       else  /* Post indexed.  */
2508         {
2509           func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
2510
2511           /* Ie ignore the offset.  */
2512           offset = pc + 8;
2513         }
2514
2515       func (stream, "\t; ");
2516       info->print_address_func (offset, info);
2517       offset = 0;
2518     }
2519   else
2520     {
2521       func (stream, "[%s",
2522             arm_regnames[(given >> 16) & 0xf]);
2523
2524       if (PRE_BIT_SET)
2525         {
2526           if ((given & 0x02000000) == 0)
2527             {
2528               /* Elide offset of positive zero when non-writeback.  */
2529               offset = given & 0xfff;
2530               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
2531                 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
2532             }
2533           else
2534             {
2535               func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
2536               arm_decode_shift (given, func, stream, TRUE);
2537             }
2538
2539           func (stream, "]%s",
2540                 WRITEBACK_BIT_SET ? "!" : "");
2541         }
2542       else
2543         {
2544           if ((given & 0x02000000) == 0)
2545             {
2546               /* Always show offset.  */
2547               offset = given & 0xfff;
2548               func (stream, "], #%s%d",
2549                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
2550             }
2551           else
2552             {
2553               func (stream, "], %s",
2554                     NEGATIVE_BIT_SET ? "-" : "");
2555               arm_decode_shift (given, func, stream, TRUE);
2556             }
2557         }
2558     }
2559
2560   return (signed long) offset;
2561 }
2562
2563 /* Print one neon instruction on INFO->STREAM.
2564    Return TRUE if the instuction matched, FALSE if this is not a
2565    recognised neon instruction.  */
2566
2567 static bfd_boolean
2568 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
2569 {
2570   const struct opcode32 *insn;
2571   void *stream = info->stream;
2572   fprintf_ftype func = info->fprintf_func;
2573
2574   if (thumb)
2575     {
2576       if ((given & 0xef000000) == 0xef000000)
2577         {
2578           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
2579           unsigned long bit28 = given & (1 << 28);
2580
2581           given &= 0x00ffffff;
2582           if (bit28)
2583             given |= 0xf3000000;
2584           else
2585             given |= 0xf2000000;
2586         }
2587       else if ((given & 0xff000000) == 0xf9000000)
2588         given ^= 0xf9000000 ^ 0xf4000000;
2589       else
2590         return FALSE;
2591     }
2592
2593   for (insn = neon_opcodes; insn->assembler; insn++)
2594     {
2595       if ((given & insn->mask) == insn->value)
2596         {
2597           signed long value_in_comment = 0;
2598           bfd_boolean is_unpredictable = FALSE;
2599           const char *c;
2600
2601           for (c = insn->assembler; *c; c++)
2602             {
2603               if (*c == '%')
2604                 {
2605                   switch (*++c)
2606                     {
2607                     case '%':
2608                       func (stream, "%%");
2609                       break;
2610
2611                     case 'u':
2612                       if (thumb && ifthen_state)
2613                         is_unpredictable = TRUE;
2614
2615                       /* Fall through.  */
2616                     case 'c':
2617                       if (thumb && ifthen_state)
2618                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
2619                       break;
2620
2621                     case 'A':
2622                       {
2623                         static const unsigned char enc[16] =
2624                         {
2625                           0x4, 0x14, /* st4 0,1 */
2626                           0x4, /* st1 2 */
2627                           0x4, /* st2 3 */
2628                           0x3, /* st3 4 */
2629                           0x13, /* st3 5 */
2630                           0x3, /* st1 6 */
2631                           0x1, /* st1 7 */
2632                           0x2, /* st2 8 */
2633                           0x12, /* st2 9 */
2634                           0x2, /* st1 10 */
2635                           0, 0, 0, 0, 0
2636                         };
2637                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2638                         int rn = ((given >> 16) & 0xf);
2639                         int rm = ((given >> 0) & 0xf);
2640                         int align = ((given >> 4) & 0x3);
2641                         int type = ((given >> 8) & 0xf);
2642                         int n = enc[type] & 0xf;
2643                         int stride = (enc[type] >> 4) + 1;
2644                         int ix;
2645
2646                         func (stream, "{");
2647                         if (stride > 1)
2648                           for (ix = 0; ix != n; ix++)
2649                             func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
2650                         else if (n == 1)
2651                           func (stream, "d%d", rd);
2652                         else
2653                           func (stream, "d%d-d%d", rd, rd + n - 1);
2654                         func (stream, "}, [%s", arm_regnames[rn]);
2655                         if (align)
2656                           func (stream, " :%d", 32 << align);
2657                         func (stream, "]");
2658                         if (rm == 0xd)
2659                           func (stream, "!");
2660                         else if (rm != 0xf)
2661                           func (stream, ", %s", arm_regnames[rm]);
2662                       }
2663                       break;
2664
2665                     case 'B':
2666                       {
2667                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2668                         int rn = ((given >> 16) & 0xf);
2669                         int rm = ((given >> 0) & 0xf);
2670                         int idx_align = ((given >> 4) & 0xf);
2671                         int align = 0;
2672                         int size = ((given >> 10) & 0x3);
2673                         int idx = idx_align >> (size + 1);
2674                         int length = ((given >> 8) & 3) + 1;
2675                         int stride = 1;
2676                         int i;
2677
2678                         if (length > 1 && size > 0)
2679                           stride = (idx_align & (1 << size)) ? 2 : 1;
2680
2681                         switch (length)
2682                           {
2683                           case 1:
2684                             {
2685                               int amask = (1 << size) - 1;
2686                               if ((idx_align & (1 << size)) != 0)
2687                                 return FALSE;
2688                               if (size > 0)
2689                                 {
2690                                   if ((idx_align & amask) == amask)
2691                                     align = 8 << size;
2692                                   else if ((idx_align & amask) != 0)
2693                                     return FALSE;
2694                                 }
2695                               }
2696                             break;
2697
2698                           case 2:
2699                             if (size == 2 && (idx_align & 2) != 0)
2700                               return FALSE;
2701                             align = (idx_align & 1) ? 16 << size : 0;
2702                             break;
2703
2704                           case 3:
2705                             if ((size == 2 && (idx_align & 3) != 0)
2706                                 || (idx_align & 1) != 0)
2707                               return FALSE;
2708                             break;
2709
2710                           case 4:
2711                             if (size == 2)
2712                               {
2713                                 if ((idx_align & 3) == 3)
2714                                   return FALSE;
2715                                 align = (idx_align & 3) * 64;
2716                               }
2717                             else
2718                               align = (idx_align & 1) ? 32 << size : 0;
2719                             break;
2720
2721                           default:
2722                             abort ();
2723                           }
2724
2725                         func (stream, "{");
2726                         for (i = 0; i < length; i++)
2727                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
2728                             rd + i * stride, idx);
2729                         func (stream, "}, [%s", arm_regnames[rn]);
2730                         if (align)
2731                           func (stream, " :%d", align);
2732                         func (stream, "]");
2733                         if (rm == 0xd)
2734                           func (stream, "!");
2735                         else if (rm != 0xf)
2736                           func (stream, ", %s", arm_regnames[rm]);
2737                       }
2738                       break;
2739
2740                     case 'C':
2741                       {
2742                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2743                         int rn = ((given >> 16) & 0xf);
2744                         int rm = ((given >> 0) & 0xf);
2745                         int align = ((given >> 4) & 0x1);
2746                         int size = ((given >> 6) & 0x3);
2747                         int type = ((given >> 8) & 0x3);
2748                         int n = type + 1;
2749                         int stride = ((given >> 5) & 0x1);
2750                         int ix;
2751
2752                         if (stride && (n == 1))
2753                           n++;
2754                         else
2755                           stride++;
2756
2757                         func (stream, "{");
2758                         if (stride > 1)
2759                           for (ix = 0; ix != n; ix++)
2760                             func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
2761                         else if (n == 1)
2762                           func (stream, "d%d[]", rd);
2763                         else
2764                           func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
2765                         func (stream, "}, [%s", arm_regnames[rn]);
2766                         if (align)
2767                           {
2768                             align = (8 * (type + 1)) << size;
2769                             if (type == 3)
2770                               align = (size > 1) ? align >> 1 : align;
2771                             if (type == 2 || (type == 0 && !size))
2772                               func (stream, " :<bad align %d>", align);
2773                             else
2774                               func (stream, " :%d", align);
2775                           }
2776                         func (stream, "]");
2777                         if (rm == 0xd)
2778                           func (stream, "!");
2779                         else if (rm != 0xf)
2780                           func (stream, ", %s", arm_regnames[rm]);
2781                       }
2782                       break;
2783
2784                     case 'D':
2785                       {
2786                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
2787                         int size = (given >> 20) & 3;
2788                         int reg = raw_reg & ((4 << size) - 1);
2789                         int ix = raw_reg >> size >> 2;
2790
2791                         func (stream, "d%d[%d]", reg, ix);
2792                       }
2793                       break;
2794
2795                     case 'E':
2796                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
2797                       {
2798                         int bits = 0;
2799                         int cmode = (given >> 8) & 0xf;
2800                         int op = (given >> 5) & 0x1;
2801                         unsigned long value = 0, hival = 0;
2802                         unsigned shift;
2803                         int size = 0;
2804                         int isfloat = 0;
2805
2806                         bits |= ((given >> 24) & 1) << 7;
2807                         bits |= ((given >> 16) & 7) << 4;
2808                         bits |= ((given >> 0) & 15) << 0;
2809
2810                         if (cmode < 8)
2811                           {
2812                             shift = (cmode >> 1) & 3;
2813                             value = (unsigned long) bits << (8 * shift);
2814                             size = 32;
2815                           }
2816                         else if (cmode < 12)
2817                           {
2818                             shift = (cmode >> 1) & 1;
2819                             value = (unsigned long) bits << (8 * shift);
2820                             size = 16;
2821                           }
2822                         else if (cmode < 14)
2823                           {
2824                             shift = (cmode & 1) + 1;
2825                             value = (unsigned long) bits << (8 * shift);
2826                             value |= (1ul << (8 * shift)) - 1;
2827                             size = 32;
2828                           }
2829                         else if (cmode == 14)
2830                           {
2831                             if (op)
2832                               {
2833                                 /* Bit replication into bytes.  */
2834                                 int ix;
2835                                 unsigned long mask;
2836
2837                                 value = 0;
2838                                 hival = 0;
2839                                 for (ix = 7; ix >= 0; ix--)
2840                                   {
2841                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
2842                                     if (ix <= 3)
2843                                       value = (value << 8) | mask;
2844                                     else
2845                                       hival = (hival << 8) | mask;
2846                                   }
2847                                 size = 64;
2848                               }
2849                             else
2850                               {
2851                                 /* Byte replication.  */
2852                                 value = (unsigned long) bits;
2853                                 size = 8;
2854                               }
2855                           }
2856                         else if (!op)
2857                           {
2858                             /* Floating point encoding.  */
2859                             int tmp;
2860
2861                             value = (unsigned long)  (bits & 0x7f) << 19;
2862                             value |= (unsigned long) (bits & 0x80) << 24;
2863                             tmp = bits & 0x40 ? 0x3c : 0x40;
2864                             value |= (unsigned long) tmp << 24;
2865                             size = 32;
2866                             isfloat = 1;
2867                           }
2868                         else
2869                           {
2870                             func (stream, "<illegal constant %.8x:%x:%x>",
2871                                   bits, cmode, op);
2872                             size = 32;
2873                             break;
2874                           }
2875                         switch (size)
2876                           {
2877                           case 8:
2878                             func (stream, "#%ld\t; 0x%.2lx", value, value);
2879                             break;
2880
2881                           case 16:
2882                             func (stream, "#%ld\t; 0x%.4lx", value, value);
2883                             break;
2884
2885                           case 32:
2886                             if (isfloat)
2887                               {
2888                                 unsigned char valbytes[4];
2889                                 double fvalue;
2890
2891                                 /* Do this a byte at a time so we don't have to
2892                                    worry about the host's endianness.  */
2893                                 valbytes[0] = value & 0xff;
2894                                 valbytes[1] = (value >> 8) & 0xff;
2895                                 valbytes[2] = (value >> 16) & 0xff;
2896                                 valbytes[3] = (value >> 24) & 0xff;
2897
2898                                 floatformat_to_double
2899                                   (& floatformat_ieee_single_little, valbytes,
2900                                   & fvalue);
2901
2902                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
2903                                       value);
2904                               }
2905                             else
2906                               func (stream, "#%ld\t; 0x%.8lx",
2907                                     (long) (((value & 0x80000000L) != 0)
2908                                             ? value | ~0xffffffffL : value),
2909                                     value);
2910                             break;
2911
2912                           case 64:
2913                             func (stream, "#0x%.8lx%.8lx", hival, value);
2914                             break;
2915
2916                           default:
2917                             abort ();
2918                           }
2919                       }
2920                       break;
2921
2922                     case 'F':
2923                       {
2924                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
2925                         int num = (given >> 8) & 0x3;
2926
2927                         if (!num)
2928                           func (stream, "{d%d}", regno);
2929                         else if (num + regno >= 32)
2930                           func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
2931                         else
2932                           func (stream, "{d%d-d%d}", regno, regno + num);
2933                       }
2934                       break;
2935
2936
2937                     case '0': case '1': case '2': case '3': case '4':
2938                     case '5': case '6': case '7': case '8': case '9':
2939                       {
2940                         int width;
2941                         unsigned long value;
2942
2943                         c = arm_decode_bitfield (c, given, &value, &width);
2944
2945                         switch (*c)
2946                           {
2947                           case 'r':
2948                             func (stream, "%s", arm_regnames[value]);
2949                             break;
2950                           case 'd':
2951                             func (stream, "%ld", value);
2952                             value_in_comment = value;
2953                             break;
2954                           case 'e':
2955                             func (stream, "%ld", (1ul << width) - value);
2956                             break;
2957
2958                           case 'S':
2959                           case 'T':
2960                           case 'U':
2961                             /* Various width encodings.  */
2962                             {
2963                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
2964                               int limit;
2965                               unsigned low, high;
2966
2967                               c++;
2968                               if (*c >= '0' && *c <= '9')
2969                                 limit = *c - '0';
2970                               else if (*c >= 'a' && *c <= 'f')
2971                                 limit = *c - 'a' + 10;
2972                               else
2973                                 abort ();
2974                               low = limit >> 2;
2975                               high = limit & 3;
2976
2977                               if (value < low || value > high)
2978                                 func (stream, "<illegal width %d>", base << value);
2979                               else
2980                                 func (stream, "%d", base << value);
2981                             }
2982                             break;
2983                           case 'R':
2984                             if (given & (1 << 6))
2985                               goto Q;
2986                             /* FALLTHROUGH */
2987                           case 'D':
2988                             func (stream, "d%ld", value);
2989                             break;
2990                           case 'Q':
2991                           Q:
2992                             if (value & 1)
2993                               func (stream, "<illegal reg q%ld.5>", value >> 1);
2994                             else
2995                               func (stream, "q%ld", value >> 1);
2996                             break;
2997
2998                           case '`':
2999                             c++;
3000                             if (value == 0)
3001                               func (stream, "%c", *c);
3002                             break;
3003                           case '\'':
3004                             c++;
3005                             if (value == ((1ul << width) - 1))
3006                               func (stream, "%c", *c);
3007                             break;
3008                           case '?':
3009                             func (stream, "%c", c[(1 << width) - (int) value]);
3010                             c += 1 << width;
3011                             break;
3012                           default:
3013                             abort ();
3014                           }
3015                         break;
3016
3017                       default:
3018                         abort ();
3019                       }
3020                     }
3021                 }
3022               else
3023                 func (stream, "%c", *c);
3024             }
3025
3026           if (value_in_comment > 32 || value_in_comment < -16)
3027             func (stream, "\t; 0x%lx", value_in_comment);
3028
3029           if (is_unpredictable)
3030             func (stream, UNPREDICTABLE_INSTRUCTION);
3031
3032           return TRUE;
3033         }
3034     }
3035   return FALSE;
3036 }
3037
3038 /* Return the name of a v7A special register.  */
3039
3040 static const char *
3041 banked_regname (unsigned reg)
3042 {
3043   switch (reg)
3044     {
3045       case 15: return "CPSR";
3046       case 32: return "R8_usr";
3047       case 33: return "R9_usr";
3048       case 34: return "R10_usr";
3049       case 35: return "R11_usr";
3050       case 36: return "R12_usr";
3051       case 37: return "SP_usr";
3052       case 38: return "LR_usr";
3053       case 40: return "R8_fiq";
3054       case 41: return "R9_fiq";
3055       case 42: return "R10_fiq";
3056       case 43: return "R11_fiq";
3057       case 44: return "R12_fiq";
3058       case 45: return "SP_fiq";
3059       case 46: return "LR_fiq";
3060       case 48: return "LR_irq";
3061       case 49: return "SP_irq";
3062       case 50: return "LR_svc";
3063       case 51: return "SP_svc";
3064       case 52: return "LR_abt";
3065       case 53: return "SP_abt";
3066       case 54: return "LR_und";
3067       case 55: return "SP_und";
3068       case 60: return "LR_mon";
3069       case 61: return "SP_mon";
3070       case 62: return "ELR_hyp";
3071       case 63: return "SP_hyp";
3072       case 79: return "SPSR";
3073       case 110: return "SPSR_fiq";
3074       case 112: return "SPSR_irq";
3075       case 114: return "SPSR_svc";
3076       case 116: return "SPSR_abt";
3077       case 118: return "SPSR_und";
3078       case 124: return "SPSR_mon";
3079       case 126: return "SPSR_hyp";
3080       default: return NULL;
3081     }
3082 }
3083
3084 /* Return the name of the DMB/DSB option.  */
3085 static const char *
3086 data_barrier_option (unsigned option)
3087 {
3088   switch (option & 0xf)
3089     {
3090     case 0xf: return "sy";
3091     case 0xe: return "st";
3092     case 0xd: return "ld";
3093     case 0xb: return "ish";
3094     case 0xa: return "ishst";
3095     case 0x9: return "ishld";
3096     case 0x7: return "un";
3097     case 0x6: return "unst";
3098     case 0x5: return "nshld";
3099     case 0x3: return "osh";
3100     case 0x2: return "oshst";
3101     case 0x1: return "oshld";
3102     default:  return NULL;
3103     }
3104 }
3105
3106 /* Print one ARM instruction from PC on INFO->STREAM.  */
3107
3108 static void
3109 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
3110 {
3111   const struct opcode32 *insn;
3112   void *stream = info->stream;
3113   fprintf_ftype func = info->fprintf_func;
3114   struct arm_private_data *private_data = info->private_data;
3115
3116   if (print_insn_coprocessor (pc, info, given, FALSE))
3117     return;
3118
3119   if (print_insn_neon (info, given, FALSE))
3120     return;
3121
3122   for (insn = arm_opcodes; insn->assembler; insn++)
3123     {
3124       if ((given & insn->mask) != insn->value)
3125         continue;
3126
3127       if ((insn->arch & private_data->features.core) == 0)
3128         continue;
3129
3130       /* Special case: an instruction with all bits set in the condition field
3131          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
3132          or by the catchall at the end of the table.  */
3133       if ((given & 0xF0000000) != 0xF0000000
3134           || (insn->mask & 0xF0000000) == 0xF0000000
3135           || (insn->mask == 0 && insn->value == 0))
3136         {
3137           unsigned long u_reg = 16;
3138           unsigned long U_reg = 16;
3139           bfd_boolean is_unpredictable = FALSE;
3140           signed long value_in_comment = 0;
3141           const char *c;
3142
3143           for (c = insn->assembler; *c; c++)
3144             {
3145               if (*c == '%')
3146                 {
3147                   bfd_boolean allow_unpredictable = FALSE;
3148
3149                   switch (*++c)
3150                     {
3151                     case '%':
3152                       func (stream, "%%");
3153                       break;
3154
3155                     case 'a':
3156                       value_in_comment = print_arm_address (pc, info, given);
3157                       break;
3158
3159                     case 'P':
3160                       /* Set P address bit and use normal address
3161                          printing routine.  */
3162                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
3163                       break;
3164
3165                     case 'S':
3166                       allow_unpredictable = TRUE;
3167                     case 's':
3168                       if ((given & 0x004f0000) == 0x004f0000)
3169                         {
3170                           /* PC relative with immediate offset.  */
3171                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
3172
3173                           if (PRE_BIT_SET)
3174                             {
3175                               /* Elide positive zero offset.  */
3176                               if (offset || NEGATIVE_BIT_SET)
3177                                 func (stream, "[pc, #%s%d]\t; ",
3178                                       NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3179                               else
3180                                 func (stream, "[pc]\t; ");
3181                               if (NEGATIVE_BIT_SET)
3182                                 offset = -offset;
3183                               info->print_address_func (offset + pc + 8, info);
3184                             }
3185                           else
3186                             {
3187                               /* Always show the offset.  */
3188                               func (stream, "[pc], #%s%d",
3189                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3190                               if (! allow_unpredictable)
3191                                 is_unpredictable = TRUE;
3192                             }
3193                         }
3194                       else
3195                         {
3196                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
3197
3198                           func (stream, "[%s",
3199                                 arm_regnames[(given >> 16) & 0xf]);
3200
3201                           if (PRE_BIT_SET)
3202                             {
3203                               if (IMMEDIATE_BIT_SET)
3204                                 {
3205                                   /* Elide offset for non-writeback
3206                                      positive zero.  */
3207                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
3208                                       || offset)
3209                                     func (stream, ", #%s%d",
3210                                           NEGATIVE_BIT_SET ? "-" : "", offset);
3211
3212                                   if (NEGATIVE_BIT_SET)
3213                                     offset = -offset;
3214
3215                                   value_in_comment = offset;
3216                                 }
3217                               else
3218                                 {
3219                                   /* Register Offset or Register Pre-Indexed.  */
3220                                   func (stream, ", %s%s",
3221                                         NEGATIVE_BIT_SET ? "-" : "",
3222                                         arm_regnames[given & 0xf]);
3223
3224                                   /* Writing back to the register that is the source/
3225                                      destination of the load/store is unpredictable.  */
3226                                   if (! allow_unpredictable
3227                                       && WRITEBACK_BIT_SET
3228                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
3229                                     is_unpredictable = TRUE;
3230                                 }
3231
3232                               func (stream, "]%s",
3233                                     WRITEBACK_BIT_SET ? "!" : "");
3234                             }
3235                           else
3236                             {
3237                               if (IMMEDIATE_BIT_SET)
3238                                 {
3239                                   /* Immediate Post-indexed.  */
3240                                   /* PR 10924: Offset must be printed, even if it is zero.  */
3241                                   func (stream, "], #%s%d",
3242                                         NEGATIVE_BIT_SET ? "-" : "", offset);
3243                                   if (NEGATIVE_BIT_SET)
3244                                     offset = -offset;
3245                                   value_in_comment = offset;
3246                                 }
3247                               else
3248                                 {
3249                                   /* Register Post-indexed.  */
3250                                   func (stream, "], %s%s",
3251                                         NEGATIVE_BIT_SET ? "-" : "",
3252                                         arm_regnames[given & 0xf]);
3253
3254                                   /* Writing back to the register that is the source/
3255                                      destination of the load/store is unpredictable.  */
3256                                   if (! allow_unpredictable
3257                                       && (given & 0xf) == ((given >> 12) & 0xf))
3258                                     is_unpredictable = TRUE;
3259                                 }
3260
3261                               if (! allow_unpredictable)
3262                                 {
3263                                   /* Writeback is automatically implied by post- addressing.
3264                                      Setting the W bit is unnecessary and ARM specify it as
3265                                      being unpredictable.  */
3266                                   if (WRITEBACK_BIT_SET
3267                                       /* Specifying the PC register as the post-indexed
3268                                          registers is also unpredictable.  */
3269                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
3270                                     is_unpredictable = TRUE;
3271                                 }
3272                             }
3273                         }
3274                       break;
3275
3276                     case 'b':
3277                       {
3278                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
3279                         info->print_address_func (disp * 4 + pc + 8, info);
3280                       }
3281                       break;
3282
3283                     case 'c':
3284                       if (((given >> 28) & 0xf) != 0xe)
3285                         func (stream, "%s",
3286                               arm_conditional [(given >> 28) & 0xf]);
3287                       break;
3288
3289                     case 'm':
3290                       {
3291                         int started = 0;
3292                         int reg;
3293
3294                         func (stream, "{");
3295                         for (reg = 0; reg < 16; reg++)
3296                           if ((given & (1 << reg)) != 0)
3297                             {
3298                               if (started)
3299                                 func (stream, ", ");
3300                               started = 1;
3301                               func (stream, "%s", arm_regnames[reg]);
3302                             }
3303                         func (stream, "}");
3304                         if (! started)
3305                           is_unpredictable = TRUE;
3306                       }
3307                       break;
3308
3309                     case 'q':
3310                       arm_decode_shift (given, func, stream, FALSE);
3311                       break;
3312
3313                     case 'o':
3314                       if ((given & 0x02000000) != 0)
3315                         {
3316                           unsigned int rotate = (given & 0xf00) >> 7;
3317                           unsigned int immed = (given & 0xff);
3318                           unsigned int a, i;
3319
3320                           a = (((immed << (32 - rotate))
3321                                 | (immed >> rotate)) & 0xffffffff);
3322                           /* If there is another encoding with smaller rotate,
3323                              the rotate should be specified directly.  */
3324                           for (i = 0; i < 32; i += 2)
3325                             if ((a << i | a >> (32 - i)) <= 0xff)
3326                               break;
3327
3328                           if (i != rotate)
3329                             func (stream, "#%d, %d", immed, rotate);
3330                           else
3331                             func (stream, "#%d", a);
3332                           value_in_comment = a;
3333                         }
3334                       else
3335                         arm_decode_shift (given, func, stream, TRUE);
3336                       break;
3337
3338                     case 'p':
3339                       if ((given & 0x0000f000) == 0x0000f000)
3340                         {
3341                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
3342                              mechanism for setting PSR flag bits.  They are
3343                              obsolete in V6 onwards.  */
3344                           if ((private_data->features.core & ARM_EXT_V6) == 0)
3345                             func (stream, "p");
3346                         }
3347                       break;
3348
3349                     case 't':
3350                       if ((given & 0x01200000) == 0x00200000)
3351                         func (stream, "t");
3352                       break;
3353
3354                     case 'A':
3355                       {
3356                         int offset = given & 0xff;
3357
3358                         value_in_comment = offset * 4;
3359                         if (NEGATIVE_BIT_SET)
3360                           value_in_comment = - value_in_comment;
3361
3362                         func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3363
3364                         if (PRE_BIT_SET)
3365                           {
3366                             if (offset)
3367                               func (stream, ", #%d]%s",
3368                                     (int) value_in_comment,
3369                                     WRITEBACK_BIT_SET ? "!" : "");
3370                             else
3371                               func (stream, "]");
3372                           }
3373                         else
3374                           {
3375                             func (stream, "]");
3376
3377                             if (WRITEBACK_BIT_SET)
3378                               {
3379                                 if (offset)
3380                                   func (stream, ", #%d", (int) value_in_comment);
3381                               }
3382                             else
3383                               {
3384                                 func (stream, ", {%d}", (int) offset);
3385                                 value_in_comment = offset;
3386                               }
3387                           }
3388                       }
3389                       break;
3390
3391                     case 'B':
3392                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
3393                       {
3394                         bfd_vma address;
3395                         bfd_vma offset = 0;
3396
3397                         if (! NEGATIVE_BIT_SET)
3398                           /* Is signed, hi bits should be ones.  */
3399                           offset = (-1) ^ 0x00ffffff;
3400
3401                         /* Offset is (SignExtend(offset field)<<2).  */
3402                         offset += given & 0x00ffffff;
3403                         offset <<= 2;
3404                         address = offset + pc + 8;
3405
3406                         if (given & 0x01000000)
3407                           /* H bit allows addressing to 2-byte boundaries.  */
3408                           address += 2;
3409
3410                         info->print_address_func (address, info);
3411                       }
3412                       break;
3413
3414                     case 'C':
3415                       if ((given & 0x02000200) == 0x200)
3416                         {
3417                           const char * name;
3418                           unsigned sysm = (given & 0x004f0000) >> 16;
3419
3420                           sysm |= (given & 0x300) >> 4;
3421                           name = banked_regname (sysm);
3422
3423                           if (name != NULL)
3424                             func (stream, "%s", name);
3425                           else
3426                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
3427                         }
3428                       else
3429                         {
3430                           func (stream, "%cPSR_",
3431                                 (given & 0x00400000) ? 'S' : 'C');
3432                           if (given & 0x80000)
3433                             func (stream, "f");
3434                           if (given & 0x40000)
3435                             func (stream, "s");
3436                           if (given & 0x20000)
3437                             func (stream, "x");
3438                           if (given & 0x10000)
3439                             func (stream, "c");
3440                         }
3441                       break;
3442
3443                     case 'U':
3444                       if ((given & 0xf0) == 0x60)
3445                         {
3446                           switch (given & 0xf)
3447                             {
3448                             case 0xf: func (stream, "sy"); break;
3449                             default:
3450                               func (stream, "#%d", (int) given & 0xf);
3451                               break;
3452                             }
3453                         }
3454                       else
3455                         {
3456                           const char * opt = data_barrier_option (given & 0xf);
3457                           if (opt != NULL)
3458                             func (stream, "%s", opt);
3459                           else
3460                               func (stream, "#%d", (int) given & 0xf);
3461                         }
3462                       break;
3463
3464                     case '0': case '1': case '2': case '3': case '4':
3465                     case '5': case '6': case '7': case '8': case '9':
3466                       {
3467                         int width;
3468                         unsigned long value;
3469
3470                         c = arm_decode_bitfield (c, given, &value, &width);
3471
3472                         switch (*c)
3473                           {
3474                           case 'R':
3475                             if (value == 15)
3476                               is_unpredictable = TRUE;
3477                             /* Fall through.  */
3478                           case 'r':
3479                           case 'T':
3480                             /* We want register + 1 when decoding T.  */
3481                             if (*c == 'T')
3482                               ++value;
3483
3484                             if (c[1] == 'u')
3485                               {
3486                                 /* Eat the 'u' character.  */
3487                                 ++ c;
3488
3489                                 if (u_reg == value)
3490                                   is_unpredictable = TRUE;
3491                                 u_reg = value;
3492                               }
3493                             if (c[1] == 'U')
3494                               {
3495                                 /* Eat the 'U' character.  */
3496                                 ++ c;
3497
3498                                 if (U_reg == value)
3499                                   is_unpredictable = TRUE;
3500                                 U_reg = value;
3501                               }
3502                             func (stream, "%s", arm_regnames[value]);
3503                             break;
3504                           case 'd':
3505                             func (stream, "%ld", value);
3506                             value_in_comment = value;
3507                             break;
3508                           case 'b':
3509                             func (stream, "%ld", value * 8);
3510                             value_in_comment = value * 8;
3511                             break;
3512                           case 'W':
3513                             func (stream, "%ld", value + 1);
3514                             value_in_comment = value + 1;
3515                             break;
3516                           case 'x':
3517                             func (stream, "0x%08lx", value);
3518
3519                             /* Some SWI instructions have special
3520                                meanings.  */
3521                             if ((given & 0x0fffffff) == 0x0FF00000)
3522                               func (stream, "\t; IMB");
3523                             else if ((given & 0x0fffffff) == 0x0FF00001)
3524                               func (stream, "\t; IMBRange");
3525                             break;
3526                           case 'X':
3527                             func (stream, "%01lx", value & 0xf);
3528                             value_in_comment = value;
3529                             break;
3530                           case '`':
3531                             c++;
3532                             if (value == 0)
3533                               func (stream, "%c", *c);
3534                             break;
3535                           case '\'':
3536                             c++;
3537                             if (value == ((1ul << width) - 1))
3538                               func (stream, "%c", *c);
3539                             break;
3540                           case '?':
3541                             func (stream, "%c", c[(1 << width) - (int) value]);
3542                             c += 1 << width;
3543                             break;
3544                           default:
3545                             abort ();
3546                           }
3547                         break;
3548
3549                       case 'e':
3550                         {
3551                           int imm;
3552
3553                           imm = (given & 0xf) | ((given & 0xfff00) >> 4);
3554                           func (stream, "%d", imm);
3555                           value_in_comment = imm;
3556                         }
3557                         break;
3558
3559                       case 'E':
3560                         /* LSB and WIDTH fields of BFI or BFC.  The machine-
3561                            language instruction encodes LSB and MSB.  */
3562                         {
3563                           long msb = (given & 0x001f0000) >> 16;
3564                           long lsb = (given & 0x00000f80) >> 7;
3565                           long w = msb - lsb + 1;
3566
3567                           if (w > 0)
3568                             func (stream, "#%lu, #%lu", lsb, w);
3569                           else
3570                             func (stream, "(invalid: %lu:%lu)", lsb, msb);
3571                         }
3572                         break;
3573
3574                       case 'R':
3575                         /* Get the PSR/banked register name.  */
3576                         {
3577                           const char * name;
3578                           unsigned sysm = (given & 0x004f0000) >> 16;
3579
3580                           sysm |= (given & 0x300) >> 4;
3581                           name = banked_regname (sysm);
3582
3583                           if (name != NULL)
3584                             func (stream, "%s", name);
3585                           else
3586                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
3587                         }
3588                         break;
3589
3590                       case 'V':
3591                         /* 16-bit unsigned immediate from a MOVT or MOVW
3592                            instruction, encoded in bits 0:11 and 15:19.  */
3593                         {
3594                           long hi = (given & 0x000f0000) >> 4;
3595                           long lo = (given & 0x00000fff);
3596                           long imm16 = hi | lo;
3597
3598                           func (stream, "#%lu", imm16);
3599                           value_in_comment = imm16;
3600                         }
3601                         break;
3602
3603                       default:
3604                         abort ();
3605                       }
3606                     }
3607                 }
3608               else
3609                 func (stream, "%c", *c);
3610             }
3611
3612           if (value_in_comment > 32 || value_in_comment < -16)
3613             func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
3614
3615           if (is_unpredictable)
3616             func (stream, UNPREDICTABLE_INSTRUCTION);
3617
3618           return;
3619         }
3620     }
3621   abort ();
3622 }
3623
3624 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
3625
3626 static void
3627 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
3628 {
3629   const struct opcode16 *insn;
3630   void *stream = info->stream;
3631   fprintf_ftype func = info->fprintf_func;
3632
3633   for (insn = thumb_opcodes; insn->assembler; insn++)
3634     if ((given & insn->mask) == insn->value)
3635       {
3636         signed long value_in_comment = 0;
3637         const char *c = insn->assembler;
3638
3639         for (; *c; c++)
3640           {
3641             int domaskpc = 0;
3642             int domasklr = 0;
3643
3644             if (*c != '%')
3645               {
3646                 func (stream, "%c", *c);
3647                 continue;
3648               }
3649
3650             switch (*++c)
3651               {
3652               case '%':
3653                 func (stream, "%%");
3654                 break;
3655
3656               case 'c':
3657                 if (ifthen_state)
3658                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
3659                 break;
3660
3661               case 'C':
3662                 if (ifthen_state)
3663                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
3664                 else
3665                   func (stream, "s");
3666                 break;
3667
3668               case 'I':
3669                 {
3670                   unsigned int tmp;
3671
3672                   ifthen_next_state = given & 0xff;
3673                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
3674                     func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
3675                   func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
3676                 }
3677                 break;
3678
3679               case 'x':
3680                 if (ifthen_next_state)
3681                   func (stream, "\t; unpredictable branch in IT block\n");
3682                 break;
3683
3684               case 'X':
3685                 if (ifthen_state)
3686                   func (stream, "\t; unpredictable <IT:%s>",
3687                         arm_conditional[IFTHEN_COND]);
3688                 break;
3689
3690               case 'S':
3691                 {
3692                   long reg;
3693
3694                   reg = (given >> 3) & 0x7;
3695                   if (given & (1 << 6))
3696                     reg += 8;
3697
3698                   func (stream, "%s", arm_regnames[reg]);
3699                 }
3700                 break;
3701
3702               case 'D':
3703                 {
3704                   long reg;
3705
3706                   reg = given & 0x7;
3707                   if (given & (1 << 7))
3708                     reg += 8;
3709
3710                   func (stream, "%s", arm_regnames[reg]);
3711                 }
3712                 break;
3713
3714               case 'N':
3715                 if (given & (1 << 8))
3716                   domasklr = 1;
3717                 /* Fall through.  */
3718               case 'O':
3719                 if (*c == 'O' && (given & (1 << 8)))
3720                   domaskpc = 1;
3721                 /* Fall through.  */
3722               case 'M':
3723                 {
3724                   int started = 0;
3725                   int reg;
3726
3727                   func (stream, "{");
3728
3729                   /* It would be nice if we could spot
3730                      ranges, and generate the rS-rE format: */
3731                   for (reg = 0; (reg < 8); reg++)
3732                     if ((given & (1 << reg)) != 0)
3733                       {
3734                         if (started)
3735                           func (stream, ", ");
3736                         started = 1;
3737                         func (stream, "%s", arm_regnames[reg]);
3738                       }
3739
3740                   if (domasklr)
3741                     {
3742                       if (started)
3743                         func (stream, ", ");
3744                       started = 1;
3745                       func (stream, "%s", arm_regnames[14] /* "lr" */);
3746                     }
3747
3748                   if (domaskpc)
3749                     {
3750                       if (started)
3751                         func (stream, ", ");
3752                       func (stream, "%s", arm_regnames[15] /* "pc" */);
3753                     }
3754
3755                   func (stream, "}");
3756                 }
3757                 break;
3758
3759               case 'W':
3760                 /* Print writeback indicator for a LDMIA.  We are doing a
3761                    writeback if the base register is not in the register
3762                    mask.  */
3763                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
3764                   func (stream, "!");
3765                 break;
3766
3767               case 'b':
3768                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
3769                 {
3770                   bfd_vma address = (pc + 4
3771                                      + ((given & 0x00f8) >> 2)
3772                                      + ((given & 0x0200) >> 3));
3773                   info->print_address_func (address, info);
3774                 }
3775                 break;
3776
3777               case 's':
3778                 /* Right shift immediate -- bits 6..10; 1-31 print
3779                    as themselves, 0 prints as 32.  */
3780                 {
3781                   long imm = (given & 0x07c0) >> 6;
3782                   if (imm == 0)
3783                     imm = 32;
3784                   func (stream, "#%ld", imm);
3785                 }
3786                 break;
3787
3788               case '0': case '1': case '2': case '3': case '4':
3789               case '5': case '6': case '7': case '8': case '9':
3790                 {
3791                   int bitstart = *c++ - '0';
3792                   int bitend = 0;
3793
3794                   while (*c >= '0' && *c <= '9')
3795                     bitstart = (bitstart * 10) + *c++ - '0';
3796
3797                   switch (*c)
3798                     {
3799                     case '-':
3800                       {
3801                         bfd_vma reg;
3802
3803                         c++;
3804                         while (*c >= '0' && *c <= '9')
3805                           bitend = (bitend * 10) + *c++ - '0';
3806                         if (!bitend)
3807                           abort ();
3808                         reg = given >> bitstart;
3809                         reg &= (2 << (bitend - bitstart)) - 1;
3810
3811                         switch (*c)
3812                           {
3813                           case 'r':
3814                             func (stream, "%s", arm_regnames[reg]);
3815                             break;
3816
3817                           case 'd':
3818                             func (stream, "%ld", (long) reg);
3819                             value_in_comment = reg;
3820                             break;
3821
3822                           case 'H':
3823                             func (stream, "%ld", (long) (reg << 1));
3824                             value_in_comment = reg << 1;
3825                             break;
3826
3827                           case 'W':
3828                             func (stream, "%ld", (long) (reg << 2));
3829                             value_in_comment = reg << 2;
3830                             break;
3831
3832                           case 'a':
3833                             /* PC-relative address -- the bottom two
3834                                bits of the address are dropped
3835                                before the calculation.  */
3836                             info->print_address_func
3837                               (((pc + 4) & ~3) + (reg << 2), info);
3838                             value_in_comment = 0;
3839                             break;
3840
3841                           case 'x':
3842                             func (stream, "0x%04lx", (long) reg);
3843                             break;
3844
3845                           case 'B':
3846                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
3847                             info->print_address_func (reg * 2 + pc + 4, info);
3848                             value_in_comment = 0;
3849                             break;
3850
3851                           case 'c':
3852                             func (stream, "%s", arm_conditional [reg]);
3853                             break;
3854
3855                           default:
3856                             abort ();
3857                           }
3858                       }
3859                       break;
3860
3861                     case '\'':
3862                       c++;
3863                       if ((given & (1 << bitstart)) != 0)
3864                         func (stream, "%c", *c);
3865                       break;
3866
3867                     case '?':
3868                       ++c;
3869                       if ((given & (1 << bitstart)) != 0)
3870                         func (stream, "%c", *c++);
3871                       else
3872                         func (stream, "%c", *++c);
3873                       break;
3874
3875                     default:
3876                       abort ();
3877                     }
3878                 }
3879                 break;
3880
3881               default:
3882                 abort ();
3883               }
3884           }
3885
3886         if (value_in_comment > 32 || value_in_comment < -16)
3887           func (stream, "\t; 0x%lx", value_in_comment);
3888         return;
3889       }
3890
3891   /* No match.  */
3892   abort ();
3893 }
3894
3895 /* Return the name of an V7M special register.  */
3896
3897 static const char *
3898 psr_name (int regno)
3899 {
3900   switch (regno)
3901     {
3902     case 0: return "APSR";
3903     case 1: return "IAPSR";
3904     case 2: return "EAPSR";
3905     case 3: return "PSR";
3906     case 5: return "IPSR";
3907     case 6: return "EPSR";
3908     case 7: return "IEPSR";
3909     case 8: return "MSP";
3910     case 9: return "PSP";
3911     case 16: return "PRIMASK";
3912     case 17: return "BASEPRI";
3913     case 18: return "BASEPRI_MAX";
3914     case 19: return "FAULTMASK";
3915     case 20: return "CONTROL";
3916     default: return "<unknown>";
3917     }
3918 }
3919
3920 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
3921
3922 static void
3923 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
3924 {
3925   const struct opcode32 *insn;
3926   void *stream = info->stream;
3927   fprintf_ftype func = info->fprintf_func;
3928
3929   if (print_insn_coprocessor (pc, info, given, TRUE))
3930     return;
3931
3932   if (print_insn_neon (info, given, TRUE))
3933     return;
3934
3935   for (insn = thumb32_opcodes; insn->assembler; insn++)
3936     if ((given & insn->mask) == insn->value)
3937       {
3938         bfd_boolean is_unpredictable = FALSE;
3939         signed long value_in_comment = 0;
3940         const char *c = insn->assembler;
3941
3942         for (; *c; c++)
3943           {
3944             if (*c != '%')
3945               {
3946                 func (stream, "%c", *c);
3947                 continue;
3948               }
3949
3950             switch (*++c)
3951               {
3952               case '%':
3953                 func (stream, "%%");
3954                 break;
3955
3956               case 'c':
3957                 if (ifthen_state)
3958                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
3959                 break;
3960
3961               case 'x':
3962                 if (ifthen_next_state)
3963                   func (stream, "\t; unpredictable branch in IT block\n");
3964                 break;
3965
3966               case 'X':
3967                 if (ifthen_state)
3968                   func (stream, "\t; unpredictable <IT:%s>",
3969                         arm_conditional[IFTHEN_COND]);
3970                 break;
3971
3972               case 'I':
3973                 {
3974                   unsigned int imm12 = 0;
3975
3976                   imm12 |= (given & 0x000000ffu);
3977                   imm12 |= (given & 0x00007000u) >> 4;
3978                   imm12 |= (given & 0x04000000u) >> 15;
3979                   func (stream, "#%u", imm12);
3980                   value_in_comment = imm12;
3981                 }
3982                 break;
3983
3984               case 'M':
3985                 {
3986                   unsigned int bits = 0, imm, imm8, mod;
3987
3988                   bits |= (given & 0x000000ffu);
3989                   bits |= (given & 0x00007000u) >> 4;
3990                   bits |= (given & 0x04000000u) >> 15;
3991                   imm8 = (bits & 0x0ff);
3992                   mod = (bits & 0xf00) >> 8;
3993                   switch (mod)
3994                     {
3995                     case 0: imm = imm8; break;
3996                     case 1: imm = ((imm8 << 16) | imm8); break;
3997                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
3998                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
3999                     default:
4000                       mod  = (bits & 0xf80) >> 7;
4001                       imm8 = (bits & 0x07f) | 0x80;
4002                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
4003                     }
4004                   func (stream, "#%u", imm);
4005                   value_in_comment = imm;
4006                 }
4007                 break;
4008
4009               case 'J':
4010                 {
4011                   unsigned int imm = 0;
4012
4013                   imm |= (given & 0x000000ffu);
4014                   imm |= (given & 0x00007000u) >> 4;
4015                   imm |= (given & 0x04000000u) >> 15;
4016                   imm |= (given & 0x000f0000u) >> 4;
4017                   func (stream, "#%u", imm);
4018                   value_in_comment = imm;
4019                 }
4020                 break;
4021
4022               case 'K':
4023                 {
4024                   unsigned int imm = 0;
4025
4026                   imm |= (given & 0x000f0000u) >> 16;
4027                   imm |= (given & 0x00000ff0u) >> 0;
4028                   imm |= (given & 0x0000000fu) << 12;
4029                   func (stream, "#%u", imm);
4030                   value_in_comment = imm;
4031                 }
4032                 break;
4033
4034               case 'V':
4035                 {
4036                   unsigned int imm = 0;
4037
4038                   imm |= (given & 0x00000fffu);
4039                   imm |= (given & 0x000f0000u) >> 4;
4040                   func (stream, "#%u", imm);
4041                   value_in_comment = imm;
4042                 }
4043                 break;
4044
4045               case 'S':
4046                 {
4047                   unsigned int reg = (given & 0x0000000fu);
4048                   unsigned int stp = (given & 0x00000030u) >> 4;
4049                   unsigned int imm = 0;
4050                   imm |= (given & 0x000000c0u) >> 6;
4051                   imm |= (given & 0x00007000u) >> 10;
4052
4053                   func (stream, "%s", arm_regnames[reg]);
4054                   switch (stp)
4055                     {
4056                     case 0:
4057                       if (imm > 0)
4058                         func (stream, ", lsl #%u", imm);
4059                       break;
4060
4061                     case 1:
4062                       if (imm == 0)
4063                         imm = 32;
4064                       func (stream, ", lsr #%u", imm);
4065                       break;
4066
4067                     case 2:
4068                       if (imm == 0)
4069                         imm = 32;
4070                       func (stream, ", asr #%u", imm);
4071                       break;
4072
4073                     case 3:
4074                       if (imm == 0)
4075                         func (stream, ", rrx");
4076                       else
4077                         func (stream, ", ror #%u", imm);
4078                     }
4079                 }
4080                 break;
4081
4082               case 'a':
4083                 {
4084                   unsigned int Rn  = (given & 0x000f0000) >> 16;
4085                   unsigned int U   = ! NEGATIVE_BIT_SET;
4086                   unsigned int op  = (given & 0x00000f00) >> 8;
4087                   unsigned int i12 = (given & 0x00000fff);
4088                   unsigned int i8  = (given & 0x000000ff);
4089                   bfd_boolean writeback = FALSE, postind = FALSE;
4090                   bfd_vma offset = 0;
4091
4092                   func (stream, "[%s", arm_regnames[Rn]);
4093                   if (U) /* 12-bit positive immediate offset.  */
4094                     {
4095                       offset = i12;
4096                       if (Rn != 15)
4097                         value_in_comment = offset;
4098                     }
4099                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
4100                     offset = - (int) i12;
4101                   else if (op == 0x0) /* Shifted register offset.  */
4102                     {
4103                       unsigned int Rm = (i8 & 0x0f);
4104                       unsigned int sh = (i8 & 0x30) >> 4;
4105
4106                       func (stream, ", %s", arm_regnames[Rm]);
4107                       if (sh)
4108                         func (stream, ", lsl #%u", sh);
4109                       func (stream, "]");
4110                       break;
4111                     }
4112                   else switch (op)
4113                     {
4114                     case 0xE:  /* 8-bit positive immediate offset.  */
4115                       offset = i8;
4116                       break;
4117
4118                     case 0xC:  /* 8-bit negative immediate offset.  */
4119                       offset = -i8;
4120                       break;
4121
4122                     case 0xF:  /* 8-bit + preindex with wb.  */
4123                       offset = i8;
4124                       writeback = TRUE;
4125                       break;
4126
4127                     case 0xD:  /* 8-bit - preindex with wb.  */
4128                       offset = -i8;
4129                       writeback = TRUE;
4130                       break;
4131
4132                     case 0xB:  /* 8-bit + postindex.  */
4133                       offset = i8;
4134                       postind = TRUE;
4135                       break;
4136
4137                     case 0x9:  /* 8-bit - postindex.  */
4138                       offset = -i8;
4139                       postind = TRUE;
4140                       break;
4141
4142                     default:
4143                       func (stream, ", <undefined>]");
4144                       goto skip;
4145                     }
4146
4147                   if (postind)
4148                     func (stream, "], #%d", (int) offset);
4149                   else
4150                     {
4151                       if (offset)
4152                         func (stream, ", #%d", (int) offset);
4153                       func (stream, writeback ? "]!" : "]");
4154                     }
4155
4156                   if (Rn == 15)
4157                     {
4158                       func (stream, "\t; ");
4159                       info->print_address_func (((pc + 4) & ~3) + offset, info);
4160                     }
4161                 }
4162               skip:
4163                 break;
4164
4165               case 'A':
4166                 {
4167                   unsigned int U   = ! NEGATIVE_BIT_SET;
4168                   unsigned int W   = WRITEBACK_BIT_SET;
4169                   unsigned int Rn  = (given & 0x000f0000) >> 16;
4170                   unsigned int off = (given & 0x000000ff);
4171
4172                   func (stream, "[%s", arm_regnames[Rn]);
4173
4174                   if (PRE_BIT_SET)
4175                     {
4176                       if (off || !U)
4177                         {
4178                           func (stream, ", #%c%u", U ? '+' : '-', off * 4);
4179                           value_in_comment = off * 4 * U ? 1 : -1;
4180                         }
4181                       func (stream, "]");
4182                       if (W)
4183                         func (stream, "!");
4184                     }
4185                   else
4186                     {
4187                       func (stream, "], ");
4188                       if (W)
4189                         {
4190                           func (stream, "#%c%u", U ? '+' : '-', off * 4);
4191                           value_in_comment = off * 4 * U ? 1 : -1;
4192                         }
4193                       else
4194                         {
4195                           func (stream, "{%u}", off);
4196                           value_in_comment = off;
4197                         }
4198                     }
4199                 }
4200                 break;
4201
4202               case 'w':
4203                 {
4204                   unsigned int Sbit = (given & 0x01000000) >> 24;
4205                   unsigned int type = (given & 0x00600000) >> 21;
4206
4207                   switch (type)
4208                     {
4209                     case 0: func (stream, Sbit ? "sb" : "b"); break;
4210                     case 1: func (stream, Sbit ? "sh" : "h"); break;
4211                     case 2:
4212                       if (Sbit)
4213                         func (stream, "??");
4214                       break;
4215                     case 3:
4216                       func (stream, "??");
4217                       break;
4218                     }
4219                 }
4220                 break;
4221
4222               case 'm':
4223                 {
4224                   int started = 0;
4225                   int reg;
4226
4227                   func (stream, "{");
4228                   for (reg = 0; reg < 16; reg++)
4229                     if ((given & (1 << reg)) != 0)
4230                       {
4231                         if (started)
4232                           func (stream, ", ");
4233                         started = 1;
4234                         func (stream, "%s", arm_regnames[reg]);
4235                       }
4236                   func (stream, "}");
4237                 }
4238                 break;
4239
4240               case 'E':
4241                 {
4242                   unsigned int msb = (given & 0x0000001f);
4243                   unsigned int lsb = 0;
4244
4245                   lsb |= (given & 0x000000c0u) >> 6;
4246                   lsb |= (given & 0x00007000u) >> 10;
4247                   func (stream, "#%u, #%u", lsb, msb - lsb + 1);
4248                 }
4249                 break;
4250
4251               case 'F':
4252                 {
4253                   unsigned int width = (given & 0x0000001f) + 1;
4254                   unsigned int lsb = 0;
4255
4256                   lsb |= (given & 0x000000c0u) >> 6;
4257                   lsb |= (given & 0x00007000u) >> 10;
4258                   func (stream, "#%u, #%u", lsb, width);
4259                 }
4260                 break;
4261
4262               case 'b':
4263                 {
4264                   unsigned int S = (given & 0x04000000u) >> 26;
4265                   unsigned int J1 = (given & 0x00002000u) >> 13;
4266                   unsigned int J2 = (given & 0x00000800u) >> 11;
4267                   bfd_vma offset = 0;
4268
4269                   offset |= !S << 20;
4270                   offset |= J2 << 19;
4271                   offset |= J1 << 18;
4272                   offset |= (given & 0x003f0000) >> 4;
4273                   offset |= (given & 0x000007ff) << 1;
4274                   offset -= (1 << 20);
4275
4276                   info->print_address_func (pc + 4 + offset, info);
4277                 }
4278                 break;
4279
4280               case 'B':
4281                 {
4282                   unsigned int S = (given & 0x04000000u) >> 26;
4283                   unsigned int I1 = (given & 0x00002000u) >> 13;
4284                   unsigned int I2 = (given & 0x00000800u) >> 11;
4285                   bfd_vma offset = 0;
4286
4287                   offset |= !S << 24;
4288                   offset |= !(I1 ^ S) << 23;
4289                   offset |= !(I2 ^ S) << 22;
4290                   offset |= (given & 0x03ff0000u) >> 4;
4291                   offset |= (given & 0x000007ffu) << 1;
4292                   offset -= (1 << 24);
4293                   offset += pc + 4;
4294
4295                   /* BLX target addresses are always word aligned.  */
4296                   if ((given & 0x00001000u) == 0)
4297                       offset &= ~2u;
4298
4299                   info->print_address_func (offset, info);
4300                 }
4301                 break;
4302
4303               case 's':
4304                 {
4305                   unsigned int shift = 0;
4306
4307                   shift |= (given & 0x000000c0u) >> 6;
4308                   shift |= (given & 0x00007000u) >> 10;
4309                   if (WRITEBACK_BIT_SET)
4310                     func (stream, ", asr #%u", shift);
4311                   else if (shift)
4312                     func (stream, ", lsl #%u", shift);
4313                   /* else print nothing - lsl #0 */
4314                 }
4315                 break;
4316
4317               case 'R':
4318                 {
4319                   unsigned int rot = (given & 0x00000030) >> 4;
4320
4321                   if (rot)
4322                     func (stream, ", ror #%u", rot * 8);
4323                 }
4324                 break;
4325
4326               case 'U':
4327                 if ((given & 0xf0) == 0x60)
4328                   {
4329                     switch (given & 0xf)
4330                       {
4331                         case 0xf: func (stream, "sy"); break;
4332                         default:
4333                           func (stream, "#%d", (int) given & 0xf);
4334                               break;
4335                       }
4336                   }
4337                 else
4338                   {
4339                     const char * opt = data_barrier_option (given & 0xf);
4340                     if (opt != NULL)
4341                       func (stream, "%s", opt);
4342                     else
4343                       func (stream, "#%d", (int) given & 0xf);
4344                    }
4345                 break;
4346
4347               case 'C':
4348                 if ((given & 0xff) == 0)
4349                   {
4350                     func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
4351                     if (given & 0x800)
4352                       func (stream, "f");
4353                     if (given & 0x400)
4354                       func (stream, "s");
4355                     if (given & 0x200)
4356                       func (stream, "x");
4357                     if (given & 0x100)
4358                       func (stream, "c");
4359                   }
4360                 else if ((given & 0x20) == 0x20)
4361                   {
4362                     char const* name;
4363                     unsigned sysm = (given & 0xf00) >> 8;
4364
4365                     sysm |= (given & 0x30);
4366                     sysm |= (given & 0x00100000) >> 14;
4367                     name = banked_regname (sysm);
4368
4369                     if (name != NULL)
4370                       func (stream, "%s", name);
4371                     else
4372                       func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4373                   }
4374                 else
4375                   {
4376                     func (stream, "%s", psr_name (given & 0xff));
4377                   }
4378                 break;
4379
4380               case 'D':
4381                 if (((given & 0xff) == 0)
4382                     || ((given & 0x20) == 0x20))
4383                   {
4384                     char const* name;
4385                     unsigned sm = (given & 0xf0000) >> 16;
4386
4387                     sm |= (given & 0x30);
4388                     sm |= (given & 0x00100000) >> 14;
4389                     name = banked_regname (sm);
4390
4391                     if (name != NULL)
4392                       func (stream, "%s", name);
4393                     else
4394                       func (stream, "(UNDEF: %lu)", (unsigned long) sm);
4395                   }
4396                 else
4397                   func (stream, "%s", psr_name (given & 0xff));
4398                 break;
4399
4400               case '0': case '1': case '2': case '3': case '4':
4401               case '5': case '6': case '7': case '8': case '9':
4402                 {
4403                   int width;
4404                   unsigned long val;
4405
4406                   c = arm_decode_bitfield (c, given, &val, &width);
4407
4408                   switch (*c)
4409                     {
4410                     case 'd':
4411                       func (stream, "%lu", val);
4412                       value_in_comment = val;
4413                       break;
4414
4415                     case 'W':
4416                       func (stream, "%lu", val * 4);
4417                       value_in_comment = val * 4;
4418                       break;
4419
4420                     case 'R':
4421                       if (val == 15)
4422                         is_unpredictable = TRUE;
4423                       /* Fall through.  */
4424                     case 'r':
4425                       func (stream, "%s", arm_regnames[val]);
4426                       break;
4427
4428                     case 'c':
4429                       func (stream, "%s", arm_conditional[val]);
4430                       break;
4431
4432                     case '\'':
4433                       c++;
4434                       if (val == ((1ul << width) - 1))
4435                         func (stream, "%c", *c);
4436                       break;
4437
4438                     case '`':
4439                       c++;
4440                       if (val == 0)
4441                         func (stream, "%c", *c);
4442                       break;
4443
4444                     case '?':
4445                       func (stream, "%c", c[(1 << width) - (int) val]);
4446                       c += 1 << width;
4447                       break;
4448
4449                     case 'x':
4450                       func (stream, "0x%lx", val & 0xffffffffUL);
4451                       break;
4452
4453                     default:
4454                       abort ();
4455                     }
4456                 }
4457                 break;
4458
4459               case 'L':
4460                 /* PR binutils/12534
4461                    If we have a PC relative offset in an LDRD or STRD
4462                    instructions then display the decoded address.  */
4463                 if (((given >> 16) & 0xf) == 0xf)
4464                   {
4465                     bfd_vma offset = (given & 0xff) * 4;
4466
4467                     if ((given & (1 << 23)) == 0)
4468                       offset = - offset;
4469                     func (stream, "\t; ");
4470                     info->print_address_func ((pc & ~3) + 4 + offset, info);
4471                   }
4472                 break;
4473
4474               default:
4475                 abort ();
4476               }
4477           }
4478
4479         if (value_in_comment > 32 || value_in_comment < -16)
4480           func (stream, "\t; 0x%lx", value_in_comment);
4481
4482         if (is_unpredictable)
4483           func (stream, UNPREDICTABLE_INSTRUCTION);
4484
4485         return;
4486       }
4487
4488   /* No match.  */
4489   abort ();
4490 }
4491
4492 /* Print data bytes on INFO->STREAM.  */
4493
4494 static void
4495 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
4496                  struct disassemble_info *info,
4497                  long given)
4498 {
4499   switch (info->bytes_per_chunk)
4500     {
4501     case 1:
4502       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
4503       break;
4504     case 2:
4505       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
4506       break;
4507     case 4:
4508       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
4509       break;
4510     default:
4511       abort ();
4512     }
4513 }
4514
4515 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
4516    being displayed in symbol relative addresses.  */
4517
4518 bfd_boolean
4519 arm_symbol_is_valid (asymbol * sym,
4520                      struct disassemble_info * info ATTRIBUTE_UNUSED)
4521 {
4522   const char * name;
4523
4524   if (sym == NULL)
4525     return FALSE;
4526
4527   name = bfd_asymbol_name (sym);
4528
4529   return (name && *name != '$');
4530 }
4531
4532 /* Parse an individual disassembler option.  */
4533
4534 void
4535 parse_arm_disassembler_option (char *option)
4536 {
4537   if (option == NULL)
4538     return;
4539
4540   if (CONST_STRNEQ (option, "reg-names-"))
4541     {
4542       int i;
4543
4544       option += 10;
4545
4546       for (i = NUM_ARM_REGNAMES; i--;)
4547         if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
4548           {
4549             regname_selected = i;
4550             break;
4551           }
4552
4553       if (i < 0)
4554         /* XXX - should break 'option' at following delimiter.  */
4555         fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
4556     }
4557   else if (CONST_STRNEQ (option, "force-thumb"))
4558     force_thumb = 1;
4559   else if (CONST_STRNEQ (option, "no-force-thumb"))
4560     force_thumb = 0;
4561   else
4562     /* XXX - should break 'option' at following delimiter.  */
4563     fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
4564
4565   return;
4566 }
4567
4568 /* Parse the string of disassembler options, spliting it at whitespaces
4569    or commas.  (Whitespace separators supported for backwards compatibility).  */
4570
4571 static void
4572 parse_disassembler_options (char *options)
4573 {
4574   if (options == NULL)
4575     return;
4576
4577   while (*options)
4578     {
4579       parse_arm_disassembler_option (options);
4580
4581       /* Skip forward to next seperator.  */
4582       while ((*options) && (! ISSPACE (*options)) && (*options != ','))
4583         ++ options;
4584       /* Skip forward past seperators.  */
4585       while (ISSPACE (*options) || (*options == ','))
4586         ++ options;
4587     }
4588 }
4589
4590 /* Search back through the insn stream to determine if this instruction is
4591    conditionally executed.  */
4592
4593 static void
4594 find_ifthen_state (bfd_vma pc,
4595                    struct disassemble_info *info,
4596                    bfd_boolean little)
4597 {
4598   unsigned char b[2];
4599   unsigned int insn;
4600   int status;
4601   /* COUNT is twice the number of instructions seen.  It will be odd if we
4602      just crossed an instruction boundary.  */
4603   int count;
4604   int it_count;
4605   unsigned int seen_it;
4606   bfd_vma addr;
4607
4608   ifthen_address = pc;
4609   ifthen_state = 0;
4610
4611   addr = pc;
4612   count = 1;
4613   it_count = 0;
4614   seen_it = 0;
4615   /* Scan backwards looking for IT instructions, keeping track of where
4616      instruction boundaries are.  We don't know if something is actually an
4617      IT instruction until we find a definite instruction boundary.  */
4618   for (;;)
4619     {
4620       if (addr == 0 || info->symbol_at_address_func (addr, info))
4621         {
4622           /* A symbol must be on an instruction boundary, and will not
4623              be within an IT block.  */
4624           if (seen_it && (count & 1))
4625             break;
4626
4627           return;
4628         }
4629       addr -= 2;
4630       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
4631       if (status)
4632         return;
4633
4634       if (little)
4635         insn = (b[0]) | (b[1] << 8);
4636       else
4637         insn = (b[1]) | (b[0] << 8);
4638       if (seen_it)
4639         {
4640           if ((insn & 0xf800) < 0xe800)
4641             {
4642               /* Addr + 2 is an instruction boundary.  See if this matches
4643                  the expected boundary based on the position of the last
4644                  IT candidate.  */
4645               if (count & 1)
4646                 break;
4647               seen_it = 0;
4648             }
4649         }
4650       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
4651         {
4652           /* This could be an IT instruction.  */
4653           seen_it = insn;
4654           it_count = count >> 1;
4655         }
4656       if ((insn & 0xf800) >= 0xe800)
4657         count++;
4658       else
4659         count = (count + 2) | 1;
4660       /* IT blocks contain at most 4 instructions.  */
4661       if (count >= 8 && !seen_it)
4662         return;
4663     }
4664   /* We found an IT instruction.  */
4665   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
4666   if ((ifthen_state & 0xf) == 0)
4667     ifthen_state = 0;
4668 }
4669
4670 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
4671    mapping symbol.  */
4672
4673 static int
4674 is_mapping_symbol (struct disassemble_info *info, int n,
4675                    enum map_type *map_type)
4676 {
4677   const char *name;
4678
4679   name = bfd_asymbol_name (info->symtab[n]);
4680   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
4681       && (name[2] == 0 || name[2] == '.'))
4682     {
4683       *map_type = ((name[1] == 'a') ? MAP_ARM
4684                    : (name[1] == 't') ? MAP_THUMB
4685                    : MAP_DATA);
4686       return TRUE;
4687     }
4688
4689   return FALSE;
4690 }
4691
4692 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
4693    Returns nonzero if *MAP_TYPE was set.  */
4694
4695 static int
4696 get_map_sym_type (struct disassemble_info *info,
4697                   int n,
4698                   enum map_type *map_type)
4699 {
4700   /* If the symbol is in a different section, ignore it.  */
4701   if (info->section != NULL && info->section != info->symtab[n]->section)
4702     return FALSE;
4703
4704   return is_mapping_symbol (info, n, map_type);
4705 }
4706
4707 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
4708    Returns nonzero if *MAP_TYPE was set.  */
4709
4710 static int
4711 get_sym_code_type (struct disassemble_info *info,
4712                    int n,
4713                    enum map_type *map_type)
4714 {
4715   elf_symbol_type *es;
4716   unsigned int type;
4717
4718   /* If the symbol is in a different section, ignore it.  */
4719   if (info->section != NULL && info->section != info->symtab[n]->section)
4720     return FALSE;
4721
4722   es = *(elf_symbol_type **)(info->symtab + n);
4723   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
4724
4725   /* If the symbol has function type then use that.  */
4726   if (type == STT_FUNC || type == STT_GNU_IFUNC)
4727     {
4728       if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
4729         *map_type = MAP_THUMB;
4730       else
4731         *map_type = MAP_ARM;
4732       return TRUE;
4733     }
4734
4735   return FALSE;
4736 }
4737
4738 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
4739    of the supplied arm_feature_set structure with bitmasks indicating
4740    the support base architectures and coprocessor extensions.
4741
4742    FIXME: This could more efficiently implemented as a constant array,
4743    although it would also be less robust.  */
4744
4745 static void
4746 select_arm_features (unsigned long mach,
4747                      arm_feature_set * features)
4748 {
4749 #undef  ARM_FEATURE
4750 #define ARM_FEATURE(ARCH,CEXT) \
4751   features->core = (ARCH); \
4752   features->coproc = (CEXT) | FPU_FPA; \
4753   return
4754
4755   switch (mach)
4756     {
4757     case bfd_mach_arm_2:       ARM_ARCH_V2;
4758     case bfd_mach_arm_2a:      ARM_ARCH_V2S;
4759     case bfd_mach_arm_3:       ARM_ARCH_V3;
4760     case bfd_mach_arm_3M:      ARM_ARCH_V3M;
4761     case bfd_mach_arm_4:       ARM_ARCH_V4;
4762     case bfd_mach_arm_4T:      ARM_ARCH_V4T;
4763     case bfd_mach_arm_5:       ARM_ARCH_V5;
4764     case bfd_mach_arm_5T:      ARM_ARCH_V5T;
4765     case bfd_mach_arm_5TE:     ARM_ARCH_V5TE;
4766     case bfd_mach_arm_XScale:  ARM_ARCH_XSCALE;
4767     case bfd_mach_arm_ep9312:  ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK | FPU_MAVERICK);
4768     case bfd_mach_arm_iWMMXt:  ARM_ARCH_IWMMXT;
4769     case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2;
4770       /* If the machine type is unknown allow all
4771          architecture types and all extensions.  */
4772     case bfd_mach_arm_unknown: ARM_FEATURE (-1UL, -1UL);
4773     default:
4774       abort ();
4775     }
4776 }
4777
4778
4779 /* NOTE: There are no checks in these routines that
4780    the relevant number of data bytes exist.  */
4781
4782 static int
4783 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
4784 {
4785   unsigned char b[4];
4786   long          given;
4787   int           status;
4788   int           is_thumb = FALSE;
4789   int           is_data = FALSE;
4790   int           little_code;
4791   unsigned int  size = 4;
4792   void          (*printer) (bfd_vma, struct disassemble_info *, long);
4793   bfd_boolean   found = FALSE;
4794   struct arm_private_data *private_data;
4795
4796   if (info->disassembler_options)
4797     {
4798       parse_disassembler_options (info->disassembler_options);
4799
4800       /* To avoid repeated parsing of these options, we remove them here.  */
4801       info->disassembler_options = NULL;
4802     }
4803
4804   /* PR 10288: Control which instructions will be disassembled.  */
4805   if (info->private_data == NULL)
4806     {
4807       static struct arm_private_data private;
4808
4809       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
4810         /* If the user did not use the -m command line switch then default to
4811            disassembling all types of ARM instruction.
4812
4813            The info->mach value has to be ignored as this will be based on
4814            the default archictecture for the target and/or hints in the notes
4815            section, but it will never be greater than the current largest arm
4816            machine value (iWMMXt2), which is only equivalent to the V5TE
4817            architecture.  ARM architectures have advanced beyond the machine
4818            value encoding, and these newer architectures would be ignored if
4819            the machine value was used.
4820
4821            Ie the -m switch is used to restrict which instructions will be
4822            disassembled.  If it is necessary to use the -m switch to tell
4823            objdump that an ARM binary is being disassembled, eg because the
4824            input is a raw binary file, but it is also desired to disassemble
4825            all ARM instructions then use "-marm".  This will select the
4826            "unknown" arm architecture which is compatible with any ARM
4827            instruction.  */
4828           info->mach = bfd_mach_arm_unknown;
4829
4830       /* Compute the architecture bitmask from the machine number.
4831          Note: This assumes that the machine number will not change
4832          during disassembly....  */
4833       select_arm_features (info->mach, & private.features);
4834
4835       private.has_mapping_symbols = -1;
4836       private.last_mapping_sym = -1;
4837       private.last_mapping_addr = 0;
4838
4839       info->private_data = & private;
4840     }
4841
4842   private_data = info->private_data;
4843
4844   /* Decide if our code is going to be little-endian, despite what the
4845      function argument might say.  */
4846   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
4847
4848   /* For ELF, consult the symbol table to determine what kind of code
4849      or data we have.  */
4850   if (info->symtab_size != 0
4851       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
4852     {
4853       bfd_vma addr;
4854       int n, start;
4855       int last_sym = -1;
4856       enum map_type type = MAP_ARM;
4857
4858       /* Start scanning at the start of the function, or wherever
4859          we finished last time.  */
4860       /* PR 14006.  When the address is 0 we are either at the start of the
4861          very first function, or else the first function in a new, unlinked
4862          executable section (eg because uf -ffunction-sections).  Either way
4863          start scanning from the beginning of the symbol table, not where we
4864          left off last time.  */
4865       if (pc == 0)
4866         start = 0;
4867       else
4868         {
4869           start = info->symtab_pos + 1;
4870           if (start < private_data->last_mapping_sym)
4871             start = private_data->last_mapping_sym;
4872         }
4873       found = FALSE;
4874
4875       /* First, look for mapping symbols.  */
4876       if (private_data->has_mapping_symbols != 0)
4877         {
4878           /* Scan up to the location being disassembled.  */
4879           for (n = start; n < info->symtab_size; n++)
4880             {
4881               addr = bfd_asymbol_value (info->symtab[n]);
4882               if (addr > pc)
4883                 break;
4884               if (get_map_sym_type (info, n, &type))
4885                 {
4886                   last_sym = n;
4887                   found = TRUE;
4888                 }
4889             }
4890
4891           if (!found)
4892             {
4893               /* No mapping symbol found at this address.  Look backwards
4894                  for a preceding one.  */
4895               for (n = start - 1; n >= 0; n--)
4896                 {
4897                   if (get_map_sym_type (info, n, &type))
4898                     {
4899                       last_sym = n;
4900                       found = TRUE;
4901                       break;
4902                     }
4903                 }
4904             }
4905
4906           if (found)
4907             private_data->has_mapping_symbols = 1;
4908
4909           /* No mapping symbols were found.  A leading $d may be
4910              omitted for sections which start with data; but for
4911              compatibility with legacy and stripped binaries, only
4912              assume the leading $d if there is at least one mapping
4913              symbol in the file.  */
4914           if (!found && private_data->has_mapping_symbols == -1)
4915             {
4916               /* Look for mapping symbols, in any section.  */
4917               for (n = 0; n < info->symtab_size; n++)
4918                 if (is_mapping_symbol (info, n, &type))
4919                   {
4920                     private_data->has_mapping_symbols = 1;
4921                     break;
4922                   }
4923               if (private_data->has_mapping_symbols == -1)
4924                 private_data->has_mapping_symbols = 0;
4925             }
4926
4927           if (!found && private_data->has_mapping_symbols == 1)
4928             {
4929               type = MAP_DATA;
4930               found = TRUE;
4931             }
4932         }
4933
4934       /* Next search for function symbols to separate ARM from Thumb
4935          in binaries without mapping symbols.  */
4936       if (!found)
4937         {
4938           /* Scan up to the location being disassembled.  */
4939           for (n = start; n < info->symtab_size; n++)
4940             {
4941               addr = bfd_asymbol_value (info->symtab[n]);
4942               if (addr > pc)
4943                 break;
4944               if (get_sym_code_type (info, n, &type))
4945                 {
4946                   last_sym = n;
4947                   found = TRUE;
4948                 }
4949             }
4950
4951           if (!found)
4952             {
4953               /* No mapping symbol found at this address.  Look backwards
4954                  for a preceding one.  */
4955               for (n = start - 1; n >= 0; n--)
4956                 {
4957                   if (get_sym_code_type (info, n, &type))
4958                     {
4959                       last_sym = n;
4960                       found = TRUE;
4961                       break;
4962                     }
4963                 }
4964             }
4965         }
4966
4967       private_data->last_mapping_sym = last_sym;
4968       private_data->last_type = type;
4969       is_thumb = (private_data->last_type == MAP_THUMB);
4970       is_data = (private_data->last_type == MAP_DATA);
4971
4972       /* Look a little bit ahead to see if we should print out
4973          two or four bytes of data.  If there's a symbol,
4974          mapping or otherwise, after two bytes then don't
4975          print more.  */
4976       if (is_data)
4977         {
4978           size = 4 - (pc & 3);
4979           for (n = last_sym + 1; n < info->symtab_size; n++)
4980             {
4981               addr = bfd_asymbol_value (info->symtab[n]);
4982               if (addr > pc
4983                   && (info->section == NULL
4984                       || info->section == info->symtab[n]->section))
4985                 {
4986                   if (addr - pc < size)
4987                     size = addr - pc;
4988                   break;
4989                 }
4990             }
4991           /* If the next symbol is after three bytes, we need to
4992              print only part of the data, so that we can use either
4993              .byte or .short.  */
4994           if (size == 3)
4995             size = (pc & 1) ? 1 : 2;
4996         }
4997     }
4998
4999   if (info->symbols != NULL)
5000     {
5001       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
5002         {
5003           coff_symbol_type * cs;
5004
5005           cs = coffsymbol (*info->symbols);
5006           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
5007                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
5008                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
5009                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
5010                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
5011         }
5012       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
5013                && !found)
5014         {
5015           /* If no mapping symbol has been found then fall back to the type
5016              of the function symbol.  */
5017           elf_symbol_type *  es;
5018           unsigned int       type;
5019
5020           es = *(elf_symbol_type **)(info->symbols);
5021           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
5022
5023           is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
5024                        == ST_BRANCH_TO_THUMB)
5025                       || type == STT_ARM_16BIT);
5026         }
5027     }
5028
5029   if (force_thumb)
5030     is_thumb = TRUE;
5031
5032   if (is_data)
5033     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
5034   else
5035     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
5036
5037   info->bytes_per_line = 4;
5038
5039   /* PR 10263: Disassemble data if requested to do so by the user.  */
5040   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
5041     {
5042       int i;
5043
5044       /* Size was already set above.  */
5045       info->bytes_per_chunk = size;
5046       printer = print_insn_data;
5047
5048       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
5049       given = 0;
5050       if (little)
5051         for (i = size - 1; i >= 0; i--)
5052           given = b[i] | (given << 8);
5053       else
5054         for (i = 0; i < (int) size; i++)
5055           given = b[i] | (given << 8);
5056     }
5057   else if (!is_thumb)
5058     {
5059       /* In ARM mode endianness is a straightforward issue: the instruction
5060          is four bytes long and is either ordered 0123 or 3210.  */
5061       printer = print_insn_arm;
5062       info->bytes_per_chunk = 4;
5063       size = 4;
5064
5065       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
5066       if (little_code)
5067         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
5068       else
5069         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
5070     }
5071   else
5072     {
5073       /* In Thumb mode we have the additional wrinkle of two
5074          instruction lengths.  Fortunately, the bits that determine
5075          the length of the current instruction are always to be found
5076          in the first two bytes.  */
5077       printer = print_insn_thumb16;
5078       info->bytes_per_chunk = 2;
5079       size = 2;
5080
5081       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
5082       if (little_code)
5083         given = (b[0]) | (b[1] << 8);
5084       else
5085         given = (b[1]) | (b[0] << 8);
5086
5087       if (!status)
5088         {
5089           /* These bit patterns signal a four-byte Thumb
5090              instruction.  */
5091           if ((given & 0xF800) == 0xF800
5092               || (given & 0xF800) == 0xF000
5093               || (given & 0xF800) == 0xE800)
5094             {
5095               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
5096               if (little_code)
5097                 given = (b[0]) | (b[1] << 8) | (given << 16);
5098               else
5099                 given = (b[1]) | (b[0] << 8) | (given << 16);
5100
5101               printer = print_insn_thumb32;
5102               size = 4;
5103             }
5104         }
5105
5106       if (ifthen_address != pc)
5107         find_ifthen_state (pc, info, little_code);
5108
5109       if (ifthen_state)
5110         {
5111           if ((ifthen_state & 0xf) == 0x8)
5112             ifthen_next_state = 0;
5113           else
5114             ifthen_next_state = (ifthen_state & 0xe0)
5115                                 | ((ifthen_state & 0xf) << 1);
5116         }
5117     }
5118
5119   if (status)
5120     {
5121       info->memory_error_func (status, pc, info);
5122       return -1;
5123     }
5124   if (info->flags & INSN_HAS_RELOC)
5125     /* If the instruction has a reloc associated with it, then
5126        the offset field in the instruction will actually be the
5127        addend for the reloc.  (We are using REL type relocs).
5128        In such cases, we can ignore the pc when computing
5129        addresses, since the addend is not currently pc-relative.  */
5130     pc = 0;
5131
5132   printer (pc, info, given);
5133
5134   if (is_thumb)
5135     {
5136       ifthen_state = ifthen_next_state;
5137       ifthen_address += size;
5138     }
5139   return size;
5140 }
5141
5142 int
5143 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
5144 {
5145   /* Detect BE8-ness and record it in the disassembler info.  */
5146   if (info->flavour == bfd_target_elf_flavour
5147       && info->section != NULL
5148       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
5149     info->endian_code = BFD_ENDIAN_LITTLE;
5150
5151   return print_insn (pc, info, FALSE);
5152 }
5153
5154 int
5155 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
5156 {
5157   return print_insn (pc, info, TRUE);
5158 }
5159
5160 void
5161 print_arm_disassembler_options (FILE *stream)
5162 {
5163   int i;
5164
5165   fprintf (stream, _("\n\
5166 The following ARM specific disassembler options are supported for use with\n\
5167 the -M switch:\n"));
5168
5169   for (i = NUM_ARM_REGNAMES; i--;)
5170     fprintf (stream, "  reg-names-%s %*c%s\n",
5171              regnames[i].name,
5172              (int)(14 - strlen (regnames[i].name)), ' ',
5173              regnames[i].description);
5174
5175   fprintf (stream, "  force-thumb              Assume all insns are Thumb insns\n");
5176   fprintf (stream, "  no-force-thumb           Examine preceding label to determine an insn's type\n\n");
5177 }