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[PATCH 52/57][Arm][OBJDUMP] Add support for MVE instructions: vadc, vabav, vabd,...
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23 #include "sysdep.h"
24 #include <assert.h>
25
26 #include "disassemble.h"
27 #include "opcode/arm.h"
28 #include "opintl.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
32
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
35 #include "libcoff.h"
36 #include "bfd.h"
37 #include "elf-bfd.h"
38 #include "elf/internal.h"
39 #include "elf/arm.h"
40 #include "mach-o.h"
41
42 /* FIXME: Belongs in global header. */
43 #ifndef strneq
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45 #endif
46
47 /* Cached mapping symbol state. */
48 enum map_type
49 {
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53 };
54
55 struct arm_private_data
56 {
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
68 bfd_vma last_mapping_addr;
69 };
70
71 enum mve_instructions
72 {
73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
211 MVE_VADC,
212 MVE_VABAV,
213 MVE_VABD_FP,
214 MVE_VABD_VEC,
215 MVE_VABS_FP,
216 MVE_VABS_VEC,
217 MVE_VADD_FP_T1,
218 MVE_VADD_FP_T2,
219 MVE_VADD_VEC_T1,
220 MVE_VADD_VEC_T2,
221 MVE_VSBC,
222 MVE_VSUB_FP_T1,
223 MVE_VSUB_FP_T2,
224 MVE_VSUB_VEC_T1,
225 MVE_VSUB_VEC_T2,
226 MVE_NONE
227 };
228
229 enum mve_unpredictable
230 {
231 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
232 */
233 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
234 fcB = 1 (vpt). */
235 UNPRED_R13, /* Unpredictable because r13 (sp) or
236 r15 (sp) used. */
237 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
238 UNPRED_Q_GT_4, /* Unpredictable because
239 vec reg start > 4 (vld4/st4). */
240 UNPRED_Q_GT_6, /* Unpredictable because
241 vec reg start > 6 (vld2/st2). */
242 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
243 and WB bit = 1. */
244 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
245 equal. */
246 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
247 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
248 same. */
249 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
250 size = 1. */
251 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
252 size = 2. */
253 UNPRED_NONE /* No unpredictable behavior. */
254 };
255
256 enum mve_undefined
257 {
258 UNDEF_SIZE, /* undefined size. */
259 UNDEF_SIZE_0, /* undefined because size == 0. */
260 UNDEF_SIZE_2, /* undefined because size == 2. */
261 UNDEF_SIZE_3, /* undefined because size == 3. */
262 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
263 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
264 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
265 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
266 size == 0. */
267 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
268 size == 1. */
269 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
270 UNDEF_VCVT_IMM6, /* imm6 < 32. */
271 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
272 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
273 op1 == (0 or 1). */
274 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
275 op2 == 0 and op1 == (0 or 1). */
276 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
277 in {0xx1, x0x1}. */
278 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
279 UNDEF_NONE /* no undefined behavior. */
280 };
281
282 struct opcode32
283 {
284 arm_feature_set arch; /* Architecture defining this insn. */
285 unsigned long value; /* If arch is 0 then value is a sentinel. */
286 unsigned long mask; /* Recognise insn if (op & mask) == value. */
287 const char * assembler; /* How to disassemble this insn. */
288 };
289
290 /* MVE opcodes. */
291
292 struct mopcode32
293 {
294 arm_feature_set arch; /* Architecture defining this insn. */
295 enum mve_instructions mve_op; /* Specific mve instruction for faster
296 decoding. */
297 unsigned long value; /* If arch is 0 then value is a sentinel. */
298 unsigned long mask; /* Recognise insn if (op & mask) == value. */
299 const char * assembler; /* How to disassemble this insn. */
300 };
301
302 enum isa {
303 ANY,
304 T32,
305 ARM
306 };
307
308
309 /* Shared (between Arm and Thumb mode) opcode. */
310 struct sopcode32
311 {
312 enum isa isa; /* Execution mode instruction availability. */
313 arm_feature_set arch; /* Architecture defining this insn. */
314 unsigned long value; /* If arch is 0 then value is a sentinel. */
315 unsigned long mask; /* Recognise insn if (op & mask) == value. */
316 const char * assembler; /* How to disassemble this insn. */
317 };
318
319 struct opcode16
320 {
321 arm_feature_set arch; /* Architecture defining this insn. */
322 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
323 const char *assembler; /* How to disassemble this insn. */
324 };
325
326 /* print_insn_coprocessor recognizes the following format control codes:
327
328 %% %
329
330 %c print condition code (always bits 28-31 in ARM mode)
331 %q print shifter argument
332 %u print condition code (unconditional in ARM mode,
333 UNPREDICTABLE if not AL in Thumb)
334 %A print address for ldc/stc/ldf/stf instruction
335 %B print vstm/vldm register list
336 %C print vscclrm register list
337 %I print cirrus signed shift immediate: bits 0..3|4..6
338 %J print register for VLDR instruction
339 %K print address for VLDR instruction
340 %F print the COUNT field of a LFM/SFM instruction.
341 %P print floating point precision in arithmetic insn
342 %Q print floating point precision in ldf/stf insn
343 %R print floating point rounding mode
344
345 %<bitfield>c print as a condition code (for vsel)
346 %<bitfield>r print as an ARM register
347 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
348 %<bitfield>ru as %<>r but each u register must be unique.
349 %<bitfield>d print the bitfield in decimal
350 %<bitfield>k print immediate for VFPv3 conversion instruction
351 %<bitfield>x print the bitfield in hex
352 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
353 %<bitfield>f print a floating point constant if >7 else a
354 floating point register
355 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
356 %<bitfield>g print as an iWMMXt 64-bit register
357 %<bitfield>G print as an iWMMXt general purpose or control register
358 %<bitfield>D print as a NEON D register
359 %<bitfield>Q print as a NEON Q register
360 %<bitfield>V print as a NEON D or Q register
361 %<bitfield>E print a quarter-float immediate value
362
363 %y<code> print a single precision VFP reg.
364 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
365 %z<code> print a double precision VFP reg
366 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
367
368 %<bitfield>'c print specified char iff bitfield is all ones
369 %<bitfield>`c print specified char iff bitfield is all zeroes
370 %<bitfield>?ab... select from array of values in big endian order
371
372 %L print as an iWMMXt N/M width field.
373 %Z print the Immediate of a WSHUFH instruction.
374 %l like 'A' except use byte offsets for 'B' & 'H'
375 versions.
376 %i print 5-bit immediate in bits 8,3..0
377 (print "32" when 0)
378 %r print register offset address for wldt/wstr instruction. */
379
380 enum opcode_sentinel_enum
381 {
382 SENTINEL_IWMMXT_START = 1,
383 SENTINEL_IWMMXT_END,
384 SENTINEL_GENERIC_START
385 } opcode_sentinels;
386
387 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
388 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
389 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
390 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
391
392 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
393
394 static const struct sopcode32 coprocessor_opcodes[] =
395 {
396 /* XScale instructions. */
397 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
398 0x0e200010, 0x0fff0ff0,
399 "mia%c\tacc0, %0-3r, %12-15r"},
400 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
401 0x0e280010, 0x0fff0ff0,
402 "miaph%c\tacc0, %0-3r, %12-15r"},
403 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
404 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
405 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
406 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
407 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
408 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
409
410 /* Intel Wireless MMX technology instructions. */
411 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
412 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
413 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
414 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
415 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
416 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
417 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
418 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
419 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
420 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
421 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
422 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
423 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
424 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
425 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
426 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
427 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
428 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
429 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
430 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
431 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
432 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
433 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
434 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
435 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
436 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
437 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
438 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
439 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
440 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
441 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
442 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
443 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
444 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
445 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
446 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
447 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
448 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
449 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
450 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
451 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
452 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
453 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
454 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
455 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
456 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
457 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
458 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
459 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
460 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
461 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
462 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
463 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
464 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
465 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
466 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
467 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
468 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
469 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
470 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
471 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
472 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
473 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
474 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
475 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
476 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
477 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
478 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
479 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
480 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
481 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
482 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
483 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
484 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
485 0x0e800120, 0x0f800ff0,
486 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
487 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
488 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
489 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
490 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
491 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
492 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
493 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
494 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
495 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
496 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
497 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
498 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
499 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
500 0x0e8000a0, 0x0f800ff0,
501 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
502 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
503 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
504 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
505 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
506 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
507 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
508 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
509 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
510 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
511 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
512 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
513 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
514 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
515 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
516 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
517 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
518 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
519 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
520 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
521 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
522 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
523 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
524 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
525 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
526 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
527 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
528 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
529 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
530 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
531 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
532 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
533 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
534 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
535 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
536 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
537 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
538 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
539 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
540 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
541 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
542 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
543 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
544 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
545 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
546 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
547 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
549 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
551 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
552 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
553 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
554 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
555 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
556 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
557 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
558 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
559 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
560 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
561 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
562 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
563 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
564 {ANY, ARM_FEATURE_CORE_LOW (0),
565 SENTINEL_IWMMXT_END, 0, "" },
566
567 /* Floating point coprocessor (FPA) instructions. */
568 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
569 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
570 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
571 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
572 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
573 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
574 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
575 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
576 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
577 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
578 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
579 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
580 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
581 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
582 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
583 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
584 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
585 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
586 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
587 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
588 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
589 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
590 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
591 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
592 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
593 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
594 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
595 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
596 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
597 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
598 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
599 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
600 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
601 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
602 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
603 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
604 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
605 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
606 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
607 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
608 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
609 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
610 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
611 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
612 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
613 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
614 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
615 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
616 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
617 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
618 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
619 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
620 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
621 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
622 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
623 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
624 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
625 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
626 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
627 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
628 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
629 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
630 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
631 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
632 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
633 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
634 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
635 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
636 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
637 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
638 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
639 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
640 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
641 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
642 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
643 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
644 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
645 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
646 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
647 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
648 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
649 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
650 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
651 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
652 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
653 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
654
655 /* Armv8.1-M Mainline instructions. */
656 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
657 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
658 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
659 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
660
661 /* ARMv8-M Mainline Security Extensions instructions. */
662 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
663 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
664 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
665 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
666
667 /* Register load/store. */
668 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
669 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
670 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
671 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
672 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
673 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
674 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
675 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
676 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
677 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
678 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
679 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
680 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
681 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
682 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
683 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
684 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
685 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
686 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
687 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
688 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
689 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
690 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
691 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
692 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
693 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
694 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
695 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
696 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
697 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
698 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
699 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
700 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
701 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
702 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
703 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
704
705 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
706 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
707 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
708 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
709 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
710 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
711 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
712 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
713
714 /* Data transfer between ARM and NEON registers. */
715 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
716 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
717 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
718 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
719 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
720 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
721 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
722 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
723 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
724 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
725 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
726 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
727 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
728 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
729 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
730 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
731 /* Half-precision conversion instructions. */
732 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
733 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
734 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
735 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
736 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
737 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
738 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
739 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
740
741 /* Floating point coprocessor (VFP) instructions. */
742 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
743 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
744 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
745 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
746 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
747 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
748 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
749 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
750 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
751 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
752 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
753 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
754 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
755 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
756 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
757 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
758 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
759 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
760 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
761 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
762 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
763 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
764 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
765 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
766 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
767 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
768 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
769 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
770 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
771 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
772 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
773 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
774 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
775 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
776 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
777 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
778 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
779 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
780 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
781 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
782 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
783 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
784 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
785 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
786 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
787 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
788 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
789 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
790 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
791 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
792 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
793 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
794 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
795 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
796 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
797 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
798 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
799 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
800 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
801 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
802 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
803 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
804 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
805 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
806 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
807 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
808 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
809 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
810 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
811 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
812 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
813 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
814 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
815 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
816 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
817 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
818 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
819 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
820 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
821 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
822 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
824 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
825 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
826 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
827 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
828 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
829 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
830 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
831 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
832 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
833 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
834 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
835 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
836 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
837 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
838 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
839 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
840 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
841 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
842 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
843 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
844 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
845 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
846 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
847 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
849 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
851 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
853 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
854 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
855 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
856 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
857 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
858 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
859 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
860 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
861 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
862 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
863 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
864 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
865 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
866 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
867 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
868 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
869 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
870 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
871 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
872 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
873 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
874 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
875 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
876 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
877 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
878 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
879 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
880
881 /* Cirrus coprocessor instructions. */
882 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
883 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
884 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
885 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
886 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
887 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
888 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
889 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
890 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
891 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
892 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
893 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
894 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
895 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
896 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
897 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
898 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
899 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
900 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
901 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
902 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
903 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
904 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
905 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
906 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
907 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
908 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
909 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
910 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
911 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
912 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
913 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
914 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
915 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
916 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
917 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
918 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
919 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
920 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
921 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
922 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
923 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
924 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
925 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
926 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
927 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
928 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
929 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
930 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
931 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
932 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
933 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
934 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
935 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
936 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
937 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
938 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
939 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
940 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
941 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
942 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
943 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
944 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
945 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
946 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
947 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
948 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
949 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
950 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
951 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
952 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
953 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
954 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
955 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
956 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
957 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
958 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
959 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
960 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
961 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
962 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
963 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
964 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
965 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
966 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
967 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
968 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
969 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
970 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
971 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
972 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
973 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
974 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
975 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
976 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
977 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
978 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
979 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
980 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
981 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
982 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
983 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
984 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
985 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
986 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
987 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
988 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
989 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
990 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
991 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
992 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
993 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
994 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
995 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
996 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
997 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
998 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
999 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1000 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1001 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1002 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1003 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1004 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1005 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1006 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1007 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1008 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1009 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1010 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1011 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1012 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1013 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1014 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1015 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1016 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1017 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1018 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1019 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1020 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1021 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1022 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1023 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1024 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1025 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1026 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1027 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1028 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1029 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1030 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1031 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1032 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1033 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1034 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1035 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1036 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1037 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1038 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1039 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1040 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1041 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1042 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1043 0x0e000600, 0x0ff00f10,
1044 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1045 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1046 0x0e100600, 0x0ff00f10,
1047 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1048 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1049 0x0e200600, 0x0ff00f10,
1050 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1051 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1052 0x0e300600, 0x0ff00f10,
1053 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1054
1055 /* VFP Fused multiply add instructions. */
1056 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1057 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1058 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1059 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1060 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1061 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1062 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1063 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1064 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1065 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1066 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1067 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1068 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1069 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1070 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1071 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1072
1073 /* FP v5. */
1074 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1075 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1076 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1077 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1078 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1079 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1080 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1081 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1082 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1083 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1084 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1085 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1086 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1087 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1088 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1089 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1090 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1091 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1092 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1093 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1094 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1095 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1096 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1097 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1098
1099 /* Generic coprocessor instructions. */
1100 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1101 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1102 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1103 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1104 0x0c500000, 0x0ff00000,
1105 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1106 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1107 0x0e000000, 0x0f000010,
1108 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1109 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1110 0x0e10f010, 0x0f10f010,
1111 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1112 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1113 0x0e100010, 0x0f100010,
1114 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1115 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1116 0x0e000010, 0x0f100010,
1117 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1118 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1119 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1120 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1121 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1122
1123 /* V6 coprocessor instructions. */
1124 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1125 0xfc500000, 0xfff00000,
1126 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1127 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1128 0xfc400000, 0xfff00000,
1129 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1130
1131 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1132 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1133 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1134 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1135 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1136 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1137 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1138 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1139 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1140 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1141 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1142 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1143 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1144 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1145 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1146 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1147 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1148 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1149 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1150 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1151 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1152
1153 /* Dot Product instructions in the space of coprocessor 13. */
1154 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1155 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1156 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1157 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1158
1159 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1160 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1161 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1162 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1163 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1164 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1165 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1166 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1167 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1168 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1169 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1170 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1171 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1172 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1173 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1174 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1175 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1176
1177 /* V5 coprocessor instructions. */
1178 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1179 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1180 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1181 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1182 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1183 0xfe000000, 0xff000010,
1184 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1185 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1186 0xfe000010, 0xff100010,
1187 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1188 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1189 0xfe100010, 0xff100010,
1190 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1191
1192 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1193 cp_num: bit <11:8> == 0b1001.
1194 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1195 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1196 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1197 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1198 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1199 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1200 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1201 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1202 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1203 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1204 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1205 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1206 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1207 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1208 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1209 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1210 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1211 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1212 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1213 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1214 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1215 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1216 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1217 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1218 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1219 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1220 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1221 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1222 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1223 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1224 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1225 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1226 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1227 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1228 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1229 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1230 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1231 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1232 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1233 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1234 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1235 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1236 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1237 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1238 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1239 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1240 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1241 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1242 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1243 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1244 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1245 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1246 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1247 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1248 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1249 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1250 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1251 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1252 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1253 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1254 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1255 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1256 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1257 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1258 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1259 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1260 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1261 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1262 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1263 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1264 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1265
1266 /* ARMv8.3 javascript conversion instruction. */
1267 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1268 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1269
1270 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1271 };
1272
1273 /* Neon opcode table: This does not encode the top byte -- that is
1274 checked by the print_insn_neon routine, as it depends on whether we are
1275 doing thumb32 or arm32 disassembly. */
1276
1277 /* print_insn_neon recognizes the following format control codes:
1278
1279 %% %
1280
1281 %c print condition code
1282 %u print condition code (unconditional in ARM mode,
1283 UNPREDICTABLE if not AL in Thumb)
1284 %A print v{st,ld}[1234] operands
1285 %B print v{st,ld}[1234] any one operands
1286 %C print v{st,ld}[1234] single->all operands
1287 %D print scalar
1288 %E print vmov, vmvn, vorr, vbic encoded constant
1289 %F print vtbl,vtbx register list
1290
1291 %<bitfield>r print as an ARM register
1292 %<bitfield>d print the bitfield in decimal
1293 %<bitfield>e print the 2^N - bitfield in decimal
1294 %<bitfield>D print as a NEON D register
1295 %<bitfield>Q print as a NEON Q register
1296 %<bitfield>R print as a NEON D or Q register
1297 %<bitfield>Sn print byte scaled width limited by n
1298 %<bitfield>Tn print short scaled width limited by n
1299 %<bitfield>Un print long scaled width limited by n
1300
1301 %<bitfield>'c print specified char iff bitfield is all ones
1302 %<bitfield>`c print specified char iff bitfield is all zeroes
1303 %<bitfield>?ab... select from array of values in big endian order. */
1304
1305 static const struct opcode32 neon_opcodes[] =
1306 {
1307 /* Extract. */
1308 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1309 0xf2b00840, 0xffb00850,
1310 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312 0xf2b00000, 0xffb00810,
1313 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1314
1315 /* Data transfer between ARM and NEON registers. */
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1318 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1319 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1325 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1327 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1328
1329 /* Move data element to all lanes. */
1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1331 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1336
1337 /* Table lookup. */
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1342
1343 /* Half-precision conversions. */
1344 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1345 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1346 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1347 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1348
1349 /* NEON fused multiply add instructions. */
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1351 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1352 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1353 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1354 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1355 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1356 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1357 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1358
1359 /* Two registers, miscellaneous. */
1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1361 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1362 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1363 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1365 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1367 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1368 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1369 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1370 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1371 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1372 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1373 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1374 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1375 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1376 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1377 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1378 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1379 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1380 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1381 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1384 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1385 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1387 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1391 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1392 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1393 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403 0xf3b20300, 0xffb30fd0,
1404 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1405 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1406 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1407 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1408 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1410 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1411 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1412 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1414 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452 0xf3bb0600, 0xffbf0e10,
1453 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1454 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1455 0xf3b70600, 0xffbf0e10,
1456 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1457
1458 /* Three registers of the same length. */
1459 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1460 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1461 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1462 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1463 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1464 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1465 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1466 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1467 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1468 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1469 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1470 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1471 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1472 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1474 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1476 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1478 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1479 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1480 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1500 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1503 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1504 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1507 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1508 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1512 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1516 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1520 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1524 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1528 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1532 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1536 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1540 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1544 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1548 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1549 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1550 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1552 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1556 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1560 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1561 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1562 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1564 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1567 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1568 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1574 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf2000b00, 0xff800f10,
1577 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579 0xf2000b10, 0xff800f10,
1580 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588 0xf3000b00, 0xff800f10,
1589 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591 0xf2000000, 0xfe800f10,
1592 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594 0xf2000010, 0xfe800f10,
1595 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597 0xf2000100, 0xfe800f10,
1598 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600 0xf2000200, 0xfe800f10,
1601 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1603 0xf2000210, 0xfe800f10,
1604 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606 0xf2000300, 0xfe800f10,
1607 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609 0xf2000310, 0xfe800f10,
1610 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612 0xf2000400, 0xfe800f10,
1613 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1615 0xf2000410, 0xfe800f10,
1616 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf2000500, 0xfe800f10,
1619 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621 0xf2000510, 0xfe800f10,
1622 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf2000600, 0xfe800f10,
1625 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627 0xf2000610, 0xfe800f10,
1628 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf2000700, 0xfe800f10,
1631 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633 0xf2000710, 0xfe800f10,
1634 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636 0xf2000910, 0xfe800f10,
1637 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1639 0xf2000a00, 0xfe800f10,
1640 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf2000a10, 0xfe800f10,
1643 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1645 0xf3000b10, 0xff800f10,
1646 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1648 0xf3000c10, 0xff800f10,
1649 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1650
1651 /* One register and an immediate value. */
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1655 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1656 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1657 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1659 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1661 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1663 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1665 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1667 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1669 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1671 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1672 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1673 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1674 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1675 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1677 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1678
1679 /* Two registers and a shift amount. */
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1681 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1683 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691 0xf2880950, 0xfeb80fd0,
1692 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714 0xf2900950, 0xfeb00fd0,
1715 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1717 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1718 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1719 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1721 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1722 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1723 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1725 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1727 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1729 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1730 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1731 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1733 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1734 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1735 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1737 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1738 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1739 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1741 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1742 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1743 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1745 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1747 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1751 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1755 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf2a00950, 0xfea00fd0,
1760 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1762 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1763 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1764 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1765 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1766 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1768 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1769 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1770 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1771 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1772 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1774 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1775 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1776 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1777 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1778 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1779 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1780 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1784 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1786 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1788 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1790 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1792 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1798 0xf2a00e10, 0xfea00e90,
1799 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1800 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1801 0xf2a00c10, 0xfea00e90,
1802 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1803
1804 /* Three registers of different lengths. */
1805 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1806 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1807 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1808 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1810 0xf2800400, 0xff800f50,
1811 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1813 0xf2800600, 0xff800f50,
1814 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1815 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1816 0xf2800900, 0xff800f50,
1817 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1819 0xf2800b00, 0xff800f50,
1820 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1821 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1822 0xf2800d00, 0xff800f50,
1823 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1825 0xf3800400, 0xff800f50,
1826 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1827 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1828 0xf3800600, 0xff800f50,
1829 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1831 0xf2800000, 0xfe800f50,
1832 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1833 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1834 0xf2800100, 0xfe800f50,
1835 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1837 0xf2800200, 0xfe800f50,
1838 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1839 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1840 0xf2800300, 0xfe800f50,
1841 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1842 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1843 0xf2800500, 0xfe800f50,
1844 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1845 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1846 0xf2800700, 0xfe800f50,
1847 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1848 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1849 0xf2800800, 0xfe800f50,
1850 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1851 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1852 0xf2800a00, 0xfe800f50,
1853 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1854 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1855 0xf2800c00, 0xfe800f50,
1856 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1857
1858 /* Two registers and a scalar. */
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1863 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1864 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1871 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1872 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1879 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1880 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1881 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1882 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1886 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1888 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1889 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1890 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1891 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1892 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1893 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1894 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1895 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1896 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1897 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1898 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1899 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1900 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1901 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1902 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1903 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1904 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1905 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1906 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1907 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1908 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1910 0xf2800240, 0xfe800f50,
1911 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913 0xf2800640, 0xfe800f50,
1914 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1916 0xf2800a40, 0xfe800f50,
1917 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1919 0xf2800e40, 0xff800f50,
1920 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1922 0xf2800f40, 0xff800f50,
1923 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1925 0xf3800e40, 0xff800f50,
1926 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1928 0xf3800f40, 0xff800f50,
1929 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1930 },
1931
1932 /* Element and structure load/store. */
1933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1934 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1936 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1937 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1938 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1939 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1940 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1942 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1943 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1944 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1945 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1946 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1948 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1949 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1950 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1951 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1952 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1954 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1955 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1956 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1958 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1959 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1960 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1962 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1963 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1964 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1965 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1966 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1967 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1968 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1969 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1970 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1971
1972 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1973 };
1974
1975 /* mve opcode table. */
1976
1977 /* print_insn_mve recognizes the following format control codes:
1978
1979 %% %
1980
1981 %a print '+' or '-' or imm offset in vldr[bhwd] and
1982 vstr[bhwd]
1983 %c print condition code
1984 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1985 %u print 'U' (unsigned) or 'S' for various mve instructions
1986 %i print MVE predicate(s) for vpt and vpst
1987 %m print rounding mode for vcvt and vrint
1988 %n print vector comparison code for predicated instruction
1989 %s print size for various vcvt instructions
1990 %v print vector predicate for instruction in predicated
1991 block
1992 %o print offset scaled for vldr[hwd] and vstr[hwd]
1993 %w print writeback mode for MVE v{st,ld}[24]
1994 %B print v{st,ld}[24] any one operands
1995 %E print vmov, vmvn, vorr, vbic encoded constant
1996 %N print generic index for vmov
1997 %T print bottom ('b') or top ('t') of source register
1998 %X print exchange field in vmla* instructions
1999
2000 %<bitfield>r print as an ARM register
2001 %<bitfield>d print the bitfield in decimal
2002 %<bitfield>A print accumulate or not
2003 %<bitfield>Q print as a MVE Q register
2004 %<bitfield>F print as a MVE S register
2005 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2006 UNPREDICTABLE
2007 %<bitfield>s print size for vector predicate & non VMOV instructions
2008 %<bitfield>I print carry flag or not
2009 %<bitfield>i print immediate for vstr/vldr reg +/- imm
2010 %<bitfield>h print high half of 64-bit destination reg
2011 %<bitfield>k print immediate for vector conversion instruction
2012 %<bitfield>l print low half of 64-bit destination reg
2013 %<bitfield>o print rotate value for vcmul
2014 %<bitfield>u print immediate value for vddup/vdwdup
2015 %<bitfield>x print the bitfield in hex.
2016 */
2017
2018 static const struct mopcode32 mve_opcodes[] =
2019 {
2020 /* MVE. */
2021
2022 {ARM_FEATURE_COPROC (FPU_MVE),
2023 MVE_VPST,
2024 0xfe310f4d, 0xffbf1fff,
2025 "vpst%i"
2026 },
2027
2028 /* Floating point VPT T1. */
2029 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2030 MVE_VPT_FP_T1,
2031 0xee310f00, 0xefb10f50,
2032 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2033 /* Floating point VPT T2. */
2034 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2035 MVE_VPT_FP_T2,
2036 0xee310f40, 0xefb10f50,
2037 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2038
2039 /* Vector VPT T1. */
2040 {ARM_FEATURE_COPROC (FPU_MVE),
2041 MVE_VPT_VEC_T1,
2042 0xfe010f00, 0xff811f51,
2043 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2044 /* Vector VPT T2. */
2045 {ARM_FEATURE_COPROC (FPU_MVE),
2046 MVE_VPT_VEC_T2,
2047 0xfe010f01, 0xff811f51,
2048 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2049 /* Vector VPT T3. */
2050 {ARM_FEATURE_COPROC (FPU_MVE),
2051 MVE_VPT_VEC_T3,
2052 0xfe011f00, 0xff811f50,
2053 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2054 /* Vector VPT T4. */
2055 {ARM_FEATURE_COPROC (FPU_MVE),
2056 MVE_VPT_VEC_T4,
2057 0xfe010f40, 0xff811f70,
2058 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2059 /* Vector VPT T5. */
2060 {ARM_FEATURE_COPROC (FPU_MVE),
2061 MVE_VPT_VEC_T5,
2062 0xfe010f60, 0xff811f70,
2063 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2064 /* Vector VPT T6. */
2065 {ARM_FEATURE_COPROC (FPU_MVE),
2066 MVE_VPT_VEC_T6,
2067 0xfe011f40, 0xff811f50,
2068 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2069
2070 /* Vector VBIC immediate. */
2071 {ARM_FEATURE_COPROC (FPU_MVE),
2072 MVE_VBIC_IMM,
2073 0xef800070, 0xefb81070,
2074 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2075
2076 /* Vector VBIC register. */
2077 {ARM_FEATURE_COPROC (FPU_MVE),
2078 MVE_VBIC_REG,
2079 0xef100150, 0xffb11f51,
2080 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2081
2082 /* Vector VABAV. */
2083 {ARM_FEATURE_COPROC (FPU_MVE),
2084 MVE_VABAV,
2085 0xee800f01, 0xefc10f51,
2086 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2087
2088 /* Vector VABD floating point. */
2089 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2090 MVE_VABD_FP,
2091 0xff200d40, 0xffa11f51,
2092 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2093
2094 /* Vector VABD. */
2095 {ARM_FEATURE_COPROC (FPU_MVE),
2096 MVE_VABD_VEC,
2097 0xef000740, 0xef811f51,
2098 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2099
2100 /* Vector VABS floating point. */
2101 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2102 MVE_VABS_FP,
2103 0xFFB10740, 0xFFB31FD1,
2104 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2105 /* Vector VABS. */
2106 {ARM_FEATURE_COPROC (FPU_MVE),
2107 MVE_VABS_VEC,
2108 0xffb10340, 0xffb31fd1,
2109 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2110
2111 /* Vector VADD floating point T1. */
2112 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2113 MVE_VADD_FP_T1,
2114 0xef000d40, 0xffa11f51,
2115 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2116 /* Vector VADD floating point T2. */
2117 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2118 MVE_VADD_FP_T2,
2119 0xee300f40, 0xefb11f70,
2120 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2121 /* Vector VADD T1. */
2122 {ARM_FEATURE_COPROC (FPU_MVE),
2123 MVE_VADD_VEC_T1,
2124 0xef000840, 0xff811f51,
2125 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2126 /* Vector VADD T2. */
2127 {ARM_FEATURE_COPROC (FPU_MVE),
2128 MVE_VADD_VEC_T2,
2129 0xee010f40, 0xff811f70,
2130 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2131
2132 /* Vector VADDLV. */
2133 {ARM_FEATURE_COPROC (FPU_MVE),
2134 MVE_VADDLV,
2135 0xee890f00, 0xef8f1fd1,
2136 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2137
2138 /* Vector VADDV. */
2139 {ARM_FEATURE_COPROC (FPU_MVE),
2140 MVE_VADDV,
2141 0xeef10f00, 0xeff31fd1,
2142 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2143
2144 /* Vector VADC. */
2145 {ARM_FEATURE_COPROC (FPU_MVE),
2146 MVE_VADC,
2147 0xee300f00, 0xffb10f51,
2148 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2149
2150 /* Vector VCADD floating point. */
2151 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2152 MVE_VCADD_FP,
2153 0xfc800840, 0xfea11f51,
2154 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2155
2156 /* Vector VCADD. */
2157 {ARM_FEATURE_COPROC (FPU_MVE),
2158 MVE_VCADD_VEC,
2159 0xfe000f00, 0xff810f51,
2160 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2161
2162 /* Vector VCMLA. */
2163 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2164 MVE_VCMLA_FP,
2165 0xfc200840, 0xfe211f51,
2166 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2167
2168 /* Vector VCMP floating point T1. */
2169 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2170 MVE_VCMP_FP_T1,
2171 0xee310f00, 0xeff1ef50,
2172 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2173
2174 /* Vector VCMP floating point T2. */
2175 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2176 MVE_VCMP_FP_T2,
2177 0xee310f40, 0xeff1ef50,
2178 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2179
2180 /* Vector VCMP T1. */
2181 {ARM_FEATURE_COPROC (FPU_MVE),
2182 MVE_VCMP_VEC_T1,
2183 0xfe010f00, 0xffc1ff51,
2184 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2185 /* Vector VCMP T2. */
2186 {ARM_FEATURE_COPROC (FPU_MVE),
2187 MVE_VCMP_VEC_T2,
2188 0xfe010f01, 0xffc1ff51,
2189 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2190 /* Vector VCMP T3. */
2191 {ARM_FEATURE_COPROC (FPU_MVE),
2192 MVE_VCMP_VEC_T3,
2193 0xfe011f00, 0xffc1ff50,
2194 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2195 /* Vector VCMP T4. */
2196 {ARM_FEATURE_COPROC (FPU_MVE),
2197 MVE_VCMP_VEC_T4,
2198 0xfe010f40, 0xffc1ff70,
2199 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2200 /* Vector VCMP T5. */
2201 {ARM_FEATURE_COPROC (FPU_MVE),
2202 MVE_VCMP_VEC_T5,
2203 0xfe010f60, 0xffc1ff70,
2204 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2205 /* Vector VCMP T6. */
2206 {ARM_FEATURE_COPROC (FPU_MVE),
2207 MVE_VCMP_VEC_T6,
2208 0xfe011f40, 0xffc1ff50,
2209 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2210
2211 /* Vector VDUP. */
2212 {ARM_FEATURE_COPROC (FPU_MVE),
2213 MVE_VDUP,
2214 0xeea00b10, 0xffb10f5f,
2215 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2216
2217 /* Vector VEOR. */
2218 {ARM_FEATURE_COPROC (FPU_MVE),
2219 MVE_VEOR,
2220 0xff000150, 0xffd11f51,
2221 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2222
2223 /* Vector VFMA, vector * scalar. */
2224 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2225 MVE_VFMA_FP_SCALAR,
2226 0xee310e40, 0xefb11f70,
2227 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2228
2229 /* Vector VFMA floating point. */
2230 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2231 MVE_VFMA_FP,
2232 0xef000c50, 0xffa11f51,
2233 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2234
2235 /* Vector VFMS floating point. */
2236 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2237 MVE_VFMS_FP,
2238 0xef200c50, 0xffa11f51,
2239 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2240
2241 /* Vector VFMAS, vector * scalar. */
2242 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2243 MVE_VFMAS_FP_SCALAR,
2244 0xee311e40, 0xefb11f70,
2245 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2246
2247 /* Vector VHADD T1. */
2248 {ARM_FEATURE_COPROC (FPU_MVE),
2249 MVE_VHADD_T1,
2250 0xef000040, 0xef811f51,
2251 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2252
2253 /* Vector VHADD T2. */
2254 {ARM_FEATURE_COPROC (FPU_MVE),
2255 MVE_VHADD_T2,
2256 0xee000f40, 0xef811f70,
2257 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2258
2259 /* Vector VHSUB T1. */
2260 {ARM_FEATURE_COPROC (FPU_MVE),
2261 MVE_VHSUB_T1,
2262 0xef000240, 0xef811f51,
2263 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2264
2265 /* Vector VHSUB T2. */
2266 {ARM_FEATURE_COPROC (FPU_MVE),
2267 MVE_VHSUB_T2,
2268 0xee001f40, 0xef811f70,
2269 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2270
2271 /* Vector VCMUL. */
2272 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2273 MVE_VCMUL_FP,
2274 0xee300e00, 0xefb10f50,
2275 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2276
2277 /* Vector VDUP. */
2278 {ARM_FEATURE_COPROC (FPU_MVE),
2279 MVE_VDUP,
2280 0xeea00b10, 0xffb10f5f,
2281 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2282
2283 /* Vector VRHADD. */
2284 {ARM_FEATURE_COPROC (FPU_MVE),
2285 MVE_VRHADD,
2286 0xef000140, 0xef811f51,
2287 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2288
2289 /* Vector VCVT. */
2290 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2291 MVE_VCVT_FP_FIX_VEC,
2292 0xef800c50, 0xef801cd1,
2293 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2294
2295 /* Vector VCVT. */
2296 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2297 MVE_VCVT_BETWEEN_FP_INT,
2298 0xffb30640, 0xffb31e51,
2299 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2300
2301 /* Vector VCVT between single and half-precision float, bottom half. */
2302 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2303 MVE_VCVT_FP_HALF_FP,
2304 0xee3f0e01, 0xefbf1fd1,
2305 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2306
2307 /* Vector VCVT between single and half-precision float, top half. */
2308 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2309 MVE_VCVT_FP_HALF_FP,
2310 0xee3f1e01, 0xefbf1fd1,
2311 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2312
2313 /* Vector VCVT. */
2314 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2315 MVE_VCVT_FROM_FP_TO_INT,
2316 0xffb30040, 0xffb31c51,
2317 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2318
2319 /* Vector VDDUP. */
2320 {ARM_FEATURE_COPROC (FPU_MVE),
2321 MVE_VDDUP,
2322 0xee011f6e, 0xff811f7e,
2323 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2324
2325 /* Vector VDWDUP. */
2326 {ARM_FEATURE_COPROC (FPU_MVE),
2327 MVE_VDWDUP,
2328 0xee011f60, 0xff811f70,
2329 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2330
2331 /* Vector VHCADD. */
2332 {ARM_FEATURE_COPROC (FPU_MVE),
2333 MVE_VHCADD,
2334 0xee000f00, 0xff810f51,
2335 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2336
2337 /* Vector VIWDUP. */
2338 {ARM_FEATURE_COPROC (FPU_MVE),
2339 MVE_VIWDUP,
2340 0xee010f60, 0xff811f70,
2341 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2342
2343 /* Vector VIDUP. */
2344 {ARM_FEATURE_COPROC (FPU_MVE),
2345 MVE_VIDUP,
2346 0xee010f6e, 0xff811f7e,
2347 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2348
2349 /* Vector VLD2. */
2350 {ARM_FEATURE_COPROC (FPU_MVE),
2351 MVE_VLD2,
2352 0xfc901e00, 0xff901e5f,
2353 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2354
2355 /* Vector VLD4. */
2356 {ARM_FEATURE_COPROC (FPU_MVE),
2357 MVE_VLD4,
2358 0xfc901e01, 0xff901e1f,
2359 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2360
2361 /* Vector VLDRB gather load. */
2362 {ARM_FEATURE_COPROC (FPU_MVE),
2363 MVE_VLDRB_GATHER_T1,
2364 0xec900e00, 0xefb01e50,
2365 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2366
2367 /* Vector VLDRH gather load. */
2368 {ARM_FEATURE_COPROC (FPU_MVE),
2369 MVE_VLDRH_GATHER_T2,
2370 0xec900e10, 0xefb01e50,
2371 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2372
2373 /* Vector VLDRW gather load. */
2374 {ARM_FEATURE_COPROC (FPU_MVE),
2375 MVE_VLDRW_GATHER_T3,
2376 0xfc900f40, 0xffb01fd0,
2377 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2378
2379 /* Vector VLDRD gather load. */
2380 {ARM_FEATURE_COPROC (FPU_MVE),
2381 MVE_VLDRD_GATHER_T4,
2382 0xec900fd0, 0xefb01fd0,
2383 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2384
2385 /* Vector VLDRW gather load. */
2386 {ARM_FEATURE_COPROC (FPU_MVE),
2387 MVE_VLDRW_GATHER_T5,
2388 0xfd101e00, 0xff111f00,
2389 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2390
2391 /* Vector VLDRD gather load, variant T6. */
2392 {ARM_FEATURE_COPROC (FPU_MVE),
2393 MVE_VLDRD_GATHER_T6,
2394 0xfd101f00, 0xff111f00,
2395 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2396
2397 /* Vector VLDRB. */
2398 {ARM_FEATURE_COPROC (FPU_MVE),
2399 MVE_VLDRB_T1,
2400 0xec100e00, 0xee581e00,
2401 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2402
2403 /* Vector VLDRH. */
2404 {ARM_FEATURE_COPROC (FPU_MVE),
2405 MVE_VLDRH_T2,
2406 0xec180e00, 0xee581e00,
2407 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2408
2409 /* Vector VLDRB unsigned, variant T5. */
2410 {ARM_FEATURE_COPROC (FPU_MVE),
2411 MVE_VLDRB_T5,
2412 0xec101e00, 0xfe101f80,
2413 "vldrb%v.u8\t%13-15,22Q, %d"},
2414
2415 /* Vector VLDRH unsigned, variant T6. */
2416 {ARM_FEATURE_COPROC (FPU_MVE),
2417 MVE_VLDRH_T6,
2418 0xec101e80, 0xfe101f80,
2419 "vldrh%v.u16\t%13-15,22Q, %d"},
2420
2421 /* Vector VLDRW unsigned, variant T7. */
2422 {ARM_FEATURE_COPROC (FPU_MVE),
2423 MVE_VLDRW_T7,
2424 0xec101f00, 0xfe101f80,
2425 "vldrw%v.u32\t%13-15,22Q, %d"},
2426
2427 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2428 opcode aliasing. */
2429 {ARM_FEATURE_COPROC (FPU_MVE),
2430 MVE_VMLALDAV,
2431 0xee801e00, 0xef801f51,
2432 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2433
2434 {ARM_FEATURE_COPROC (FPU_MVE),
2435 MVE_VMLALDAV,
2436 0xee800e00, 0xef801f51,
2437 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2438
2439 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2440 {ARM_FEATURE_COPROC (FPU_MVE),
2441 MVE_VMLADAV_T1,
2442 0xeef00e00, 0xeff01f51,
2443 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2444
2445 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2446 {ARM_FEATURE_COPROC (FPU_MVE),
2447 MVE_VMLADAV_T2,
2448 0xeef00f00, 0xeff11f51,
2449 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2450
2451 /* Vector VMLADAV T1 variant. */
2452 {ARM_FEATURE_COPROC (FPU_MVE),
2453 MVE_VMLADAV_T1,
2454 0xeef01e00, 0xeff01f51,
2455 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2456
2457 /* Vector VMLADAV T2 variant. */
2458 {ARM_FEATURE_COPROC (FPU_MVE),
2459 MVE_VMLADAV_T2,
2460 0xeef01f00, 0xeff11f51,
2461 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2462
2463 /* Vector VMLAS. */
2464 {ARM_FEATURE_COPROC (FPU_MVE),
2465 MVE_VMLAS,
2466 0xee011e40, 0xef811f70,
2467 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2468
2469 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2470 opcode aliasing. */
2471 {ARM_FEATURE_COPROC (FPU_MVE),
2472 MVE_VRMLSLDAVH,
2473 0xfe800e01, 0xff810f51,
2474 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2475
2476 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2477 opcdoe aliasing. */
2478 {ARM_FEATURE_COPROC (FPU_MVE),
2479 MVE_VMLSLDAV,
2480 0xee800e01, 0xff800f51,
2481 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2482
2483 /* Vector VMLSDAV T1 Variant. */
2484 {ARM_FEATURE_COPROC (FPU_MVE),
2485 MVE_VMLSDAV_T1,
2486 0xeef00e01, 0xfff00f51,
2487 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2488
2489 /* Vector VMLSDAV T2 Variant. */
2490 {ARM_FEATURE_COPROC (FPU_MVE),
2491 MVE_VMLSDAV_T2,
2492 0xfef00e01, 0xfff10f51,
2493 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2494
2495 /* Vector VMOV between gpr and half precision register, op == 0. */
2496 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2497 MVE_VMOV_HFP_TO_GP,
2498 0xee000910, 0xfff00f7f,
2499 "vmov.f16\t%7,16-19F, %12-15r"},
2500
2501 /* Vector VMOV between gpr and half precision register, op == 1. */
2502 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2503 MVE_VMOV_HFP_TO_GP,
2504 0xee100910, 0xfff00f7f,
2505 "vmov.f16\t%12-15r, %7,16-19F"},
2506
2507 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2508 MVE_VMOV_GP_TO_VEC_LANE,
2509 0xee000b10, 0xff900f1f,
2510 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2511
2512 /* Vector VORR immediate to vector.
2513 NOTE: MVE_VORR_IMM must appear in the table
2514 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2515 {ARM_FEATURE_COPROC (FPU_MVE),
2516 MVE_VORR_IMM,
2517 0xef800050, 0xefb810f0,
2518 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2519
2520 /* Vector VQSHL T2 Variant.
2521 NOTE: MVE_VQSHL_T2 must appear in the table before
2522 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2523 {ARM_FEATURE_COPROC (FPU_MVE),
2524 MVE_VQSHL_T2,
2525 0xef800750, 0xef801fd1,
2526 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2527
2528 /* Vector VQSHLU T3 Variant
2529 NOTE: MVE_VQSHL_T2 must appear in the table before
2530 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2531
2532 {ARM_FEATURE_COPROC (FPU_MVE),
2533 MVE_VQSHLU_T3,
2534 0xff800650, 0xff801fd1,
2535 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2536
2537 /* Vector VRSHR
2538 NOTE: MVE_VRSHR must appear in the table before
2539 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2540 {ARM_FEATURE_COPROC (FPU_MVE),
2541 MVE_VRSHR,
2542 0xef800250, 0xef801fd1,
2543 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2544
2545 /* Vector VSHL.
2546 NOTE: MVE_VSHL must appear in the table before
2547 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2548 {ARM_FEATURE_COPROC (FPU_MVE),
2549 MVE_VSHL_T1,
2550 0xef800550, 0xff801fd1,
2551 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2552
2553 /* Vector VSHR
2554 NOTE: MVE_VSHR must appear in the table before
2555 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2556 {ARM_FEATURE_COPROC (FPU_MVE),
2557 MVE_VSHR,
2558 0xef800050, 0xef801fd1,
2559 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2560
2561 /* Vector VSLI
2562 NOTE: MVE_VSLI must appear in the table before
2563 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2564 {ARM_FEATURE_COPROC (FPU_MVE),
2565 MVE_VSLI,
2566 0xff800550, 0xff801fd1,
2567 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2568
2569 /* Vector VSRI
2570 NOTE: MVE_VSRI must appear in the table before
2571 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2572 {ARM_FEATURE_COPROC (FPU_MVE),
2573 MVE_VSRI,
2574 0xff800450, 0xff801fd1,
2575 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2576
2577 /* Vector VMOV immediate to vector,
2578 cmode == 11x1 -> VMVN which is UNDEFINED
2579 for such a cmode. */
2580 {ARM_FEATURE_COPROC (FPU_MVE),
2581 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2582
2583 /* Vector VMOV immediate to vector. */
2584 {ARM_FEATURE_COPROC (FPU_MVE),
2585 MVE_VMOV_IMM_TO_VEC,
2586 0xef800050, 0xefb810d0,
2587 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2588
2589 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2590 {ARM_FEATURE_COPROC (FPU_MVE),
2591 MVE_VMOV2_VEC_LANE_TO_GP,
2592 0xec000f00, 0xffb01ff0,
2593 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2594
2595 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2596 {ARM_FEATURE_COPROC (FPU_MVE),
2597 MVE_VMOV2_VEC_LANE_TO_GP,
2598 0xec000f10, 0xffb01ff0,
2599 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2600
2601 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2602 {ARM_FEATURE_COPROC (FPU_MVE),
2603 MVE_VMOV2_GP_TO_VEC_LANE,
2604 0xec100f00, 0xffb01ff0,
2605 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2606
2607 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2608 {ARM_FEATURE_COPROC (FPU_MVE),
2609 MVE_VMOV2_GP_TO_VEC_LANE,
2610 0xec100f10, 0xffb01ff0,
2611 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2612
2613 /* Vector VMOV Vector lane to gpr. */
2614 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2615 MVE_VMOV_VEC_LANE_TO_GP,
2616 0xee100b10, 0xff100f1f,
2617 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2618
2619 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2620 to instruction opcode aliasing. */
2621 {ARM_FEATURE_COPROC (FPU_MVE),
2622 MVE_VSHLL_T1,
2623 0xeea00f40, 0xefa00fd1,
2624 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2625
2626 /* Vector VMOVL long. */
2627 {ARM_FEATURE_COPROC (FPU_MVE),
2628 MVE_VMOVL,
2629 0xeea00f40, 0xefa70fd1,
2630 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2631
2632 /* Vector VMOV and narrow. */
2633 {ARM_FEATURE_COPROC (FPU_MVE),
2634 MVE_VMOVN,
2635 0xfe310e81, 0xffb30fd1,
2636 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2637
2638 /* Floating point move extract. */
2639 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2640 MVE_VMOVX,
2641 0xfeb00a40, 0xffbf0fd0,
2642 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2643
2644 /* Vector VMULL integer. */
2645 {ARM_FEATURE_COPROC (FPU_MVE),
2646 MVE_VMULL_INT,
2647 0xee010e00, 0xef810f51,
2648 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2649
2650 /* Vector VMULL polynomial. */
2651 {ARM_FEATURE_COPROC (FPU_MVE),
2652 MVE_VMULL_POLY,
2653 0xee310e00, 0xefb10f51,
2654 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2655
2656 /* Vector VMVN immediate to vector. */
2657 {ARM_FEATURE_COPROC (FPU_MVE),
2658 MVE_VMVN_IMM,
2659 0xef800070, 0xefb810f0,
2660 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2661
2662 /* Vector VMVN register. */
2663 {ARM_FEATURE_COPROC (FPU_MVE),
2664 MVE_VMVN_REG,
2665 0xffb005c0, 0xffbf1fd1,
2666 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2667
2668 /* Vector VORN, vector bitwise or not. */
2669 {ARM_FEATURE_COPROC (FPU_MVE),
2670 MVE_VORN,
2671 0xef300150, 0xffb11f51,
2672 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2673
2674 /* Vector VORR register. */
2675 {ARM_FEATURE_COPROC (FPU_MVE),
2676 MVE_VORR_REG,
2677 0xef200150, 0xffb11f51,
2678 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2679
2680 /* Vector VQDMULL T1 variant. */
2681 {ARM_FEATURE_COPROC (FPU_MVE),
2682 MVE_VQDMULL_T1,
2683 0xee300f01, 0xefb10f51,
2684 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2685
2686 /* Vector VQDMULL T2 variant. */
2687 {ARM_FEATURE_COPROC (FPU_MVE),
2688 MVE_VQDMULL_T2,
2689 0xee300f60, 0xefb10f70,
2690 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2691
2692 /* Vector VQMOVN. */
2693 {ARM_FEATURE_COPROC (FPU_MVE),
2694 MVE_VQMOVN,
2695 0xee330e01, 0xefb30fd1,
2696 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2697
2698 /* Vector VQMOVUN. */
2699 {ARM_FEATURE_COPROC (FPU_MVE),
2700 MVE_VQMOVUN,
2701 0xee310e81, 0xffb30fd1,
2702 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2703
2704 /* Vector VQDMLADH. */
2705 {ARM_FEATURE_COPROC (FPU_MVE),
2706 MVE_VQDMLADH,
2707 0xee000e00, 0xff810f51,
2708 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2709
2710 /* Vector VQRDMLADH. */
2711 {ARM_FEATURE_COPROC (FPU_MVE),
2712 MVE_VQRDMLADH,
2713 0xee000e01, 0xff810f51,
2714 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2715
2716 /* Vector VQDMLAH. */
2717 {ARM_FEATURE_COPROC (FPU_MVE),
2718 MVE_VQDMLAH,
2719 0xee000e60, 0xef811f70,
2720 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2721
2722 /* Vector VQRDMLAH. */
2723 {ARM_FEATURE_COPROC (FPU_MVE),
2724 MVE_VQRDMLAH,
2725 0xee000e40, 0xef811f70,
2726 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2727
2728 /* Vector VQDMLASH. */
2729 {ARM_FEATURE_COPROC (FPU_MVE),
2730 MVE_VQDMLASH,
2731 0xee001e60, 0xef811f70,
2732 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2733
2734 /* Vector VQRDMLASH. */
2735 {ARM_FEATURE_COPROC (FPU_MVE),
2736 MVE_VQRDMLASH,
2737 0xee001e40, 0xef811f70,
2738 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2739
2740 /* Vector VQDMLSDH. */
2741 {ARM_FEATURE_COPROC (FPU_MVE),
2742 MVE_VQDMLSDH,
2743 0xfe000e00, 0xff810f51,
2744 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2745
2746 /* Vector VQRDMLSDH. */
2747 {ARM_FEATURE_COPROC (FPU_MVE),
2748 MVE_VQRDMLSDH,
2749 0xfe000e01, 0xff810f51,
2750 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2751
2752 /* Vector VQDMULH T1 variant. */
2753 {ARM_FEATURE_COPROC (FPU_MVE),
2754 MVE_VQDMULH_T1,
2755 0xef000b40, 0xff811f51,
2756 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2757
2758 /* Vector VQRDMULH T2 variant. */
2759 {ARM_FEATURE_COPROC (FPU_MVE),
2760 MVE_VQRDMULH_T2,
2761 0xff000b40, 0xff811f51,
2762 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2763
2764 /* Vector VQDMULH T3 variant. */
2765 {ARM_FEATURE_COPROC (FPU_MVE),
2766 MVE_VQDMULH_T3,
2767 0xee010e60, 0xff811f70,
2768 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2769
2770 /* Vector VQRDMULH T4 variant. */
2771 {ARM_FEATURE_COPROC (FPU_MVE),
2772 MVE_VQRDMULH_T4,
2773 0xfe010e60, 0xff811f70,
2774 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2775
2776 /* Vector VQRSHL T1 variant. */
2777 {ARM_FEATURE_COPROC (FPU_MVE),
2778 MVE_VQRSHL_T1,
2779 0xef000550, 0xef811f51,
2780 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2781
2782 /* Vector VQRSHL T2 variant. */
2783 {ARM_FEATURE_COPROC (FPU_MVE),
2784 MVE_VQRSHL_T2,
2785 0xee331ee0, 0xefb31ff0,
2786 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2787
2788 /* Vector VQRSHRN. */
2789 {ARM_FEATURE_COPROC (FPU_MVE),
2790 MVE_VQRSHRN,
2791 0xee800f41, 0xefa00fd1,
2792 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2793
2794 /* Vector VQRSHRUN. */
2795 {ARM_FEATURE_COPROC (FPU_MVE),
2796 MVE_VQRSHRUN,
2797 0xfe800fc0, 0xffa00fd1,
2798 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2799
2800 /* Vector VQSHL T1 Variant. */
2801 {ARM_FEATURE_COPROC (FPU_MVE),
2802 MVE_VQSHL_T1,
2803 0xee311ee0, 0xefb31ff0,
2804 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2805
2806 /* Vector VQSHL T4 Variant. */
2807 {ARM_FEATURE_COPROC (FPU_MVE),
2808 MVE_VQSHL_T4,
2809 0xef000450, 0xef811f51,
2810 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2811
2812 /* Vector VQSHRN. */
2813 {ARM_FEATURE_COPROC (FPU_MVE),
2814 MVE_VQSHRN,
2815 0xee800f40, 0xefa00fd1,
2816 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2817
2818 /* Vector VQSHRUN. */
2819 {ARM_FEATURE_COPROC (FPU_MVE),
2820 MVE_VQSHRUN,
2821 0xee800fc0, 0xffa00fd1,
2822 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2823
2824 /* Vector VRINT floating point. */
2825 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2826 MVE_VRINT_FP,
2827 0xffb20440, 0xffb31c51,
2828 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2829
2830 /* Vector VRMLALDAVH. */
2831 {ARM_FEATURE_COPROC (FPU_MVE),
2832 MVE_VRMLALDAVH,
2833 0xee800f00, 0xef811f51,
2834 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2835
2836 /* Vector VRMLALDAVH. */
2837 {ARM_FEATURE_COPROC (FPU_MVE),
2838 MVE_VRMLALDAVH,
2839 0xee801f00, 0xef811f51,
2840 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2841
2842 /* Vector VRSHL T1 Variant. */
2843 {ARM_FEATURE_COPROC (FPU_MVE),
2844 MVE_VRSHL_T1,
2845 0xef000540, 0xef811f51,
2846 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2847
2848 /* Vector VRSHL T2 Variant. */
2849 {ARM_FEATURE_COPROC (FPU_MVE),
2850 MVE_VRSHL_T2,
2851 0xee331e60, 0xefb31ff0,
2852 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2853
2854 /* Vector VRSHRN. */
2855 {ARM_FEATURE_COPROC (FPU_MVE),
2856 MVE_VRSHRN,
2857 0xfe800fc1, 0xffa00fd1,
2858 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2859
2860 /* Vector VSBC. */
2861 {ARM_FEATURE_COPROC (FPU_MVE),
2862 MVE_VSBC,
2863 0xfe300f00, 0xffb10f51,
2864 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2865
2866 /* Vector VSHL T2 Variant. */
2867 {ARM_FEATURE_COPROC (FPU_MVE),
2868 MVE_VSHL_T2,
2869 0xee311e60, 0xefb31ff0,
2870 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2871
2872 /* Vector VSHL T3 Variant. */
2873 {ARM_FEATURE_COPROC (FPU_MVE),
2874 MVE_VSHL_T3,
2875 0xef000440, 0xef811f51,
2876 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2877
2878 /* Vector VSHLC. */
2879 {ARM_FEATURE_COPROC (FPU_MVE),
2880 MVE_VSHLC,
2881 0xeea00fc0, 0xffa01ff0,
2882 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
2883
2884 /* Vector VSHLL T2 Variant. */
2885 {ARM_FEATURE_COPROC (FPU_MVE),
2886 MVE_VSHLL_T2,
2887 0xee310e01, 0xefb30fd1,
2888 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
2889
2890 /* Vector VSHRN. */
2891 {ARM_FEATURE_COPROC (FPU_MVE),
2892 MVE_VSHRN,
2893 0xee800fc1, 0xffa00fd1,
2894 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2895
2896 /* Vector VST2 no writeback. */
2897 {ARM_FEATURE_COPROC (FPU_MVE),
2898 MVE_VST2,
2899 0xfc801e00, 0xffb01e5f,
2900 "vst2%5d.%7-8s\t%B, [%16-19r]"},
2901
2902 /* Vector VST2 writeback. */
2903 {ARM_FEATURE_COPROC (FPU_MVE),
2904 MVE_VST2,
2905 0xfca01e00, 0xffb01e5f,
2906 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2907
2908 /* Vector VST4 no writeback. */
2909 {ARM_FEATURE_COPROC (FPU_MVE),
2910 MVE_VST4,
2911 0xfc801e01, 0xffb01e1f,
2912 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2913
2914 /* Vector VST4 writeback. */
2915 {ARM_FEATURE_COPROC (FPU_MVE),
2916 MVE_VST4,
2917 0xfca01e01, 0xffb01e1f,
2918 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2919
2920 /* Vector VSTRB scatter store, T1 variant. */
2921 {ARM_FEATURE_COPROC (FPU_MVE),
2922 MVE_VSTRB_SCATTER_T1,
2923 0xec800e00, 0xffb01e50,
2924 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2925
2926 /* Vector VSTRH scatter store, T2 variant. */
2927 {ARM_FEATURE_COPROC (FPU_MVE),
2928 MVE_VSTRH_SCATTER_T2,
2929 0xec800e10, 0xffb01e50,
2930 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2931
2932 /* Vector VSTRW scatter store, T3 variant. */
2933 {ARM_FEATURE_COPROC (FPU_MVE),
2934 MVE_VSTRW_SCATTER_T3,
2935 0xec800e40, 0xffb01e50,
2936 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2937
2938 /* Vector VSTRD scatter store, T4 variant. */
2939 {ARM_FEATURE_COPROC (FPU_MVE),
2940 MVE_VSTRD_SCATTER_T4,
2941 0xec800fd0, 0xffb01fd0,
2942 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2943
2944 /* Vector VSTRW scatter store, T5 variant. */
2945 {ARM_FEATURE_COPROC (FPU_MVE),
2946 MVE_VSTRW_SCATTER_T5,
2947 0xfd001e00, 0xff111f00,
2948 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2949
2950 /* Vector VSTRD scatter store, T6 variant. */
2951 {ARM_FEATURE_COPROC (FPU_MVE),
2952 MVE_VSTRD_SCATTER_T6,
2953 0xfd001f00, 0xff111f00,
2954 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2955
2956 /* Vector VSTRB. */
2957 {ARM_FEATURE_COPROC (FPU_MVE),
2958 MVE_VSTRB_T1,
2959 0xec000e00, 0xfe581e00,
2960 "vstrb%v.%7-8s\t%13-15Q, %d"},
2961
2962 /* Vector VSTRH. */
2963 {ARM_FEATURE_COPROC (FPU_MVE),
2964 MVE_VSTRH_T2,
2965 0xec080e00, 0xfe581e00,
2966 "vstrh%v.%7-8s\t%13-15Q, %d"},
2967
2968 /* Vector VSTRB variant T5. */
2969 {ARM_FEATURE_COPROC (FPU_MVE),
2970 MVE_VSTRB_T5,
2971 0xec001e00, 0xfe101f80,
2972 "vstrb%v.8\t%13-15,22Q, %d"},
2973
2974 /* Vector VSTRH variant T6. */
2975 {ARM_FEATURE_COPROC (FPU_MVE),
2976 MVE_VSTRH_T6,
2977 0xec001e80, 0xfe101f80,
2978 "vstrh%v.16\t%13-15,22Q, %d"},
2979
2980 /* Vector VSTRW variant T7. */
2981 {ARM_FEATURE_COPROC (FPU_MVE),
2982 MVE_VSTRW_T7,
2983 0xec001f00, 0xfe101f80,
2984 "vstrw%v.32\t%13-15,22Q, %d"},
2985
2986 /* Vector VSUB floating point T1 variant. */
2987 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2988 MVE_VSUB_FP_T1,
2989 0xef200d40, 0xffa11f51,
2990 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2991
2992 /* Vector VSUB floating point T2 variant. */
2993 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2994 MVE_VSUB_FP_T2,
2995 0xee301f40, 0xefb11f70,
2996 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2997
2998 /* Vector VSUB T1 variant. */
2999 {ARM_FEATURE_COPROC (FPU_MVE),
3000 MVE_VSUB_VEC_T1,
3001 0xff000840, 0xff811f51,
3002 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3003
3004 /* Vector VSUB T2 variant. */
3005 {ARM_FEATURE_COPROC (FPU_MVE),
3006 MVE_VSUB_VEC_T2,
3007 0xee011f40, 0xff811f70,
3008 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3009
3010 {ARM_FEATURE_CORE_LOW (0),
3011 MVE_NONE,
3012 0x00000000, 0x00000000, 0}
3013 };
3014
3015 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3016 ordered: they must be searched linearly from the top to obtain a correct
3017 match. */
3018
3019 /* print_insn_arm recognizes the following format control codes:
3020
3021 %% %
3022
3023 %a print address for ldr/str instruction
3024 %s print address for ldr/str halfword/signextend instruction
3025 %S like %s but allow UNPREDICTABLE addressing
3026 %b print branch destination
3027 %c print condition code (always bits 28-31)
3028 %m print register mask for ldm/stm instruction
3029 %o print operand2 (immediate or register + shift)
3030 %p print 'p' iff bits 12-15 are 15
3031 %t print 't' iff bit 21 set and bit 24 clear
3032 %B print arm BLX(1) destination
3033 %C print the PSR sub type.
3034 %U print barrier type.
3035 %P print address for pli instruction.
3036
3037 %<bitfield>r print as an ARM register
3038 %<bitfield>T print as an ARM register + 1
3039 %<bitfield>R as %r but r15 is UNPREDICTABLE
3040 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3041 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3042 %<bitfield>d print the bitfield in decimal
3043 %<bitfield>W print the bitfield plus one in decimal
3044 %<bitfield>x print the bitfield in hex
3045 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
3046
3047 %<bitfield>'c print specified char iff bitfield is all ones
3048 %<bitfield>`c print specified char iff bitfield is all zeroes
3049 %<bitfield>?ab... select from array of values in big endian order
3050
3051 %e print arm SMI operand (bits 0..7,8..19).
3052 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
3053 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3054 %R print the SPSR/CPSR or banked register of an MRS. */
3055
3056 static const struct opcode32 arm_opcodes[] =
3057 {
3058 /* ARM instructions. */
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3060 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3062 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3063
3064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3065 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3067 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3069 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3071 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3073 0x00800090, 0x0fa000f0,
3074 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3076 0x00a00090, 0x0fa000f0,
3077 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3078
3079 /* V8.2 RAS extension instructions. */
3080 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3081 0xe320f010, 0xffffffff, "esb"},
3082
3083 /* V8 instructions. */
3084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3085 0x0320f005, 0x0fffffff, "sevl"},
3086 /* Defined in V8 but is in NOP space so available to all arch. */
3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3088 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
3089 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
3090 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3092 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3094 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3096 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3098 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3100 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3102 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3104 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3106 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3108 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3109 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3110 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3111 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3112 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3113 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3114 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3115 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3116 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3117 /* CRC32 instructions. */
3118 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3119 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3120 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3121 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3122 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3123 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3124 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3125 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3126 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3127 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3128 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3129 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3130
3131 /* Privileged Access Never extension instructions. */
3132 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3133 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3134
3135 /* Virtualization Extension instructions. */
3136 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3138
3139 /* Integer Divide Extension instructions. */
3140 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3141 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3142 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3143 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3144
3145 /* MP Extension instructions. */
3146 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3147
3148 /* Speculation Barriers. */
3149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3152
3153 /* V7 instructions. */
3154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3162 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3163
3164 /* ARM V6T2 instructions. */
3165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3166 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3168 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3170 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3172 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3173
3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3175 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3177 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3178
3179 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3180 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3181 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3182 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3184 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3186 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3187
3188 /* ARM Security extension instructions. */
3189 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3190 0x01600070, 0x0ff000f0, "smc%c\t%e"},
3191
3192 /* ARM V6K instructions. */
3193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3194 0xf57ff01f, 0xffffffff, "clrex"},
3195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3196 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3198 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3200 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3202 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3204 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3206 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3207
3208 /* ARMv8.5-A instructions. */
3209 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3210
3211 /* ARM V6K NOP hints. */
3212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3213 0x0320f001, 0x0fffffff, "yield%c"},
3214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3215 0x0320f002, 0x0fffffff, "wfe%c"},
3216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3217 0x0320f003, 0x0fffffff, "wfi%c"},
3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3219 0x0320f004, 0x0fffffff, "sev%c"},
3220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3221 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3222
3223 /* ARM V6 instructions. */
3224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3225 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3227 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3229 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3231 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3233 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3235 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3237 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3239 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3241 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3243 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3245 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3247 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3249 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3251 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3253 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3255 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3257 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3259 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3261 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3263 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3265 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3267 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3269 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3271 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3273 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3275 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3277 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3279 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3281 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3283 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3285 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3287 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3289 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3291 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3293 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3295 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3297 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3299 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3301 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3303 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3305 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3307 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3309 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3311 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3313 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3315 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3317 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3319 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3321 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3323 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3325 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3327 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3329 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3331 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3333 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3335 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3337 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3339 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3341 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3343 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3345 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3347 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3349 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3351 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3353 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3355 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3357 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3359 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3361 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3363 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3365 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3367 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3369 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3371 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3373 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3375 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3377 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3379 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3381 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3383 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3385 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3387 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3389 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3391 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3393 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3395 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3397 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3399 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3401 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3403 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3405 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3407 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3409 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3411 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3413 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3415 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3417 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3419 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3421 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3423 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3425 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3427 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3429 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3431 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3433 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3435 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3437 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3439 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3441 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3443 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3445 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3447 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3449 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3451 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3453 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3455 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3457 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3459 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3461 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3463 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3465 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3467 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
3468
3469 /* V5J instruction. */
3470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3471 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3472
3473 /* V5 Instructions. */
3474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3475 0xe1200070, 0xfff000f0,
3476 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3478 0xfa000000, 0xfe000000, "blx\t%B"},
3479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3480 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3482 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3483
3484 /* V5E "El Segundo" Instructions. */
3485 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3486 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3488 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3490 0xf450f000, 0xfc70f000, "pld\t%a"},
3491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3492 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3494 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3496 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3498 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3499
3500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3501 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3503 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3504
3505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3506 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3508 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3510 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3512 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3513
3514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3515 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3517 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3519 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3521 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3522
3523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3524 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3526 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3527
3528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3529 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3531 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3533 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3535 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
3536
3537 /* ARM Instructions. */
3538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3539 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3540
3541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3542 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3544 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3546 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3548 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3550 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3552 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3553
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3555 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3557 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3559 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3561 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3562
3563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3564 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3566 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3568 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3570 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3571
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3573 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3575 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3577 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3578
3579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3580 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3582 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3584 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3585
3586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3587 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3589 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3591 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3592
3593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3594 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3596 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3598 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3599
3600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3601 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3603 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3605 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3606
3607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3608 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3610 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3612 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3613
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3615 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3617 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3619 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3620
3621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3622 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3624 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3626 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3627
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
3629 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3631 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3633 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3634
3635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3636 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3638 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3640 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3641
3642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3643 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3645 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
3646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3647 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
3648
3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3650 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3652 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3654 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3655
3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3657 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3659 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3661 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3662
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3664 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3666 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3668 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3669
3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3671 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3673 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3675 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3677 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3679 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3681 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3683 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3684
3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3686 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3688 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3690 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3691
3692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3693 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3695 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3697 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3698
3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3700 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
3701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3702 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3703
3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3705 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3706
3707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3708 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3710 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3711
3712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3713 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3715 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3717 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3719 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3721 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3723 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3725 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3727 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3729 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3731 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3733 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3735 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3737 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3739 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3741 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3743 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3745 0x092d0000, 0x0fff0000, "push%c\t%m"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3747 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3749 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3750
3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3752 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3754 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3756 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3758 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3760 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3762 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3764 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3766 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3768 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3770 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3772 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3774 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3776 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3778 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3780 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3782 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3784 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3786 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3788 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3789
3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3791 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3793 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
3794
3795 /* The rest. */
3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3797 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3799 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3800 {ARM_FEATURE_CORE_LOW (0),
3801 0x00000000, 0x00000000, 0}
3802 };
3803
3804 /* print_insn_thumb16 recognizes the following format control codes:
3805
3806 %S print Thumb register (bits 3..5 as high number if bit 6 set)
3807 %D print Thumb register (bits 0..2 as high number if bit 7 set)
3808 %<bitfield>I print bitfield as a signed decimal
3809 (top bit of range being the sign bit)
3810 %N print Thumb register mask (with LR)
3811 %O print Thumb register mask (with PC)
3812 %M print Thumb register mask
3813 %b print CZB's 6-bit unsigned branch destination
3814 %s print Thumb right-shift immediate (6..10; 0 == 32).
3815 %c print the condition code
3816 %C print the condition code, or "s" if not conditional
3817 %x print warning if conditional an not at end of IT block"
3818 %X print "\t; unpredictable <IT:code>" if conditional
3819 %I print IT instruction suffix and operands
3820 %W print Thumb Writeback indicator for LDMIA
3821 %<bitfield>r print bitfield as an ARM register
3822 %<bitfield>d print bitfield as a decimal
3823 %<bitfield>H print (bitfield * 2) as a decimal
3824 %<bitfield>W print (bitfield * 4) as a decimal
3825 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3826 %<bitfield>B print Thumb branch destination (signed displacement)
3827 %<bitfield>c print bitfield as a condition code
3828 %<bitnum>'c print specified char iff bit is one
3829 %<bitnum>?ab print a if bit is one else print b. */
3830
3831 static const struct opcode16 thumb_opcodes[] =
3832 {
3833 /* Thumb instructions. */
3834
3835 /* ARMv8-M Security Extensions instructions. */
3836 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
3837 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
3838
3839 /* ARM V8 instructions. */
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
3841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
3842 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
3843
3844 /* ARM V6K no-argument instructions. */
3845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
3847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
3851
3852 /* ARM V6T2 instructions. */
3853 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3854 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
3855 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3856 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
3857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
3858
3859 /* ARM V6. */
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
3871
3872 /* ARM V5 ISA extends Thumb. */
3873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3874 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
3875 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3877 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
3878 /* ARM V4T ISA (Thumb v1). */
3879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3880 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
3881 /* Format 4. */
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
3883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
3885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
3898 /* format 13 */
3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
3901 /* format 5 */
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
3903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
3906 /* format 14 */
3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
3909 /* format 2 */
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3911 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3913 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3915 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3917 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
3918 /* format 8 */
3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3920 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3922 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3924 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
3925 /* format 7 */
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3927 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3929 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3930 /* format 1 */
3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3933 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
3936 /* format 3 */
3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
3941 /* format 6 */
3942 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3944 0x4800, 0xF800,
3945 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
3946 /* format 9 */
3947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3948 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3950 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3952 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3954 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
3955 /* format 10 */
3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3957 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3959 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
3960 /* format 11 */
3961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3962 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3964 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
3965 /* format 12 */
3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3967 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3969 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
3970 /* format 15 */
3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
3973 /* format 17 */
3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
3975 /* format 16 */
3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
3978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
3979 /* format 18 */
3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
3981
3982 /* The E800 .. FFFF range is unconditionally redirected to the
3983 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3984 are processed via that table. Thus, we can never encounter a
3985 bare "second half of BL/BLX(1)" instruction here. */
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
3987 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3988 };
3989
3990 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
3991 We adopt the convention that hw1 is the high 16 bits of .value and
3992 .mask, hw2 the low 16 bits.
3993
3994 print_insn_thumb32 recognizes the following format control codes:
3995
3996 %% %
3997
3998 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3999 %M print a modified 12-bit immediate (same location)
4000 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4001 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4002 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
4003 %S print a possibly-shifted Rm
4004
4005 %L print address for a ldrd/strd instruction
4006 %a print the address of a plain load/store
4007 %w print the width and signedness of a core load/store
4008 %m print register mask for ldm/stm
4009 %n print register mask for clrm
4010
4011 %E print the lsb and width fields of a bfc/bfi instruction
4012 %F print the lsb and width fields of a sbfx/ubfx instruction
4013 %G print a fallback offset for Branch Future instructions
4014 %W print an offset for BF instruction
4015 %Y print an offset for BFL instruction
4016 %Z print an offset for BFCSEL instruction
4017 %Q print an offset for Low Overhead Loop instructions
4018 %P print an offset for Low Overhead Loop end instructions
4019 %b print a conditional branch offset
4020 %B print an unconditional branch offset
4021 %s print the shift field of an SSAT instruction
4022 %R print the rotation field of an SXT instruction
4023 %U print barrier type.
4024 %P print address for pli instruction.
4025 %c print the condition code
4026 %x print warning if conditional an not at end of IT block"
4027 %X print "\t; unpredictable <IT:code>" if conditional
4028
4029 %<bitfield>d print bitfield in decimal
4030 %<bitfield>D print bitfield plus one in decimal
4031 %<bitfield>W print bitfield*4 in decimal
4032 %<bitfield>r print bitfield as an ARM register
4033 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4034 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4035 %<bitfield>c print bitfield as a condition code
4036
4037 %<bitfield>'c print specified char iff bitfield is all ones
4038 %<bitfield>`c print specified char iff bitfield is all zeroes
4039 %<bitfield>?ab... select from array of values in big endian order
4040
4041 With one exception at the bottom (done because BL and BLX(1) need
4042 to come dead last), this table was machine-sorted first in
4043 decreasing order of number of bits set in the mask, then in
4044 increasing numeric order of mask, then in increasing numeric order
4045 of opcode. This order is not the clearest for a human reader, but
4046 is guaranteed never to catch a special-case bit pattern with a more
4047 general mask, which is important, because this instruction encoding
4048 makes heavy use of special-case bit patterns. */
4049 static const struct opcode32 thumb32_opcodes[] =
4050 {
4051 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4052 instructions. */
4053 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4054 0xf00fe001, 0xffffffff, "lctp%c"},
4055 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4056 0xf02fc001, 0xfffff001, "le\t%P"},
4057 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4058 0xf00fc001, 0xfffff001, "le\tlr, %P"},
4059 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4060 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4061 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4062 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4063 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4064 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4065 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4066 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4067 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4068 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
4069
4070 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4071 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4072 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4073 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4074 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4075 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4076 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4077 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4078 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4079 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4080
4081 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4082 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4083
4084 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4086 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4087 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4088 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4089 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4090 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4091 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4092 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4093 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4094
4095 /* ARM V8.2 RAS extension instructions. */
4096 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
4097 0xf3af8010, 0xffffffff, "esb"},
4098
4099 /* V8 instructions. */
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4101 0xf3af8005, 0xffffffff, "sevl%c.w"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4103 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4105 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4107 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4109 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4111 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4113 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4115 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4117 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4119 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4121 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4123 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4125 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4127 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4129 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4131 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4132
4133 /* CRC32 instructions. */
4134 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4135 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4136 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4137 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4138 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4139 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4140 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4141 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4142 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4143 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4144 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4145 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4146
4147 /* Speculation Barriers. */
4148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4151
4152 /* V7 instructions. */
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4161 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4163 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4164
4165 /* Virtualization Extension instructions. */
4166 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4167 /* We skip ERET as that is SUBS pc, lr, #0. */
4168
4169 /* MP Extension instructions. */
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
4171
4172 /* Security extension instructions. */
4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4174
4175 /* ARMv8.5-A instructions. */
4176 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4177
4178 /* Instructions defined in the basic V6T2 set. */
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4185 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4187
4188 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4189 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4191 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4193 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4195 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4197 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4199 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4201 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4203 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4205 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4207 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4209 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4211 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4213 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4215 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4216 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4217 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4218 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4219 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4221 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4223 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4225 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4227 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4229 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4231 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4233 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4235 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4236 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4237 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4239 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4241 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4243 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4245 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4247 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4249 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4251 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4253 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4255 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4257 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4259 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4261 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4263 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4265 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4267 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4269 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4271 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4273 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4275 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4277 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4279 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4281 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4283 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4285 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4287 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4289 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4291 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4293 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4295 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4297 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4299 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4301 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4303 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4305 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4307 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4309 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4311 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4313 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4315 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4317 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4319 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4321 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4323 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4325 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4327 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4329 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4331 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4333 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4335 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4337 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4339 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4341 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4343 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4344 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4345 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4347 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4349 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4351 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4353 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4355 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4357 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4359 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4361 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4363 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4365 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4367 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4369 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4371 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4373 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4375 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4377 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4379 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4381 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4383 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4385 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4387 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4389 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4391 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4393 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4395 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4397 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4399 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4401 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4403 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4405 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4407 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4409 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4411 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4412 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4413 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4415 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4417 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4419 0xf810f000, 0xff70f000, "pld%c\t%a"},
4420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4421 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4423 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4425 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4427 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4429 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4431 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4433 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4435 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4437 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4439 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4441 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4443 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4445 0xfb100000, 0xfff000c0,
4446 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4448 0xfbc00080, 0xfff000c0,
4449 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4451 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4453 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4455 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
4456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4457 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4459 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4460 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4461 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4463 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4464 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4465 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4467 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4469 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4471 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4473 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4475 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4477 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4479 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4481 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4483 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4485 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4486 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4487 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4489 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4491 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4493 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4495 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4497 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4499 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4501 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4503 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4505 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4507 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4509 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4511 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4513 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4515 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4517 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4519 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4521 0xe9400000, 0xff500000,
4522 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4524 0xe9500000, 0xff500000,
4525 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4527 0xe8600000, 0xff700000,
4528 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4529 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4530 0xe8700000, 0xff700000,
4531 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4533 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4535 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
4536
4537 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
4538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4539 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4541 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4543 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4545 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
4546
4547 /* These have been 32-bit since the invention of Thumb. */
4548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4549 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4551 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
4552
4553 /* Fallback. */
4554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4555 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4556 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4557 };
4558
4559 static const char *const arm_conditional[] =
4560 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
4561 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
4562
4563 static const char *const arm_fp_const[] =
4564 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
4565
4566 static const char *const arm_shift[] =
4567 {"lsl", "lsr", "asr", "ror"};
4568
4569 typedef struct
4570 {
4571 const char *name;
4572 const char *description;
4573 const char *reg_names[16];
4574 }
4575 arm_regname;
4576
4577 static const arm_regname regnames[] =
4578 {
4579 { "reg-names-raw", N_("Select raw register names"),
4580 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
4581 { "reg-names-gcc", N_("Select register names used by GCC"),
4582 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
4583 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
4584 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
4585 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
4586 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
4587 { "reg-names-apcs", N_("Select register names used in the APCS"),
4588 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
4589 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
4590 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
4591 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4592 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
4593 };
4594
4595 static const char *const iwmmxt_wwnames[] =
4596 {"b", "h", "w", "d"};
4597
4598 static const char *const iwmmxt_wwssnames[] =
4599 {"b", "bus", "bc", "bss",
4600 "h", "hus", "hc", "hss",
4601 "w", "wus", "wc", "wss",
4602 "d", "dus", "dc", "dss"
4603 };
4604
4605 static const char *const iwmmxt_regnames[] =
4606 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4607 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4608 };
4609
4610 static const char *const iwmmxt_cregnames[] =
4611 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4612 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4613 };
4614
4615 static const char *const vec_condnames[] =
4616 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4617 };
4618
4619 static const char *const mve_predicatenames[] =
4620 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4621 "eee", "ee", "eet", "e", "ett", "et", "ete"
4622 };
4623
4624 /* Names for 2-bit size field for mve vector isntructions. */
4625 static const char *const mve_vec_sizename[] =
4626 { "8", "16", "32", "64"};
4627
4628 /* Indicates whether we are processing a then predicate,
4629 else predicate or none at all. */
4630 enum vpt_pred_state
4631 {
4632 PRED_NONE,
4633 PRED_THEN,
4634 PRED_ELSE
4635 };
4636
4637 /* Information used to process a vpt block and subsequent instructions. */
4638 struct vpt_block
4639 {
4640 /* Are we in a vpt block. */
4641 bfd_boolean in_vpt_block;
4642
4643 /* Next predicate state if in vpt block. */
4644 enum vpt_pred_state next_pred_state;
4645
4646 /* Mask from vpt/vpst instruction. */
4647 long predicate_mask;
4648
4649 /* Instruction number in vpt block. */
4650 long current_insn_num;
4651
4652 /* Number of instructions in vpt block.. */
4653 long num_pred_insn;
4654 };
4655
4656 static struct vpt_block vpt_block_state =
4657 {
4658 FALSE,
4659 PRED_NONE,
4660 0,
4661 0,
4662 0
4663 };
4664
4665 /* Default to GCC register name set. */
4666 static unsigned int regname_selected = 1;
4667
4668 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
4669 #define arm_regnames regnames[regname_selected].reg_names
4670
4671 static bfd_boolean force_thumb = FALSE;
4672
4673 /* Current IT instruction state. This contains the same state as the IT
4674 bits in the CPSR. */
4675 static unsigned int ifthen_state;
4676 /* IT state for the next instruction. */
4677 static unsigned int ifthen_next_state;
4678 /* The address of the insn for which the IT state is valid. */
4679 static bfd_vma ifthen_address;
4680 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
4681 /* Indicates that the current Conditional state is unconditional or outside
4682 an IT block. */
4683 #define COND_UNCOND 16
4684
4685 \f
4686 /* Functions. */
4687 /* Extract the predicate mask for a VPT or VPST instruction.
4688 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
4689
4690 static long
4691 mve_extract_pred_mask (long given)
4692 {
4693 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
4694 }
4695
4696 /* Return the number of instructions in a MVE predicate block. */
4697 static long
4698 num_instructions_vpt_block (long given)
4699 {
4700 long mask = mve_extract_pred_mask (given);
4701 if (mask == 0)
4702 return 0;
4703
4704 if (mask == 8)
4705 return 1;
4706
4707 if ((mask & 7) == 4)
4708 return 2;
4709
4710 if ((mask & 3) == 2)
4711 return 3;
4712
4713 if ((mask & 1) == 1)
4714 return 4;
4715
4716 return 0;
4717 }
4718
4719 static void
4720 mark_outside_vpt_block (void)
4721 {
4722 vpt_block_state.in_vpt_block = FALSE;
4723 vpt_block_state.next_pred_state = PRED_NONE;
4724 vpt_block_state.predicate_mask = 0;
4725 vpt_block_state.current_insn_num = 0;
4726 vpt_block_state.num_pred_insn = 0;
4727 }
4728
4729 static void
4730 mark_inside_vpt_block (long given)
4731 {
4732 vpt_block_state.in_vpt_block = TRUE;
4733 vpt_block_state.next_pred_state = PRED_THEN;
4734 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
4735 vpt_block_state.current_insn_num = 0;
4736 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
4737 assert (vpt_block_state.num_pred_insn >= 1);
4738 }
4739
4740 static enum vpt_pred_state
4741 invert_next_predicate_state (enum vpt_pred_state astate)
4742 {
4743 if (astate == PRED_THEN)
4744 return PRED_ELSE;
4745 else if (astate == PRED_ELSE)
4746 return PRED_THEN;
4747 else
4748 return PRED_NONE;
4749 }
4750
4751 static enum vpt_pred_state
4752 update_next_predicate_state (void)
4753 {
4754 long pred_mask = vpt_block_state.predicate_mask;
4755 long mask_for_insn = 0;
4756
4757 switch (vpt_block_state.current_insn_num)
4758 {
4759 case 1:
4760 mask_for_insn = 8;
4761 break;
4762
4763 case 2:
4764 mask_for_insn = 4;
4765 break;
4766
4767 case 3:
4768 mask_for_insn = 2;
4769 break;
4770
4771 case 4:
4772 return PRED_NONE;
4773 }
4774
4775 if (pred_mask & mask_for_insn)
4776 return invert_next_predicate_state (vpt_block_state.next_pred_state);
4777 else
4778 return vpt_block_state.next_pred_state;
4779 }
4780
4781 static void
4782 update_vpt_block_state (void)
4783 {
4784 vpt_block_state.current_insn_num++;
4785 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
4786 {
4787 /* No more instructions to process in vpt block. */
4788 mark_outside_vpt_block ();
4789 return;
4790 }
4791
4792 vpt_block_state.next_pred_state = update_next_predicate_state ();
4793 }
4794
4795 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
4796 Returns pointer to following character of the format string and
4797 fills in *VALUEP and *WIDTHP with the extracted value and number of
4798 bits extracted. WIDTHP can be NULL. */
4799
4800 static const char *
4801 arm_decode_bitfield (const char *ptr,
4802 unsigned long insn,
4803 unsigned long *valuep,
4804 int *widthp)
4805 {
4806 unsigned long value = 0;
4807 int width = 0;
4808
4809 do
4810 {
4811 int start, end;
4812 int bits;
4813
4814 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
4815 start = start * 10 + *ptr - '0';
4816 if (*ptr == '-')
4817 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
4818 end = end * 10 + *ptr - '0';
4819 else
4820 end = start;
4821 bits = end - start;
4822 if (bits < 0)
4823 abort ();
4824 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
4825 width += bits + 1;
4826 }
4827 while (*ptr++ == ',');
4828 *valuep = value;
4829 if (widthp)
4830 *widthp = width;
4831 return ptr - 1;
4832 }
4833
4834 static void
4835 arm_decode_shift (long given, fprintf_ftype func, void *stream,
4836 bfd_boolean print_shift)
4837 {
4838 func (stream, "%s", arm_regnames[given & 0xf]);
4839
4840 if ((given & 0xff0) != 0)
4841 {
4842 if ((given & 0x10) == 0)
4843 {
4844 int amount = (given & 0xf80) >> 7;
4845 int shift = (given & 0x60) >> 5;
4846
4847 if (amount == 0)
4848 {
4849 if (shift == 3)
4850 {
4851 func (stream, ", rrx");
4852 return;
4853 }
4854
4855 amount = 32;
4856 }
4857
4858 if (print_shift)
4859 func (stream, ", %s #%d", arm_shift[shift], amount);
4860 else
4861 func (stream, ", #%d", amount);
4862 }
4863 else if ((given & 0x80) == 0x80)
4864 func (stream, "\t; <illegal shifter operand>");
4865 else if (print_shift)
4866 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
4867 arm_regnames[(given & 0xf00) >> 8]);
4868 else
4869 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
4870 }
4871 }
4872
4873 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
4874
4875 static bfd_boolean
4876 is_mve_okay_in_it (enum mve_instructions matched_insn)
4877 {
4878 switch (matched_insn)
4879 {
4880 case MVE_VMOV_GP_TO_VEC_LANE:
4881 case MVE_VMOV2_VEC_LANE_TO_GP:
4882 case MVE_VMOV2_GP_TO_VEC_LANE:
4883 case MVE_VMOV_VEC_LANE_TO_GP:
4884 return TRUE;
4885 default:
4886 return FALSE;
4887 }
4888 }
4889
4890 static bfd_boolean
4891 is_mve_architecture (struct disassemble_info *info)
4892 {
4893 struct arm_private_data *private_data = info->private_data;
4894 arm_feature_set allowed_arches = private_data->features;
4895
4896 arm_feature_set arm_ext_v8_1m_main
4897 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
4898
4899 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
4900 && !ARM_CPU_IS_ANY (allowed_arches))
4901 return TRUE;
4902 else
4903 return FALSE;
4904 }
4905
4906 static bfd_boolean
4907 is_vpt_instruction (long given)
4908 {
4909
4910 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
4911 if ((given & 0x0040e000) == 0)
4912 return FALSE;
4913
4914 /* VPT floating point T1 variant. */
4915 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
4916 /* VPT floating point T2 variant. */
4917 || ((given & 0xefb10f50) == 0xee310f40)
4918 /* VPT vector T1 variant. */
4919 || ((given & 0xff811f51) == 0xfe010f00)
4920 /* VPT vector T2 variant. */
4921 || ((given & 0xff811f51) == 0xfe010f01
4922 && ((given & 0x300000) != 0x300000))
4923 /* VPT vector T3 variant. */
4924 || ((given & 0xff811f50) == 0xfe011f00)
4925 /* VPT vector T4 variant. */
4926 || ((given & 0xff811f70) == 0xfe010f40)
4927 /* VPT vector T5 variant. */
4928 || ((given & 0xff811f70) == 0xfe010f60)
4929 /* VPT vector T6 variant. */
4930 || ((given & 0xff811f50) == 0xfe011f40)
4931 /* VPST vector T variant. */
4932 || ((given & 0xffbf1fff) == 0xfe310f4d))
4933 return TRUE;
4934 else
4935 return FALSE;
4936 }
4937
4938 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
4939 and ending bitfield = END. END must be greater than START. */
4940
4941 static unsigned long
4942 arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
4943 {
4944 int bits = end - start;
4945
4946 if (bits < 0)
4947 abort ();
4948
4949 return ((given >> start) & ((2ul << bits) - 1));
4950 }
4951
4952 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
4953 START:END and START2:END2. END/END2 must be greater than
4954 START/START2. */
4955
4956 static unsigned long
4957 arm_decode_field_multiple (unsigned long given, unsigned int start,
4958 unsigned int end, unsigned int start2,
4959 unsigned int end2)
4960 {
4961 int bits = end - start;
4962 int bits2 = end2 - start2;
4963 unsigned long value = 0;
4964 int width = 0;
4965
4966 if (bits2 < 0)
4967 abort ();
4968
4969 value = arm_decode_field (given, start, end);
4970 width += bits + 1;
4971
4972 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
4973 return value;
4974 }
4975
4976 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
4977 This helps us decode instructions that change mnemonic depending on specific
4978 operand values/encodings. */
4979
4980 static bfd_boolean
4981 is_mve_encoding_conflict (unsigned long given,
4982 enum mve_instructions matched_insn)
4983 {
4984 switch (matched_insn)
4985 {
4986 case MVE_VPST:
4987 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4988 return TRUE;
4989 else
4990 return FALSE;
4991
4992 case MVE_VPT_FP_T1:
4993 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4994 return TRUE;
4995 if ((arm_decode_field (given, 12, 12) == 0)
4996 && (arm_decode_field (given, 0, 0) == 1))
4997 return TRUE;
4998 return FALSE;
4999
5000 case MVE_VPT_FP_T2:
5001 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5002 return TRUE;
5003 if (arm_decode_field (given, 0, 3) == 0xd)
5004 return TRUE;
5005 return FALSE;
5006
5007 case MVE_VPT_VEC_T1:
5008 case MVE_VPT_VEC_T2:
5009 case MVE_VPT_VEC_T3:
5010 case MVE_VPT_VEC_T4:
5011 case MVE_VPT_VEC_T5:
5012 case MVE_VPT_VEC_T6:
5013 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5014 return TRUE;
5015 if (arm_decode_field (given, 20, 21) == 3)
5016 return TRUE;
5017 return FALSE;
5018
5019 case MVE_VCMP_FP_T1:
5020 if ((arm_decode_field (given, 12, 12) == 0)
5021 && (arm_decode_field (given, 0, 0) == 1))
5022 return TRUE;
5023 else
5024 return FALSE;
5025
5026 case MVE_VCMP_FP_T2:
5027 if (arm_decode_field (given, 0, 3) == 0xd)
5028 return TRUE;
5029 else
5030 return FALSE;
5031
5032 case MVE_VADD_VEC_T2:
5033 case MVE_VSUB_VEC_T2:
5034 case MVE_VABAV:
5035 case MVE_VQRSHL_T1:
5036 case MVE_VQSHL_T4:
5037 case MVE_VRSHL_T1:
5038 case MVE_VSHL_T3:
5039 case MVE_VCADD_VEC:
5040 case MVE_VHCADD:
5041 case MVE_VDDUP:
5042 case MVE_VIDUP:
5043 case MVE_VQRDMLADH:
5044 case MVE_VQDMLAH:
5045 case MVE_VQRDMLAH:
5046 case MVE_VQDMLASH:
5047 case MVE_VQRDMLASH:
5048 case MVE_VQDMLSDH:
5049 case MVE_VQRDMLSDH:
5050 case MVE_VQDMULH_T3:
5051 case MVE_VQRDMULH_T4:
5052 case MVE_VQDMLADH:
5053 case MVE_VMLAS:
5054 case MVE_VMULL_INT:
5055 case MVE_VHADD_T2:
5056 case MVE_VHSUB_T2:
5057 case MVE_VCMP_VEC_T1:
5058 case MVE_VCMP_VEC_T2:
5059 case MVE_VCMP_VEC_T3:
5060 case MVE_VCMP_VEC_T4:
5061 case MVE_VCMP_VEC_T5:
5062 case MVE_VCMP_VEC_T6:
5063 if (arm_decode_field (given, 20, 21) == 3)
5064 return TRUE;
5065 else
5066 return FALSE;
5067
5068 case MVE_VLD2:
5069 case MVE_VLD4:
5070 case MVE_VST2:
5071 case MVE_VST4:
5072 if (arm_decode_field (given, 7, 8) == 3)
5073 return TRUE;
5074 else
5075 return FALSE;
5076
5077 case MVE_VSTRB_T1:
5078 case MVE_VSTRH_T2:
5079 if ((arm_decode_field (given, 24, 24) == 0)
5080 && (arm_decode_field (given, 21, 21) == 0))
5081 {
5082 return TRUE;
5083 }
5084 else if ((arm_decode_field (given, 7, 8) == 3))
5085 return TRUE;
5086 else
5087 return FALSE;
5088
5089 case MVE_VSTRB_T5:
5090 case MVE_VSTRH_T6:
5091 case MVE_VSTRW_T7:
5092 if ((arm_decode_field (given, 24, 24) == 0)
5093 && (arm_decode_field (given, 21, 21) == 0))
5094 {
5095 return TRUE;
5096 }
5097 else
5098 return FALSE;
5099
5100 case MVE_VCVT_FP_FIX_VEC:
5101 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5102
5103 case MVE_VBIC_IMM:
5104 case MVE_VORR_IMM:
5105 {
5106 unsigned long cmode = arm_decode_field (given, 8, 11);
5107
5108 if ((cmode & 1) == 0)
5109 return TRUE;
5110 else if ((cmode & 0xc) == 0xc)
5111 return TRUE;
5112 else
5113 return FALSE;
5114 }
5115
5116 case MVE_VMVN_IMM:
5117 {
5118 unsigned long cmode = arm_decode_field (given, 8, 11);
5119
5120 if ((cmode & 9) == 1)
5121 return TRUE;
5122 else if ((cmode & 5) == 1)
5123 return TRUE;
5124 else if ((cmode & 0xe) == 0xe)
5125 return TRUE;
5126 else
5127 return FALSE;
5128 }
5129
5130 case MVE_VMOV_IMM_TO_VEC:
5131 if ((arm_decode_field (given, 5, 5) == 1)
5132 && (arm_decode_field (given, 8, 11) != 0xe))
5133 return TRUE;
5134 else
5135 return FALSE;
5136
5137 case MVE_VMOVL:
5138 {
5139 unsigned long size = arm_decode_field (given, 19, 20);
5140 if ((size == 0) || (size == 3))
5141 return TRUE;
5142 else
5143 return FALSE;
5144 }
5145
5146 case MVE_VQRSHL_T2:
5147 case MVE_VQSHL_T1:
5148 case MVE_VRSHL_T2:
5149 case MVE_VSHL_T2:
5150 case MVE_VSHLL_T2:
5151 case MVE_VADDV:
5152 case MVE_VMOVN:
5153 case MVE_VQMOVUN:
5154 case MVE_VQMOVN:
5155 if (arm_decode_field (given, 18, 19) == 3)
5156 return TRUE;
5157 else
5158 return FALSE;
5159
5160 case MVE_VMLSLDAV:
5161 case MVE_VRMLSLDAVH:
5162 case MVE_VMLALDAV:
5163 case MVE_VADDLV:
5164 if (arm_decode_field (given, 20, 22) == 7)
5165 return TRUE;
5166 else
5167 return FALSE;
5168
5169 case MVE_VRMLALDAVH:
5170 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5171 return TRUE;
5172 else
5173 return FALSE;
5174
5175 case MVE_VDWDUP:
5176 case MVE_VIWDUP:
5177 if ((arm_decode_field (given, 20, 21) == 3)
5178 || (arm_decode_field (given, 1, 3) == 7))
5179 return TRUE;
5180 else
5181 return FALSE;
5182
5183
5184 case MVE_VSHLL_T1:
5185 if (arm_decode_field (given, 16, 18) == 0)
5186 {
5187 unsigned long sz = arm_decode_field (given, 19, 20);
5188
5189 if ((sz == 1) || (sz == 2))
5190 return TRUE;
5191 else
5192 return FALSE;
5193 }
5194 else
5195 return FALSE;
5196
5197 case MVE_VQSHL_T2:
5198 case MVE_VQSHLU_T3:
5199 case MVE_VRSHR:
5200 case MVE_VSHL_T1:
5201 case MVE_VSHR:
5202 case MVE_VSLI:
5203 case MVE_VSRI:
5204 if (arm_decode_field (given, 19, 21) == 0)
5205 return TRUE;
5206 else
5207 return FALSE;
5208
5209 default:
5210 case MVE_VADD_FP_T1:
5211 case MVE_VADD_FP_T2:
5212 case MVE_VADD_VEC_T1:
5213 return FALSE;
5214
5215 }
5216 }
5217
5218 static void
5219 print_mve_vld_str_addr (struct disassemble_info *info,
5220 unsigned long given,
5221 enum mve_instructions matched_insn)
5222 {
5223 void *stream = info->stream;
5224 fprintf_ftype func = info->fprintf_func;
5225
5226 unsigned long p, w, gpr, imm, add, mod_imm;
5227
5228 imm = arm_decode_field (given, 0, 6);
5229 mod_imm = imm;
5230
5231 switch (matched_insn)
5232 {
5233 case MVE_VLDRB_T1:
5234 case MVE_VSTRB_T1:
5235 gpr = arm_decode_field (given, 16, 18);
5236 break;
5237
5238 case MVE_VLDRH_T2:
5239 case MVE_VSTRH_T2:
5240 gpr = arm_decode_field (given, 16, 18);
5241 mod_imm = imm << 1;
5242 break;
5243
5244 case MVE_VLDRH_T6:
5245 case MVE_VSTRH_T6:
5246 gpr = arm_decode_field (given, 16, 19);
5247 mod_imm = imm << 1;
5248 break;
5249
5250 case MVE_VLDRW_T7:
5251 case MVE_VSTRW_T7:
5252 gpr = arm_decode_field (given, 16, 19);
5253 mod_imm = imm << 2;
5254 break;
5255
5256 case MVE_VLDRB_T5:
5257 case MVE_VSTRB_T5:
5258 gpr = arm_decode_field (given, 16, 19);
5259 break;
5260
5261 default:
5262 return;
5263 }
5264
5265 p = arm_decode_field (given, 24, 24);
5266 w = arm_decode_field (given, 21, 21);
5267
5268 add = arm_decode_field (given, 23, 23);
5269
5270 char * add_sub;
5271
5272 /* Don't print anything for '+' as it is implied. */
5273 if (add == 1)
5274 add_sub = "";
5275 else
5276 add_sub = "-";
5277
5278 if (p == 1)
5279 {
5280 /* Offset mode. */
5281 if (w == 0)
5282 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5283 /* Pre-indexed mode. */
5284 else
5285 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5286 }
5287 else if ((p == 0) && (w == 1))
5288 /* Post-index mode. */
5289 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5290 }
5291
5292 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5293 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5294 this encoding is undefined. */
5295
5296 static bfd_boolean
5297 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5298 enum mve_undefined *undefined_code)
5299 {
5300 *undefined_code = UNDEF_NONE;
5301
5302 switch (matched_insn)
5303 {
5304 case MVE_VDUP:
5305 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5306 {
5307 *undefined_code = UNDEF_SIZE_3;
5308 return TRUE;
5309 }
5310 else
5311 return FALSE;
5312
5313 case MVE_VABD_VEC:
5314 case MVE_VADD_VEC_T1:
5315 case MVE_VSUB_VEC_T1:
5316 case MVE_VQDMULH_T1:
5317 case MVE_VQRDMULH_T2:
5318 case MVE_VRHADD:
5319 case MVE_VHADD_T1:
5320 case MVE_VHSUB_T1:
5321 if (arm_decode_field (given, 20, 21) == 3)
5322 {
5323 *undefined_code = UNDEF_SIZE_3;
5324 return TRUE;
5325 }
5326 else
5327 return FALSE;
5328
5329 case MVE_VLDRB_T1:
5330 if (arm_decode_field (given, 7, 8) == 3)
5331 {
5332 *undefined_code = UNDEF_SIZE_3;
5333 return TRUE;
5334 }
5335 else
5336 return FALSE;
5337
5338 case MVE_VLDRH_T2:
5339 if (arm_decode_field (given, 7, 8) <= 1)
5340 {
5341 *undefined_code = UNDEF_SIZE_LE_1;
5342 return TRUE;
5343 }
5344 else
5345 return FALSE;
5346
5347 case MVE_VSTRB_T1:
5348 if ((arm_decode_field (given, 7, 8) == 0))
5349 {
5350 *undefined_code = UNDEF_SIZE_0;
5351 return TRUE;
5352 }
5353 else
5354 return FALSE;
5355
5356 case MVE_VSTRH_T2:
5357 if ((arm_decode_field (given, 7, 8) <= 1))
5358 {
5359 *undefined_code = UNDEF_SIZE_LE_1;
5360 return TRUE;
5361 }
5362 else
5363 return FALSE;
5364
5365 case MVE_VLDRB_GATHER_T1:
5366 if (arm_decode_field (given, 7, 8) == 3)
5367 {
5368 *undefined_code = UNDEF_SIZE_3;
5369 return TRUE;
5370 }
5371 else if ((arm_decode_field (given, 28, 28) == 0)
5372 && (arm_decode_field (given, 7, 8) == 0))
5373 {
5374 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5375 return TRUE;
5376 }
5377 else
5378 return FALSE;
5379
5380 case MVE_VLDRH_GATHER_T2:
5381 if (arm_decode_field (given, 7, 8) == 3)
5382 {
5383 *undefined_code = UNDEF_SIZE_3;
5384 return TRUE;
5385 }
5386 else if ((arm_decode_field (given, 28, 28) == 0)
5387 && (arm_decode_field (given, 7, 8) == 1))
5388 {
5389 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5390 return TRUE;
5391 }
5392 else if (arm_decode_field (given, 7, 8) == 0)
5393 {
5394 *undefined_code = UNDEF_SIZE_0;
5395 return TRUE;
5396 }
5397 else
5398 return FALSE;
5399
5400 case MVE_VLDRW_GATHER_T3:
5401 if (arm_decode_field (given, 7, 8) != 2)
5402 {
5403 *undefined_code = UNDEF_SIZE_NOT_2;
5404 return TRUE;
5405 }
5406 else if (arm_decode_field (given, 28, 28) == 0)
5407 {
5408 *undefined_code = UNDEF_NOT_UNSIGNED;
5409 return TRUE;
5410 }
5411 else
5412 return FALSE;
5413
5414 case MVE_VLDRD_GATHER_T4:
5415 if (arm_decode_field (given, 7, 8) != 3)
5416 {
5417 *undefined_code = UNDEF_SIZE_NOT_3;
5418 return TRUE;
5419 }
5420 else if (arm_decode_field (given, 28, 28) == 0)
5421 {
5422 *undefined_code = UNDEF_NOT_UNSIGNED;
5423 return TRUE;
5424 }
5425 else
5426 return FALSE;
5427
5428 case MVE_VSTRB_SCATTER_T1:
5429 if (arm_decode_field (given, 7, 8) == 3)
5430 {
5431 *undefined_code = UNDEF_SIZE_3;
5432 return TRUE;
5433 }
5434 else
5435 return FALSE;
5436
5437 case MVE_VSTRH_SCATTER_T2:
5438 {
5439 unsigned long size = arm_decode_field (given, 7, 8);
5440 if (size == 3)
5441 {
5442 *undefined_code = UNDEF_SIZE_3;
5443 return TRUE;
5444 }
5445 else if (size == 0)
5446 {
5447 *undefined_code = UNDEF_SIZE_0;
5448 return TRUE;
5449 }
5450 else
5451 return FALSE;
5452 }
5453
5454 case MVE_VSTRW_SCATTER_T3:
5455 if (arm_decode_field (given, 7, 8) != 2)
5456 {
5457 *undefined_code = UNDEF_SIZE_NOT_2;
5458 return TRUE;
5459 }
5460 else
5461 return FALSE;
5462
5463 case MVE_VSTRD_SCATTER_T4:
5464 if (arm_decode_field (given, 7, 8) != 3)
5465 {
5466 *undefined_code = UNDEF_SIZE_NOT_3;
5467 return TRUE;
5468 }
5469 else
5470 return FALSE;
5471
5472 case MVE_VCVT_FP_FIX_VEC:
5473 {
5474 unsigned long imm6 = arm_decode_field (given, 16, 21);
5475 if ((imm6 & 0x20) == 0)
5476 {
5477 *undefined_code = UNDEF_VCVT_IMM6;
5478 return TRUE;
5479 }
5480
5481 if ((arm_decode_field (given, 9, 9) == 0)
5482 && ((imm6 & 0x30) == 0x20))
5483 {
5484 *undefined_code = UNDEF_VCVT_FSI_IMM6;
5485 return TRUE;
5486 }
5487
5488 return FALSE;
5489 }
5490
5491 case MVE_VABS_FP:
5492 case MVE_VCVT_BETWEEN_FP_INT:
5493 case MVE_VCVT_FROM_FP_TO_INT:
5494 {
5495 unsigned long size = arm_decode_field (given, 18, 19);
5496 if (size == 0)
5497 {
5498 *undefined_code = UNDEF_SIZE_0;
5499 return TRUE;
5500 }
5501 else if (size == 3)
5502 {
5503 *undefined_code = UNDEF_SIZE_3;
5504 return TRUE;
5505 }
5506 else
5507 return FALSE;
5508 }
5509
5510 case MVE_VMOV_VEC_LANE_TO_GP:
5511 {
5512 unsigned long op1 = arm_decode_field (given, 21, 22);
5513 unsigned long op2 = arm_decode_field (given, 5, 6);
5514 unsigned long u = arm_decode_field (given, 23, 23);
5515
5516 if ((op2 == 0) && (u == 1))
5517 {
5518 if ((op1 == 0) || (op1 == 1))
5519 {
5520 *undefined_code = UNDEF_BAD_U_OP1_OP2;
5521 return TRUE;
5522 }
5523 else
5524 return FALSE;
5525 }
5526 else if (op2 == 2)
5527 {
5528 if ((op1 == 0) || (op1 == 1))
5529 {
5530 *undefined_code = UNDEF_BAD_OP1_OP2;
5531 return TRUE;
5532 }
5533 else
5534 return FALSE;
5535 }
5536
5537 return FALSE;
5538 }
5539
5540 case MVE_VMOV_GP_TO_VEC_LANE:
5541 if (arm_decode_field (given, 5, 6) == 2)
5542 {
5543 unsigned long op1 = arm_decode_field (given, 21, 22);
5544 if ((op1 == 0) || (op1 == 1))
5545 {
5546 *undefined_code = UNDEF_BAD_OP1_OP2;
5547 return TRUE;
5548 }
5549 else
5550 return FALSE;
5551 }
5552 else
5553 return FALSE;
5554
5555 case MVE_VMOV_IMM_TO_VEC:
5556 if (arm_decode_field (given, 5, 5) == 0)
5557 {
5558 unsigned long cmode = arm_decode_field (given, 8, 11);
5559
5560 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
5561 {
5562 *undefined_code = UNDEF_OP_0_BAD_CMODE;
5563 return TRUE;
5564 }
5565 else
5566 return FALSE;
5567 }
5568 else
5569 return FALSE;
5570
5571 case MVE_VSHLL_T2:
5572 case MVE_VMOVN:
5573 if (arm_decode_field (given, 18, 19) == 2)
5574 {
5575 *undefined_code = UNDEF_SIZE_2;
5576 return TRUE;
5577 }
5578 else
5579 return FALSE;
5580
5581 case MVE_VRMLALDAVH:
5582 case MVE_VMLADAV_T1:
5583 case MVE_VMLADAV_T2:
5584 case MVE_VMLALDAV:
5585 if ((arm_decode_field (given, 28, 28) == 1)
5586 && (arm_decode_field (given, 12, 12) == 1))
5587 {
5588 *undefined_code = UNDEF_XCHG_UNS;
5589 return TRUE;
5590 }
5591 else
5592 return FALSE;
5593
5594 case MVE_VQSHRN:
5595 case MVE_VQSHRUN:
5596 case MVE_VSHLL_T1:
5597 case MVE_VSHRN:
5598 {
5599 unsigned long sz = arm_decode_field (given, 19, 20);
5600 if (sz == 1)
5601 return FALSE;
5602 else if ((sz & 2) == 2)
5603 return FALSE;
5604 else
5605 {
5606 *undefined_code = UNDEF_SIZE;
5607 return TRUE;
5608 }
5609 }
5610 break;
5611
5612 case MVE_VQSHL_T2:
5613 case MVE_VQSHLU_T3:
5614 case MVE_VRSHR:
5615 case MVE_VSHL_T1:
5616 case MVE_VSHR:
5617 case MVE_VSLI:
5618 case MVE_VSRI:
5619 {
5620 unsigned long sz = arm_decode_field (given, 19, 21);
5621 if ((sz & 7) == 1)
5622 return FALSE;
5623 else if ((sz & 6) == 2)
5624 return FALSE;
5625 else if ((sz & 4) == 4)
5626 return FALSE;
5627 else
5628 {
5629 *undefined_code = UNDEF_SIZE;
5630 return TRUE;
5631 }
5632 }
5633
5634 case MVE_VQRSHRN:
5635 case MVE_VQRSHRUN:
5636 if (arm_decode_field (given, 19, 20) == 0)
5637 {
5638 *undefined_code = UNDEF_SIZE_0;
5639 return TRUE;
5640 }
5641 else
5642 return FALSE;
5643
5644 case MVE_VABS_VEC:
5645 if (arm_decode_field (given, 18, 19) == 3)
5646 {
5647 *undefined_code = UNDEF_SIZE_3;
5648 return TRUE;
5649 }
5650 else
5651 return FALSE;
5652
5653 default:
5654 return FALSE;
5655 }
5656 }
5657
5658 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
5659 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
5660 why this encoding is unpredictable. */
5661
5662 static bfd_boolean
5663 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
5664 enum mve_unpredictable *unpredictable_code)
5665 {
5666 *unpredictable_code = UNPRED_NONE;
5667
5668 switch (matched_insn)
5669 {
5670 case MVE_VCMP_FP_T2:
5671 case MVE_VPT_FP_T2:
5672 if ((arm_decode_field (given, 12, 12) == 0)
5673 && (arm_decode_field (given, 5, 5) == 1))
5674 {
5675 *unpredictable_code = UNPRED_FCA_0_FCB_1;
5676 return TRUE;
5677 }
5678 else
5679 return FALSE;
5680
5681 case MVE_VPT_VEC_T4:
5682 case MVE_VPT_VEC_T5:
5683 case MVE_VPT_VEC_T6:
5684 case MVE_VCMP_VEC_T4:
5685 case MVE_VCMP_VEC_T5:
5686 case MVE_VCMP_VEC_T6:
5687 if (arm_decode_field (given, 0, 3) == 0xd)
5688 {
5689 *unpredictable_code = UNPRED_R13;
5690 return TRUE;
5691 }
5692 else
5693 return FALSE;
5694
5695 case MVE_VDUP:
5696 {
5697 unsigned long gpr = arm_decode_field (given, 12, 15);
5698 if (gpr == 0xd)
5699 {
5700 *unpredictable_code = UNPRED_R13;
5701 return TRUE;
5702 }
5703 else if (gpr == 0xf)
5704 {
5705 *unpredictable_code = UNPRED_R15;
5706 return TRUE;
5707 }
5708
5709 return FALSE;
5710 }
5711
5712 case MVE_VADD_FP_T2:
5713 case MVE_VSUB_FP_T2:
5714 case MVE_VADD_VEC_T2:
5715 case MVE_VSUB_VEC_T2:
5716 case MVE_VQRSHL_T2:
5717 case MVE_VQSHL_T1:
5718 case MVE_VRSHL_T2:
5719 case MVE_VSHL_T2:
5720 case MVE_VSHLC:
5721 case MVE_VQDMLAH:
5722 case MVE_VQRDMLAH:
5723 case MVE_VQDMLASH:
5724 case MVE_VQRDMLASH:
5725 case MVE_VQDMULH_T3:
5726 case MVE_VQRDMULH_T4:
5727 case MVE_VMLAS:
5728 case MVE_VFMA_FP_SCALAR:
5729 case MVE_VFMAS_FP_SCALAR:
5730 case MVE_VHADD_T2:
5731 case MVE_VHSUB_T2:
5732 {
5733 unsigned long gpr = arm_decode_field (given, 0, 3);
5734 if (gpr == 0xd)
5735 {
5736 *unpredictable_code = UNPRED_R13;
5737 return TRUE;
5738 }
5739 else if (gpr == 0xf)
5740 {
5741 *unpredictable_code = UNPRED_R15;
5742 return TRUE;
5743 }
5744
5745 return FALSE;
5746 }
5747
5748 case MVE_VLD2:
5749 case MVE_VST2:
5750 {
5751 unsigned long rn = arm_decode_field (given, 16, 19);
5752
5753 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5754 {
5755 *unpredictable_code = UNPRED_R13_AND_WB;
5756 return TRUE;
5757 }
5758
5759 if (rn == 0xf)
5760 {
5761 *unpredictable_code = UNPRED_R15;
5762 return TRUE;
5763 }
5764
5765 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
5766 {
5767 *unpredictable_code = UNPRED_Q_GT_6;
5768 return TRUE;
5769 }
5770 else
5771 return FALSE;
5772 }
5773
5774 case MVE_VLD4:
5775 case MVE_VST4:
5776 {
5777 unsigned long rn = arm_decode_field (given, 16, 19);
5778
5779 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5780 {
5781 *unpredictable_code = UNPRED_R13_AND_WB;
5782 return TRUE;
5783 }
5784
5785 if (rn == 0xf)
5786 {
5787 *unpredictable_code = UNPRED_R15;
5788 return TRUE;
5789 }
5790
5791 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
5792 {
5793 *unpredictable_code = UNPRED_Q_GT_4;
5794 return TRUE;
5795 }
5796 else
5797 return FALSE;
5798 }
5799
5800 case MVE_VLDRB_T5:
5801 case MVE_VLDRH_T6:
5802 case MVE_VLDRW_T7:
5803 case MVE_VSTRB_T5:
5804 case MVE_VSTRH_T6:
5805 case MVE_VSTRW_T7:
5806 {
5807 unsigned long rn = arm_decode_field (given, 16, 19);
5808
5809 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5810 {
5811 *unpredictable_code = UNPRED_R13_AND_WB;
5812 return TRUE;
5813 }
5814 else if (rn == 0xf)
5815 {
5816 *unpredictable_code = UNPRED_R15;
5817 return TRUE;
5818 }
5819 else
5820 return FALSE;
5821 }
5822
5823 case MVE_VLDRB_GATHER_T1:
5824 if (arm_decode_field (given, 0, 0) == 1)
5825 {
5826 *unpredictable_code = UNPRED_OS;
5827 return TRUE;
5828 }
5829
5830 /* fall through. */
5831 /* To handle common code with T2-T4 variants. */
5832 case MVE_VLDRH_GATHER_T2:
5833 case MVE_VLDRW_GATHER_T3:
5834 case MVE_VLDRD_GATHER_T4:
5835 {
5836 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5837 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5838
5839 if (qd == qm)
5840 {
5841 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
5842 return TRUE;
5843 }
5844
5845 if (arm_decode_field (given, 16, 19) == 0xf)
5846 {
5847 *unpredictable_code = UNPRED_R15;
5848 return TRUE;
5849 }
5850
5851 return FALSE;
5852 }
5853
5854 case MVE_VLDRW_GATHER_T5:
5855 case MVE_VLDRD_GATHER_T6:
5856 {
5857 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5858 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
5859
5860 if (qd == qm)
5861 {
5862 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
5863 return TRUE;
5864 }
5865 else
5866 return FALSE;
5867 }
5868
5869 case MVE_VSTRB_SCATTER_T1:
5870 if (arm_decode_field (given, 16, 19) == 0xf)
5871 {
5872 *unpredictable_code = UNPRED_R15;
5873 return TRUE;
5874 }
5875 else if (arm_decode_field (given, 0, 0) == 1)
5876 {
5877 *unpredictable_code = UNPRED_OS;
5878 return TRUE;
5879 }
5880 else
5881 return FALSE;
5882
5883 case MVE_VSTRH_SCATTER_T2:
5884 case MVE_VSTRW_SCATTER_T3:
5885 case MVE_VSTRD_SCATTER_T4:
5886 if (arm_decode_field (given, 16, 19) == 0xf)
5887 {
5888 *unpredictable_code = UNPRED_R15;
5889 return TRUE;
5890 }
5891 else
5892 return FALSE;
5893
5894 case MVE_VMOV2_VEC_LANE_TO_GP:
5895 case MVE_VMOV2_GP_TO_VEC_LANE:
5896 case MVE_VCVT_BETWEEN_FP_INT:
5897 case MVE_VCVT_FROM_FP_TO_INT:
5898 {
5899 unsigned long rt = arm_decode_field (given, 0, 3);
5900 unsigned long rt2 = arm_decode_field (given, 16, 19);
5901
5902 if ((rt == 0xd) || (rt2 == 0xd))
5903 {
5904 *unpredictable_code = UNPRED_R13;
5905 return TRUE;
5906 }
5907 else if ((rt == 0xf) || (rt2 == 0xf))
5908 {
5909 *unpredictable_code = UNPRED_R15;
5910 return TRUE;
5911 }
5912 else if (rt == rt2)
5913 {
5914 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
5915 return TRUE;
5916 }
5917
5918 return FALSE;
5919 }
5920
5921 case MVE_VABAV:
5922 case MVE_VMOV_HFP_TO_GP:
5923 case MVE_VMOV_GP_TO_VEC_LANE:
5924 case MVE_VMOV_VEC_LANE_TO_GP:
5925 {
5926 unsigned long rda = arm_decode_field (given, 12, 15);
5927 if (rda == 0xd)
5928 {
5929 *unpredictable_code = UNPRED_R13;
5930 return TRUE;
5931 }
5932 else if (rda == 0xf)
5933 {
5934 *unpredictable_code = UNPRED_R15;
5935 return TRUE;
5936 }
5937
5938 return FALSE;
5939 }
5940
5941 case MVE_VQRDMLADH:
5942 case MVE_VQDMLSDH:
5943 case MVE_VQRDMLSDH:
5944 case MVE_VQDMLADH:
5945 case MVE_VMULL_INT:
5946 {
5947 unsigned long Qd;
5948 unsigned long Qm;
5949 unsigned long Qn;
5950
5951 if (arm_decode_field (given, 20, 21) == 2)
5952 {
5953 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5954 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5955 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5956
5957 if ((Qd == Qn) || (Qd == Qm))
5958 {
5959 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
5960 return TRUE;
5961 }
5962 else
5963 return FALSE;
5964 }
5965 else
5966 return FALSE;
5967 }
5968
5969 case MVE_VCMUL_FP:
5970 case MVE_VQDMULL_T1:
5971 {
5972 unsigned long Qd;
5973 unsigned long Qm;
5974 unsigned long Qn;
5975
5976 if (arm_decode_field (given, 28, 28) == 1)
5977 {
5978 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5979 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5980 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5981
5982 if ((Qd == Qn) || (Qd == Qm))
5983 {
5984 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5985 return TRUE;
5986 }
5987 else
5988 return FALSE;
5989 }
5990 else
5991 return FALSE;
5992 }
5993
5994 case MVE_VQDMULL_T2:
5995 {
5996 unsigned long gpr = arm_decode_field (given, 0, 3);
5997 if (gpr == 0xd)
5998 {
5999 *unpredictable_code = UNPRED_R13;
6000 return TRUE;
6001 }
6002 else if (gpr == 0xf)
6003 {
6004 *unpredictable_code = UNPRED_R15;
6005 return TRUE;
6006 }
6007
6008 if (arm_decode_field (given, 28, 28) == 1)
6009 {
6010 unsigned long Qd
6011 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6012 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6013
6014 if ((Qd == Qn))
6015 {
6016 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6017 return TRUE;
6018 }
6019 else
6020 return FALSE;
6021 }
6022
6023 return FALSE;
6024 }
6025
6026 case MVE_VMLSLDAV:
6027 case MVE_VRMLSLDAVH:
6028 case MVE_VMLALDAV:
6029 case MVE_VADDLV:
6030 if (arm_decode_field (given, 20, 22) == 6)
6031 {
6032 *unpredictable_code = UNPRED_R13;
6033 return TRUE;
6034 }
6035 else
6036 return FALSE;
6037
6038 case MVE_VDWDUP:
6039 case MVE_VIWDUP:
6040 if (arm_decode_field (given, 1, 3) == 6)
6041 {
6042 *unpredictable_code = UNPRED_R13;
6043 return TRUE;
6044 }
6045 else
6046 return FALSE;
6047
6048 case MVE_VCADD_VEC:
6049 case MVE_VHCADD:
6050 {
6051 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6052 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6053 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6054 {
6055 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6056 return TRUE;
6057 }
6058 else
6059 return FALSE;
6060 }
6061
6062 case MVE_VCADD_FP:
6063 {
6064 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6065 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6066 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6067 {
6068 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6069 return TRUE;
6070 }
6071 else
6072 return FALSE;
6073 }
6074
6075 case MVE_VCMLA_FP:
6076 {
6077 unsigned long Qda;
6078 unsigned long Qm;
6079 unsigned long Qn;
6080
6081 if (arm_decode_field (given, 20, 20) == 1)
6082 {
6083 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6084 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6085 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6086
6087 if ((Qda == Qn) || (Qda == Qm))
6088 {
6089 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6090 return TRUE;
6091 }
6092 else
6093 return FALSE;
6094 }
6095 else
6096 return FALSE;
6097
6098 }
6099
6100 default:
6101 return FALSE;
6102 }
6103 }
6104
6105 static void
6106 print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6107 {
6108 unsigned long op1 = arm_decode_field (given, 21, 22);
6109 unsigned long op2 = arm_decode_field (given, 5, 6);
6110 unsigned long h = arm_decode_field (given, 16, 16);
6111 unsigned long index, esize, targetBeat, idx;
6112 void *stream = info->stream;
6113 fprintf_ftype func = info->fprintf_func;
6114
6115 if ((op1 & 0x2) == 0x2)
6116 {
6117 index = op2;
6118 esize = 8;
6119 }
6120 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6121 {
6122 index = op2 >> 1;
6123 esize = 16;
6124 }
6125 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6126 {
6127 index = 0;
6128 esize = 32;
6129 }
6130 else
6131 {
6132 func (stream, "<undefined index>");
6133 return;
6134 }
6135
6136 targetBeat = (op1 & 0x1) | (h << 1);
6137 idx = index + targetBeat * (32/esize);
6138
6139 func (stream, "%lu", idx);
6140 }
6141
6142 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6143 in length and integer of floating-point type. */
6144 static void
6145 print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6146 unsigned int ibit_loc, const struct mopcode32 *insn)
6147 {
6148 int bits = 0;
6149 int cmode = (given >> 8) & 0xf;
6150 int op = (given >> 5) & 0x1;
6151 unsigned long value = 0, hival = 0;
6152 unsigned shift;
6153 int size = 0;
6154 int isfloat = 0;
6155 void *stream = info->stream;
6156 fprintf_ftype func = info->fprintf_func;
6157
6158 /* On Neon the 'i' bit is at bit 24, on mve it is
6159 at bit 28. */
6160 bits |= ((given >> ibit_loc) & 1) << 7;
6161 bits |= ((given >> 16) & 7) << 4;
6162 bits |= ((given >> 0) & 15) << 0;
6163
6164 if (cmode < 8)
6165 {
6166 shift = (cmode >> 1) & 3;
6167 value = (unsigned long) bits << (8 * shift);
6168 size = 32;
6169 }
6170 else if (cmode < 12)
6171 {
6172 shift = (cmode >> 1) & 1;
6173 value = (unsigned long) bits << (8 * shift);
6174 size = 16;
6175 }
6176 else if (cmode < 14)
6177 {
6178 shift = (cmode & 1) + 1;
6179 value = (unsigned long) bits << (8 * shift);
6180 value |= (1ul << (8 * shift)) - 1;
6181 size = 32;
6182 }
6183 else if (cmode == 14)
6184 {
6185 if (op)
6186 {
6187 /* Bit replication into bytes. */
6188 int ix;
6189 unsigned long mask;
6190
6191 value = 0;
6192 hival = 0;
6193 for (ix = 7; ix >= 0; ix--)
6194 {
6195 mask = ((bits >> ix) & 1) ? 0xff : 0;
6196 if (ix <= 3)
6197 value = (value << 8) | mask;
6198 else
6199 hival = (hival << 8) | mask;
6200 }
6201 size = 64;
6202 }
6203 else
6204 {
6205 /* Byte replication. */
6206 value = (unsigned long) bits;
6207 size = 8;
6208 }
6209 }
6210 else if (!op)
6211 {
6212 /* Floating point encoding. */
6213 int tmp;
6214
6215 value = (unsigned long) (bits & 0x7f) << 19;
6216 value |= (unsigned long) (bits & 0x80) << 24;
6217 tmp = bits & 0x40 ? 0x3c : 0x40;
6218 value |= (unsigned long) tmp << 24;
6219 size = 32;
6220 isfloat = 1;
6221 }
6222 else
6223 {
6224 func (stream, "<illegal constant %.8x:%x:%x>",
6225 bits, cmode, op);
6226 size = 32;
6227 return;
6228 }
6229
6230 // printU determines whether the immediate value should be printed as
6231 // unsigned.
6232 unsigned printU = 0;
6233 switch (insn->mve_op)
6234 {
6235 default:
6236 break;
6237 // We want this for instructions that don't have a 'signed' type
6238 case MVE_VBIC_IMM:
6239 case MVE_VORR_IMM:
6240 case MVE_VMVN_IMM:
6241 case MVE_VMOV_IMM_TO_VEC:
6242 printU = 1;
6243 break;
6244 }
6245 switch (size)
6246 {
6247 case 8:
6248 func (stream, "#%ld\t; 0x%.2lx", value, value);
6249 break;
6250
6251 case 16:
6252 func (stream,
6253 printU
6254 ? "#%lu\t; 0x%.4lx"
6255 : "#%ld\t; 0x%.4lx", value, value);
6256 break;
6257
6258 case 32:
6259 if (isfloat)
6260 {
6261 unsigned char valbytes[4];
6262 double fvalue;
6263
6264 /* Do this a byte at a time so we don't have to
6265 worry about the host's endianness. */
6266 valbytes[0] = value & 0xff;
6267 valbytes[1] = (value >> 8) & 0xff;
6268 valbytes[2] = (value >> 16) & 0xff;
6269 valbytes[3] = (value >> 24) & 0xff;
6270
6271 floatformat_to_double
6272 (& floatformat_ieee_single_little, valbytes,
6273 & fvalue);
6274
6275 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
6276 value);
6277 }
6278 else
6279 func (stream,
6280 printU
6281 ? "#%lu\t; 0x%.8lx"
6282 : "#%ld\t; 0x%.8lx",
6283 (long) (((value & 0x80000000L) != 0)
6284 && !printU
6285 ? value | ~0xffffffffL : value),
6286 value);
6287 break;
6288
6289 case 64:
6290 func (stream, "#0x%.8lx%.8lx", hival, value);
6291 break;
6292
6293 default:
6294 abort ();
6295 }
6296
6297 }
6298
6299 static void
6300 print_mve_undefined (struct disassemble_info *info,
6301 enum mve_undefined undefined_code)
6302 {
6303 void *stream = info->stream;
6304 fprintf_ftype func = info->fprintf_func;
6305
6306 func (stream, "\t\tundefined instruction: ");
6307
6308 switch (undefined_code)
6309 {
6310 case UNDEF_SIZE:
6311 func (stream, "illegal size");
6312 break;
6313
6314 case UNDEF_SIZE_0:
6315 func (stream, "size equals zero");
6316 break;
6317
6318 case UNDEF_SIZE_2:
6319 func (stream, "size equals two");
6320 break;
6321
6322 case UNDEF_SIZE_3:
6323 func (stream, "size equals three");
6324 break;
6325
6326 case UNDEF_SIZE_LE_1:
6327 func (stream, "size <= 1");
6328 break;
6329
6330 case UNDEF_SIZE_NOT_2:
6331 func (stream, "size not equal to 2");
6332 break;
6333
6334 case UNDEF_SIZE_NOT_3:
6335 func (stream, "size not equal to 3");
6336 break;
6337
6338 case UNDEF_NOT_UNS_SIZE_0:
6339 func (stream, "not unsigned and size = zero");
6340 break;
6341
6342 case UNDEF_NOT_UNS_SIZE_1:
6343 func (stream, "not unsigned and size = one");
6344 break;
6345
6346 case UNDEF_NOT_UNSIGNED:
6347 func (stream, "not unsigned");
6348 break;
6349
6350 case UNDEF_VCVT_IMM6:
6351 func (stream, "invalid imm6");
6352 break;
6353
6354 case UNDEF_VCVT_FSI_IMM6:
6355 func (stream, "fsi = 0 and invalid imm6");
6356 break;
6357
6358 case UNDEF_BAD_OP1_OP2:
6359 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
6360 break;
6361
6362 case UNDEF_BAD_U_OP1_OP2:
6363 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
6364 break;
6365
6366 case UNDEF_OP_0_BAD_CMODE:
6367 func (stream, "op field equal 0 and bad cmode");
6368 break;
6369
6370 case UNDEF_XCHG_UNS:
6371 func (stream, "exchange and unsigned together");
6372 break;
6373
6374 case UNDEF_NONE:
6375 break;
6376 }
6377
6378 }
6379
6380 static void
6381 print_mve_unpredictable (struct disassemble_info *info,
6382 enum mve_unpredictable unpredict_code)
6383 {
6384 void *stream = info->stream;
6385 fprintf_ftype func = info->fprintf_func;
6386
6387 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
6388
6389 switch (unpredict_code)
6390 {
6391 case UNPRED_IT_BLOCK:
6392 func (stream, "mve instruction in it block");
6393 break;
6394
6395 case UNPRED_FCA_0_FCB_1:
6396 func (stream, "condition bits, fca = 0 and fcb = 1");
6397 break;
6398
6399 case UNPRED_R13:
6400 func (stream, "use of r13 (sp)");
6401 break;
6402
6403 case UNPRED_R15:
6404 func (stream, "use of r15 (pc)");
6405 break;
6406
6407 case UNPRED_Q_GT_4:
6408 func (stream, "start register block > r4");
6409 break;
6410
6411 case UNPRED_Q_GT_6:
6412 func (stream, "start register block > r6");
6413 break;
6414
6415 case UNPRED_R13_AND_WB:
6416 func (stream, "use of r13 and write back");
6417 break;
6418
6419 case UNPRED_Q_REGS_EQUAL:
6420 func (stream,
6421 "same vector register used for destination and other operand");
6422 break;
6423
6424 case UNPRED_OS:
6425 func (stream, "use of offset scaled");
6426 break;
6427
6428 case UNPRED_GP_REGS_EQUAL:
6429 func (stream, "same general-purpose register used for both operands");
6430 break;
6431
6432 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
6433 func (stream, "use of identical q registers and size = 1");
6434 break;
6435
6436 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
6437 func (stream, "use of identical q registers and size = 1");
6438 break;
6439
6440 case UNPRED_NONE:
6441 break;
6442 }
6443 }
6444
6445 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
6446
6447 static void
6448 print_mve_register_blocks (struct disassemble_info *info,
6449 unsigned long given,
6450 enum mve_instructions matched_insn)
6451 {
6452 void *stream = info->stream;
6453 fprintf_ftype func = info->fprintf_func;
6454
6455 unsigned long q_reg_start = arm_decode_field_multiple (given,
6456 13, 15,
6457 22, 22);
6458 switch (matched_insn)
6459 {
6460 case MVE_VLD2:
6461 case MVE_VST2:
6462 if (q_reg_start <= 6)
6463 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
6464 else
6465 func (stream, "<illegal reg q%ld>", q_reg_start);
6466 break;
6467
6468 case MVE_VLD4:
6469 case MVE_VST4:
6470 if (q_reg_start <= 4)
6471 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
6472 q_reg_start + 1, q_reg_start + 2,
6473 q_reg_start + 3);
6474 else
6475 func (stream, "<illegal reg q%ld>", q_reg_start);
6476 break;
6477
6478 default:
6479 break;
6480 }
6481 }
6482
6483 static void
6484 print_mve_rounding_mode (struct disassemble_info *info,
6485 unsigned long given,
6486 enum mve_instructions matched_insn)
6487 {
6488 void *stream = info->stream;
6489 fprintf_ftype func = info->fprintf_func;
6490
6491 switch (matched_insn)
6492 {
6493 case MVE_VCVT_FROM_FP_TO_INT:
6494 {
6495 switch (arm_decode_field (given, 8, 9))
6496 {
6497 case 0:
6498 func (stream, "a");
6499 break;
6500
6501 case 1:
6502 func (stream, "n");
6503 break;
6504
6505 case 2:
6506 func (stream, "p");
6507 break;
6508
6509 case 3:
6510 func (stream, "m");
6511 break;
6512
6513 default:
6514 break;
6515 }
6516 }
6517 break;
6518
6519 case MVE_VRINT_FP:
6520 {
6521 switch (arm_decode_field (given, 7, 9))
6522 {
6523 case 0:
6524 func (stream, "n");
6525 break;
6526
6527 case 1:
6528 func (stream, "x");
6529 break;
6530
6531 case 2:
6532 func (stream, "a");
6533 break;
6534
6535 case 3:
6536 func (stream, "z");
6537 break;
6538
6539 case 5:
6540 func (stream, "m");
6541 break;
6542
6543 case 7:
6544 func (stream, "p");
6545
6546 case 4:
6547 case 6:
6548 default:
6549 break;
6550 }
6551 }
6552 break;
6553
6554 default:
6555 break;
6556 }
6557 }
6558
6559 static void
6560 print_mve_vcvt_size (struct disassemble_info *info,
6561 unsigned long given,
6562 enum mve_instructions matched_insn)
6563 {
6564 unsigned long mode = 0;
6565 void *stream = info->stream;
6566 fprintf_ftype func = info->fprintf_func;
6567
6568 switch (matched_insn)
6569 {
6570 case MVE_VCVT_FP_FIX_VEC:
6571 {
6572 mode = (((given & 0x200) >> 7)
6573 | ((given & 0x10000000) >> 27)
6574 | ((given & 0x100) >> 8));
6575
6576 switch (mode)
6577 {
6578 case 0:
6579 func (stream, "f16.s16");
6580 break;
6581
6582 case 1:
6583 func (stream, "s16.f16");
6584 break;
6585
6586 case 2:
6587 func (stream, "f16.u16");
6588 break;
6589
6590 case 3:
6591 func (stream, "u16.f16");
6592 break;
6593
6594 case 4:
6595 func (stream, "f32.s32");
6596 break;
6597
6598 case 5:
6599 func (stream, "s32.f32");
6600 break;
6601
6602 case 6:
6603 func (stream, "f32.u32");
6604 break;
6605
6606 case 7:
6607 func (stream, "u32.f32");
6608 break;
6609
6610 default:
6611 break;
6612 }
6613 break;
6614 }
6615 case MVE_VCVT_BETWEEN_FP_INT:
6616 {
6617 unsigned long size = arm_decode_field (given, 18, 19);
6618 unsigned long op = arm_decode_field (given, 7, 8);
6619
6620 if (size == 1)
6621 {
6622 switch (op)
6623 {
6624 case 0:
6625 func (stream, "f16.s16");
6626 break;
6627
6628 case 1:
6629 func (stream, "f16.u16");
6630 break;
6631
6632 case 2:
6633 func (stream, "s16.f16");
6634 break;
6635
6636 case 3:
6637 func (stream, "u16.f16");
6638 break;
6639
6640 default:
6641 break;
6642 }
6643 }
6644 else if (size == 2)
6645 {
6646 switch (op)
6647 {
6648 case 0:
6649 func (stream, "f32.s32");
6650 break;
6651
6652 case 1:
6653 func (stream, "f32.u32");
6654 break;
6655
6656 case 2:
6657 func (stream, "s32.f32");
6658 break;
6659
6660 case 3:
6661 func (stream, "u32.f32");
6662 break;
6663 }
6664 }
6665 }
6666 break;
6667
6668 case MVE_VCVT_FP_HALF_FP:
6669 {
6670 unsigned long op = arm_decode_field (given, 28, 28);
6671 if (op == 0)
6672 func (stream, "f16.f32");
6673 else if (op == 1)
6674 func (stream, "f32.f16");
6675 }
6676 break;
6677
6678 case MVE_VCVT_FROM_FP_TO_INT:
6679 {
6680 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
6681
6682 switch (size)
6683 {
6684 case 2:
6685 func (stream, "s16.f16");
6686 break;
6687
6688 case 3:
6689 func (stream, "u16.f16");
6690 break;
6691
6692 case 4:
6693 func (stream, "s32.f32");
6694 break;
6695
6696 case 5:
6697 func (stream, "u32.f32");
6698 break;
6699
6700 default:
6701 break;
6702 }
6703 }
6704 break;
6705
6706 default:
6707 break;
6708 }
6709 }
6710
6711 static void
6712 print_mve_rotate (struct disassemble_info *info, unsigned long rot,
6713 unsigned long rot_width)
6714 {
6715 void *stream = info->stream;
6716 fprintf_ftype func = info->fprintf_func;
6717
6718 if (rot_width == 1)
6719 {
6720 switch (rot)
6721 {
6722 case 0:
6723 func (stream, "90");
6724 break;
6725 case 1:
6726 func (stream, "270");
6727 break;
6728 default:
6729 break;
6730 }
6731 }
6732 else if (rot_width == 2)
6733 {
6734 switch (rot)
6735 {
6736 case 0:
6737 func (stream, "0");
6738 break;
6739 case 1:
6740 func (stream, "90");
6741 break;
6742 case 2:
6743 func (stream, "180");
6744 break;
6745 case 3:
6746 func (stream, "270");
6747 break;
6748 default:
6749 break;
6750 }
6751 }
6752 }
6753
6754 static void
6755 print_instruction_predicate (struct disassemble_info *info)
6756 {
6757 void *stream = info->stream;
6758 fprintf_ftype func = info->fprintf_func;
6759
6760 if (vpt_block_state.next_pred_state == PRED_THEN)
6761 func (stream, "t");
6762 else if (vpt_block_state.next_pred_state == PRED_ELSE)
6763 func (stream, "e");
6764 }
6765
6766 static void
6767 print_mve_size (struct disassemble_info *info,
6768 unsigned long size,
6769 enum mve_instructions matched_insn)
6770 {
6771 void *stream = info->stream;
6772 fprintf_ftype func = info->fprintf_func;
6773
6774 switch (matched_insn)
6775 {
6776 case MVE_VABAV:
6777 case MVE_VABD_VEC:
6778 case MVE_VABS_FP:
6779 case MVE_VABS_VEC:
6780 case MVE_VADD_VEC_T1:
6781 case MVE_VADD_VEC_T2:
6782 case MVE_VADDV:
6783 case MVE_VCADD_VEC:
6784 case MVE_VCMP_VEC_T1:
6785 case MVE_VCMP_VEC_T2:
6786 case MVE_VCMP_VEC_T3:
6787 case MVE_VCMP_VEC_T4:
6788 case MVE_VCMP_VEC_T5:
6789 case MVE_VCMP_VEC_T6:
6790 case MVE_VDDUP:
6791 case MVE_VDWDUP:
6792 case MVE_VHADD_T1:
6793 case MVE_VHADD_T2:
6794 case MVE_VHCADD:
6795 case MVE_VHSUB_T1:
6796 case MVE_VHSUB_T2:
6797 case MVE_VIDUP:
6798 case MVE_VIWDUP:
6799 case MVE_VLD2:
6800 case MVE_VLD4:
6801 case MVE_VLDRB_GATHER_T1:
6802 case MVE_VLDRH_GATHER_T2:
6803 case MVE_VLDRW_GATHER_T3:
6804 case MVE_VLDRD_GATHER_T4:
6805 case MVE_VLDRB_T1:
6806 case MVE_VLDRH_T2:
6807 case MVE_VMLAS:
6808 case MVE_VPT_VEC_T1:
6809 case MVE_VPT_VEC_T2:
6810 case MVE_VPT_VEC_T3:
6811 case MVE_VPT_VEC_T4:
6812 case MVE_VPT_VEC_T5:
6813 case MVE_VPT_VEC_T6:
6814 case MVE_VQDMLADH:
6815 case MVE_VQRDMLADH:
6816 case MVE_VQDMLAH:
6817 case MVE_VQRDMLAH:
6818 case MVE_VQDMLASH:
6819 case MVE_VQRDMLASH:
6820 case MVE_VQDMLSDH:
6821 case MVE_VQRDMLSDH:
6822 case MVE_VQDMULH_T1:
6823 case MVE_VQRDMULH_T2:
6824 case MVE_VQDMULH_T3:
6825 case MVE_VQRDMULH_T4:
6826 case MVE_VQRSHL_T1:
6827 case MVE_VQRSHL_T2:
6828 case MVE_VQSHL_T1:
6829 case MVE_VQSHL_T4:
6830 case MVE_VRHADD:
6831 case MVE_VRINT_FP:
6832 case MVE_VRSHL_T1:
6833 case MVE_VRSHL_T2:
6834 case MVE_VSHL_T2:
6835 case MVE_VSHL_T3:
6836 case MVE_VSHLL_T2:
6837 case MVE_VST2:
6838 case MVE_VST4:
6839 case MVE_VSTRB_SCATTER_T1:
6840 case MVE_VSTRH_SCATTER_T2:
6841 case MVE_VSTRW_SCATTER_T3:
6842 case MVE_VSTRB_T1:
6843 case MVE_VSTRH_T2:
6844 case MVE_VSUB_VEC_T1:
6845 case MVE_VSUB_VEC_T2:
6846 if (size <= 3)
6847 func (stream, "%s", mve_vec_sizename[size]);
6848 else
6849 func (stream, "<undef size>");
6850 break;
6851
6852 case MVE_VABD_FP:
6853 case MVE_VADD_FP_T1:
6854 case MVE_VADD_FP_T2:
6855 case MVE_VSUB_FP_T1:
6856 case MVE_VSUB_FP_T2:
6857 case MVE_VCMP_FP_T1:
6858 case MVE_VCMP_FP_T2:
6859 case MVE_VFMA_FP_SCALAR:
6860 case MVE_VFMA_FP:
6861 case MVE_VFMS_FP:
6862 case MVE_VFMAS_FP_SCALAR:
6863 case MVE_VPT_FP_T1:
6864 case MVE_VPT_FP_T2:
6865 if (size == 0)
6866 func (stream, "32");
6867 else if (size == 1)
6868 func (stream, "16");
6869 break;
6870
6871 case MVE_VCADD_FP:
6872 case MVE_VCMLA_FP:
6873 case MVE_VCMUL_FP:
6874 case MVE_VMLADAV_T1:
6875 case MVE_VMLALDAV:
6876 case MVE_VMLSDAV_T1:
6877 case MVE_VMLSLDAV:
6878 case MVE_VMOVN:
6879 case MVE_VQDMULL_T1:
6880 case MVE_VQDMULL_T2:
6881 case MVE_VQMOVN:
6882 case MVE_VQMOVUN:
6883 if (size == 0)
6884 func (stream, "16");
6885 else if (size == 1)
6886 func (stream, "32");
6887 break;
6888
6889 case MVE_VMOVL:
6890 if (size == 1)
6891 func (stream, "8");
6892 else if (size == 2)
6893 func (stream, "16");
6894 break;
6895
6896 case MVE_VDUP:
6897 switch (size)
6898 {
6899 case 0:
6900 func (stream, "32");
6901 break;
6902 case 1:
6903 func (stream, "16");
6904 break;
6905 case 2:
6906 func (stream, "8");
6907 break;
6908 default:
6909 break;
6910 }
6911 break;
6912
6913 case MVE_VMOV_GP_TO_VEC_LANE:
6914 case MVE_VMOV_VEC_LANE_TO_GP:
6915 switch (size)
6916 {
6917 case 0: case 4:
6918 func (stream, "32");
6919 break;
6920
6921 case 1: case 3:
6922 case 5: case 7:
6923 func (stream, "16");
6924 break;
6925
6926 case 8: case 9: case 10: case 11:
6927 case 12: case 13: case 14: case 15:
6928 func (stream, "8");
6929 break;
6930
6931 default:
6932 break;
6933 }
6934 break;
6935
6936 case MVE_VMOV_IMM_TO_VEC:
6937 switch (size)
6938 {
6939 case 0: case 4: case 8:
6940 case 12: case 24: case 26:
6941 func (stream, "i32");
6942 break;
6943 case 16: case 20:
6944 func (stream, "i16");
6945 break;
6946 case 28:
6947 func (stream, "i8");
6948 break;
6949 case 29:
6950 func (stream, "i64");
6951 break;
6952 case 30:
6953 func (stream, "f32");
6954 break;
6955 default:
6956 break;
6957 }
6958 break;
6959
6960 case MVE_VMULL_POLY:
6961 if (size == 0)
6962 func (stream, "p8");
6963 else if (size == 1)
6964 func (stream, "p16");
6965 break;
6966
6967 case MVE_VMVN_IMM:
6968 switch (size)
6969 {
6970 case 0: case 2: case 4:
6971 case 6: case 12: case 13:
6972 func (stream, "32");
6973 break;
6974
6975 case 8: case 10:
6976 func (stream, "16");
6977 break;
6978
6979 default:
6980 break;
6981 }
6982 break;
6983
6984 case MVE_VBIC_IMM:
6985 case MVE_VORR_IMM:
6986 switch (size)
6987 {
6988 case 1: case 3:
6989 case 5: case 7:
6990 func (stream, "32");
6991 break;
6992
6993 case 9: case 11:
6994 func (stream, "16");
6995 break;
6996
6997 default:
6998 break;
6999 }
7000 break;
7001
7002 case MVE_VQSHRN:
7003 case MVE_VQSHRUN:
7004 case MVE_VQRSHRN:
7005 case MVE_VQRSHRUN:
7006 case MVE_VRSHRN:
7007 case MVE_VSHRN:
7008 {
7009 switch (size)
7010 {
7011 case 1:
7012 func (stream, "16");
7013 break;
7014
7015 case 2: case 3:
7016 func (stream, "32");
7017 break;
7018
7019 default:
7020 break;
7021 }
7022 }
7023 break;
7024
7025 case MVE_VQSHL_T2:
7026 case MVE_VQSHLU_T3:
7027 case MVE_VRSHR:
7028 case MVE_VSHL_T1:
7029 case MVE_VSHLL_T1:
7030 case MVE_VSHR:
7031 case MVE_VSLI:
7032 case MVE_VSRI:
7033 {
7034 switch (size)
7035 {
7036 case 1:
7037 func (stream, "8");
7038 break;
7039
7040 case 2: case 3:
7041 func (stream, "16");
7042 break;
7043
7044 case 4: case 5: case 6: case 7:
7045 func (stream, "32");
7046 break;
7047
7048 default:
7049 break;
7050 }
7051 }
7052 break;
7053
7054 default:
7055 break;
7056 }
7057 }
7058
7059 static void
7060 print_mve_shift_n (struct disassemble_info *info, long given,
7061 enum mve_instructions matched_insn)
7062 {
7063 void *stream = info->stream;
7064 fprintf_ftype func = info->fprintf_func;
7065
7066 int startAt0
7067 = matched_insn == MVE_VQSHL_T2
7068 || matched_insn == MVE_VQSHLU_T3
7069 || matched_insn == MVE_VSHL_T1
7070 || matched_insn == MVE_VSHLL_T1
7071 || matched_insn == MVE_VSLI;
7072
7073 unsigned imm6 = (given & 0x3f0000) >> 16;
7074
7075 if (matched_insn == MVE_VSHLL_T1)
7076 imm6 &= 0x1f;
7077
7078 unsigned shiftAmount = 0;
7079 if ((imm6 & 0x20) != 0)
7080 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7081 else if ((imm6 & 0x10) != 0)
7082 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7083 else if ((imm6 & 0x08) != 0)
7084 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7085 else
7086 print_mve_undefined (info, UNDEF_SIZE_0);
7087
7088 func (stream, "%u", shiftAmount);
7089 }
7090
7091 static void
7092 print_vec_condition (struct disassemble_info *info, long given,
7093 enum mve_instructions matched_insn)
7094 {
7095 void *stream = info->stream;
7096 fprintf_ftype func = info->fprintf_func;
7097 long vec_cond = 0;
7098
7099 switch (matched_insn)
7100 {
7101 case MVE_VPT_FP_T1:
7102 case MVE_VCMP_FP_T1:
7103 vec_cond = (((given & 0x1000) >> 10)
7104 | ((given & 1) << 1)
7105 | ((given & 0x0080) >> 7));
7106 func (stream, "%s",vec_condnames[vec_cond]);
7107 break;
7108
7109 case MVE_VPT_FP_T2:
7110 case MVE_VCMP_FP_T2:
7111 vec_cond = (((given & 0x1000) >> 10)
7112 | ((given & 0x0020) >> 4)
7113 | ((given & 0x0080) >> 7));
7114 func (stream, "%s",vec_condnames[vec_cond]);
7115 break;
7116
7117 case MVE_VPT_VEC_T1:
7118 case MVE_VCMP_VEC_T1:
7119 vec_cond = (given & 0x0080) >> 7;
7120 func (stream, "%s",vec_condnames[vec_cond]);
7121 break;
7122
7123 case MVE_VPT_VEC_T2:
7124 case MVE_VCMP_VEC_T2:
7125 vec_cond = 2 | ((given & 0x0080) >> 7);
7126 func (stream, "%s",vec_condnames[vec_cond]);
7127 break;
7128
7129 case MVE_VPT_VEC_T3:
7130 case MVE_VCMP_VEC_T3:
7131 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7132 func (stream, "%s",vec_condnames[vec_cond]);
7133 break;
7134
7135 case MVE_VPT_VEC_T4:
7136 case MVE_VCMP_VEC_T4:
7137 vec_cond = (given & 0x0080) >> 7;
7138 func (stream, "%s",vec_condnames[vec_cond]);
7139 break;
7140
7141 case MVE_VPT_VEC_T5:
7142 case MVE_VCMP_VEC_T5:
7143 vec_cond = 2 | ((given & 0x0080) >> 7);
7144 func (stream, "%s",vec_condnames[vec_cond]);
7145 break;
7146
7147 case MVE_VPT_VEC_T6:
7148 case MVE_VCMP_VEC_T6:
7149 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7150 func (stream, "%s",vec_condnames[vec_cond]);
7151 break;
7152
7153 case MVE_NONE:
7154 case MVE_VPST:
7155 default:
7156 break;
7157 }
7158 }
7159
7160 #define W_BIT 21
7161 #define I_BIT 22
7162 #define U_BIT 23
7163 #define P_BIT 24
7164
7165 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7166 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7167 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7168 #define PRE_BIT_SET (given & (1 << P_BIT))
7169
7170
7171 /* Print one coprocessor instruction on INFO->STREAM.
7172 Return TRUE if the instuction matched, FALSE if this is not a
7173 recognised coprocessor instruction. */
7174
7175 static bfd_boolean
7176 print_insn_coprocessor (bfd_vma pc,
7177 struct disassemble_info *info,
7178 long given,
7179 bfd_boolean thumb)
7180 {
7181 const struct sopcode32 *insn;
7182 void *stream = info->stream;
7183 fprintf_ftype func = info->fprintf_func;
7184 unsigned long mask;
7185 unsigned long value = 0;
7186 int cond;
7187 int cp_num;
7188 struct arm_private_data *private_data = info->private_data;
7189 arm_feature_set allowed_arches = ARM_ARCH_NONE;
7190 arm_feature_set arm_ext_v8_1m_main =
7191 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
7192
7193 allowed_arches = private_data->features;
7194
7195 for (insn = coprocessor_opcodes; insn->assembler; insn++)
7196 {
7197 unsigned long u_reg = 16;
7198 bfd_boolean is_unpredictable = FALSE;
7199 signed long value_in_comment = 0;
7200 const char *c;
7201
7202 if (ARM_FEATURE_ZERO (insn->arch))
7203 switch (insn->value)
7204 {
7205 case SENTINEL_IWMMXT_START:
7206 if (info->mach != bfd_mach_arm_XScale
7207 && info->mach != bfd_mach_arm_iWMMXt
7208 && info->mach != bfd_mach_arm_iWMMXt2)
7209 do
7210 insn++;
7211 while ((! ARM_FEATURE_ZERO (insn->arch))
7212 && insn->value != SENTINEL_IWMMXT_END);
7213 continue;
7214
7215 case SENTINEL_IWMMXT_END:
7216 continue;
7217
7218 case SENTINEL_GENERIC_START:
7219 allowed_arches = private_data->features;
7220 continue;
7221
7222 default:
7223 abort ();
7224 }
7225
7226 mask = insn->mask;
7227 value = insn->value;
7228 cp_num = (given >> 8) & 0xf;
7229
7230 if (thumb)
7231 {
7232 /* The high 4 bits are 0xe for Arm conditional instructions, and
7233 0xe for arm unconditional instructions. The rest of the
7234 encoding is the same. */
7235 mask |= 0xf0000000;
7236 value |= 0xe0000000;
7237 if (ifthen_state)
7238 cond = IFTHEN_COND;
7239 else
7240 cond = COND_UNCOND;
7241 }
7242 else
7243 {
7244 /* Only match unconditional instuctions against unconditional
7245 patterns. */
7246 if ((given & 0xf0000000) == 0xf0000000)
7247 {
7248 mask |= 0xf0000000;
7249 cond = COND_UNCOND;
7250 }
7251 else
7252 {
7253 cond = (given >> 28) & 0xf;
7254 if (cond == 0xe)
7255 cond = COND_UNCOND;
7256 }
7257 }
7258
7259 if ((insn->isa == T32 && !thumb)
7260 || (insn->isa == ARM && thumb))
7261 continue;
7262
7263 if ((given & mask) != value)
7264 continue;
7265
7266 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
7267 continue;
7268
7269 if (insn->value == 0xfe000010 /* mcr2 */
7270 || insn->value == 0xfe100010 /* mrc2 */
7271 || insn->value == 0xfc100000 /* ldc2 */
7272 || insn->value == 0xfc000000) /* stc2 */
7273 {
7274 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
7275 is_unpredictable = TRUE;
7276
7277 /* Armv8.1-M Mainline FP & MVE instructions. */
7278 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7279 && !ARM_CPU_IS_ANY (allowed_arches)
7280 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7281 continue;
7282
7283 }
7284 else if (insn->value == 0x0e000000 /* cdp */
7285 || insn->value == 0xfe000000 /* cdp2 */
7286 || insn->value == 0x0e000010 /* mcr */
7287 || insn->value == 0x0e100010 /* mrc */
7288 || insn->value == 0x0c100000 /* ldc */
7289 || insn->value == 0x0c000000) /* stc */
7290 {
7291 /* Floating-point instructions. */
7292 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
7293 continue;
7294
7295 /* Armv8.1-M Mainline FP & MVE instructions. */
7296 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7297 && !ARM_CPU_IS_ANY (allowed_arches)
7298 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7299 continue;
7300 }
7301 else if ((insn->value == 0xec100f80 /* vldr (system register) */
7302 || insn->value == 0xec000f80) /* vstr (system register) */
7303 && arm_decode_field (given, 24, 24) == 0
7304 && arm_decode_field (given, 21, 21) == 0)
7305 /* If the P and W bits are both 0 then these encodings match the MVE
7306 VLDR and VSTR instructions, these are in a different table, so we
7307 don't let it match here. */
7308 continue;
7309
7310 for (c = insn->assembler; *c; c++)
7311 {
7312 if (*c == '%')
7313 {
7314 const char mod = *++c;
7315 switch (mod)
7316 {
7317 case '%':
7318 func (stream, "%%");
7319 break;
7320
7321 case 'A':
7322 case 'K':
7323 {
7324 int rn = (given >> 16) & 0xf;
7325 bfd_vma offset = given & 0xff;
7326
7327 if (mod == 'K')
7328 offset = given & 0x7f;
7329
7330 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
7331
7332 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
7333 {
7334 /* Not unindexed. The offset is scaled. */
7335 if (cp_num == 9)
7336 /* vldr.16/vstr.16 will shift the address
7337 left by 1 bit only. */
7338 offset = offset * 2;
7339 else
7340 offset = offset * 4;
7341
7342 if (NEGATIVE_BIT_SET)
7343 offset = - offset;
7344 if (rn != 15)
7345 value_in_comment = offset;
7346 }
7347
7348 if (PRE_BIT_SET)
7349 {
7350 if (offset)
7351 func (stream, ", #%d]%s",
7352 (int) offset,
7353 WRITEBACK_BIT_SET ? "!" : "");
7354 else if (NEGATIVE_BIT_SET)
7355 func (stream, ", #-0]");
7356 else
7357 func (stream, "]");
7358 }
7359 else
7360 {
7361 func (stream, "]");
7362
7363 if (WRITEBACK_BIT_SET)
7364 {
7365 if (offset)
7366 func (stream, ", #%d", (int) offset);
7367 else if (NEGATIVE_BIT_SET)
7368 func (stream, ", #-0");
7369 }
7370 else
7371 {
7372 func (stream, ", {%s%d}",
7373 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
7374 (int) offset);
7375 value_in_comment = offset;
7376 }
7377 }
7378 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
7379 {
7380 func (stream, "\t; ");
7381 /* For unaligned PCs, apply off-by-alignment
7382 correction. */
7383 info->print_address_func (offset + pc
7384 + info->bytes_per_chunk * 2
7385 - (pc & 3),
7386 info);
7387 }
7388 }
7389 break;
7390
7391 case 'B':
7392 {
7393 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
7394 int offset = (given >> 1) & 0x3f;
7395
7396 if (offset == 1)
7397 func (stream, "{d%d}", regno);
7398 else if (regno + offset > 32)
7399 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
7400 else
7401 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
7402 }
7403 break;
7404
7405 case 'C':
7406 {
7407 bfd_boolean single = ((given >> 8) & 1) == 0;
7408 char reg_prefix = single ? 's' : 'd';
7409 int Dreg = (given >> 22) & 0x1;
7410 int Vdreg = (given >> 12) & 0xf;
7411 int reg = single ? ((Vdreg << 1) | Dreg)
7412 : ((Dreg << 4) | Vdreg);
7413 int num = (given >> (single ? 0 : 1)) & 0x7f;
7414 int maxreg = single ? 31 : 15;
7415 int topreg = reg + num - 1;
7416
7417 if (!num)
7418 func (stream, "{VPR}");
7419 else if (num == 1)
7420 func (stream, "{%c%d, VPR}", reg_prefix, reg);
7421 else if (topreg > maxreg)
7422 func (stream, "{%c%d-<overflow reg d%d, VPR}",
7423 reg_prefix, reg, single ? topreg >> 1 : topreg);
7424 else
7425 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
7426 reg_prefix, topreg);
7427 }
7428 break;
7429
7430 case 'u':
7431 if (cond != COND_UNCOND)
7432 is_unpredictable = TRUE;
7433
7434 /* Fall through. */
7435 case 'c':
7436 if (cond != COND_UNCOND && cp_num == 9)
7437 is_unpredictable = TRUE;
7438
7439 func (stream, "%s", arm_conditional[cond]);
7440 break;
7441
7442 case 'I':
7443 /* Print a Cirrus/DSP shift immediate. */
7444 /* Immediates are 7bit signed ints with bits 0..3 in
7445 bits 0..3 of opcode and bits 4..6 in bits 5..7
7446 of opcode. */
7447 {
7448 int imm;
7449
7450 imm = (given & 0xf) | ((given & 0xe0) >> 1);
7451
7452 /* Is ``imm'' a negative number? */
7453 if (imm & 0x40)
7454 imm -= 0x80;
7455
7456 func (stream, "%d", imm);
7457 }
7458
7459 break;
7460
7461 case 'J':
7462 {
7463 unsigned long regno
7464 = arm_decode_field_multiple (given, 13, 15, 22, 22);
7465
7466 switch (regno)
7467 {
7468 case 0x1:
7469 func (stream, "FPSCR");
7470 break;
7471 case 0x2:
7472 func (stream, "FPSCR_nzcvqc");
7473 break;
7474 case 0xc:
7475 func (stream, "VPR");
7476 break;
7477 case 0xd:
7478 func (stream, "P0");
7479 break;
7480 case 0xe:
7481 func (stream, "FPCXTNS");
7482 break;
7483 case 0xf:
7484 func (stream, "FPCXTS");
7485 break;
7486 default:
7487 func (stream, "<invalid reg %lu>", regno);
7488 break;
7489 }
7490 }
7491 break;
7492
7493 case 'F':
7494 switch (given & 0x00408000)
7495 {
7496 case 0:
7497 func (stream, "4");
7498 break;
7499 case 0x8000:
7500 func (stream, "1");
7501 break;
7502 case 0x00400000:
7503 func (stream, "2");
7504 break;
7505 default:
7506 func (stream, "3");
7507 }
7508 break;
7509
7510 case 'P':
7511 switch (given & 0x00080080)
7512 {
7513 case 0:
7514 func (stream, "s");
7515 break;
7516 case 0x80:
7517 func (stream, "d");
7518 break;
7519 case 0x00080000:
7520 func (stream, "e");
7521 break;
7522 default:
7523 func (stream, _("<illegal precision>"));
7524 break;
7525 }
7526 break;
7527
7528 case 'Q':
7529 switch (given & 0x00408000)
7530 {
7531 case 0:
7532 func (stream, "s");
7533 break;
7534 case 0x8000:
7535 func (stream, "d");
7536 break;
7537 case 0x00400000:
7538 func (stream, "e");
7539 break;
7540 default:
7541 func (stream, "p");
7542 break;
7543 }
7544 break;
7545
7546 case 'R':
7547 switch (given & 0x60)
7548 {
7549 case 0:
7550 break;
7551 case 0x20:
7552 func (stream, "p");
7553 break;
7554 case 0x40:
7555 func (stream, "m");
7556 break;
7557 default:
7558 func (stream, "z");
7559 break;
7560 }
7561 break;
7562
7563 case '0': case '1': case '2': case '3': case '4':
7564 case '5': case '6': case '7': case '8': case '9':
7565 {
7566 int width;
7567
7568 c = arm_decode_bitfield (c, given, &value, &width);
7569
7570 switch (*c)
7571 {
7572 case 'R':
7573 if (value == 15)
7574 is_unpredictable = TRUE;
7575 /* Fall through. */
7576 case 'r':
7577 if (c[1] == 'u')
7578 {
7579 /* Eat the 'u' character. */
7580 ++ c;
7581
7582 if (u_reg == value)
7583 is_unpredictable = TRUE;
7584 u_reg = value;
7585 }
7586 func (stream, "%s", arm_regnames[value]);
7587 break;
7588 case 'V':
7589 if (given & (1 << 6))
7590 goto Q;
7591 /* FALLTHROUGH */
7592 case 'D':
7593 func (stream, "d%ld", value);
7594 break;
7595 case 'Q':
7596 Q:
7597 if (value & 1)
7598 func (stream, "<illegal reg q%ld.5>", value >> 1);
7599 else
7600 func (stream, "q%ld", value >> 1);
7601 break;
7602 case 'd':
7603 func (stream, "%ld", value);
7604 value_in_comment = value;
7605 break;
7606 case 'E':
7607 {
7608 /* Converts immediate 8 bit back to float value. */
7609 unsigned floatVal = (value & 0x80) << 24
7610 | (value & 0x3F) << 19
7611 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
7612
7613 /* Quarter float have a maximum value of 31.0.
7614 Get floating point value multiplied by 1e7.
7615 The maximum value stays in limit of a 32-bit int. */
7616 unsigned decVal =
7617 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
7618 (16 + (value & 0xF));
7619
7620 if (!(decVal % 1000000))
7621 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
7622 floatVal, value & 0x80 ? '-' : ' ',
7623 decVal / 10000000,
7624 decVal % 10000000 / 1000000);
7625 else if (!(decVal % 10000))
7626 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
7627 floatVal, value & 0x80 ? '-' : ' ',
7628 decVal / 10000000,
7629 decVal % 10000000 / 10000);
7630 else
7631 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
7632 floatVal, value & 0x80 ? '-' : ' ',
7633 decVal / 10000000, decVal % 10000000);
7634 break;
7635 }
7636 case 'k':
7637 {
7638 int from = (given & (1 << 7)) ? 32 : 16;
7639 func (stream, "%ld", from - value);
7640 }
7641 break;
7642
7643 case 'f':
7644 if (value > 7)
7645 func (stream, "#%s", arm_fp_const[value & 7]);
7646 else
7647 func (stream, "f%ld", value);
7648 break;
7649
7650 case 'w':
7651 if (width == 2)
7652 func (stream, "%s", iwmmxt_wwnames[value]);
7653 else
7654 func (stream, "%s", iwmmxt_wwssnames[value]);
7655 break;
7656
7657 case 'g':
7658 func (stream, "%s", iwmmxt_regnames[value]);
7659 break;
7660 case 'G':
7661 func (stream, "%s", iwmmxt_cregnames[value]);
7662 break;
7663
7664 case 'x':
7665 func (stream, "0x%lx", (value & 0xffffffffUL));
7666 break;
7667
7668 case 'c':
7669 switch (value)
7670 {
7671 case 0:
7672 func (stream, "eq");
7673 break;
7674
7675 case 1:
7676 func (stream, "vs");
7677 break;
7678
7679 case 2:
7680 func (stream, "ge");
7681 break;
7682
7683 case 3:
7684 func (stream, "gt");
7685 break;
7686
7687 default:
7688 func (stream, "??");
7689 break;
7690 }
7691 break;
7692
7693 case '`':
7694 c++;
7695 if (value == 0)
7696 func (stream, "%c", *c);
7697 break;
7698 case '\'':
7699 c++;
7700 if (value == ((1ul << width) - 1))
7701 func (stream, "%c", *c);
7702 break;
7703 case '?':
7704 func (stream, "%c", c[(1 << width) - (int) value]);
7705 c += 1 << width;
7706 break;
7707 default:
7708 abort ();
7709 }
7710 }
7711 break;
7712
7713 case 'y':
7714 case 'z':
7715 {
7716 int single = *c++ == 'y';
7717 int regno;
7718
7719 switch (*c)
7720 {
7721 case '4': /* Sm pair */
7722 case '0': /* Sm, Dm */
7723 regno = given & 0x0000000f;
7724 if (single)
7725 {
7726 regno <<= 1;
7727 regno += (given >> 5) & 1;
7728 }
7729 else
7730 regno += ((given >> 5) & 1) << 4;
7731 break;
7732
7733 case '1': /* Sd, Dd */
7734 regno = (given >> 12) & 0x0000000f;
7735 if (single)
7736 {
7737 regno <<= 1;
7738 regno += (given >> 22) & 1;
7739 }
7740 else
7741 regno += ((given >> 22) & 1) << 4;
7742 break;
7743
7744 case '2': /* Sn, Dn */
7745 regno = (given >> 16) & 0x0000000f;
7746 if (single)
7747 {
7748 regno <<= 1;
7749 regno += (given >> 7) & 1;
7750 }
7751 else
7752 regno += ((given >> 7) & 1) << 4;
7753 break;
7754
7755 case '3': /* List */
7756 func (stream, "{");
7757 regno = (given >> 12) & 0x0000000f;
7758 if (single)
7759 {
7760 regno <<= 1;
7761 regno += (given >> 22) & 1;
7762 }
7763 else
7764 regno += ((given >> 22) & 1) << 4;
7765 break;
7766
7767 default:
7768 abort ();
7769 }
7770
7771 func (stream, "%c%d", single ? 's' : 'd', regno);
7772
7773 if (*c == '3')
7774 {
7775 int count = given & 0xff;
7776
7777 if (single == 0)
7778 count >>= 1;
7779
7780 if (--count)
7781 {
7782 func (stream, "-%c%d",
7783 single ? 's' : 'd',
7784 regno + count);
7785 }
7786
7787 func (stream, "}");
7788 }
7789 else if (*c == '4')
7790 func (stream, ", %c%d", single ? 's' : 'd',
7791 regno + 1);
7792 }
7793 break;
7794
7795 case 'L':
7796 switch (given & 0x00400100)
7797 {
7798 case 0x00000000: func (stream, "b"); break;
7799 case 0x00400000: func (stream, "h"); break;
7800 case 0x00000100: func (stream, "w"); break;
7801 case 0x00400100: func (stream, "d"); break;
7802 default:
7803 break;
7804 }
7805 break;
7806
7807 case 'Z':
7808 {
7809 /* given (20, 23) | given (0, 3) */
7810 value = ((given >> 16) & 0xf0) | (given & 0xf);
7811 func (stream, "%d", (int) value);
7812 }
7813 break;
7814
7815 case 'l':
7816 /* This is like the 'A' operator, except that if
7817 the width field "M" is zero, then the offset is
7818 *not* multiplied by four. */
7819 {
7820 int offset = given & 0xff;
7821 int multiplier = (given & 0x00000100) ? 4 : 1;
7822
7823 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
7824
7825 if (multiplier > 1)
7826 {
7827 value_in_comment = offset * multiplier;
7828 if (NEGATIVE_BIT_SET)
7829 value_in_comment = - value_in_comment;
7830 }
7831
7832 if (offset)
7833 {
7834 if (PRE_BIT_SET)
7835 func (stream, ", #%s%d]%s",
7836 NEGATIVE_BIT_SET ? "-" : "",
7837 offset * multiplier,
7838 WRITEBACK_BIT_SET ? "!" : "");
7839 else
7840 func (stream, "], #%s%d",
7841 NEGATIVE_BIT_SET ? "-" : "",
7842 offset * multiplier);
7843 }
7844 else
7845 func (stream, "]");
7846 }
7847 break;
7848
7849 case 'r':
7850 {
7851 int imm4 = (given >> 4) & 0xf;
7852 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
7853 int ubit = ! NEGATIVE_BIT_SET;
7854 const char *rm = arm_regnames [given & 0xf];
7855 const char *rn = arm_regnames [(given >> 16) & 0xf];
7856
7857 switch (puw_bits)
7858 {
7859 case 1:
7860 case 3:
7861 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
7862 if (imm4)
7863 func (stream, ", lsl #%d", imm4);
7864 break;
7865
7866 case 4:
7867 case 5:
7868 case 6:
7869 case 7:
7870 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
7871 if (imm4 > 0)
7872 func (stream, ", lsl #%d", imm4);
7873 func (stream, "]");
7874 if (puw_bits == 5 || puw_bits == 7)
7875 func (stream, "!");
7876 break;
7877
7878 default:
7879 func (stream, "INVALID");
7880 }
7881 }
7882 break;
7883
7884 case 'i':
7885 {
7886 long imm5;
7887 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
7888 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
7889 }
7890 break;
7891
7892 default:
7893 abort ();
7894 }
7895 }
7896 else
7897 func (stream, "%c", *c);
7898 }
7899
7900 if (value_in_comment > 32 || value_in_comment < -16)
7901 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
7902
7903 if (is_unpredictable)
7904 func (stream, UNPREDICTABLE_INSTRUCTION);
7905
7906 return TRUE;
7907 }
7908 return FALSE;
7909 }
7910
7911 /* Decodes and prints ARM addressing modes. Returns the offset
7912 used in the address, if any, if it is worthwhile printing the
7913 offset as a hexadecimal value in a comment at the end of the
7914 line of disassembly. */
7915
7916 static signed long
7917 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
7918 {
7919 void *stream = info->stream;
7920 fprintf_ftype func = info->fprintf_func;
7921 bfd_vma offset = 0;
7922
7923 if (((given & 0x000f0000) == 0x000f0000)
7924 && ((given & 0x02000000) == 0))
7925 {
7926 offset = given & 0xfff;
7927
7928 func (stream, "[pc");
7929
7930 if (PRE_BIT_SET)
7931 {
7932 /* Pre-indexed. Elide offset of positive zero when
7933 non-writeback. */
7934 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
7935 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
7936
7937 if (NEGATIVE_BIT_SET)
7938 offset = -offset;
7939
7940 offset += pc + 8;
7941
7942 /* Cope with the possibility of write-back
7943 being used. Probably a very dangerous thing
7944 for the programmer to do, but who are we to
7945 argue ? */
7946 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
7947 }
7948 else /* Post indexed. */
7949 {
7950 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
7951
7952 /* Ie ignore the offset. */
7953 offset = pc + 8;
7954 }
7955
7956 func (stream, "\t; ");
7957 info->print_address_func (offset, info);
7958 offset = 0;
7959 }
7960 else
7961 {
7962 func (stream, "[%s",
7963 arm_regnames[(given >> 16) & 0xf]);
7964
7965 if (PRE_BIT_SET)
7966 {
7967 if ((given & 0x02000000) == 0)
7968 {
7969 /* Elide offset of positive zero when non-writeback. */
7970 offset = given & 0xfff;
7971 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
7972 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
7973 }
7974 else
7975 {
7976 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
7977 arm_decode_shift (given, func, stream, TRUE);
7978 }
7979
7980 func (stream, "]%s",
7981 WRITEBACK_BIT_SET ? "!" : "");
7982 }
7983 else
7984 {
7985 if ((given & 0x02000000) == 0)
7986 {
7987 /* Always show offset. */
7988 offset = given & 0xfff;
7989 func (stream, "], #%s%d",
7990 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
7991 }
7992 else
7993 {
7994 func (stream, "], %s",
7995 NEGATIVE_BIT_SET ? "-" : "");
7996 arm_decode_shift (given, func, stream, TRUE);
7997 }
7998 }
7999 if (NEGATIVE_BIT_SET)
8000 offset = -offset;
8001 }
8002
8003 return (signed long) offset;
8004 }
8005
8006 /* Print one neon instruction on INFO->STREAM.
8007 Return TRUE if the instuction matched, FALSE if this is not a
8008 recognised neon instruction. */
8009
8010 static bfd_boolean
8011 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
8012 {
8013 const struct opcode32 *insn;
8014 void *stream = info->stream;
8015 fprintf_ftype func = info->fprintf_func;
8016
8017 if (thumb)
8018 {
8019 if ((given & 0xef000000) == 0xef000000)
8020 {
8021 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
8022 unsigned long bit28 = given & (1 << 28);
8023
8024 given &= 0x00ffffff;
8025 if (bit28)
8026 given |= 0xf3000000;
8027 else
8028 given |= 0xf2000000;
8029 }
8030 else if ((given & 0xff000000) == 0xf9000000)
8031 given ^= 0xf9000000 ^ 0xf4000000;
8032 /* vdup is also a valid neon instruction. */
8033 else if ((given & 0xff910f5f) != 0xee800b10)
8034 return FALSE;
8035 }
8036
8037 for (insn = neon_opcodes; insn->assembler; insn++)
8038 {
8039 if ((given & insn->mask) == insn->value)
8040 {
8041 signed long value_in_comment = 0;
8042 bfd_boolean is_unpredictable = FALSE;
8043 const char *c;
8044
8045 for (c = insn->assembler; *c; c++)
8046 {
8047 if (*c == '%')
8048 {
8049 switch (*++c)
8050 {
8051 case '%':
8052 func (stream, "%%");
8053 break;
8054
8055 case 'u':
8056 if (thumb && ifthen_state)
8057 is_unpredictable = TRUE;
8058
8059 /* Fall through. */
8060 case 'c':
8061 if (thumb && ifthen_state)
8062 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8063 break;
8064
8065 case 'A':
8066 {
8067 static const unsigned char enc[16] =
8068 {
8069 0x4, 0x14, /* st4 0,1 */
8070 0x4, /* st1 2 */
8071 0x4, /* st2 3 */
8072 0x3, /* st3 4 */
8073 0x13, /* st3 5 */
8074 0x3, /* st1 6 */
8075 0x1, /* st1 7 */
8076 0x2, /* st2 8 */
8077 0x12, /* st2 9 */
8078 0x2, /* st1 10 */
8079 0, 0, 0, 0, 0
8080 };
8081 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8082 int rn = ((given >> 16) & 0xf);
8083 int rm = ((given >> 0) & 0xf);
8084 int align = ((given >> 4) & 0x3);
8085 int type = ((given >> 8) & 0xf);
8086 int n = enc[type] & 0xf;
8087 int stride = (enc[type] >> 4) + 1;
8088 int ix;
8089
8090 func (stream, "{");
8091 if (stride > 1)
8092 for (ix = 0; ix != n; ix++)
8093 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
8094 else if (n == 1)
8095 func (stream, "d%d", rd);
8096 else
8097 func (stream, "d%d-d%d", rd, rd + n - 1);
8098 func (stream, "}, [%s", arm_regnames[rn]);
8099 if (align)
8100 func (stream, " :%d", 32 << align);
8101 func (stream, "]");
8102 if (rm == 0xd)
8103 func (stream, "!");
8104 else if (rm != 0xf)
8105 func (stream, ", %s", arm_regnames[rm]);
8106 }
8107 break;
8108
8109 case 'B':
8110 {
8111 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8112 int rn = ((given >> 16) & 0xf);
8113 int rm = ((given >> 0) & 0xf);
8114 int idx_align = ((given >> 4) & 0xf);
8115 int align = 0;
8116 int size = ((given >> 10) & 0x3);
8117 int idx = idx_align >> (size + 1);
8118 int length = ((given >> 8) & 3) + 1;
8119 int stride = 1;
8120 int i;
8121
8122 if (length > 1 && size > 0)
8123 stride = (idx_align & (1 << size)) ? 2 : 1;
8124
8125 switch (length)
8126 {
8127 case 1:
8128 {
8129 int amask = (1 << size) - 1;
8130 if ((idx_align & (1 << size)) != 0)
8131 return FALSE;
8132 if (size > 0)
8133 {
8134 if ((idx_align & amask) == amask)
8135 align = 8 << size;
8136 else if ((idx_align & amask) != 0)
8137 return FALSE;
8138 }
8139 }
8140 break;
8141
8142 case 2:
8143 if (size == 2 && (idx_align & 2) != 0)
8144 return FALSE;
8145 align = (idx_align & 1) ? 16 << size : 0;
8146 break;
8147
8148 case 3:
8149 if ((size == 2 && (idx_align & 3) != 0)
8150 || (idx_align & 1) != 0)
8151 return FALSE;
8152 break;
8153
8154 case 4:
8155 if (size == 2)
8156 {
8157 if ((idx_align & 3) == 3)
8158 return FALSE;
8159 align = (idx_align & 3) * 64;
8160 }
8161 else
8162 align = (idx_align & 1) ? 32 << size : 0;
8163 break;
8164
8165 default:
8166 abort ();
8167 }
8168
8169 func (stream, "{");
8170 for (i = 0; i < length; i++)
8171 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
8172 rd + i * stride, idx);
8173 func (stream, "}, [%s", arm_regnames[rn]);
8174 if (align)
8175 func (stream, " :%d", align);
8176 func (stream, "]");
8177 if (rm == 0xd)
8178 func (stream, "!");
8179 else if (rm != 0xf)
8180 func (stream, ", %s", arm_regnames[rm]);
8181 }
8182 break;
8183
8184 case 'C':
8185 {
8186 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8187 int rn = ((given >> 16) & 0xf);
8188 int rm = ((given >> 0) & 0xf);
8189 int align = ((given >> 4) & 0x1);
8190 int size = ((given >> 6) & 0x3);
8191 int type = ((given >> 8) & 0x3);
8192 int n = type + 1;
8193 int stride = ((given >> 5) & 0x1);
8194 int ix;
8195
8196 if (stride && (n == 1))
8197 n++;
8198 else
8199 stride++;
8200
8201 func (stream, "{");
8202 if (stride > 1)
8203 for (ix = 0; ix != n; ix++)
8204 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
8205 else if (n == 1)
8206 func (stream, "d%d[]", rd);
8207 else
8208 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
8209 func (stream, "}, [%s", arm_regnames[rn]);
8210 if (align)
8211 {
8212 align = (8 * (type + 1)) << size;
8213 if (type == 3)
8214 align = (size > 1) ? align >> 1 : align;
8215 if (type == 2 || (type == 0 && !size))
8216 func (stream, " :<bad align %d>", align);
8217 else
8218 func (stream, " :%d", align);
8219 }
8220 func (stream, "]");
8221 if (rm == 0xd)
8222 func (stream, "!");
8223 else if (rm != 0xf)
8224 func (stream, ", %s", arm_regnames[rm]);
8225 }
8226 break;
8227
8228 case 'D':
8229 {
8230 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
8231 int size = (given >> 20) & 3;
8232 int reg = raw_reg & ((4 << size) - 1);
8233 int ix = raw_reg >> size >> 2;
8234
8235 func (stream, "d%d[%d]", reg, ix);
8236 }
8237 break;
8238
8239 case 'E':
8240 /* Neon encoded constant for mov, mvn, vorr, vbic. */
8241 {
8242 int bits = 0;
8243 int cmode = (given >> 8) & 0xf;
8244 int op = (given >> 5) & 0x1;
8245 unsigned long value = 0, hival = 0;
8246 unsigned shift;
8247 int size = 0;
8248 int isfloat = 0;
8249
8250 bits |= ((given >> 24) & 1) << 7;
8251 bits |= ((given >> 16) & 7) << 4;
8252 bits |= ((given >> 0) & 15) << 0;
8253
8254 if (cmode < 8)
8255 {
8256 shift = (cmode >> 1) & 3;
8257 value = (unsigned long) bits << (8 * shift);
8258 size = 32;
8259 }
8260 else if (cmode < 12)
8261 {
8262 shift = (cmode >> 1) & 1;
8263 value = (unsigned long) bits << (8 * shift);
8264 size = 16;
8265 }
8266 else if (cmode < 14)
8267 {
8268 shift = (cmode & 1) + 1;
8269 value = (unsigned long) bits << (8 * shift);
8270 value |= (1ul << (8 * shift)) - 1;
8271 size = 32;
8272 }
8273 else if (cmode == 14)
8274 {
8275 if (op)
8276 {
8277 /* Bit replication into bytes. */
8278 int ix;
8279 unsigned long mask;
8280
8281 value = 0;
8282 hival = 0;
8283 for (ix = 7; ix >= 0; ix--)
8284 {
8285 mask = ((bits >> ix) & 1) ? 0xff : 0;
8286 if (ix <= 3)
8287 value = (value << 8) | mask;
8288 else
8289 hival = (hival << 8) | mask;
8290 }
8291 size = 64;
8292 }
8293 else
8294 {
8295 /* Byte replication. */
8296 value = (unsigned long) bits;
8297 size = 8;
8298 }
8299 }
8300 else if (!op)
8301 {
8302 /* Floating point encoding. */
8303 int tmp;
8304
8305 value = (unsigned long) (bits & 0x7f) << 19;
8306 value |= (unsigned long) (bits & 0x80) << 24;
8307 tmp = bits & 0x40 ? 0x3c : 0x40;
8308 value |= (unsigned long) tmp << 24;
8309 size = 32;
8310 isfloat = 1;
8311 }
8312 else
8313 {
8314 func (stream, "<illegal constant %.8x:%x:%x>",
8315 bits, cmode, op);
8316 size = 32;
8317 break;
8318 }
8319 switch (size)
8320 {
8321 case 8:
8322 func (stream, "#%ld\t; 0x%.2lx", value, value);
8323 break;
8324
8325 case 16:
8326 func (stream, "#%ld\t; 0x%.4lx", value, value);
8327 break;
8328
8329 case 32:
8330 if (isfloat)
8331 {
8332 unsigned char valbytes[4];
8333 double fvalue;
8334
8335 /* Do this a byte at a time so we don't have to
8336 worry about the host's endianness. */
8337 valbytes[0] = value & 0xff;
8338 valbytes[1] = (value >> 8) & 0xff;
8339 valbytes[2] = (value >> 16) & 0xff;
8340 valbytes[3] = (value >> 24) & 0xff;
8341
8342 floatformat_to_double
8343 (& floatformat_ieee_single_little, valbytes,
8344 & fvalue);
8345
8346 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
8347 value);
8348 }
8349 else
8350 func (stream, "#%ld\t; 0x%.8lx",
8351 (long) (((value & 0x80000000L) != 0)
8352 ? value | ~0xffffffffL : value),
8353 value);
8354 break;
8355
8356 case 64:
8357 func (stream, "#0x%.8lx%.8lx", hival, value);
8358 break;
8359
8360 default:
8361 abort ();
8362 }
8363 }
8364 break;
8365
8366 case 'F':
8367 {
8368 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
8369 int num = (given >> 8) & 0x3;
8370
8371 if (!num)
8372 func (stream, "{d%d}", regno);
8373 else if (num + regno >= 32)
8374 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
8375 else
8376 func (stream, "{d%d-d%d}", regno, regno + num);
8377 }
8378 break;
8379
8380
8381 case '0': case '1': case '2': case '3': case '4':
8382 case '5': case '6': case '7': case '8': case '9':
8383 {
8384 int width;
8385 unsigned long value;
8386
8387 c = arm_decode_bitfield (c, given, &value, &width);
8388
8389 switch (*c)
8390 {
8391 case 'r':
8392 func (stream, "%s", arm_regnames[value]);
8393 break;
8394 case 'd':
8395 func (stream, "%ld", value);
8396 value_in_comment = value;
8397 break;
8398 case 'e':
8399 func (stream, "%ld", (1ul << width) - value);
8400 break;
8401
8402 case 'S':
8403 case 'T':
8404 case 'U':
8405 /* Various width encodings. */
8406 {
8407 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
8408 int limit;
8409 unsigned low, high;
8410
8411 c++;
8412 if (*c >= '0' && *c <= '9')
8413 limit = *c - '0';
8414 else if (*c >= 'a' && *c <= 'f')
8415 limit = *c - 'a' + 10;
8416 else
8417 abort ();
8418 low = limit >> 2;
8419 high = limit & 3;
8420
8421 if (value < low || value > high)
8422 func (stream, "<illegal width %d>", base << value);
8423 else
8424 func (stream, "%d", base << value);
8425 }
8426 break;
8427 case 'R':
8428 if (given & (1 << 6))
8429 goto Q;
8430 /* FALLTHROUGH */
8431 case 'D':
8432 func (stream, "d%ld", value);
8433 break;
8434 case 'Q':
8435 Q:
8436 if (value & 1)
8437 func (stream, "<illegal reg q%ld.5>", value >> 1);
8438 else
8439 func (stream, "q%ld", value >> 1);
8440 break;
8441
8442 case '`':
8443 c++;
8444 if (value == 0)
8445 func (stream, "%c", *c);
8446 break;
8447 case '\'':
8448 c++;
8449 if (value == ((1ul << width) - 1))
8450 func (stream, "%c", *c);
8451 break;
8452 case '?':
8453 func (stream, "%c", c[(1 << width) - (int) value]);
8454 c += 1 << width;
8455 break;
8456 default:
8457 abort ();
8458 }
8459 }
8460 break;
8461
8462 default:
8463 abort ();
8464 }
8465 }
8466 else
8467 func (stream, "%c", *c);
8468 }
8469
8470 if (value_in_comment > 32 || value_in_comment < -16)
8471 func (stream, "\t; 0x%lx", value_in_comment);
8472
8473 if (is_unpredictable)
8474 func (stream, UNPREDICTABLE_INSTRUCTION);
8475
8476 return TRUE;
8477 }
8478 }
8479 return FALSE;
8480 }
8481
8482 /* Print one mve instruction on INFO->STREAM.
8483 Return TRUE if the instuction matched, FALSE if this is not a
8484 recognised mve instruction. */
8485
8486 static bfd_boolean
8487 print_insn_mve (struct disassemble_info *info, long given)
8488 {
8489 const struct mopcode32 *insn;
8490 void *stream = info->stream;
8491 fprintf_ftype func = info->fprintf_func;
8492
8493 for (insn = mve_opcodes; insn->assembler; insn++)
8494 {
8495 if (((given & insn->mask) == insn->value)
8496 && !is_mve_encoding_conflict (given, insn->mve_op))
8497 {
8498 signed long value_in_comment = 0;
8499 bfd_boolean is_unpredictable = FALSE;
8500 bfd_boolean is_undefined = FALSE;
8501 const char *c;
8502 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
8503 enum mve_undefined undefined_cond = UNDEF_NONE;
8504
8505 /* Most vector mve instruction are illegal in a it block.
8506 There are a few exceptions; check for them. */
8507 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
8508 {
8509 is_unpredictable = TRUE;
8510 unpredictable_cond = UNPRED_IT_BLOCK;
8511 }
8512 else if (is_mve_unpredictable (given, insn->mve_op,
8513 &unpredictable_cond))
8514 is_unpredictable = TRUE;
8515
8516 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
8517 is_undefined = TRUE;
8518
8519 for (c = insn->assembler; *c; c++)
8520 {
8521 if (*c == '%')
8522 {
8523 switch (*++c)
8524 {
8525 case '%':
8526 func (stream, "%%");
8527 break;
8528
8529 case 'a':
8530 /* Don't print anything for '+' as it is implied. */
8531 if (arm_decode_field (given, 23, 23) == 0)
8532 func (stream, "-");
8533 break;
8534
8535 case 'c':
8536 if (ifthen_state)
8537 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8538 break;
8539
8540 case 'd':
8541 print_mve_vld_str_addr (info, given, insn->mve_op);
8542 break;
8543
8544 case 'i':
8545 {
8546 long mve_mask = mve_extract_pred_mask (given);
8547 func (stream, "%s", mve_predicatenames[mve_mask]);
8548 }
8549 break;
8550
8551 case 'n':
8552 print_vec_condition (info, given, insn->mve_op);
8553 break;
8554
8555 case 'o':
8556 if (arm_decode_field (given, 0, 0) == 1)
8557 {
8558 unsigned long size
8559 = arm_decode_field (given, 4, 4)
8560 | (arm_decode_field (given, 6, 6) << 1);
8561
8562 func (stream, ", uxtw #%lu", size);
8563 }
8564 break;
8565
8566 case 'm':
8567 print_mve_rounding_mode (info, given, insn->mve_op);
8568 break;
8569
8570 case 's':
8571 print_mve_vcvt_size (info, given, insn->mve_op);
8572 break;
8573
8574 case 'u':
8575 {
8576 unsigned long op1 = arm_decode_field (given, 21, 22);
8577
8578 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
8579 {
8580 /* Check for signed. */
8581 if (arm_decode_field (given, 23, 23) == 0)
8582 {
8583 /* We don't print 's' for S32. */
8584 if ((arm_decode_field (given, 5, 6) == 0)
8585 && ((op1 == 0) || (op1 == 1)))
8586 ;
8587 else
8588 func (stream, "s");
8589 }
8590 else
8591 func (stream, "u");
8592 }
8593 else
8594 {
8595 if (arm_decode_field (given, 28, 28) == 0)
8596 func (stream, "s");
8597 else
8598 func (stream, "u");
8599 }
8600 }
8601 break;
8602
8603 case 'v':
8604 print_instruction_predicate (info);
8605 break;
8606
8607 case 'w':
8608 if (arm_decode_field (given, 21, 21) == 1)
8609 func (stream, "!");
8610 break;
8611
8612 case 'B':
8613 print_mve_register_blocks (info, given, insn->mve_op);
8614 break;
8615
8616 case 'E':
8617 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
8618
8619 print_simd_imm8 (info, given, 28, insn);
8620 break;
8621
8622 case 'N':
8623 print_mve_vmov_index (info, given);
8624 break;
8625
8626 case 'T':
8627 if (arm_decode_field (given, 12, 12) == 0)
8628 func (stream, "b");
8629 else
8630 func (stream, "t");
8631 break;
8632
8633 case 'X':
8634 if (arm_decode_field (given, 12, 12) == 1)
8635 func (stream, "x");
8636 break;
8637
8638 case '0': case '1': case '2': case '3': case '4':
8639 case '5': case '6': case '7': case '8': case '9':
8640 {
8641 int width;
8642 unsigned long value;
8643
8644 c = arm_decode_bitfield (c, given, &value, &width);
8645
8646 switch (*c)
8647 {
8648 case 'Z':
8649 if (value == 13)
8650 is_unpredictable = TRUE;
8651 else if (value == 15)
8652 func (stream, "zr");
8653 else
8654 func (stream, "%s", arm_regnames[value]);
8655 break;
8656 case 's':
8657 print_mve_size (info,
8658 value,
8659 insn->mve_op);
8660 break;
8661 case 'I':
8662 if (value == 1)
8663 func (stream, "i");
8664 break;
8665 case 'A':
8666 if (value == 1)
8667 func (stream, "a");
8668 break;
8669 case 'h':
8670 {
8671 unsigned int odd_reg = (value << 1) | 1;
8672 func (stream, "%s", arm_regnames[odd_reg]);
8673 }
8674 break;
8675 case 'i':
8676 {
8677 unsigned long imm
8678 = arm_decode_field (given, 0, 6);
8679 unsigned long mod_imm = imm;
8680
8681 switch (insn->mve_op)
8682 {
8683 case MVE_VLDRW_GATHER_T5:
8684 case MVE_VSTRW_SCATTER_T5:
8685 mod_imm = mod_imm << 2;
8686 break;
8687 case MVE_VSTRD_SCATTER_T6:
8688 case MVE_VLDRD_GATHER_T6:
8689 mod_imm = mod_imm << 3;
8690 break;
8691
8692 default:
8693 break;
8694 }
8695
8696 func (stream, "%lu", mod_imm);
8697 }
8698 break;
8699 case 'k':
8700 func (stream, "%lu", 64 - value);
8701 break;
8702 case 'l':
8703 {
8704 unsigned int even_reg = value << 1;
8705 func (stream, "%s", arm_regnames[even_reg]);
8706 }
8707 break;
8708 case 'u':
8709 switch (value)
8710 {
8711 case 0:
8712 func (stream, "1");
8713 break;
8714 case 1:
8715 func (stream, "2");
8716 break;
8717 case 2:
8718 func (stream, "4");
8719 break;
8720 case 3:
8721 func (stream, "8");
8722 break;
8723 default:
8724 break;
8725 }
8726 break;
8727 case 'o':
8728 print_mve_rotate (info, value, width);
8729 break;
8730 case 'r':
8731 func (stream, "%s", arm_regnames[value]);
8732 break;
8733 case 'd':
8734 if (insn->mve_op == MVE_VQSHL_T2
8735 || insn->mve_op == MVE_VQSHLU_T3
8736 || insn->mve_op == MVE_VRSHR
8737 || insn->mve_op == MVE_VRSHRN
8738 || insn->mve_op == MVE_VSHL_T1
8739 || insn->mve_op == MVE_VSHLL_T1
8740 || insn->mve_op == MVE_VSHR
8741 || insn->mve_op == MVE_VSHRN
8742 || insn->mve_op == MVE_VSLI
8743 || insn->mve_op == MVE_VSRI)
8744 print_mve_shift_n (info, given, insn->mve_op);
8745 else if (insn->mve_op == MVE_VSHLL_T2)
8746 {
8747 switch (value)
8748 {
8749 case 0x00:
8750 func (stream, "8");
8751 break;
8752 case 0x01:
8753 func (stream, "16");
8754 break;
8755 case 0x10:
8756 print_mve_undefined (info, UNDEF_SIZE_0);
8757 break;
8758 default:
8759 assert (0);
8760 break;
8761 }
8762 }
8763 else
8764 {
8765 if (insn->mve_op == MVE_VSHLC && value == 0)
8766 value = 32;
8767 func (stream, "%ld", value);
8768 value_in_comment = value;
8769 }
8770 break;
8771 case 'F':
8772 func (stream, "s%ld", value);
8773 break;
8774 case 'Q':
8775 if (value & 0x8)
8776 func (stream, "<illegal reg q%ld.5>", value);
8777 else
8778 func (stream, "q%ld", value);
8779 break;
8780 case 'x':
8781 func (stream, "0x%08lx", value);
8782 break;
8783 default:
8784 abort ();
8785 }
8786 break;
8787 default:
8788 abort ();
8789 }
8790 }
8791 }
8792 else
8793 func (stream, "%c", *c);
8794 }
8795
8796 if (value_in_comment > 32 || value_in_comment < -16)
8797 func (stream, "\t; 0x%lx", value_in_comment);
8798
8799 if (is_unpredictable)
8800 print_mve_unpredictable (info, unpredictable_cond);
8801
8802 if (is_undefined)
8803 print_mve_undefined (info, undefined_cond);
8804
8805 if ((vpt_block_state.in_vpt_block == FALSE)
8806 && !ifthen_state
8807 && (is_vpt_instruction (given) == TRUE))
8808 mark_inside_vpt_block (given);
8809 else if (vpt_block_state.in_vpt_block == TRUE)
8810 update_vpt_block_state ();
8811
8812 return TRUE;
8813 }
8814 }
8815 return FALSE;
8816 }
8817
8818
8819 /* Return the name of a v7A special register. */
8820
8821 static const char *
8822 banked_regname (unsigned reg)
8823 {
8824 switch (reg)
8825 {
8826 case 15: return "CPSR";
8827 case 32: return "R8_usr";
8828 case 33: return "R9_usr";
8829 case 34: return "R10_usr";
8830 case 35: return "R11_usr";
8831 case 36: return "R12_usr";
8832 case 37: return "SP_usr";
8833 case 38: return "LR_usr";
8834 case 40: return "R8_fiq";
8835 case 41: return "R9_fiq";
8836 case 42: return "R10_fiq";
8837 case 43: return "R11_fiq";
8838 case 44: return "R12_fiq";
8839 case 45: return "SP_fiq";
8840 case 46: return "LR_fiq";
8841 case 48: return "LR_irq";
8842 case 49: return "SP_irq";
8843 case 50: return "LR_svc";
8844 case 51: return "SP_svc";
8845 case 52: return "LR_abt";
8846 case 53: return "SP_abt";
8847 case 54: return "LR_und";
8848 case 55: return "SP_und";
8849 case 60: return "LR_mon";
8850 case 61: return "SP_mon";
8851 case 62: return "ELR_hyp";
8852 case 63: return "SP_hyp";
8853 case 79: return "SPSR";
8854 case 110: return "SPSR_fiq";
8855 case 112: return "SPSR_irq";
8856 case 114: return "SPSR_svc";
8857 case 116: return "SPSR_abt";
8858 case 118: return "SPSR_und";
8859 case 124: return "SPSR_mon";
8860 case 126: return "SPSR_hyp";
8861 default: return NULL;
8862 }
8863 }
8864
8865 /* Return the name of the DMB/DSB option. */
8866 static const char *
8867 data_barrier_option (unsigned option)
8868 {
8869 switch (option & 0xf)
8870 {
8871 case 0xf: return "sy";
8872 case 0xe: return "st";
8873 case 0xd: return "ld";
8874 case 0xb: return "ish";
8875 case 0xa: return "ishst";
8876 case 0x9: return "ishld";
8877 case 0x7: return "un";
8878 case 0x6: return "unst";
8879 case 0x5: return "nshld";
8880 case 0x3: return "osh";
8881 case 0x2: return "oshst";
8882 case 0x1: return "oshld";
8883 default: return NULL;
8884 }
8885 }
8886
8887 /* Print one ARM instruction from PC on INFO->STREAM. */
8888
8889 static void
8890 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
8891 {
8892 const struct opcode32 *insn;
8893 void *stream = info->stream;
8894 fprintf_ftype func = info->fprintf_func;
8895 struct arm_private_data *private_data = info->private_data;
8896
8897 if (print_insn_coprocessor (pc, info, given, FALSE))
8898 return;
8899
8900 if (print_insn_neon (info, given, FALSE))
8901 return;
8902
8903 for (insn = arm_opcodes; insn->assembler; insn++)
8904 {
8905 if ((given & insn->mask) != insn->value)
8906 continue;
8907
8908 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
8909 continue;
8910
8911 /* Special case: an instruction with all bits set in the condition field
8912 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
8913 or by the catchall at the end of the table. */
8914 if ((given & 0xF0000000) != 0xF0000000
8915 || (insn->mask & 0xF0000000) == 0xF0000000
8916 || (insn->mask == 0 && insn->value == 0))
8917 {
8918 unsigned long u_reg = 16;
8919 unsigned long U_reg = 16;
8920 bfd_boolean is_unpredictable = FALSE;
8921 signed long value_in_comment = 0;
8922 const char *c;
8923
8924 for (c = insn->assembler; *c; c++)
8925 {
8926 if (*c == '%')
8927 {
8928 bfd_boolean allow_unpredictable = FALSE;
8929
8930 switch (*++c)
8931 {
8932 case '%':
8933 func (stream, "%%");
8934 break;
8935
8936 case 'a':
8937 value_in_comment = print_arm_address (pc, info, given);
8938 break;
8939
8940 case 'P':
8941 /* Set P address bit and use normal address
8942 printing routine. */
8943 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
8944 break;
8945
8946 case 'S':
8947 allow_unpredictable = TRUE;
8948 /* Fall through. */
8949 case 's':
8950 if ((given & 0x004f0000) == 0x004f0000)
8951 {
8952 /* PC relative with immediate offset. */
8953 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
8954
8955 if (PRE_BIT_SET)
8956 {
8957 /* Elide positive zero offset. */
8958 if (offset || NEGATIVE_BIT_SET)
8959 func (stream, "[pc, #%s%d]\t; ",
8960 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8961 else
8962 func (stream, "[pc]\t; ");
8963 if (NEGATIVE_BIT_SET)
8964 offset = -offset;
8965 info->print_address_func (offset + pc + 8, info);
8966 }
8967 else
8968 {
8969 /* Always show the offset. */
8970 func (stream, "[pc], #%s%d",
8971 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8972 if (! allow_unpredictable)
8973 is_unpredictable = TRUE;
8974 }
8975 }
8976 else
8977 {
8978 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
8979
8980 func (stream, "[%s",
8981 arm_regnames[(given >> 16) & 0xf]);
8982
8983 if (PRE_BIT_SET)
8984 {
8985 if (IMMEDIATE_BIT_SET)
8986 {
8987 /* Elide offset for non-writeback
8988 positive zero. */
8989 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
8990 || offset)
8991 func (stream, ", #%s%d",
8992 NEGATIVE_BIT_SET ? "-" : "", offset);
8993
8994 if (NEGATIVE_BIT_SET)
8995 offset = -offset;
8996
8997 value_in_comment = offset;
8998 }
8999 else
9000 {
9001 /* Register Offset or Register Pre-Indexed. */
9002 func (stream, ", %s%s",
9003 NEGATIVE_BIT_SET ? "-" : "",
9004 arm_regnames[given & 0xf]);
9005
9006 /* Writing back to the register that is the source/
9007 destination of the load/store is unpredictable. */
9008 if (! allow_unpredictable
9009 && WRITEBACK_BIT_SET
9010 && ((given & 0xf) == ((given >> 12) & 0xf)))
9011 is_unpredictable = TRUE;
9012 }
9013
9014 func (stream, "]%s",
9015 WRITEBACK_BIT_SET ? "!" : "");
9016 }
9017 else
9018 {
9019 if (IMMEDIATE_BIT_SET)
9020 {
9021 /* Immediate Post-indexed. */
9022 /* PR 10924: Offset must be printed, even if it is zero. */
9023 func (stream, "], #%s%d",
9024 NEGATIVE_BIT_SET ? "-" : "", offset);
9025 if (NEGATIVE_BIT_SET)
9026 offset = -offset;
9027 value_in_comment = offset;
9028 }
9029 else
9030 {
9031 /* Register Post-indexed. */
9032 func (stream, "], %s%s",
9033 NEGATIVE_BIT_SET ? "-" : "",
9034 arm_regnames[given & 0xf]);
9035
9036 /* Writing back to the register that is the source/
9037 destination of the load/store is unpredictable. */
9038 if (! allow_unpredictable
9039 && (given & 0xf) == ((given >> 12) & 0xf))
9040 is_unpredictable = TRUE;
9041 }
9042
9043 if (! allow_unpredictable)
9044 {
9045 /* Writeback is automatically implied by post- addressing.
9046 Setting the W bit is unnecessary and ARM specify it as
9047 being unpredictable. */
9048 if (WRITEBACK_BIT_SET
9049 /* Specifying the PC register as the post-indexed
9050 registers is also unpredictable. */
9051 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
9052 is_unpredictable = TRUE;
9053 }
9054 }
9055 }
9056 break;
9057
9058 case 'b':
9059 {
9060 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
9061 info->print_address_func (disp * 4 + pc + 8, info);
9062 }
9063 break;
9064
9065 case 'c':
9066 if (((given >> 28) & 0xf) != 0xe)
9067 func (stream, "%s",
9068 arm_conditional [(given >> 28) & 0xf]);
9069 break;
9070
9071 case 'm':
9072 {
9073 int started = 0;
9074 int reg;
9075
9076 func (stream, "{");
9077 for (reg = 0; reg < 16; reg++)
9078 if ((given & (1 << reg)) != 0)
9079 {
9080 if (started)
9081 func (stream, ", ");
9082 started = 1;
9083 func (stream, "%s", arm_regnames[reg]);
9084 }
9085 func (stream, "}");
9086 if (! started)
9087 is_unpredictable = TRUE;
9088 }
9089 break;
9090
9091 case 'q':
9092 arm_decode_shift (given, func, stream, FALSE);
9093 break;
9094
9095 case 'o':
9096 if ((given & 0x02000000) != 0)
9097 {
9098 unsigned int rotate = (given & 0xf00) >> 7;
9099 unsigned int immed = (given & 0xff);
9100 unsigned int a, i;
9101
9102 a = (((immed << (32 - rotate))
9103 | (immed >> rotate)) & 0xffffffff);
9104 /* If there is another encoding with smaller rotate,
9105 the rotate should be specified directly. */
9106 for (i = 0; i < 32; i += 2)
9107 if ((a << i | a >> (32 - i)) <= 0xff)
9108 break;
9109
9110 if (i != rotate)
9111 func (stream, "#%d, %d", immed, rotate);
9112 else
9113 func (stream, "#%d", a);
9114 value_in_comment = a;
9115 }
9116 else
9117 arm_decode_shift (given, func, stream, TRUE);
9118 break;
9119
9120 case 'p':
9121 if ((given & 0x0000f000) == 0x0000f000)
9122 {
9123 arm_feature_set arm_ext_v6 =
9124 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
9125
9126 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9127 mechanism for setting PSR flag bits. They are
9128 obsolete in V6 onwards. */
9129 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
9130 arm_ext_v6))
9131 func (stream, "p");
9132 else
9133 is_unpredictable = TRUE;
9134 }
9135 break;
9136
9137 case 't':
9138 if ((given & 0x01200000) == 0x00200000)
9139 func (stream, "t");
9140 break;
9141
9142 case 'A':
9143 {
9144 int offset = given & 0xff;
9145
9146 value_in_comment = offset * 4;
9147 if (NEGATIVE_BIT_SET)
9148 value_in_comment = - value_in_comment;
9149
9150 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
9151
9152 if (PRE_BIT_SET)
9153 {
9154 if (offset)
9155 func (stream, ", #%d]%s",
9156 (int) value_in_comment,
9157 WRITEBACK_BIT_SET ? "!" : "");
9158 else
9159 func (stream, "]");
9160 }
9161 else
9162 {
9163 func (stream, "]");
9164
9165 if (WRITEBACK_BIT_SET)
9166 {
9167 if (offset)
9168 func (stream, ", #%d", (int) value_in_comment);
9169 }
9170 else
9171 {
9172 func (stream, ", {%d}", (int) offset);
9173 value_in_comment = offset;
9174 }
9175 }
9176 }
9177 break;
9178
9179 case 'B':
9180 /* Print ARM V5 BLX(1) address: pc+25 bits. */
9181 {
9182 bfd_vma address;
9183 bfd_vma offset = 0;
9184
9185 if (! NEGATIVE_BIT_SET)
9186 /* Is signed, hi bits should be ones. */
9187 offset = (-1) ^ 0x00ffffff;
9188
9189 /* Offset is (SignExtend(offset field)<<2). */
9190 offset += given & 0x00ffffff;
9191 offset <<= 2;
9192 address = offset + pc + 8;
9193
9194 if (given & 0x01000000)
9195 /* H bit allows addressing to 2-byte boundaries. */
9196 address += 2;
9197
9198 info->print_address_func (address, info);
9199 }
9200 break;
9201
9202 case 'C':
9203 if ((given & 0x02000200) == 0x200)
9204 {
9205 const char * name;
9206 unsigned sysm = (given & 0x004f0000) >> 16;
9207
9208 sysm |= (given & 0x300) >> 4;
9209 name = banked_regname (sysm);
9210
9211 if (name != NULL)
9212 func (stream, "%s", name);
9213 else
9214 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
9215 }
9216 else
9217 {
9218 func (stream, "%cPSR_",
9219 (given & 0x00400000) ? 'S' : 'C');
9220 if (given & 0x80000)
9221 func (stream, "f");
9222 if (given & 0x40000)
9223 func (stream, "s");
9224 if (given & 0x20000)
9225 func (stream, "x");
9226 if (given & 0x10000)
9227 func (stream, "c");
9228 }
9229 break;
9230
9231 case 'U':
9232 if ((given & 0xf0) == 0x60)
9233 {
9234 switch (given & 0xf)
9235 {
9236 case 0xf: func (stream, "sy"); break;
9237 default:
9238 func (stream, "#%d", (int) given & 0xf);
9239 break;
9240 }
9241 }
9242 else
9243 {
9244 const char * opt = data_barrier_option (given & 0xf);
9245 if (opt != NULL)
9246 func (stream, "%s", opt);
9247 else
9248 func (stream, "#%d", (int) given & 0xf);
9249 }
9250 break;
9251
9252 case '0': case '1': case '2': case '3': case '4':
9253 case '5': case '6': case '7': case '8': case '9':
9254 {
9255 int width;
9256 unsigned long value;
9257
9258 c = arm_decode_bitfield (c, given, &value, &width);
9259
9260 switch (*c)
9261 {
9262 case 'R':
9263 if (value == 15)
9264 is_unpredictable = TRUE;
9265 /* Fall through. */
9266 case 'r':
9267 case 'T':
9268 /* We want register + 1 when decoding T. */
9269 if (*c == 'T')
9270 ++value;
9271
9272 if (c[1] == 'u')
9273 {
9274 /* Eat the 'u' character. */
9275 ++ c;
9276
9277 if (u_reg == value)
9278 is_unpredictable = TRUE;
9279 u_reg = value;
9280 }
9281 if (c[1] == 'U')
9282 {
9283 /* Eat the 'U' character. */
9284 ++ c;
9285
9286 if (U_reg == value)
9287 is_unpredictable = TRUE;
9288 U_reg = value;
9289 }
9290 func (stream, "%s", arm_regnames[value]);
9291 break;
9292 case 'd':
9293 func (stream, "%ld", value);
9294 value_in_comment = value;
9295 break;
9296 case 'b':
9297 func (stream, "%ld", value * 8);
9298 value_in_comment = value * 8;
9299 break;
9300 case 'W':
9301 func (stream, "%ld", value + 1);
9302 value_in_comment = value + 1;
9303 break;
9304 case 'x':
9305 func (stream, "0x%08lx", value);
9306
9307 /* Some SWI instructions have special
9308 meanings. */
9309 if ((given & 0x0fffffff) == 0x0FF00000)
9310 func (stream, "\t; IMB");
9311 else if ((given & 0x0fffffff) == 0x0FF00001)
9312 func (stream, "\t; IMBRange");
9313 break;
9314 case 'X':
9315 func (stream, "%01lx", value & 0xf);
9316 value_in_comment = value;
9317 break;
9318 case '`':
9319 c++;
9320 if (value == 0)
9321 func (stream, "%c", *c);
9322 break;
9323 case '\'':
9324 c++;
9325 if (value == ((1ul << width) - 1))
9326 func (stream, "%c", *c);
9327 break;
9328 case '?':
9329 func (stream, "%c", c[(1 << width) - (int) value]);
9330 c += 1 << width;
9331 break;
9332 default:
9333 abort ();
9334 }
9335 }
9336 break;
9337
9338 case 'e':
9339 {
9340 int imm;
9341
9342 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
9343 func (stream, "%d", imm);
9344 value_in_comment = imm;
9345 }
9346 break;
9347
9348 case 'E':
9349 /* LSB and WIDTH fields of BFI or BFC. The machine-
9350 language instruction encodes LSB and MSB. */
9351 {
9352 long msb = (given & 0x001f0000) >> 16;
9353 long lsb = (given & 0x00000f80) >> 7;
9354 long w = msb - lsb + 1;
9355
9356 if (w > 0)
9357 func (stream, "#%lu, #%lu", lsb, w);
9358 else
9359 func (stream, "(invalid: %lu:%lu)", lsb, msb);
9360 }
9361 break;
9362
9363 case 'R':
9364 /* Get the PSR/banked register name. */
9365 {
9366 const char * name;
9367 unsigned sysm = (given & 0x004f0000) >> 16;
9368
9369 sysm |= (given & 0x300) >> 4;
9370 name = banked_regname (sysm);
9371
9372 if (name != NULL)
9373 func (stream, "%s", name);
9374 else
9375 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
9376 }
9377 break;
9378
9379 case 'V':
9380 /* 16-bit unsigned immediate from a MOVT or MOVW
9381 instruction, encoded in bits 0:11 and 15:19. */
9382 {
9383 long hi = (given & 0x000f0000) >> 4;
9384 long lo = (given & 0x00000fff);
9385 long imm16 = hi | lo;
9386
9387 func (stream, "#%lu", imm16);
9388 value_in_comment = imm16;
9389 }
9390 break;
9391
9392 default:
9393 abort ();
9394 }
9395 }
9396 else
9397 func (stream, "%c", *c);
9398 }
9399
9400 if (value_in_comment > 32 || value_in_comment < -16)
9401 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
9402
9403 if (is_unpredictable)
9404 func (stream, UNPREDICTABLE_INSTRUCTION);
9405
9406 return;
9407 }
9408 }
9409 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
9410 return;
9411 }
9412
9413 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
9414
9415 static void
9416 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
9417 {
9418 const struct opcode16 *insn;
9419 void *stream = info->stream;
9420 fprintf_ftype func = info->fprintf_func;
9421
9422 for (insn = thumb_opcodes; insn->assembler; insn++)
9423 if ((given & insn->mask) == insn->value)
9424 {
9425 signed long value_in_comment = 0;
9426 const char *c = insn->assembler;
9427
9428 for (; *c; c++)
9429 {
9430 int domaskpc = 0;
9431 int domasklr = 0;
9432
9433 if (*c != '%')
9434 {
9435 func (stream, "%c", *c);
9436 continue;
9437 }
9438
9439 switch (*++c)
9440 {
9441 case '%':
9442 func (stream, "%%");
9443 break;
9444
9445 case 'c':
9446 if (ifthen_state)
9447 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9448 break;
9449
9450 case 'C':
9451 if (ifthen_state)
9452 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9453 else
9454 func (stream, "s");
9455 break;
9456
9457 case 'I':
9458 {
9459 unsigned int tmp;
9460
9461 ifthen_next_state = given & 0xff;
9462 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
9463 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
9464 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
9465 }
9466 break;
9467
9468 case 'x':
9469 if (ifthen_next_state)
9470 func (stream, "\t; unpredictable branch in IT block\n");
9471 break;
9472
9473 case 'X':
9474 if (ifthen_state)
9475 func (stream, "\t; unpredictable <IT:%s>",
9476 arm_conditional[IFTHEN_COND]);
9477 break;
9478
9479 case 'S':
9480 {
9481 long reg;
9482
9483 reg = (given >> 3) & 0x7;
9484 if (given & (1 << 6))
9485 reg += 8;
9486
9487 func (stream, "%s", arm_regnames[reg]);
9488 }
9489 break;
9490
9491 case 'D':
9492 {
9493 long reg;
9494
9495 reg = given & 0x7;
9496 if (given & (1 << 7))
9497 reg += 8;
9498
9499 func (stream, "%s", arm_regnames[reg]);
9500 }
9501 break;
9502
9503 case 'N':
9504 if (given & (1 << 8))
9505 domasklr = 1;
9506 /* Fall through. */
9507 case 'O':
9508 if (*c == 'O' && (given & (1 << 8)))
9509 domaskpc = 1;
9510 /* Fall through. */
9511 case 'M':
9512 {
9513 int started = 0;
9514 int reg;
9515
9516 func (stream, "{");
9517
9518 /* It would be nice if we could spot
9519 ranges, and generate the rS-rE format: */
9520 for (reg = 0; (reg < 8); reg++)
9521 if ((given & (1 << reg)) != 0)
9522 {
9523 if (started)
9524 func (stream, ", ");
9525 started = 1;
9526 func (stream, "%s", arm_regnames[reg]);
9527 }
9528
9529 if (domasklr)
9530 {
9531 if (started)
9532 func (stream, ", ");
9533 started = 1;
9534 func (stream, "%s", arm_regnames[14] /* "lr" */);
9535 }
9536
9537 if (domaskpc)
9538 {
9539 if (started)
9540 func (stream, ", ");
9541 func (stream, "%s", arm_regnames[15] /* "pc" */);
9542 }
9543
9544 func (stream, "}");
9545 }
9546 break;
9547
9548 case 'W':
9549 /* Print writeback indicator for a LDMIA. We are doing a
9550 writeback if the base register is not in the register
9551 mask. */
9552 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
9553 func (stream, "!");
9554 break;
9555
9556 case 'b':
9557 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
9558 {
9559 bfd_vma address = (pc + 4
9560 + ((given & 0x00f8) >> 2)
9561 + ((given & 0x0200) >> 3));
9562 info->print_address_func (address, info);
9563 }
9564 break;
9565
9566 case 's':
9567 /* Right shift immediate -- bits 6..10; 1-31 print
9568 as themselves, 0 prints as 32. */
9569 {
9570 long imm = (given & 0x07c0) >> 6;
9571 if (imm == 0)
9572 imm = 32;
9573 func (stream, "#%ld", imm);
9574 }
9575 break;
9576
9577 case '0': case '1': case '2': case '3': case '4':
9578 case '5': case '6': case '7': case '8': case '9':
9579 {
9580 int bitstart = *c++ - '0';
9581 int bitend = 0;
9582
9583 while (*c >= '0' && *c <= '9')
9584 bitstart = (bitstart * 10) + *c++ - '0';
9585
9586 switch (*c)
9587 {
9588 case '-':
9589 {
9590 bfd_vma reg;
9591
9592 c++;
9593 while (*c >= '0' && *c <= '9')
9594 bitend = (bitend * 10) + *c++ - '0';
9595 if (!bitend)
9596 abort ();
9597 reg = given >> bitstart;
9598 reg &= (2 << (bitend - bitstart)) - 1;
9599
9600 switch (*c)
9601 {
9602 case 'r':
9603 func (stream, "%s", arm_regnames[reg]);
9604 break;
9605
9606 case 'd':
9607 func (stream, "%ld", (long) reg);
9608 value_in_comment = reg;
9609 break;
9610
9611 case 'H':
9612 func (stream, "%ld", (long) (reg << 1));
9613 value_in_comment = reg << 1;
9614 break;
9615
9616 case 'W':
9617 func (stream, "%ld", (long) (reg << 2));
9618 value_in_comment = reg << 2;
9619 break;
9620
9621 case 'a':
9622 /* PC-relative address -- the bottom two
9623 bits of the address are dropped
9624 before the calculation. */
9625 info->print_address_func
9626 (((pc + 4) & ~3) + (reg << 2), info);
9627 value_in_comment = 0;
9628 break;
9629
9630 case 'x':
9631 func (stream, "0x%04lx", (long) reg);
9632 break;
9633
9634 case 'B':
9635 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
9636 info->print_address_func (reg * 2 + pc + 4, info);
9637 value_in_comment = 0;
9638 break;
9639
9640 case 'c':
9641 func (stream, "%s", arm_conditional [reg]);
9642 break;
9643
9644 default:
9645 abort ();
9646 }
9647 }
9648 break;
9649
9650 case '\'':
9651 c++;
9652 if ((given & (1 << bitstart)) != 0)
9653 func (stream, "%c", *c);
9654 break;
9655
9656 case '?':
9657 ++c;
9658 if ((given & (1 << bitstart)) != 0)
9659 func (stream, "%c", *c++);
9660 else
9661 func (stream, "%c", *++c);
9662 break;
9663
9664 default:
9665 abort ();
9666 }
9667 }
9668 break;
9669
9670 default:
9671 abort ();
9672 }
9673 }
9674
9675 if (value_in_comment > 32 || value_in_comment < -16)
9676 func (stream, "\t; 0x%lx", value_in_comment);
9677 return;
9678 }
9679
9680 /* No match. */
9681 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
9682 return;
9683 }
9684
9685 /* Return the name of an V7M special register. */
9686
9687 static const char *
9688 psr_name (int regno)
9689 {
9690 switch (regno)
9691 {
9692 case 0x0: return "APSR";
9693 case 0x1: return "IAPSR";
9694 case 0x2: return "EAPSR";
9695 case 0x3: return "PSR";
9696 case 0x5: return "IPSR";
9697 case 0x6: return "EPSR";
9698 case 0x7: return "IEPSR";
9699 case 0x8: return "MSP";
9700 case 0x9: return "PSP";
9701 case 0xa: return "MSPLIM";
9702 case 0xb: return "PSPLIM";
9703 case 0x10: return "PRIMASK";
9704 case 0x11: return "BASEPRI";
9705 case 0x12: return "BASEPRI_MAX";
9706 case 0x13: return "FAULTMASK";
9707 case 0x14: return "CONTROL";
9708 case 0x88: return "MSP_NS";
9709 case 0x89: return "PSP_NS";
9710 case 0x8a: return "MSPLIM_NS";
9711 case 0x8b: return "PSPLIM_NS";
9712 case 0x90: return "PRIMASK_NS";
9713 case 0x91: return "BASEPRI_NS";
9714 case 0x93: return "FAULTMASK_NS";
9715 case 0x94: return "CONTROL_NS";
9716 case 0x98: return "SP_NS";
9717 default: return "<unknown>";
9718 }
9719 }
9720
9721 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
9722
9723 static void
9724 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
9725 {
9726 const struct opcode32 *insn;
9727 void *stream = info->stream;
9728 fprintf_ftype func = info->fprintf_func;
9729 bfd_boolean is_mve = is_mve_architecture (info);
9730
9731 if (print_insn_coprocessor (pc, info, given, TRUE))
9732 return;
9733
9734 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
9735 return;
9736
9737 if (is_mve && print_insn_mve (info, given))
9738 return;
9739
9740 for (insn = thumb32_opcodes; insn->assembler; insn++)
9741 if ((given & insn->mask) == insn->value)
9742 {
9743 bfd_boolean is_clrm = FALSE;
9744 bfd_boolean is_unpredictable = FALSE;
9745 signed long value_in_comment = 0;
9746 const char *c = insn->assembler;
9747
9748 for (; *c; c++)
9749 {
9750 if (*c != '%')
9751 {
9752 func (stream, "%c", *c);
9753 continue;
9754 }
9755
9756 switch (*++c)
9757 {
9758 case '%':
9759 func (stream, "%%");
9760 break;
9761
9762 case 'c':
9763 if (ifthen_state)
9764 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9765 break;
9766
9767 case 'x':
9768 if (ifthen_next_state)
9769 func (stream, "\t; unpredictable branch in IT block\n");
9770 break;
9771
9772 case 'X':
9773 if (ifthen_state)
9774 func (stream, "\t; unpredictable <IT:%s>",
9775 arm_conditional[IFTHEN_COND]);
9776 break;
9777
9778 case 'I':
9779 {
9780 unsigned int imm12 = 0;
9781
9782 imm12 |= (given & 0x000000ffu);
9783 imm12 |= (given & 0x00007000u) >> 4;
9784 imm12 |= (given & 0x04000000u) >> 15;
9785 func (stream, "#%u", imm12);
9786 value_in_comment = imm12;
9787 }
9788 break;
9789
9790 case 'M':
9791 {
9792 unsigned int bits = 0, imm, imm8, mod;
9793
9794 bits |= (given & 0x000000ffu);
9795 bits |= (given & 0x00007000u) >> 4;
9796 bits |= (given & 0x04000000u) >> 15;
9797 imm8 = (bits & 0x0ff);
9798 mod = (bits & 0xf00) >> 8;
9799 switch (mod)
9800 {
9801 case 0: imm = imm8; break;
9802 case 1: imm = ((imm8 << 16) | imm8); break;
9803 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
9804 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
9805 default:
9806 mod = (bits & 0xf80) >> 7;
9807 imm8 = (bits & 0x07f) | 0x80;
9808 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
9809 }
9810 func (stream, "#%u", imm);
9811 value_in_comment = imm;
9812 }
9813 break;
9814
9815 case 'J':
9816 {
9817 unsigned int imm = 0;
9818
9819 imm |= (given & 0x000000ffu);
9820 imm |= (given & 0x00007000u) >> 4;
9821 imm |= (given & 0x04000000u) >> 15;
9822 imm |= (given & 0x000f0000u) >> 4;
9823 func (stream, "#%u", imm);
9824 value_in_comment = imm;
9825 }
9826 break;
9827
9828 case 'K':
9829 {
9830 unsigned int imm = 0;
9831
9832 imm |= (given & 0x000f0000u) >> 16;
9833 imm |= (given & 0x00000ff0u) >> 0;
9834 imm |= (given & 0x0000000fu) << 12;
9835 func (stream, "#%u", imm);
9836 value_in_comment = imm;
9837 }
9838 break;
9839
9840 case 'H':
9841 {
9842 unsigned int imm = 0;
9843
9844 imm |= (given & 0x000f0000u) >> 4;
9845 imm |= (given & 0x00000fffu) >> 0;
9846 func (stream, "#%u", imm);
9847 value_in_comment = imm;
9848 }
9849 break;
9850
9851 case 'V':
9852 {
9853 unsigned int imm = 0;
9854
9855 imm |= (given & 0x00000fffu);
9856 imm |= (given & 0x000f0000u) >> 4;
9857 func (stream, "#%u", imm);
9858 value_in_comment = imm;
9859 }
9860 break;
9861
9862 case 'S':
9863 {
9864 unsigned int reg = (given & 0x0000000fu);
9865 unsigned int stp = (given & 0x00000030u) >> 4;
9866 unsigned int imm = 0;
9867 imm |= (given & 0x000000c0u) >> 6;
9868 imm |= (given & 0x00007000u) >> 10;
9869
9870 func (stream, "%s", arm_regnames[reg]);
9871 switch (stp)
9872 {
9873 case 0:
9874 if (imm > 0)
9875 func (stream, ", lsl #%u", imm);
9876 break;
9877
9878 case 1:
9879 if (imm == 0)
9880 imm = 32;
9881 func (stream, ", lsr #%u", imm);
9882 break;
9883
9884 case 2:
9885 if (imm == 0)
9886 imm = 32;
9887 func (stream, ", asr #%u", imm);
9888 break;
9889
9890 case 3:
9891 if (imm == 0)
9892 func (stream, ", rrx");
9893 else
9894 func (stream, ", ror #%u", imm);
9895 }
9896 }
9897 break;
9898
9899 case 'a':
9900 {
9901 unsigned int Rn = (given & 0x000f0000) >> 16;
9902 unsigned int U = ! NEGATIVE_BIT_SET;
9903 unsigned int op = (given & 0x00000f00) >> 8;
9904 unsigned int i12 = (given & 0x00000fff);
9905 unsigned int i8 = (given & 0x000000ff);
9906 bfd_boolean writeback = FALSE, postind = FALSE;
9907 bfd_vma offset = 0;
9908
9909 func (stream, "[%s", arm_regnames[Rn]);
9910 if (U) /* 12-bit positive immediate offset. */
9911 {
9912 offset = i12;
9913 if (Rn != 15)
9914 value_in_comment = offset;
9915 }
9916 else if (Rn == 15) /* 12-bit negative immediate offset. */
9917 offset = - (int) i12;
9918 else if (op == 0x0) /* Shifted register offset. */
9919 {
9920 unsigned int Rm = (i8 & 0x0f);
9921 unsigned int sh = (i8 & 0x30) >> 4;
9922
9923 func (stream, ", %s", arm_regnames[Rm]);
9924 if (sh)
9925 func (stream, ", lsl #%u", sh);
9926 func (stream, "]");
9927 break;
9928 }
9929 else switch (op)
9930 {
9931 case 0xE: /* 8-bit positive immediate offset. */
9932 offset = i8;
9933 break;
9934
9935 case 0xC: /* 8-bit negative immediate offset. */
9936 offset = -i8;
9937 break;
9938
9939 case 0xF: /* 8-bit + preindex with wb. */
9940 offset = i8;
9941 writeback = TRUE;
9942 break;
9943
9944 case 0xD: /* 8-bit - preindex with wb. */
9945 offset = -i8;
9946 writeback = TRUE;
9947 break;
9948
9949 case 0xB: /* 8-bit + postindex. */
9950 offset = i8;
9951 postind = TRUE;
9952 break;
9953
9954 case 0x9: /* 8-bit - postindex. */
9955 offset = -i8;
9956 postind = TRUE;
9957 break;
9958
9959 default:
9960 func (stream, ", <undefined>]");
9961 goto skip;
9962 }
9963
9964 if (postind)
9965 func (stream, "], #%d", (int) offset);
9966 else
9967 {
9968 if (offset)
9969 func (stream, ", #%d", (int) offset);
9970 func (stream, writeback ? "]!" : "]");
9971 }
9972
9973 if (Rn == 15)
9974 {
9975 func (stream, "\t; ");
9976 info->print_address_func (((pc + 4) & ~3) + offset, info);
9977 }
9978 }
9979 skip:
9980 break;
9981
9982 case 'A':
9983 {
9984 unsigned int U = ! NEGATIVE_BIT_SET;
9985 unsigned int W = WRITEBACK_BIT_SET;
9986 unsigned int Rn = (given & 0x000f0000) >> 16;
9987 unsigned int off = (given & 0x000000ff);
9988
9989 func (stream, "[%s", arm_regnames[Rn]);
9990
9991 if (PRE_BIT_SET)
9992 {
9993 if (off || !U)
9994 {
9995 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
9996 value_in_comment = off * 4 * (U ? 1 : -1);
9997 }
9998 func (stream, "]");
9999 if (W)
10000 func (stream, "!");
10001 }
10002 else
10003 {
10004 func (stream, "], ");
10005 if (W)
10006 {
10007 func (stream, "#%c%u", U ? '+' : '-', off * 4);
10008 value_in_comment = off * 4 * (U ? 1 : -1);
10009 }
10010 else
10011 {
10012 func (stream, "{%u}", off);
10013 value_in_comment = off;
10014 }
10015 }
10016 }
10017 break;
10018
10019 case 'w':
10020 {
10021 unsigned int Sbit = (given & 0x01000000) >> 24;
10022 unsigned int type = (given & 0x00600000) >> 21;
10023
10024 switch (type)
10025 {
10026 case 0: func (stream, Sbit ? "sb" : "b"); break;
10027 case 1: func (stream, Sbit ? "sh" : "h"); break;
10028 case 2:
10029 if (Sbit)
10030 func (stream, "??");
10031 break;
10032 case 3:
10033 func (stream, "??");
10034 break;
10035 }
10036 }
10037 break;
10038
10039 case 'n':
10040 is_clrm = TRUE;
10041 /* Fall through. */
10042 case 'm':
10043 {
10044 int started = 0;
10045 int reg;
10046
10047 func (stream, "{");
10048 for (reg = 0; reg < 16; reg++)
10049 if ((given & (1 << reg)) != 0)
10050 {
10051 if (started)
10052 func (stream, ", ");
10053 started = 1;
10054 if (is_clrm && reg == 13)
10055 func (stream, "(invalid: %s)", arm_regnames[reg]);
10056 else if (is_clrm && reg == 15)
10057 func (stream, "%s", "APSR");
10058 else
10059 func (stream, "%s", arm_regnames[reg]);
10060 }
10061 func (stream, "}");
10062 }
10063 break;
10064
10065 case 'E':
10066 {
10067 unsigned int msb = (given & 0x0000001f);
10068 unsigned int lsb = 0;
10069
10070 lsb |= (given & 0x000000c0u) >> 6;
10071 lsb |= (given & 0x00007000u) >> 10;
10072 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
10073 }
10074 break;
10075
10076 case 'F':
10077 {
10078 unsigned int width = (given & 0x0000001f) + 1;
10079 unsigned int lsb = 0;
10080
10081 lsb |= (given & 0x000000c0u) >> 6;
10082 lsb |= (given & 0x00007000u) >> 10;
10083 func (stream, "#%u, #%u", lsb, width);
10084 }
10085 break;
10086
10087 case 'G':
10088 {
10089 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
10090 func (stream, "%x", boff);
10091 }
10092 break;
10093
10094 case 'W':
10095 {
10096 unsigned int immA = (given & 0x001f0000u) >> 16;
10097 unsigned int immB = (given & 0x000007feu) >> 1;
10098 unsigned int immC = (given & 0x00000800u) >> 11;
10099 bfd_vma offset = 0;
10100
10101 offset |= immA << 12;
10102 offset |= immB << 2;
10103 offset |= immC << 1;
10104 /* Sign extend. */
10105 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
10106
10107 info->print_address_func (pc + 4 + offset, info);
10108 }
10109 break;
10110
10111 case 'Y':
10112 {
10113 unsigned int immA = (given & 0x007f0000u) >> 16;
10114 unsigned int immB = (given & 0x000007feu) >> 1;
10115 unsigned int immC = (given & 0x00000800u) >> 11;
10116 bfd_vma offset = 0;
10117
10118 offset |= immA << 12;
10119 offset |= immB << 2;
10120 offset |= immC << 1;
10121 /* Sign extend. */
10122 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
10123
10124 info->print_address_func (pc + 4 + offset, info);
10125 }
10126 break;
10127
10128 case 'Z':
10129 {
10130 unsigned int immA = (given & 0x00010000u) >> 16;
10131 unsigned int immB = (given & 0x000007feu) >> 1;
10132 unsigned int immC = (given & 0x00000800u) >> 11;
10133 bfd_vma offset = 0;
10134
10135 offset |= immA << 12;
10136 offset |= immB << 2;
10137 offset |= immC << 1;
10138 /* Sign extend. */
10139 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
10140
10141 info->print_address_func (pc + 4 + offset, info);
10142
10143 unsigned int T = (given & 0x00020000u) >> 17;
10144 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
10145 unsigned int boffset = (T == 1) ? 4 : 2;
10146 func (stream, ", ");
10147 func (stream, "%x", endoffset + boffset);
10148 }
10149 break;
10150
10151 case 'Q':
10152 {
10153 unsigned int immh = (given & 0x000007feu) >> 1;
10154 unsigned int imml = (given & 0x00000800u) >> 11;
10155 bfd_vma imm32 = 0;
10156
10157 imm32 |= immh << 2;
10158 imm32 |= imml << 1;
10159
10160 info->print_address_func (pc + 4 + imm32, info);
10161 }
10162 break;
10163
10164 case 'P':
10165 {
10166 unsigned int immh = (given & 0x000007feu) >> 1;
10167 unsigned int imml = (given & 0x00000800u) >> 11;
10168 bfd_vma imm32 = 0;
10169
10170 imm32 |= immh << 2;
10171 imm32 |= imml << 1;
10172
10173 info->print_address_func (pc + 4 - imm32, info);
10174 }
10175 break;
10176
10177 case 'b':
10178 {
10179 unsigned int S = (given & 0x04000000u) >> 26;
10180 unsigned int J1 = (given & 0x00002000u) >> 13;
10181 unsigned int J2 = (given & 0x00000800u) >> 11;
10182 bfd_vma offset = 0;
10183
10184 offset |= !S << 20;
10185 offset |= J2 << 19;
10186 offset |= J1 << 18;
10187 offset |= (given & 0x003f0000) >> 4;
10188 offset |= (given & 0x000007ff) << 1;
10189 offset -= (1 << 20);
10190
10191 info->print_address_func (pc + 4 + offset, info);
10192 }
10193 break;
10194
10195 case 'B':
10196 {
10197 unsigned int S = (given & 0x04000000u) >> 26;
10198 unsigned int I1 = (given & 0x00002000u) >> 13;
10199 unsigned int I2 = (given & 0x00000800u) >> 11;
10200 bfd_vma offset = 0;
10201
10202 offset |= !S << 24;
10203 offset |= !(I1 ^ S) << 23;
10204 offset |= !(I2 ^ S) << 22;
10205 offset |= (given & 0x03ff0000u) >> 4;
10206 offset |= (given & 0x000007ffu) << 1;
10207 offset -= (1 << 24);
10208 offset += pc + 4;
10209
10210 /* BLX target addresses are always word aligned. */
10211 if ((given & 0x00001000u) == 0)
10212 offset &= ~2u;
10213
10214 info->print_address_func (offset, info);
10215 }
10216 break;
10217
10218 case 's':
10219 {
10220 unsigned int shift = 0;
10221
10222 shift |= (given & 0x000000c0u) >> 6;
10223 shift |= (given & 0x00007000u) >> 10;
10224 if (WRITEBACK_BIT_SET)
10225 func (stream, ", asr #%u", shift);
10226 else if (shift)
10227 func (stream, ", lsl #%u", shift);
10228 /* else print nothing - lsl #0 */
10229 }
10230 break;
10231
10232 case 'R':
10233 {
10234 unsigned int rot = (given & 0x00000030) >> 4;
10235
10236 if (rot)
10237 func (stream, ", ror #%u", rot * 8);
10238 }
10239 break;
10240
10241 case 'U':
10242 if ((given & 0xf0) == 0x60)
10243 {
10244 switch (given & 0xf)
10245 {
10246 case 0xf: func (stream, "sy"); break;
10247 default:
10248 func (stream, "#%d", (int) given & 0xf);
10249 break;
10250 }
10251 }
10252 else
10253 {
10254 const char * opt = data_barrier_option (given & 0xf);
10255 if (opt != NULL)
10256 func (stream, "%s", opt);
10257 else
10258 func (stream, "#%d", (int) given & 0xf);
10259 }
10260 break;
10261
10262 case 'C':
10263 if ((given & 0xff) == 0)
10264 {
10265 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
10266 if (given & 0x800)
10267 func (stream, "f");
10268 if (given & 0x400)
10269 func (stream, "s");
10270 if (given & 0x200)
10271 func (stream, "x");
10272 if (given & 0x100)
10273 func (stream, "c");
10274 }
10275 else if ((given & 0x20) == 0x20)
10276 {
10277 char const* name;
10278 unsigned sysm = (given & 0xf00) >> 8;
10279
10280 sysm |= (given & 0x30);
10281 sysm |= (given & 0x00100000) >> 14;
10282 name = banked_regname (sysm);
10283
10284 if (name != NULL)
10285 func (stream, "%s", name);
10286 else
10287 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10288 }
10289 else
10290 {
10291 func (stream, "%s", psr_name (given & 0xff));
10292 }
10293 break;
10294
10295 case 'D':
10296 if (((given & 0xff) == 0)
10297 || ((given & 0x20) == 0x20))
10298 {
10299 char const* name;
10300 unsigned sm = (given & 0xf0000) >> 16;
10301
10302 sm |= (given & 0x30);
10303 sm |= (given & 0x00100000) >> 14;
10304 name = banked_regname (sm);
10305
10306 if (name != NULL)
10307 func (stream, "%s", name);
10308 else
10309 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
10310 }
10311 else
10312 func (stream, "%s", psr_name (given & 0xff));
10313 break;
10314
10315 case '0': case '1': case '2': case '3': case '4':
10316 case '5': case '6': case '7': case '8': case '9':
10317 {
10318 int width;
10319 unsigned long val;
10320
10321 c = arm_decode_bitfield (c, given, &val, &width);
10322
10323 switch (*c)
10324 {
10325 case 's':
10326 if (val <= 3)
10327 func (stream, "%s", mve_vec_sizename[val]);
10328 else
10329 func (stream, "<undef size>");
10330 break;
10331
10332 case 'd':
10333 func (stream, "%lu", val);
10334 value_in_comment = val;
10335 break;
10336
10337 case 'D':
10338 func (stream, "%lu", val + 1);
10339 value_in_comment = val + 1;
10340 break;
10341
10342 case 'W':
10343 func (stream, "%lu", val * 4);
10344 value_in_comment = val * 4;
10345 break;
10346
10347 case 'S':
10348 if (val == 13)
10349 is_unpredictable = TRUE;
10350 /* Fall through. */
10351 case 'R':
10352 if (val == 15)
10353 is_unpredictable = TRUE;
10354 /* Fall through. */
10355 case 'r':
10356 func (stream, "%s", arm_regnames[val]);
10357 break;
10358
10359 case 'c':
10360 func (stream, "%s", arm_conditional[val]);
10361 break;
10362
10363 case '\'':
10364 c++;
10365 if (val == ((1ul << width) - 1))
10366 func (stream, "%c", *c);
10367 break;
10368
10369 case '`':
10370 c++;
10371 if (val == 0)
10372 func (stream, "%c", *c);
10373 break;
10374
10375 case '?':
10376 func (stream, "%c", c[(1 << width) - (int) val]);
10377 c += 1 << width;
10378 break;
10379
10380 case 'x':
10381 func (stream, "0x%lx", val & 0xffffffffUL);
10382 break;
10383
10384 default:
10385 abort ();
10386 }
10387 }
10388 break;
10389
10390 case 'L':
10391 /* PR binutils/12534
10392 If we have a PC relative offset in an LDRD or STRD
10393 instructions then display the decoded address. */
10394 if (((given >> 16) & 0xf) == 0xf)
10395 {
10396 bfd_vma offset = (given & 0xff) * 4;
10397
10398 if ((given & (1 << 23)) == 0)
10399 offset = - offset;
10400 func (stream, "\t; ");
10401 info->print_address_func ((pc & ~3) + 4 + offset, info);
10402 }
10403 break;
10404
10405 default:
10406 abort ();
10407 }
10408 }
10409
10410 if (value_in_comment > 32 || value_in_comment < -16)
10411 func (stream, "\t; 0x%lx", value_in_comment);
10412
10413 if (is_unpredictable)
10414 func (stream, UNPREDICTABLE_INSTRUCTION);
10415
10416 return;
10417 }
10418
10419 /* No match. */
10420 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10421 return;
10422 }
10423
10424 /* Print data bytes on INFO->STREAM. */
10425
10426 static void
10427 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
10428 struct disassemble_info *info,
10429 long given)
10430 {
10431 switch (info->bytes_per_chunk)
10432 {
10433 case 1:
10434 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
10435 break;
10436 case 2:
10437 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
10438 break;
10439 case 4:
10440 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
10441 break;
10442 default:
10443 abort ();
10444 }
10445 }
10446
10447 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
10448 being displayed in symbol relative addresses.
10449
10450 Also disallow private symbol, with __tagsym$$ prefix,
10451 from ARM RVCT toolchain being displayed. */
10452
10453 bfd_boolean
10454 arm_symbol_is_valid (asymbol * sym,
10455 struct disassemble_info * info ATTRIBUTE_UNUSED)
10456 {
10457 const char * name;
10458
10459 if (sym == NULL)
10460 return FALSE;
10461
10462 name = bfd_asymbol_name (sym);
10463
10464 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
10465 }
10466
10467 /* Parse the string of disassembler options. */
10468
10469 static void
10470 parse_arm_disassembler_options (const char *options)
10471 {
10472 const char *opt;
10473
10474 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
10475 {
10476 if (CONST_STRNEQ (opt, "reg-names-"))
10477 {
10478 unsigned int i;
10479 for (i = 0; i < NUM_ARM_OPTIONS; i++)
10480 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
10481 {
10482 regname_selected = i;
10483 break;
10484 }
10485
10486 if (i >= NUM_ARM_OPTIONS)
10487 /* xgettext: c-format */
10488 opcodes_error_handler (_("unrecognised register name set: %s"),
10489 opt);
10490 }
10491 else if (CONST_STRNEQ (opt, "force-thumb"))
10492 force_thumb = 1;
10493 else if (CONST_STRNEQ (opt, "no-force-thumb"))
10494 force_thumb = 0;
10495 else
10496 /* xgettext: c-format */
10497 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
10498 }
10499
10500 return;
10501 }
10502
10503 static bfd_boolean
10504 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
10505 enum map_type *map_symbol);
10506
10507 /* Search back through the insn stream to determine if this instruction is
10508 conditionally executed. */
10509
10510 static void
10511 find_ifthen_state (bfd_vma pc,
10512 struct disassemble_info *info,
10513 bfd_boolean little)
10514 {
10515 unsigned char b[2];
10516 unsigned int insn;
10517 int status;
10518 /* COUNT is twice the number of instructions seen. It will be odd if we
10519 just crossed an instruction boundary. */
10520 int count;
10521 int it_count;
10522 unsigned int seen_it;
10523 bfd_vma addr;
10524
10525 ifthen_address = pc;
10526 ifthen_state = 0;
10527
10528 addr = pc;
10529 count = 1;
10530 it_count = 0;
10531 seen_it = 0;
10532 /* Scan backwards looking for IT instructions, keeping track of where
10533 instruction boundaries are. We don't know if something is actually an
10534 IT instruction until we find a definite instruction boundary. */
10535 for (;;)
10536 {
10537 if (addr == 0 || info->symbol_at_address_func (addr, info))
10538 {
10539 /* A symbol must be on an instruction boundary, and will not
10540 be within an IT block. */
10541 if (seen_it && (count & 1))
10542 break;
10543
10544 return;
10545 }
10546 addr -= 2;
10547 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
10548 if (status)
10549 return;
10550
10551 if (little)
10552 insn = (b[0]) | (b[1] << 8);
10553 else
10554 insn = (b[1]) | (b[0] << 8);
10555 if (seen_it)
10556 {
10557 if ((insn & 0xf800) < 0xe800)
10558 {
10559 /* Addr + 2 is an instruction boundary. See if this matches
10560 the expected boundary based on the position of the last
10561 IT candidate. */
10562 if (count & 1)
10563 break;
10564 seen_it = 0;
10565 }
10566 }
10567 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
10568 {
10569 enum map_type type = MAP_ARM;
10570 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
10571
10572 if (!found || (found && type == MAP_THUMB))
10573 {
10574 /* This could be an IT instruction. */
10575 seen_it = insn;
10576 it_count = count >> 1;
10577 }
10578 }
10579 if ((insn & 0xf800) >= 0xe800)
10580 count++;
10581 else
10582 count = (count + 2) | 1;
10583 /* IT blocks contain at most 4 instructions. */
10584 if (count >= 8 && !seen_it)
10585 return;
10586 }
10587 /* We found an IT instruction. */
10588 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
10589 if ((ifthen_state & 0xf) == 0)
10590 ifthen_state = 0;
10591 }
10592
10593 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
10594 mapping symbol. */
10595
10596 static int
10597 is_mapping_symbol (struct disassemble_info *info, int n,
10598 enum map_type *map_type)
10599 {
10600 const char *name;
10601
10602 name = bfd_asymbol_name (info->symtab[n]);
10603 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
10604 && (name[2] == 0 || name[2] == '.'))
10605 {
10606 *map_type = ((name[1] == 'a') ? MAP_ARM
10607 : (name[1] == 't') ? MAP_THUMB
10608 : MAP_DATA);
10609 return TRUE;
10610 }
10611
10612 return FALSE;
10613 }
10614
10615 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
10616 Returns nonzero if *MAP_TYPE was set. */
10617
10618 static int
10619 get_map_sym_type (struct disassemble_info *info,
10620 int n,
10621 enum map_type *map_type)
10622 {
10623 /* If the symbol is in a different section, ignore it. */
10624 if (info->section != NULL && info->section != info->symtab[n]->section)
10625 return FALSE;
10626
10627 return is_mapping_symbol (info, n, map_type);
10628 }
10629
10630 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
10631 Returns nonzero if *MAP_TYPE was set. */
10632
10633 static int
10634 get_sym_code_type (struct disassemble_info *info,
10635 int n,
10636 enum map_type *map_type)
10637 {
10638 elf_symbol_type *es;
10639 unsigned int type;
10640
10641 /* If the symbol is in a different section, ignore it. */
10642 if (info->section != NULL && info->section != info->symtab[n]->section)
10643 return FALSE;
10644
10645 es = *(elf_symbol_type **)(info->symtab + n);
10646 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
10647
10648 /* If the symbol has function type then use that. */
10649 if (type == STT_FUNC || type == STT_GNU_IFUNC)
10650 {
10651 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
10652 == ST_BRANCH_TO_THUMB)
10653 *map_type = MAP_THUMB;
10654 else
10655 *map_type = MAP_ARM;
10656 return TRUE;
10657 }
10658
10659 return FALSE;
10660 }
10661
10662 /* Search the mapping symbol state for instruction at pc. This is only
10663 applicable for elf target.
10664
10665 There is an assumption Here, info->private_data contains the correct AND
10666 up-to-date information about current scan process. The information will be
10667 used to speed this search process.
10668
10669 Return TRUE if the mapping state can be determined, and map_symbol
10670 will be updated accordingly. Otherwise, return FALSE. */
10671
10672 static bfd_boolean
10673 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
10674 enum map_type *map_symbol)
10675 {
10676 bfd_vma addr, section_vma = 0;
10677 int n, last_sym = -1;
10678 bfd_boolean found = FALSE;
10679 bfd_boolean can_use_search_opt_p = FALSE;
10680
10681 /* Default to DATA. A text section is required by the ABI to contain an
10682 INSN mapping symbol at the start. A data section has no such
10683 requirement, hence if no mapping symbol is found the section must
10684 contain only data. This however isn't very useful if the user has
10685 fully stripped the binaries. If this is the case use the section
10686 attributes to determine the default. If we have no section default to
10687 INSN as well, as we may be disassembling some raw bytes on a baremetal
10688 HEX file or similar. */
10689 enum map_type type = MAP_DATA;
10690 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
10691 type = MAP_ARM;
10692 struct arm_private_data *private_data;
10693
10694 if (info->private_data == NULL
10695 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
10696 return FALSE;
10697
10698 private_data = info->private_data;
10699
10700 /* First, look for mapping symbols. */
10701 if (info->symtab_size != 0)
10702 {
10703 if (pc <= private_data->last_mapping_addr)
10704 private_data->last_mapping_sym = -1;
10705
10706 /* Start scanning at the start of the function, or wherever
10707 we finished last time. */
10708 n = info->symtab_pos + 1;
10709
10710 /* If the last stop offset is different from the current one it means we
10711 are disassembling a different glob of bytes. As such the optimization
10712 would not be safe and we should start over. */
10713 can_use_search_opt_p
10714 = private_data->last_mapping_sym >= 0
10715 && info->stop_offset == private_data->last_stop_offset;
10716
10717 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
10718 n = private_data->last_mapping_sym;
10719
10720 /* Look down while we haven't passed the location being disassembled.
10721 The reason for this is that there's no defined order between a symbol
10722 and an mapping symbol that may be at the same address. We may have to
10723 look at least one position ahead. */
10724 for (; n < info->symtab_size; n++)
10725 {
10726 addr = bfd_asymbol_value (info->symtab[n]);
10727 if (addr > pc)
10728 break;
10729 if (get_map_sym_type (info, n, &type))
10730 {
10731 last_sym = n;
10732 found = TRUE;
10733 }
10734 }
10735
10736 if (!found)
10737 {
10738 n = info->symtab_pos;
10739 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
10740 n = private_data->last_mapping_sym;
10741
10742 /* No mapping symbol found at this address. Look backwards
10743 for a preceeding one, but don't go pass the section start
10744 otherwise a data section with no mapping symbol can pick up
10745 a text mapping symbol of a preceeding section. The documentation
10746 says section can be NULL, in which case we will seek up all the
10747 way to the top. */
10748 if (info->section)
10749 section_vma = info->section->vma;
10750
10751 for (; n >= 0; n--)
10752 {
10753 addr = bfd_asymbol_value (info->symtab[n]);
10754 if (addr < section_vma)
10755 break;
10756
10757 if (get_map_sym_type (info, n, &type))
10758 {
10759 last_sym = n;
10760 found = TRUE;
10761 break;
10762 }
10763 }
10764 }
10765 }
10766
10767 /* If no mapping symbol was found, try looking up without a mapping
10768 symbol. This is done by walking up from the current PC to the nearest
10769 symbol. We don't actually have to loop here since symtab_pos will
10770 contain the nearest symbol already. */
10771 if (!found)
10772 {
10773 n = info->symtab_pos;
10774 if (n >= 0 && get_sym_code_type (info, n, &type))
10775 {
10776 last_sym = n;
10777 found = TRUE;
10778 }
10779 }
10780
10781 private_data->last_mapping_sym = last_sym;
10782 private_data->last_type = type;
10783 private_data->last_stop_offset = info->stop_offset;
10784
10785 *map_symbol = type;
10786 return found;
10787 }
10788
10789 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
10790 of the supplied arm_feature_set structure with bitmasks indicating
10791 the supported base architectures and coprocessor extensions.
10792
10793 FIXME: This could more efficiently implemented as a constant array,
10794 although it would also be less robust. */
10795
10796 static void
10797 select_arm_features (unsigned long mach,
10798 arm_feature_set * features)
10799 {
10800 arm_feature_set arch_fset;
10801 const arm_feature_set fpu_any = FPU_ANY;
10802
10803 #undef ARM_SET_FEATURES
10804 #define ARM_SET_FEATURES(FSET) \
10805 { \
10806 const arm_feature_set fset = FSET; \
10807 arch_fset = fset; \
10808 }
10809
10810 /* When several architecture versions share the same bfd_mach_arm_XXX value
10811 the most featureful is chosen. */
10812 switch (mach)
10813 {
10814 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
10815 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
10816 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
10817 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
10818 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
10819 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
10820 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
10821 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
10822 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
10823 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
10824 case bfd_mach_arm_ep9312:
10825 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
10826 ARM_CEXT_MAVERICK | FPU_MAVERICK));
10827 break;
10828 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
10829 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
10830 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
10831 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
10832 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
10833 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
10834 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
10835 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
10836 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
10837 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
10838 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
10839 case bfd_mach_arm_8:
10840 {
10841 /* Add bits for extensions that Armv8.5-A recognizes. */
10842 arm_feature_set armv8_5_ext_fset
10843 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
10844 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
10845 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
10846 break;
10847 }
10848 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
10849 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
10850 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
10851 case bfd_mach_arm_8_1M_MAIN:
10852 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
10853 force_thumb = 1;
10854 break;
10855 /* If the machine type is unknown allow all architecture types and all
10856 extensions. */
10857 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
10858 default:
10859 abort ();
10860 }
10861 #undef ARM_SET_FEATURES
10862
10863 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
10864 and thus on bfd_mach_arm_XXX value. Therefore for a given
10865 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
10866 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
10867 }
10868
10869
10870 /* NOTE: There are no checks in these routines that
10871 the relevant number of data bytes exist. */
10872
10873 static int
10874 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
10875 {
10876 unsigned char b[4];
10877 long given;
10878 int status;
10879 int is_thumb = FALSE;
10880 int is_data = FALSE;
10881 int little_code;
10882 unsigned int size = 4;
10883 void (*printer) (bfd_vma, struct disassemble_info *, long);
10884 bfd_boolean found = FALSE;
10885 struct arm_private_data *private_data;
10886
10887 if (info->disassembler_options)
10888 {
10889 parse_arm_disassembler_options (info->disassembler_options);
10890
10891 /* To avoid repeated parsing of these options, we remove them here. */
10892 info->disassembler_options = NULL;
10893 }
10894
10895 /* PR 10288: Control which instructions will be disassembled. */
10896 if (info->private_data == NULL)
10897 {
10898 static struct arm_private_data private;
10899
10900 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
10901 /* If the user did not use the -m command line switch then default to
10902 disassembling all types of ARM instruction.
10903
10904 The info->mach value has to be ignored as this will be based on
10905 the default archictecture for the target and/or hints in the notes
10906 section, but it will never be greater than the current largest arm
10907 machine value (iWMMXt2), which is only equivalent to the V5TE
10908 architecture. ARM architectures have advanced beyond the machine
10909 value encoding, and these newer architectures would be ignored if
10910 the machine value was used.
10911
10912 Ie the -m switch is used to restrict which instructions will be
10913 disassembled. If it is necessary to use the -m switch to tell
10914 objdump that an ARM binary is being disassembled, eg because the
10915 input is a raw binary file, but it is also desired to disassemble
10916 all ARM instructions then use "-marm". This will select the
10917 "unknown" arm architecture which is compatible with any ARM
10918 instruction. */
10919 info->mach = bfd_mach_arm_unknown;
10920
10921 /* Compute the architecture bitmask from the machine number.
10922 Note: This assumes that the machine number will not change
10923 during disassembly.... */
10924 select_arm_features (info->mach, & private.features);
10925
10926 private.last_mapping_sym = -1;
10927 private.last_mapping_addr = 0;
10928 private.last_stop_offset = 0;
10929
10930 info->private_data = & private;
10931 }
10932
10933 private_data = info->private_data;
10934
10935 /* Decide if our code is going to be little-endian, despite what the
10936 function argument might say. */
10937 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
10938
10939 /* For ELF, consult the symbol table to determine what kind of code
10940 or data we have. */
10941 if (info->symtab_size != 0
10942 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
10943 {
10944 bfd_vma addr;
10945 int n;
10946 int last_sym = -1;
10947 enum map_type type = MAP_ARM;
10948
10949 found = mapping_symbol_for_insn (pc, info, &type);
10950 last_sym = private_data->last_mapping_sym;
10951
10952 is_thumb = (private_data->last_type == MAP_THUMB);
10953 is_data = (private_data->last_type == MAP_DATA);
10954
10955 /* Look a little bit ahead to see if we should print out
10956 two or four bytes of data. If there's a symbol,
10957 mapping or otherwise, after two bytes then don't
10958 print more. */
10959 if (is_data)
10960 {
10961 size = 4 - (pc & 3);
10962 for (n = last_sym + 1; n < info->symtab_size; n++)
10963 {
10964 addr = bfd_asymbol_value (info->symtab[n]);
10965 if (addr > pc
10966 && (info->section == NULL
10967 || info->section == info->symtab[n]->section))
10968 {
10969 if (addr - pc < size)
10970 size = addr - pc;
10971 break;
10972 }
10973 }
10974 /* If the next symbol is after three bytes, we need to
10975 print only part of the data, so that we can use either
10976 .byte or .short. */
10977 if (size == 3)
10978 size = (pc & 1) ? 1 : 2;
10979 }
10980 }
10981
10982 if (info->symbols != NULL)
10983 {
10984 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
10985 {
10986 coff_symbol_type * cs;
10987
10988 cs = coffsymbol (*info->symbols);
10989 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
10990 || cs->native->u.syment.n_sclass == C_THUMBSTAT
10991 || cs->native->u.syment.n_sclass == C_THUMBLABEL
10992 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
10993 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
10994 }
10995 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
10996 && !found)
10997 {
10998 /* If no mapping symbol has been found then fall back to the type
10999 of the function symbol. */
11000 elf_symbol_type * es;
11001 unsigned int type;
11002
11003 es = *(elf_symbol_type **)(info->symbols);
11004 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11005
11006 is_thumb =
11007 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11008 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
11009 }
11010 else if (bfd_asymbol_flavour (*info->symbols)
11011 == bfd_target_mach_o_flavour)
11012 {
11013 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
11014
11015 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
11016 }
11017 }
11018
11019 if (force_thumb)
11020 is_thumb = TRUE;
11021
11022 if (is_data)
11023 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11024 else
11025 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11026
11027 info->bytes_per_line = 4;
11028
11029 /* PR 10263: Disassemble data if requested to do so by the user. */
11030 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
11031 {
11032 int i;
11033
11034 /* Size was already set above. */
11035 info->bytes_per_chunk = size;
11036 printer = print_insn_data;
11037
11038 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
11039 given = 0;
11040 if (little)
11041 for (i = size - 1; i >= 0; i--)
11042 given = b[i] | (given << 8);
11043 else
11044 for (i = 0; i < (int) size; i++)
11045 given = b[i] | (given << 8);
11046 }
11047 else if (!is_thumb)
11048 {
11049 /* In ARM mode endianness is a straightforward issue: the instruction
11050 is four bytes long and is either ordered 0123 or 3210. */
11051 printer = print_insn_arm;
11052 info->bytes_per_chunk = 4;
11053 size = 4;
11054
11055 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
11056 if (little_code)
11057 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
11058 else
11059 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
11060 }
11061 else
11062 {
11063 /* In Thumb mode we have the additional wrinkle of two
11064 instruction lengths. Fortunately, the bits that determine
11065 the length of the current instruction are always to be found
11066 in the first two bytes. */
11067 printer = print_insn_thumb16;
11068 info->bytes_per_chunk = 2;
11069 size = 2;
11070
11071 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
11072 if (little_code)
11073 given = (b[0]) | (b[1] << 8);
11074 else
11075 given = (b[1]) | (b[0] << 8);
11076
11077 if (!status)
11078 {
11079 /* These bit patterns signal a four-byte Thumb
11080 instruction. */
11081 if ((given & 0xF800) == 0xF800
11082 || (given & 0xF800) == 0xF000
11083 || (given & 0xF800) == 0xE800)
11084 {
11085 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
11086 if (little_code)
11087 given = (b[0]) | (b[1] << 8) | (given << 16);
11088 else
11089 given = (b[1]) | (b[0] << 8) | (given << 16);
11090
11091 printer = print_insn_thumb32;
11092 size = 4;
11093 }
11094 }
11095
11096 if (ifthen_address != pc)
11097 find_ifthen_state (pc, info, little_code);
11098
11099 if (ifthen_state)
11100 {
11101 if ((ifthen_state & 0xf) == 0x8)
11102 ifthen_next_state = 0;
11103 else
11104 ifthen_next_state = (ifthen_state & 0xe0)
11105 | ((ifthen_state & 0xf) << 1);
11106 }
11107 }
11108
11109 if (status)
11110 {
11111 info->memory_error_func (status, pc, info);
11112 return -1;
11113 }
11114 if (info->flags & INSN_HAS_RELOC)
11115 /* If the instruction has a reloc associated with it, then
11116 the offset field in the instruction will actually be the
11117 addend for the reloc. (We are using REL type relocs).
11118 In such cases, we can ignore the pc when computing
11119 addresses, since the addend is not currently pc-relative. */
11120 pc = 0;
11121
11122 printer (pc, info, given);
11123
11124 if (is_thumb)
11125 {
11126 ifthen_state = ifthen_next_state;
11127 ifthen_address += size;
11128 }
11129 return size;
11130 }
11131
11132 int
11133 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
11134 {
11135 /* Detect BE8-ness and record it in the disassembler info. */
11136 if (info->flavour == bfd_target_elf_flavour
11137 && info->section != NULL
11138 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
11139 info->endian_code = BFD_ENDIAN_LITTLE;
11140
11141 return print_insn (pc, info, FALSE);
11142 }
11143
11144 int
11145 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
11146 {
11147 return print_insn (pc, info, TRUE);
11148 }
11149
11150 const disasm_options_and_args_t *
11151 disassembler_options_arm (void)
11152 {
11153 static disasm_options_and_args_t *opts_and_args;
11154
11155 if (opts_and_args == NULL)
11156 {
11157 disasm_options_t *opts;
11158 unsigned int i;
11159
11160 opts_and_args = XNEW (disasm_options_and_args_t);
11161 opts_and_args->args = NULL;
11162
11163 opts = &opts_and_args->options;
11164 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11165 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11166 opts->arg = NULL;
11167 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11168 {
11169 opts->name[i] = regnames[i].name;
11170 if (regnames[i].description != NULL)
11171 opts->description[i] = _(regnames[i].description);
11172 else
11173 opts->description[i] = NULL;
11174 }
11175 /* The array we return must be NULL terminated. */
11176 opts->name[i] = NULL;
11177 opts->description[i] = NULL;
11178 }
11179
11180 return opts_and_args;
11181 }
11182
11183 void
11184 print_arm_disassembler_options (FILE *stream)
11185 {
11186 unsigned int i, max_len = 0;
11187 fprintf (stream, _("\n\
11188 The following ARM specific disassembler options are supported for use with\n\
11189 the -M switch:\n"));
11190
11191 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11192 {
11193 unsigned int len = strlen (regnames[i].name);
11194 if (max_len < len)
11195 max_len = len;
11196 }
11197
11198 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
11199 fprintf (stream, " %s%*c %s\n",
11200 regnames[i].name,
11201 (int)(max_len - strlen (regnames[i].name)), ' ',
11202 _(regnames[i].description));
11203 }
GDB Binutils - Deliverables
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