1 /* Instruction printing code for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This program is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2 of the License, or (at your option)
13 This program is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
26 #include "coff/internal.h"
30 /* FIXME: This shouldn't be done here */
32 #include "elf/internal.h"
36 #define streq(a,b) (strcmp ((a), (b)) == 0)
40 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
44 #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
47 static char * arm_conditional
[] =
48 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
49 "hi", "ls", "ge", "lt", "gt", "le", "", "nv"};
54 const char * description
;
55 const char * reg_names
[16];
59 static arm_regname regnames
[] =
61 { "raw" , "Select raw register names",
62 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
63 { "gcc", "Select register names used by GCC",
64 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65 { "std", "Select register names used in ARM's ISA documentation",
66 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
67 { "apcs", "Select register names used in the APCS",
68 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
69 { "atpcs", "Select register names used in the ATPCS",
70 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
71 { "special-atpcs", "Select special register names used in the ATPCS",
72 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
75 /* Default to GCC register name set. */
76 static unsigned int regname_selected
= 1;
78 #define NUM_ARM_REGNAMES NUM_ELEM (regnames)
79 #define arm_regnames regnames[regname_selected].reg_names
81 static boolean force_thumb
= false;
83 static char * arm_fp_const
[] =
84 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
86 static char * arm_shift
[] =
87 {"lsl", "lsr", "asr", "ror"};
89 /* Forward declarations. */
90 static void arm_decode_shift
PARAMS ((long, fprintf_ftype
, void *));
91 static int print_insn_arm
PARAMS ((bfd_vma
, struct disassemble_info
*, long));
92 static int print_insn_thumb
PARAMS ((bfd_vma
, struct disassemble_info
*, long));
93 static void parse_disassembler_options
PARAMS ((char *));
94 static int print_insn
PARAMS ((bfd_vma
, struct disassemble_info
*, boolean
));
95 int get_arm_regname_num_options (void);
96 int set_arm_regname_option (int option
);
97 int get_arm_regnames (int option
, const char **setname
,
98 const char **setdescription
,
99 const char ***register_names
);
103 get_arm_regname_num_options (void)
105 return NUM_ARM_REGNAMES
;
109 set_arm_regname_option (int option
)
111 int old
= regname_selected
;
112 regname_selected
= option
;
117 get_arm_regnames (int option
, const char **setname
,
118 const char **setdescription
,
119 const char ***register_names
)
121 *setname
= regnames
[option
].name
;
122 *setdescription
= regnames
[option
].description
;
123 *register_names
= regnames
[option
].reg_names
;
128 arm_decode_shift (given
, func
, stream
)
133 func (stream
, "%s", arm_regnames
[given
& 0xf]);
135 if ((given
& 0xff0) != 0)
137 if ((given
& 0x10) == 0)
139 int amount
= (given
& 0xf80) >> 7;
140 int shift
= (given
& 0x60) >> 5;
146 func (stream
, ", rrx");
153 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
156 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
157 arm_regnames
[(given
& 0xf00) >> 8]);
161 /* Print one instruction from PC on INFO->STREAM.
162 Return the size of the instruction (always 4 on ARM). */
164 print_insn_arm (pc
, info
, given
)
166 struct disassemble_info
* info
;
169 struct arm_opcode
* insn
;
170 void * stream
= info
->stream
;
171 fprintf_ftype func
= info
->fprintf_func
;
173 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
175 if ((given
& insn
->mask
) == insn
->value
)
179 for (c
= insn
->assembler
; *c
; c
++)
190 if (((given
& 0x000f0000) == 0x000f0000)
191 && ((given
& 0x02000000) == 0))
193 int offset
= given
& 0xfff;
195 func (stream
, "[pc");
197 if (given
& 0x01000000)
199 if ((given
& 0x00800000) == 0)
203 func (stream
, ", #%x]", offset
);
207 /* Cope with the possibility of write-back
208 being used. Probably a very dangerous thing
209 for the programmer to do, but who are we to
211 if (given
& 0x00200000)
217 func (stream
, "], #%x", offset
);
219 offset
= pc
+ 8; /* ie ignore the offset. */
222 func (stream
, "\t; ");
223 info
->print_address_func (offset
, info
);
228 arm_regnames
[(given
>> 16) & 0xf]);
229 if ((given
& 0x01000000) != 0)
231 if ((given
& 0x02000000) == 0)
233 int offset
= given
& 0xfff;
235 func (stream
, ", %s#%d",
236 (((given
& 0x00800000) == 0)
237 ? "-" : ""), offset
);
241 func (stream
, ", %s",
242 (((given
& 0x00800000) == 0)
244 arm_decode_shift (given
, func
, stream
);
248 ((given
& 0x00200000) != 0) ? "!" : "");
252 if ((given
& 0x02000000) == 0)
254 int offset
= given
& 0xfff;
256 func (stream
, "], %s#%d",
257 (((given
& 0x00800000) == 0)
258 ? "-" : ""), offset
);
264 func (stream
, "], %s",
265 (((given
& 0x00800000) == 0)
267 arm_decode_shift (given
, func
, stream
);
274 if ((given
& 0x004f0000) == 0x004f0000)
276 /* PC relative with immediate offset. */
277 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
279 if ((given
& 0x00800000) == 0)
282 func (stream
, "[pc, #%x]\t; ", offset
);
284 (*info
->print_address_func
)
285 (offset
+ pc
+ 8, info
);
290 arm_regnames
[(given
>> 16) & 0xf]);
291 if ((given
& 0x01000000) != 0)
294 if ((given
& 0x00400000) == 0x00400000)
297 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
299 func (stream
, ", %s#%d",
300 (((given
& 0x00800000) == 0)
301 ? "-" : ""), offset
);
306 func (stream
, ", %s%s",
307 (((given
& 0x00800000) == 0)
309 arm_regnames
[given
& 0xf]);
313 ((given
& 0x00200000) != 0) ? "!" : "");
318 if ((given
& 0x00400000) == 0x00400000)
321 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
323 func (stream
, "], %s#%d",
324 (((given
& 0x00800000) == 0)
325 ? "-" : ""), offset
);
332 func (stream
, "], %s%s",
333 (((given
& 0x00800000) == 0)
335 arm_regnames
[given
& 0xf]);
342 (*info
->print_address_func
)
343 (BDISP (given
) * 4 + pc
+ 8, info
);
348 arm_conditional
[(given
>> 28) & 0xf]);
357 for (reg
= 0; reg
< 16; reg
++)
358 if ((given
& (1 << reg
)) != 0)
363 func (stream
, "%s", arm_regnames
[reg
]);
370 if ((given
& 0x02000000) != 0)
372 int rotate
= (given
& 0xf00) >> 7;
373 int immed
= (given
& 0xff);
374 immed
= (((immed
<< (32 - rotate
))
375 | (immed
>> rotate
)) & 0xffffffff);
376 func (stream
, "#%d\t; 0x%x", immed
, immed
);
379 arm_decode_shift (given
, func
, stream
);
383 if ((given
& 0x0000f000) == 0x0000f000)
388 if ((given
& 0x01200000) == 0x00200000)
393 if ((given
& 0x00000020) == 0x00000020)
400 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
401 if ((given
& 0x01000000) != 0)
403 int offset
= given
& 0xff;
405 func (stream
, ", %s#%d]%s",
406 ((given
& 0x00800000) == 0 ? "-" : ""),
408 ((given
& 0x00200000) != 0 ? "!" : ""));
414 int offset
= given
& 0xff;
416 func (stream
, "], %s#%d",
417 ((given
& 0x00800000) == 0 ? "-" : ""),
425 switch (given
& 0x000f0000)
428 func (stream
, "_???");
431 func (stream
, "_all");
449 switch (given
& 0x00408000)
466 switch (given
& 0x00080080)
478 func (stream
, _("<illegal precision>"));
483 switch (given
& 0x00408000)
500 switch (given
& 0x60)
516 case '0': case '1': case '2': case '3': case '4':
517 case '5': case '6': case '7': case '8': case '9':
519 int bitstart
= *c
++ - '0';
521 while (*c
>= '0' && *c
<= '9')
522 bitstart
= (bitstart
* 10) + *c
++ - '0';
529 while (*c
>= '0' && *c
<= '9')
530 bitend
= (bitend
* 10) + *c
++ - '0';
541 reg
= given
>> bitstart
;
542 reg
&= (2 << (bitend
- bitstart
)) - 1;
544 func (stream
, "%s", arm_regnames
[reg
]);
551 reg
= given
>> bitstart
;
552 reg
&= (2 << (bitend
- bitstart
)) - 1;
554 func (stream
, "%d", reg
);
561 reg
= given
>> bitstart
;
562 reg
&= (2 << (bitend
- bitstart
)) - 1;
564 func (stream
, "0x%08x", reg
);
566 /* Some SWI instructions have special
568 if ((given
& 0x0fffffff) == 0x0FF00000)
569 func (stream
, "\t; IMB");
570 else if ((given
& 0x0fffffff) == 0x0FF00001)
571 func (stream
, "\t; IMBRange");
578 reg
= given
>> bitstart
;
579 reg
&= (2 << (bitend
- bitstart
)) - 1;
581 func (stream
, "%01x", reg
& 0xf);
588 reg
= given
>> bitstart
;
589 reg
&= (2 << (bitend
- bitstart
)) - 1;
593 arm_fp_const
[reg
& 7]);
595 func (stream
, "f%d", reg
);
605 if ((given
& (1 << bitstart
)) == 0)
606 func (stream
, "%c", *c
);
610 if ((given
& (1 << bitstart
)) != 0)
611 func (stream
, "%c", *c
);
615 if ((given
& (1 << bitstart
)) != 0)
616 func (stream
, "%c", *c
++);
618 func (stream
, "%c", *++c
);
631 func (stream
, "%c", *c
);
639 /* Print one instruction from PC on INFO->STREAM.
640 Return the size of the instruction. */
642 print_insn_thumb (pc
, info
, given
)
644 struct disassemble_info
* info
;
647 struct thumb_opcode
* insn
;
648 void * stream
= info
->stream
;
649 fprintf_ftype func
= info
->fprintf_func
;
651 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
653 if ((given
& insn
->mask
) == insn
->value
)
655 char * c
= insn
->assembler
;
657 /* Special processing for Thumb 2 instruction BL sequence: */
658 if (!*c
) /* Check for empty (not NULL) assembler string. */
660 info
->bytes_per_chunk
= 4;
661 info
->bytes_per_line
= 4;
663 func (stream
, "bl\t");
665 info
->print_address_func (BDISP23 (given
) * 2 + pc
+ 4, info
);
670 info
->bytes_per_chunk
= 2;
671 info
->bytes_per_line
= 4;
692 reg
= (given
>> 3) & 0x7;
693 if (given
& (1 << 6))
696 func (stream
, "%s", arm_regnames
[reg
]);
705 if (given
& (1 << 7))
708 func (stream
, "%s", arm_regnames
[reg
]);
714 arm_conditional
[(given
>> 8) & 0xf]);
718 if (given
& (1 << 8))
722 if (*c
== 'O' && (given
& (1 << 8)))
732 /* It would be nice if we could spot
733 ranges, and generate the rS-rE format: */
734 for (reg
= 0; (reg
< 8); reg
++)
735 if ((given
& (1 << reg
)) != 0)
740 func (stream
, "%s", arm_regnames
[reg
]);
748 func (stream
, arm_regnames
[14] /* "lr" */);
755 func (stream
, arm_regnames
[15] /* "pc" */);
763 case '0': case '1': case '2': case '3': case '4':
764 case '5': case '6': case '7': case '8': case '9':
766 int bitstart
= *c
++ - '0';
769 while (*c
>= '0' && *c
<= '9')
770 bitstart
= (bitstart
* 10) + *c
++ - '0';
779 while (*c
>= '0' && *c
<= '9')
780 bitend
= (bitend
* 10) + *c
++ - '0';
783 reg
= given
>> bitstart
;
784 reg
&= (2 << (bitend
- bitstart
)) - 1;
788 func (stream
, "%s", arm_regnames
[reg
]);
792 func (stream
, "%d", reg
);
796 func (stream
, "%d", reg
<< 1);
800 func (stream
, "%d", reg
<< 2);
804 /* PC-relative address -- the bottom two
805 bits of the address are dropped
806 before the calculation. */
807 info
->print_address_func
808 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
812 func (stream
, "0x%04x", reg
);
816 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
817 func (stream
, "%d", reg
);
821 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
822 (*info
->print_address_func
)
823 (reg
* 2 + pc
+ 4, info
);
834 if ((given
& (1 << bitstart
)) != 0)
835 func (stream
, "%c", *c
);
840 if ((given
& (1 << bitstart
)) != 0)
841 func (stream
, "%c", *c
++);
843 func (stream
, "%c", *++c
);
857 func (stream
, "%c", *c
);
868 /* Parse an individual disassembler option. */
870 parse_arm_disassembler_option (option
)
876 if (strneq (option
, "reg-names-", 10))
882 for (i
= NUM_ARM_REGNAMES
; i
--;)
883 if (streq (option
, regnames
[i
].name
))
885 regname_selected
= i
;
890 fprintf (stderr
, _("Unrecognised register name set: %s\n"), option
);
892 else if (streq (option
, "force-thumb"))
894 else if (streq (option
, "no-force-thumb"))
897 fprintf (stderr
, _("Unrecognised disassembler option: %s\n"), option
);
902 /* Parse the string of disassembler options, spliting it at whitespaces. */
904 parse_disassembler_options (options
)
914 space
= strchr (options
, ' ');
919 parse_arm_disassembler_option (options
);
924 parse_arm_disassembler_option (options
);
929 /* NOTE: There are no checks in these routines that
930 the relevant number of data bytes exist. */
932 print_insn (pc
, info
, little
)
934 struct disassemble_info
* info
;
942 if (info
->disassembler_options
)
944 parse_disassembler_options (info
->disassembler_options
);
946 /* To avoid repeated parsing of these options, we remove them here. */
947 info
->disassembler_options
= NULL
;
950 is_thumb
= force_thumb
;
952 if (!is_thumb
&& info
->symbols
!= NULL
)
954 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
956 coff_symbol_type
* cs
;
958 cs
= coffsymbol (*info
->symbols
);
959 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
960 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
961 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
962 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
963 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
965 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
)
967 elf_symbol_type
* es
;
970 es
= *(elf_symbol_type
**)(info
->symbols
);
971 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
973 is_thumb
= (type
== STT_ARM_TFUNC
) || (type
== STT_ARM_16BIT
);
977 info
->bytes_per_chunk
= 4;
978 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
982 status
= info
->read_memory_func (pc
, (bfd_byte
*) &b
[0], 4, info
);
983 if (status
!= 0 && is_thumb
)
985 info
->bytes_per_chunk
= 2;
987 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
993 info
->memory_error_func (status
, pc
, info
);
997 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | (b
[3] << 24);
1001 status
= info
->read_memory_func
1002 (pc
& ~ 0x3, (bfd_byte
*) &b
[0], 4, info
);
1005 info
->memory_error_func (status
, pc
, info
);
1013 given
= (b
[2] << 8) | b
[3];
1015 status
= info
->read_memory_func
1016 ((pc
+ 4) & ~ 0x3, (bfd_byte
*) b
, 4, info
);
1019 info
->memory_error_func (status
, pc
+ 4, info
);
1023 given
|= (b
[0] << 24) | (b
[1] << 16);
1026 given
= (b
[0] << 8) | b
[1] | (b
[2] << 24) | (b
[3] << 16);
1029 given
= (b
[0] << 24) | (b
[1] << 16) | (b
[2] << 8) | (b
[3]);
1033 status
= print_insn_thumb (pc
, info
, given
);
1035 status
= print_insn_arm (pc
, info
, given
);
1041 print_insn_big_arm (pc
, info
)
1043 struct disassemble_info
* info
;
1045 return print_insn (pc
, info
, false);
1049 print_insn_little_arm (pc
, info
)
1051 struct disassemble_info
* info
;
1053 return print_insn (pc
, info
, true);
1057 print_arm_disassembler_options (FILE * stream
)
1061 fprintf (stream
, _("\n\
1062 The following ARM specific disassembler options are supported for use with\n\
1063 the -M switch:\n"));
1065 for (i
= NUM_ARM_REGNAMES
; i
--;)
1066 fprintf (stream
, " reg-names-%s %*c%s\n",
1068 14 - strlen (regnames
[i
].name
), ' ',
1069 regnames
[i
].description
);
1071 fprintf (stream
, " force-thumb Assume all insns are Thumb insns\n");
1072 fprintf (stream
, " no-force-thumb Examine preceeding label to determine an insn's type\n\n");