1 /* Instruction printing code for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This program is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2 of the License, or (at your option)
13 This program is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
26 #include "coff/internal.h"
30 /* FIXME: This shouldn't be done here */
32 #include "elf/internal.h"
35 static char * arm_conditional
[] =
36 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
37 "hi", "ls", "ge", "lt", "gt", "le", "", "nv"};
39 static char * arm_regnames_raw
[] =
40 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
41 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
43 static char * arm_regnames_standard
[] =
44 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
45 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc"};
47 static char * arm_regnames_apcs
[] =
48 {"a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4",
49 "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc"};
51 /* Choose which register name set to use. */
52 static char ** arm_regnames
= arm_regnames_standard
;
54 static char * arm_fp_const
[] =
55 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
57 static char * arm_shift
[] =
58 {"lsl", "lsr", "asr", "ror"};
60 static int print_insn_arm
61 PARAMS ((bfd_vma
, struct disassemble_info
*, long));
64 arm_decode_shift (given
, func
, stream
)
69 func (stream
, "%s", arm_regnames
[given
& 0xf]);
71 if ((given
& 0xff0) != 0)
73 if ((given
& 0x10) == 0)
75 int amount
= (given
& 0xf80) >> 7;
76 int shift
= (given
& 0x60) >> 5;
82 func (stream
, ", rrx");
89 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
92 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
93 arm_regnames
[(given
& 0xf00) >> 8]);
97 /* Print one instruction from PC on INFO->STREAM.
98 Return the size of the instruction (always 4 on ARM). */
101 print_insn_arm (pc
, info
, given
)
103 struct disassemble_info
* info
;
106 struct arm_opcode
* insn
;
107 void * stream
= info
->stream
;
108 fprintf_ftype func
= info
->fprintf_func
;
110 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
112 if ((given
& insn
->mask
) == insn
->value
)
116 for (c
= insn
->assembler
; *c
; c
++)
127 if (((given
& 0x000f0000) == 0x000f0000)
128 && ((given
& 0x02000000) == 0))
130 int offset
= given
& 0xfff;
132 func (stream
, "[pc");
134 if (given
& 0x01000000)
136 if ((given
& 0x00800000) == 0)
140 func (stream
, ", #%x]", offset
);
144 /* Cope with the possibility of write-back being used.
145 Probably a very dangerous thing for the programmer
146 to do, but who are we to argue ? */
147 if (given
& 0x00200000)
153 func (stream
, "], #%x", offset
);
155 offset
= pc
+ 8; /* ie ignore the offset */
158 func (stream
, "\t; ");
159 info
->print_address_func (offset
, info
);
164 arm_regnames
[(given
>> 16) & 0xf]);
165 if ((given
& 0x01000000) != 0)
167 if ((given
& 0x02000000) == 0)
169 int offset
= given
& 0xfff;
171 func (stream
, ", %s#%d",
172 (((given
& 0x00800000) == 0)
173 ? "-" : ""), offset
);
177 func (stream
, ", %s",
178 (((given
& 0x00800000) == 0)
180 arm_decode_shift (given
, func
, stream
);
184 ((given
& 0x00200000) != 0) ? "!" : "");
188 if ((given
& 0x02000000) == 0)
190 int offset
= given
& 0xfff;
192 func (stream
, "], %s#%d",
193 (((given
& 0x00800000) == 0)
194 ? "-" : ""), offset
);
200 func (stream
, "], %s",
201 (((given
& 0x00800000) == 0)
203 arm_decode_shift (given
, func
, stream
);
210 if ((given
& 0x004f0000) == 0x004f0000)
212 /* PC relative with immediate offset */
213 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
215 if ((given
& 0x00800000) == 0)
218 func (stream
, "[pc, #%x]\t; ", offset
);
220 (*info
->print_address_func
)
221 (offset
+ pc
+ 8, info
);
226 arm_regnames
[(given
>> 16) & 0xf]);
227 if ((given
& 0x01000000) != 0)
230 if ((given
& 0x00400000) == 0x00400000)
233 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
235 func (stream
, ", %s#%d",
236 (((given
& 0x00800000) == 0)
237 ? "-" : ""), offset
);
242 func (stream
, ", %s%s",
243 (((given
& 0x00800000) == 0)
245 arm_regnames
[given
& 0xf]);
249 ((given
& 0x00200000) != 0) ? "!" : "");
254 if ((given
& 0x00400000) == 0x00400000)
257 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
259 func (stream
, "], %s#%d",
260 (((given
& 0x00800000) == 0)
261 ? "-" : ""), offset
);
268 func (stream
, "], %s%s",
269 (((given
& 0x00800000) == 0)
271 arm_regnames
[given
& 0xf]);
278 (*info
->print_address_func
)
279 (BDISP (given
) * 4 + pc
+ 8, info
);
284 arm_conditional
[(given
>> 28) & 0xf]);
293 for (reg
= 0; reg
< 16; reg
++)
294 if ((given
& (1 << reg
)) != 0)
299 func (stream
, "%s", arm_regnames
[reg
]);
306 if ((given
& 0x02000000) != 0)
308 int rotate
= (given
& 0xf00) >> 7;
309 int immed
= (given
& 0xff);
310 immed
= (((immed
<< (32 - rotate
))
311 | (immed
>> rotate
)) & 0xffffffff);
312 func (stream
, "#%d\t; 0x%x", immed
, immed
);
315 arm_decode_shift (given
, func
, stream
);
319 if ((given
& 0x0000f000) == 0x0000f000)
324 if ((given
& 0x01200000) == 0x00200000)
329 if ((given
& 0x00000020) == 0x00000020)
336 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
337 if ((given
& 0x01000000) != 0)
339 int offset
= given
& 0xff;
341 func (stream
, ", %s#%d]%s",
342 ((given
& 0x00800000) == 0 ? "-" : ""),
344 ((given
& 0x00200000) != 0 ? "!" : ""));
350 int offset
= given
& 0xff;
352 func (stream
, "], %s#%d",
353 ((given
& 0x00800000) == 0 ? "-" : ""),
361 switch (given
& 0x00090000)
364 func (stream
, "_???");
367 func (stream
, "_all");
370 func (stream
, "_ctl");
373 func (stream
, "_flg");
379 switch (given
& 0x00408000)
396 switch (given
& 0x00080080)
408 func (stream
, _("<illegal precision>"));
413 switch (given
& 0x00408000)
430 switch (given
& 0x60)
446 case '0': case '1': case '2': case '3': case '4':
447 case '5': case '6': case '7': case '8': case '9':
449 int bitstart
= *c
++ - '0';
451 while (*c
>= '0' && *c
<= '9')
452 bitstart
= (bitstart
* 10) + *c
++ - '0';
458 while (*c
>= '0' && *c
<= '9')
459 bitend
= (bitend
* 10) + *c
++ - '0';
467 reg
= given
>> bitstart
;
468 reg
&= (2 << (bitend
- bitstart
)) - 1;
469 func (stream
, "%s", arm_regnames
[reg
]);
475 reg
= given
>> bitstart
;
476 reg
&= (2 << (bitend
- bitstart
)) - 1;
477 func (stream
, "%d", reg
);
483 reg
= given
>> bitstart
;
484 reg
&= (2 << (bitend
- bitstart
)) - 1;
485 func (stream
, "0x%08x", reg
);
487 /* Some SWI instructions have special meanings. */
488 if ((given
& 0x0fffffff) == 0x0FF00000)
489 func (stream
, "\t; IMB");
490 else if ((given
& 0x0fffffff) == 0x0FF00001)
491 func (stream
, "\t; IMBRange");
497 reg
= given
>> bitstart
;
498 reg
&= (2 << (bitend
- bitstart
)) - 1;
499 func (stream
, "%01x", reg
& 0xf);
505 reg
= given
>> bitstart
;
506 reg
&= (2 << (bitend
- bitstart
)) - 1;
509 arm_fp_const
[reg
& 7]);
511 func (stream
, "f%d", reg
);
520 if ((given
& (1 << bitstart
)) == 0)
521 func (stream
, "%c", *c
);
525 if ((given
& (1 << bitstart
)) != 0)
526 func (stream
, "%c", *c
);
530 if ((given
& (1 << bitstart
)) != 0)
531 func (stream
, "%c", *c
++);
533 func (stream
, "%c", *++c
);
546 func (stream
, "%c", *c
);
554 /* Print one instruction from PC on INFO->STREAM.
555 Return the size of the instruction. */
558 print_insn_thumb (pc
, info
, given
)
560 struct disassemble_info
* info
;
563 struct thumb_opcode
* insn
;
564 void * stream
= info
->stream
;
565 fprintf_ftype func
= info
->fprintf_func
;
567 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
569 if ((given
& insn
->mask
) == insn
->value
)
571 char * c
= insn
->assembler
;
573 /* Special processing for Thumb 2 instruction BL sequence: */
574 if (!*c
) /* check for empty (not NULL) assembler string */
576 info
->bytes_per_chunk
= 4;
577 info
->bytes_per_line
= 4;
579 func (stream
, "%04x\tbl\t", given
& 0xffff);
580 (*info
->print_address_func
)
581 (BDISP23 (given
) * 2 + pc
+ 4, info
);
586 info
->bytes_per_chunk
= 2;
587 info
->bytes_per_line
= 4;
590 func (stream
, "%04x\t", given
);
608 reg
= (given
>> 3) & 0x7;
609 if (given
& (1 << 6))
611 func (stream
, "%s", arm_regnames
[reg
]);
620 if (given
& (1 << 7))
622 func (stream
, "%s", arm_regnames
[reg
]);
628 arm_conditional
[(given
>> 8) & 0xf]);
632 if (given
& (1 << 8))
636 if (*c
== 'O' && (given
& (1 << 8)))
645 /* It would be nice if we could spot
646 ranges, and generate the rS-rE format: */
647 for (reg
= 0; (reg
< 8); reg
++)
648 if ((given
& (1 << reg
)) != 0)
653 func (stream
, "%s", arm_regnames
[reg
]);
676 case '0': case '1': case '2': case '3': case '4':
677 case '5': case '6': case '7': case '8': case '9':
679 int bitstart
= *c
++ - '0';
682 while (*c
>= '0' && *c
<= '9')
683 bitstart
= (bitstart
* 10) + *c
++ - '0';
692 while (*c
>= '0' && *c
<= '9')
693 bitend
= (bitend
* 10) + *c
++ - '0';
696 reg
= given
>> bitstart
;
697 reg
&= (2 << (bitend
- bitstart
)) - 1;
701 func (stream
, "%s", arm_regnames
[reg
]);
705 func (stream
, "%d", reg
);
709 func (stream
, "%d", reg
<< 1);
713 func (stream
, "%d", reg
<< 2);
717 /* PC-relative address -- the bottom two
718 bits of the address are dropped before
720 info
->print_address_func
721 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
725 func (stream
, "0x%04x", reg
);
729 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
730 func (stream
, "%d", reg
);
734 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
735 (*info
->print_address_func
)
736 (reg
* 2 + pc
+ 4, info
);
747 if ((given
& (1 << bitstart
)) != 0)
748 func (stream
, "%c", *c
);
753 if ((given
& (1 << bitstart
)) != 0)
754 func (stream
, "%c", *c
++);
756 func (stream
, "%c", *++c
);
770 func (stream
, "%c", *c
);
781 /* Select a different register name set.
782 Returns true if the name set selected is the APCS name set. */
784 arm_toggle_regnames ()
786 if (arm_regnames
== arm_regnames_standard
)
787 arm_regnames
= arm_regnames_apcs
;
789 arm_regnames
= arm_regnames_standard
;
791 return arm_regnames
== arm_regnames_apcs
;
795 parse_disassembler_options (options
)
801 if (strncmp (options
, "reg-names-", 10) == 0)
805 if (strcmp (options
, "std") == 0)
806 arm_regnames
= arm_regnames_standard
;
807 else if (strcmp (options
, "apcs") == 0)
808 arm_regnames
= arm_regnames_apcs
;
809 else if (strcmp (options
, "raw") == 0)
810 arm_regnames
= arm_regnames_raw
;
812 fprintf (stderr
, "Unrecognised register name set: %s\n", options
);
815 fprintf (stderr
, "Unrecognised disassembler option: %s\n", options
);
820 /* NOTE: There are no checks in these routines that the relevant number of data bytes exist */
823 print_insn_big_arm (pc
, info
)
825 struct disassemble_info
* info
;
830 coff_symbol_type
* cs
;
831 elf_symbol_type
* es
;
834 if (info
->disassembler_options
)
836 parse_disassembler_options (info
->disassembler_options
);
838 /* To avoid repeated parsing of this option, we remove it here. */
839 info
->disassembler_options
= NULL
;
843 if (info
->symbols
!= NULL
)
845 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
847 cs
= coffsymbol (*info
->symbols
);
848 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
849 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
850 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
851 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
852 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
854 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
)
856 es
= *(elf_symbol_type
**)(info
->symbols
);
857 is_thumb
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
) ==
862 info
->bytes_per_chunk
= 4;
863 info
->display_endian
= BFD_ENDIAN_BIG
;
865 /* Always fetch word aligned values. */
867 status
= (*info
->read_memory_func
) (pc
& ~ 0x3, (bfd_byte
*) &b
[0], 4, info
);
870 (*info
->memory_error_func
) (status
, pc
, info
);
878 given
= (b
[2] << 8) | b
[3];
880 status
= info
->read_memory_func ((pc
+ 4) & ~ 0x3, (bfd_byte
*) b
, 4, info
);
883 info
->memory_error_func (status
, pc
+ 4, info
);
887 given
|= (b
[0] << 24) | (b
[1] << 16);
890 given
= (b
[0] << 8) | b
[1] | (b
[2] << 24) | (b
[3] << 16);
893 given
= (b
[0] << 24) | (b
[1] << 16) | (b
[2] << 8) | (b
[3]);
896 status
= print_insn_thumb (pc
, info
, given
);
898 status
= print_insn_arm (pc
, info
, given
);
904 print_insn_little_arm (pc
, info
)
906 struct disassemble_info
* info
;
911 coff_symbol_type
* cs
;
912 elf_symbol_type
* es
;
915 if (info
->disassembler_options
)
917 parse_disassembler_options (info
->disassembler_options
);
919 /* To avoid repeated parsing of this option, we remove it here. */
920 info
->disassembler_options
= NULL
;
925 if (info
->symbols
!= NULL
)
927 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
929 cs
= coffsymbol (*info
->symbols
);
930 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
931 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
932 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
933 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
934 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
936 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
)
938 es
= *(elf_symbol_type
**)(info
->symbols
);
939 is_thumb
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
) ==
944 info
->bytes_per_chunk
= 4;
945 info
->display_endian
= BFD_ENDIAN_LITTLE
;
947 status
= (*info
->read_memory_func
) (pc
, (bfd_byte
*) &b
[0], 4, info
);
948 if (status
!= 0 && is_thumb
)
950 info
->bytes_per_chunk
= 2;
952 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
957 (*info
->memory_error_func
) (status
, pc
, info
);
961 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | (b
[3] << 24);
964 status
= print_insn_thumb (pc
, info
, given
);
966 status
= print_insn_arm (pc
, info
, given
);
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