opcodes/arm-opc.h

   1 /* Opcode table for the ARM.
   2
   3    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000
   4    Free Software Foundation, Inc.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 2, or (at your option)
   9    any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20
  21 struct arm_opcode {
  22     unsigned long value, mask;  /* recognise instruction if (op&mask)==value */
  23     char *assembler;            /* how to disassemble this instruction */
  24 };
  25
  26 struct thumb_opcode
  27 {
  28     unsigned short value, mask; /* recognise instruction if (op&mask)==value */
  29     char * assembler;           /* how to disassemble this instruction */
  30 };
  31
  32 /* format of the assembler string :
  33
  34    %%                   %
  35    %<bitfield>d         print the bitfield in decimal
  36    %<bitfield>x         print the bitfield in hex
  37    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
  38    %<bitfield>r         print as an ARM register
  39    %<bitfield>f         print a floating point constant if >7 else a
  40                         floating point register
  41    %c                   print condition code (always bits 28-31)
  42    %P                   print floating point precision in arithmetic insn
  43    %Q                   print floating point precision in ldf/stf insn
  44    %R                   print floating point rounding mode
  45    %<bitnum>'c          print specified char iff bit is one
  46    %<bitnum>`c          print specified char iff bit is zero
  47    %<bitnum>?ab         print a if bit is one else print b
  48    %p                   print 'p' iff bits 12-15 are 15
  49    %t                   print 't' iff bit 21 set and bit 24 clear
  50    %h                   print 'h' iff bit 5 set, else print 'b'
  51    %o                   print operand2 (immediate or register + shift)
  52    %a                   print address for ldr/str instruction
  53    %s                   print address for ldr/str halfword/signextend instruction
  54    %b                   print branch destination
  55    %B                   print arm BLX(1) destination
  56    %A                   print address for ldc/stc/ldf/stf instruction
  57    %m                   print register mask for ldm/stm instruction
  58    %C                   print the PSR sub type.
  59    %F                   print the COUNT field of a LFM/SFM instruction.
  60 Thumb specific format options:
  61    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
  62    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
  63    %<bitfield>I         print bitfield as a signed decimal
  64                                 (top bit of range being the sign bit)
  65    %M                   print Thumb register mask
  66    %N                   print Thumb register mask (with LR)
  67    %O                   print Thumb register mask (with PC)
  68    %T                   print Thumb condition code (always bits 8-11)
  69    %I                   print cirrus signed shift immediate: bits 0..3|4..6
  70    %<bitfield>B         print Thumb branch destination (signed displacement)
  71    %<bitfield>W         print (bitfield * 4) as a decimal
  72    %<bitfield>H         print (bitfield * 2) as a decimal
  73    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
  74 */
  75
  76 /* Note: There is a partial ordering in this table - it must be searched from
  77    the top to obtain a correct match. */
  78
  79 static struct arm_opcode arm_opcodes[] =
  80 {
  81     /* ARM instructions.  */
  82     {0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
  83     {0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
  84     {0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"},
  85     {0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"},
  86     {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"},
  87     {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
  88     {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
  89
  90     /* XScale instructions.  */
  91     {0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
  92     {0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
  93     {0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
  94     {0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
  95     {0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
  96     {0xf450f000, 0xfc70f000, "pld\t%a"},
  97
  98     /* V5 Instructions.  */
  99     {0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
 100     {0xfa000000, 0xfe000000, "blx\t%B"},
 101     {0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"},
 102     {0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"},
 103     {0xfc100000, 0xfe100000, "ldc2%22'l\t%8-11d, cr%12-15d, %A"},
 104     {0xfc000000, 0xfe100000, "stc2%22'l\t%8-11d, cr%12-15d, %A"},
 105     {0xfe000000, 0xff000010, "cdp2\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 106     {0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 107     {0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 108
 109     /* V5E "El Segundo" Instructions.  */
 110     {0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"},
 111     {0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"},
 112     {0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
 113     {0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
 114     {0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
 115     {0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
 116
 117     {0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
 118     {0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
 119
 120     {0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
 121     {0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
 122     {0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
 123     {0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
 124
 125     {0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"},
 126     {0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"},
 127     {0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"},
 128     {0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"},
 129
 130     {0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"},
 131     {0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"},
 132
 133     {0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15r, %0-3r, %16-19r"},
 134     {0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"},
 135     {0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15r, %0-3r, %16-19r"},
 136     {0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
 137
 138     {0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
 139     {0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
 140
 141     /* ARM Instructions.  */
 142     {0x00000090, 0x0e100090, "str%c%6's%h\t%12-15r, %s"},
 143     {0x00100090, 0x0e100090, "ldr%c%6's%h\t%12-15r, %s"},
 144     {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"},
 145     {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"},
 146     {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"},
 147     {0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"},
 148     {0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"},
 149     {0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"},
 150     {0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"},
 151     {0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"},
 152     {0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
 153     {0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},
 154     {0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"},
 155     {0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"},
 156     {0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"},
 157     {0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"},
 158     {0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"},
 159     {0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"},
 160     {0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"},
 161     {0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"},
 162     {0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"},
 163     {0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"},
 164     {0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"},
 165     {0x06000010, 0x0e000010, "undefined"},
 166     {0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"},
 167     {0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
 168     {0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
 169     {0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
 170     {0x0f000000, 0x0f000000, "swi%c\t%0-23x"},
 171
 172     /* Floating point coprocessor instructions */
 173     {0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 174     {0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 175     {0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 176     {0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 177     {0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 178     {0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 179     {0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 180     {0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 181     {0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 182     {0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 183     {0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 184     {0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 185     {0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 186     {0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 187     {0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 188     {0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 189     {0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 190     {0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 191     {0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 192     {0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 193     {0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 194     {0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 195     {0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 196     {0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 197     {0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 198     {0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 199     {0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 200     {0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 201     {0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 202     {0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 203     {0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 204     {0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 205     {0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 206     {0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 207     {0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 208     {0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 209     {0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 210     {0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 211     {0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 212     {0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 213     {0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 214     {0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 215     {0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 216
 217     /* Cirrus coprocessor instructions.  */
 218     {0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 219     {0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 220     {0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 221     {0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 222     {0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 223     {0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 224     {0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 225     {0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 226     {0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 227     {0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 228     {0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 229     {0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 230     {0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 231     {0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 232     {0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 233     {0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 234     {0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
 235     {0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
 236     {0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
 237     {0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
 238     {0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
 239     {0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
 240     {0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
 241     {0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
 242     {0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
 243     {0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
 244     {0x0e100610, 0x0ff0fff0, "cfmval32%c\tmvax%0-3d, mvfx%16-19d"},
 245     {0x0e000610, 0x0ff0fff0, "cfmv32al%c\tmvfx%0-3d, mvax%16-19d"},
 246     {0x0e100630, 0x0ff0fff0, "cfmvam32%c\tmvax%0-3d, mvfx%16-19d"},
 247     {0x0e000630, 0x0ff0fff0, "cfmv32am%c\tmvfx%0-3d, mvax%16-19d"},
 248     {0x0e100650, 0x0ff0fff0, "cfmvah32%c\tmvax%0-3d, mvfx%16-19d"},
 249     {0x0e000650, 0x0ff0fff0, "cfmv32ah%c\tmvfx%0-3d, mvax%16-19d"},
 250     {0x0e000670, 0x0ff0fff0, "cfmv32a%c\tmvfx%0-3d, mvax%16-19d"},
 251     {0x0e100670, 0x0ff0fff0, "cfmva32%c\tmvax%0-3d, mvfx%16-19d"},
 252     {0x0e000690, 0x0ff0fff0, "cfmv64a%c\tmvdx%0-3d, mvax%16-19d"},
 253     {0x0e100690, 0x0ff0fff0, "cfmva64%c\tmvax%0-3d, mvdx%16-19d"},
 254     {0x0e1006b0, 0x0ff0fff0, "cfmvsc32%c\tdspsc, mvfx%16-19d"},
 255     {0x0e0006b0, 0x0ff0fff0, "cfmv32sc%c\tmvfx%0-3d, dspsc"},
 256     {0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
 257     {0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
 258     {0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
 259     {0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
 260     {0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
 261     {0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
 262     {0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
 263     {0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
 264     {0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
 265     {0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
 266     {0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
 267     {0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
 268     {0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
 269     {0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
 270     {0x0e000500, 0x0ff00f00, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
 271     {0x0e200500, 0x0ff00f00, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
 272     {0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
 273     {0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
 274     {0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
 275     {0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
 276     {0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
 277     {0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
 278     {0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
 279     {0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
 280     {0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 281     {0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 282     {0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 283     {0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 284     {0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 285     {0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 286     {0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
 287     {0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
 288     {0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
 289     {0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
 290     {0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 291     {0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 292     {0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 293     {0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 294     {0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 295     {0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 296     {0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 297     {0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 298     {0x0e000600, 0x0ff00f00, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 299     {0x0e100600, 0x0ff00f00, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 300     {0x0e200600, 0x0ff00f00, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 301     {0x0e300600, 0x0ff00f00, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 302
 303     /* Generic coprocessor instructions */
 304     {0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 305     {0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 306     {0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 307     {0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"},
 308     {0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"},
 309
 310     /* The rest.  */
 311     {0x00000000, 0x00000000, "undefined instruction %0-31x"},
 312     {0x00000000, 0x00000000, 0}
 313 };
 314
 315 #define BDISP(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000) /* 26 bit */
 316
 317 static struct thumb_opcode thumb_opcodes[] =
 318 {
 319   /* Thumb instructions.  */
 320
 321   /* ARM V5 ISA extends Thumb.  */
 322   {0xbe00, 0xff00, "bkpt\t%0-7x"},
 323   {0x4780, 0xff87, "blx\t%3-6r"},       /* note: 4 bit register number.  */
 324   /* Note: this is BLX(2).  BLX(1) is done in arm-dis.c/print_insn_thumb()
 325      as an extension of the special processing there for Thumb BL.
 326      BL and BLX(1) involve 2 successive 16-bit instructions, which must
 327      always appear together in the correct order.  So, the empty
 328      string is put in this table, and the string interpreter takes <empty>
 329      to mean it has a pair of BL-ish instructions.  */
 330   {0x46C0, 0xFFFF, "nop\t\t\t(mov r8, r8)"},
 331   /* Format 5 instructions do not update the PSR.  */
 332   {0x1C00, 0xFFC0, "mov\t%0-2r, %3-5r\t\t(add %0-2r, %3-5r, #%6-8d)"},
 333   /* Format 4.  */
 334   {0x4000, 0xFFC0, "and\t%0-2r, %3-5r"},
 335   {0x4040, 0xFFC0, "eor\t%0-2r, %3-5r"},
 336   {0x4080, 0xFFC0, "lsl\t%0-2r, %3-5r"},
 337   {0x40C0, 0xFFC0, "lsr\t%0-2r, %3-5r"},
 338   {0x4100, 0xFFC0, "asr\t%0-2r, %3-5r"},
 339   {0x4140, 0xFFC0, "adc\t%0-2r, %3-5r"},
 340   {0x4180, 0xFFC0, "sbc\t%0-2r, %3-5r"},
 341   {0x41C0, 0xFFC0, "ror\t%0-2r, %3-5r"},
 342   {0x4200, 0xFFC0, "tst\t%0-2r, %3-5r"},
 343   {0x4240, 0xFFC0, "neg\t%0-2r, %3-5r"},
 344   {0x4280, 0xFFC0, "cmp\t%0-2r, %3-5r"},
 345   {0x42C0, 0xFFC0, "cmn\t%0-2r, %3-5r"},
 346   {0x4300, 0xFFC0, "orr\t%0-2r, %3-5r"},
 347   {0x4340, 0xFFC0, "mul\t%0-2r, %3-5r"},
 348   {0x4380, 0xFFC0, "bic\t%0-2r, %3-5r"},
 349   {0x43C0, 0xFFC0, "mvn\t%0-2r, %3-5r"},
 350   /* format 13 */
 351   {0xB000, 0xFF80, "add\tsp, #%0-6W"},
 352   {0xB080, 0xFF80, "sub\tsp, #%0-6W"},
 353   /* format 5 */
 354   {0x4700, 0xFF80, "bx\t%S"},
 355   {0x4400, 0xFF00, "add\t%D, %S"},
 356   {0x4500, 0xFF00, "cmp\t%D, %S"},
 357   {0x4600, 0xFF00, "mov\t%D, %S"},
 358   /* format 14 */
 359   {0xB400, 0xFE00, "push\t%N"},
 360   {0xBC00, 0xFE00, "pop\t%O"},
 361   /* format 2 */
 362   {0x1800, 0xFE00, "add\t%0-2r, %3-5r, %6-8r"},
 363   {0x1A00, 0xFE00, "sub\t%0-2r, %3-5r, %6-8r"},
 364   {0x1C00, 0xFE00, "add\t%0-2r, %3-5r, #%6-8d"},
 365   {0x1E00, 0xFE00, "sub\t%0-2r, %3-5r, #%6-8d"},
 366   /* format 8 */
 367   {0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"},
 368   {0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"},
 369   {0x5600, 0xF600, "ldrs%11?hb\t%0-2r, [%3-5r, %6-8r]"},
 370   /* format 7 */
 371   {0x5000, 0xFA00, "str%10'b\t%0-2r, [%3-5r, %6-8r]"},
 372   {0x5800, 0xFA00, "ldr%10'b\t%0-2r, [%3-5r, %6-8r]"},
 373   /* format 1 */
 374   {0x0000, 0xF800, "lsl\t%0-2r, %3-5r, #%6-10d"},
 375   {0x0800, 0xF800, "lsr\t%0-2r, %3-5r, #%6-10d"},
 376   {0x1000, 0xF800, "asr\t%0-2r, %3-5r, #%6-10d"},
 377   /* format 3 */
 378   {0x2000, 0xF800, "mov\t%8-10r, #%0-7d"},
 379   {0x2800, 0xF800, "cmp\t%8-10r, #%0-7d"},
 380   {0x3000, 0xF800, "add\t%8-10r, #%0-7d"},
 381   {0x3800, 0xF800, "sub\t%8-10r, #%0-7d"},
 382   /* format 6 */
 383   {0x4800, 0xF800, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"},  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
 384   /* format 9 */
 385   {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},
 386   {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"},
 387   {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"},
 388   {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"},
 389   /* format 10 */
 390   {0x8000, 0xF800, "strh\t%0-2r, [%3-5r, #%6-10H]"},
 391   {0x8800, 0xF800, "ldrh\t%0-2r, [%3-5r, #%6-10H]"},
 392   /* format 11 */
 393   {0x9000, 0xF800, "str\t%8-10r, [sp, #%0-7W]"},
 394   {0x9800, 0xF800, "ldr\t%8-10r, [sp, #%0-7W]"},
 395   /* format 12 */
 396   {0xA000, 0xF800, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"},
 397   {0xA800, 0xF800, "add\t%8-10r, sp, #%0-7W"},
 398   /* format 15 */
 399   {0xC000, 0xF800, "stmia\t%8-10r!,%M"},
 400   {0xC800, 0xF800, "ldmia\t%8-10r!,%M"},
 401   /* format 18 */
 402   {0xE000, 0xF800, "b\t%0-10B"},
 403   {0xE800, 0xF800, "undefined"},
 404   /* format 19 */
 405   {0xF000, 0xF800, ""}, /* special processing required in disassembler */
 406   {0xF800, 0xF800, "second half of BL instruction %0-15x"},
 407   /* format 16 */
 408   {0xD000, 0xFF00, "beq\t%0-7B"},
 409   {0xD100, 0xFF00, "bne\t%0-7B"},
 410   {0xD200, 0xFF00, "bcs\t%0-7B"},
 411   {0xD300, 0xFF00, "bcc\t%0-7B"},
 412   {0xD400, 0xFF00, "bmi\t%0-7B"},
 413   {0xD500, 0xFF00, "bpl\t%0-7B"},
 414   {0xD600, 0xFF00, "bvs\t%0-7B"},
 415   {0xD700, 0xFF00, "bvc\t%0-7B"},
 416   {0xD800, 0xFF00, "bhi\t%0-7B"},
 417   {0xD900, 0xFF00, "bls\t%0-7B"},
 418   {0xDA00, 0xFF00, "bge\t%0-7B"},
 419   {0xDB00, 0xFF00, "blt\t%0-7B"},
 420   {0xDC00, 0xFF00, "bgt\t%0-7B"},
 421   {0xDD00, 0xFF00, "ble\t%0-7B"},
 422   /* format 17 */
 423   {0xDE00, 0xFF00, "bal\t%0-7B"},
 424   {0xDF00, 0xFF00, "swi\t%0-7d"},
 425   /* format 9 */
 426   {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},
 427   {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"},
 428   {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"},
 429   {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"},
 430   /* the rest */
 431   {0x0000, 0x0000, "undefined instruction %0-15x"},
 432   {0x0000, 0x0000, 0}
 433 };
 434
 435 #define BDISP23(x) ((((((x) & 0x07ff) << 11) | (((x) & 0x07ff0000) >> 16)) \
 436                      ^ 0x200000) - 0x200000) /* 23bit */
 437