1 /* Disassemble ADI Blackfin Instructions.
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 This file is part of libopcodes.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
25 #include "opcode/bfin.h"
47 #define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
48 #define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
49 #define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
50 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
54 typedef unsigned int bu32
;
56 static char comment
= 0;
57 static char parallel
= 0;
61 c_0
, c_1
, c_4
, c_2
, c_uimm2
, c_uimm3
, c_imm3
, c_pcrel4
,
62 c_imm4
, c_uimm4s4
, c_uimm4s4d
, c_uimm4
, c_uimm4s2
, c_negimm5s4
, c_imm5
, c_imm5d
, c_uimm5
, c_imm6
,
63 c_imm7
, c_imm7d
, c_imm8
, c_uimm8
, c_pcrel8
, c_uimm8s4
, c_pcrel8s4
, c_lppcrel10
, c_pcrel10
,
64 c_pcrel12
, c_imm16s4
, c_luimm16
, c_imm16
, c_imm16d
, c_huimm16
, c_rimm16
, c_imm16s2
, c_uimm16s4
,
65 c_uimm16s4d
, c_uimm16
, c_pcrel24
, c_uimm32
, c_imm32
, c_huimm32
, c_huimm32e
,
82 } constant_formats
[] =
84 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
85 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
86 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
88 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
89 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
91 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
92 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
94 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
95 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
97 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
98 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
99 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
100 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
101 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
102 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
103 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
104 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
107 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
108 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
109 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
110 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
111 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
112 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
113 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
114 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
118 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
119 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
120 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
121 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
122 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
123 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
124 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
125 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
126 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
130 fmtconst (const_forms_t cf
, TIword x
, bfd_vma pc
, disassemble_info
*outf
)
134 if (constant_formats
[cf
].reloc
)
136 bfd_vma ea
= (((constant_formats
[cf
].pcrel
? SIGNEXTEND (x
, constant_formats
[cf
].nbits
)
137 : x
) + constant_formats
[cf
].offset
) << constant_formats
[cf
].scale
);
138 if (constant_formats
[cf
].pcrel
)
141 if (outf
->symbol_at_address_func (ea
, outf
) || !constant_formats
[cf
].exact
)
143 outf
->print_address_func (ea
, outf
);
148 sprintf (buf
, "%lx", (unsigned long) x
);
153 /* Negative constants have an implied sign bit. */
154 if (constant_formats
[cf
].negative
)
156 int nb
= constant_formats
[cf
].nbits
+ 1;
158 x
= x
| (1 << constant_formats
[cf
].nbits
);
159 x
= SIGNEXTEND (x
, nb
);
162 x
= constant_formats
[cf
].issigned
? SIGNEXTEND (x
, constant_formats
[cf
].nbits
) : x
;
164 if (constant_formats
[cf
].offset
)
165 x
+= constant_formats
[cf
].offset
;
167 if (constant_formats
[cf
].scale
)
168 x
<<= constant_formats
[cf
].scale
;
170 if (constant_formats
[cf
].decimal
)
172 if (constant_formats
[cf
].leading
)
175 sprintf (ps
, "%%%ii", constant_formats
[cf
].leading
);
176 sprintf (buf
, ps
, x
);
179 sprintf (buf
, "%li", x
);
183 if (constant_formats
[cf
].issigned
&& x
< 0)
184 sprintf (buf
, "-0x%x", abs (x
));
186 sprintf (buf
, "0x%lx", (unsigned long) x
);
193 fmtconst_val (const_forms_t cf
, unsigned int x
, unsigned int pc
)
195 if (0 && constant_formats
[cf
].reloc
)
197 bu32 ea
= (((constant_formats
[cf
].pcrel
198 ? SIGNEXTEND (x
, constant_formats
[cf
].nbits
)
199 : x
) + constant_formats
[cf
].offset
)
200 << constant_formats
[cf
].scale
);
201 if (constant_formats
[cf
].pcrel
)
207 /* Negative constants have an implied sign bit. */
208 if (constant_formats
[cf
].negative
)
210 int nb
= constant_formats
[cf
].nbits
+ 1;
211 x
= x
| (1 << constant_formats
[cf
].nbits
);
212 x
= SIGNEXTEND (x
, nb
);
214 else if (constant_formats
[cf
].issigned
)
215 x
= SIGNEXTEND (x
, constant_formats
[cf
].nbits
);
217 x
+= constant_formats
[cf
].offset
;
218 x
<<= constant_formats
[cf
].scale
;
223 enum machine_registers
225 REG_RL0
, REG_RL1
, REG_RL2
, REG_RL3
, REG_RL4
, REG_RL5
, REG_RL6
, REG_RL7
,
226 REG_RH0
, REG_RH1
, REG_RH2
, REG_RH3
, REG_RH4
, REG_RH5
, REG_RH6
, REG_RH7
,
227 REG_R0
, REG_R1
, REG_R2
, REG_R3
, REG_R4
, REG_R5
, REG_R6
, REG_R7
,
228 REG_R1_0
, REG_R3_2
, REG_R5_4
, REG_R7_6
, REG_P0
, REG_P1
, REG_P2
, REG_P3
,
229 REG_P4
, REG_P5
, REG_SP
, REG_FP
, REG_A0x
, REG_A1x
, REG_A0w
, REG_A1w
,
230 REG_A0
, REG_A1
, REG_I0
, REG_I1
, REG_I2
, REG_I3
, REG_M0
, REG_M1
,
231 REG_M2
, REG_M3
, REG_B0
, REG_B1
, REG_B2
, REG_B3
, REG_L0
, REG_L1
,
233 REG_AZ
, REG_AN
, REG_AC0
, REG_AC1
, REG_AV0
, REG_AV1
, REG_AV0S
, REG_AV1S
,
234 REG_AQ
, REG_V
, REG_VS
,
235 REG_sftreset
, REG_omode
, REG_excause
, REG_emucause
, REG_idle_req
, REG_hwerrcause
, REG_CC
, REG_LC0
,
236 REG_LC1
, REG_GP
, REG_ASTAT
, REG_RETS
, REG_LT0
, REG_LB0
, REG_LT1
, REG_LB1
,
237 REG_CYCLES
, REG_CYCLES2
, REG_USP
, REG_SEQSTAT
, REG_SYSCFG
, REG_RETI
, REG_RETX
, REG_RETN
,
238 REG_RETE
, REG_EMUDAT
, REG_BR0
, REG_BR1
, REG_BR2
, REG_BR3
, REG_BR4
, REG_BR5
, REG_BR6
,
239 REG_BR7
, REG_PL0
, REG_PL1
, REG_PL2
, REG_PL3
, REG_PL4
, REG_PL5
, REG_SLP
, REG_FLP
,
240 REG_PH0
, REG_PH1
, REG_PH2
, REG_PH3
, REG_PH4
, REG_PH5
, REG_SHP
, REG_FHP
,
241 REG_IL0
, REG_IL1
, REG_IL2
, REG_IL3
, REG_ML0
, REG_ML1
, REG_ML2
, REG_ML3
,
242 REG_BL0
, REG_BL1
, REG_BL2
, REG_BL3
, REG_LL0
, REG_LL1
, REG_LL2
, REG_LL3
,
243 REG_IH0
, REG_IH1
, REG_IH2
, REG_IH3
, REG_MH0
, REG_MH1
, REG_MH2
, REG_MH3
,
244 REG_BH0
, REG_BH1
, REG_BH2
, REG_BH3
, REG_LH0
, REG_LH1
, REG_LH2
, REG_LH3
,
245 REG_AC0_COPY
, REG_V_COPY
, REG_RND_MOD
,
251 rc_dregs_lo
, rc_dregs_hi
, rc_dregs
, rc_dregs_pair
, rc_pregs
, rc_spfp
, rc_dregs_hilo
, rc_accum_ext
,
252 rc_accum_word
, rc_accum
, rc_iregs
, rc_mregs
, rc_bregs
, rc_lregs
, rc_dpregs
, rc_gregs
,
253 rc_regs
, rc_statbits
, rc_ignore_bits
, rc_ccstat
, rc_counters
, rc_dregs2_sysregs1
, rc_open
, rc_sysregs2
,
254 rc_sysregs3
, rc_allregs
,
258 static const char *reg_names
[] =
260 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
261 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
262 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
263 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
264 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
265 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
266 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
268 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
270 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
271 "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
272 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
274 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
275 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
276 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
277 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
278 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
279 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
280 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
281 "AC0_COPY", "V_COPY", "RND_MOD",
286 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
289 static enum machine_registers decode_dregs_lo
[] =
291 REG_RL0
, REG_RL1
, REG_RL2
, REG_RL3
, REG_RL4
, REG_RL5
, REG_RL6
, REG_RL7
,
294 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
297 static enum machine_registers decode_dregs_hi
[] =
299 REG_RH0
, REG_RH1
, REG_RH2
, REG_RH3
, REG_RH4
, REG_RH5
, REG_RH6
, REG_RH7
,
302 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
305 static enum machine_registers decode_dregs
[] =
307 REG_R0
, REG_R1
, REG_R2
, REG_R3
, REG_R4
, REG_R5
, REG_R6
, REG_R7
,
310 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
313 static enum machine_registers decode_dregs_byte
[] =
315 REG_BR0
, REG_BR1
, REG_BR2
, REG_BR3
, REG_BR4
, REG_BR5
, REG_BR6
, REG_BR7
,
318 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
321 static enum machine_registers decode_pregs
[] =
323 REG_P0
, REG_P1
, REG_P2
, REG_P3
, REG_P4
, REG_P5
, REG_SP
, REG_FP
,
326 #define pregs(x) REGNAME (decode_pregs[(x) & 7])
327 #define spfp(x) REGNAME (decode_spfp[(x) & 1])
328 #define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
329 #define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
330 #define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
331 #define accum(x) REGNAME (decode_accum[(x) & 1])
334 static enum machine_registers decode_iregs
[] =
336 REG_I0
, REG_I1
, REG_I2
, REG_I3
,
339 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
342 static enum machine_registers decode_mregs
[] =
344 REG_M0
, REG_M1
, REG_M2
, REG_M3
,
347 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
348 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
349 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
352 static enum machine_registers decode_dpregs
[] =
354 REG_R0
, REG_R1
, REG_R2
, REG_R3
, REG_R4
, REG_R5
, REG_R6
, REG_R7
,
355 REG_P0
, REG_P1
, REG_P2
, REG_P3
, REG_P4
, REG_P5
, REG_SP
, REG_FP
,
358 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
361 static enum machine_registers decode_gregs
[] =
363 REG_R0
, REG_R1
, REG_R2
, REG_R3
, REG_R4
, REG_R5
, REG_R6
, REG_R7
,
364 REG_P0
, REG_P1
, REG_P2
, REG_P3
, REG_P4
, REG_P5
, REG_SP
, REG_FP
,
367 #define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
369 /* [dregs pregs (iregs mregs) (bregs lregs)]. */
370 static enum machine_registers decode_regs
[] =
372 REG_R0
, REG_R1
, REG_R2
, REG_R3
, REG_R4
, REG_R5
, REG_R6
, REG_R7
,
373 REG_P0
, REG_P1
, REG_P2
, REG_P3
, REG_P4
, REG_P5
, REG_SP
, REG_FP
,
374 REG_I0
, REG_I1
, REG_I2
, REG_I3
, REG_M0
, REG_M1
, REG_M2
, REG_M3
,
375 REG_B0
, REG_B1
, REG_B2
, REG_B3
, REG_L0
, REG_L1
, REG_L2
, REG_L3
,
378 #define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
380 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
381 static enum machine_registers decode_regs_lo
[] =
383 REG_RL0
, REG_RL1
, REG_RL2
, REG_RL3
, REG_RL4
, REG_RL5
, REG_RL6
, REG_RL7
,
384 REG_PL0
, REG_PL1
, REG_PL2
, REG_PL3
, REG_PL4
, REG_PL5
, REG_SLP
, REG_FLP
,
385 REG_IL0
, REG_IL1
, REG_IL2
, REG_IL3
, REG_ML0
, REG_ML1
, REG_ML2
, REG_ML3
,
386 REG_BL0
, REG_BL1
, REG_BL2
, REG_BL3
, REG_LL0
, REG_LL1
, REG_LL2
, REG_LL3
,
389 #define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
390 /* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
391 static enum machine_registers decode_regs_hi
[] =
393 REG_RH0
, REG_RH1
, REG_RH2
, REG_RH3
, REG_RH4
, REG_RH5
, REG_RH6
, REG_RH7
,
394 REG_PH0
, REG_PH1
, REG_PH2
, REG_PH3
, REG_PH4
, REG_PH5
, REG_SHP
, REG_FHP
,
395 REG_IH0
, REG_IH1
, REG_IH2
, REG_IH3
, REG_MH0
, REG_MH1
, REG_MH2
, REG_MH3
,
396 REG_BH0
, REG_BH1
, REG_BH2
, REG_BH3
, REG_LH0
, REG_LH1
, REG_LH2
, REG_LH3
,
399 #define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
401 static enum machine_registers decode_statbits
[] =
403 REG_AZ
, REG_AN
, REG_AC0_COPY
, REG_V_COPY
,
404 REG_LASTREG
, REG_LASTREG
, REG_AQ
, REG_LASTREG
,
405 REG_RND_MOD
, REG_LASTREG
, REG_LASTREG
, REG_LASTREG
,
406 REG_AC0
, REG_AC1
, REG_LASTREG
, REG_LASTREG
,
407 REG_AV0
, REG_AV0S
, REG_AV1
, REG_AV1S
,
408 REG_LASTREG
, REG_LASTREG
, REG_LASTREG
, REG_LASTREG
,
409 REG_V
, REG_VS
, REG_LASTREG
, REG_LASTREG
,
410 REG_LASTREG
, REG_LASTREG
, REG_LASTREG
, REG_LASTREG
,
413 #define statbits(x) REGNAME (decode_statbits[(x) & 31])
416 static enum machine_registers decode_counters
[] =
421 #define counters(x) REGNAME (decode_counters[(x) & 1])
422 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
424 /* [dregs pregs (iregs mregs) (bregs lregs)
425 dregs2_sysregs1 open sysregs2 sysregs3]. */
426 static enum machine_registers decode_allregs
[] =
428 REG_R0
, REG_R1
, REG_R2
, REG_R3
, REG_R4
, REG_R5
, REG_R6
, REG_R7
,
429 REG_P0
, REG_P1
, REG_P2
, REG_P3
, REG_P4
, REG_P5
, REG_SP
, REG_FP
,
430 REG_I0
, REG_I1
, REG_I2
, REG_I3
, REG_M0
, REG_M1
, REG_M2
, REG_M3
,
431 REG_B0
, REG_B1
, REG_B2
, REG_B3
, REG_L0
, REG_L1
, REG_L2
, REG_L3
,
432 REG_A0x
, REG_A0w
, REG_A1x
, REG_A1w
, REG_GP
, REG_LASTREG
, REG_ASTAT
, REG_RETS
,
433 REG_LASTREG
, REG_LASTREG
, REG_LASTREG
, REG_LASTREG
, REG_LASTREG
, REG_LASTREG
, REG_LASTREG
, REG_LASTREG
,
434 REG_LC0
, REG_LT0
, REG_LB0
, REG_LC1
, REG_LT1
, REG_LB1
, REG_CYCLES
, REG_CYCLES2
,
435 REG_USP
, REG_SEQSTAT
, REG_SYSCFG
, REG_RETI
, REG_RETX
, REG_RETN
, REG_RETE
, REG_EMUDAT
,
439 #define IS_DREG(g,r) ((g) == 0 && (r) < 8)
440 #define IS_PREG(g,r) ((g) == 1 && (r) < 8)
441 #define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
442 #define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
443 #define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
444 #define IS_SYSREG(g,r) \
445 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
446 #define IS_RESERVEDREG(g,r) \
447 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
449 #define allreg(r,g) (!IS_RESERVEDREG (g, r))
450 #define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
452 #define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
453 #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
454 #define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
455 #define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
456 #define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
457 #define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
458 #define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
459 #define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
460 #define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
461 #define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
462 #define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
463 #define imm16(x) fmtconst (c_imm16, x, 0, outf)
464 #define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
465 #define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
466 #define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
467 #define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
468 #define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
469 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
470 #define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
471 #define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
472 #define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
473 #define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
474 #define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
475 #define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
476 #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
477 #define imm3(x) fmtconst (c_imm3, x, 0, outf)
478 #define imm4(x) fmtconst (c_imm4, x, 0, outf)
479 #define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
480 #define imm5(x) fmtconst (c_imm5, x, 0, outf)
481 #define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
482 #define imm6(x) fmtconst (c_imm6, x, 0, outf)
483 #define imm7(x) fmtconst (c_imm7, x, 0, outf)
484 #define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
485 #define imm8(x) fmtconst (c_imm8, x, 0, outf)
486 #define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
487 #define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
488 #define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
489 #define imm32(x) fmtconst (c_imm32, x, 0, outf)
490 #define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
491 #define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
492 #define imm7_val(x) fmtconst_val (c_imm7, x, 0)
493 #define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
494 #define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
496 /* (arch.pm)arch_disassembler_functions. */
498 #define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
502 amod0 (int s0
, int x0
, disassemble_info
*outf
)
504 if (s0
== 1 && x0
== 0)
506 else if (s0
== 0 && x0
== 1)
507 OUTS (outf
, " (CO)");
508 else if (s0
== 1 && x0
== 1)
509 OUTS (outf
, " (SCO)");
513 amod1 (int s0
, int x0
, disassemble_info
*outf
)
515 if (s0
== 0 && x0
== 0)
516 OUTS (outf
, " (NS)");
517 else if (s0
== 1 && x0
== 0)
522 amod0amod2 (int s0
, int x0
, int aop0
, disassemble_info
*outf
)
524 if (s0
== 1 && x0
== 0 && aop0
== 0)
526 else if (s0
== 0 && x0
== 1 && aop0
== 0)
527 OUTS (outf
, " (CO)");
528 else if (s0
== 1 && x0
== 1 && aop0
== 0)
529 OUTS (outf
, " (SCO)");
530 else if (s0
== 0 && x0
== 0 && aop0
== 2)
531 OUTS (outf
, " (ASR)");
532 else if (s0
== 1 && x0
== 0 && aop0
== 2)
533 OUTS (outf
, " (S, ASR)");
534 else if (s0
== 0 && x0
== 1 && aop0
== 2)
535 OUTS (outf
, " (CO, ASR)");
536 else if (s0
== 1 && x0
== 1 && aop0
== 2)
537 OUTS (outf
, " (SCO, ASR)");
538 else if (s0
== 0 && x0
== 0 && aop0
== 3)
539 OUTS (outf
, " (ASL)");
540 else if (s0
== 1 && x0
== 0 && aop0
== 3)
541 OUTS (outf
, " (S, ASL)");
542 else if (s0
== 0 && x0
== 1 && aop0
== 3)
543 OUTS (outf
, " (CO, ASL)");
544 else if (s0
== 1 && x0
== 1 && aop0
== 3)
545 OUTS (outf
, " (SCO, ASL)");
549 searchmod (int r0
, disassemble_info
*outf
)
562 aligndir (int r0
, disassemble_info
*outf
)
569 decode_multfunc (int h0
, int h1
, int src0
, int src1
, disassemble_info
* outf
)
574 s0
= dregs_hi (src0
);
576 s0
= dregs_lo (src0
);
579 s1
= dregs_hi (src1
);
581 s1
= dregs_lo (src1
);
590 decode_macfunc (int which
, int op
, int h0
, int h1
, int src0
, int src1
, disassemble_info
* outf
)
593 const char *sop
= "<unknown op>";
608 case 0: sop
= " = "; break;
609 case 1: sop
= " += "; break;
610 case 2: sop
= " -= "; break;
616 decode_multfunc (h0
, h1
, src0
, src1
, outf
);
622 decode_optmode (int mod
, int MM
, disassemble_info
*outf
)
624 if (mod
== 0 && MM
== 0)
639 OUTS (outf
, "S2RND");
642 else if (mod
== M_W32
)
644 else if (mod
== M_FU
)
646 else if (mod
== M_TFU
)
648 else if (mod
== M_IS
)
650 else if (mod
== M_ISS2
)
652 else if (mod
== M_IH
)
654 else if (mod
== M_IU
)
664 bu32 dpregs
[16], iregs
[4], mregs
[4], bregs
[4], lregs
[4];
665 bu32 a0x
, a0w
, a1x
, a1w
;
666 bu32 lt
[2], lc
[2], lb
[2];
667 int ac0
, ac0_copy
, ac1
, an
, aq
;
668 int av0
, av0s
, av1
, av1s
, az
, cc
, v
, v_copy
, vs
;
678 int end_of_registers
;
681 unsigned char *memory
;
682 unsigned long bfd_mach
;
685 #define DREG(x) (saved_state.dpregs[x])
686 #define GREG(x,i) DPREG ((x) | (i << 3))
687 #define DPREG(x) (saved_state.dpregs[x])
688 #define DREG(x) (saved_state.dpregs[x])
689 #define PREG(x) (saved_state.dpregs[x + 8])
690 #define SPREG PREG (6)
691 #define FPREG PREG (7)
692 #define IREG(x) (saved_state.iregs[x])
693 #define MREG(x) (saved_state.mregs[x])
694 #define BREG(x) (saved_state.bregs[x])
695 #define LREG(x) (saved_state.lregs[x])
696 #define A0XREG (saved_state.a0x)
697 #define A0WREG (saved_state.a0w)
698 #define A1XREG (saved_state.a1x)
699 #define A1WREG (saved_state.a1w)
700 #define CCREG (saved_state.cc)
701 #define LC0REG (saved_state.lc[0])
702 #define LT0REG (saved_state.lt[0])
703 #define LB0REG (saved_state.lb[0])
704 #define LC1REG (saved_state.lc[1])
705 #define LT1REG (saved_state.lt[1])
706 #define LB1REG (saved_state.lb[1])
707 #define RETSREG (saved_state.rets)
708 #define PCREG (saved_state.pc)
711 get_allreg (int grp
, int reg
)
713 int fullreg
= (grp
<< 3) | reg
;
714 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
715 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
716 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
717 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
718 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
720 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
722 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
724 switch (fullreg
>> 2)
726 case 0: case 1: return &DREG (reg
); break;
727 case 2: case 3: return &PREG (reg
); break;
728 case 4: return &IREG (reg
& 3); break;
729 case 5: return &MREG (reg
& 3); break;
730 case 6: return &BREG (reg
& 3); break;
731 case 7: return &LREG (reg
& 3); break;
735 case 32: return &saved_state
.a0x
;
736 case 33: return &saved_state
.a0w
;
737 case 34: return &saved_state
.a1x
;
738 case 35: return &saved_state
.a1w
;
739 case 39: return &saved_state
.rets
;
740 case 48: return &LC0REG
;
741 case 49: return <0REG
;
742 case 50: return &LB0REG
;
743 case 51: return &LC1REG
;
744 case 52: return <1REG
;
745 case 53: return &LB1REG
;
752 decode_ProgCtrl_0 (TIword iw0
, disassemble_info
*outf
)
755 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
756 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
757 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
758 int poprnd
= ((iw0
>> ProgCtrl_poprnd_bits
) & ProgCtrl_poprnd_mask
);
759 int prgfunc
= ((iw0
>> ProgCtrl_prgfunc_bits
) & ProgCtrl_prgfunc_mask
);
761 if (prgfunc
== 0 && poprnd
== 0)
765 else if (prgfunc
== 1 && poprnd
== 0)
767 else if (prgfunc
== 1 && poprnd
== 1)
769 else if (prgfunc
== 1 && poprnd
== 2)
771 else if (prgfunc
== 1 && poprnd
== 3)
773 else if (prgfunc
== 1 && poprnd
== 4)
775 else if (prgfunc
== 2 && poprnd
== 0)
777 else if (prgfunc
== 2 && poprnd
== 3)
778 OUTS (outf
, "CSYNC");
779 else if (prgfunc
== 2 && poprnd
== 4)
780 OUTS (outf
, "SSYNC");
781 else if (prgfunc
== 2 && poprnd
== 5)
782 OUTS (outf
, "EMUEXCPT");
783 else if (prgfunc
== 3 && IS_DREG (0, poprnd
))
786 OUTS (outf
, dregs (poprnd
));
788 else if (prgfunc
== 4 && IS_DREG (0, poprnd
))
791 OUTS (outf
, dregs (poprnd
));
793 else if (prgfunc
== 5 && IS_PREG (1, poprnd
))
795 OUTS (outf
, "JUMP (");
796 OUTS (outf
, pregs (poprnd
));
799 else if (prgfunc
== 6 && IS_PREG (1, poprnd
))
801 OUTS (outf
, "CALL (");
802 OUTS (outf
, pregs (poprnd
));
805 else if (prgfunc
== 7 && IS_PREG (1, poprnd
))
807 OUTS (outf
, "CALL (PC + ");
808 OUTS (outf
, pregs (poprnd
));
811 else if (prgfunc
== 8 && IS_PREG (1, poprnd
))
813 OUTS (outf
, "JUMP (PC + ");
814 OUTS (outf
, pregs (poprnd
));
817 else if (prgfunc
== 9)
819 OUTS (outf
, "RAISE ");
820 OUTS (outf
, uimm4 (poprnd
));
822 else if (prgfunc
== 10)
824 OUTS (outf
, "EXCPT ");
825 OUTS (outf
, uimm4 (poprnd
));
827 else if (prgfunc
== 11 && IS_PREG (1, poprnd
) && poprnd
<= 5)
829 OUTS (outf
, "TESTSET (");
830 OUTS (outf
, pregs (poprnd
));
839 decode_CaCTRL_0 (TIword iw0
, disassemble_info
*outf
)
842 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
843 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
844 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
845 int a
= ((iw0
>> CaCTRL_a_bits
) & CaCTRL_a_mask
);
846 int op
= ((iw0
>> CaCTRL_op_bits
) & CaCTRL_op_mask
);
847 int reg
= ((iw0
>> CaCTRL_reg_bits
) & CaCTRL_reg_mask
);
852 if (a
== 0 && op
== 0)
854 OUTS (outf
, "PREFETCH[");
855 OUTS (outf
, pregs (reg
));
858 else if (a
== 0 && op
== 1)
860 OUTS (outf
, "FLUSHINV[");
861 OUTS (outf
, pregs (reg
));
864 else if (a
== 0 && op
== 2)
866 OUTS (outf
, "FLUSH[");
867 OUTS (outf
, pregs (reg
));
870 else if (a
== 0 && op
== 3)
872 OUTS (outf
, "IFLUSH[");
873 OUTS (outf
, pregs (reg
));
876 else if (a
== 1 && op
== 0)
878 OUTS (outf
, "PREFETCH[");
879 OUTS (outf
, pregs (reg
));
882 else if (a
== 1 && op
== 1)
884 OUTS (outf
, "FLUSHINV[");
885 OUTS (outf
, pregs (reg
));
888 else if (a
== 1 && op
== 2)
890 OUTS (outf
, "FLUSH[");
891 OUTS (outf
, pregs (reg
));
894 else if (a
== 1 && op
== 3)
896 OUTS (outf
, "IFLUSH[");
897 OUTS (outf
, pregs (reg
));
906 decode_PushPopReg_0 (TIword iw0
, disassemble_info
*outf
)
909 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
910 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
911 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
912 int W
= ((iw0
>> PushPopReg_W_bits
) & PushPopReg_W_mask
);
913 int grp
= ((iw0
>> PushPopReg_grp_bits
) & PushPopReg_grp_mask
);
914 int reg
= ((iw0
>> PushPopReg_reg_bits
) & PushPopReg_reg_mask
);
919 if (W
== 0 && mostreg (reg
, grp
))
921 OUTS (outf
, allregs (reg
, grp
));
922 OUTS (outf
, " = [SP++]");
924 else if (W
== 1 && allreg (reg
, grp
) && !(grp
== 1 && reg
== 6))
926 OUTS (outf
, "[--SP] = ");
927 OUTS (outf
, allregs (reg
, grp
));
935 decode_PushPopMultiple_0 (TIword iw0
, disassemble_info
*outf
)
938 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
939 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
940 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
941 int p
= ((iw0
>> PushPopMultiple_p_bits
) & PushPopMultiple_p_mask
);
942 int d
= ((iw0
>> PushPopMultiple_d_bits
) & PushPopMultiple_d_mask
);
943 int W
= ((iw0
>> PushPopMultiple_W_bits
) & PushPopMultiple_W_mask
);
944 int dr
= ((iw0
>> PushPopMultiple_dr_bits
) & PushPopMultiple_dr_mask
);
945 int pr
= ((iw0
>> PushPopMultiple_pr_bits
) & PushPopMultiple_pr_mask
);
953 if (W
== 1 && d
== 1 && p
== 1)
955 OUTS (outf
, "[--SP] = (R7:");
956 OUTS (outf
, imm5d (dr
));
957 OUTS (outf
, ", P5:");
958 OUTS (outf
, imm5d (pr
));
961 else if (W
== 1 && d
== 1 && p
== 0 && pr
== 0)
963 OUTS (outf
, "[--SP] = (R7:");
964 OUTS (outf
, imm5d (dr
));
967 else if (W
== 1 && d
== 0 && p
== 1 && dr
== 0)
969 OUTS (outf
, "[--SP] = (P5:");
970 OUTS (outf
, imm5d (pr
));
973 else if (W
== 0 && d
== 1 && p
== 1)
976 OUTS (outf
, imm5d (dr
));
977 OUTS (outf
, ", P5:");
978 OUTS (outf
, imm5d (pr
));
979 OUTS (outf
, ") = [SP++]");
981 else if (W
== 0 && d
== 1 && p
== 0 && pr
== 0)
984 OUTS (outf
, imm5d (dr
));
985 OUTS (outf
, ") = [SP++]");
987 else if (W
== 0 && d
== 0 && p
== 1 && dr
== 0)
990 OUTS (outf
, imm5d (pr
));
991 OUTS (outf
, ") = [SP++]");
999 decode_ccMV_0 (TIword iw0
, disassemble_info
*outf
)
1002 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1003 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
1004 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1005 int s
= ((iw0
>> CCmv_s_bits
) & CCmv_s_mask
);
1006 int d
= ((iw0
>> CCmv_d_bits
) & CCmv_d_mask
);
1007 int T
= ((iw0
>> CCmv_T_bits
) & CCmv_T_mask
);
1008 int src
= ((iw0
>> CCmv_src_bits
) & CCmv_src_mask
);
1009 int dst
= ((iw0
>> CCmv_dst_bits
) & CCmv_dst_mask
);
1016 OUTS (outf
, "IF CC ");
1017 OUTS (outf
, gregs (dst
, d
));
1019 OUTS (outf
, gregs (src
, s
));
1023 OUTS (outf
, "IF !CC ");
1024 OUTS (outf
, gregs (dst
, d
));
1026 OUTS (outf
, gregs (src
, s
));
1034 decode_CCflag_0 (TIword iw0
, disassemble_info
*outf
)
1037 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1038 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1039 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1040 int x
= ((iw0
>> CCflag_x_bits
) & CCflag_x_mask
);
1041 int y
= ((iw0
>> CCflag_y_bits
) & CCflag_y_mask
);
1042 int I
= ((iw0
>> CCflag_I_bits
) & CCflag_I_mask
);
1043 int G
= ((iw0
>> CCflag_G_bits
) & CCflag_G_mask
);
1044 int opc
= ((iw0
>> CCflag_opc_bits
) & CCflag_opc_mask
);
1049 if (opc
== 0 && I
== 0 && G
== 0)
1051 OUTS (outf
, "CC = ");
1052 OUTS (outf
, dregs (x
));
1053 OUTS (outf
, " == ");
1054 OUTS (outf
, dregs (y
));
1056 else if (opc
== 1 && I
== 0 && G
== 0)
1058 OUTS (outf
, "CC = ");
1059 OUTS (outf
, dregs (x
));
1061 OUTS (outf
, dregs (y
));
1063 else if (opc
== 2 && I
== 0 && G
== 0)
1065 OUTS (outf
, "CC = ");
1066 OUTS (outf
, dregs (x
));
1067 OUTS (outf
, " <= ");
1068 OUTS (outf
, dregs (y
));
1070 else if (opc
== 3 && I
== 0 && G
== 0)
1072 OUTS (outf
, "CC = ");
1073 OUTS (outf
, dregs (x
));
1075 OUTS (outf
, dregs (y
));
1076 OUTS (outf
, " (IU)");
1078 else if (opc
== 4 && I
== 0 && G
== 0)
1080 OUTS (outf
, "CC = ");
1081 OUTS (outf
, dregs (x
));
1082 OUTS (outf
, " <= ");
1083 OUTS (outf
, dregs (y
));
1084 OUTS (outf
, " (IU)");
1086 else if (opc
== 0 && I
== 1 && G
== 0)
1088 OUTS (outf
, "CC = ");
1089 OUTS (outf
, dregs (x
));
1090 OUTS (outf
, " == ");
1091 OUTS (outf
, imm3 (y
));
1093 else if (opc
== 1 && I
== 1 && G
== 0)
1095 OUTS (outf
, "CC = ");
1096 OUTS (outf
, dregs (x
));
1098 OUTS (outf
, imm3 (y
));
1100 else if (opc
== 2 && I
== 1 && G
== 0)
1102 OUTS (outf
, "CC = ");
1103 OUTS (outf
, dregs (x
));
1104 OUTS (outf
, " <= ");
1105 OUTS (outf
, imm3 (y
));
1107 else if (opc
== 3 && I
== 1 && G
== 0)
1109 OUTS (outf
, "CC = ");
1110 OUTS (outf
, dregs (x
));
1112 OUTS (outf
, uimm3 (y
));
1113 OUTS (outf
, " (IU)");
1115 else if (opc
== 4 && I
== 1 && G
== 0)
1117 OUTS (outf
, "CC = ");
1118 OUTS (outf
, dregs (x
));
1119 OUTS (outf
, " <= ");
1120 OUTS (outf
, uimm3 (y
));
1121 OUTS (outf
, " (IU)");
1123 else if (opc
== 0 && I
== 0 && G
== 1)
1125 OUTS (outf
, "CC = ");
1126 OUTS (outf
, pregs (x
));
1127 OUTS (outf
, " == ");
1128 OUTS (outf
, pregs (y
));
1130 else if (opc
== 1 && I
== 0 && G
== 1)
1132 OUTS (outf
, "CC = ");
1133 OUTS (outf
, pregs (x
));
1135 OUTS (outf
, pregs (y
));
1137 else if (opc
== 2 && I
== 0 && G
== 1)
1139 OUTS (outf
, "CC = ");
1140 OUTS (outf
, pregs (x
));
1141 OUTS (outf
, " <= ");
1142 OUTS (outf
, pregs (y
));
1144 else if (opc
== 3 && I
== 0 && G
== 1)
1146 OUTS (outf
, "CC = ");
1147 OUTS (outf
, pregs (x
));
1149 OUTS (outf
, pregs (y
));
1150 OUTS (outf
, " (IU)");
1152 else if (opc
== 4 && I
== 0 && G
== 1)
1154 OUTS (outf
, "CC = ");
1155 OUTS (outf
, pregs (x
));
1156 OUTS (outf
, " <= ");
1157 OUTS (outf
, pregs (y
));
1158 OUTS (outf
, " (IU)");
1160 else if (opc
== 0 && I
== 1 && G
== 1)
1162 OUTS (outf
, "CC = ");
1163 OUTS (outf
, pregs (x
));
1164 OUTS (outf
, " == ");
1165 OUTS (outf
, imm3 (y
));
1167 else if (opc
== 1 && I
== 1 && G
== 1)
1169 OUTS (outf
, "CC = ");
1170 OUTS (outf
, pregs (x
));
1172 OUTS (outf
, imm3 (y
));
1174 else if (opc
== 2 && I
== 1 && G
== 1)
1176 OUTS (outf
, "CC = ");
1177 OUTS (outf
, pregs (x
));
1178 OUTS (outf
, " <= ");
1179 OUTS (outf
, imm3 (y
));
1181 else if (opc
== 3 && I
== 1 && G
== 1)
1183 OUTS (outf
, "CC = ");
1184 OUTS (outf
, pregs (x
));
1186 OUTS (outf
, uimm3 (y
));
1187 OUTS (outf
, " (IU)");
1189 else if (opc
== 4 && I
== 1 && G
== 1)
1191 OUTS (outf
, "CC = ");
1192 OUTS (outf
, pregs (x
));
1193 OUTS (outf
, " <= ");
1194 OUTS (outf
, uimm3 (y
));
1195 OUTS (outf
, " (IU)");
1197 else if (opc
== 5 && I
== 0 && G
== 0 && x
== 0 && y
== 0)
1198 OUTS (outf
, "CC = A0 == A1");
1200 else if (opc
== 6 && I
== 0 && G
== 0 && x
== 0 && y
== 0)
1201 OUTS (outf
, "CC = A0 < A1");
1203 else if (opc
== 7 && I
== 0 && G
== 0 && x
== 0 && y
== 0)
1204 OUTS (outf
, "CC = A0 <= A1");
1212 decode_CC2dreg_0 (TIword iw0
, disassemble_info
*outf
)
1215 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1216 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1217 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1218 int op
= ((iw0
>> CC2dreg_op_bits
) & CC2dreg_op_mask
);
1219 int reg
= ((iw0
>> CC2dreg_reg_bits
) & CC2dreg_reg_mask
);
1226 OUTS (outf
, dregs (reg
));
1227 OUTS (outf
, " = CC");
1231 OUTS (outf
, "CC = ");
1232 OUTS (outf
, dregs (reg
));
1234 else if (op
== 3 && reg
== 0)
1235 OUTS (outf
, "CC = !CC");
1243 decode_CC2stat_0 (TIword iw0
, disassemble_info
*outf
)
1246 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1247 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1248 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1249 int D
= ((iw0
>> CC2stat_D_bits
) & CC2stat_D_mask
);
1250 int op
= ((iw0
>> CC2stat_op_bits
) & CC2stat_op_mask
);
1251 int cbit
= ((iw0
>> CC2stat_cbit_bits
) & CC2stat_cbit_mask
);
1253 const char *bitname
= statbits (cbit
);
1258 if (decode_statbits
[cbit
] == REG_LASTREG
)
1260 /* All ASTAT bits except CC may be operated on in hardware, but may
1261 not have a dedicated insn, so still decode "valid" insns. */
1262 static char bitnames
[64];
1264 sprintf (bitnames
, "ASTAT[%i /* unused bit */]", cbit
);
1271 if (op
== 0 && D
== 0)
1273 OUTS (outf
, "CC = ");
1274 OUTS (outf
, bitname
);
1276 else if (op
== 1 && D
== 0)
1278 OUTS (outf
, "CC |= ");
1279 OUTS (outf
, bitname
);
1281 else if (op
== 2 && D
== 0)
1283 OUTS (outf
, "CC &= ");
1284 OUTS (outf
, bitname
);
1286 else if (op
== 3 && D
== 0)
1288 OUTS (outf
, "CC ^= ");
1289 OUTS (outf
, bitname
);
1291 else if (op
== 0 && D
== 1)
1293 OUTS (outf
, bitname
);
1294 OUTS (outf
, " = CC");
1296 else if (op
== 1 && D
== 1)
1298 OUTS (outf
, bitname
);
1299 OUTS (outf
, " |= CC");
1301 else if (op
== 2 && D
== 1)
1303 OUTS (outf
, bitname
);
1304 OUTS (outf
, " &= CC");
1306 else if (op
== 3 && D
== 1)
1308 OUTS (outf
, bitname
);
1309 OUTS (outf
, " ^= CC");
1318 decode_BRCC_0 (TIword iw0
, bfd_vma pc
, disassemble_info
*outf
)
1321 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1322 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1323 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1324 int B
= ((iw0
>> BRCC_B_bits
) & BRCC_B_mask
);
1325 int T
= ((iw0
>> BRCC_T_bits
) & BRCC_T_mask
);
1326 int offset
= ((iw0
>> BRCC_offset_bits
) & BRCC_offset_mask
);
1331 if (T
== 1 && B
== 1)
1333 OUTS (outf
, "IF CC JUMP 0x");
1334 OUTS (outf
, pcrel10 (offset
));
1335 OUTS (outf
, " (BP)");
1337 else if (T
== 0 && B
== 1)
1339 OUTS (outf
, "IF !CC JUMP 0x");
1340 OUTS (outf
, pcrel10 (offset
));
1341 OUTS (outf
, " (BP)");
1345 OUTS (outf
, "IF CC JUMP 0x");
1346 OUTS (outf
, pcrel10 (offset
));
1350 OUTS (outf
, "IF !CC JUMP 0x");
1351 OUTS (outf
, pcrel10 (offset
));
1360 decode_UJUMP_0 (TIword iw0
, bfd_vma pc
, disassemble_info
*outf
)
1363 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1364 | 0 | 0 | 1 | 0 |.offset........................................|
1365 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1366 int offset
= ((iw0
>> UJump_offset_bits
) & UJump_offset_mask
);
1371 OUTS (outf
, "JUMP.S 0x");
1372 OUTS (outf
, pcrel12 (offset
));
1377 decode_REGMV_0 (TIword iw0
, disassemble_info
*outf
)
1380 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1381 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1382 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1383 int gs
= ((iw0
>> RegMv_gs_bits
) & RegMv_gs_mask
);
1384 int gd
= ((iw0
>> RegMv_gd_bits
) & RegMv_gd_mask
);
1385 int src
= ((iw0
>> RegMv_src_bits
) & RegMv_src_mask
);
1386 int dst
= ((iw0
>> RegMv_dst_bits
) & RegMv_dst_mask
);
1388 if (!((IS_GENREG (gd
, dst
) && IS_GENREG (gs
, src
))
1389 || (IS_GENREG (gd
, dst
) && IS_DAGREG (gs
, src
))
1390 || (IS_DAGREG (gd
, dst
) && IS_GENREG (gs
, src
))
1391 || (IS_DAGREG (gd
, dst
) && IS_DAGREG (gs
, src
))
1392 || (IS_GENREG (gd
, dst
) && gs
== 7 && src
== 0)
1393 || (gd
== 7 && dst
== 0 && IS_GENREG (gs
, src
))
1394 || (IS_DREG (gd
, dst
) && IS_SYSREG (gs
, src
))
1395 || (IS_PREG (gd
, dst
) && IS_SYSREG (gs
, src
))
1396 || (IS_SYSREG (gd
, dst
) && IS_DREG (gs
, src
))
1397 || (IS_SYSREG (gd
, dst
) && IS_PREG (gs
, src
))
1398 || (IS_SYSREG (gd
, dst
) && gs
== 7 && src
== 0)))
1401 OUTS (outf
, allregs (dst
, gd
));
1403 OUTS (outf
, allregs (src
, gs
));
1408 decode_ALU2op_0 (TIword iw0
, disassemble_info
*outf
)
1411 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1412 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1413 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1414 int src
= ((iw0
>> ALU2op_src_bits
) & ALU2op_src_mask
);
1415 int opc
= ((iw0
>> ALU2op_opc_bits
) & ALU2op_opc_mask
);
1416 int dst
= ((iw0
>> ALU2op_dst_bits
) & ALU2op_dst_mask
);
1420 OUTS (outf
, dregs (dst
));
1421 OUTS (outf
, " >>>= ");
1422 OUTS (outf
, dregs (src
));
1426 OUTS (outf
, dregs (dst
));
1427 OUTS (outf
, " >>= ");
1428 OUTS (outf
, dregs (src
));
1432 OUTS (outf
, dregs (dst
));
1433 OUTS (outf
, " <<= ");
1434 OUTS (outf
, dregs (src
));
1438 OUTS (outf
, dregs (dst
));
1439 OUTS (outf
, " *= ");
1440 OUTS (outf
, dregs (src
));
1444 OUTS (outf
, dregs (dst
));
1445 OUTS (outf
, " = (");
1446 OUTS (outf
, dregs (dst
));
1448 OUTS (outf
, dregs (src
));
1449 OUTS (outf
, ") << 0x1");
1453 OUTS (outf
, dregs (dst
));
1454 OUTS (outf
, " = (");
1455 OUTS (outf
, dregs (dst
));
1457 OUTS (outf
, dregs (src
));
1458 OUTS (outf
, ") << 0x2");
1462 OUTS (outf
, "DIVQ (");
1463 OUTS (outf
, dregs (dst
));
1465 OUTS (outf
, dregs (src
));
1470 OUTS (outf
, "DIVS (");
1471 OUTS (outf
, dregs (dst
));
1473 OUTS (outf
, dregs (src
));
1478 OUTS (outf
, dregs (dst
));
1480 OUTS (outf
, dregs_lo (src
));
1481 OUTS (outf
, " (X)");
1485 OUTS (outf
, dregs (dst
));
1487 OUTS (outf
, dregs_lo (src
));
1488 OUTS (outf
, " (Z)");
1492 OUTS (outf
, dregs (dst
));
1494 OUTS (outf
, dregs_byte (src
));
1495 OUTS (outf
, " (X)");
1499 OUTS (outf
, dregs (dst
));
1501 OUTS (outf
, dregs_byte (src
));
1502 OUTS (outf
, " (Z)");
1506 OUTS (outf
, dregs (dst
));
1507 OUTS (outf
, " = -");
1508 OUTS (outf
, dregs (src
));
1512 OUTS (outf
, dregs (dst
));
1513 OUTS (outf
, " =~ ");
1514 OUTS (outf
, dregs (src
));
1523 decode_PTR2op_0 (TIword iw0
, disassemble_info
*outf
)
1526 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1527 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1528 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1529 int src
= ((iw0
>> PTR2op_src_bits
) & PTR2op_dst_mask
);
1530 int opc
= ((iw0
>> PTR2op_opc_bits
) & PTR2op_opc_mask
);
1531 int dst
= ((iw0
>> PTR2op_dst_bits
) & PTR2op_dst_mask
);
1535 OUTS (outf
, pregs (dst
));
1536 OUTS (outf
, " -= ");
1537 OUTS (outf
, pregs (src
));
1541 OUTS (outf
, pregs (dst
));
1543 OUTS (outf
, pregs (src
));
1544 OUTS (outf
, " << 0x2");
1548 OUTS (outf
, pregs (dst
));
1550 OUTS (outf
, pregs (src
));
1551 OUTS (outf
, " >> 0x2");
1555 OUTS (outf
, pregs (dst
));
1557 OUTS (outf
, pregs (src
));
1558 OUTS (outf
, " >> 0x1");
1562 OUTS (outf
, pregs (dst
));
1563 OUTS (outf
, " += ");
1564 OUTS (outf
, pregs (src
));
1565 OUTS (outf
, " (BREV)");
1569 OUTS (outf
, pregs (dst
));
1570 OUTS (outf
, " = (");
1571 OUTS (outf
, pregs (dst
));
1573 OUTS (outf
, pregs (src
));
1574 OUTS (outf
, ") << 0x1");
1578 OUTS (outf
, pregs (dst
));
1579 OUTS (outf
, " = (");
1580 OUTS (outf
, pregs (dst
));
1582 OUTS (outf
, pregs (src
));
1583 OUTS (outf
, ") << 0x2");
1592 decode_LOGI2op_0 (TIword iw0
, disassemble_info
*outf
)
1595 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1596 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1597 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1598 int src
= ((iw0
>> LOGI2op_src_bits
) & LOGI2op_src_mask
);
1599 int opc
= ((iw0
>> LOGI2op_opc_bits
) & LOGI2op_opc_mask
);
1600 int dst
= ((iw0
>> LOGI2op_dst_bits
) & LOGI2op_dst_mask
);
1607 OUTS (outf
, "CC = !BITTST (");
1608 OUTS (outf
, dregs (dst
));
1610 OUTS (outf
, uimm5 (src
));
1611 OUTS (outf
, ");\t\t/* bit");
1612 OUTS (outf
, imm7d (src
));
1618 OUTS (outf
, "CC = BITTST (");
1619 OUTS (outf
, dregs (dst
));
1621 OUTS (outf
, uimm5 (src
));
1622 OUTS (outf
, ");\t\t/* bit");
1623 OUTS (outf
, imm7d (src
));
1629 OUTS (outf
, "BITSET (");
1630 OUTS (outf
, dregs (dst
));
1632 OUTS (outf
, uimm5 (src
));
1633 OUTS (outf
, ");\t\t/* bit");
1634 OUTS (outf
, imm7d (src
));
1640 OUTS (outf
, "BITTGL (");
1641 OUTS (outf
, dregs (dst
));
1643 OUTS (outf
, uimm5 (src
));
1644 OUTS (outf
, ");\t\t/* bit");
1645 OUTS (outf
, imm7d (src
));
1651 OUTS (outf
, "BITCLR (");
1652 OUTS (outf
, dregs (dst
));
1654 OUTS (outf
, uimm5 (src
));
1655 OUTS (outf
, ");\t\t/* bit");
1656 OUTS (outf
, imm7d (src
));
1662 OUTS (outf
, dregs (dst
));
1663 OUTS (outf
, " >>>= ");
1664 OUTS (outf
, uimm5 (src
));
1668 OUTS (outf
, dregs (dst
));
1669 OUTS (outf
, " >>= ");
1670 OUTS (outf
, uimm5 (src
));
1674 OUTS (outf
, dregs (dst
));
1675 OUTS (outf
, " <<= ");
1676 OUTS (outf
, uimm5 (src
));
1685 decode_COMP3op_0 (TIword iw0
, disassemble_info
*outf
)
1688 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1689 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1690 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1691 int opc
= ((iw0
>> COMP3op_opc_bits
) & COMP3op_opc_mask
);
1692 int dst
= ((iw0
>> COMP3op_dst_bits
) & COMP3op_dst_mask
);
1693 int src0
= ((iw0
>> COMP3op_src0_bits
) & COMP3op_src0_mask
);
1694 int src1
= ((iw0
>> COMP3op_src1_bits
) & COMP3op_src1_mask
);
1696 if (opc
== 5 && src1
== src0
)
1698 OUTS (outf
, pregs (dst
));
1700 OUTS (outf
, pregs (src0
));
1701 OUTS (outf
, " << 0x1");
1705 OUTS (outf
, dregs (dst
));
1707 OUTS (outf
, dregs (src0
));
1709 OUTS (outf
, dregs (src1
));
1713 OUTS (outf
, dregs (dst
));
1715 OUTS (outf
, dregs (src0
));
1717 OUTS (outf
, dregs (src1
));
1721 OUTS (outf
, dregs (dst
));
1723 OUTS (outf
, dregs (src0
));
1725 OUTS (outf
, dregs (src1
));
1729 OUTS (outf
, dregs (dst
));
1731 OUTS (outf
, dregs (src0
));
1733 OUTS (outf
, dregs (src1
));
1737 OUTS (outf
, pregs (dst
));
1739 OUTS (outf
, pregs (src0
));
1741 OUTS (outf
, pregs (src1
));
1745 OUTS (outf
, pregs (dst
));
1747 OUTS (outf
, pregs (src0
));
1748 OUTS (outf
, " + (");
1749 OUTS (outf
, pregs (src1
));
1750 OUTS (outf
, " << 0x1)");
1754 OUTS (outf
, pregs (dst
));
1756 OUTS (outf
, pregs (src0
));
1757 OUTS (outf
, " + (");
1758 OUTS (outf
, pregs (src1
));
1759 OUTS (outf
, " << 0x2)");
1763 OUTS (outf
, dregs (dst
));
1765 OUTS (outf
, dregs (src0
));
1767 OUTS (outf
, dregs (src1
));
1776 decode_COMPI2opD_0 (TIword iw0
, disassemble_info
*outf
)
1779 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1780 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1781 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1782 int op
= ((iw0
>> COMPI2opD_op_bits
) & COMPI2opD_op_mask
);
1783 int dst
= ((iw0
>> COMPI2opD_dst_bits
) & COMPI2opD_dst_mask
);
1784 int src
= ((iw0
>> COMPI2opD_src_bits
) & COMPI2opD_src_mask
);
1786 bu32
*pval
= get_allreg (0, dst
);
1791 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1792 to combine them, so it prints out the right values.
1793 Here we keep track of the registers. */
1796 *pval
= imm7_val (src
);
1798 *pval
|= 0xFFFFFF80;
1805 OUTS (outf
, dregs (dst
));
1807 OUTS (outf
, imm7 (src
));
1808 OUTS (outf
, " (X);\t\t/*\t\t");
1809 OUTS (outf
, dregs (dst
));
1811 OUTS (outf
, uimm32 (*pval
));
1813 OUTS (outf
, imm32 (*pval
));
1814 OUTS (outf
, ") */");
1819 OUTS (outf
, dregs (dst
));
1820 OUTS (outf
, " += ");
1821 OUTS (outf
, imm7 (src
));
1822 OUTS (outf
, ";\t\t/* (");
1823 OUTS (outf
, imm7d (src
));
1824 OUTS (outf
, ") */");
1834 decode_COMPI2opP_0 (TIword iw0
, disassemble_info
*outf
)
1837 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1838 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1839 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1840 int op
= ((iw0
>> COMPI2opP_op_bits
) & COMPI2opP_op_mask
);
1841 int src
= ((iw0
>> COMPI2opP_src_bits
) & COMPI2opP_src_mask
);
1842 int dst
= ((iw0
>> COMPI2opP_dst_bits
) & COMPI2opP_dst_mask
);
1844 bu32
*pval
= get_allreg (1, dst
);
1851 *pval
= imm7_val (src
);
1853 *pval
|= 0xFFFFFF80;
1860 OUTS (outf
, pregs (dst
));
1862 OUTS (outf
, imm7 (src
));
1863 OUTS (outf
, " (X);\t\t/*\t\t");
1864 OUTS (outf
, pregs (dst
));
1866 OUTS (outf
, uimm32 (*pval
));
1868 OUTS (outf
, imm32 (*pval
));
1869 OUTS (outf
, ") */");
1874 OUTS (outf
, pregs (dst
));
1875 OUTS (outf
, " += ");
1876 OUTS (outf
, imm7 (src
));
1877 OUTS (outf
, ";\t\t/* (");
1878 OUTS (outf
, imm7d (src
));
1879 OUTS (outf
, ") */");
1889 decode_LDSTpmod_0 (TIword iw0
, disassemble_info
*outf
)
1892 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1893 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1894 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1895 int W
= ((iw0
>> LDSTpmod_W_bits
) & LDSTpmod_W_mask
);
1896 int aop
= ((iw0
>> LDSTpmod_aop_bits
) & LDSTpmod_aop_mask
);
1897 int idx
= ((iw0
>> LDSTpmod_idx_bits
) & LDSTpmod_idx_mask
);
1898 int ptr
= ((iw0
>> LDSTpmod_ptr_bits
) & LDSTpmod_ptr_mask
);
1899 int reg
= ((iw0
>> LDSTpmod_reg_bits
) & LDSTpmod_reg_mask
);
1901 if (aop
== 1 && W
== 0 && idx
== ptr
)
1903 OUTS (outf
, dregs_lo (reg
));
1904 OUTS (outf
, " = W[");
1905 OUTS (outf
, pregs (ptr
));
1908 else if (aop
== 2 && W
== 0 && idx
== ptr
)
1910 OUTS (outf
, dregs_hi (reg
));
1911 OUTS (outf
, " = W[");
1912 OUTS (outf
, pregs (ptr
));
1915 else if (aop
== 1 && W
== 1 && idx
== ptr
)
1918 OUTS (outf
, pregs (ptr
));
1919 OUTS (outf
, "] = ");
1920 OUTS (outf
, dregs_lo (reg
));
1922 else if (aop
== 2 && W
== 1 && idx
== ptr
)
1925 OUTS (outf
, pregs (ptr
));
1926 OUTS (outf
, "] = ");
1927 OUTS (outf
, dregs_hi (reg
));
1929 else if (aop
== 0 && W
== 0)
1931 OUTS (outf
, dregs (reg
));
1932 OUTS (outf
, " = [");
1933 OUTS (outf
, pregs (ptr
));
1934 OUTS (outf
, " ++ ");
1935 OUTS (outf
, pregs (idx
));
1938 else if (aop
== 1 && W
== 0)
1940 OUTS (outf
, dregs_lo (reg
));
1941 OUTS (outf
, " = W[");
1942 OUTS (outf
, pregs (ptr
));
1943 OUTS (outf
, " ++ ");
1944 OUTS (outf
, pregs (idx
));
1947 else if (aop
== 2 && W
== 0)
1949 OUTS (outf
, dregs_hi (reg
));
1950 OUTS (outf
, " = W[");
1951 OUTS (outf
, pregs (ptr
));
1952 OUTS (outf
, " ++ ");
1953 OUTS (outf
, pregs (idx
));
1956 else if (aop
== 3 && W
== 0)
1958 OUTS (outf
, dregs (reg
));
1959 OUTS (outf
, " = W[");
1960 OUTS (outf
, pregs (ptr
));
1961 OUTS (outf
, " ++ ");
1962 OUTS (outf
, pregs (idx
));
1963 OUTS (outf
, "] (Z)");
1965 else if (aop
== 3 && W
== 1)
1967 OUTS (outf
, dregs (reg
));
1968 OUTS (outf
, " = W[");
1969 OUTS (outf
, pregs (ptr
));
1970 OUTS (outf
, " ++ ");
1971 OUTS (outf
, pregs (idx
));
1972 OUTS (outf
, "] (X)");
1974 else if (aop
== 0 && W
== 1)
1977 OUTS (outf
, pregs (ptr
));
1978 OUTS (outf
, " ++ ");
1979 OUTS (outf
, pregs (idx
));
1980 OUTS (outf
, "] = ");
1981 OUTS (outf
, dregs (reg
));
1983 else if (aop
== 1 && W
== 1)
1986 OUTS (outf
, pregs (ptr
));
1987 OUTS (outf
, " ++ ");
1988 OUTS (outf
, pregs (idx
));
1989 OUTS (outf
, "] = ");
1990 OUTS (outf
, dregs_lo (reg
));
1992 else if (aop
== 2 && W
== 1)
1995 OUTS (outf
, pregs (ptr
));
1996 OUTS (outf
, " ++ ");
1997 OUTS (outf
, pregs (idx
));
1998 OUTS (outf
, "] = ");
1999 OUTS (outf
, dregs_hi (reg
));
2008 decode_dagMODim_0 (TIword iw0
, disassemble_info
*outf
)
2011 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2012 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2013 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2014 int i
= ((iw0
>> DagMODim_i_bits
) & DagMODim_i_mask
);
2015 int m
= ((iw0
>> DagMODim_m_bits
) & DagMODim_m_mask
);
2016 int br
= ((iw0
>> DagMODim_br_bits
) & DagMODim_br_mask
);
2017 int op
= ((iw0
>> DagMODim_op_bits
) & DagMODim_op_mask
);
2019 if (op
== 0 && br
== 1)
2021 OUTS (outf
, iregs (i
));
2022 OUTS (outf
, " += ");
2023 OUTS (outf
, mregs (m
));
2024 OUTS (outf
, " (BREV)");
2028 OUTS (outf
, iregs (i
));
2029 OUTS (outf
, " += ");
2030 OUTS (outf
, mregs (m
));
2032 else if (op
== 1 && br
== 0)
2034 OUTS (outf
, iregs (i
));
2035 OUTS (outf
, " -= ");
2036 OUTS (outf
, mregs (m
));
2045 decode_dagMODik_0 (TIword iw0
, disassemble_info
*outf
)
2048 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2049 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2050 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2051 int i
= ((iw0
>> DagMODik_i_bits
) & DagMODik_i_mask
);
2052 int op
= ((iw0
>> DagMODik_op_bits
) & DagMODik_op_mask
);
2056 OUTS (outf
, iregs (i
));
2057 OUTS (outf
, " += 0x2");
2061 OUTS (outf
, iregs (i
));
2062 OUTS (outf
, " -= 0x2");
2066 OUTS (outf
, iregs (i
));
2067 OUTS (outf
, " += 0x4");
2071 OUTS (outf
, iregs (i
));
2072 OUTS (outf
, " -= 0x4");
2079 OUTS (outf
, ";\t\t/* ( ");
2080 if (op
== 0 || op
== 1)
2082 else if (op
== 2 || op
== 3)
2084 OUTS (outf
, ") */");
2092 decode_dspLDST_0 (TIword iw0
, disassemble_info
*outf
)
2095 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2096 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2097 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2098 int i
= ((iw0
>> DspLDST_i_bits
) & DspLDST_i_mask
);
2099 int m
= ((iw0
>> DspLDST_m_bits
) & DspLDST_m_mask
);
2100 int W
= ((iw0
>> DspLDST_W_bits
) & DspLDST_W_mask
);
2101 int aop
= ((iw0
>> DspLDST_aop_bits
) & DspLDST_aop_mask
);
2102 int reg
= ((iw0
>> DspLDST_reg_bits
) & DspLDST_reg_mask
);
2104 if (aop
== 0 && W
== 0 && m
== 0)
2106 OUTS (outf
, dregs (reg
));
2107 OUTS (outf
, " = [");
2108 OUTS (outf
, iregs (i
));
2111 else if (aop
== 0 && W
== 0 && m
== 1)
2113 OUTS (outf
, dregs_lo (reg
));
2114 OUTS (outf
, " = W[");
2115 OUTS (outf
, iregs (i
));
2118 else if (aop
== 0 && W
== 0 && m
== 2)
2120 OUTS (outf
, dregs_hi (reg
));
2121 OUTS (outf
, " = W[");
2122 OUTS (outf
, iregs (i
));
2125 else if (aop
== 1 && W
== 0 && m
== 0)
2127 OUTS (outf
, dregs (reg
));
2128 OUTS (outf
, " = [");
2129 OUTS (outf
, iregs (i
));
2132 else if (aop
== 1 && W
== 0 && m
== 1)
2134 OUTS (outf
, dregs_lo (reg
));
2135 OUTS (outf
, " = W[");
2136 OUTS (outf
, iregs (i
));
2139 else if (aop
== 1 && W
== 0 && m
== 2)
2141 OUTS (outf
, dregs_hi (reg
));
2142 OUTS (outf
, " = W[");
2143 OUTS (outf
, iregs (i
));
2146 else if (aop
== 2 && W
== 0 && m
== 0)
2148 OUTS (outf
, dregs (reg
));
2149 OUTS (outf
, " = [");
2150 OUTS (outf
, iregs (i
));
2153 else if (aop
== 2 && W
== 0 && m
== 1)
2155 OUTS (outf
, dregs_lo (reg
));
2156 OUTS (outf
, " = W[");
2157 OUTS (outf
, iregs (i
));
2160 else if (aop
== 2 && W
== 0 && m
== 2)
2162 OUTS (outf
, dregs_hi (reg
));
2163 OUTS (outf
, " = W[");
2164 OUTS (outf
, iregs (i
));
2167 else if (aop
== 0 && W
== 1 && m
== 0)
2170 OUTS (outf
, iregs (i
));
2171 OUTS (outf
, "++] = ");
2172 OUTS (outf
, dregs (reg
));
2174 else if (aop
== 0 && W
== 1 && m
== 1)
2177 OUTS (outf
, iregs (i
));
2178 OUTS (outf
, "++] = ");
2179 OUTS (outf
, dregs_lo (reg
));
2181 else if (aop
== 0 && W
== 1 && m
== 2)
2184 OUTS (outf
, iregs (i
));
2185 OUTS (outf
, "++] = ");
2186 OUTS (outf
, dregs_hi (reg
));
2188 else if (aop
== 1 && W
== 1 && m
== 0)
2191 OUTS (outf
, iregs (i
));
2192 OUTS (outf
, "--] = ");
2193 OUTS (outf
, dregs (reg
));
2195 else if (aop
== 1 && W
== 1 && m
== 1)
2198 OUTS (outf
, iregs (i
));
2199 OUTS (outf
, "--] = ");
2200 OUTS (outf
, dregs_lo (reg
));
2202 else if (aop
== 1 && W
== 1 && m
== 2)
2205 OUTS (outf
, iregs (i
));
2206 OUTS (outf
, "--] = ");
2207 OUTS (outf
, dregs_hi (reg
));
2209 else if (aop
== 2 && W
== 1 && m
== 0)
2212 OUTS (outf
, iregs (i
));
2213 OUTS (outf
, "] = ");
2214 OUTS (outf
, dregs (reg
));
2216 else if (aop
== 2 && W
== 1 && m
== 1)
2219 OUTS (outf
, iregs (i
));
2220 OUTS (outf
, "] = ");
2221 OUTS (outf
, dregs_lo (reg
));
2223 else if (aop
== 2 && W
== 1 && m
== 2)
2226 OUTS (outf
, iregs (i
));
2227 OUTS (outf
, "] = ");
2228 OUTS (outf
, dregs_hi (reg
));
2230 else if (aop
== 3 && W
== 0)
2232 OUTS (outf
, dregs (reg
));
2233 OUTS (outf
, " = [");
2234 OUTS (outf
, iregs (i
));
2235 OUTS (outf
, " ++ ");
2236 OUTS (outf
, mregs (m
));
2239 else if (aop
== 3 && W
== 1)
2242 OUTS (outf
, iregs (i
));
2243 OUTS (outf
, " ++ ");
2244 OUTS (outf
, mregs (m
));
2245 OUTS (outf
, "] = ");
2246 OUTS (outf
, dregs (reg
));
2255 decode_LDST_0 (TIword iw0
, disassemble_info
*outf
)
2258 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2259 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2260 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2261 int Z
= ((iw0
>> LDST_Z_bits
) & LDST_Z_mask
);
2262 int W
= ((iw0
>> LDST_W_bits
) & LDST_W_mask
);
2263 int sz
= ((iw0
>> LDST_sz_bits
) & LDST_sz_mask
);
2264 int aop
= ((iw0
>> LDST_aop_bits
) & LDST_aop_mask
);
2265 int reg
= ((iw0
>> LDST_reg_bits
) & LDST_reg_mask
);
2266 int ptr
= ((iw0
>> LDST_ptr_bits
) & LDST_ptr_mask
);
2268 if (aop
== 0 && sz
== 0 && Z
== 0 && W
== 0)
2270 OUTS (outf
, dregs (reg
));
2271 OUTS (outf
, " = [");
2272 OUTS (outf
, pregs (ptr
));
2275 else if (aop
== 0 && sz
== 0 && Z
== 1 && W
== 0 && reg
!= ptr
)
2277 OUTS (outf
, pregs (reg
));
2278 OUTS (outf
, " = [");
2279 OUTS (outf
, pregs (ptr
));
2282 else if (aop
== 0 && sz
== 1 && Z
== 0 && W
== 0)
2284 OUTS (outf
, dregs (reg
));
2285 OUTS (outf
, " = W[");
2286 OUTS (outf
, pregs (ptr
));
2287 OUTS (outf
, "++] (Z)");
2289 else if (aop
== 0 && sz
== 1 && Z
== 1 && W
== 0)
2291 OUTS (outf
, dregs (reg
));
2292 OUTS (outf
, " = W[");
2293 OUTS (outf
, pregs (ptr
));
2294 OUTS (outf
, "++] (X)");
2296 else if (aop
== 0 && sz
== 2 && Z
== 0 && W
== 0)
2298 OUTS (outf
, dregs (reg
));
2299 OUTS (outf
, " = B[");
2300 OUTS (outf
, pregs (ptr
));
2301 OUTS (outf
, "++] (Z)");
2303 else if (aop
== 0 && sz
== 2 && Z
== 1 && W
== 0)
2305 OUTS (outf
, dregs (reg
));
2306 OUTS (outf
, " = B[");
2307 OUTS (outf
, pregs (ptr
));
2308 OUTS (outf
, "++] (X)");
2310 else if (aop
== 1 && sz
== 0 && Z
== 0 && W
== 0)
2312 OUTS (outf
, dregs (reg
));
2313 OUTS (outf
, " = [");
2314 OUTS (outf
, pregs (ptr
));
2317 else if (aop
== 1 && sz
== 0 && Z
== 1 && W
== 0 && reg
!= ptr
)
2319 OUTS (outf
, pregs (reg
));
2320 OUTS (outf
, " = [");
2321 OUTS (outf
, pregs (ptr
));
2324 else if (aop
== 1 && sz
== 1 && Z
== 0 && W
== 0)
2326 OUTS (outf
, dregs (reg
));
2327 OUTS (outf
, " = W[");
2328 OUTS (outf
, pregs (ptr
));
2329 OUTS (outf
, "--] (Z)");
2331 else if (aop
== 1 && sz
== 1 && Z
== 1 && W
== 0)
2333 OUTS (outf
, dregs (reg
));
2334 OUTS (outf
, " = W[");
2335 OUTS (outf
, pregs (ptr
));
2336 OUTS (outf
, "--] (X)");
2338 else if (aop
== 1 && sz
== 2 && Z
== 0 && W
== 0)
2340 OUTS (outf
, dregs (reg
));
2341 OUTS (outf
, " = B[");
2342 OUTS (outf
, pregs (ptr
));
2343 OUTS (outf
, "--] (Z)");
2345 else if (aop
== 1 && sz
== 2 && Z
== 1 && W
== 0)
2347 OUTS (outf
, dregs (reg
));
2348 OUTS (outf
, " = B[");
2349 OUTS (outf
, pregs (ptr
));
2350 OUTS (outf
, "--] (X)");
2352 else if (aop
== 2 && sz
== 0 && Z
== 0 && W
== 0)
2354 OUTS (outf
, dregs (reg
));
2355 OUTS (outf
, " = [");
2356 OUTS (outf
, pregs (ptr
));
2359 else if (aop
== 2 && sz
== 0 && Z
== 1 && W
== 0)
2361 OUTS (outf
, pregs (reg
));
2362 OUTS (outf
, " = [");
2363 OUTS (outf
, pregs (ptr
));
2366 else if (aop
== 2 && sz
== 1 && Z
== 0 && W
== 0)
2368 OUTS (outf
, dregs (reg
));
2369 OUTS (outf
, " = W[");
2370 OUTS (outf
, pregs (ptr
));
2371 OUTS (outf
, "] (Z)");
2373 else if (aop
== 2 && sz
== 1 && Z
== 1 && W
== 0)
2375 OUTS (outf
, dregs (reg
));
2376 OUTS (outf
, " = W[");
2377 OUTS (outf
, pregs (ptr
));
2378 OUTS (outf
, "] (X)");
2380 else if (aop
== 2 && sz
== 2 && Z
== 0 && W
== 0)
2382 OUTS (outf
, dregs (reg
));
2383 OUTS (outf
, " = B[");
2384 OUTS (outf
, pregs (ptr
));
2385 OUTS (outf
, "] (Z)");
2387 else if (aop
== 2 && sz
== 2 && Z
== 1 && W
== 0)
2389 OUTS (outf
, dregs (reg
));
2390 OUTS (outf
, " = B[");
2391 OUTS (outf
, pregs (ptr
));
2392 OUTS (outf
, "] (X)");
2394 else if (aop
== 0 && sz
== 0 && Z
== 0 && W
== 1)
2397 OUTS (outf
, pregs (ptr
));
2398 OUTS (outf
, "++] = ");
2399 OUTS (outf
, dregs (reg
));
2401 else if (aop
== 0 && sz
== 0 && Z
== 1 && W
== 1)
2404 OUTS (outf
, pregs (ptr
));
2405 OUTS (outf
, "++] = ");
2406 OUTS (outf
, pregs (reg
));
2408 else if (aop
== 0 && sz
== 1 && Z
== 0 && W
== 1)
2411 OUTS (outf
, pregs (ptr
));
2412 OUTS (outf
, "++] = ");
2413 OUTS (outf
, dregs (reg
));
2415 else if (aop
== 0 && sz
== 2 && Z
== 0 && W
== 1)
2418 OUTS (outf
, pregs (ptr
));
2419 OUTS (outf
, "++] = ");
2420 OUTS (outf
, dregs (reg
));
2422 else if (aop
== 1 && sz
== 0 && Z
== 0 && W
== 1)
2425 OUTS (outf
, pregs (ptr
));
2426 OUTS (outf
, "--] = ");
2427 OUTS (outf
, dregs (reg
));
2429 else if (aop
== 1 && sz
== 0 && Z
== 1 && W
== 1)
2432 OUTS (outf
, pregs (ptr
));
2433 OUTS (outf
, "--] = ");
2434 OUTS (outf
, pregs (reg
));
2436 else if (aop
== 1 && sz
== 1 && Z
== 0 && W
== 1)
2439 OUTS (outf
, pregs (ptr
));
2440 OUTS (outf
, "--] = ");
2441 OUTS (outf
, dregs (reg
));
2443 else if (aop
== 1 && sz
== 2 && Z
== 0 && W
== 1)
2446 OUTS (outf
, pregs (ptr
));
2447 OUTS (outf
, "--] = ");
2448 OUTS (outf
, dregs (reg
));
2450 else if (aop
== 2 && sz
== 0 && Z
== 0 && W
== 1)
2453 OUTS (outf
, pregs (ptr
));
2454 OUTS (outf
, "] = ");
2455 OUTS (outf
, dregs (reg
));
2457 else if (aop
== 2 && sz
== 0 && Z
== 1 && W
== 1)
2460 OUTS (outf
, pregs (ptr
));
2461 OUTS (outf
, "] = ");
2462 OUTS (outf
, pregs (reg
));
2464 else if (aop
== 2 && sz
== 1 && Z
== 0 && W
== 1)
2467 OUTS (outf
, pregs (ptr
));
2468 OUTS (outf
, "] = ");
2469 OUTS (outf
, dregs (reg
));
2471 else if (aop
== 2 && sz
== 2 && Z
== 0 && W
== 1)
2474 OUTS (outf
, pregs (ptr
));
2475 OUTS (outf
, "] = ");
2476 OUTS (outf
, dregs (reg
));
2485 decode_LDSTiiFP_0 (TIword iw0
, disassemble_info
*outf
)
2488 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2489 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2490 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2491 int reg
= ((iw0
>> LDSTiiFP_reg_bits
) & LDSTiiFP_reg_mask
);
2492 int offset
= ((iw0
>> LDSTiiFP_offset_bits
) & LDSTiiFP_offset_mask
);
2493 int W
= ((iw0
>> LDSTiiFP_W_bits
) & LDSTiiFP_W_mask
);
2497 OUTS (outf
, dpregs (reg
));
2498 OUTS (outf
, " = [FP ");
2499 OUTS (outf
, negimm5s4 (offset
));
2504 OUTS (outf
, "[FP ");
2505 OUTS (outf
, negimm5s4 (offset
));
2506 OUTS (outf
, "] = ");
2507 OUTS (outf
, dpregs (reg
));
2516 decode_LDSTii_0 (TIword iw0
, disassemble_info
*outf
)
2519 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2520 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2521 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2522 int reg
= ((iw0
>> LDSTii_reg_bit
) & LDSTii_reg_mask
);
2523 int ptr
= ((iw0
>> LDSTii_ptr_bit
) & LDSTii_ptr_mask
);
2524 int offset
= ((iw0
>> LDSTii_offset_bit
) & LDSTii_offset_mask
);
2525 int op
= ((iw0
>> LDSTii_op_bit
) & LDSTii_op_mask
);
2526 int W
= ((iw0
>> LDSTii_W_bit
) & LDSTii_W_mask
);
2528 if (W
== 0 && op
== 0)
2530 OUTS (outf
, dregs (reg
));
2531 OUTS (outf
, " = [");
2532 OUTS (outf
, pregs (ptr
));
2534 OUTS (outf
, uimm4s4 (offset
));
2537 else if (W
== 0 && op
== 1)
2539 OUTS (outf
, dregs (reg
));
2540 OUTS (outf
, " = W[");
2541 OUTS (outf
, pregs (ptr
));
2543 OUTS (outf
, uimm4s2 (offset
));
2544 OUTS (outf
, "] (Z)");
2546 else if (W
== 0 && op
== 2)
2548 OUTS (outf
, dregs (reg
));
2549 OUTS (outf
, " = W[");
2550 OUTS (outf
, pregs (ptr
));
2552 OUTS (outf
, uimm4s2 (offset
));
2553 OUTS (outf
, "] (X)");
2555 else if (W
== 0 && op
== 3)
2557 OUTS (outf
, pregs (reg
));
2558 OUTS (outf
, " = [");
2559 OUTS (outf
, pregs (ptr
));
2561 OUTS (outf
, uimm4s4 (offset
));
2564 else if (W
== 1 && op
== 0)
2567 OUTS (outf
, pregs (ptr
));
2569 OUTS (outf
, uimm4s4 (offset
));
2570 OUTS (outf
, "] = ");
2571 OUTS (outf
, dregs (reg
));
2573 else if (W
== 1 && op
== 1)
2576 OUTS (outf
, pregs (ptr
));
2578 OUTS (outf
, uimm4s2 (offset
));
2579 OUTS (outf
, "] = ");
2580 OUTS (outf
, dregs (reg
));
2582 else if (W
== 1 && op
== 3)
2585 OUTS (outf
, pregs (ptr
));
2587 OUTS (outf
, uimm4s4 (offset
));
2588 OUTS (outf
, "] = ");
2589 OUTS (outf
, pregs (reg
));
2598 decode_LoopSetup_0 (TIword iw0
, TIword iw1
, bfd_vma pc
, disassemble_info
*outf
)
2601 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2602 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2603 |.reg...........| - | - |.eoffset...............................|
2604 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2605 int c
= ((iw0
>> (LoopSetup_c_bits
- 16)) & LoopSetup_c_mask
);
2606 int reg
= ((iw1
>> LoopSetup_reg_bits
) & LoopSetup_reg_mask
);
2607 int rop
= ((iw0
>> (LoopSetup_rop_bits
- 16)) & LoopSetup_rop_mask
);
2608 int soffset
= ((iw0
>> (LoopSetup_soffset_bits
- 16)) & LoopSetup_soffset_mask
);
2609 int eoffset
= ((iw1
>> LoopSetup_eoffset_bits
) & LoopSetup_eoffset_mask
);
2616 OUTS (outf
, "LSETUP");
2618 OUTS (outf
, pcrel4 (soffset
));
2619 OUTS (outf
, ", 0x");
2620 OUTS (outf
, lppcrel10 (eoffset
));
2622 OUTS (outf
, counters (c
));
2626 OUTS (outf
, "LSETUP");
2628 OUTS (outf
, pcrel4 (soffset
));
2629 OUTS (outf
, ", 0x");
2630 OUTS (outf
, lppcrel10 (eoffset
));
2632 OUTS (outf
, counters (c
));
2634 OUTS (outf
, pregs (reg
));
2638 OUTS (outf
, "LSETUP");
2640 OUTS (outf
, pcrel4 (soffset
));
2641 OUTS (outf
, ", 0x");
2642 OUTS (outf
, lppcrel10 (eoffset
));
2644 OUTS (outf
, counters (c
));
2646 OUTS (outf
, pregs (reg
));
2647 OUTS (outf
, " >> 0x1");
2656 decode_LDIMMhalf_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
2659 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2660 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2661 |.hword.........................................................|
2662 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2663 int H
= ((iw0
>> (LDIMMhalf_H_bits
- 16)) & LDIMMhalf_H_mask
);
2664 int Z
= ((iw0
>> (LDIMMhalf_Z_bits
- 16)) & LDIMMhalf_Z_mask
);
2665 int S
= ((iw0
>> (LDIMMhalf_S_bits
- 16)) & LDIMMhalf_S_mask
);
2666 int reg
= ((iw0
>> (LDIMMhalf_reg_bits
- 16)) & LDIMMhalf_reg_mask
);
2667 int grp
= ((iw0
>> (LDIMMhalf_grp_bits
- 16)) & LDIMMhalf_grp_mask
);
2668 int hword
= ((iw1
>> LDIMMhalf_hword_bits
) & LDIMMhalf_hword_mask
);
2670 bu32
*pval
= get_allreg (grp
, reg
);
2675 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2676 to combine them, so it prints out the right values.
2677 Here we keep track of the registers. */
2678 if (H
== 0 && S
== 1 && Z
== 0)
2680 /* regs = imm16 (x) */
2681 *pval
= imm16_val (hword
);
2683 *pval
|= 0xFFFF0000;
2687 else if (H
== 0 && S
== 0 && Z
== 1)
2689 /* regs = luimm16 (Z) */
2690 *pval
= luimm16_val (hword
);
2693 else if (H
== 0 && S
== 0 && Z
== 0)
2695 /* regs_lo = luimm16 */
2696 *pval
&= 0xFFFF0000;
2697 *pval
|= luimm16_val (hword
);
2699 else if (H
== 1 && S
== 0 && Z
== 0)
2701 /* regs_hi = huimm16 */
2703 *pval
|= luimm16_val (hword
) << 16;
2706 /* Here we do the disassembly */
2707 if (grp
== 0 && H
== 0 && S
== 0 && Z
== 0)
2709 OUTS (outf
, dregs_lo (reg
));
2711 OUTS (outf
, uimm16 (hword
));
2713 else if (grp
== 0 && H
== 1 && S
== 0 && Z
== 0)
2715 OUTS (outf
, dregs_hi (reg
));
2717 OUTS (outf
, uimm16 (hword
));
2719 else if (grp
== 0 && H
== 0 && S
== 1 && Z
== 0)
2721 OUTS (outf
, dregs (reg
));
2723 OUTS (outf
, imm16 (hword
));
2724 OUTS (outf
, " (X)");
2726 else if (H
== 0 && S
== 1 && Z
== 0)
2728 OUTS (outf
, regs (reg
, grp
));
2730 OUTS (outf
, imm16 (hword
));
2731 OUTS (outf
, " (X)");
2733 else if (H
== 0 && S
== 0 && Z
== 1)
2735 OUTS (outf
, regs (reg
, grp
));
2737 OUTS (outf
, uimm16 (hword
));
2738 OUTS (outf
, " (Z)");
2740 else if (H
== 0 && S
== 0 && Z
== 0)
2742 OUTS (outf
, regs_lo (reg
, grp
));
2744 OUTS (outf
, uimm16 (hword
));
2746 else if (H
== 1 && S
== 0 && Z
== 0)
2748 OUTS (outf
, regs_hi (reg
, grp
));
2750 OUTS (outf
, uimm16 (hword
));
2755 /* And we print out the 32-bit value if it is a pointer. */
2756 if (S
== 0 && Z
== 0)
2758 OUTS (outf
, ";\t\t/* (");
2759 OUTS (outf
, imm16d (hword
));
2762 /* If it is an MMR, don't print the symbol. */
2763 if (*pval
< 0xFFC00000 && grp
== 1)
2765 OUTS (outf
, regs (reg
, grp
));
2767 OUTS (outf
, huimm32e (*pval
));
2771 OUTS (outf
, regs (reg
, grp
));
2773 OUTS (outf
, huimm32e (*pval
));
2775 OUTS (outf
, imm32 (*pval
));
2782 if (S
== 1 || Z
== 1)
2784 OUTS (outf
, ";\t\t/*\t\t");
2785 OUTS (outf
, regs (reg
, grp
));
2787 OUTS (outf
, huimm32e (*pval
));
2789 OUTS (outf
, imm32 (*pval
));
2790 OUTS (outf
, ") */");
2797 decode_CALLa_0 (TIword iw0
, TIword iw1
, bfd_vma pc
, disassemble_info
*outf
)
2800 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2801 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2802 |.lsw...........................................................|
2803 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2804 int S
= ((iw0
>> (CALLa_S_bits
- 16)) & CALLa_S_mask
);
2805 int lsw
= ((iw1
>> 0) & 0xffff);
2806 int msw
= ((iw0
>> 0) & 0xff);
2812 OUTS (outf
, "CALL 0x");
2814 OUTS (outf
, "JUMP.L 0x");
2818 OUTS (outf
, pcrel24 (((msw
) << 16) | (lsw
)));
2823 decode_LDSTidxI_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
2826 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2827 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2828 |.offset........................................................|
2829 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2830 int Z
= ((iw0
>> (LDSTidxI_Z_bits
- 16)) & LDSTidxI_Z_mask
);
2831 int W
= ((iw0
>> (LDSTidxI_W_bits
- 16)) & LDSTidxI_W_mask
);
2832 int sz
= ((iw0
>> (LDSTidxI_sz_bits
- 16)) & LDSTidxI_sz_mask
);
2833 int reg
= ((iw0
>> (LDSTidxI_reg_bits
- 16)) & LDSTidxI_reg_mask
);
2834 int ptr
= ((iw0
>> (LDSTidxI_ptr_bits
- 16)) & LDSTidxI_ptr_mask
);
2835 int offset
= ((iw1
>> LDSTidxI_offset_bits
) & LDSTidxI_offset_mask
);
2837 if (W
== 0 && sz
== 0 && Z
== 0)
2839 OUTS (outf
, dregs (reg
));
2840 OUTS (outf
, " = [");
2841 OUTS (outf
, pregs (ptr
));
2843 OUTS (outf
, imm16s4 (offset
));
2846 else if (W
== 0 && sz
== 0 && Z
== 1)
2848 OUTS (outf
, pregs (reg
));
2849 OUTS (outf
, " = [");
2850 OUTS (outf
, pregs (ptr
));
2852 OUTS (outf
, imm16s4 (offset
));
2855 else if (W
== 0 && sz
== 1 && Z
== 0)
2857 OUTS (outf
, dregs (reg
));
2858 OUTS (outf
, " = W[");
2859 OUTS (outf
, pregs (ptr
));
2861 OUTS (outf
, imm16s2 (offset
));
2862 OUTS (outf
, "] (Z)");
2864 else if (W
== 0 && sz
== 1 && Z
== 1)
2866 OUTS (outf
, dregs (reg
));
2867 OUTS (outf
, " = W[");
2868 OUTS (outf
, pregs (ptr
));
2870 OUTS (outf
, imm16s2 (offset
));
2871 OUTS (outf
, "] (X)");
2873 else if (W
== 0 && sz
== 2 && Z
== 0)
2875 OUTS (outf
, dregs (reg
));
2876 OUTS (outf
, " = B[");
2877 OUTS (outf
, pregs (ptr
));
2879 OUTS (outf
, imm16 (offset
));
2880 OUTS (outf
, "] (Z)");
2882 else if (W
== 0 && sz
== 2 && Z
== 1)
2884 OUTS (outf
, dregs (reg
));
2885 OUTS (outf
, " = B[");
2886 OUTS (outf
, pregs (ptr
));
2888 OUTS (outf
, imm16 (offset
));
2889 OUTS (outf
, "] (X)");
2891 else if (W
== 1 && sz
== 0 && Z
== 0)
2894 OUTS (outf
, pregs (ptr
));
2896 OUTS (outf
, imm16s4 (offset
));
2897 OUTS (outf
, "] = ");
2898 OUTS (outf
, dregs (reg
));
2900 else if (W
== 1 && sz
== 0 && Z
== 1)
2903 OUTS (outf
, pregs (ptr
));
2905 OUTS (outf
, imm16s4 (offset
));
2906 OUTS (outf
, "] = ");
2907 OUTS (outf
, pregs (reg
));
2909 else if (W
== 1 && sz
== 1 && Z
== 0)
2912 OUTS (outf
, pregs (ptr
));
2914 OUTS (outf
, imm16s2 (offset
));
2915 OUTS (outf
, "] = ");
2916 OUTS (outf
, dregs (reg
));
2918 else if (W
== 1 && sz
== 2 && Z
== 0)
2921 OUTS (outf
, pregs (ptr
));
2923 OUTS (outf
, imm16 (offset
));
2924 OUTS (outf
, "] = ");
2925 OUTS (outf
, dregs (reg
));
2934 decode_linkage_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
2937 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2938 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2939 |.framesize.....................................................|
2940 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2941 int R
= ((iw0
>> (Linkage_R_bits
- 16)) & Linkage_R_mask
);
2942 int framesize
= ((iw1
>> Linkage_framesize_bits
) & Linkage_framesize_mask
);
2949 OUTS (outf
, "LINK ");
2950 OUTS (outf
, uimm16s4 (framesize
));
2951 OUTS (outf
, ";\t\t/* (");
2952 OUTS (outf
, uimm16s4d (framesize
));
2953 OUTS (outf
, ") */");
2957 OUTS (outf
, "UNLINK");
2965 decode_dsp32mac_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
2968 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2969 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2970 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2971 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2972 int op1
= ((iw0
>> (DSP32Mac_op1_bits
- 16)) & DSP32Mac_op1_mask
);
2973 int w1
= ((iw0
>> (DSP32Mac_w1_bits
- 16)) & DSP32Mac_w1_mask
);
2974 int P
= ((iw0
>> (DSP32Mac_p_bits
- 16)) & DSP32Mac_p_mask
);
2975 int MM
= ((iw0
>> (DSP32Mac_MM_bits
- 16)) & DSP32Mac_MM_mask
);
2976 int mmod
= ((iw0
>> (DSP32Mac_mmod_bits
- 16)) & DSP32Mac_mmod_mask
);
2977 int w0
= ((iw1
>> DSP32Mac_w0_bits
) & DSP32Mac_w0_mask
);
2978 int src0
= ((iw1
>> DSP32Mac_src0_bits
) & DSP32Mac_src0_mask
);
2979 int src1
= ((iw1
>> DSP32Mac_src1_bits
) & DSP32Mac_src1_mask
);
2980 int dst
= ((iw1
>> DSP32Mac_dst_bits
) & DSP32Mac_dst_mask
);
2981 int h10
= ((iw1
>> DSP32Mac_h10_bits
) & DSP32Mac_h10_mask
);
2982 int h00
= ((iw1
>> DSP32Mac_h00_bits
) & DSP32Mac_h00_mask
);
2983 int op0
= ((iw1
>> DSP32Mac_op0_bits
) & DSP32Mac_op0_mask
);
2984 int h11
= ((iw1
>> DSP32Mac_h11_bits
) & DSP32Mac_h11_mask
);
2985 int h01
= ((iw1
>> DSP32Mac_h01_bits
) & DSP32Mac_h01_mask
);
2987 if (w0
== 0 && w1
== 0 && op1
== 3 && op0
== 3)
2993 if ((w1
|| w0
) && mmod
== M_W32
)
2996 if (((1 << mmod
) & (P
? 0x131b : 0x1b5f)) == 0)
2999 if (w1
== 1 || op1
!= 3)
3002 OUTS (outf
, P
? dregs (dst
+ 1) : dregs_hi (dst
));
3005 OUTS (outf
, " = A1");
3009 OUTS (outf
, " = (");
3010 decode_macfunc (1, op1
, h01
, h11
, src0
, src1
, outf
);
3015 if (w0
== 1 || op0
!= 3)
3018 OUTS (outf
, " (M)");
3024 if (w0
== 1 || op0
!= 3)
3027 OUTS (outf
, P
? dregs (dst
) : dregs_lo (dst
));
3030 OUTS (outf
, " = A0");
3034 OUTS (outf
, " = (");
3035 decode_macfunc (0, op0
, h00
, h10
, src0
, src1
, outf
);
3041 decode_optmode (mmod
, MM
, outf
);
3047 decode_dsp32mult_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
3050 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3051 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3052 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3053 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3054 int w1
= ((iw0
>> (DSP32Mac_w1_bits
- 16)) & DSP32Mac_w1_mask
);
3055 int P
= ((iw0
>> (DSP32Mac_p_bits
- 16)) & DSP32Mac_p_mask
);
3056 int MM
= ((iw0
>> (DSP32Mac_MM_bits
- 16)) & DSP32Mac_MM_mask
);
3057 int mmod
= ((iw0
>> (DSP32Mac_mmod_bits
- 16)) & DSP32Mac_mmod_mask
);
3058 int w0
= ((iw1
>> DSP32Mac_w0_bits
) & DSP32Mac_w0_mask
);
3059 int src0
= ((iw1
>> DSP32Mac_src0_bits
) & DSP32Mac_src0_mask
);
3060 int src1
= ((iw1
>> DSP32Mac_src1_bits
) & DSP32Mac_src1_mask
);
3061 int dst
= ((iw1
>> DSP32Mac_dst_bits
) & DSP32Mac_dst_mask
);
3062 int h10
= ((iw1
>> DSP32Mac_h10_bits
) & DSP32Mac_h10_mask
);
3063 int h00
= ((iw1
>> DSP32Mac_h00_bits
) & DSP32Mac_h00_mask
);
3064 int h11
= ((iw1
>> DSP32Mac_h11_bits
) & DSP32Mac_h11_mask
);
3065 int h01
= ((iw1
>> DSP32Mac_h01_bits
) & DSP32Mac_h01_mask
);
3067 if (w1
== 0 && w0
== 0)
3070 if (((1 << mmod
) & (P
? 0x313 : 0x1b57)) == 0)
3075 OUTS (outf
, P
? dregs (dst
| 1) : dregs_hi (dst
));
3077 decode_multfunc (h01
, h11
, src0
, src1
, outf
);
3082 OUTS (outf
, " (M)");
3090 OUTS (outf
, dregs (dst
));
3092 decode_multfunc (h00
, h10
, src0
, src1
, outf
);
3095 decode_optmode (mmod
, MM
, outf
);
3100 decode_dsp32alu_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
3103 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3104 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3105 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3106 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3107 int s
= ((iw1
>> DSP32Alu_s_bits
) & DSP32Alu_s_mask
);
3108 int x
= ((iw1
>> DSP32Alu_x_bits
) & DSP32Alu_x_mask
);
3109 int aop
= ((iw1
>> DSP32Alu_aop_bits
) & DSP32Alu_aop_mask
);
3110 int src0
= ((iw1
>> DSP32Alu_src0_bits
) & DSP32Alu_src0_mask
);
3111 int src1
= ((iw1
>> DSP32Alu_src1_bits
) & DSP32Alu_src1_mask
);
3112 int dst0
= ((iw1
>> DSP32Alu_dst0_bits
) & DSP32Alu_dst0_mask
);
3113 int dst1
= ((iw1
>> DSP32Alu_dst1_bits
) & DSP32Alu_dst1_mask
);
3114 int HL
= ((iw0
>> (DSP32Alu_HL_bits
- 16)) & DSP32Alu_HL_mask
);
3115 int aopcde
= ((iw0
>> (DSP32Alu_aopcde_bits
- 16)) & DSP32Alu_aopcde_mask
);
3117 if (aop
== 0 && aopcde
== 9 && HL
== 0 && s
== 0)
3119 OUTS (outf
, "A0.L = ");
3120 OUTS (outf
, dregs_lo (src0
));
3122 else if (aop
== 2 && aopcde
== 9 && HL
== 1 && s
== 0)
3124 OUTS (outf
, "A1.H = ");
3125 OUTS (outf
, dregs_hi (src0
));
3127 else if (aop
== 2 && aopcde
== 9 && HL
== 0 && s
== 0)
3129 OUTS (outf
, "A1.L = ");
3130 OUTS (outf
, dregs_lo (src0
));
3132 else if (aop
== 0 && aopcde
== 9 && HL
== 1 && s
== 0)
3134 OUTS (outf
, "A0.H = ");
3135 OUTS (outf
, dregs_hi (src0
));
3137 else if (x
== 1 && HL
== 1 && aop
== 3 && aopcde
== 5)
3139 OUTS (outf
, dregs_hi (dst0
));
3141 OUTS (outf
, dregs (src0
));
3143 OUTS (outf
, dregs (src1
));
3144 OUTS (outf
, " (RND20)");
3146 else if (x
== 1 && HL
== 1 && aop
== 2 && aopcde
== 5)
3148 OUTS (outf
, dregs_hi (dst0
));
3150 OUTS (outf
, dregs (src0
));
3152 OUTS (outf
, dregs (src1
));
3153 OUTS (outf
, " (RND20)");
3155 else if (x
== 0 && HL
== 0 && aop
== 1 && aopcde
== 5)
3157 OUTS (outf
, dregs_lo (dst0
));
3159 OUTS (outf
, dregs (src0
));
3161 OUTS (outf
, dregs (src1
));
3162 OUTS (outf
, " (RND12)");
3164 else if (x
== 0 && HL
== 0 && aop
== 0 && aopcde
== 5)
3166 OUTS (outf
, dregs_lo (dst0
));
3168 OUTS (outf
, dregs (src0
));
3170 OUTS (outf
, dregs (src1
));
3171 OUTS (outf
, " (RND12)");
3173 else if (x
== 1 && HL
== 0 && aop
== 3 && aopcde
== 5)
3175 OUTS (outf
, dregs_lo (dst0
));
3177 OUTS (outf
, dregs (src0
));
3179 OUTS (outf
, dregs (src1
));
3180 OUTS (outf
, " (RND20)");
3182 else if (x
== 0 && HL
== 1 && aop
== 0 && aopcde
== 5)
3184 OUTS (outf
, dregs_hi (dst0
));
3186 OUTS (outf
, dregs (src0
));
3188 OUTS (outf
, dregs (src1
));
3189 OUTS (outf
, " (RND12)");
3191 else if (x
== 1 && HL
== 0 && aop
== 2 && aopcde
== 5)
3193 OUTS (outf
, dregs_lo (dst0
));
3195 OUTS (outf
, dregs (src0
));
3197 OUTS (outf
, dregs (src1
));
3198 OUTS (outf
, " (RND20)");
3200 else if (x
== 0 && HL
== 1 && aop
== 1 && aopcde
== 5)
3202 OUTS (outf
, dregs_hi (dst0
));
3204 OUTS (outf
, dregs (src0
));
3206 OUTS (outf
, dregs (src1
));
3207 OUTS (outf
, " (RND12)");
3209 else if (HL
== 1 && aop
== 0 && aopcde
== 2)
3211 OUTS (outf
, dregs_hi (dst0
));
3213 OUTS (outf
, dregs_lo (src0
));
3215 OUTS (outf
, dregs_lo (src1
));
3218 else if (HL
== 1 && aop
== 1 && aopcde
== 2)
3220 OUTS (outf
, dregs_hi (dst0
));
3222 OUTS (outf
, dregs_lo (src0
));
3224 OUTS (outf
, dregs_hi (src1
));
3227 else if (HL
== 1 && aop
== 2 && aopcde
== 2)
3229 OUTS (outf
, dregs_hi (dst0
));
3231 OUTS (outf
, dregs_hi (src0
));
3233 OUTS (outf
, dregs_lo (src1
));
3236 else if (HL
== 1 && aop
== 3 && aopcde
== 2)
3238 OUTS (outf
, dregs_hi (dst0
));
3240 OUTS (outf
, dregs_hi (src0
));
3242 OUTS (outf
, dregs_hi (src1
));
3245 else if (HL
== 0 && aop
== 0 && aopcde
== 3)
3247 OUTS (outf
, dregs_lo (dst0
));
3249 OUTS (outf
, dregs_lo (src0
));
3251 OUTS (outf
, dregs_lo (src1
));
3254 else if (HL
== 0 && aop
== 1 && aopcde
== 3)
3256 OUTS (outf
, dregs_lo (dst0
));
3258 OUTS (outf
, dregs_lo (src0
));
3260 OUTS (outf
, dregs_hi (src1
));
3263 else if (HL
== 0 && aop
== 3 && aopcde
== 2)
3265 OUTS (outf
, dregs_lo (dst0
));
3267 OUTS (outf
, dregs_hi (src0
));
3269 OUTS (outf
, dregs_hi (src1
));
3272 else if (HL
== 1 && aop
== 0 && aopcde
== 3)
3274 OUTS (outf
, dregs_hi (dst0
));
3276 OUTS (outf
, dregs_lo (src0
));
3278 OUTS (outf
, dregs_lo (src1
));
3281 else if (HL
== 1 && aop
== 1 && aopcde
== 3)
3283 OUTS (outf
, dregs_hi (dst0
));
3285 OUTS (outf
, dregs_lo (src0
));
3287 OUTS (outf
, dregs_hi (src1
));
3290 else if (HL
== 1 && aop
== 2 && aopcde
== 3)
3292 OUTS (outf
, dregs_hi (dst0
));
3294 OUTS (outf
, dregs_hi (src0
));
3296 OUTS (outf
, dregs_lo (src1
));
3299 else if (HL
== 1 && aop
== 3 && aopcde
== 3)
3301 OUTS (outf
, dregs_hi (dst0
));
3303 OUTS (outf
, dregs_hi (src0
));
3305 OUTS (outf
, dregs_hi (src1
));
3308 else if (HL
== 0 && aop
== 2 && aopcde
== 2)
3310 OUTS (outf
, dregs_lo (dst0
));
3312 OUTS (outf
, dregs_hi (src0
));
3314 OUTS (outf
, dregs_lo (src1
));
3317 else if (HL
== 0 && aop
== 1 && aopcde
== 2)
3319 OUTS (outf
, dregs_lo (dst0
));
3321 OUTS (outf
, dregs_lo (src0
));
3323 OUTS (outf
, dregs_hi (src1
));
3326 else if (HL
== 0 && aop
== 2 && aopcde
== 3)
3328 OUTS (outf
, dregs_lo (dst0
));
3330 OUTS (outf
, dregs_hi (src0
));
3332 OUTS (outf
, dregs_lo (src1
));
3335 else if (HL
== 0 && aop
== 3 && aopcde
== 3)
3337 OUTS (outf
, dregs_lo (dst0
));
3339 OUTS (outf
, dregs_hi (src0
));
3341 OUTS (outf
, dregs_hi (src1
));
3344 else if (HL
== 0 && aop
== 0 && aopcde
== 2)
3346 OUTS (outf
, dregs_lo (dst0
));
3348 OUTS (outf
, dregs_lo (src0
));
3350 OUTS (outf
, dregs_lo (src1
));
3353 else if (aop
== 0 && aopcde
== 9 && s
== 1)
3355 OUTS (outf
, "A0 = ");
3356 OUTS (outf
, dregs (src0
));
3358 else if (aop
== 3 && aopcde
== 11 && s
== 0)
3359 OUTS (outf
, "A0 -= A1");
3361 else if (aop
== 3 && aopcde
== 11 && s
== 1)
3362 OUTS (outf
, "A0 -= A1 (W32)");
3364 else if (aop
== 3 && aopcde
== 22 && HL
== 1)
3366 OUTS (outf
, dregs (dst0
));
3367 OUTS (outf
, " = BYTEOP2M (");
3368 OUTS (outf
, dregs (src0
+ 1));
3370 OUTS (outf
, imm5 (src0
));
3372 OUTS (outf
, dregs (src1
+ 1));
3374 OUTS (outf
, imm5 (src1
));
3375 OUTS (outf
, ") (TH");
3377 OUTS (outf
, ", R)");
3381 else if (aop
== 3 && aopcde
== 22 && HL
== 0)
3383 OUTS (outf
, dregs (dst0
));
3384 OUTS (outf
, " = BYTEOP2M (");
3385 OUTS (outf
, dregs (src0
+ 1));
3387 OUTS (outf
, imm5 (src0
));
3389 OUTS (outf
, dregs (src1
+ 1));
3391 OUTS (outf
, imm5 (src1
));
3392 OUTS (outf
, ") (TL");
3394 OUTS (outf
, ", R)");
3398 else if (aop
== 2 && aopcde
== 22 && HL
== 1)
3400 OUTS (outf
, dregs (dst0
));
3401 OUTS (outf
, " = BYTEOP2M (");
3402 OUTS (outf
, dregs (src0
+ 1));
3404 OUTS (outf
, imm5 (src0
));
3406 OUTS (outf
, dregs (src1
+ 1));
3408 OUTS (outf
, imm5 (src1
));
3409 OUTS (outf
, ") (RNDH");
3411 OUTS (outf
, ", R)");
3415 else if (aop
== 2 && aopcde
== 22 && HL
== 0)
3417 OUTS (outf
, dregs (dst0
));
3418 OUTS (outf
, " = BYTEOP2M (");
3419 OUTS (outf
, dregs (src0
+ 1));
3421 OUTS (outf
, imm5 (src0
));
3423 OUTS (outf
, dregs (src1
+ 1));
3425 OUTS (outf
, imm5 (src1
));
3426 OUTS (outf
, ") (RNDL");
3428 OUTS (outf
, ", R)");
3432 else if (aop
== 1 && aopcde
== 22 && HL
== 1)
3434 OUTS (outf
, dregs (dst0
));
3435 OUTS (outf
, " = BYTEOP2P (");
3436 OUTS (outf
, dregs (src0
+ 1));
3438 OUTS (outf
, imm5d (src0
));
3440 OUTS (outf
, dregs (src1
+ 1));
3442 OUTS (outf
, imm5d (src1
));
3443 OUTS (outf
, ") (TH");
3445 OUTS (outf
, ", R)");
3449 else if (aop
== 1 && aopcde
== 22 && HL
== 0)
3451 OUTS (outf
, dregs (dst0
));
3452 OUTS (outf
, " = BYTEOP2P (");
3453 OUTS (outf
, dregs (src0
+ 1));
3455 OUTS (outf
, imm5d (src0
));
3457 OUTS (outf
, dregs (src1
+ 1));
3459 OUTS (outf
, imm5d (src1
));
3460 OUTS (outf
, ") (TL");
3462 OUTS (outf
, ", R)");
3466 else if (aop
== 0 && aopcde
== 22 && HL
== 1)
3468 OUTS (outf
, dregs (dst0
));
3469 OUTS (outf
, " = BYTEOP2P (");
3470 OUTS (outf
, dregs (src0
+ 1));
3472 OUTS (outf
, imm5d (src0
));
3474 OUTS (outf
, dregs (src1
+ 1));
3476 OUTS (outf
, imm5d (src1
));
3477 OUTS (outf
, ") (RNDH");
3479 OUTS (outf
, ", R)");
3483 else if (aop
== 0 && aopcde
== 22 && HL
== 0)
3485 OUTS (outf
, dregs (dst0
));
3486 OUTS (outf
, " = BYTEOP2P (");
3487 OUTS (outf
, dregs (src0
+ 1));
3489 OUTS (outf
, imm5d (src0
));
3491 OUTS (outf
, dregs (src1
+ 1));
3493 OUTS (outf
, imm5d (src1
));
3494 OUTS (outf
, ") (RNDL");
3496 OUTS (outf
, ", R)");
3500 else if (aop
== 0 && s
== 0 && aopcde
== 8)
3501 OUTS (outf
, "A0 = 0");
3503 else if (aop
== 0 && s
== 1 && aopcde
== 8)
3504 OUTS (outf
, "A0 = A0 (S)");
3506 else if (aop
== 1 && s
== 0 && aopcde
== 8)
3507 OUTS (outf
, "A1 = 0");
3509 else if (aop
== 1 && s
== 1 && aopcde
== 8)
3510 OUTS (outf
, "A1 = A1 (S)");
3512 else if (aop
== 2 && s
== 0 && aopcde
== 8)
3513 OUTS (outf
, "A1 = A0 = 0");
3515 else if (aop
== 2 && s
== 1 && aopcde
== 8)
3516 OUTS (outf
, "A1 = A1 (S), A0 = A0 (S)");
3518 else if (aop
== 3 && s
== 0 && aopcde
== 8)
3519 OUTS (outf
, "A0 = A1");
3521 else if (aop
== 3 && s
== 1 && aopcde
== 8)
3522 OUTS (outf
, "A1 = A0");
3524 else if (aop
== 1 && aopcde
== 9 && s
== 0)
3526 OUTS (outf
, "A0.X = ");
3527 OUTS (outf
, dregs_lo (src0
));
3529 else if (aop
== 1 && HL
== 0 && aopcde
== 11)
3531 OUTS (outf
, dregs_lo (dst0
));
3532 OUTS (outf
, " = (A0 += A1)");
3534 else if (aop
== 3 && HL
== 0 && aopcde
== 16)
3535 OUTS (outf
, "A1 = ABS A0, A0 = ABS A0");
3537 else if (aop
== 0 && aopcde
== 23 && HL
== 1)
3539 OUTS (outf
, dregs (dst0
));
3540 OUTS (outf
, " = BYTEOP3P (");
3541 OUTS (outf
, dregs (src0
+ 1));
3543 OUTS (outf
, imm5d (src0
));
3545 OUTS (outf
, dregs (src1
+ 1));
3547 OUTS (outf
, imm5d (src1
));
3548 OUTS (outf
, ") (HI");
3550 OUTS (outf
, ", R)");
3554 else if (aop
== 3 && aopcde
== 9 && s
== 0)
3556 OUTS (outf
, "A1.X = ");
3557 OUTS (outf
, dregs_lo (src0
));
3559 else if (aop
== 1 && HL
== 1 && aopcde
== 16)
3560 OUTS (outf
, "A1 = ABS A1");
3562 else if (aop
== 0 && HL
== 1 && aopcde
== 16)
3563 OUTS (outf
, "A1 = ABS A0");
3565 else if (aop
== 2 && aopcde
== 9 && s
== 1)
3567 OUTS (outf
, "A1 = ");
3568 OUTS (outf
, dregs (src0
));
3570 else if (HL
== 0 && aop
== 3 && aopcde
== 12)
3572 OUTS (outf
, dregs_lo (dst0
));
3574 OUTS (outf
, dregs (src0
));
3575 OUTS (outf
, " (RND)");
3577 else if (aop
== 1 && HL
== 0 && aopcde
== 16)
3578 OUTS (outf
, "A0 = ABS A1");
3580 else if (aop
== 0 && HL
== 0 && aopcde
== 16)
3581 OUTS (outf
, "A0 = ABS A0");
3583 else if (aop
== 3 && HL
== 0 && aopcde
== 15)
3585 OUTS (outf
, dregs (dst0
));
3586 OUTS (outf
, " = -");
3587 OUTS (outf
, dregs (src0
));
3588 OUTS (outf
, " (V)");
3590 else if (aop
== 3 && s
== 1 && HL
== 0 && aopcde
== 7)
3592 OUTS (outf
, dregs (dst0
));
3593 OUTS (outf
, " = -");
3594 OUTS (outf
, dregs (src0
));
3595 OUTS (outf
, " (S)");
3597 else if (aop
== 3 && s
== 0 && HL
== 0 && aopcde
== 7)
3599 OUTS (outf
, dregs (dst0
));
3600 OUTS (outf
, " = -");
3601 OUTS (outf
, dregs (src0
));
3602 OUTS (outf
, " (NS)");
3604 else if (aop
== 1 && HL
== 1 && aopcde
== 11)
3606 OUTS (outf
, dregs_hi (dst0
));
3607 OUTS (outf
, " = (A0 += A1)");
3609 else if (aop
== 2 && aopcde
== 11 && s
== 0)
3610 OUTS (outf
, "A0 += A1");
3612 else if (aop
== 2 && aopcde
== 11 && s
== 1)
3613 OUTS (outf
, "A0 += A1 (W32)");
3615 else if (aop
== 3 && HL
== 0 && aopcde
== 14)
3616 OUTS (outf
, "A1 = -A1, A0 = -A0");
3618 else if (HL
== 1 && aop
== 3 && aopcde
== 12)
3620 OUTS (outf
, dregs_hi (dst0
));
3622 OUTS (outf
, dregs (src0
));
3623 OUTS (outf
, " (RND)");
3625 else if (aop
== 0 && aopcde
== 23 && HL
== 0)
3627 OUTS (outf
, dregs (dst0
));
3628 OUTS (outf
, " = BYTEOP3P (");
3629 OUTS (outf
, dregs (src0
+ 1));
3631 OUTS (outf
, imm5d (src0
));
3633 OUTS (outf
, dregs (src1
+ 1));
3635 OUTS (outf
, imm5d (src1
));
3636 OUTS (outf
, ") (LO");
3638 OUTS (outf
, ", R)");
3642 else if (aop
== 0 && HL
== 0 && aopcde
== 14)
3643 OUTS (outf
, "A0 = -A0");
3645 else if (aop
== 1 && HL
== 0 && aopcde
== 14)
3646 OUTS (outf
, "A0 = -A1");
3648 else if (aop
== 0 && HL
== 1 && aopcde
== 14)
3649 OUTS (outf
, "A1 = -A0");
3651 else if (aop
== 1 && HL
== 1 && aopcde
== 14)
3652 OUTS (outf
, "A1 = -A1");
3654 else if (aop
== 0 && aopcde
== 12)
3656 OUTS (outf
, dregs_hi (dst0
));
3658 OUTS (outf
, dregs_lo (dst0
));
3659 OUTS (outf
, " = SIGN (");
3660 OUTS (outf
, dregs_hi (src0
));
3661 OUTS (outf
, ") * ");
3662 OUTS (outf
, dregs_hi (src1
));
3663 OUTS (outf
, " + SIGN (");
3664 OUTS (outf
, dregs_lo (src0
));
3665 OUTS (outf
, ") * ");
3666 OUTS (outf
, dregs_lo (src1
));
3668 else if (aop
== 2 && aopcde
== 0)
3670 OUTS (outf
, dregs (dst0
));
3672 OUTS (outf
, dregs (src0
));
3673 OUTS (outf
, " -|+ ");
3674 OUTS (outf
, dregs (src1
));
3677 else if (aop
== 1 && aopcde
== 12)
3679 OUTS (outf
, dregs (dst1
));
3680 OUTS (outf
, " = A1.L + A1.H, ");
3681 OUTS (outf
, dregs (dst0
));
3682 OUTS (outf
, " = A0.L + A0.H");
3684 else if (aop
== 2 && aopcde
== 4)
3686 OUTS (outf
, dregs (dst1
));
3688 OUTS (outf
, dregs (src0
));
3690 OUTS (outf
, dregs (src1
));
3692 OUTS (outf
, dregs (dst0
));
3694 OUTS (outf
, dregs (src0
));
3696 OUTS (outf
, dregs (src1
));
3699 else if (HL
== 0 && aopcde
== 1)
3701 OUTS (outf
, dregs (dst1
));
3703 OUTS (outf
, dregs (src0
));
3704 OUTS (outf
, " +|+ ");
3705 OUTS (outf
, dregs (src1
));
3707 OUTS (outf
, dregs (dst0
));
3709 OUTS (outf
, dregs (src0
));
3710 OUTS (outf
, " -|- ");
3711 OUTS (outf
, dregs (src1
));
3712 amod0amod2 (s
, x
, aop
, outf
);
3714 else if (aop
== 0 && aopcde
== 11)
3716 OUTS (outf
, dregs (dst0
));
3717 OUTS (outf
, " = (A0 += A1)");
3719 else if (aop
== 0 && aopcde
== 10)
3721 OUTS (outf
, dregs_lo (dst0
));
3722 OUTS (outf
, " = A0.X");
3724 else if (aop
== 1 && aopcde
== 10)
3726 OUTS (outf
, dregs_lo (dst0
));
3727 OUTS (outf
, " = A1.X");
3729 else if (aop
== 1 && aopcde
== 0)
3731 OUTS (outf
, dregs (dst0
));
3733 OUTS (outf
, dregs (src0
));
3734 OUTS (outf
, " +|- ");
3735 OUTS (outf
, dregs (src1
));
3738 else if (aop
== 3 && aopcde
== 0)
3740 OUTS (outf
, dregs (dst0
));
3742 OUTS (outf
, dregs (src0
));
3743 OUTS (outf
, " -|- ");
3744 OUTS (outf
, dregs (src1
));
3747 else if (aop
== 1 && aopcde
== 4)
3749 OUTS (outf
, dregs (dst0
));
3751 OUTS (outf
, dregs (src0
));
3753 OUTS (outf
, dregs (src1
));
3756 else if (aop
== 0 && aopcde
== 17)
3758 OUTS (outf
, dregs (dst1
));
3759 OUTS (outf
, " = A1 + A0, ");
3760 OUTS (outf
, dregs (dst0
));
3761 OUTS (outf
, " = A1 - A0");
3764 else if (aop
== 1 && aopcde
== 17)
3766 OUTS (outf
, dregs (dst1
));
3767 OUTS (outf
, " = A0 + A1, ");
3768 OUTS (outf
, dregs (dst0
));
3769 OUTS (outf
, " = A0 - A1");
3772 else if (aop
== 0 && aopcde
== 18)
3774 OUTS (outf
, "SAA (");
3775 OUTS (outf
, dregs (src0
+ 1));
3777 OUTS (outf
, imm5d (src0
));
3779 OUTS (outf
, dregs (src1
+ 1));
3781 OUTS (outf
, imm5d (src1
));
3785 else if (aop
== 3 && aopcde
== 18)
3786 OUTS (outf
, "DISALGNEXCPT");
3788 else if (aop
== 0 && aopcde
== 20)
3790 OUTS (outf
, dregs (dst0
));
3791 OUTS (outf
, " = BYTEOP1P (");
3792 OUTS (outf
, dregs (src0
+ 1));
3794 OUTS (outf
, imm5d (src0
));
3796 OUTS (outf
, dregs (src1
+ 1));
3798 OUTS (outf
, imm5d (src1
));
3802 else if (aop
== 1 && aopcde
== 20)
3804 OUTS (outf
, dregs (dst0
));
3805 OUTS (outf
, " = BYTEOP1P (");
3806 OUTS (outf
, dregs (src0
+ 1));
3808 OUTS (outf
, imm5d (src0
));
3810 OUTS (outf
, dregs (src1
+ 1));
3812 OUTS (outf
, imm5d (src1
));
3813 OUTS (outf
, ") (T");
3815 OUTS (outf
, ", R)");
3819 else if (aop
== 0 && aopcde
== 21)
3822 OUTS (outf
, dregs (dst1
));
3824 OUTS (outf
, dregs (dst0
));
3825 OUTS (outf
, ") = BYTEOP16P (");
3826 OUTS (outf
, dregs (src0
+ 1));
3828 OUTS (outf
, imm5d (src0
));
3830 OUTS (outf
, dregs (src1
+ 1));
3832 OUTS (outf
, imm5d (src1
));
3836 else if (aop
== 1 && aopcde
== 21)
3839 OUTS (outf
, dregs (dst1
));
3841 OUTS (outf
, dregs (dst0
));
3842 OUTS (outf
, ") = BYTEOP16M (");
3843 OUTS (outf
, dregs (src0
+ 1));
3845 OUTS (outf
, imm5d (src0
));
3847 OUTS (outf
, dregs (src1
+ 1));
3849 OUTS (outf
, imm5d (src1
));
3853 else if (aop
== 2 && aopcde
== 7)
3855 OUTS (outf
, dregs (dst0
));
3856 OUTS (outf
, " = ABS ");
3857 OUTS (outf
, dregs (src0
));
3859 else if (aop
== 1 && aopcde
== 7)
3861 OUTS (outf
, dregs (dst0
));
3862 OUTS (outf
, " = MIN (");
3863 OUTS (outf
, dregs (src0
));
3865 OUTS (outf
, dregs (src1
));
3868 else if (aop
== 0 && aopcde
== 7)
3870 OUTS (outf
, dregs (dst0
));
3871 OUTS (outf
, " = MAX (");
3872 OUTS (outf
, dregs (src0
));
3874 OUTS (outf
, dregs (src1
));
3877 else if (aop
== 2 && aopcde
== 6)
3879 OUTS (outf
, dregs (dst0
));
3880 OUTS (outf
, " = ABS ");
3881 OUTS (outf
, dregs (src0
));
3882 OUTS (outf
, " (V)");
3884 else if (aop
== 1 && aopcde
== 6)
3886 OUTS (outf
, dregs (dst0
));
3887 OUTS (outf
, " = MIN (");
3888 OUTS (outf
, dregs (src0
));
3890 OUTS (outf
, dregs (src1
));
3891 OUTS (outf
, ") (V)");
3893 else if (aop
== 0 && aopcde
== 6)
3895 OUTS (outf
, dregs (dst0
));
3896 OUTS (outf
, " = MAX (");
3897 OUTS (outf
, dregs (src0
));
3899 OUTS (outf
, dregs (src1
));
3900 OUTS (outf
, ") (V)");
3902 else if (HL
== 1 && aopcde
== 1)
3904 OUTS (outf
, dregs (dst1
));
3906 OUTS (outf
, dregs (src0
));
3907 OUTS (outf
, " +|- ");
3908 OUTS (outf
, dregs (src1
));
3910 OUTS (outf
, dregs (dst0
));
3912 OUTS (outf
, dregs (src0
));
3913 OUTS (outf
, " -|+ ");
3914 OUTS (outf
, dregs (src1
));
3915 amod0amod2 (s
, x
, aop
, outf
);
3917 else if (aop
== 0 && aopcde
== 4)
3919 OUTS (outf
, dregs (dst0
));
3921 OUTS (outf
, dregs (src0
));
3923 OUTS (outf
, dregs (src1
));
3926 else if (aop
== 0 && aopcde
== 0)
3928 OUTS (outf
, dregs (dst0
));
3930 OUTS (outf
, dregs (src0
));
3931 OUTS (outf
, " +|+ ");
3932 OUTS (outf
, dregs (src1
));
3935 else if (aop
== 0 && aopcde
== 24)
3937 OUTS (outf
, dregs (dst0
));
3938 OUTS (outf
, " = BYTEPACK (");
3939 OUTS (outf
, dregs (src0
));
3941 OUTS (outf
, dregs (src1
));
3944 else if (aop
== 1 && aopcde
== 24)
3947 OUTS (outf
, dregs (dst1
));
3949 OUTS (outf
, dregs (dst0
));
3950 OUTS (outf
, ") = BYTEUNPACK ");
3951 OUTS (outf
, dregs (src0
+ 1));
3953 OUTS (outf
, imm5d (src0
));
3956 else if (aopcde
== 13)
3959 OUTS (outf
, dregs (dst1
));
3961 OUTS (outf
, dregs (dst0
));
3962 OUTS (outf
, ") = SEARCH ");
3963 OUTS (outf
, dregs (src0
));
3965 searchmod (aop
, outf
);
3975 decode_dsp32shift_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
3978 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3979 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3980 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3981 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3982 int HLs
= ((iw1
>> DSP32Shift_HLs_bits
) & DSP32Shift_HLs_mask
);
3983 int sop
= ((iw1
>> DSP32Shift_sop_bits
) & DSP32Shift_sop_mask
);
3984 int src0
= ((iw1
>> DSP32Shift_src0_bits
) & DSP32Shift_src0_mask
);
3985 int src1
= ((iw1
>> DSP32Shift_src1_bits
) & DSP32Shift_src1_mask
);
3986 int dst0
= ((iw1
>> DSP32Shift_dst0_bits
) & DSP32Shift_dst0_mask
);
3987 int sopcde
= ((iw0
>> (DSP32Shift_sopcde_bits
- 16)) & DSP32Shift_sopcde_mask
);
3988 const char *acc01
= (HLs
& 1) == 0 ? "A0" : "A1";
3990 if (HLs
== 0 && sop
== 0 && sopcde
== 0)
3992 OUTS (outf
, dregs_lo (dst0
));
3993 OUTS (outf
, " = ASHIFT ");
3994 OUTS (outf
, dregs_lo (src1
));
3995 OUTS (outf
, " BY ");
3996 OUTS (outf
, dregs_lo (src0
));
3998 else if (HLs
== 1 && sop
== 0 && sopcde
== 0)
4000 OUTS (outf
, dregs_lo (dst0
));
4001 OUTS (outf
, " = ASHIFT ");
4002 OUTS (outf
, dregs_hi (src1
));
4003 OUTS (outf
, " BY ");
4004 OUTS (outf
, dregs_lo (src0
));
4006 else if (HLs
== 2 && sop
== 0 && sopcde
== 0)
4008 OUTS (outf
, dregs_hi (dst0
));
4009 OUTS (outf
, " = ASHIFT ");
4010 OUTS (outf
, dregs_lo (src1
));
4011 OUTS (outf
, " BY ");
4012 OUTS (outf
, dregs_lo (src0
));
4014 else if (HLs
== 3 && sop
== 0 && sopcde
== 0)
4016 OUTS (outf
, dregs_hi (dst0
));
4017 OUTS (outf
, " = ASHIFT ");
4018 OUTS (outf
, dregs_hi (src1
));
4019 OUTS (outf
, " BY ");
4020 OUTS (outf
, dregs_lo (src0
));
4022 else if (HLs
== 0 && sop
== 1 && sopcde
== 0)
4024 OUTS (outf
, dregs_lo (dst0
));
4025 OUTS (outf
, " = ASHIFT ");
4026 OUTS (outf
, dregs_lo (src1
));
4027 OUTS (outf
, " BY ");
4028 OUTS (outf
, dregs_lo (src0
));
4029 OUTS (outf
, " (S)");
4031 else if (HLs
== 1 && sop
== 1 && sopcde
== 0)
4033 OUTS (outf
, dregs_lo (dst0
));
4034 OUTS (outf
, " = ASHIFT ");
4035 OUTS (outf
, dregs_hi (src1
));
4036 OUTS (outf
, " BY ");
4037 OUTS (outf
, dregs_lo (src0
));
4038 OUTS (outf
, " (S)");
4040 else if (HLs
== 2 && sop
== 1 && sopcde
== 0)
4042 OUTS (outf
, dregs_hi (dst0
));
4043 OUTS (outf
, " = ASHIFT ");
4044 OUTS (outf
, dregs_lo (src1
));
4045 OUTS (outf
, " BY ");
4046 OUTS (outf
, dregs_lo (src0
));
4047 OUTS (outf
, " (S)");
4049 else if (HLs
== 3 && sop
== 1 && sopcde
== 0)
4051 OUTS (outf
, dregs_hi (dst0
));
4052 OUTS (outf
, " = ASHIFT ");
4053 OUTS (outf
, dregs_hi (src1
));
4054 OUTS (outf
, " BY ");
4055 OUTS (outf
, dregs_lo (src0
));
4056 OUTS (outf
, " (S)");
4058 else if (sop
== 2 && sopcde
== 0)
4060 OUTS (outf
, (HLs
& 2) == 0 ? dregs_lo (dst0
) : dregs_hi (dst0
));
4061 OUTS (outf
, " = LSHIFT ");
4062 OUTS (outf
, (HLs
& 1) == 0 ? dregs_lo (src1
) : dregs_hi (src1
));
4063 OUTS (outf
, " BY ");
4064 OUTS (outf
, dregs_lo (src0
));
4066 else if (sop
== 0 && sopcde
== 3)
4069 OUTS (outf
, " = ASHIFT ");
4071 OUTS (outf
, " BY ");
4072 OUTS (outf
, dregs_lo (src0
));
4074 else if (sop
== 1 && sopcde
== 3)
4077 OUTS (outf
, " = LSHIFT ");
4079 OUTS (outf
, " BY ");
4080 OUTS (outf
, dregs_lo (src0
));
4082 else if (sop
== 2 && sopcde
== 3)
4085 OUTS (outf
, " = ROT ");
4087 OUTS (outf
, " BY ");
4088 OUTS (outf
, dregs_lo (src0
));
4090 else if (sop
== 3 && sopcde
== 3)
4092 OUTS (outf
, dregs (dst0
));
4093 OUTS (outf
, " = ROT ");
4094 OUTS (outf
, dregs (src1
));
4095 OUTS (outf
, " BY ");
4096 OUTS (outf
, dregs_lo (src0
));
4098 else if (sop
== 1 && sopcde
== 1)
4100 OUTS (outf
, dregs (dst0
));
4101 OUTS (outf
, " = ASHIFT ");
4102 OUTS (outf
, dregs (src1
));
4103 OUTS (outf
, " BY ");
4104 OUTS (outf
, dregs_lo (src0
));
4105 OUTS (outf
, " (V, S)");
4107 else if (sop
== 0 && sopcde
== 1)
4109 OUTS (outf
, dregs (dst0
));
4110 OUTS (outf
, " = ASHIFT ");
4111 OUTS (outf
, dregs (src1
));
4112 OUTS (outf
, " BY ");
4113 OUTS (outf
, dregs_lo (src0
));
4114 OUTS (outf
, " (V)");
4116 else if (sop
== 0 && sopcde
== 2)
4118 OUTS (outf
, dregs (dst0
));
4119 OUTS (outf
, " = ASHIFT ");
4120 OUTS (outf
, dregs (src1
));
4121 OUTS (outf
, " BY ");
4122 OUTS (outf
, dregs_lo (src0
));
4124 else if (sop
== 1 && sopcde
== 2)
4126 OUTS (outf
, dregs (dst0
));
4127 OUTS (outf
, " = ASHIFT ");
4128 OUTS (outf
, dregs (src1
));
4129 OUTS (outf
, " BY ");
4130 OUTS (outf
, dregs_lo (src0
));
4131 OUTS (outf
, " (S)");
4133 else if (sop
== 2 && sopcde
== 2)
4135 OUTS (outf
, dregs (dst0
));
4136 OUTS (outf
, " = LSHIFT ");
4137 OUTS (outf
, dregs (src1
));
4138 OUTS (outf
, " BY ");
4139 OUTS (outf
, dregs_lo (src0
));
4141 else if (sop
== 3 && sopcde
== 2)
4143 OUTS (outf
, dregs (dst0
));
4144 OUTS (outf
, " = ROT ");
4145 OUTS (outf
, dregs (src1
));
4146 OUTS (outf
, " BY ");
4147 OUTS (outf
, dregs_lo (src0
));
4149 else if (sop
== 2 && sopcde
== 1)
4151 OUTS (outf
, dregs (dst0
));
4152 OUTS (outf
, " = LSHIFT ");
4153 OUTS (outf
, dregs (src1
));
4154 OUTS (outf
, " BY ");
4155 OUTS (outf
, dregs_lo (src0
));
4156 OUTS (outf
, " (V)");
4158 else if (sop
== 0 && sopcde
== 4)
4160 OUTS (outf
, dregs (dst0
));
4161 OUTS (outf
, " = PACK (");
4162 OUTS (outf
, dregs_lo (src1
));
4164 OUTS (outf
, dregs_lo (src0
));
4167 else if (sop
== 1 && sopcde
== 4)
4169 OUTS (outf
, dregs (dst0
));
4170 OUTS (outf
, " = PACK (");
4171 OUTS (outf
, dregs_lo (src1
));
4173 OUTS (outf
, dregs_hi (src0
));
4176 else if (sop
== 2 && sopcde
== 4)
4178 OUTS (outf
, dregs (dst0
));
4179 OUTS (outf
, " = PACK (");
4180 OUTS (outf
, dregs_hi (src1
));
4182 OUTS (outf
, dregs_lo (src0
));
4185 else if (sop
== 3 && sopcde
== 4)
4187 OUTS (outf
, dregs (dst0
));
4188 OUTS (outf
, " = PACK (");
4189 OUTS (outf
, dregs_hi (src1
));
4191 OUTS (outf
, dregs_hi (src0
));
4194 else if (sop
== 0 && sopcde
== 5)
4196 OUTS (outf
, dregs_lo (dst0
));
4197 OUTS (outf
, " = SIGNBITS ");
4198 OUTS (outf
, dregs (src1
));
4200 else if (sop
== 1 && sopcde
== 5)
4202 OUTS (outf
, dregs_lo (dst0
));
4203 OUTS (outf
, " = SIGNBITS ");
4204 OUTS (outf
, dregs_lo (src1
));
4206 else if (sop
== 2 && sopcde
== 5)
4208 OUTS (outf
, dregs_lo (dst0
));
4209 OUTS (outf
, " = SIGNBITS ");
4210 OUTS (outf
, dregs_hi (src1
));
4212 else if (sop
== 0 && sopcde
== 6)
4214 OUTS (outf
, dregs_lo (dst0
));
4215 OUTS (outf
, " = SIGNBITS A0");
4217 else if (sop
== 1 && sopcde
== 6)
4219 OUTS (outf
, dregs_lo (dst0
));
4220 OUTS (outf
, " = SIGNBITS A1");
4222 else if (sop
== 3 && sopcde
== 6)
4224 OUTS (outf
, dregs_lo (dst0
));
4225 OUTS (outf
, " = ONES ");
4226 OUTS (outf
, dregs (src1
));
4228 else if (sop
== 0 && sopcde
== 7)
4230 OUTS (outf
, dregs_lo (dst0
));
4231 OUTS (outf
, " = EXPADJ (");
4232 OUTS (outf
, dregs (src1
));
4234 OUTS (outf
, dregs_lo (src0
));
4237 else if (sop
== 1 && sopcde
== 7)
4239 OUTS (outf
, dregs_lo (dst0
));
4240 OUTS (outf
, " = EXPADJ (");
4241 OUTS (outf
, dregs (src1
));
4243 OUTS (outf
, dregs_lo (src0
));
4244 OUTS (outf
, ") (V)");
4246 else if (sop
== 2 && sopcde
== 7)
4248 OUTS (outf
, dregs_lo (dst0
));
4249 OUTS (outf
, " = EXPADJ (");
4250 OUTS (outf
, dregs_lo (src1
));
4252 OUTS (outf
, dregs_lo (src0
));
4255 else if (sop
== 3 && sopcde
== 7)
4257 OUTS (outf
, dregs_lo (dst0
));
4258 OUTS (outf
, " = EXPADJ (");
4259 OUTS (outf
, dregs_hi (src1
));
4261 OUTS (outf
, dregs_lo (src0
));
4264 else if (sop
== 0 && sopcde
== 8)
4266 OUTS (outf
, "BITMUX (");
4267 OUTS (outf
, dregs (src0
));
4269 OUTS (outf
, dregs (src1
));
4270 OUTS (outf
, ", A0) (ASR)");
4272 else if (sop
== 1 && sopcde
== 8)
4274 OUTS (outf
, "BITMUX (");
4275 OUTS (outf
, dregs (src0
));
4277 OUTS (outf
, dregs (src1
));
4278 OUTS (outf
, ", A0) (ASL)");
4280 else if (sop
== 0 && sopcde
== 9)
4282 OUTS (outf
, dregs_lo (dst0
));
4283 OUTS (outf
, " = VIT_MAX (");
4284 OUTS (outf
, dregs (src1
));
4285 OUTS (outf
, ") (ASL)");
4287 else if (sop
== 1 && sopcde
== 9)
4289 OUTS (outf
, dregs_lo (dst0
));
4290 OUTS (outf
, " = VIT_MAX (");
4291 OUTS (outf
, dregs (src1
));
4292 OUTS (outf
, ") (ASR)");
4294 else if (sop
== 2 && sopcde
== 9)
4296 OUTS (outf
, dregs (dst0
));
4297 OUTS (outf
, " = VIT_MAX (");
4298 OUTS (outf
, dregs (src1
));
4300 OUTS (outf
, dregs (src0
));
4301 OUTS (outf
, ") (ASL)");
4303 else if (sop
== 3 && sopcde
== 9)
4305 OUTS (outf
, dregs (dst0
));
4306 OUTS (outf
, " = VIT_MAX (");
4307 OUTS (outf
, dregs (src1
));
4309 OUTS (outf
, dregs (src0
));
4310 OUTS (outf
, ") (ASR)");
4312 else if (sop
== 0 && sopcde
== 10)
4314 OUTS (outf
, dregs (dst0
));
4315 OUTS (outf
, " = EXTRACT (");
4316 OUTS (outf
, dregs (src1
));
4318 OUTS (outf
, dregs_lo (src0
));
4319 OUTS (outf
, ") (Z)");
4321 else if (sop
== 1 && sopcde
== 10)
4323 OUTS (outf
, dregs (dst0
));
4324 OUTS (outf
, " = EXTRACT (");
4325 OUTS (outf
, dregs (src1
));
4327 OUTS (outf
, dregs_lo (src0
));
4328 OUTS (outf
, ") (X)");
4330 else if (sop
== 2 && sopcde
== 10)
4332 OUTS (outf
, dregs (dst0
));
4333 OUTS (outf
, " = DEPOSIT (");
4334 OUTS (outf
, dregs (src1
));
4336 OUTS (outf
, dregs (src0
));
4339 else if (sop
== 3 && sopcde
== 10)
4341 OUTS (outf
, dregs (dst0
));
4342 OUTS (outf
, " = DEPOSIT (");
4343 OUTS (outf
, dregs (src1
));
4345 OUTS (outf
, dregs (src0
));
4346 OUTS (outf
, ") (X)");
4348 else if (sop
== 0 && sopcde
== 11)
4350 OUTS (outf
, dregs_lo (dst0
));
4351 OUTS (outf
, " = CC = BXORSHIFT (A0, ");
4352 OUTS (outf
, dregs (src0
));
4355 else if (sop
== 1 && sopcde
== 11)
4357 OUTS (outf
, dregs_lo (dst0
));
4358 OUTS (outf
, " = CC = BXOR (A0, ");
4359 OUTS (outf
, dregs (src0
));
4362 else if (sop
== 0 && sopcde
== 12)
4363 OUTS (outf
, "A0 = BXORSHIFT (A0, A1, CC)");
4365 else if (sop
== 1 && sopcde
== 12)
4367 OUTS (outf
, dregs_lo (dst0
));
4368 OUTS (outf
, " = CC = BXOR (A0, A1, CC)");
4370 else if (sop
== 0 && sopcde
== 13)
4372 OUTS (outf
, dregs (dst0
));
4373 OUTS (outf
, " = ALIGN8 (");
4374 OUTS (outf
, dregs (src1
));
4376 OUTS (outf
, dregs (src0
));
4379 else if (sop
== 1 && sopcde
== 13)
4381 OUTS (outf
, dregs (dst0
));
4382 OUTS (outf
, " = ALIGN16 (");
4383 OUTS (outf
, dregs (src1
));
4385 OUTS (outf
, dregs (src0
));
4388 else if (sop
== 2 && sopcde
== 13)
4390 OUTS (outf
, dregs (dst0
));
4391 OUTS (outf
, " = ALIGN24 (");
4392 OUTS (outf
, dregs (src1
));
4394 OUTS (outf
, dregs (src0
));
4404 decode_dsp32shiftimm_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
4407 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4408 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4409 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4410 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4411 int src1
= ((iw1
>> DSP32ShiftImm_src1_bits
) & DSP32ShiftImm_src1_mask
);
4412 int sop
= ((iw1
>> DSP32ShiftImm_sop_bits
) & DSP32ShiftImm_sop_mask
);
4413 int bit8
= ((iw1
>> 8) & 0x1);
4414 int immag
= ((iw1
>> DSP32ShiftImm_immag_bits
) & DSP32ShiftImm_immag_mask
);
4415 int newimmag
= (-(iw1
>> DSP32ShiftImm_immag_bits
) & DSP32ShiftImm_immag_mask
);
4416 int dst0
= ((iw1
>> DSP32ShiftImm_dst0_bits
) & DSP32ShiftImm_dst0_mask
);
4417 int sopcde
= ((iw0
>> (DSP32ShiftImm_sopcde_bits
- 16)) & DSP32ShiftImm_sopcde_mask
);
4418 int HLs
= ((iw1
>> DSP32ShiftImm_HLs_bits
) & DSP32ShiftImm_HLs_mask
);
4421 if (sop
== 0 && sopcde
== 0)
4423 OUTS (outf
, (HLs
& 2) ? dregs_hi (dst0
) : dregs_lo (dst0
));
4425 OUTS (outf
, (HLs
& 1) ? dregs_hi (src1
) : dregs_lo (src1
));
4426 OUTS (outf
, " >>> ");
4427 OUTS (outf
, uimm4 (newimmag
));
4429 else if (sop
== 1 && sopcde
== 0 && bit8
== 0)
4431 OUTS (outf
, (HLs
& 2) ? dregs_hi (dst0
) : dregs_lo (dst0
));
4433 OUTS (outf
, (HLs
& 1) ? dregs_hi (src1
) : dregs_lo (src1
));
4434 OUTS (outf
, " << ");
4435 OUTS (outf
, uimm4 (immag
));
4436 OUTS (outf
, " (S)");
4438 else if (sop
== 1 && sopcde
== 0 && bit8
== 1)
4440 OUTS (outf
, (HLs
& 2) ? dregs_hi (dst0
) : dregs_lo (dst0
));
4442 OUTS (outf
, (HLs
& 1) ? dregs_hi (src1
) : dregs_lo (src1
));
4443 OUTS (outf
, " >>> ");
4444 OUTS (outf
, uimm4 (newimmag
));
4445 OUTS (outf
, " (S)");
4447 else if (sop
== 2 && sopcde
== 0 && bit8
== 0)
4449 OUTS (outf
, (HLs
& 2) ? dregs_hi (dst0
) : dregs_lo (dst0
));
4451 OUTS (outf
, (HLs
& 1) ? dregs_hi (src1
) : dregs_lo (src1
));
4452 OUTS (outf
, " << ");
4453 OUTS (outf
, uimm4 (immag
));
4455 else if (sop
== 2 && sopcde
== 0 && bit8
== 1)
4457 OUTS (outf
, (HLs
& 2) ? dregs_hi (dst0
) : dregs_lo (dst0
));
4459 OUTS (outf
, (HLs
& 1) ? dregs_hi (src1
) : dregs_lo (src1
));
4460 OUTS (outf
, " >> ");
4461 OUTS (outf
, uimm4 (newimmag
));
4463 else if (sop
== 2 && sopcde
== 3 && HLs
== 1)
4465 OUTS (outf
, "A1 = ROT A1 BY ");
4466 OUTS (outf
, imm6 (immag
));
4468 else if (sop
== 0 && sopcde
== 3 && HLs
== 0 && bit8
== 0)
4470 OUTS (outf
, "A0 = A0 << ");
4471 OUTS (outf
, uimm5 (immag
));
4473 else if (sop
== 0 && sopcde
== 3 && HLs
== 0 && bit8
== 1)
4475 OUTS (outf
, "A0 = A0 >>> ");
4476 OUTS (outf
, uimm5 (newimmag
));
4478 else if (sop
== 0 && sopcde
== 3 && HLs
== 1 && bit8
== 0)
4480 OUTS (outf
, "A1 = A1 << ");
4481 OUTS (outf
, uimm5 (immag
));
4483 else if (sop
== 0 && sopcde
== 3 && HLs
== 1 && bit8
== 1)
4485 OUTS (outf
, "A1 = A1 >>> ");
4486 OUTS (outf
, uimm5 (newimmag
));
4488 else if (sop
== 1 && sopcde
== 3 && HLs
== 0)
4490 OUTS (outf
, "A0 = A0 >> ");
4491 OUTS (outf
, uimm5 (newimmag
));
4493 else if (sop
== 1 && sopcde
== 3 && HLs
== 1)
4495 OUTS (outf
, "A1 = A1 >> ");
4496 OUTS (outf
, uimm5 (newimmag
));
4498 else if (sop
== 2 && sopcde
== 3 && HLs
== 0)
4500 OUTS (outf
, "A0 = ROT A0 BY ");
4501 OUTS (outf
, imm6 (immag
));
4503 else if (sop
== 1 && sopcde
== 1 && bit8
== 0)
4505 OUTS (outf
, dregs (dst0
));
4507 OUTS (outf
, dregs (src1
));
4508 OUTS (outf
, " << ");
4509 OUTS (outf
, uimm5 (immag
));
4510 OUTS (outf
, " (V, S)");
4512 else if (sop
== 1 && sopcde
== 1 && bit8
== 1)
4514 OUTS (outf
, dregs (dst0
));
4516 OUTS (outf
, dregs (src1
));
4517 OUTS (outf
, " >>> ");
4518 OUTS (outf
, imm5 (-immag
));
4519 OUTS (outf
, " (V, S)");
4521 else if (sop
== 2 && sopcde
== 1 && bit8
== 1)
4523 OUTS (outf
, dregs (dst0
));
4525 OUTS (outf
, dregs (src1
));
4526 OUTS (outf
, " >> ");
4527 OUTS (outf
, uimm5 (newimmag
));
4528 OUTS (outf
, " (V)");
4530 else if (sop
== 2 && sopcde
== 1 && bit8
== 0)
4532 OUTS (outf
, dregs (dst0
));
4534 OUTS (outf
, dregs (src1
));
4535 OUTS (outf
, " << ");
4536 OUTS (outf
, imm5 (immag
));
4537 OUTS (outf
, " (V)");
4539 else if (sop
== 0 && sopcde
== 1)
4541 OUTS (outf
, dregs (dst0
));
4543 OUTS (outf
, dregs (src1
));
4544 OUTS (outf
, " >>> ");
4545 OUTS (outf
, uimm5 (newimmag
));
4546 OUTS (outf
, " (V)");
4548 else if (sop
== 1 && sopcde
== 2)
4550 OUTS (outf
, dregs (dst0
));
4552 OUTS (outf
, dregs (src1
));
4553 OUTS (outf
, " << ");
4554 OUTS (outf
, uimm5 (immag
));
4555 OUTS (outf
, " (S)");
4557 else if (sop
== 2 && sopcde
== 2 && bit8
== 1)
4559 OUTS (outf
, dregs (dst0
));
4561 OUTS (outf
, dregs (src1
));
4562 OUTS (outf
, " >> ");
4563 OUTS (outf
, uimm5 (newimmag
));
4565 else if (sop
== 2 && sopcde
== 2 && bit8
== 0)
4567 OUTS (outf
, dregs (dst0
));
4569 OUTS (outf
, dregs (src1
));
4570 OUTS (outf
, " << ");
4571 OUTS (outf
, uimm5 (immag
));
4573 else if (sop
== 3 && sopcde
== 2)
4575 OUTS (outf
, dregs (dst0
));
4576 OUTS (outf
, " = ROT ");
4577 OUTS (outf
, dregs (src1
));
4578 OUTS (outf
, " BY ");
4579 OUTS (outf
, imm6 (immag
));
4581 else if (sop
== 0 && sopcde
== 2)
4583 OUTS (outf
, dregs (dst0
));
4585 OUTS (outf
, dregs (src1
));
4586 OUTS (outf
, " >>> ");
4587 OUTS (outf
, uimm5 (newimmag
));
4596 decode_pseudoDEBUG_0 (TIword iw0
, disassemble_info
*outf
)
4599 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4600 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4601 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4602 int fn
= ((iw0
>> PseudoDbg_fn_bits
) & PseudoDbg_fn_mask
);
4603 int grp
= ((iw0
>> PseudoDbg_grp_bits
) & PseudoDbg_grp_mask
);
4604 int reg
= ((iw0
>> PseudoDbg_reg_bits
) & PseudoDbg_reg_mask
);
4609 if (reg
== 0 && fn
== 3)
4610 OUTS (outf
, "DBG A0");
4612 else if (reg
== 1 && fn
== 3)
4613 OUTS (outf
, "DBG A1");
4615 else if (reg
== 3 && fn
== 3)
4616 OUTS (outf
, "ABORT");
4618 else if (reg
== 4 && fn
== 3)
4621 else if (reg
== 5 && fn
== 3)
4622 OUTS (outf
, "DBGHALT");
4624 else if (reg
== 6 && fn
== 3)
4626 OUTS (outf
, "DBGCMPLX (");
4627 OUTS (outf
, dregs (grp
));
4630 else if (reg
== 7 && fn
== 3)
4633 else if (grp
== 0 && fn
== 2)
4635 OUTS (outf
, "OUTC ");
4636 OUTS (outf
, dregs (reg
));
4640 OUTS (outf
, "DBG ");
4641 OUTS (outf
, allregs (reg
, grp
));
4645 OUTS (outf
, "PRNT");
4646 OUTS (outf
, allregs (reg
, grp
));
4655 decode_pseudoOChar_0 (TIword iw0
, disassemble_info
*outf
)
4658 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4659 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4660 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4661 int ch
= ((iw0
>> PseudoChr_ch_bits
) & PseudoChr_ch_mask
);
4666 OUTS (outf
, "OUTC ");
4667 OUTS (outf
, uimm8 (ch
));
4673 decode_pseudodbg_assert_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
4676 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4677 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4678 |.expected......................................................|
4679 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4680 int expected
= ((iw1
>> PseudoDbg_Assert_expected_bits
) & PseudoDbg_Assert_expected_mask
);
4681 int dbgop
= ((iw0
>> (PseudoDbg_Assert_dbgop_bits
- 16)) & PseudoDbg_Assert_dbgop_mask
);
4682 int grp
= ((iw0
>> (PseudoDbg_Assert_grp_bits
- 16)) & PseudoDbg_Assert_grp_mask
);
4683 int regtest
= ((iw0
>> (PseudoDbg_Assert_regtest_bits
- 16)) & PseudoDbg_Assert_regtest_mask
);
4690 OUTS (outf
, "DBGA (");
4691 OUTS (outf
, regs_lo (regtest
, grp
));
4693 OUTS (outf
, uimm16 (expected
));
4696 else if (dbgop
== 1)
4698 OUTS (outf
, "DBGA (");
4699 OUTS (outf
, regs_hi (regtest
, grp
));
4701 OUTS (outf
, uimm16 (expected
));
4704 else if (dbgop
== 2)
4706 OUTS (outf
, "DBGAL (");
4707 OUTS (outf
, allregs (regtest
, grp
));
4709 OUTS (outf
, uimm16 (expected
));
4712 else if (dbgop
== 3)
4714 OUTS (outf
, "DBGAH (");
4715 OUTS (outf
, allregs (regtest
, grp
));
4717 OUTS (outf
, uimm16 (expected
));
4726 _print_insn_bfin (bfd_vma pc
, disassemble_info
*outf
)
4734 status
= (*outf
->read_memory_func
) (pc
& ~0x1, buf
, 2, outf
);
4737 status
= (*outf
->read_memory_func
) ((pc
+ 2) & ~0x1, buf
+ 2, 2, outf
);
4741 iw0
= bfd_getl16 (buf
);
4742 iw1
= bfd_getl16 (buf
+ 2);
4744 if ((iw0
& 0xf7ff) == 0xc003 && iw1
== 0x1800)
4748 OUTS (outf
, "ILLEGAL");
4751 OUTS (outf
, "MNOP");
4754 else if ((iw0
& 0xff00) == 0x0000)
4755 rv
= decode_ProgCtrl_0 (iw0
, outf
);
4756 else if ((iw0
& 0xffc0) == 0x0240)
4757 rv
= decode_CaCTRL_0 (iw0
, outf
);
4758 else if ((iw0
& 0xff80) == 0x0100)
4759 rv
= decode_PushPopReg_0 (iw0
, outf
);
4760 else if ((iw0
& 0xfe00) == 0x0400)
4761 rv
= decode_PushPopMultiple_0 (iw0
, outf
);
4762 else if ((iw0
& 0xfe00) == 0x0600)
4763 rv
= decode_ccMV_0 (iw0
, outf
);
4764 else if ((iw0
& 0xf800) == 0x0800)
4765 rv
= decode_CCflag_0 (iw0
, outf
);
4766 else if ((iw0
& 0xffe0) == 0x0200)
4767 rv
= decode_CC2dreg_0 (iw0
, outf
);
4768 else if ((iw0
& 0xff00) == 0x0300)
4769 rv
= decode_CC2stat_0 (iw0
, outf
);
4770 else if ((iw0
& 0xf000) == 0x1000)
4771 rv
= decode_BRCC_0 (iw0
, pc
, outf
);
4772 else if ((iw0
& 0xf000) == 0x2000)
4773 rv
= decode_UJUMP_0 (iw0
, pc
, outf
);
4774 else if ((iw0
& 0xf000) == 0x3000)
4775 rv
= decode_REGMV_0 (iw0
, outf
);
4776 else if ((iw0
& 0xfc00) == 0x4000)
4777 rv
= decode_ALU2op_0 (iw0
, outf
);
4778 else if ((iw0
& 0xfe00) == 0x4400)
4779 rv
= decode_PTR2op_0 (iw0
, outf
);
4780 else if ((iw0
& 0xf800) == 0x4800)
4781 rv
= decode_LOGI2op_0 (iw0
, outf
);
4782 else if ((iw0
& 0xf000) == 0x5000)
4783 rv
= decode_COMP3op_0 (iw0
, outf
);
4784 else if ((iw0
& 0xf800) == 0x6000)
4785 rv
= decode_COMPI2opD_0 (iw0
, outf
);
4786 else if ((iw0
& 0xf800) == 0x6800)
4787 rv
= decode_COMPI2opP_0 (iw0
, outf
);
4788 else if ((iw0
& 0xf000) == 0x8000)
4789 rv
= decode_LDSTpmod_0 (iw0
, outf
);
4790 else if ((iw0
& 0xff60) == 0x9e60)
4791 rv
= decode_dagMODim_0 (iw0
, outf
);
4792 else if ((iw0
& 0xfff0) == 0x9f60)
4793 rv
= decode_dagMODik_0 (iw0
, outf
);
4794 else if ((iw0
& 0xfc00) == 0x9c00)
4795 rv
= decode_dspLDST_0 (iw0
, outf
);
4796 else if ((iw0
& 0xf000) == 0x9000)
4797 rv
= decode_LDST_0 (iw0
, outf
);
4798 else if ((iw0
& 0xfc00) == 0xb800)
4799 rv
= decode_LDSTiiFP_0 (iw0
, outf
);
4800 else if ((iw0
& 0xe000) == 0xA000)
4801 rv
= decode_LDSTii_0 (iw0
, outf
);
4802 else if ((iw0
& 0xff80) == 0xe080 && (iw1
& 0x0C00) == 0x0000)
4803 rv
= decode_LoopSetup_0 (iw0
, iw1
, pc
, outf
);
4804 else if ((iw0
& 0xff00) == 0xe100 && (iw1
& 0x0000) == 0x0000)
4805 rv
= decode_LDIMMhalf_0 (iw0
, iw1
, outf
);
4806 else if ((iw0
& 0xfe00) == 0xe200 && (iw1
& 0x0000) == 0x0000)
4807 rv
= decode_CALLa_0 (iw0
, iw1
, pc
, outf
);
4808 else if ((iw0
& 0xfc00) == 0xe400 && (iw1
& 0x0000) == 0x0000)
4809 rv
= decode_LDSTidxI_0 (iw0
, iw1
, outf
);
4810 else if ((iw0
& 0xfffe) == 0xe800 && (iw1
& 0x0000) == 0x0000)
4811 rv
= decode_linkage_0 (iw0
, iw1
, outf
);
4812 else if ((iw0
& 0xf600) == 0xc000 && (iw1
& 0x0000) == 0x0000)
4813 rv
= decode_dsp32mac_0 (iw0
, iw1
, outf
);
4814 else if ((iw0
& 0xf600) == 0xc200 && (iw1
& 0x0000) == 0x0000)
4815 rv
= decode_dsp32mult_0 (iw0
, iw1
, outf
);
4816 else if ((iw0
& 0xf7c0) == 0xc400 && (iw1
& 0x0000) == 0x0000)
4817 rv
= decode_dsp32alu_0 (iw0
, iw1
, outf
);
4818 else if ((iw0
& 0xf780) == 0xc600 && (iw1
& 0x01c0) == 0x0000)
4819 rv
= decode_dsp32shift_0 (iw0
, iw1
, outf
);
4820 else if ((iw0
& 0xf780) == 0xc680 && (iw1
& 0x0000) == 0x0000)
4821 rv
= decode_dsp32shiftimm_0 (iw0
, iw1
, outf
);
4822 else if ((iw0
& 0xff00) == 0xf800)
4823 rv
= decode_pseudoDEBUG_0 (iw0
, outf
);
4824 else if ((iw0
& 0xFF00) == 0xF900)
4825 rv
= decode_pseudoOChar_0 (iw0
, outf
);
4826 else if ((iw0
& 0xFF00) == 0xf000 && (iw1
& 0x0000) == 0x0000)
4827 rv
= decode_pseudodbg_assert_0 (iw0
, iw1
, outf
);
4830 OUTS (outf
, "ILLEGAL");
4837 print_insn_bfin (bfd_vma pc
, disassemble_info
*outf
)
4844 status
= (*outf
->read_memory_func
) (pc
& ~0x01, buf
, 2, outf
);
4847 iw0
= bfd_getl16 (buf
);
4849 count
+= _print_insn_bfin (pc
, outf
);
4851 /* Proper display of multiple issue instructions. */
4853 if (count
== 4 && (iw0
& 0xc000) == 0xc000 && (iw0
& BIT_MULTI_INS
)
4854 && ((iw0
& 0xe800) != 0xe800 /* Not Linkage. */ ))
4860 outf
->fprintf_func (outf
->stream
, " || ");
4861 len
= _print_insn_bfin (pc
+ 4, outf
);
4862 outf
->fprintf_func (outf
->stream
, " || ");
4865 len
= _print_insn_bfin (pc
+ 6, outf
);
4873 outf
->fprintf_func (outf
->stream
, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
4881 outf
->fprintf_func (outf
->stream
, ";");