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[deliverable/binutils-gdb.git] / opcodes / bfin-dis.c
1 /* Disassemble ADI Blackfin Instructions.
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
3
4 This file is part of libopcodes.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21 #include <stdio.h>
22 #include <stdlib.h>
23 #include <string.h>
24
25 #include "opcode/bfin.h"
26
27 #define M_S2RND 1
28 #define M_T 2
29 #define M_W32 3
30 #define M_FU 4
31 #define M_TFU 6
32 #define M_IS 8
33 #define M_ISS2 9
34 #define M_IH 11
35 #define M_IU 12
36
37 #ifndef PRINTF
38 #define PRINTF printf
39 #endif
40
41 #ifndef EXIT
42 #define EXIT exit
43 #endif
44
45 typedef long TIword;
46
47 #define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
48 #define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
49 #define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
50 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
51
52 #include "dis-asm.h"
53
54 typedef unsigned int bu32;
55
56 static char comment = 0;
57 static char parallel = 0;
58
59 typedef enum
60 {
61 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
62 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
63 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
64 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
65 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
66 } const_forms_t;
67
68 static const struct
69 {
70 const char *name;
71 const int nbits;
72 const char reloc;
73 const char issigned;
74 const char pcrel;
75 const char scale;
76 const char offset;
77 const char negative;
78 const char positive;
79 const char decimal;
80 const char leading;
81 const char exact;
82 } constant_formats[] =
83 {
84 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
85 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
86 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
88 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
89 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
91 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
92 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
94 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
95 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
97 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
98 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
99 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
100 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
101 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
102 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
103 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
104 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
107 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
108 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
109 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
110 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
111 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
112 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
113 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
114 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
118 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
119 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
120 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
121 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
122 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
123 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
124 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
125 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
126 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
127 };
128
129 static const char *
130 fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
131 {
132 static char buf[60];
133
134 if (constant_formats[cf].reloc)
135 {
136 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
137 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
138 if (constant_formats[cf].pcrel)
139 ea += pc;
140
141 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
142 {
143 outf->print_address_func (ea, outf);
144 return "";
145 }
146 else
147 {
148 sprintf (buf, "%lx", (unsigned long) x);
149 return buf;
150 }
151 }
152
153 /* Negative constants have an implied sign bit. */
154 if (constant_formats[cf].negative)
155 {
156 int nb = constant_formats[cf].nbits + 1;
157
158 x = x | (1 << constant_formats[cf].nbits);
159 x = SIGNEXTEND (x, nb);
160 }
161 else
162 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
163
164 if (constant_formats[cf].offset)
165 x += constant_formats[cf].offset;
166
167 if (constant_formats[cf].scale)
168 x <<= constant_formats[cf].scale;
169
170 if (constant_formats[cf].decimal)
171 {
172 if (constant_formats[cf].leading)
173 {
174 char ps[10];
175 sprintf (ps, "%%%ii", constant_formats[cf].leading);
176 sprintf (buf, ps, x);
177 }
178 else
179 sprintf (buf, "%li", x);
180 }
181 else
182 {
183 if (constant_formats[cf].issigned && x < 0)
184 sprintf (buf, "-0x%x", abs (x));
185 else
186 sprintf (buf, "0x%lx", (unsigned long) x);
187 }
188
189 return buf;
190 }
191
192 static bu32
193 fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
194 {
195 if (0 && constant_formats[cf].reloc)
196 {
197 bu32 ea = (((constant_formats[cf].pcrel
198 ? SIGNEXTEND (x, constant_formats[cf].nbits)
199 : x) + constant_formats[cf].offset)
200 << constant_formats[cf].scale);
201 if (constant_formats[cf].pcrel)
202 ea += pc;
203
204 return ea;
205 }
206
207 /* Negative constants have an implied sign bit. */
208 if (constant_formats[cf].negative)
209 {
210 int nb = constant_formats[cf].nbits + 1;
211 x = x | (1 << constant_formats[cf].nbits);
212 x = SIGNEXTEND (x, nb);
213 }
214 else if (constant_formats[cf].issigned)
215 x = SIGNEXTEND (x, constant_formats[cf].nbits);
216
217 x += constant_formats[cf].offset;
218 x <<= constant_formats[cf].scale;
219
220 return x;
221 }
222
223 enum machine_registers
224 {
225 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
226 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
227 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
228 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
229 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
230 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
231 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
232 REG_L2, REG_L3,
233 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
234 REG_AQ, REG_V, REG_VS,
235 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
236 REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
237 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
238 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
239 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
240 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
241 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
242 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
243 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
244 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
245 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
246 REG_LASTREG,
247 };
248
249 enum reg_class
250 {
251 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
252 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
253 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
254 rc_sysregs3, rc_allregs,
255 LIM_REG_CLASSES
256 };
257
258 static const char *reg_names[] =
259 {
260 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
261 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
262 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
263 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
264 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
265 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
266 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
267 "L2", "L3",
268 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
269 "AQ", "V", "VS",
270 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
271 "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
272 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
273 "RETE", "EMUDAT",
274 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
275 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
276 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
277 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
278 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
279 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
280 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
281 "AC0_COPY", "V_COPY", "RND_MOD",
282 "LASTREG",
283 0
284 };
285
286 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
287
288 /* RL(0..7). */
289 static enum machine_registers decode_dregs_lo[] =
290 {
291 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
292 };
293
294 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
295
296 /* RH(0..7). */
297 static enum machine_registers decode_dregs_hi[] =
298 {
299 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
300 };
301
302 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
303
304 /* R(0..7). */
305 static enum machine_registers decode_dregs[] =
306 {
307 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
308 };
309
310 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
311
312 /* R BYTE(0..7). */
313 static enum machine_registers decode_dregs_byte[] =
314 {
315 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
316 };
317
318 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
319
320 /* P(0..5) SP FP. */
321 static enum machine_registers decode_pregs[] =
322 {
323 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
324 };
325
326 #define pregs(x) REGNAME (decode_pregs[(x) & 7])
327 #define spfp(x) REGNAME (decode_spfp[(x) & 1])
328 #define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
329 #define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
330 #define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
331 #define accum(x) REGNAME (decode_accum[(x) & 1])
332
333 /* I(0..3). */
334 static enum machine_registers decode_iregs[] =
335 {
336 REG_I0, REG_I1, REG_I2, REG_I3,
337 };
338
339 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
340
341 /* M(0..3). */
342 static enum machine_registers decode_mregs[] =
343 {
344 REG_M0, REG_M1, REG_M2, REG_M3,
345 };
346
347 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
348 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
349 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
350
351 /* dregs pregs. */
352 static enum machine_registers decode_dpregs[] =
353 {
354 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
355 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
356 };
357
358 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
359
360 /* [dregs pregs]. */
361 static enum machine_registers decode_gregs[] =
362 {
363 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
364 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
365 };
366
367 #define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
368
369 /* [dregs pregs (iregs mregs) (bregs lregs)]. */
370 static enum machine_registers decode_regs[] =
371 {
372 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
373 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
374 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
375 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
376 };
377
378 #define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
379
380 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
381 static enum machine_registers decode_regs_lo[] =
382 {
383 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
384 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
385 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
386 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
387 };
388
389 #define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
390 /* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
391 static enum machine_registers decode_regs_hi[] =
392 {
393 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
394 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
395 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
396 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
397 };
398
399 #define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
400
401 static enum machine_registers decode_statbits[] =
402 {
403 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
404 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
405 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
406 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
407 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
408 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
409 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
410 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
411 };
412
413 #define statbits(x) REGNAME (decode_statbits[(x) & 31])
414
415 /* LC0 LC1. */
416 static enum machine_registers decode_counters[] =
417 {
418 REG_LC0, REG_LC1,
419 };
420
421 #define counters(x) REGNAME (decode_counters[(x) & 1])
422 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
423
424 /* [dregs pregs (iregs mregs) (bregs lregs)
425 dregs2_sysregs1 open sysregs2 sysregs3]. */
426 static enum machine_registers decode_allregs[] =
427 {
428 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
429 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
430 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
431 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
432 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
433 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
434 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
435 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
436 REG_LASTREG,
437 };
438
439 #define IS_DREG(g,r) ((g) == 0 && (r) < 8)
440 #define IS_PREG(g,r) ((g) == 1 && (r) < 8)
441 #define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
442 #define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
443 #define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
444 #define IS_SYSREG(g,r) \
445 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
446 #define IS_RESERVEDREG(g,r) \
447 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
448
449 #define allreg(r,g) (!IS_RESERVEDREG (g, r))
450 #define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
451
452 #define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
453 #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
454 #define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
455 #define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
456 #define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
457 #define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
458 #define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
459 #define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
460 #define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
461 #define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
462 #define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
463 #define imm16(x) fmtconst (c_imm16, x, 0, outf)
464 #define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
465 #define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
466 #define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
467 #define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
468 #define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
469 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
470 #define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
471 #define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
472 #define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
473 #define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
474 #define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
475 #define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
476 #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
477 #define imm3(x) fmtconst (c_imm3, x, 0, outf)
478 #define imm4(x) fmtconst (c_imm4, x, 0, outf)
479 #define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
480 #define imm5(x) fmtconst (c_imm5, x, 0, outf)
481 #define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
482 #define imm6(x) fmtconst (c_imm6, x, 0, outf)
483 #define imm7(x) fmtconst (c_imm7, x, 0, outf)
484 #define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
485 #define imm8(x) fmtconst (c_imm8, x, 0, outf)
486 #define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
487 #define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
488 #define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
489 #define imm32(x) fmtconst (c_imm32, x, 0, outf)
490 #define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
491 #define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
492 #define imm7_val(x) fmtconst_val (c_imm7, x, 0)
493 #define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
494 #define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
495
496 /* (arch.pm)arch_disassembler_functions. */
497 #ifndef OUTS
498 #define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
499 #endif
500
501 static void
502 amod0 (int s0, int x0, disassemble_info *outf)
503 {
504 if (s0 == 1 && x0 == 0)
505 OUTS (outf, " (S)");
506 else if (s0 == 0 && x0 == 1)
507 OUTS (outf, " (CO)");
508 else if (s0 == 1 && x0 == 1)
509 OUTS (outf, " (SCO)");
510 }
511
512 static void
513 amod1 (int s0, int x0, disassemble_info *outf)
514 {
515 if (s0 == 0 && x0 == 0)
516 OUTS (outf, " (NS)");
517 else if (s0 == 1 && x0 == 0)
518 OUTS (outf, " (S)");
519 }
520
521 static void
522 amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
523 {
524 if (s0 == 1 && x0 == 0 && aop0 == 0)
525 OUTS (outf, " (S)");
526 else if (s0 == 0 && x0 == 1 && aop0 == 0)
527 OUTS (outf, " (CO)");
528 else if (s0 == 1 && x0 == 1 && aop0 == 0)
529 OUTS (outf, " (SCO)");
530 else if (s0 == 0 && x0 == 0 && aop0 == 2)
531 OUTS (outf, " (ASR)");
532 else if (s0 == 1 && x0 == 0 && aop0 == 2)
533 OUTS (outf, " (S, ASR)");
534 else if (s0 == 0 && x0 == 1 && aop0 == 2)
535 OUTS (outf, " (CO, ASR)");
536 else if (s0 == 1 && x0 == 1 && aop0 == 2)
537 OUTS (outf, " (SCO, ASR)");
538 else if (s0 == 0 && x0 == 0 && aop0 == 3)
539 OUTS (outf, " (ASL)");
540 else if (s0 == 1 && x0 == 0 && aop0 == 3)
541 OUTS (outf, " (S, ASL)");
542 else if (s0 == 0 && x0 == 1 && aop0 == 3)
543 OUTS (outf, " (CO, ASL)");
544 else if (s0 == 1 && x0 == 1 && aop0 == 3)
545 OUTS (outf, " (SCO, ASL)");
546 }
547
548 static void
549 searchmod (int r0, disassemble_info *outf)
550 {
551 if (r0 == 0)
552 OUTS (outf, "GT");
553 else if (r0 == 1)
554 OUTS (outf, "GE");
555 else if (r0 == 2)
556 OUTS (outf, "LT");
557 else if (r0 == 3)
558 OUTS (outf, "LE");
559 }
560
561 static void
562 aligndir (int r0, disassemble_info *outf)
563 {
564 if (r0 == 1)
565 OUTS (outf, " (R)");
566 }
567
568 static int
569 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
570 {
571 const char *s0, *s1;
572
573 if (h0)
574 s0 = dregs_hi (src0);
575 else
576 s0 = dregs_lo (src0);
577
578 if (h1)
579 s1 = dregs_hi (src1);
580 else
581 s1 = dregs_lo (src1);
582
583 OUTS (outf, s0);
584 OUTS (outf, " * ");
585 OUTS (outf, s1);
586 return 0;
587 }
588
589 static int
590 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf)
591 {
592 const char *a;
593 const char *sop = "<unknown op>";
594
595 if (which)
596 a = "A1";
597 else
598 a = "A0";
599
600 if (op == 3)
601 {
602 OUTS (outf, a);
603 return 0;
604 }
605
606 switch (op)
607 {
608 case 0: sop = " = "; break;
609 case 1: sop = " += "; break;
610 case 2: sop = " -= "; break;
611 default: break;
612 }
613
614 OUTS (outf, a);
615 OUTS (outf, sop);
616 decode_multfunc (h0, h1, src0, src1, outf);
617
618 return 0;
619 }
620
621 static void
622 decode_optmode (int mod, int MM, disassemble_info *outf)
623 {
624 if (mod == 0 && MM == 0)
625 return;
626
627 OUTS (outf, " (");
628
629 if (MM && !mod)
630 {
631 OUTS (outf, "M)");
632 return;
633 }
634
635 if (MM)
636 OUTS (outf, "M, ");
637
638 if (mod == M_S2RND)
639 OUTS (outf, "S2RND");
640 else if (mod == M_T)
641 OUTS (outf, "T");
642 else if (mod == M_W32)
643 OUTS (outf, "W32");
644 else if (mod == M_FU)
645 OUTS (outf, "FU");
646 else if (mod == M_TFU)
647 OUTS (outf, "TFU");
648 else if (mod == M_IS)
649 OUTS (outf, "IS");
650 else if (mod == M_ISS2)
651 OUTS (outf, "ISS2");
652 else if (mod == M_IH)
653 OUTS (outf, "IH");
654 else if (mod == M_IU)
655 OUTS (outf, "IU");
656 else
657 abort ();
658
659 OUTS (outf, ")");
660 }
661
662 struct saved_state
663 {
664 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
665 bu32 a0x, a0w, a1x, a1w;
666 bu32 lt[2], lc[2], lb[2];
667 int ac0, ac0_copy, ac1, an, aq;
668 int av0, av0s, av1, av1s, az, cc, v, v_copy, vs;
669 int rnd_mod;
670 int v_internal;
671 bu32 pc, rets;
672
673 int ticks;
674 int insts;
675
676 int exception;
677
678 int end_of_registers;
679
680 int msize;
681 unsigned char *memory;
682 unsigned long bfd_mach;
683 } saved_state;
684
685 #define DREG(x) (saved_state.dpregs[x])
686 #define GREG(x,i) DPREG ((x) | (i << 3))
687 #define DPREG(x) (saved_state.dpregs[x])
688 #define DREG(x) (saved_state.dpregs[x])
689 #define PREG(x) (saved_state.dpregs[x + 8])
690 #define SPREG PREG (6)
691 #define FPREG PREG (7)
692 #define IREG(x) (saved_state.iregs[x])
693 #define MREG(x) (saved_state.mregs[x])
694 #define BREG(x) (saved_state.bregs[x])
695 #define LREG(x) (saved_state.lregs[x])
696 #define A0XREG (saved_state.a0x)
697 #define A0WREG (saved_state.a0w)
698 #define A1XREG (saved_state.a1x)
699 #define A1WREG (saved_state.a1w)
700 #define CCREG (saved_state.cc)
701 #define LC0REG (saved_state.lc[0])
702 #define LT0REG (saved_state.lt[0])
703 #define LB0REG (saved_state.lb[0])
704 #define LC1REG (saved_state.lc[1])
705 #define LT1REG (saved_state.lt[1])
706 #define LB1REG (saved_state.lb[1])
707 #define RETSREG (saved_state.rets)
708 #define PCREG (saved_state.pc)
709
710 static bu32 *
711 get_allreg (int grp, int reg)
712 {
713 int fullreg = (grp << 3) | reg;
714 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
715 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
716 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
717 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
718 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
719 , , , , , , , ,
720 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
721 REG_CYCLES2,
722 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
723 REG_LASTREG */
724 switch (fullreg >> 2)
725 {
726 case 0: case 1: return &DREG (reg); break;
727 case 2: case 3: return &PREG (reg); break;
728 case 4: return &IREG (reg & 3); break;
729 case 5: return &MREG (reg & 3); break;
730 case 6: return &BREG (reg & 3); break;
731 case 7: return &LREG (reg & 3); break;
732 default:
733 switch (fullreg)
734 {
735 case 32: return &saved_state.a0x;
736 case 33: return &saved_state.a0w;
737 case 34: return &saved_state.a1x;
738 case 35: return &saved_state.a1w;
739 case 39: return &saved_state.rets;
740 case 48: return &LC0REG;
741 case 49: return &LT0REG;
742 case 50: return &LB0REG;
743 case 51: return &LC1REG;
744 case 52: return &LT1REG;
745 case 53: return &LB1REG;
746 }
747 return 0;
748 }
749 }
750
751 static int
752 decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
753 {
754 /* ProgCtrl
755 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
756 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
757 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
758 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
759 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
760
761 if (prgfunc == 0 && poprnd == 0)
762 OUTS (outf, "NOP");
763 else if (prgfunc == 1 && poprnd == 0)
764 OUTS (outf, "RTS");
765 else if (prgfunc == 1 && poprnd == 1)
766 OUTS (outf, "RTI");
767 else if (prgfunc == 1 && poprnd == 2)
768 OUTS (outf, "RTX");
769 else if (prgfunc == 1 && poprnd == 3)
770 OUTS (outf, "RTN");
771 else if (prgfunc == 1 && poprnd == 4)
772 OUTS (outf, "RTE");
773 else if (prgfunc == 2 && poprnd == 0)
774 OUTS (outf, "IDLE");
775 else if (prgfunc == 2 && poprnd == 3)
776 OUTS (outf, "CSYNC");
777 else if (prgfunc == 2 && poprnd == 4)
778 OUTS (outf, "SSYNC");
779 else if (prgfunc == 2 && poprnd == 5)
780 OUTS (outf, "EMUEXCPT");
781 else if (prgfunc == 3 && IS_DREG (0, poprnd))
782 {
783 OUTS (outf, "CLI ");
784 OUTS (outf, dregs (poprnd));
785 }
786 else if (prgfunc == 4 && IS_DREG (0, poprnd))
787 {
788 OUTS (outf, "STI ");
789 OUTS (outf, dregs (poprnd));
790 }
791 else if (prgfunc == 5 && IS_PREG (1, poprnd))
792 {
793 OUTS (outf, "JUMP (");
794 OUTS (outf, pregs (poprnd));
795 OUTS (outf, ")");
796 }
797 else if (prgfunc == 6 && IS_PREG (1, poprnd))
798 {
799 OUTS (outf, "CALL (");
800 OUTS (outf, pregs (poprnd));
801 OUTS (outf, ")");
802 }
803 else if (prgfunc == 7 && IS_PREG (1, poprnd))
804 {
805 OUTS (outf, "CALL (PC + ");
806 OUTS (outf, pregs (poprnd));
807 OUTS (outf, ")");
808 }
809 else if (prgfunc == 8 && IS_PREG (1, poprnd))
810 {
811 OUTS (outf, "JUMP (PC + ");
812 OUTS (outf, pregs (poprnd));
813 OUTS (outf, ")");
814 }
815 else if (prgfunc == 9)
816 {
817 OUTS (outf, "RAISE ");
818 OUTS (outf, uimm4 (poprnd));
819 }
820 else if (prgfunc == 10)
821 {
822 OUTS (outf, "EXCPT ");
823 OUTS (outf, uimm4 (poprnd));
824 }
825 else if (prgfunc == 11 && IS_PREG (1, poprnd))
826 {
827 OUTS (outf, "TESTSET (");
828 OUTS (outf, pregs (poprnd));
829 OUTS (outf, ")");
830 }
831 else
832 return 0;
833 return 2;
834 }
835
836 static int
837 decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
838 {
839 /* CaCTRL
840 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
841 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
842 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
843 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
844 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
845 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
846
847 if (a == 0 && op == 0)
848 {
849 OUTS (outf, "PREFETCH[");
850 OUTS (outf, pregs (reg));
851 OUTS (outf, "]");
852 }
853 else if (a == 0 && op == 1)
854 {
855 OUTS (outf, "FLUSHINV[");
856 OUTS (outf, pregs (reg));
857 OUTS (outf, "]");
858 }
859 else if (a == 0 && op == 2)
860 {
861 OUTS (outf, "FLUSH[");
862 OUTS (outf, pregs (reg));
863 OUTS (outf, "]");
864 }
865 else if (a == 0 && op == 3)
866 {
867 OUTS (outf, "IFLUSH[");
868 OUTS (outf, pregs (reg));
869 OUTS (outf, "]");
870 }
871 else if (a == 1 && op == 0)
872 {
873 OUTS (outf, "PREFETCH[");
874 OUTS (outf, pregs (reg));
875 OUTS (outf, "++]");
876 }
877 else if (a == 1 && op == 1)
878 {
879 OUTS (outf, "FLUSHINV[");
880 OUTS (outf, pregs (reg));
881 OUTS (outf, "++]");
882 }
883 else if (a == 1 && op == 2)
884 {
885 OUTS (outf, "FLUSH[");
886 OUTS (outf, pregs (reg));
887 OUTS (outf, "++]");
888 }
889 else if (a == 1 && op == 3)
890 {
891 OUTS (outf, "IFLUSH[");
892 OUTS (outf, pregs (reg));
893 OUTS (outf, "++]");
894 }
895 else
896 return 0;
897 return 2;
898 }
899
900 static int
901 decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
902 {
903 /* PushPopReg
904 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
905 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
906 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
907 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
908 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
909 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
910
911 if (W == 0 && mostreg (reg, grp))
912 {
913 OUTS (outf, allregs (reg, grp));
914 OUTS (outf, " = [SP++]");
915 }
916 else if (W == 1 && allreg (reg, grp))
917 {
918 OUTS (outf, "[--SP] = ");
919 OUTS (outf, allregs (reg, grp));
920 }
921 else
922 return 0;
923 return 2;
924 }
925
926 static int
927 decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
928 {
929 /* PushPopMultiple
930 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
931 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
932 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
933 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
934 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
935 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
936 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
937 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
938
939 if (W == 1 && d == 1 && p == 1)
940 {
941 OUTS (outf, "[--SP] = (R7:");
942 OUTS (outf, imm5d (dr));
943 OUTS (outf, ", P5:");
944 OUTS (outf, imm5d (pr));
945 OUTS (outf, ")");
946 }
947 else if (W == 1 && d == 1 && p == 0)
948 {
949 OUTS (outf, "[--SP] = (R7:");
950 OUTS (outf, imm5d (dr));
951 OUTS (outf, ")");
952 }
953 else if (W == 1 && d == 0 && p == 1)
954 {
955 OUTS (outf, "[--SP] = (P5:");
956 OUTS (outf, imm5d (pr));
957 OUTS (outf, ")");
958 }
959 else if (W == 0 && d == 1 && p == 1)
960 {
961 OUTS (outf, "(R7:");
962 OUTS (outf, imm5d (dr));
963 OUTS (outf, ", P5:");
964 OUTS (outf, imm5d (pr));
965 OUTS (outf, ") = [SP++]");
966 }
967 else if (W == 0 && d == 1 && p == 0)
968 {
969 OUTS (outf, "(R7:");
970 OUTS (outf, imm5d (dr));
971 OUTS (outf, ") = [SP++]");
972 }
973 else if (W == 0 && d == 0 && p == 1)
974 {
975 OUTS (outf, "(P5:");
976 OUTS (outf, imm5d (pr));
977 OUTS (outf, ") = [SP++]");
978 }
979 else
980 return 0;
981 return 2;
982 }
983
984 static int
985 decode_ccMV_0 (TIword iw0, disassemble_info *outf)
986 {
987 /* ccMV
988 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
989 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
990 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
991 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
992 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
993 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
994 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
995 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
996
997 if (T == 1)
998 {
999 OUTS (outf, "IF CC ");
1000 OUTS (outf, gregs (dst, d));
1001 OUTS (outf, " = ");
1002 OUTS (outf, gregs (src, s));
1003 }
1004 else if (T == 0)
1005 {
1006 OUTS (outf, "IF !CC ");
1007 OUTS (outf, gregs (dst, d));
1008 OUTS (outf, " = ");
1009 OUTS (outf, gregs (src, s));
1010 }
1011 else
1012 return 0;
1013 return 2;
1014 }
1015
1016 static int
1017 decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1018 {
1019 /* CCflag
1020 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1021 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1022 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1023 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1024 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1025 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1026 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1027 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1028
1029 if (opc == 0 && I == 0 && G == 0)
1030 {
1031 OUTS (outf, "CC = ");
1032 OUTS (outf, dregs (x));
1033 OUTS (outf, " == ");
1034 OUTS (outf, dregs (y));
1035 }
1036 else if (opc == 1 && I == 0 && G == 0)
1037 {
1038 OUTS (outf, "CC = ");
1039 OUTS (outf, dregs (x));
1040 OUTS (outf, " < ");
1041 OUTS (outf, dregs (y));
1042 }
1043 else if (opc == 2 && I == 0 && G == 0)
1044 {
1045 OUTS (outf, "CC = ");
1046 OUTS (outf, dregs (x));
1047 OUTS (outf, " <= ");
1048 OUTS (outf, dregs (y));
1049 }
1050 else if (opc == 3 && I == 0 && G == 0)
1051 {
1052 OUTS (outf, "CC = ");
1053 OUTS (outf, dregs (x));
1054 OUTS (outf, " < ");
1055 OUTS (outf, dregs (y));
1056 OUTS (outf, " (IU)");
1057 }
1058 else if (opc == 4 && I == 0 && G == 0)
1059 {
1060 OUTS (outf, "CC = ");
1061 OUTS (outf, dregs (x));
1062 OUTS (outf, " <= ");
1063 OUTS (outf, dregs (y));
1064 OUTS (outf, " (IU)");
1065 }
1066 else if (opc == 0 && I == 1 && G == 0)
1067 {
1068 OUTS (outf, "CC = ");
1069 OUTS (outf, dregs (x));
1070 OUTS (outf, " == ");
1071 OUTS (outf, imm3 (y));
1072 }
1073 else if (opc == 1 && I == 1 && G == 0)
1074 {
1075 OUTS (outf, "CC = ");
1076 OUTS (outf, dregs (x));
1077 OUTS (outf, " < ");
1078 OUTS (outf, imm3 (y));
1079 }
1080 else if (opc == 2 && I == 1 && G == 0)
1081 {
1082 OUTS (outf, "CC = ");
1083 OUTS (outf, dregs (x));
1084 OUTS (outf, " <= ");
1085 OUTS (outf, imm3 (y));
1086 }
1087 else if (opc == 3 && I == 1 && G == 0)
1088 {
1089 OUTS (outf, "CC = ");
1090 OUTS (outf, dregs (x));
1091 OUTS (outf, " < ");
1092 OUTS (outf, uimm3 (y));
1093 OUTS (outf, " (IU)");
1094 }
1095 else if (opc == 4 && I == 1 && G == 0)
1096 {
1097 OUTS (outf, "CC = ");
1098 OUTS (outf, dregs (x));
1099 OUTS (outf, " <= ");
1100 OUTS (outf, uimm3 (y));
1101 OUTS (outf, " (IU)");
1102 }
1103 else if (opc == 0 && I == 0 && G == 1)
1104 {
1105 OUTS (outf, "CC = ");
1106 OUTS (outf, pregs (x));
1107 OUTS (outf, " == ");
1108 OUTS (outf, pregs (y));
1109 }
1110 else if (opc == 1 && I == 0 && G == 1)
1111 {
1112 OUTS (outf, "CC = ");
1113 OUTS (outf, pregs (x));
1114 OUTS (outf, " < ");
1115 OUTS (outf, pregs (y));
1116 }
1117 else if (opc == 2 && I == 0 && G == 1)
1118 {
1119 OUTS (outf, "CC = ");
1120 OUTS (outf, pregs (x));
1121 OUTS (outf, " <= ");
1122 OUTS (outf, pregs (y));
1123 }
1124 else if (opc == 3 && I == 0 && G == 1)
1125 {
1126 OUTS (outf, "CC = ");
1127 OUTS (outf, pregs (x));
1128 OUTS (outf, " < ");
1129 OUTS (outf, pregs (y));
1130 OUTS (outf, " (IU)");
1131 }
1132 else if (opc == 4 && I == 0 && G == 1)
1133 {
1134 OUTS (outf, "CC = ");
1135 OUTS (outf, pregs (x));
1136 OUTS (outf, " <= ");
1137 OUTS (outf, pregs (y));
1138 OUTS (outf, " (IU)");
1139 }
1140 else if (opc == 0 && I == 1 && G == 1)
1141 {
1142 OUTS (outf, "CC = ");
1143 OUTS (outf, pregs (x));
1144 OUTS (outf, " == ");
1145 OUTS (outf, imm3 (y));
1146 }
1147 else if (opc == 1 && I == 1 && G == 1)
1148 {
1149 OUTS (outf, "CC = ");
1150 OUTS (outf, pregs (x));
1151 OUTS (outf, " < ");
1152 OUTS (outf, imm3 (y));
1153 }
1154 else if (opc == 2 && I == 1 && G == 1)
1155 {
1156 OUTS (outf, "CC = ");
1157 OUTS (outf, pregs (x));
1158 OUTS (outf, " <= ");
1159 OUTS (outf, imm3 (y));
1160 }
1161 else if (opc == 3 && I == 1 && G == 1)
1162 {
1163 OUTS (outf, "CC = ");
1164 OUTS (outf, pregs (x));
1165 OUTS (outf, " < ");
1166 OUTS (outf, uimm3 (y));
1167 OUTS (outf, " (IU)");
1168 }
1169 else if (opc == 4 && I == 1 && G == 1)
1170 {
1171 OUTS (outf, "CC = ");
1172 OUTS (outf, pregs (x));
1173 OUTS (outf, " <= ");
1174 OUTS (outf, uimm3 (y));
1175 OUTS (outf, " (IU)");
1176 }
1177 else if (opc == 5 && I == 0 && G == 0)
1178 OUTS (outf, "CC = A0 == A1");
1179
1180 else if (opc == 6 && I == 0 && G == 0)
1181 OUTS (outf, "CC = A0 < A1");
1182
1183 else if (opc == 7 && I == 0 && G == 0)
1184 OUTS (outf, "CC = A0 <= A1");
1185
1186 else
1187 return 0;
1188 return 2;
1189 }
1190
1191 static int
1192 decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1193 {
1194 /* CC2dreg
1195 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1196 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1197 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1198 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1199 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1200
1201 if (op == 0)
1202 {
1203 OUTS (outf, dregs (reg));
1204 OUTS (outf, " = CC");
1205 }
1206 else if (op == 1)
1207 {
1208 OUTS (outf, "CC = ");
1209 OUTS (outf, dregs (reg));
1210 }
1211 else if (op == 3 && reg == 0)
1212 OUTS (outf, "CC = !CC");
1213 else
1214 return 0;
1215
1216 return 2;
1217 }
1218
1219 static int
1220 decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1221 {
1222 /* CC2stat
1223 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1224 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1225 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1226 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1227 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1228 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1229
1230 const char *bitname = statbits (cbit);
1231 if (decode_statbits[cbit] == REG_LASTREG)
1232 {
1233 /* All ASTAT bits except CC may be operated on in hardware, but may
1234 not have a dedicated insn, so still decode "valid" insns. */
1235 static char bitnames[64];
1236 if (cbit != 5)
1237 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1238 else
1239 strcpy (bitnames, "CC /* ... Illegal register ... */");
1240 bitname = bitnames;
1241 }
1242
1243 if (op == 0 && D == 0)
1244 {
1245 OUTS (outf, "CC = ");
1246 OUTS (outf, bitname);
1247 }
1248 else if (op == 1 && D == 0)
1249 {
1250 OUTS (outf, "CC |= ");
1251 OUTS (outf, bitname);
1252 }
1253 else if (op == 2 && D == 0)
1254 {
1255 OUTS (outf, "CC &= ");
1256 OUTS (outf, bitname);
1257 }
1258 else if (op == 3 && D == 0)
1259 {
1260 OUTS (outf, "CC ^= ");
1261 OUTS (outf, bitname);
1262 }
1263 else if (op == 0 && D == 1)
1264 {
1265 OUTS (outf, bitname);
1266 OUTS (outf, " = CC");
1267 }
1268 else if (op == 1 && D == 1)
1269 {
1270 OUTS (outf, bitname);
1271 OUTS (outf, " |= CC");
1272 }
1273 else if (op == 2 && D == 1)
1274 {
1275 OUTS (outf, bitname);
1276 OUTS (outf, " &= CC");
1277 }
1278 else if (op == 3 && D == 1)
1279 {
1280 OUTS (outf, bitname);
1281 OUTS (outf, " ^= CC");
1282 }
1283 else
1284 return 0;
1285
1286 return 2;
1287 }
1288
1289 static int
1290 decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1291 {
1292 /* BRCC
1293 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1294 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1295 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1296 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1297 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1298 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1299
1300 if (T == 1 && B == 1)
1301 {
1302 OUTS (outf, "IF CC JUMP 0x");
1303 OUTS (outf, pcrel10 (offset));
1304 OUTS (outf, " (BP)");
1305 }
1306 else if (T == 0 && B == 1)
1307 {
1308 OUTS (outf, "IF !CC JUMP 0x");
1309 OUTS (outf, pcrel10 (offset));
1310 OUTS (outf, " (BP)");
1311 }
1312 else if (T == 1)
1313 {
1314 OUTS (outf, "IF CC JUMP 0x");
1315 OUTS (outf, pcrel10 (offset));
1316 }
1317 else if (T == 0)
1318 {
1319 OUTS (outf, "IF !CC JUMP 0x");
1320 OUTS (outf, pcrel10 (offset));
1321 }
1322 else
1323 return 0;
1324
1325 return 2;
1326 }
1327
1328 static int
1329 decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1330 {
1331 /* UJUMP
1332 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1333 | 0 | 0 | 1 | 0 |.offset........................................|
1334 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1335 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1336
1337 OUTS (outf, "JUMP.S 0x");
1338 OUTS (outf, pcrel12 (offset));
1339 return 2;
1340 }
1341
1342 static int
1343 decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1344 {
1345 /* REGMV
1346 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1347 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1348 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1349 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1350 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1351 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1352 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1353
1354 if (!((IS_GENREG (gd, dst) && IS_GENREG (gs, src))
1355 || (IS_GENREG (gd, dst) && IS_DAGREG (gs, src))
1356 || (IS_DAGREG (gd, dst) && IS_GENREG (gs, src))
1357 || (IS_DAGREG (gd, dst) && IS_DAGREG (gs, src))
1358 || (IS_GENREG (gd, dst) && gs == 7 && src == 0)
1359 || (gd == 7 && dst == 0 && IS_GENREG (gs, src))
1360 || (IS_DREG (gd, dst) && IS_SYSREG (gs, src))
1361 || (IS_PREG (gd, dst) && IS_SYSREG (gs, src))
1362 || (IS_SYSREG (gd, dst) && IS_DREG (gs, src))
1363 || (IS_SYSREG (gd, dst) && IS_PREG (gs, src))
1364 || (IS_SYSREG (gd, dst) && gs == 7 && src == 0)))
1365 return 0;
1366
1367 OUTS (outf, allregs (dst, gd));
1368 OUTS (outf, " = ");
1369 OUTS (outf, allregs (src, gs));
1370 return 2;
1371 }
1372
1373 static int
1374 decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1375 {
1376 /* ALU2op
1377 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1378 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1379 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1380 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1381 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1382 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1383
1384 if (opc == 0)
1385 {
1386 OUTS (outf, dregs (dst));
1387 OUTS (outf, " >>>= ");
1388 OUTS (outf, dregs (src));
1389 }
1390 else if (opc == 1)
1391 {
1392 OUTS (outf, dregs (dst));
1393 OUTS (outf, " >>= ");
1394 OUTS (outf, dregs (src));
1395 }
1396 else if (opc == 2)
1397 {
1398 OUTS (outf, dregs (dst));
1399 OUTS (outf, " <<= ");
1400 OUTS (outf, dregs (src));
1401 }
1402 else if (opc == 3)
1403 {
1404 OUTS (outf, dregs (dst));
1405 OUTS (outf, " *= ");
1406 OUTS (outf, dregs (src));
1407 }
1408 else if (opc == 4)
1409 {
1410 OUTS (outf, dregs (dst));
1411 OUTS (outf, " = (");
1412 OUTS (outf, dregs (dst));
1413 OUTS (outf, " + ");
1414 OUTS (outf, dregs (src));
1415 OUTS (outf, ") << 0x1");
1416 }
1417 else if (opc == 5)
1418 {
1419 OUTS (outf, dregs (dst));
1420 OUTS (outf, " = (");
1421 OUTS (outf, dregs (dst));
1422 OUTS (outf, " + ");
1423 OUTS (outf, dregs (src));
1424 OUTS (outf, ") << 0x2");
1425 }
1426 else if (opc == 8)
1427 {
1428 OUTS (outf, "DIVQ (");
1429 OUTS (outf, dregs (dst));
1430 OUTS (outf, ", ");
1431 OUTS (outf, dregs (src));
1432 OUTS (outf, ")");
1433 }
1434 else if (opc == 9)
1435 {
1436 OUTS (outf, "DIVS (");
1437 OUTS (outf, dregs (dst));
1438 OUTS (outf, ", ");
1439 OUTS (outf, dregs (src));
1440 OUTS (outf, ")");
1441 }
1442 else if (opc == 10)
1443 {
1444 OUTS (outf, dregs (dst));
1445 OUTS (outf, " = ");
1446 OUTS (outf, dregs_lo (src));
1447 OUTS (outf, " (X)");
1448 }
1449 else if (opc == 11)
1450 {
1451 OUTS (outf, dregs (dst));
1452 OUTS (outf, " = ");
1453 OUTS (outf, dregs_lo (src));
1454 OUTS (outf, " (Z)");
1455 }
1456 else if (opc == 12)
1457 {
1458 OUTS (outf, dregs (dst));
1459 OUTS (outf, " = ");
1460 OUTS (outf, dregs_byte (src));
1461 OUTS (outf, " (X)");
1462 }
1463 else if (opc == 13)
1464 {
1465 OUTS (outf, dregs (dst));
1466 OUTS (outf, " = ");
1467 OUTS (outf, dregs_byte (src));
1468 OUTS (outf, " (Z)");
1469 }
1470 else if (opc == 14)
1471 {
1472 OUTS (outf, dregs (dst));
1473 OUTS (outf, " = -");
1474 OUTS (outf, dregs (src));
1475 }
1476 else if (opc == 15)
1477 {
1478 OUTS (outf, dregs (dst));
1479 OUTS (outf, " =~ ");
1480 OUTS (outf, dregs (src));
1481 }
1482 else
1483 return 0;
1484
1485 return 2;
1486 }
1487
1488 static int
1489 decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1490 {
1491 /* PTR2op
1492 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1493 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1494 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1495 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1496 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1497 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1498
1499 if (opc == 0)
1500 {
1501 OUTS (outf, pregs (dst));
1502 OUTS (outf, " -= ");
1503 OUTS (outf, pregs (src));
1504 }
1505 else if (opc == 1)
1506 {
1507 OUTS (outf, pregs (dst));
1508 OUTS (outf, " = ");
1509 OUTS (outf, pregs (src));
1510 OUTS (outf, " << 0x2");
1511 }
1512 else if (opc == 3)
1513 {
1514 OUTS (outf, pregs (dst));
1515 OUTS (outf, " = ");
1516 OUTS (outf, pregs (src));
1517 OUTS (outf, " >> 0x2");
1518 }
1519 else if (opc == 4)
1520 {
1521 OUTS (outf, pregs (dst));
1522 OUTS (outf, " = ");
1523 OUTS (outf, pregs (src));
1524 OUTS (outf, " >> 0x1");
1525 }
1526 else if (opc == 5)
1527 {
1528 OUTS (outf, pregs (dst));
1529 OUTS (outf, " += ");
1530 OUTS (outf, pregs (src));
1531 OUTS (outf, " (BREV)");
1532 }
1533 else if (opc == 6)
1534 {
1535 OUTS (outf, pregs (dst));
1536 OUTS (outf, " = (");
1537 OUTS (outf, pregs (dst));
1538 OUTS (outf, " + ");
1539 OUTS (outf, pregs (src));
1540 OUTS (outf, ") << 0x1");
1541 }
1542 else if (opc == 7)
1543 {
1544 OUTS (outf, pregs (dst));
1545 OUTS (outf, " = (");
1546 OUTS (outf, pregs (dst));
1547 OUTS (outf, " + ");
1548 OUTS (outf, pregs (src));
1549 OUTS (outf, ") << 0x2");
1550 }
1551 else
1552 return 0;
1553
1554 return 2;
1555 }
1556
1557 static int
1558 decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1559 {
1560 /* LOGI2op
1561 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1562 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1563 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1564 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1565 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1566 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1567
1568 if (opc == 0)
1569 {
1570 OUTS (outf, "CC = !BITTST (");
1571 OUTS (outf, dregs (dst));
1572 OUTS (outf, ", ");
1573 OUTS (outf, uimm5 (src));
1574 OUTS (outf, ");\t\t/* bit");
1575 OUTS (outf, imm7d (src));
1576 OUTS (outf, " */");
1577 comment = 1;
1578 }
1579 else if (opc == 1)
1580 {
1581 OUTS (outf, "CC = BITTST (");
1582 OUTS (outf, dregs (dst));
1583 OUTS (outf, ", ");
1584 OUTS (outf, uimm5 (src));
1585 OUTS (outf, ");\t\t/* bit");
1586 OUTS (outf, imm7d (src));
1587 OUTS (outf, " */");
1588 comment = 1;
1589 }
1590 else if (opc == 2)
1591 {
1592 OUTS (outf, "BITSET (");
1593 OUTS (outf, dregs (dst));
1594 OUTS (outf, ", ");
1595 OUTS (outf, uimm5 (src));
1596 OUTS (outf, ");\t\t/* bit");
1597 OUTS (outf, imm7d (src));
1598 OUTS (outf, " */");
1599 comment = 1;
1600 }
1601 else if (opc == 3)
1602 {
1603 OUTS (outf, "BITTGL (");
1604 OUTS (outf, dregs (dst));
1605 OUTS (outf, ", ");
1606 OUTS (outf, uimm5 (src));
1607 OUTS (outf, ");\t\t/* bit");
1608 OUTS (outf, imm7d (src));
1609 OUTS (outf, " */");
1610 comment = 1;
1611 }
1612 else if (opc == 4)
1613 {
1614 OUTS (outf, "BITCLR (");
1615 OUTS (outf, dregs (dst));
1616 OUTS (outf, ", ");
1617 OUTS (outf, uimm5 (src));
1618 OUTS (outf, ");\t\t/* bit");
1619 OUTS (outf, imm7d (src));
1620 OUTS (outf, " */");
1621 comment = 1;
1622 }
1623 else if (opc == 5)
1624 {
1625 OUTS (outf, dregs (dst));
1626 OUTS (outf, " >>>= ");
1627 OUTS (outf, uimm5 (src));
1628 }
1629 else if (opc == 6)
1630 {
1631 OUTS (outf, dregs (dst));
1632 OUTS (outf, " >>= ");
1633 OUTS (outf, uimm5 (src));
1634 }
1635 else if (opc == 7)
1636 {
1637 OUTS (outf, dregs (dst));
1638 OUTS (outf, " <<= ");
1639 OUTS (outf, uimm5 (src));
1640 }
1641 else
1642 return 0;
1643
1644 return 2;
1645 }
1646
1647 static int
1648 decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1649 {
1650 /* COMP3op
1651 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1652 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1653 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1654 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1655 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1656 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1657 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1658
1659 if (opc == 5 && src1 == src0)
1660 {
1661 OUTS (outf, pregs (dst));
1662 OUTS (outf, " = ");
1663 OUTS (outf, pregs (src0));
1664 OUTS (outf, " << 0x1");
1665 }
1666 else if (opc == 1)
1667 {
1668 OUTS (outf, dregs (dst));
1669 OUTS (outf, " = ");
1670 OUTS (outf, dregs (src0));
1671 OUTS (outf, " - ");
1672 OUTS (outf, dregs (src1));
1673 }
1674 else if (opc == 2)
1675 {
1676 OUTS (outf, dregs (dst));
1677 OUTS (outf, " = ");
1678 OUTS (outf, dregs (src0));
1679 OUTS (outf, " & ");
1680 OUTS (outf, dregs (src1));
1681 }
1682 else if (opc == 3)
1683 {
1684 OUTS (outf, dregs (dst));
1685 OUTS (outf, " = ");
1686 OUTS (outf, dregs (src0));
1687 OUTS (outf, " | ");
1688 OUTS (outf, dregs (src1));
1689 }
1690 else if (opc == 4)
1691 {
1692 OUTS (outf, dregs (dst));
1693 OUTS (outf, " = ");
1694 OUTS (outf, dregs (src0));
1695 OUTS (outf, " ^ ");
1696 OUTS (outf, dregs (src1));
1697 }
1698 else if (opc == 5)
1699 {
1700 OUTS (outf, pregs (dst));
1701 OUTS (outf, " = ");
1702 OUTS (outf, pregs (src0));
1703 OUTS (outf, " + ");
1704 OUTS (outf, pregs (src1));
1705 }
1706 else if (opc == 6)
1707 {
1708 OUTS (outf, pregs (dst));
1709 OUTS (outf, " = ");
1710 OUTS (outf, pregs (src0));
1711 OUTS (outf, " + (");
1712 OUTS (outf, pregs (src1));
1713 OUTS (outf, " << 0x1)");
1714 }
1715 else if (opc == 7)
1716 {
1717 OUTS (outf, pregs (dst));
1718 OUTS (outf, " = ");
1719 OUTS (outf, pregs (src0));
1720 OUTS (outf, " + (");
1721 OUTS (outf, pregs (src1));
1722 OUTS (outf, " << 0x2)");
1723 }
1724 else if (opc == 0)
1725 {
1726 OUTS (outf, dregs (dst));
1727 OUTS (outf, " = ");
1728 OUTS (outf, dregs (src0));
1729 OUTS (outf, " + ");
1730 OUTS (outf, dregs (src1));
1731 }
1732 else
1733 return 0;
1734
1735 return 2;
1736 }
1737
1738 static int
1739 decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1740 {
1741 /* COMPI2opD
1742 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1743 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1744 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1745 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1746 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1747 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1748
1749 bu32 *pval = get_allreg (0, dst);
1750
1751 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1752 to combine them, so it prints out the right values.
1753 Here we keep track of the registers. */
1754 if (op == 0)
1755 {
1756 *pval = imm7_val (src);
1757 if (src & 0x40)
1758 *pval |= 0xFFFFFF80;
1759 else
1760 *pval &= 0x7F;
1761 }
1762
1763 if (op == 0)
1764 {
1765 OUTS (outf, dregs (dst));
1766 OUTS (outf, " = ");
1767 OUTS (outf, imm7 (src));
1768 OUTS (outf, " (X);\t\t/*\t\t");
1769 OUTS (outf, dregs (dst));
1770 OUTS (outf, "=");
1771 OUTS (outf, uimm32 (*pval));
1772 OUTS (outf, "(");
1773 OUTS (outf, imm32 (*pval));
1774 OUTS (outf, ") */");
1775 comment = 1;
1776 }
1777 else if (op == 1)
1778 {
1779 OUTS (outf, dregs (dst));
1780 OUTS (outf, " += ");
1781 OUTS (outf, imm7 (src));
1782 OUTS (outf, ";\t\t/* (");
1783 OUTS (outf, imm7d (src));
1784 OUTS (outf, ") */");
1785 comment = 1;
1786 }
1787 else
1788 return 0;
1789
1790 return 2;
1791 }
1792
1793 static int
1794 decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1795 {
1796 /* COMPI2opP
1797 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1798 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1799 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1800 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1801 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1802 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1803
1804 bu32 *pval = get_allreg (1, dst);
1805
1806 if (op == 0)
1807 {
1808 *pval = imm7_val (src);
1809 if (src & 0x40)
1810 *pval |= 0xFFFFFF80;
1811 else
1812 *pval &= 0x7F;
1813 }
1814
1815 if (op == 0)
1816 {
1817 OUTS (outf, pregs (dst));
1818 OUTS (outf, " = ");
1819 OUTS (outf, imm7 (src));
1820 OUTS (outf, " (X);\t\t/*\t\t");
1821 OUTS (outf, pregs (dst));
1822 OUTS (outf, "=");
1823 OUTS (outf, uimm32 (*pval));
1824 OUTS (outf, "(");
1825 OUTS (outf, imm32 (*pval));
1826 OUTS (outf, ") */");
1827 comment = 1;
1828 }
1829 else if (op == 1)
1830 {
1831 OUTS (outf, pregs (dst));
1832 OUTS (outf, " += ");
1833 OUTS (outf, imm7 (src));
1834 OUTS (outf, ";\t\t/* (");
1835 OUTS (outf, imm7d (src));
1836 OUTS (outf, ") */");
1837 comment = 1;
1838 }
1839 else
1840 return 0;
1841
1842 return 2;
1843 }
1844
1845 static int
1846 decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1847 {
1848 /* LDSTpmod
1849 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1850 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1851 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1852 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1853 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1854 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1855 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1856 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1857
1858 if (aop == 1 && W == 0 && idx == ptr)
1859 {
1860 OUTS (outf, dregs_lo (reg));
1861 OUTS (outf, " = W[");
1862 OUTS (outf, pregs (ptr));
1863 OUTS (outf, "]");
1864 }
1865 else if (aop == 2 && W == 0 && idx == ptr)
1866 {
1867 OUTS (outf, dregs_hi (reg));
1868 OUTS (outf, " = W[");
1869 OUTS (outf, pregs (ptr));
1870 OUTS (outf, "]");
1871 }
1872 else if (aop == 1 && W == 1 && idx == ptr)
1873 {
1874 OUTS (outf, "W[");
1875 OUTS (outf, pregs (ptr));
1876 OUTS (outf, "] = ");
1877 OUTS (outf, dregs_lo (reg));
1878 }
1879 else if (aop == 2 && W == 1 && idx == ptr)
1880 {
1881 OUTS (outf, "W[");
1882 OUTS (outf, pregs (ptr));
1883 OUTS (outf, "] = ");
1884 OUTS (outf, dregs_hi (reg));
1885 }
1886 else if (aop == 0 && W == 0)
1887 {
1888 OUTS (outf, dregs (reg));
1889 OUTS (outf, " = [");
1890 OUTS (outf, pregs (ptr));
1891 OUTS (outf, " ++ ");
1892 OUTS (outf, pregs (idx));
1893 OUTS (outf, "]");
1894 }
1895 else if (aop == 1 && W == 0)
1896 {
1897 OUTS (outf, dregs_lo (reg));
1898 OUTS (outf, " = W[");
1899 OUTS (outf, pregs (ptr));
1900 OUTS (outf, " ++ ");
1901 OUTS (outf, pregs (idx));
1902 OUTS (outf, "]");
1903 }
1904 else if (aop == 2 && W == 0)
1905 {
1906 OUTS (outf, dregs_hi (reg));
1907 OUTS (outf, " = W[");
1908 OUTS (outf, pregs (ptr));
1909 OUTS (outf, " ++ ");
1910 OUTS (outf, pregs (idx));
1911 OUTS (outf, "]");
1912 }
1913 else if (aop == 3 && W == 0)
1914 {
1915 OUTS (outf, dregs (reg));
1916 OUTS (outf, " = W[");
1917 OUTS (outf, pregs (ptr));
1918 OUTS (outf, " ++ ");
1919 OUTS (outf, pregs (idx));
1920 OUTS (outf, "] (Z)");
1921 }
1922 else if (aop == 3 && W == 1)
1923 {
1924 OUTS (outf, dregs (reg));
1925 OUTS (outf, " = W[");
1926 OUTS (outf, pregs (ptr));
1927 OUTS (outf, " ++ ");
1928 OUTS (outf, pregs (idx));
1929 OUTS (outf, "] (X)");
1930 }
1931 else if (aop == 0 && W == 1)
1932 {
1933 OUTS (outf, "[");
1934 OUTS (outf, pregs (ptr));
1935 OUTS (outf, " ++ ");
1936 OUTS (outf, pregs (idx));
1937 OUTS (outf, "] = ");
1938 OUTS (outf, dregs (reg));
1939 }
1940 else if (aop == 1 && W == 1)
1941 {
1942 OUTS (outf, "W[");
1943 OUTS (outf, pregs (ptr));
1944 OUTS (outf, " ++ ");
1945 OUTS (outf, pregs (idx));
1946 OUTS (outf, "] = ");
1947 OUTS (outf, dregs_lo (reg));
1948 }
1949 else if (aop == 2 && W == 1)
1950 {
1951 OUTS (outf, "W[");
1952 OUTS (outf, pregs (ptr));
1953 OUTS (outf, " ++ ");
1954 OUTS (outf, pregs (idx));
1955 OUTS (outf, "] = ");
1956 OUTS (outf, dregs_hi (reg));
1957 }
1958 else
1959 return 0;
1960
1961 return 2;
1962 }
1963
1964 static int
1965 decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
1966 {
1967 /* dagMODim
1968 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1969 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1970 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1971 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
1972 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
1973 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
1974 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
1975
1976 if (op == 0 && br == 1)
1977 {
1978 OUTS (outf, iregs (i));
1979 OUTS (outf, " += ");
1980 OUTS (outf, mregs (m));
1981 OUTS (outf, " (BREV)");
1982 }
1983 else if (op == 0)
1984 {
1985 OUTS (outf, iregs (i));
1986 OUTS (outf, " += ");
1987 OUTS (outf, mregs (m));
1988 }
1989 else if (op == 1)
1990 {
1991 OUTS (outf, iregs (i));
1992 OUTS (outf, " -= ");
1993 OUTS (outf, mregs (m));
1994 }
1995 else
1996 return 0;
1997
1998 return 2;
1999 }
2000
2001 static int
2002 decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2003 {
2004 /* dagMODik
2005 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2006 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2007 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2008 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2009 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2010
2011 if (op == 0)
2012 {
2013 OUTS (outf, iregs (i));
2014 OUTS (outf, " += 0x2");
2015 }
2016 else if (op == 1)
2017 {
2018 OUTS (outf, iregs (i));
2019 OUTS (outf, " -= 0x2");
2020 }
2021 else if (op == 2)
2022 {
2023 OUTS (outf, iregs (i));
2024 OUTS (outf, " += 0x4");
2025 }
2026 else if (op == 3)
2027 {
2028 OUTS (outf, iregs (i));
2029 OUTS (outf, " -= 0x4");
2030 }
2031 else
2032 return 0;
2033
2034 if (! parallel )
2035 {
2036 OUTS (outf, ";\t\t/* ( ");
2037 if (op == 0 || op == 1)
2038 OUTS (outf, "2");
2039 else if (op == 2 || op == 3)
2040 OUTS (outf, "4");
2041 OUTS (outf, ") */");
2042 comment = 1;
2043 }
2044
2045 return 2;
2046 }
2047
2048 static int
2049 decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2050 {
2051 /* dspLDST
2052 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2053 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2054 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2055 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2056 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2057 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2058 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2059 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2060
2061 if (aop == 0 && W == 0 && m == 0)
2062 {
2063 OUTS (outf, dregs (reg));
2064 OUTS (outf, " = [");
2065 OUTS (outf, iregs (i));
2066 OUTS (outf, "++]");
2067 }
2068 else if (aop == 0 && W == 0 && m == 1)
2069 {
2070 OUTS (outf, dregs_lo (reg));
2071 OUTS (outf, " = W[");
2072 OUTS (outf, iregs (i));
2073 OUTS (outf, "++]");
2074 }
2075 else if (aop == 0 && W == 0 && m == 2)
2076 {
2077 OUTS (outf, dregs_hi (reg));
2078 OUTS (outf, " = W[");
2079 OUTS (outf, iregs (i));
2080 OUTS (outf, "++]");
2081 }
2082 else if (aop == 1 && W == 0 && m == 0)
2083 {
2084 OUTS (outf, dregs (reg));
2085 OUTS (outf, " = [");
2086 OUTS (outf, iregs (i));
2087 OUTS (outf, "--]");
2088 }
2089 else if (aop == 1 && W == 0 && m == 1)
2090 {
2091 OUTS (outf, dregs_lo (reg));
2092 OUTS (outf, " = W[");
2093 OUTS (outf, iregs (i));
2094 OUTS (outf, "--]");
2095 }
2096 else if (aop == 1 && W == 0 && m == 2)
2097 {
2098 OUTS (outf, dregs_hi (reg));
2099 OUTS (outf, " = W[");
2100 OUTS (outf, iregs (i));
2101 OUTS (outf, "--]");
2102 }
2103 else if (aop == 2 && W == 0 && m == 0)
2104 {
2105 OUTS (outf, dregs (reg));
2106 OUTS (outf, " = [");
2107 OUTS (outf, iregs (i));
2108 OUTS (outf, "]");
2109 }
2110 else if (aop == 2 && W == 0 && m == 1)
2111 {
2112 OUTS (outf, dregs_lo (reg));
2113 OUTS (outf, " = W[");
2114 OUTS (outf, iregs (i));
2115 OUTS (outf, "]");
2116 }
2117 else if (aop == 2 && W == 0 && m == 2)
2118 {
2119 OUTS (outf, dregs_hi (reg));
2120 OUTS (outf, " = W[");
2121 OUTS (outf, iregs (i));
2122 OUTS (outf, "]");
2123 }
2124 else if (aop == 0 && W == 1 && m == 0)
2125 {
2126 OUTS (outf, "[");
2127 OUTS (outf, iregs (i));
2128 OUTS (outf, "++] = ");
2129 OUTS (outf, dregs (reg));
2130 }
2131 else if (aop == 0 && W == 1 && m == 1)
2132 {
2133 OUTS (outf, "W[");
2134 OUTS (outf, iregs (i));
2135 OUTS (outf, "++] = ");
2136 OUTS (outf, dregs_lo (reg));
2137 }
2138 else if (aop == 0 && W == 1 && m == 2)
2139 {
2140 OUTS (outf, "W[");
2141 OUTS (outf, iregs (i));
2142 OUTS (outf, "++] = ");
2143 OUTS (outf, dregs_hi (reg));
2144 }
2145 else if (aop == 1 && W == 1 && m == 0)
2146 {
2147 OUTS (outf, "[");
2148 OUTS (outf, iregs (i));
2149 OUTS (outf, "--] = ");
2150 OUTS (outf, dregs (reg));
2151 }
2152 else if (aop == 1 && W == 1 && m == 1)
2153 {
2154 OUTS (outf, "W[");
2155 OUTS (outf, iregs (i));
2156 OUTS (outf, "--] = ");
2157 OUTS (outf, dregs_lo (reg));
2158 }
2159 else if (aop == 1 && W == 1 && m == 2)
2160 {
2161 OUTS (outf, "W[");
2162 OUTS (outf, iregs (i));
2163 OUTS (outf, "--] = ");
2164 OUTS (outf, dregs_hi (reg));
2165 }
2166 else if (aop == 2 && W == 1 && m == 0)
2167 {
2168 OUTS (outf, "[");
2169 OUTS (outf, iregs (i));
2170 OUTS (outf, "] = ");
2171 OUTS (outf, dregs (reg));
2172 }
2173 else if (aop == 2 && W == 1 && m == 1)
2174 {
2175 OUTS (outf, "W[");
2176 OUTS (outf, iregs (i));
2177 OUTS (outf, "] = ");
2178 OUTS (outf, dregs_lo (reg));
2179 }
2180 else if (aop == 2 && W == 1 && m == 2)
2181 {
2182 OUTS (outf, "W[");
2183 OUTS (outf, iregs (i));
2184 OUTS (outf, "] = ");
2185 OUTS (outf, dregs_hi (reg));
2186 }
2187 else if (aop == 3 && W == 0)
2188 {
2189 OUTS (outf, dregs (reg));
2190 OUTS (outf, " = [");
2191 OUTS (outf, iregs (i));
2192 OUTS (outf, " ++ ");
2193 OUTS (outf, mregs (m));
2194 OUTS (outf, "]");
2195 }
2196 else if (aop == 3 && W == 1)
2197 {
2198 OUTS (outf, "[");
2199 OUTS (outf, iregs (i));
2200 OUTS (outf, " ++ ");
2201 OUTS (outf, mregs (m));
2202 OUTS (outf, "] = ");
2203 OUTS (outf, dregs (reg));
2204 }
2205 else
2206 return 0;
2207
2208 return 2;
2209 }
2210
2211 static int
2212 decode_LDST_0 (TIword iw0, disassemble_info *outf)
2213 {
2214 /* LDST
2215 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2216 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2217 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2218 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2219 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2220 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2221 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2222 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2223 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2224
2225 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2226 {
2227 OUTS (outf, dregs (reg));
2228 OUTS (outf, " = [");
2229 OUTS (outf, pregs (ptr));
2230 OUTS (outf, "++]");
2231 }
2232 else if (aop == 0 && sz == 0 && Z == 1 && W == 0)
2233 {
2234 OUTS (outf, pregs (reg));
2235 OUTS (outf, " = [");
2236 OUTS (outf, pregs (ptr));
2237 OUTS (outf, "++]");
2238 }
2239 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2240 {
2241 OUTS (outf, dregs (reg));
2242 OUTS (outf, " = W[");
2243 OUTS (outf, pregs (ptr));
2244 OUTS (outf, "++] (Z)");
2245 }
2246 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2247 {
2248 OUTS (outf, dregs (reg));
2249 OUTS (outf, " = W[");
2250 OUTS (outf, pregs (ptr));
2251 OUTS (outf, "++] (X)");
2252 }
2253 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2254 {
2255 OUTS (outf, dregs (reg));
2256 OUTS (outf, " = B[");
2257 OUTS (outf, pregs (ptr));
2258 OUTS (outf, "++] (Z)");
2259 }
2260 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2261 {
2262 OUTS (outf, dregs (reg));
2263 OUTS (outf, " = B[");
2264 OUTS (outf, pregs (ptr));
2265 OUTS (outf, "++] (X)");
2266 }
2267 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2268 {
2269 OUTS (outf, dregs (reg));
2270 OUTS (outf, " = [");
2271 OUTS (outf, pregs (ptr));
2272 OUTS (outf, "--]");
2273 }
2274 else if (aop == 1 && sz == 0 && Z == 1 && W == 0)
2275 {
2276 OUTS (outf, pregs (reg));
2277 OUTS (outf, " = [");
2278 OUTS (outf, pregs (ptr));
2279 OUTS (outf, "--]");
2280 }
2281 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2282 {
2283 OUTS (outf, dregs (reg));
2284 OUTS (outf, " = W[");
2285 OUTS (outf, pregs (ptr));
2286 OUTS (outf, "--] (Z)");
2287 }
2288 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2289 {
2290 OUTS (outf, dregs (reg));
2291 OUTS (outf, " = W[");
2292 OUTS (outf, pregs (ptr));
2293 OUTS (outf, "--] (X)");
2294 }
2295 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2296 {
2297 OUTS (outf, dregs (reg));
2298 OUTS (outf, " = B[");
2299 OUTS (outf, pregs (ptr));
2300 OUTS (outf, "--] (Z)");
2301 }
2302 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2303 {
2304 OUTS (outf, dregs (reg));
2305 OUTS (outf, " = B[");
2306 OUTS (outf, pregs (ptr));
2307 OUTS (outf, "--] (X)");
2308 }
2309 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2310 {
2311 OUTS (outf, dregs (reg));
2312 OUTS (outf, " = [");
2313 OUTS (outf, pregs (ptr));
2314 OUTS (outf, "]");
2315 }
2316 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2317 {
2318 OUTS (outf, pregs (reg));
2319 OUTS (outf, " = [");
2320 OUTS (outf, pregs (ptr));
2321 OUTS (outf, "]");
2322 }
2323 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2324 {
2325 OUTS (outf, dregs (reg));
2326 OUTS (outf, " = W[");
2327 OUTS (outf, pregs (ptr));
2328 OUTS (outf, "] (Z)");
2329 }
2330 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2331 {
2332 OUTS (outf, dregs (reg));
2333 OUTS (outf, " = W[");
2334 OUTS (outf, pregs (ptr));
2335 OUTS (outf, "] (X)");
2336 }
2337 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2338 {
2339 OUTS (outf, dregs (reg));
2340 OUTS (outf, " = B[");
2341 OUTS (outf, pregs (ptr));
2342 OUTS (outf, "] (Z)");
2343 }
2344 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2345 {
2346 OUTS (outf, dregs (reg));
2347 OUTS (outf, " = B[");
2348 OUTS (outf, pregs (ptr));
2349 OUTS (outf, "] (X)");
2350 }
2351 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2352 {
2353 OUTS (outf, "[");
2354 OUTS (outf, pregs (ptr));
2355 OUTS (outf, "++] = ");
2356 OUTS (outf, dregs (reg));
2357 }
2358 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2359 {
2360 OUTS (outf, "[");
2361 OUTS (outf, pregs (ptr));
2362 OUTS (outf, "++] = ");
2363 OUTS (outf, pregs (reg));
2364 }
2365 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2366 {
2367 OUTS (outf, "W[");
2368 OUTS (outf, pregs (ptr));
2369 OUTS (outf, "++] = ");
2370 OUTS (outf, dregs (reg));
2371 }
2372 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2373 {
2374 OUTS (outf, "B[");
2375 OUTS (outf, pregs (ptr));
2376 OUTS (outf, "++] = ");
2377 OUTS (outf, dregs (reg));
2378 }
2379 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2380 {
2381 OUTS (outf, "[");
2382 OUTS (outf, pregs (ptr));
2383 OUTS (outf, "--] = ");
2384 OUTS (outf, dregs (reg));
2385 }
2386 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2387 {
2388 OUTS (outf, "[");
2389 OUTS (outf, pregs (ptr));
2390 OUTS (outf, "--] = ");
2391 OUTS (outf, pregs (reg));
2392 }
2393 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2394 {
2395 OUTS (outf, "W[");
2396 OUTS (outf, pregs (ptr));
2397 OUTS (outf, "--] = ");
2398 OUTS (outf, dregs (reg));
2399 }
2400 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2401 {
2402 OUTS (outf, "B[");
2403 OUTS (outf, pregs (ptr));
2404 OUTS (outf, "--] = ");
2405 OUTS (outf, dregs (reg));
2406 }
2407 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2408 {
2409 OUTS (outf, "[");
2410 OUTS (outf, pregs (ptr));
2411 OUTS (outf, "] = ");
2412 OUTS (outf, dregs (reg));
2413 }
2414 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2415 {
2416 OUTS (outf, "[");
2417 OUTS (outf, pregs (ptr));
2418 OUTS (outf, "] = ");
2419 OUTS (outf, pregs (reg));
2420 }
2421 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2422 {
2423 OUTS (outf, "W[");
2424 OUTS (outf, pregs (ptr));
2425 OUTS (outf, "] = ");
2426 OUTS (outf, dregs (reg));
2427 }
2428 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2429 {
2430 OUTS (outf, "B[");
2431 OUTS (outf, pregs (ptr));
2432 OUTS (outf, "] = ");
2433 OUTS (outf, dregs (reg));
2434 }
2435 else
2436 return 0;
2437
2438 return 2;
2439 }
2440
2441 static int
2442 decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2443 {
2444 /* LDSTiiFP
2445 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2446 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2447 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2448 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2449 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2450 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2451
2452 if (W == 0)
2453 {
2454 OUTS (outf, dpregs (reg));
2455 OUTS (outf, " = [FP ");
2456 OUTS (outf, negimm5s4 (offset));
2457 OUTS (outf, "]");
2458 }
2459 else if (W == 1)
2460 {
2461 OUTS (outf, "[FP ");
2462 OUTS (outf, negimm5s4 (offset));
2463 OUTS (outf, "] = ");
2464 OUTS (outf, dpregs (reg));
2465 }
2466 else
2467 return 0;
2468
2469 return 2;
2470 }
2471
2472 static int
2473 decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2474 {
2475 /* LDSTii
2476 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2477 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2478 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2479 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2480 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2481 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2482 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2483 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2484
2485 if (W == 0 && op == 0)
2486 {
2487 OUTS (outf, dregs (reg));
2488 OUTS (outf, " = [");
2489 OUTS (outf, pregs (ptr));
2490 OUTS (outf, " + ");
2491 OUTS (outf, uimm4s4 (offset));
2492 OUTS (outf, "]");
2493 }
2494 else if (W == 0 && op == 1)
2495 {
2496 OUTS (outf, dregs (reg));
2497 OUTS (outf, " = W[");
2498 OUTS (outf, pregs (ptr));
2499 OUTS (outf, " + ");
2500 OUTS (outf, uimm4s2 (offset));
2501 OUTS (outf, "] (Z)");
2502 }
2503 else if (W == 0 && op == 2)
2504 {
2505 OUTS (outf, dregs (reg));
2506 OUTS (outf, " = W[");
2507 OUTS (outf, pregs (ptr));
2508 OUTS (outf, " + ");
2509 OUTS (outf, uimm4s2 (offset));
2510 OUTS (outf, "] (X)");
2511 }
2512 else if (W == 0 && op == 3)
2513 {
2514 OUTS (outf, pregs (reg));
2515 OUTS (outf, " = [");
2516 OUTS (outf, pregs (ptr));
2517 OUTS (outf, " + ");
2518 OUTS (outf, uimm4s4 (offset));
2519 OUTS (outf, "]");
2520 }
2521 else if (W == 1 && op == 0)
2522 {
2523 OUTS (outf, "[");
2524 OUTS (outf, pregs (ptr));
2525 OUTS (outf, " + ");
2526 OUTS (outf, uimm4s4 (offset));
2527 OUTS (outf, "] = ");
2528 OUTS (outf, dregs (reg));
2529 }
2530 else if (W == 1 && op == 1)
2531 {
2532 OUTS (outf, "W[");
2533 OUTS (outf, pregs (ptr));
2534 OUTS (outf, " + ");
2535 OUTS (outf, uimm4s2 (offset));
2536 OUTS (outf, "] = ");
2537 OUTS (outf, dregs (reg));
2538 }
2539 else if (W == 1 && op == 3)
2540 {
2541 OUTS (outf, "[");
2542 OUTS (outf, pregs (ptr));
2543 OUTS (outf, " + ");
2544 OUTS (outf, uimm4s4 (offset));
2545 OUTS (outf, "] = ");
2546 OUTS (outf, pregs (reg));
2547 }
2548 else
2549 return 0;
2550
2551 return 2;
2552 }
2553
2554 static int
2555 decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2556 {
2557 /* LoopSetup
2558 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2559 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2560 |.reg...........| - | - |.eoffset...............................|
2561 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2562 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2563 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2564 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2565 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2566 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2567
2568 if (rop == 0)
2569 {
2570 OUTS (outf, "LSETUP");
2571 OUTS (outf, "(0x");
2572 OUTS (outf, pcrel4 (soffset));
2573 OUTS (outf, ", 0x");
2574 OUTS (outf, lppcrel10 (eoffset));
2575 OUTS (outf, ") ");
2576 OUTS (outf, counters (c));
2577 }
2578 else if (rop == 1)
2579 {
2580 OUTS (outf, "LSETUP");
2581 OUTS (outf, "(0x");
2582 OUTS (outf, pcrel4 (soffset));
2583 OUTS (outf, ", 0x");
2584 OUTS (outf, lppcrel10 (eoffset));
2585 OUTS (outf, ") ");
2586 OUTS (outf, counters (c));
2587 OUTS (outf, " = ");
2588 OUTS (outf, pregs (reg));
2589 }
2590 else if (rop == 3)
2591 {
2592 OUTS (outf, "LSETUP");
2593 OUTS (outf, "(0x");
2594 OUTS (outf, pcrel4 (soffset));
2595 OUTS (outf, ", 0x");
2596 OUTS (outf, lppcrel10 (eoffset));
2597 OUTS (outf, ") ");
2598 OUTS (outf, counters (c));
2599 OUTS (outf, " = ");
2600 OUTS (outf, pregs (reg));
2601 OUTS (outf, " >> 0x1");
2602 }
2603 else
2604 return 0;
2605
2606 return 4;
2607 }
2608
2609 static int
2610 decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2611 {
2612 /* LDIMMhalf
2613 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2614 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2615 |.hword.........................................................|
2616 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2617 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2618 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2619 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2620 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2621 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2622 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2623
2624 bu32 *pval = get_allreg (grp, reg);
2625
2626 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2627 to combine them, so it prints out the right values.
2628 Here we keep track of the registers. */
2629 if (H == 0 && S == 1 && Z == 0)
2630 {
2631 /* regs = imm16 (x) */
2632 *pval = imm16_val (hword);
2633 if (hword & 0x8000)
2634 *pval |= 0xFFFF0000;
2635 else
2636 *pval &= 0xFFFF;
2637 }
2638 else if (H == 0 && S == 0 && Z == 1)
2639 {
2640 /* regs = luimm16 (Z) */
2641 *pval = luimm16_val (hword);
2642 *pval &= 0xFFFF;
2643 }
2644 else if (H == 0 && S == 0 && Z == 0)
2645 {
2646 /* regs_lo = luimm16 */
2647 *pval &= 0xFFFF0000;
2648 *pval |= luimm16_val (hword);
2649 }
2650 else if (H == 1 && S == 0 && Z == 0)
2651 {
2652 /* regs_hi = huimm16 */
2653 *pval &= 0xFFFF;
2654 *pval |= luimm16_val (hword) << 16;
2655 }
2656
2657 /* Here we do the disassembly */
2658 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2659 {
2660 OUTS (outf, dregs_lo (reg));
2661 OUTS (outf, " = ");
2662 OUTS (outf, uimm16 (hword));
2663 }
2664 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2665 {
2666 OUTS (outf, dregs_hi (reg));
2667 OUTS (outf, " = ");
2668 OUTS (outf, uimm16 (hword));
2669 }
2670 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2671 {
2672 OUTS (outf, dregs (reg));
2673 OUTS (outf, " = ");
2674 OUTS (outf, imm16 (hword));
2675 OUTS (outf, " (X)");
2676 }
2677 else if (H == 0 && S == 1 && Z == 0)
2678 {
2679 OUTS (outf, regs (reg, grp));
2680 OUTS (outf, " = ");
2681 OUTS (outf, imm16 (hword));
2682 OUTS (outf, " (X)");
2683 }
2684 else if (H == 0 && S == 0 && Z == 1)
2685 {
2686 OUTS (outf, regs (reg, grp));
2687 OUTS (outf, " = ");
2688 OUTS (outf, uimm16 (hword));
2689 OUTS (outf, " (Z)");
2690 }
2691 else if (H == 0 && S == 0 && Z == 0)
2692 {
2693 OUTS (outf, regs_lo (reg, grp));
2694 OUTS (outf, " = ");
2695 OUTS (outf, uimm16 (hword));
2696 }
2697 else if (H == 1 && S == 0 && Z == 0)
2698 {
2699 OUTS (outf, regs_hi (reg, grp));
2700 OUTS (outf, " = ");
2701 OUTS (outf, uimm16 (hword));
2702 }
2703 else
2704 return 0;
2705
2706 /* And we print out the 32-bit value if it is a pointer. */
2707 if (S == 0 && Z == 0)
2708 {
2709 OUTS (outf, ";\t\t/* (");
2710 OUTS (outf, imm16d (hword));
2711 OUTS (outf, ")\t");
2712
2713 /* If it is an MMR, don't print the symbol. */
2714 if (*pval < 0xFFC00000 && grp == 1)
2715 {
2716 OUTS (outf, regs (reg, grp));
2717 OUTS (outf, "=0x");
2718 OUTS (outf, huimm32e (*pval));
2719 }
2720 else
2721 {
2722 OUTS (outf, regs (reg, grp));
2723 OUTS (outf, "=0x");
2724 OUTS (outf, huimm32e (*pval));
2725 OUTS (outf, "(");
2726 OUTS (outf, imm32 (*pval));
2727 OUTS (outf, ")");
2728 }
2729
2730 OUTS (outf, " */");
2731 comment = 1;
2732 }
2733 if (S == 1 || Z == 1)
2734 {
2735 OUTS (outf, ";\t\t/*\t\t");
2736 OUTS (outf, regs (reg, grp));
2737 OUTS (outf, "=0x");
2738 OUTS (outf, huimm32e (*pval));
2739 OUTS (outf, "(");
2740 OUTS (outf, imm32 (*pval));
2741 OUTS (outf, ") */");
2742 comment = 1;
2743 }
2744 return 4;
2745 }
2746
2747 static int
2748 decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2749 {
2750 /* CALLa
2751 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2752 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2753 |.lsw...........................................................|
2754 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2755 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2756 int lsw = ((iw1 >> 0) & 0xffff);
2757 int msw = ((iw0 >> 0) & 0xff);
2758
2759 if (S == 1)
2760 OUTS (outf, "CALL 0x");
2761 else if (S == 0)
2762 OUTS (outf, "JUMP.L 0x");
2763 else
2764 return 0;
2765
2766 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2767 return 4;
2768 }
2769
2770 static int
2771 decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2772 {
2773 /* LDSTidxI
2774 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2775 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2776 |.offset........................................................|
2777 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2778 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2779 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2780 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2781 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2782 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2783 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2784
2785 if (W == 0 && sz == 0 && Z == 0)
2786 {
2787 OUTS (outf, dregs (reg));
2788 OUTS (outf, " = [");
2789 OUTS (outf, pregs (ptr));
2790 OUTS (outf, " + ");
2791 OUTS (outf, imm16s4 (offset));
2792 OUTS (outf, "]");
2793 }
2794 else if (W == 0 && sz == 0 && Z == 1)
2795 {
2796 OUTS (outf, pregs (reg));
2797 OUTS (outf, " = [");
2798 OUTS (outf, pregs (ptr));
2799 OUTS (outf, " + ");
2800 OUTS (outf, imm16s4 (offset));
2801 OUTS (outf, "]");
2802 }
2803 else if (W == 0 && sz == 1 && Z == 0)
2804 {
2805 OUTS (outf, dregs (reg));
2806 OUTS (outf, " = W[");
2807 OUTS (outf, pregs (ptr));
2808 OUTS (outf, " + ");
2809 OUTS (outf, imm16s2 (offset));
2810 OUTS (outf, "] (Z)");
2811 }
2812 else if (W == 0 && sz == 1 && Z == 1)
2813 {
2814 OUTS (outf, dregs (reg));
2815 OUTS (outf, " = W[");
2816 OUTS (outf, pregs (ptr));
2817 OUTS (outf, " + ");
2818 OUTS (outf, imm16s2 (offset));
2819 OUTS (outf, "] (X)");
2820 }
2821 else if (W == 0 && sz == 2 && Z == 0)
2822 {
2823 OUTS (outf, dregs (reg));
2824 OUTS (outf, " = B[");
2825 OUTS (outf, pregs (ptr));
2826 OUTS (outf, " + ");
2827 OUTS (outf, imm16 (offset));
2828 OUTS (outf, "] (Z)");
2829 }
2830 else if (W == 0 && sz == 2 && Z == 1)
2831 {
2832 OUTS (outf, dregs (reg));
2833 OUTS (outf, " = B[");
2834 OUTS (outf, pregs (ptr));
2835 OUTS (outf, " + ");
2836 OUTS (outf, imm16 (offset));
2837 OUTS (outf, "] (X)");
2838 }
2839 else if (W == 1 && sz == 0 && Z == 0)
2840 {
2841 OUTS (outf, "[");
2842 OUTS (outf, pregs (ptr));
2843 OUTS (outf, " + ");
2844 OUTS (outf, imm16s4 (offset));
2845 OUTS (outf, "] = ");
2846 OUTS (outf, dregs (reg));
2847 }
2848 else if (W == 1 && sz == 0 && Z == 1)
2849 {
2850 OUTS (outf, "[");
2851 OUTS (outf, pregs (ptr));
2852 OUTS (outf, " + ");
2853 OUTS (outf, imm16s4 (offset));
2854 OUTS (outf, "] = ");
2855 OUTS (outf, pregs (reg));
2856 }
2857 else if (W == 1 && sz == 1 && Z == 0)
2858 {
2859 OUTS (outf, "W[");
2860 OUTS (outf, pregs (ptr));
2861 OUTS (outf, " + ");
2862 OUTS (outf, imm16s2 (offset));
2863 OUTS (outf, "] = ");
2864 OUTS (outf, dregs (reg));
2865 }
2866 else if (W == 1 && sz == 2 && Z == 0)
2867 {
2868 OUTS (outf, "B[");
2869 OUTS (outf, pregs (ptr));
2870 OUTS (outf, " + ");
2871 OUTS (outf, imm16 (offset));
2872 OUTS (outf, "] = ");
2873 OUTS (outf, dregs (reg));
2874 }
2875 else
2876 return 0;
2877
2878 return 4;
2879 }
2880
2881 static int
2882 decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2883 {
2884 /* linkage
2885 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2886 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2887 |.framesize.....................................................|
2888 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2889 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2890 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2891
2892 if (R == 0)
2893 {
2894 OUTS (outf, "LINK ");
2895 OUTS (outf, uimm16s4 (framesize));
2896 OUTS (outf, ";\t\t/* (");
2897 OUTS (outf, uimm16s4d (framesize));
2898 OUTS (outf, ") */");
2899 comment = 1;
2900 }
2901 else if (R == 1)
2902 OUTS (outf, "UNLINK");
2903 else
2904 return 0;
2905
2906 return 4;
2907 }
2908
2909 static int
2910 decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2911 {
2912 /* dsp32mac
2913 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2914 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2915 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2916 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2917 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2918 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2919 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2920 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2921 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2922 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2923 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2924 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2925 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2926 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2927 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2928 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2929 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2930 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2931
2932 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2933 return 0;
2934
2935 if (op1 == 3 && MM)
2936 return 0;
2937
2938 if ((w1 || w0) && mmod == M_W32)
2939 return 0;
2940
2941 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
2942 return 0;
2943
2944 if (w1 == 1 || op1 != 3)
2945 {
2946 if (w1)
2947 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
2948
2949 if (op1 == 3)
2950 OUTS (outf, " = A1");
2951 else
2952 {
2953 if (w1)
2954 OUTS (outf, " = (");
2955 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
2956 if (w1)
2957 OUTS (outf, ")");
2958 }
2959
2960 if (w0 == 1 || op0 != 3)
2961 {
2962 if (MM)
2963 OUTS (outf, " (M)");
2964 MM = 0;
2965 OUTS (outf, ", ");
2966 }
2967 }
2968
2969 if (w0 == 1 || op0 != 3)
2970 {
2971 if (w0)
2972 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
2973
2974 if (op0 == 3)
2975 OUTS (outf, " = A0");
2976 else
2977 {
2978 if (w0)
2979 OUTS (outf, " = (");
2980 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
2981 if (w0)
2982 OUTS (outf, ")");
2983 }
2984 }
2985
2986 decode_optmode (mmod, MM, outf);
2987
2988 return 4;
2989 }
2990
2991 static int
2992 decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2993 {
2994 /* dsp32mult
2995 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2996 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
2997 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2998 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2999 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3000 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3001 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
3002 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
3003 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
3004 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3005 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
3006 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3007 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3008 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3009 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3010 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3011
3012 if (w1 == 0 && w0 == 0)
3013 return 0;
3014
3015 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3016 return 0;
3017
3018 if (w1)
3019 {
3020 OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst));
3021 OUTS (outf, " = ");
3022 decode_multfunc (h01, h11, src0, src1, outf);
3023
3024 if (w0)
3025 {
3026 if (MM)
3027 OUTS (outf, " (M)");
3028 MM = 0;
3029 OUTS (outf, ", ");
3030 }
3031 }
3032
3033 if (w0)
3034 {
3035 OUTS (outf, dregs (dst));
3036 OUTS (outf, " = ");
3037 decode_multfunc (h00, h10, src0, src1, outf);
3038 }
3039
3040 decode_optmode (mmod, MM, outf);
3041 return 4;
3042 }
3043
3044 static int
3045 decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3046 {
3047 /* dsp32alu
3048 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3049 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3050 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3051 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3052 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3053 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3054 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3055 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3056 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3057 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3058 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3059 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3060 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3061
3062 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3063 {
3064 OUTS (outf, "A0.L = ");
3065 OUTS (outf, dregs_lo (src0));
3066 }
3067 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3068 {
3069 OUTS (outf, "A1.H = ");
3070 OUTS (outf, dregs_hi (src0));
3071 }
3072 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3073 {
3074 OUTS (outf, "A1.L = ");
3075 OUTS (outf, dregs_lo (src0));
3076 }
3077 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3078 {
3079 OUTS (outf, "A0.H = ");
3080 OUTS (outf, dregs_hi (src0));
3081 }
3082 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3083 {
3084 OUTS (outf, dregs_hi (dst0));
3085 OUTS (outf, " = ");
3086 OUTS (outf, dregs (src0));
3087 OUTS (outf, " - ");
3088 OUTS (outf, dregs (src1));
3089 OUTS (outf, " (RND20)");
3090 }
3091 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3092 {
3093 OUTS (outf, dregs_hi (dst0));
3094 OUTS (outf, " = ");
3095 OUTS (outf, dregs (src0));
3096 OUTS (outf, " + ");
3097 OUTS (outf, dregs (src1));
3098 OUTS (outf, " (RND20)");
3099 }
3100 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3101 {
3102 OUTS (outf, dregs_lo (dst0));
3103 OUTS (outf, " = ");
3104 OUTS (outf, dregs (src0));
3105 OUTS (outf, " - ");
3106 OUTS (outf, dregs (src1));
3107 OUTS (outf, " (RND12)");
3108 }
3109 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3110 {
3111 OUTS (outf, dregs_lo (dst0));
3112 OUTS (outf, " = ");
3113 OUTS (outf, dregs (src0));
3114 OUTS (outf, " + ");
3115 OUTS (outf, dregs (src1));
3116 OUTS (outf, " (RND12)");
3117 }
3118 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3119 {
3120 OUTS (outf, dregs_lo (dst0));
3121 OUTS (outf, " = ");
3122 OUTS (outf, dregs (src0));
3123 OUTS (outf, " - ");
3124 OUTS (outf, dregs (src1));
3125 OUTS (outf, " (RND20)");
3126 }
3127 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3128 {
3129 OUTS (outf, dregs_hi (dst0));
3130 OUTS (outf, " = ");
3131 OUTS (outf, dregs (src0));
3132 OUTS (outf, " + ");
3133 OUTS (outf, dregs (src1));
3134 OUTS (outf, " (RND12)");
3135 }
3136 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3137 {
3138 OUTS (outf, dregs_lo (dst0));
3139 OUTS (outf, " = ");
3140 OUTS (outf, dregs (src0));
3141 OUTS (outf, " + ");
3142 OUTS (outf, dregs (src1));
3143 OUTS (outf, " (RND20)");
3144 }
3145 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3146 {
3147 OUTS (outf, dregs_hi (dst0));
3148 OUTS (outf, " = ");
3149 OUTS (outf, dregs (src0));
3150 OUTS (outf, " - ");
3151 OUTS (outf, dregs (src1));
3152 OUTS (outf, " (RND12)");
3153 }
3154 else if (HL == 1 && aop == 0 && aopcde == 2)
3155 {
3156 OUTS (outf, dregs_hi (dst0));
3157 OUTS (outf, " = ");
3158 OUTS (outf, dregs_lo (src0));
3159 OUTS (outf, " + ");
3160 OUTS (outf, dregs_lo (src1));
3161 amod1 (s, x, outf);
3162 }
3163 else if (HL == 1 && aop == 1 && aopcde == 2)
3164 {
3165 OUTS (outf, dregs_hi (dst0));
3166 OUTS (outf, " = ");
3167 OUTS (outf, dregs_lo (src0));
3168 OUTS (outf, " + ");
3169 OUTS (outf, dregs_hi (src1));
3170 amod1 (s, x, outf);
3171 }
3172 else if (HL == 1 && aop == 2 && aopcde == 2)
3173 {
3174 OUTS (outf, dregs_hi (dst0));
3175 OUTS (outf, " = ");
3176 OUTS (outf, dregs_hi (src0));
3177 OUTS (outf, " + ");
3178 OUTS (outf, dregs_lo (src1));
3179 amod1 (s, x, outf);
3180 }
3181 else if (HL == 1 && aop == 3 && aopcde == 2)
3182 {
3183 OUTS (outf, dregs_hi (dst0));
3184 OUTS (outf, " = ");
3185 OUTS (outf, dregs_hi (src0));
3186 OUTS (outf, " + ");
3187 OUTS (outf, dregs_hi (src1));
3188 amod1 (s, x, outf);
3189 }
3190 else if (HL == 0 && aop == 0 && aopcde == 3)
3191 {
3192 OUTS (outf, dregs_lo (dst0));
3193 OUTS (outf, " = ");
3194 OUTS (outf, dregs_lo (src0));
3195 OUTS (outf, " - ");
3196 OUTS (outf, dregs_lo (src1));
3197 amod1 (s, x, outf);
3198 }
3199 else if (HL == 0 && aop == 1 && aopcde == 3)
3200 {
3201 OUTS (outf, dregs_lo (dst0));
3202 OUTS (outf, " = ");
3203 OUTS (outf, dregs_lo (src0));
3204 OUTS (outf, " - ");
3205 OUTS (outf, dregs_hi (src1));
3206 amod1 (s, x, outf);
3207 }
3208 else if (HL == 0 && aop == 3 && aopcde == 2)
3209 {
3210 OUTS (outf, dregs_lo (dst0));
3211 OUTS (outf, " = ");
3212 OUTS (outf, dregs_hi (src0));
3213 OUTS (outf, " + ");
3214 OUTS (outf, dregs_hi (src1));
3215 amod1 (s, x, outf);
3216 }
3217 else if (HL == 1 && aop == 0 && aopcde == 3)
3218 {
3219 OUTS (outf, dregs_hi (dst0));
3220 OUTS (outf, " = ");
3221 OUTS (outf, dregs_lo (src0));
3222 OUTS (outf, " - ");
3223 OUTS (outf, dregs_lo (src1));
3224 amod1 (s, x, outf);
3225 }
3226 else if (HL == 1 && aop == 1 && aopcde == 3)
3227 {
3228 OUTS (outf, dregs_hi (dst0));
3229 OUTS (outf, " = ");
3230 OUTS (outf, dregs_lo (src0));
3231 OUTS (outf, " - ");
3232 OUTS (outf, dregs_hi (src1));
3233 amod1 (s, x, outf);
3234 }
3235 else if (HL == 1 && aop == 2 && aopcde == 3)
3236 {
3237 OUTS (outf, dregs_hi (dst0));
3238 OUTS (outf, " = ");
3239 OUTS (outf, dregs_hi (src0));
3240 OUTS (outf, " - ");
3241 OUTS (outf, dregs_lo (src1));
3242 amod1 (s, x, outf);
3243 }
3244 else if (HL == 1 && aop == 3 && aopcde == 3)
3245 {
3246 OUTS (outf, dregs_hi (dst0));
3247 OUTS (outf, " = ");
3248 OUTS (outf, dregs_hi (src0));
3249 OUTS (outf, " - ");
3250 OUTS (outf, dregs_hi (src1));
3251 amod1 (s, x, outf);
3252 }
3253 else if (HL == 0 && aop == 2 && aopcde == 2)
3254 {
3255 OUTS (outf, dregs_lo (dst0));
3256 OUTS (outf, " = ");
3257 OUTS (outf, dregs_hi (src0));
3258 OUTS (outf, " + ");
3259 OUTS (outf, dregs_lo (src1));
3260 amod1 (s, x, outf);
3261 }
3262 else if (HL == 0 && aop == 1 && aopcde == 2)
3263 {
3264 OUTS (outf, dregs_lo (dst0));
3265 OUTS (outf, " = ");
3266 OUTS (outf, dregs_lo (src0));
3267 OUTS (outf, " + ");
3268 OUTS (outf, dregs_hi (src1));
3269 amod1 (s, x, outf);
3270 }
3271 else if (HL == 0 && aop == 2 && aopcde == 3)
3272 {
3273 OUTS (outf, dregs_lo (dst0));
3274 OUTS (outf, " = ");
3275 OUTS (outf, dregs_hi (src0));
3276 OUTS (outf, " - ");
3277 OUTS (outf, dregs_lo (src1));
3278 amod1 (s, x, outf);
3279 }
3280 else if (HL == 0 && aop == 3 && aopcde == 3)
3281 {
3282 OUTS (outf, dregs_lo (dst0));
3283 OUTS (outf, " = ");
3284 OUTS (outf, dregs_hi (src0));
3285 OUTS (outf, " - ");
3286 OUTS (outf, dregs_hi (src1));
3287 amod1 (s, x, outf);
3288 }
3289 else if (HL == 0 && aop == 0 && aopcde == 2)
3290 {
3291 OUTS (outf, dregs_lo (dst0));
3292 OUTS (outf, " = ");
3293 OUTS (outf, dregs_lo (src0));
3294 OUTS (outf, " + ");
3295 OUTS (outf, dregs_lo (src1));
3296 amod1 (s, x, outf);
3297 }
3298 else if (aop == 0 && aopcde == 9 && s == 1)
3299 {
3300 OUTS (outf, "A0 = ");
3301 OUTS (outf, dregs (src0));
3302 }
3303 else if (aop == 3 && aopcde == 11 && s == 0)
3304 OUTS (outf, "A0 -= A1");
3305
3306 else if (aop == 3 && aopcde == 11 && s == 1)
3307 OUTS (outf, "A0 -= A1 (W32)");
3308
3309 else if (aop == 3 && aopcde == 22 && HL == 1)
3310 {
3311 OUTS (outf, dregs (dst0));
3312 OUTS (outf, " = BYTEOP2M (");
3313 OUTS (outf, dregs (src0 + 1));
3314 OUTS (outf, ":");
3315 OUTS (outf, imm5 (src0));
3316 OUTS (outf, ", ");
3317 OUTS (outf, dregs (src1 + 1));
3318 OUTS (outf, ":");
3319 OUTS (outf, imm5 (src1));
3320 OUTS (outf, ") (TH");
3321 if (s == 1)
3322 OUTS (outf, ", R)");
3323 else
3324 OUTS (outf, ")");
3325 }
3326 else if (aop == 3 && aopcde == 22 && HL == 0)
3327 {
3328 OUTS (outf, dregs (dst0));
3329 OUTS (outf, " = BYTEOP2M (");
3330 OUTS (outf, dregs (src0 + 1));
3331 OUTS (outf, ":");
3332 OUTS (outf, imm5 (src0));
3333 OUTS (outf, ", ");
3334 OUTS (outf, dregs (src1 + 1));
3335 OUTS (outf, ":");
3336 OUTS (outf, imm5 (src1));
3337 OUTS (outf, ") (TL");
3338 if (s == 1)
3339 OUTS (outf, ", R)");
3340 else
3341 OUTS (outf, ")");
3342 }
3343 else if (aop == 2 && aopcde == 22 && HL == 1)
3344 {
3345 OUTS (outf, dregs (dst0));
3346 OUTS (outf, " = BYTEOP2M (");
3347 OUTS (outf, dregs (src0 + 1));
3348 OUTS (outf, ":");
3349 OUTS (outf, imm5 (src0));
3350 OUTS (outf, ", ");
3351 OUTS (outf, dregs (src1 + 1));
3352 OUTS (outf, ":");
3353 OUTS (outf, imm5 (src1));
3354 OUTS (outf, ") (RNDH");
3355 if (s == 1)
3356 OUTS (outf, ", R)");
3357 else
3358 OUTS (outf, ")");
3359 }
3360 else if (aop == 2 && aopcde == 22 && HL == 0)
3361 {
3362 OUTS (outf, dregs (dst0));
3363 OUTS (outf, " = BYTEOP2M (");
3364 OUTS (outf, dregs (src0 + 1));
3365 OUTS (outf, ":");
3366 OUTS (outf, imm5 (src0));
3367 OUTS (outf, ", ");
3368 OUTS (outf, dregs (src1 + 1));
3369 OUTS (outf, ":");
3370 OUTS (outf, imm5 (src1));
3371 OUTS (outf, ") (RNDL");
3372 if (s == 1)
3373 OUTS (outf, ", R)");
3374 else
3375 OUTS (outf, ")");
3376 }
3377 else if (aop == 1 && aopcde == 22 && HL == 1)
3378 {
3379 OUTS (outf, dregs (dst0));
3380 OUTS (outf, " = BYTEOP2P (");
3381 OUTS (outf, dregs (src0 + 1));
3382 OUTS (outf, ":");
3383 OUTS (outf, imm5d (src0));
3384 OUTS (outf, ", ");
3385 OUTS (outf, dregs (src1 + 1));
3386 OUTS (outf, ":");
3387 OUTS (outf, imm5d (src1));
3388 OUTS (outf, ") (TH");
3389 if (s == 1)
3390 OUTS (outf, ", R)");
3391 else
3392 OUTS (outf, ")");
3393 }
3394 else if (aop == 1 && aopcde == 22 && HL == 0)
3395 {
3396 OUTS (outf, dregs (dst0));
3397 OUTS (outf, " = BYTEOP2P (");
3398 OUTS (outf, dregs (src0 + 1));
3399 OUTS (outf, ":");
3400 OUTS (outf, imm5d (src0));
3401 OUTS (outf, ", ");
3402 OUTS (outf, dregs (src1 + 1));
3403 OUTS (outf, ":");
3404 OUTS (outf, imm5d (src1));
3405 OUTS (outf, ") (TL");
3406 if (s == 1)
3407 OUTS (outf, ", R)");
3408 else
3409 OUTS (outf, ")");
3410 }
3411 else if (aop == 0 && aopcde == 22 && HL == 1)
3412 {
3413 OUTS (outf, dregs (dst0));
3414 OUTS (outf, " = BYTEOP2P (");
3415 OUTS (outf, dregs (src0 + 1));
3416 OUTS (outf, ":");
3417 OUTS (outf, imm5d (src0));
3418 OUTS (outf, ", ");
3419 OUTS (outf, dregs (src1 + 1));
3420 OUTS (outf, ":");
3421 OUTS (outf, imm5d (src1));
3422 OUTS (outf, ") (RNDH");
3423 if (s == 1)
3424 OUTS (outf, ", R)");
3425 else
3426 OUTS (outf, ")");
3427 }
3428 else if (aop == 0 && aopcde == 22 && HL == 0)
3429 {
3430 OUTS (outf, dregs (dst0));
3431 OUTS (outf, " = BYTEOP2P (");
3432 OUTS (outf, dregs (src0 + 1));
3433 OUTS (outf, ":");
3434 OUTS (outf, imm5d (src0));
3435 OUTS (outf, ", ");
3436 OUTS (outf, dregs (src1 + 1));
3437 OUTS (outf, ":");
3438 OUTS (outf, imm5d (src1));
3439 OUTS (outf, ") (RNDL");
3440 if (s == 1)
3441 OUTS (outf, ", R)");
3442 else
3443 OUTS (outf, ")");
3444 }
3445 else if (aop == 0 && s == 0 && aopcde == 8)
3446 OUTS (outf, "A0 = 0");
3447
3448 else if (aop == 0 && s == 1 && aopcde == 8)
3449 OUTS (outf, "A0 = A0 (S)");
3450
3451 else if (aop == 1 && s == 0 && aopcde == 8)
3452 OUTS (outf, "A1 = 0");
3453
3454 else if (aop == 1 && s == 1 && aopcde == 8)
3455 OUTS (outf, "A1 = A1 (S)");
3456
3457 else if (aop == 2 && s == 0 && aopcde == 8)
3458 OUTS (outf, "A1 = A0 = 0");
3459
3460 else if (aop == 2 && s == 1 && aopcde == 8)
3461 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3462
3463 else if (aop == 3 && s == 0 && aopcde == 8)
3464 OUTS (outf, "A0 = A1");
3465
3466 else if (aop == 3 && s == 1 && aopcde == 8)
3467 OUTS (outf, "A1 = A0");
3468
3469 else if (aop == 1 && aopcde == 9 && s == 0)
3470 {
3471 OUTS (outf, "A0.X = ");
3472 OUTS (outf, dregs_lo (src0));
3473 }
3474 else if (aop == 1 && HL == 0 && aopcde == 11)
3475 {
3476 OUTS (outf, dregs_lo (dst0));
3477 OUTS (outf, " = (A0 += A1)");
3478 }
3479 else if (aop == 3 && HL == 0 && aopcde == 16)
3480 OUTS (outf, "A1 = ABS A0, A0 = ABS A0");
3481
3482 else if (aop == 0 && aopcde == 23 && HL == 1)
3483 {
3484 OUTS (outf, dregs (dst0));
3485 OUTS (outf, " = BYTEOP3P (");
3486 OUTS (outf, dregs (src0 + 1));
3487 OUTS (outf, ":");
3488 OUTS (outf, imm5d (src0));
3489 OUTS (outf, ", ");
3490 OUTS (outf, dregs (src1 + 1));
3491 OUTS (outf, ":");
3492 OUTS (outf, imm5d (src1));
3493 OUTS (outf, ") (HI");
3494 if (s == 1)
3495 OUTS (outf, ", R)");
3496 else
3497 OUTS (outf, ")");
3498 }
3499 else if (aop == 3 && aopcde == 9 && s == 0)
3500 {
3501 OUTS (outf, "A1.X = ");
3502 OUTS (outf, dregs_lo (src0));
3503 }
3504 else if (aop == 1 && HL == 1 && aopcde == 16)
3505 OUTS (outf, "A1 = ABS A1");
3506
3507 else if (aop == 0 && HL == 1 && aopcde == 16)
3508 OUTS (outf, "A1 = ABS A0");
3509
3510 else if (aop == 2 && aopcde == 9 && s == 1)
3511 {
3512 OUTS (outf, "A1 = ");
3513 OUTS (outf, dregs (src0));
3514 }
3515 else if (HL == 0 && aop == 3 && aopcde == 12)
3516 {
3517 OUTS (outf, dregs_lo (dst0));
3518 OUTS (outf, " = ");
3519 OUTS (outf, dregs (src0));
3520 OUTS (outf, " (RND)");
3521 }
3522 else if (aop == 1 && HL == 0 && aopcde == 16)
3523 OUTS (outf, "A0 = ABS A1");
3524
3525 else if (aop == 0 && HL == 0 && aopcde == 16)
3526 OUTS (outf, "A0 = ABS A0");
3527
3528 else if (aop == 3 && HL == 0 && aopcde == 15)
3529 {
3530 OUTS (outf, dregs (dst0));
3531 OUTS (outf, " = -");
3532 OUTS (outf, dregs (src0));
3533 OUTS (outf, " (V)");
3534 }
3535 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3536 {
3537 OUTS (outf, dregs (dst0));
3538 OUTS (outf, " = -");
3539 OUTS (outf, dregs (src0));
3540 OUTS (outf, " (S)");
3541 }
3542 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3543 {
3544 OUTS (outf, dregs (dst0));
3545 OUTS (outf, " = -");
3546 OUTS (outf, dregs (src0));
3547 OUTS (outf, " (NS)");
3548 }
3549 else if (aop == 1 && HL == 1 && aopcde == 11)
3550 {
3551 OUTS (outf, dregs_hi (dst0));
3552 OUTS (outf, " = (A0 += A1)");
3553 }
3554 else if (aop == 2 && aopcde == 11 && s == 0)
3555 OUTS (outf, "A0 += A1");
3556
3557 else if (aop == 2 && aopcde == 11 && s == 1)
3558 OUTS (outf, "A0 += A1 (W32)");
3559
3560 else if (aop == 3 && HL == 0 && aopcde == 14)
3561 OUTS (outf, "A1 = -A1, A0 = -A0");
3562
3563 else if (HL == 1 && aop == 3 && aopcde == 12)
3564 {
3565 OUTS (outf, dregs_hi (dst0));
3566 OUTS (outf, " = ");
3567 OUTS (outf, dregs (src0));
3568 OUTS (outf, " (RND)");
3569 }
3570 else if (aop == 0 && aopcde == 23 && HL == 0)
3571 {
3572 OUTS (outf, dregs (dst0));
3573 OUTS (outf, " = BYTEOP3P (");
3574 OUTS (outf, dregs (src0 + 1));
3575 OUTS (outf, ":");
3576 OUTS (outf, imm5d (src0));
3577 OUTS (outf, ", ");
3578 OUTS (outf, dregs (src1 + 1));
3579 OUTS (outf, ":");
3580 OUTS (outf, imm5d (src1));
3581 OUTS (outf, ") (LO");
3582 if (s == 1)
3583 OUTS (outf, ", R)");
3584 else
3585 OUTS (outf, ")");
3586 }
3587 else if (aop == 0 && HL == 0 && aopcde == 14)
3588 OUTS (outf, "A0 = -A0");
3589
3590 else if (aop == 1 && HL == 0 && aopcde == 14)
3591 OUTS (outf, "A0 = -A1");
3592
3593 else if (aop == 0 && HL == 1 && aopcde == 14)
3594 OUTS (outf, "A1 = -A0");
3595
3596 else if (aop == 1 && HL == 1 && aopcde == 14)
3597 OUTS (outf, "A1 = -A1");
3598
3599 else if (aop == 0 && aopcde == 12)
3600 {
3601 OUTS (outf, dregs_hi (dst0));
3602 OUTS (outf, " = ");
3603 OUTS (outf, dregs_lo (dst0));
3604 OUTS (outf, " = SIGN (");
3605 OUTS (outf, dregs_hi (src0));
3606 OUTS (outf, ") * ");
3607 OUTS (outf, dregs_hi (src1));
3608 OUTS (outf, " + SIGN (");
3609 OUTS (outf, dregs_lo (src0));
3610 OUTS (outf, ") * ");
3611 OUTS (outf, dregs_lo (src1));
3612 }
3613 else if (aop == 2 && aopcde == 0)
3614 {
3615 OUTS (outf, dregs (dst0));
3616 OUTS (outf, " = ");
3617 OUTS (outf, dregs (src0));
3618 OUTS (outf, " -|+ ");
3619 OUTS (outf, dregs (src1));
3620 amod0 (s, x, outf);
3621 }
3622 else if (aop == 1 && aopcde == 12)
3623 {
3624 OUTS (outf, dregs (dst1));
3625 OUTS (outf, " = A1.L + A1.H, ");
3626 OUTS (outf, dregs (dst0));
3627 OUTS (outf, " = A0.L + A0.H");
3628 }
3629 else if (aop == 2 && aopcde == 4)
3630 {
3631 OUTS (outf, dregs (dst1));
3632 OUTS (outf, " = ");
3633 OUTS (outf, dregs (src0));
3634 OUTS (outf, " + ");
3635 OUTS (outf, dregs (src1));
3636 OUTS (outf, ", ");
3637 OUTS (outf, dregs (dst0));
3638 OUTS (outf, " = ");
3639 OUTS (outf, dregs (src0));
3640 OUTS (outf, " - ");
3641 OUTS (outf, dregs (src1));
3642 amod1 (s, x, outf);
3643 }
3644 else if (HL == 0 && aopcde == 1)
3645 {
3646 OUTS (outf, dregs (dst1));
3647 OUTS (outf, " = ");
3648 OUTS (outf, dregs (src0));
3649 OUTS (outf, " +|+ ");
3650 OUTS (outf, dregs (src1));
3651 OUTS (outf, ", ");
3652 OUTS (outf, dregs (dst0));
3653 OUTS (outf, " = ");
3654 OUTS (outf, dregs (src0));
3655 OUTS (outf, " -|- ");
3656 OUTS (outf, dregs (src1));
3657 amod0amod2 (s, x, aop, outf);
3658 }
3659 else if (aop == 0 && aopcde == 11)
3660 {
3661 OUTS (outf, dregs (dst0));
3662 OUTS (outf, " = (A0 += A1)");
3663 }
3664 else if (aop == 0 && aopcde == 10)
3665 {
3666 OUTS (outf, dregs_lo (dst0));
3667 OUTS (outf, " = A0.X");
3668 }
3669 else if (aop == 1 && aopcde == 10)
3670 {
3671 OUTS (outf, dregs_lo (dst0));
3672 OUTS (outf, " = A1.X");
3673 }
3674 else if (aop == 1 && aopcde == 0)
3675 {
3676 OUTS (outf, dregs (dst0));
3677 OUTS (outf, " = ");
3678 OUTS (outf, dregs (src0));
3679 OUTS (outf, " +|- ");
3680 OUTS (outf, dregs (src1));
3681 amod0 (s, x, outf);
3682 }
3683 else if (aop == 3 && aopcde == 0)
3684 {
3685 OUTS (outf, dregs (dst0));
3686 OUTS (outf, " = ");
3687 OUTS (outf, dregs (src0));
3688 OUTS (outf, " -|- ");
3689 OUTS (outf, dregs (src1));
3690 amod0 (s, x, outf);
3691 }
3692 else if (aop == 1 && aopcde == 4)
3693 {
3694 OUTS (outf, dregs (dst0));
3695 OUTS (outf, " = ");
3696 OUTS (outf, dregs (src0));
3697 OUTS (outf, " - ");
3698 OUTS (outf, dregs (src1));
3699 amod1 (s, x, outf);
3700 }
3701 else if (aop == 0 && aopcde == 17)
3702 {
3703 OUTS (outf, dregs (dst1));
3704 OUTS (outf, " = A1 + A0, ");
3705 OUTS (outf, dregs (dst0));
3706 OUTS (outf, " = A1 - A0");
3707 amod1 (s, x, outf);
3708 }
3709 else if (aop == 1 && aopcde == 17)
3710 {
3711 OUTS (outf, dregs (dst1));
3712 OUTS (outf, " = A0 + A1, ");
3713 OUTS (outf, dregs (dst0));
3714 OUTS (outf, " = A0 - A1");
3715 amod1 (s, x, outf);
3716 }
3717 else if (aop == 0 && aopcde == 18)
3718 {
3719 OUTS (outf, "SAA (");
3720 OUTS (outf, dregs (src0 + 1));
3721 OUTS (outf, ":");
3722 OUTS (outf, imm5d (src0));
3723 OUTS (outf, ", ");
3724 OUTS (outf, dregs (src1 + 1));
3725 OUTS (outf, ":");
3726 OUTS (outf, imm5d (src1));
3727 OUTS (outf, ")");
3728 aligndir (s, outf);
3729 }
3730 else if (aop == 3 && aopcde == 18)
3731 OUTS (outf, "DISALGNEXCPT");
3732
3733 else if (aop == 0 && aopcde == 20)
3734 {
3735 OUTS (outf, dregs (dst0));
3736 OUTS (outf, " = BYTEOP1P (");
3737 OUTS (outf, dregs (src0 + 1));
3738 OUTS (outf, ":");
3739 OUTS (outf, imm5d (src0));
3740 OUTS (outf, ", ");
3741 OUTS (outf, dregs (src1 + 1));
3742 OUTS (outf, ":");
3743 OUTS (outf, imm5d (src1));
3744 OUTS (outf, ")");
3745 aligndir (s, outf);
3746 }
3747 else if (aop == 1 && aopcde == 20)
3748 {
3749 OUTS (outf, dregs (dst0));
3750 OUTS (outf, " = BYTEOP1P (");
3751 OUTS (outf, dregs (src0 + 1));
3752 OUTS (outf, ":");
3753 OUTS (outf, imm5d (src0));
3754 OUTS (outf, ", ");
3755 OUTS (outf, dregs (src1 + 1));
3756 OUTS (outf, ":");
3757 OUTS (outf, imm5d (src1));
3758 OUTS (outf, ") (T");
3759 if (s == 1)
3760 OUTS (outf, ", R)");
3761 else
3762 OUTS (outf, ")");
3763 }
3764 else if (aop == 0 && aopcde == 21)
3765 {
3766 OUTS (outf, "(");
3767 OUTS (outf, dregs (dst1));
3768 OUTS (outf, ", ");
3769 OUTS (outf, dregs (dst0));
3770 OUTS (outf, ") = BYTEOP16P (");
3771 OUTS (outf, dregs (src0 + 1));
3772 OUTS (outf, ":");
3773 OUTS (outf, imm5d (src0));
3774 OUTS (outf, ", ");
3775 OUTS (outf, dregs (src1 + 1));
3776 OUTS (outf, ":");
3777 OUTS (outf, imm5d (src1));
3778 OUTS (outf, ")");
3779 aligndir (s, outf);
3780 }
3781 else if (aop == 1 && aopcde == 21)
3782 {
3783 OUTS (outf, "(");
3784 OUTS (outf, dregs (dst1));
3785 OUTS (outf, ", ");
3786 OUTS (outf, dregs (dst0));
3787 OUTS (outf, ") = BYTEOP16M (");
3788 OUTS (outf, dregs (src0 + 1));
3789 OUTS (outf, ":");
3790 OUTS (outf, imm5d (src0));
3791 OUTS (outf, ", ");
3792 OUTS (outf, dregs (src1 + 1));
3793 OUTS (outf, ":");
3794 OUTS (outf, imm5d (src1));
3795 OUTS (outf, ")");
3796 aligndir (s, outf);
3797 }
3798 else if (aop == 2 && aopcde == 7)
3799 {
3800 OUTS (outf, dregs (dst0));
3801 OUTS (outf, " = ABS ");
3802 OUTS (outf, dregs (src0));
3803 }
3804 else if (aop == 1 && aopcde == 7)
3805 {
3806 OUTS (outf, dregs (dst0));
3807 OUTS (outf, " = MIN (");
3808 OUTS (outf, dregs (src0));
3809 OUTS (outf, ", ");
3810 OUTS (outf, dregs (src1));
3811 OUTS (outf, ")");
3812 }
3813 else if (aop == 0 && aopcde == 7)
3814 {
3815 OUTS (outf, dregs (dst0));
3816 OUTS (outf, " = MAX (");
3817 OUTS (outf, dregs (src0));
3818 OUTS (outf, ", ");
3819 OUTS (outf, dregs (src1));
3820 OUTS (outf, ")");
3821 }
3822 else if (aop == 2 && aopcde == 6)
3823 {
3824 OUTS (outf, dregs (dst0));
3825 OUTS (outf, " = ABS ");
3826 OUTS (outf, dregs (src0));
3827 OUTS (outf, " (V)");
3828 }
3829 else if (aop == 1 && aopcde == 6)
3830 {
3831 OUTS (outf, dregs (dst0));
3832 OUTS (outf, " = MIN (");
3833 OUTS (outf, dregs (src0));
3834 OUTS (outf, ", ");
3835 OUTS (outf, dregs (src1));
3836 OUTS (outf, ") (V)");
3837 }
3838 else if (aop == 0 && aopcde == 6)
3839 {
3840 OUTS (outf, dregs (dst0));
3841 OUTS (outf, " = MAX (");
3842 OUTS (outf, dregs (src0));
3843 OUTS (outf, ", ");
3844 OUTS (outf, dregs (src1));
3845 OUTS (outf, ") (V)");
3846 }
3847 else if (HL == 1 && aopcde == 1)
3848 {
3849 OUTS (outf, dregs (dst1));
3850 OUTS (outf, " = ");
3851 OUTS (outf, dregs (src0));
3852 OUTS (outf, " +|- ");
3853 OUTS (outf, dregs (src1));
3854 OUTS (outf, ", ");
3855 OUTS (outf, dregs (dst0));
3856 OUTS (outf, " = ");
3857 OUTS (outf, dregs (src0));
3858 OUTS (outf, " -|+ ");
3859 OUTS (outf, dregs (src1));
3860 amod0amod2 (s, x, aop, outf);
3861 }
3862 else if (aop == 0 && aopcde == 4)
3863 {
3864 OUTS (outf, dregs (dst0));
3865 OUTS (outf, " = ");
3866 OUTS (outf, dregs (src0));
3867 OUTS (outf, " + ");
3868 OUTS (outf, dregs (src1));
3869 amod1 (s, x, outf);
3870 }
3871 else if (aop == 0 && aopcde == 0)
3872 {
3873 OUTS (outf, dregs (dst0));
3874 OUTS (outf, " = ");
3875 OUTS (outf, dregs (src0));
3876 OUTS (outf, " +|+ ");
3877 OUTS (outf, dregs (src1));
3878 amod0 (s, x, outf);
3879 }
3880 else if (aop == 0 && aopcde == 24)
3881 {
3882 OUTS (outf, dregs (dst0));
3883 OUTS (outf, " = BYTEPACK (");
3884 OUTS (outf, dregs (src0));
3885 OUTS (outf, ", ");
3886 OUTS (outf, dregs (src1));
3887 OUTS (outf, ")");
3888 }
3889 else if (aop == 1 && aopcde == 24)
3890 {
3891 OUTS (outf, "(");
3892 OUTS (outf, dregs (dst1));
3893 OUTS (outf, ", ");
3894 OUTS (outf, dregs (dst0));
3895 OUTS (outf, ") = BYTEUNPACK ");
3896 OUTS (outf, dregs (src0 + 1));
3897 OUTS (outf, ":");
3898 OUTS (outf, imm5d (src0));
3899 aligndir (s, outf);
3900 }
3901 else if (aopcde == 13)
3902 {
3903 OUTS (outf, "(");
3904 OUTS (outf, dregs (dst1));
3905 OUTS (outf, ", ");
3906 OUTS (outf, dregs (dst0));
3907 OUTS (outf, ") = SEARCH ");
3908 OUTS (outf, dregs (src0));
3909 OUTS (outf, " (");
3910 searchmod (aop, outf);
3911 OUTS (outf, ")");
3912 }
3913 else
3914 return 0;
3915
3916 return 4;
3917 }
3918
3919 static int
3920 decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3921 {
3922 /* dsp32shift
3923 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3924 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3925 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3926 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3927 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3928 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3929 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3930 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3931 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3932 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3933 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3934
3935 if (HLs == 0 && sop == 0 && sopcde == 0)
3936 {
3937 OUTS (outf, dregs_lo (dst0));
3938 OUTS (outf, " = ASHIFT ");
3939 OUTS (outf, dregs_lo (src1));
3940 OUTS (outf, " BY ");
3941 OUTS (outf, dregs_lo (src0));
3942 }
3943 else if (HLs == 1 && sop == 0 && sopcde == 0)
3944 {
3945 OUTS (outf, dregs_lo (dst0));
3946 OUTS (outf, " = ASHIFT ");
3947 OUTS (outf, dregs_hi (src1));
3948 OUTS (outf, " BY ");
3949 OUTS (outf, dregs_lo (src0));
3950 }
3951 else if (HLs == 2 && sop == 0 && sopcde == 0)
3952 {
3953 OUTS (outf, dregs_hi (dst0));
3954 OUTS (outf, " = ASHIFT ");
3955 OUTS (outf, dregs_lo (src1));
3956 OUTS (outf, " BY ");
3957 OUTS (outf, dregs_lo (src0));
3958 }
3959 else if (HLs == 3 && sop == 0 && sopcde == 0)
3960 {
3961 OUTS (outf, dregs_hi (dst0));
3962 OUTS (outf, " = ASHIFT ");
3963 OUTS (outf, dregs_hi (src1));
3964 OUTS (outf, " BY ");
3965 OUTS (outf, dregs_lo (src0));
3966 }
3967 else if (HLs == 0 && sop == 1 && sopcde == 0)
3968 {
3969 OUTS (outf, dregs_lo (dst0));
3970 OUTS (outf, " = ASHIFT ");
3971 OUTS (outf, dregs_lo (src1));
3972 OUTS (outf, " BY ");
3973 OUTS (outf, dregs_lo (src0));
3974 OUTS (outf, " (S)");
3975 }
3976 else if (HLs == 1 && sop == 1 && sopcde == 0)
3977 {
3978 OUTS (outf, dregs_lo (dst0));
3979 OUTS (outf, " = ASHIFT ");
3980 OUTS (outf, dregs_hi (src1));
3981 OUTS (outf, " BY ");
3982 OUTS (outf, dregs_lo (src0));
3983 OUTS (outf, " (S)");
3984 }
3985 else if (HLs == 2 && sop == 1 && sopcde == 0)
3986 {
3987 OUTS (outf, dregs_hi (dst0));
3988 OUTS (outf, " = ASHIFT ");
3989 OUTS (outf, dregs_lo (src1));
3990 OUTS (outf, " BY ");
3991 OUTS (outf, dregs_lo (src0));
3992 OUTS (outf, " (S)");
3993 }
3994 else if (HLs == 3 && sop == 1 && sopcde == 0)
3995 {
3996 OUTS (outf, dregs_hi (dst0));
3997 OUTS (outf, " = ASHIFT ");
3998 OUTS (outf, dregs_hi (src1));
3999 OUTS (outf, " BY ");
4000 OUTS (outf, dregs_lo (src0));
4001 OUTS (outf, " (S)");
4002 }
4003 else if (sop == 2 && sopcde == 0)
4004 {
4005 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
4006 OUTS (outf, " = LSHIFT ");
4007 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
4008 OUTS (outf, " BY ");
4009 OUTS (outf, dregs_lo (src0));
4010 }
4011 else if (sop == 0 && sopcde == 3)
4012 {
4013 OUTS (outf, acc01);
4014 OUTS (outf, " = ASHIFT ");
4015 OUTS (outf, acc01);
4016 OUTS (outf, " BY ");
4017 OUTS (outf, dregs_lo (src0));
4018 }
4019 else if (sop == 1 && sopcde == 3)
4020 {
4021 OUTS (outf, acc01);
4022 OUTS (outf, " = LSHIFT ");
4023 OUTS (outf, acc01);
4024 OUTS (outf, " BY ");
4025 OUTS (outf, dregs_lo (src0));
4026 }
4027 else if (sop == 2 && sopcde == 3)
4028 {
4029 OUTS (outf, acc01);
4030 OUTS (outf, " = ROT ");
4031 OUTS (outf, acc01);
4032 OUTS (outf, " BY ");
4033 OUTS (outf, dregs_lo (src0));
4034 }
4035 else if (sop == 3 && sopcde == 3)
4036 {
4037 OUTS (outf, dregs (dst0));
4038 OUTS (outf, " = ROT ");
4039 OUTS (outf, dregs (src1));
4040 OUTS (outf, " BY ");
4041 OUTS (outf, dregs_lo (src0));
4042 }
4043 else if (sop == 1 && sopcde == 1)
4044 {
4045 OUTS (outf, dregs (dst0));
4046 OUTS (outf, " = ASHIFT ");
4047 OUTS (outf, dregs (src1));
4048 OUTS (outf, " BY ");
4049 OUTS (outf, dregs_lo (src0));
4050 OUTS (outf, " (V, S)");
4051 }
4052 else if (sop == 0 && sopcde == 1)
4053 {
4054 OUTS (outf, dregs (dst0));
4055 OUTS (outf, " = ASHIFT ");
4056 OUTS (outf, dregs (src1));
4057 OUTS (outf, " BY ");
4058 OUTS (outf, dregs_lo (src0));
4059 OUTS (outf, " (V)");
4060 }
4061 else if (sop == 0 && sopcde == 2)
4062 {
4063 OUTS (outf, dregs (dst0));
4064 OUTS (outf, " = ASHIFT ");
4065 OUTS (outf, dregs (src1));
4066 OUTS (outf, " BY ");
4067 OUTS (outf, dregs_lo (src0));
4068 }
4069 else if (sop == 1 && sopcde == 2)
4070 {
4071 OUTS (outf, dregs (dst0));
4072 OUTS (outf, " = ASHIFT ");
4073 OUTS (outf, dregs (src1));
4074 OUTS (outf, " BY ");
4075 OUTS (outf, dregs_lo (src0));
4076 OUTS (outf, " (S)");
4077 }
4078 else if (sop == 2 && sopcde == 2)
4079 {
4080 OUTS (outf, dregs (dst0));
4081 OUTS (outf, " = LSHIFT ");
4082 OUTS (outf, dregs (src1));
4083 OUTS (outf, " BY ");
4084 OUTS (outf, dregs_lo (src0));
4085 }
4086 else if (sop == 3 && sopcde == 2)
4087 {
4088 OUTS (outf, dregs (dst0));
4089 OUTS (outf, " = ROT ");
4090 OUTS (outf, dregs (src1));
4091 OUTS (outf, " BY ");
4092 OUTS (outf, dregs_lo (src0));
4093 }
4094 else if (sop == 2 && sopcde == 1)
4095 {
4096 OUTS (outf, dregs (dst0));
4097 OUTS (outf, " = LSHIFT ");
4098 OUTS (outf, dregs (src1));
4099 OUTS (outf, " BY ");
4100 OUTS (outf, dregs_lo (src0));
4101 OUTS (outf, " (V)");
4102 }
4103 else if (sop == 0 && sopcde == 4)
4104 {
4105 OUTS (outf, dregs (dst0));
4106 OUTS (outf, " = PACK (");
4107 OUTS (outf, dregs_lo (src1));
4108 OUTS (outf, ", ");
4109 OUTS (outf, dregs_lo (src0));
4110 OUTS (outf, ")");
4111 }
4112 else if (sop == 1 && sopcde == 4)
4113 {
4114 OUTS (outf, dregs (dst0));
4115 OUTS (outf, " = PACK (");
4116 OUTS (outf, dregs_lo (src1));
4117 OUTS (outf, ", ");
4118 OUTS (outf, dregs_hi (src0));
4119 OUTS (outf, ")");
4120 }
4121 else if (sop == 2 && sopcde == 4)
4122 {
4123 OUTS (outf, dregs (dst0));
4124 OUTS (outf, " = PACK (");
4125 OUTS (outf, dregs_hi (src1));
4126 OUTS (outf, ", ");
4127 OUTS (outf, dregs_lo (src0));
4128 OUTS (outf, ")");
4129 }
4130 else if (sop == 3 && sopcde == 4)
4131 {
4132 OUTS (outf, dregs (dst0));
4133 OUTS (outf, " = PACK (");
4134 OUTS (outf, dregs_hi (src1));
4135 OUTS (outf, ", ");
4136 OUTS (outf, dregs_hi (src0));
4137 OUTS (outf, ")");
4138 }
4139 else if (sop == 0 && sopcde == 5)
4140 {
4141 OUTS (outf, dregs_lo (dst0));
4142 OUTS (outf, " = SIGNBITS ");
4143 OUTS (outf, dregs (src1));
4144 }
4145 else if (sop == 1 && sopcde == 5)
4146 {
4147 OUTS (outf, dregs_lo (dst0));
4148 OUTS (outf, " = SIGNBITS ");
4149 OUTS (outf, dregs_lo (src1));
4150 }
4151 else if (sop == 2 && sopcde == 5)
4152 {
4153 OUTS (outf, dregs_lo (dst0));
4154 OUTS (outf, " = SIGNBITS ");
4155 OUTS (outf, dregs_hi (src1));
4156 }
4157 else if (sop == 0 && sopcde == 6)
4158 {
4159 OUTS (outf, dregs_lo (dst0));
4160 OUTS (outf, " = SIGNBITS A0");
4161 }
4162 else if (sop == 1 && sopcde == 6)
4163 {
4164 OUTS (outf, dregs_lo (dst0));
4165 OUTS (outf, " = SIGNBITS A1");
4166 }
4167 else if (sop == 3 && sopcde == 6)
4168 {
4169 OUTS (outf, dregs_lo (dst0));
4170 OUTS (outf, " = ONES ");
4171 OUTS (outf, dregs (src1));
4172 }
4173 else if (sop == 0 && sopcde == 7)
4174 {
4175 OUTS (outf, dregs_lo (dst0));
4176 OUTS (outf, " = EXPADJ (");
4177 OUTS (outf, dregs (src1));
4178 OUTS (outf, ", ");
4179 OUTS (outf, dregs_lo (src0));
4180 OUTS (outf, ")");
4181 }
4182 else if (sop == 1 && sopcde == 7)
4183 {
4184 OUTS (outf, dregs_lo (dst0));
4185 OUTS (outf, " = EXPADJ (");
4186 OUTS (outf, dregs (src1));
4187 OUTS (outf, ", ");
4188 OUTS (outf, dregs_lo (src0));
4189 OUTS (outf, ") (V)");
4190 }
4191 else if (sop == 2 && sopcde == 7)
4192 {
4193 OUTS (outf, dregs_lo (dst0));
4194 OUTS (outf, " = EXPADJ (");
4195 OUTS (outf, dregs_lo (src1));
4196 OUTS (outf, ", ");
4197 OUTS (outf, dregs_lo (src0));
4198 OUTS (outf, ")");
4199 }
4200 else if (sop == 3 && sopcde == 7)
4201 {
4202 OUTS (outf, dregs_lo (dst0));
4203 OUTS (outf, " = EXPADJ (");
4204 OUTS (outf, dregs_hi (src1));
4205 OUTS (outf, ", ");
4206 OUTS (outf, dregs_lo (src0));
4207 OUTS (outf, ")");
4208 }
4209 else if (sop == 0 && sopcde == 8)
4210 {
4211 OUTS (outf, "BITMUX (");
4212 OUTS (outf, dregs (src0));
4213 OUTS (outf, ", ");
4214 OUTS (outf, dregs (src1));
4215 OUTS (outf, ", A0) (ASR)");
4216 }
4217 else if (sop == 1 && sopcde == 8)
4218 {
4219 OUTS (outf, "BITMUX (");
4220 OUTS (outf, dregs (src0));
4221 OUTS (outf, ", ");
4222 OUTS (outf, dregs (src1));
4223 OUTS (outf, ", A0) (ASL)");
4224 }
4225 else if (sop == 0 && sopcde == 9)
4226 {
4227 OUTS (outf, dregs_lo (dst0));
4228 OUTS (outf, " = VIT_MAX (");
4229 OUTS (outf, dregs (src1));
4230 OUTS (outf, ") (ASL)");
4231 }
4232 else if (sop == 1 && sopcde == 9)
4233 {
4234 OUTS (outf, dregs_lo (dst0));
4235 OUTS (outf, " = VIT_MAX (");
4236 OUTS (outf, dregs (src1));
4237 OUTS (outf, ") (ASR)");
4238 }
4239 else if (sop == 2 && sopcde == 9)
4240 {
4241 OUTS (outf, dregs (dst0));
4242 OUTS (outf, " = VIT_MAX (");
4243 OUTS (outf, dregs (src1));
4244 OUTS (outf, ", ");
4245 OUTS (outf, dregs (src0));
4246 OUTS (outf, ") (ASL)");
4247 }
4248 else if (sop == 3 && sopcde == 9)
4249 {
4250 OUTS (outf, dregs (dst0));
4251 OUTS (outf, " = VIT_MAX (");
4252 OUTS (outf, dregs (src1));
4253 OUTS (outf, ", ");
4254 OUTS (outf, dregs (src0));
4255 OUTS (outf, ") (ASR)");
4256 }
4257 else if (sop == 0 && sopcde == 10)
4258 {
4259 OUTS (outf, dregs (dst0));
4260 OUTS (outf, " = EXTRACT (");
4261 OUTS (outf, dregs (src1));
4262 OUTS (outf, ", ");
4263 OUTS (outf, dregs_lo (src0));
4264 OUTS (outf, ") (Z)");
4265 }
4266 else if (sop == 1 && sopcde == 10)
4267 {
4268 OUTS (outf, dregs (dst0));
4269 OUTS (outf, " = EXTRACT (");
4270 OUTS (outf, dregs (src1));
4271 OUTS (outf, ", ");
4272 OUTS (outf, dregs_lo (src0));
4273 OUTS (outf, ") (X)");
4274 }
4275 else if (sop == 2 && sopcde == 10)
4276 {
4277 OUTS (outf, dregs (dst0));
4278 OUTS (outf, " = DEPOSIT (");
4279 OUTS (outf, dregs (src1));
4280 OUTS (outf, ", ");
4281 OUTS (outf, dregs (src0));
4282 OUTS (outf, ")");
4283 }
4284 else if (sop == 3 && sopcde == 10)
4285 {
4286 OUTS (outf, dregs (dst0));
4287 OUTS (outf, " = DEPOSIT (");
4288 OUTS (outf, dregs (src1));
4289 OUTS (outf, ", ");
4290 OUTS (outf, dregs (src0));
4291 OUTS (outf, ") (X)");
4292 }
4293 else if (sop == 0 && sopcde == 11)
4294 {
4295 OUTS (outf, dregs_lo (dst0));
4296 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4297 OUTS (outf, dregs (src0));
4298 OUTS (outf, ")");
4299 }
4300 else if (sop == 1 && sopcde == 11)
4301 {
4302 OUTS (outf, dregs_lo (dst0));
4303 OUTS (outf, " = CC = BXOR (A0, ");
4304 OUTS (outf, dregs (src0));
4305 OUTS (outf, ")");
4306 }
4307 else if (sop == 0 && sopcde == 12)
4308 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4309
4310 else if (sop == 1 && sopcde == 12)
4311 {
4312 OUTS (outf, dregs_lo (dst0));
4313 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4314 }
4315 else if (sop == 0 && sopcde == 13)
4316 {
4317 OUTS (outf, dregs (dst0));
4318 OUTS (outf, " = ALIGN8 (");
4319 OUTS (outf, dregs (src1));
4320 OUTS (outf, ", ");
4321 OUTS (outf, dregs (src0));
4322 OUTS (outf, ")");
4323 }
4324 else if (sop == 1 && sopcde == 13)
4325 {
4326 OUTS (outf, dregs (dst0));
4327 OUTS (outf, " = ALIGN16 (");
4328 OUTS (outf, dregs (src1));
4329 OUTS (outf, ", ");
4330 OUTS (outf, dregs (src0));
4331 OUTS (outf, ")");
4332 }
4333 else if (sop == 2 && sopcde == 13)
4334 {
4335 OUTS (outf, dregs (dst0));
4336 OUTS (outf, " = ALIGN24 (");
4337 OUTS (outf, dregs (src1));
4338 OUTS (outf, ", ");
4339 OUTS (outf, dregs (src0));
4340 OUTS (outf, ")");
4341 }
4342 else
4343 return 0;
4344
4345 return 4;
4346 }
4347
4348 static int
4349 decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4350 {
4351 /* dsp32shiftimm
4352 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4353 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4354 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4355 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4356 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4357 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4358 int bit8 = ((iw1 >> 8) & 0x1);
4359 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4360 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4361 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4362 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4363 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4364
4365
4366 if (sop == 0 && sopcde == 0)
4367 {
4368 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4369 OUTS (outf, " = ");
4370 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4371 OUTS (outf, " >>> ");
4372 OUTS (outf, uimm4 (newimmag));
4373 }
4374 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4375 {
4376 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4377 OUTS (outf, " = ");
4378 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4379 OUTS (outf, " << ");
4380 OUTS (outf, uimm4 (immag));
4381 OUTS (outf, " (S)");
4382 }
4383 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4384 {
4385 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4386 OUTS (outf, " = ");
4387 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4388 OUTS (outf, " >>> ");
4389 OUTS (outf, uimm4 (newimmag));
4390 OUTS (outf, " (S)");
4391 }
4392 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4393 {
4394 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4395 OUTS (outf, " = ");
4396 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4397 OUTS (outf, " << ");
4398 OUTS (outf, uimm4 (immag));
4399 }
4400 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4401 {
4402 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4403 OUTS (outf, " = ");
4404 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4405 OUTS (outf, " >> ");
4406 OUTS (outf, uimm4 (newimmag));
4407 }
4408 else if (sop == 2 && sopcde == 3 && HLs == 1)
4409 {
4410 OUTS (outf, "A1 = ROT A1 BY ");
4411 OUTS (outf, imm6 (immag));
4412 }
4413 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4414 {
4415 OUTS (outf, "A0 = A0 << ");
4416 OUTS (outf, uimm5 (immag));
4417 }
4418 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4419 {
4420 OUTS (outf, "A0 = A0 >>> ");
4421 OUTS (outf, uimm5 (newimmag));
4422 }
4423 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4424 {
4425 OUTS (outf, "A1 = A1 << ");
4426 OUTS (outf, uimm5 (immag));
4427 }
4428 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4429 {
4430 OUTS (outf, "A1 = A1 >>> ");
4431 OUTS (outf, uimm5 (newimmag));
4432 }
4433 else if (sop == 1 && sopcde == 3 && HLs == 0)
4434 {
4435 OUTS (outf, "A0 = A0 >> ");
4436 OUTS (outf, uimm5 (newimmag));
4437 }
4438 else if (sop == 1 && sopcde == 3 && HLs == 1)
4439 {
4440 OUTS (outf, "A1 = A1 >> ");
4441 OUTS (outf, uimm5 (newimmag));
4442 }
4443 else if (sop == 2 && sopcde == 3 && HLs == 0)
4444 {
4445 OUTS (outf, "A0 = ROT A0 BY ");
4446 OUTS (outf, imm6 (immag));
4447 }
4448 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4449 {
4450 OUTS (outf, dregs (dst0));
4451 OUTS (outf, " = ");
4452 OUTS (outf, dregs (src1));
4453 OUTS (outf, " << ");
4454 OUTS (outf, uimm5 (immag));
4455 OUTS (outf, " (V, S)");
4456 }
4457 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4458 {
4459 OUTS (outf, dregs (dst0));
4460 OUTS (outf, " = ");
4461 OUTS (outf, dregs (src1));
4462 OUTS (outf, " >>> ");
4463 OUTS (outf, imm5 (-immag));
4464 OUTS (outf, " (V)");
4465 }
4466 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4467 {
4468 OUTS (outf, dregs (dst0));
4469 OUTS (outf, " = ");
4470 OUTS (outf, dregs (src1));
4471 OUTS (outf, " >> ");
4472 OUTS (outf, uimm5 (newimmag));
4473 OUTS (outf, " (V)");
4474 }
4475 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4476 {
4477 OUTS (outf, dregs (dst0));
4478 OUTS (outf, " = ");
4479 OUTS (outf, dregs (src1));
4480 OUTS (outf, " << ");
4481 OUTS (outf, imm5 (immag));
4482 OUTS (outf, " (V)");
4483 }
4484 else if (sop == 0 && sopcde == 1)
4485 {
4486 OUTS (outf, dregs (dst0));
4487 OUTS (outf, " = ");
4488 OUTS (outf, dregs (src1));
4489 OUTS (outf, " >>> ");
4490 OUTS (outf, uimm5 (newimmag));
4491 OUTS (outf, " (V)");
4492 }
4493 else if (sop == 1 && sopcde == 2)
4494 {
4495 OUTS (outf, dregs (dst0));
4496 OUTS (outf, " = ");
4497 OUTS (outf, dregs (src1));
4498 OUTS (outf, " << ");
4499 OUTS (outf, uimm5 (immag));
4500 OUTS (outf, " (S)");
4501 }
4502 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4503 {
4504 OUTS (outf, dregs (dst0));
4505 OUTS (outf, " = ");
4506 OUTS (outf, dregs (src1));
4507 OUTS (outf, " >> ");
4508 OUTS (outf, uimm5 (newimmag));
4509 }
4510 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4511 {
4512 OUTS (outf, dregs (dst0));
4513 OUTS (outf, " = ");
4514 OUTS (outf, dregs (src1));
4515 OUTS (outf, " << ");
4516 OUTS (outf, uimm5 (immag));
4517 }
4518 else if (sop == 3 && sopcde == 2)
4519 {
4520 OUTS (outf, dregs (dst0));
4521 OUTS (outf, " = ROT ");
4522 OUTS (outf, dregs (src1));
4523 OUTS (outf, " BY ");
4524 OUTS (outf, imm6 (immag));
4525 }
4526 else if (sop == 0 && sopcde == 2)
4527 {
4528 OUTS (outf, dregs (dst0));
4529 OUTS (outf, " = ");
4530 OUTS (outf, dregs (src1));
4531 OUTS (outf, " >>> ");
4532 OUTS (outf, uimm5 (newimmag));
4533 }
4534 else
4535 return 0;
4536
4537 return 4;
4538 }
4539
4540 static int
4541 decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4542 {
4543 /* pseudoDEBUG
4544 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4545 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4546 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4547 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4548 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4549 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4550
4551 if (reg == 0 && fn == 3)
4552 OUTS (outf, "DBG A0");
4553
4554 else if (reg == 1 && fn == 3)
4555 OUTS (outf, "DBG A1");
4556
4557 else if (reg == 3 && fn == 3)
4558 OUTS (outf, "ABORT");
4559
4560 else if (reg == 4 && fn == 3)
4561 OUTS (outf, "HLT");
4562
4563 else if (reg == 5 && fn == 3)
4564 OUTS (outf, "DBGHALT");
4565
4566 else if (reg == 6 && fn == 3)
4567 {
4568 OUTS (outf, "DBGCMPLX (");
4569 OUTS (outf, dregs (grp));
4570 OUTS (outf, ")");
4571 }
4572 else if (reg == 7 && fn == 3)
4573 OUTS (outf, "DBG");
4574
4575 else if (grp == 0 && fn == 2)
4576 {
4577 OUTS (outf, "OUTC ");
4578 OUTS (outf, dregs (reg));
4579 }
4580 else if (fn == 0)
4581 {
4582 OUTS (outf, "DBG ");
4583 OUTS (outf, allregs (reg, grp));
4584 }
4585 else if (fn == 1)
4586 {
4587 OUTS (outf, "PRNT");
4588 OUTS (outf, allregs (reg, grp));
4589 }
4590 else
4591 return 0;
4592
4593 return 2;
4594 }
4595
4596 static int
4597 decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4598 {
4599 /* psedoOChar
4600 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4601 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4602 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4603 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4604
4605 OUTS (outf, "OUTC ");
4606 OUTS (outf, uimm8 (ch));
4607
4608 return 2;
4609 }
4610
4611 static int
4612 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4613 {
4614 /* pseudodbg_assert
4615 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4616 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4617 |.expected......................................................|
4618 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4619 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4620 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4621 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
4622 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4623
4624 if (dbgop == 0)
4625 {
4626 OUTS (outf, "DBGA (");
4627 OUTS (outf, regs_lo (regtest, grp));
4628 OUTS (outf, ", ");
4629 OUTS (outf, uimm16 (expected));
4630 OUTS (outf, ")");
4631 }
4632 else if (dbgop == 1)
4633 {
4634 OUTS (outf, "DBGA (");
4635 OUTS (outf, regs_hi (regtest, grp));
4636 OUTS (outf, ", ");
4637 OUTS (outf, uimm16 (expected));
4638 OUTS (outf, ")");
4639 }
4640 else if (dbgop == 2)
4641 {
4642 OUTS (outf, "DBGAL (");
4643 OUTS (outf, allregs (regtest, grp));
4644 OUTS (outf, ", ");
4645 OUTS (outf, uimm16 (expected));
4646 OUTS (outf, ")");
4647 }
4648 else if (dbgop == 3)
4649 {
4650 OUTS (outf, "DBGAH (");
4651 OUTS (outf, allregs (regtest, grp));
4652 OUTS (outf, ", ");
4653 OUTS (outf, uimm16 (expected));
4654 OUTS (outf, ")");
4655 }
4656 else
4657 return 0;
4658 return 4;
4659 }
4660
4661 static int
4662 _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4663 {
4664 bfd_byte buf[4];
4665 TIword iw0;
4666 TIword iw1;
4667 int status;
4668 int rv = 0;
4669
4670 status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
4671 /* FIXME */
4672 (void) status;
4673 status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
4674 /* FIXME */
4675 (void) status;
4676
4677 iw0 = bfd_getl16 (buf);
4678 iw1 = bfd_getl16 (buf + 2);
4679
4680 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4681 {
4682 OUTS (outf, "MNOP");
4683 return 4;
4684 }
4685 else if ((iw0 & 0xff00) == 0x0000)
4686 rv = decode_ProgCtrl_0 (iw0, outf);
4687 else if ((iw0 & 0xffc0) == 0x0240)
4688 rv = decode_CaCTRL_0 (iw0, outf);
4689 else if ((iw0 & 0xff80) == 0x0100)
4690 rv = decode_PushPopReg_0 (iw0, outf);
4691 else if ((iw0 & 0xfe00) == 0x0400)
4692 rv = decode_PushPopMultiple_0 (iw0, outf);
4693 else if ((iw0 & 0xfe00) == 0x0600)
4694 rv = decode_ccMV_0 (iw0, outf);
4695 else if ((iw0 & 0xf800) == 0x0800)
4696 rv = decode_CCflag_0 (iw0, outf);
4697 else if ((iw0 & 0xffe0) == 0x0200)
4698 rv = decode_CC2dreg_0 (iw0, outf);
4699 else if ((iw0 & 0xff00) == 0x0300)
4700 rv = decode_CC2stat_0 (iw0, outf);
4701 else if ((iw0 & 0xf000) == 0x1000)
4702 rv = decode_BRCC_0 (iw0, pc, outf);
4703 else if ((iw0 & 0xf000) == 0x2000)
4704 rv = decode_UJUMP_0 (iw0, pc, outf);
4705 else if ((iw0 & 0xf000) == 0x3000)
4706 rv = decode_REGMV_0 (iw0, outf);
4707 else if ((iw0 & 0xfc00) == 0x4000)
4708 rv = decode_ALU2op_0 (iw0, outf);
4709 else if ((iw0 & 0xfe00) == 0x4400)
4710 rv = decode_PTR2op_0 (iw0, outf);
4711 else if ((iw0 & 0xf800) == 0x4800)
4712 rv = decode_LOGI2op_0 (iw0, outf);
4713 else if ((iw0 & 0xf000) == 0x5000)
4714 rv = decode_COMP3op_0 (iw0, outf);
4715 else if ((iw0 & 0xf800) == 0x6000)
4716 rv = decode_COMPI2opD_0 (iw0, outf);
4717 else if ((iw0 & 0xf800) == 0x6800)
4718 rv = decode_COMPI2opP_0 (iw0, outf);
4719 else if ((iw0 & 0xf000) == 0x8000)
4720 rv = decode_LDSTpmod_0 (iw0, outf);
4721 else if ((iw0 & 0xff60) == 0x9e60)
4722 rv = decode_dagMODim_0 (iw0, outf);
4723 else if ((iw0 & 0xfff0) == 0x9f60)
4724 rv = decode_dagMODik_0 (iw0, outf);
4725 else if ((iw0 & 0xfc00) == 0x9c00)
4726 rv = decode_dspLDST_0 (iw0, outf);
4727 else if ((iw0 & 0xf000) == 0x9000)
4728 rv = decode_LDST_0 (iw0, outf);
4729 else if ((iw0 & 0xfc00) == 0xb800)
4730 rv = decode_LDSTiiFP_0 (iw0, outf);
4731 else if ((iw0 & 0xe000) == 0xA000)
4732 rv = decode_LDSTii_0 (iw0, outf);
4733 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4734 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4735 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4736 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4737 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4738 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4739 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4740 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4741 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4742 rv = decode_linkage_0 (iw0, iw1, outf);
4743 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4744 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4745 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4746 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4747 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4748 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4749 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4750 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4751 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4752 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4753 else if ((iw0 & 0xff00) == 0xf800)
4754 rv = decode_pseudoDEBUG_0 (iw0, outf);
4755 else if ((iw0 & 0xFF00) == 0xF900)
4756 rv = decode_pseudoOChar_0 (iw0, outf);
4757 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4758 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4759
4760 return rv;
4761 }
4762
4763
4764 int
4765 print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4766 {
4767 bfd_byte buf[2];
4768 unsigned short iw0;
4769 int status;
4770 int count = 0;
4771
4772 status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
4773 /* FIXME */
4774 (void) status;
4775 iw0 = bfd_getl16 (buf);
4776
4777 count += _print_insn_bfin (pc, outf);
4778
4779 /* Proper display of multiple issue instructions. */
4780
4781 if ((iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
4782 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4783 {
4784 parallel = 1;
4785 outf->fprintf_func (outf->stream, " || ");
4786 count += _print_insn_bfin (pc + 4, outf);
4787 outf->fprintf_func (outf->stream, " || ");
4788 count += _print_insn_bfin (pc + 6, outf);
4789 parallel = 0;
4790 }
4791 if (count == 0)
4792 {
4793 outf->fprintf_func (outf->stream, "ILLEGAL");
4794 return 2;
4795 }
4796 if (!comment)
4797 outf->fprintf_func (outf->stream, ";");
4798
4799 comment = 0;
4800
4801 return count;
4802 }
GDB Binutils - Deliverables
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