1 /* Disassemble ADI Blackfin Instructions.
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 This file is part of libopcodes.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
25 #include "opcode/bfin.h"
47 #define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
48 #define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
49 #define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
50 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
54 typedef unsigned int bu32
;
56 static char comment
= 0;
57 static char parallel
= 0;
61 c_0
, c_1
, c_4
, c_2
, c_uimm2
, c_uimm3
, c_imm3
, c_pcrel4
,
62 c_imm4
, c_uimm4s4
, c_uimm4s4d
, c_uimm4
, c_uimm4s2
, c_negimm5s4
, c_imm5
, c_imm5d
, c_uimm5
, c_imm6
,
63 c_imm7
, c_imm7d
, c_imm8
, c_uimm8
, c_pcrel8
, c_uimm8s4
, c_pcrel8s4
, c_lppcrel10
, c_pcrel10
,
64 c_pcrel12
, c_imm16s4
, c_luimm16
, c_imm16
, c_imm16d
, c_huimm16
, c_rimm16
, c_imm16s2
, c_uimm16s4
,
65 c_uimm16s4d
, c_uimm16
, c_pcrel24
, c_uimm32
, c_imm32
, c_huimm32
, c_huimm32e
,
82 } constant_formats
[] =
84 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
85 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
86 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
88 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
89 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
91 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
92 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
94 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
95 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
97 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
98 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
99 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
100 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
101 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
102 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
103 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
104 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
107 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
108 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
109 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
110 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
111 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
112 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
113 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
114 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
118 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
119 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
120 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
121 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
122 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
123 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
124 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
125 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
126 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
130 fmtconst (const_forms_t cf
, TIword x
, bfd_vma pc
, disassemble_info
*outf
)
134 if (constant_formats
[cf
].reloc
)
136 bfd_vma ea
= (((constant_formats
[cf
].pcrel
? SIGNEXTEND (x
, constant_formats
[cf
].nbits
)
137 : x
) + constant_formats
[cf
].offset
) << constant_formats
[cf
].scale
);
138 if (constant_formats
[cf
].pcrel
)
141 if (outf
->symbol_at_address_func (ea
, outf
) || !constant_formats
[cf
].exact
)
143 outf
->print_address_func (ea
, outf
);
148 sprintf (buf
, "%lx", (unsigned long) x
);
153 /* Negative constants have an implied sign bit. */
154 if (constant_formats
[cf
].negative
)
156 int nb
= constant_formats
[cf
].nbits
+ 1;
158 x
= x
| (1 << constant_formats
[cf
].nbits
);
159 x
= SIGNEXTEND (x
, nb
);
162 x
= constant_formats
[cf
].issigned
? SIGNEXTEND (x
, constant_formats
[cf
].nbits
) : x
;
164 if (constant_formats
[cf
].offset
)
165 x
+= constant_formats
[cf
].offset
;
167 if (constant_formats
[cf
].scale
)
168 x
<<= constant_formats
[cf
].scale
;
170 if (constant_formats
[cf
].decimal
)
172 if (constant_formats
[cf
].leading
)
175 sprintf (ps
, "%%%ii", constant_formats
[cf
].leading
);
176 sprintf (buf
, ps
, x
);
179 sprintf (buf
, "%li", x
);
183 if (constant_formats
[cf
].issigned
&& x
< 0)
184 sprintf (buf
, "-0x%x", abs (x
));
186 sprintf (buf
, "0x%lx", (unsigned long) x
);
193 fmtconst_val (const_forms_t cf
, unsigned int x
, unsigned int pc
)
195 if (0 && constant_formats
[cf
].reloc
)
197 bu32 ea
= (((constant_formats
[cf
].pcrel
198 ? SIGNEXTEND (x
, constant_formats
[cf
].nbits
)
199 : x
) + constant_formats
[cf
].offset
)
200 << constant_formats
[cf
].scale
);
201 if (constant_formats
[cf
].pcrel
)
207 /* Negative constants have an implied sign bit. */
208 if (constant_formats
[cf
].negative
)
210 int nb
= constant_formats
[cf
].nbits
+ 1;
211 x
= x
| (1 << constant_formats
[cf
].nbits
);
212 x
= SIGNEXTEND (x
, nb
);
214 else if (constant_formats
[cf
].issigned
)
215 x
= SIGNEXTEND (x
, constant_formats
[cf
].nbits
);
217 x
+= constant_formats
[cf
].offset
;
218 x
<<= constant_formats
[cf
].scale
;
223 enum machine_registers
225 REG_RL0
, REG_RL1
, REG_RL2
, REG_RL3
, REG_RL4
, REG_RL5
, REG_RL6
, REG_RL7
,
226 REG_RH0
, REG_RH1
, REG_RH2
, REG_RH3
, REG_RH4
, REG_RH5
, REG_RH6
, REG_RH7
,
227 REG_R0
, REG_R1
, REG_R2
, REG_R3
, REG_R4
, REG_R5
, REG_R6
, REG_R7
,
228 REG_R1_0
, REG_R3_2
, REG_R5_4
, REG_R7_6
, REG_P0
, REG_P1
, REG_P2
, REG_P3
,
229 REG_P4
, REG_P5
, REG_SP
, REG_FP
, REG_A0x
, REG_A1x
, REG_A0w
, REG_A1w
,
230 REG_A0
, REG_A1
, REG_I0
, REG_I1
, REG_I2
, REG_I3
, REG_M0
, REG_M1
,
231 REG_M2
, REG_M3
, REG_B0
, REG_B1
, REG_B2
, REG_B3
, REG_L0
, REG_L1
,
233 REG_AZ
, REG_AN
, REG_AC0
, REG_AC1
, REG_AV0
, REG_AV1
, REG_AV0S
, REG_AV1S
,
234 REG_AQ
, REG_V
, REG_VS
,
235 REG_sftreset
, REG_omode
, REG_excause
, REG_emucause
, REG_idle_req
, REG_hwerrcause
, REG_CC
, REG_LC0
,
236 REG_LC1
, REG_GP
, REG_ASTAT
, REG_RETS
, REG_LT0
, REG_LB0
, REG_LT1
, REG_LB1
,
237 REG_CYCLES
, REG_CYCLES2
, REG_USP
, REG_SEQSTAT
, REG_SYSCFG
, REG_RETI
, REG_RETX
, REG_RETN
,
238 REG_RETE
, REG_EMUDAT
, REG_BR0
, REG_BR1
, REG_BR2
, REG_BR3
, REG_BR4
, REG_BR5
, REG_BR6
,
239 REG_BR7
, REG_PL0
, REG_PL1
, REG_PL2
, REG_PL3
, REG_PL4
, REG_PL5
, REG_SLP
, REG_FLP
,
240 REG_PH0
, REG_PH1
, REG_PH2
, REG_PH3
, REG_PH4
, REG_PH5
, REG_SHP
, REG_FHP
,
241 REG_IL0
, REG_IL1
, REG_IL2
, REG_IL3
, REG_ML0
, REG_ML1
, REG_ML2
, REG_ML3
,
242 REG_BL0
, REG_BL1
, REG_BL2
, REG_BL3
, REG_LL0
, REG_LL1
, REG_LL2
, REG_LL3
,
243 REG_IH0
, REG_IH1
, REG_IH2
, REG_IH3
, REG_MH0
, REG_MH1
, REG_MH2
, REG_MH3
,
244 REG_BH0
, REG_BH1
, REG_BH2
, REG_BH3
, REG_LH0
, REG_LH1
, REG_LH2
, REG_LH3
,
245 REG_AC0_COPY
, REG_V_COPY
, REG_RND_MOD
,
251 rc_dregs_lo
, rc_dregs_hi
, rc_dregs
, rc_dregs_pair
, rc_pregs
, rc_spfp
, rc_dregs_hilo
, rc_accum_ext
,
252 rc_accum_word
, rc_accum
, rc_iregs
, rc_mregs
, rc_bregs
, rc_lregs
, rc_dpregs
, rc_gregs
,
253 rc_regs
, rc_statbits
, rc_ignore_bits
, rc_ccstat
, rc_counters
, rc_dregs2_sysregs1
, rc_open
, rc_sysregs2
,
254 rc_sysregs3
, rc_allregs
,
258 static const char *reg_names
[] =
260 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
261 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
262 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
263 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
264 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
265 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
266 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
268 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
270 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
271 "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
272 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
274 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
275 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
276 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
277 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
278 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
279 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
280 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
281 "AC0_COPY", "V_COPY", "RND_MOD",
286 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
289 static enum machine_registers decode_dregs_lo
[] =
291 REG_RL0
, REG_RL1
, REG_RL2
, REG_RL3
, REG_RL4
, REG_RL5
, REG_RL6
, REG_RL7
,
294 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
297 static enum machine_registers decode_dregs_hi
[] =
299 REG_RH0
, REG_RH1
, REG_RH2
, REG_RH3
, REG_RH4
, REG_RH5
, REG_RH6
, REG_RH7
,
302 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
305 static enum machine_registers decode_dregs
[] =
307 REG_R0
, REG_R1
, REG_R2
, REG_R3
, REG_R4
, REG_R5
, REG_R6
, REG_R7
,
310 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
313 static enum machine_registers decode_dregs_byte
[] =
315 REG_BR0
, REG_BR1
, REG_BR2
, REG_BR3
, REG_BR4
, REG_BR5
, REG_BR6
, REG_BR7
,
318 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
321 static enum machine_registers decode_pregs
[] =
323 REG_P0
, REG_P1
, REG_P2
, REG_P3
, REG_P4
, REG_P5
, REG_SP
, REG_FP
,
326 #define pregs(x) REGNAME (decode_pregs[(x) & 7])
327 #define spfp(x) REGNAME (decode_spfp[(x) & 1])
328 #define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
329 #define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
330 #define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
331 #define accum(x) REGNAME (decode_accum[(x) & 1])
334 static enum machine_registers decode_iregs
[] =
336 REG_I0
, REG_I1
, REG_I2
, REG_I3
,
339 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
342 static enum machine_registers decode_mregs
[] =
344 REG_M0
, REG_M1
, REG_M2
, REG_M3
,
347 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
348 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
349 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
352 static enum machine_registers decode_dpregs
[] =
354 REG_R0
, REG_R1
, REG_R2
, REG_R3
, REG_R4
, REG_R5
, REG_R6
, REG_R7
,
355 REG_P0
, REG_P1
, REG_P2
, REG_P3
, REG_P4
, REG_P5
, REG_SP
, REG_FP
,
358 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
361 static enum machine_registers decode_gregs
[] =
363 REG_R0
, REG_R1
, REG_R2
, REG_R3
, REG_R4
, REG_R5
, REG_R6
, REG_R7
,
364 REG_P0
, REG_P1
, REG_P2
, REG_P3
, REG_P4
, REG_P5
, REG_SP
, REG_FP
,
367 #define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
369 /* [dregs pregs (iregs mregs) (bregs lregs)]. */
370 static enum machine_registers decode_regs
[] =
372 REG_R0
, REG_R1
, REG_R2
, REG_R3
, REG_R4
, REG_R5
, REG_R6
, REG_R7
,
373 REG_P0
, REG_P1
, REG_P2
, REG_P3
, REG_P4
, REG_P5
, REG_SP
, REG_FP
,
374 REG_I0
, REG_I1
, REG_I2
, REG_I3
, REG_M0
, REG_M1
, REG_M2
, REG_M3
,
375 REG_B0
, REG_B1
, REG_B2
, REG_B3
, REG_L0
, REG_L1
, REG_L2
, REG_L3
,
378 #define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
380 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
381 static enum machine_registers decode_regs_lo
[] =
383 REG_RL0
, REG_RL1
, REG_RL2
, REG_RL3
, REG_RL4
, REG_RL5
, REG_RL6
, REG_RL7
,
384 REG_PL0
, REG_PL1
, REG_PL2
, REG_PL3
, REG_PL4
, REG_PL5
, REG_SLP
, REG_FLP
,
385 REG_IL0
, REG_IL1
, REG_IL2
, REG_IL3
, REG_ML0
, REG_ML1
, REG_ML2
, REG_ML3
,
386 REG_BL0
, REG_BL1
, REG_BL2
, REG_BL3
, REG_LL0
, REG_LL1
, REG_LL2
, REG_LL3
,
389 #define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
390 /* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
391 static enum machine_registers decode_regs_hi
[] =
393 REG_RH0
, REG_RH1
, REG_RH2
, REG_RH3
, REG_RH4
, REG_RH5
, REG_RH6
, REG_RH7
,
394 REG_PH0
, REG_PH1
, REG_PH2
, REG_PH3
, REG_PH4
, REG_PH5
, REG_SHP
, REG_FHP
,
395 REG_IH0
, REG_IH1
, REG_IH2
, REG_IH3
, REG_MH0
, REG_MH1
, REG_MH2
, REG_MH3
,
396 REG_BH0
, REG_BH1
, REG_BH2
, REG_BH3
, REG_LH0
, REG_LH1
, REG_LH2
, REG_LH3
,
399 #define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
401 static enum machine_registers decode_statbits
[] =
403 REG_AZ
, REG_AN
, REG_AC0_COPY
, REG_V_COPY
,
404 REG_LASTREG
, REG_LASTREG
, REG_AQ
, REG_LASTREG
,
405 REG_RND_MOD
, REG_LASTREG
, REG_LASTREG
, REG_LASTREG
,
406 REG_AC0
, REG_AC1
, REG_LASTREG
, REG_LASTREG
,
407 REG_AV0
, REG_AV0S
, REG_AV1
, REG_AV1S
,
408 REG_LASTREG
, REG_LASTREG
, REG_LASTREG
, REG_LASTREG
,
409 REG_V
, REG_VS
, REG_LASTREG
, REG_LASTREG
,
410 REG_LASTREG
, REG_LASTREG
, REG_LASTREG
, REG_LASTREG
,
413 #define statbits(x) REGNAME (decode_statbits[(x) & 31])
416 static enum machine_registers decode_counters
[] =
421 #define counters(x) REGNAME (decode_counters[(x) & 1])
422 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
424 /* [dregs pregs (iregs mregs) (bregs lregs)
425 dregs2_sysregs1 open sysregs2 sysregs3]. */
426 static enum machine_registers decode_allregs
[] =
428 REG_R0
, REG_R1
, REG_R2
, REG_R3
, REG_R4
, REG_R5
, REG_R6
, REG_R7
,
429 REG_P0
, REG_P1
, REG_P2
, REG_P3
, REG_P4
, REG_P5
, REG_SP
, REG_FP
,
430 REG_I0
, REG_I1
, REG_I2
, REG_I3
, REG_M0
, REG_M1
, REG_M2
, REG_M3
,
431 REG_B0
, REG_B1
, REG_B2
, REG_B3
, REG_L0
, REG_L1
, REG_L2
, REG_L3
,
432 REG_A0x
, REG_A0w
, REG_A1x
, REG_A1w
, REG_GP
, REG_LASTREG
, REG_ASTAT
, REG_RETS
,
433 REG_LASTREG
, REG_LASTREG
, REG_LASTREG
, REG_LASTREG
, REG_LASTREG
, REG_LASTREG
, REG_LASTREG
, REG_LASTREG
,
434 REG_LC0
, REG_LT0
, REG_LB0
, REG_LC1
, REG_LT1
, REG_LB1
, REG_CYCLES
, REG_CYCLES2
,
435 REG_USP
, REG_SEQSTAT
, REG_SYSCFG
, REG_RETI
, REG_RETX
, REG_RETN
, REG_RETE
, REG_EMUDAT
,
439 #define IS_DREG(g,r) ((g) == 0 && (r) < 8)
440 #define IS_PREG(g,r) ((g) == 1 && (r) < 8)
441 #define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
442 #define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
443 #define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
444 #define IS_SYSREG(g,r) \
445 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
446 #define IS_RESERVEDREG(g,r) \
447 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
449 #define allreg(r,g) (!IS_RESERVEDREG (g, r))
450 #define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
452 #define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
453 #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
454 #define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
455 #define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
456 #define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
457 #define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
458 #define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
459 #define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
460 #define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
461 #define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
462 #define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
463 #define imm16(x) fmtconst (c_imm16, x, 0, outf)
464 #define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
465 #define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
466 #define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
467 #define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
468 #define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
469 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
470 #define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
471 #define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
472 #define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
473 #define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
474 #define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
475 #define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
476 #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
477 #define imm3(x) fmtconst (c_imm3, x, 0, outf)
478 #define imm4(x) fmtconst (c_imm4, x, 0, outf)
479 #define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
480 #define imm5(x) fmtconst (c_imm5, x, 0, outf)
481 #define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
482 #define imm6(x) fmtconst (c_imm6, x, 0, outf)
483 #define imm7(x) fmtconst (c_imm7, x, 0, outf)
484 #define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
485 #define imm8(x) fmtconst (c_imm8, x, 0, outf)
486 #define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
487 #define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
488 #define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
489 #define imm32(x) fmtconst (c_imm32, x, 0, outf)
490 #define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
491 #define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
492 #define imm7_val(x) fmtconst_val (c_imm7, x, 0)
493 #define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
494 #define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
496 /* (arch.pm)arch_disassembler_functions. */
498 #define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
502 amod0 (int s0
, int x0
, disassemble_info
*outf
)
504 if (s0
== 1 && x0
== 0)
506 else if (s0
== 0 && x0
== 1)
507 OUTS (outf
, " (CO)");
508 else if (s0
== 1 && x0
== 1)
509 OUTS (outf
, " (SCO)");
513 amod1 (int s0
, int x0
, disassemble_info
*outf
)
515 if (s0
== 0 && x0
== 0)
516 OUTS (outf
, " (NS)");
517 else if (s0
== 1 && x0
== 0)
522 amod0amod2 (int s0
, int x0
, int aop0
, disassemble_info
*outf
)
524 if (s0
== 1 && x0
== 0 && aop0
== 0)
526 else if (s0
== 0 && x0
== 1 && aop0
== 0)
527 OUTS (outf
, " (CO)");
528 else if (s0
== 1 && x0
== 1 && aop0
== 0)
529 OUTS (outf
, " (SCO)");
530 else if (s0
== 0 && x0
== 0 && aop0
== 2)
531 OUTS (outf
, " (ASR)");
532 else if (s0
== 1 && x0
== 0 && aop0
== 2)
533 OUTS (outf
, " (S, ASR)");
534 else if (s0
== 0 && x0
== 1 && aop0
== 2)
535 OUTS (outf
, " (CO, ASR)");
536 else if (s0
== 1 && x0
== 1 && aop0
== 2)
537 OUTS (outf
, " (SCO, ASR)");
538 else if (s0
== 0 && x0
== 0 && aop0
== 3)
539 OUTS (outf
, " (ASL)");
540 else if (s0
== 1 && x0
== 0 && aop0
== 3)
541 OUTS (outf
, " (S, ASL)");
542 else if (s0
== 0 && x0
== 1 && aop0
== 3)
543 OUTS (outf
, " (CO, ASL)");
544 else if (s0
== 1 && x0
== 1 && aop0
== 3)
545 OUTS (outf
, " (SCO, ASL)");
549 searchmod (int r0
, disassemble_info
*outf
)
562 aligndir (int r0
, disassemble_info
*outf
)
569 decode_multfunc (int h0
, int h1
, int src0
, int src1
, disassemble_info
* outf
)
574 s0
= dregs_hi (src0
);
576 s0
= dregs_lo (src0
);
579 s1
= dregs_hi (src1
);
581 s1
= dregs_lo (src1
);
590 decode_macfunc (int which
, int op
, int h0
, int h1
, int src0
, int src1
, disassemble_info
* outf
)
593 const char *sop
= "<unknown op>";
608 case 0: sop
= " = "; break;
609 case 1: sop
= " += "; break;
610 case 2: sop
= " -= "; break;
616 decode_multfunc (h0
, h1
, src0
, src1
, outf
);
622 decode_optmode (int mod
, int MM
, disassemble_info
*outf
)
624 if (mod
== 0 && MM
== 0)
639 OUTS (outf
, "S2RND");
642 else if (mod
== M_W32
)
644 else if (mod
== M_FU
)
646 else if (mod
== M_TFU
)
648 else if (mod
== M_IS
)
650 else if (mod
== M_ISS2
)
652 else if (mod
== M_IH
)
654 else if (mod
== M_IU
)
664 bu32 dpregs
[16], iregs
[4], mregs
[4], bregs
[4], lregs
[4];
665 bu32 a0x
, a0w
, a1x
, a1w
;
666 bu32 lt
[2], lc
[2], lb
[2];
667 int ac0
, ac0_copy
, ac1
, an
, aq
;
668 int av0
, av0s
, av1
, av1s
, az
, cc
, v
, v_copy
, vs
;
678 int end_of_registers
;
681 unsigned char *memory
;
682 unsigned long bfd_mach
;
685 #define DREG(x) (saved_state.dpregs[x])
686 #define GREG(x,i) DPREG ((x) | (i << 3))
687 #define DPREG(x) (saved_state.dpregs[x])
688 #define DREG(x) (saved_state.dpregs[x])
689 #define PREG(x) (saved_state.dpregs[x + 8])
690 #define SPREG PREG (6)
691 #define FPREG PREG (7)
692 #define IREG(x) (saved_state.iregs[x])
693 #define MREG(x) (saved_state.mregs[x])
694 #define BREG(x) (saved_state.bregs[x])
695 #define LREG(x) (saved_state.lregs[x])
696 #define A0XREG (saved_state.a0x)
697 #define A0WREG (saved_state.a0w)
698 #define A1XREG (saved_state.a1x)
699 #define A1WREG (saved_state.a1w)
700 #define CCREG (saved_state.cc)
701 #define LC0REG (saved_state.lc[0])
702 #define LT0REG (saved_state.lt[0])
703 #define LB0REG (saved_state.lb[0])
704 #define LC1REG (saved_state.lc[1])
705 #define LT1REG (saved_state.lt[1])
706 #define LB1REG (saved_state.lb[1])
707 #define RETSREG (saved_state.rets)
708 #define PCREG (saved_state.pc)
711 get_allreg (int grp
, int reg
)
713 int fullreg
= (grp
<< 3) | reg
;
714 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
715 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
716 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
717 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
718 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
720 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
722 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
724 switch (fullreg
>> 2)
726 case 0: case 1: return &DREG (reg
); break;
727 case 2: case 3: return &PREG (reg
); break;
728 case 4: return &IREG (reg
& 3); break;
729 case 5: return &MREG (reg
& 3); break;
730 case 6: return &BREG (reg
& 3); break;
731 case 7: return &LREG (reg
& 3); break;
735 case 32: return &saved_state
.a0x
;
736 case 33: return &saved_state
.a0w
;
737 case 34: return &saved_state
.a1x
;
738 case 35: return &saved_state
.a1w
;
739 case 39: return &saved_state
.rets
;
740 case 48: return &LC0REG
;
741 case 49: return <0REG
;
742 case 50: return &LB0REG
;
743 case 51: return &LC1REG
;
744 case 52: return <1REG
;
745 case 53: return &LB1REG
;
752 decode_ProgCtrl_0 (TIword iw0
, disassemble_info
*outf
)
755 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
756 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
757 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
758 int poprnd
= ((iw0
>> ProgCtrl_poprnd_bits
) & ProgCtrl_poprnd_mask
);
759 int prgfunc
= ((iw0
>> ProgCtrl_prgfunc_bits
) & ProgCtrl_prgfunc_mask
);
761 if (prgfunc
== 0 && poprnd
== 0)
765 else if (prgfunc
== 1 && poprnd
== 0)
767 else if (prgfunc
== 1 && poprnd
== 1)
769 else if (prgfunc
== 1 && poprnd
== 2)
771 else if (prgfunc
== 1 && poprnd
== 3)
773 else if (prgfunc
== 1 && poprnd
== 4)
775 else if (prgfunc
== 2 && poprnd
== 0)
777 else if (prgfunc
== 2 && poprnd
== 3)
778 OUTS (outf
, "CSYNC");
779 else if (prgfunc
== 2 && poprnd
== 4)
780 OUTS (outf
, "SSYNC");
781 else if (prgfunc
== 2 && poprnd
== 5)
782 OUTS (outf
, "EMUEXCPT");
783 else if (prgfunc
== 3 && IS_DREG (0, poprnd
))
786 OUTS (outf
, dregs (poprnd
));
788 else if (prgfunc
== 4 && IS_DREG (0, poprnd
))
791 OUTS (outf
, dregs (poprnd
));
793 else if (prgfunc
== 5 && IS_PREG (1, poprnd
))
795 OUTS (outf
, "JUMP (");
796 OUTS (outf
, pregs (poprnd
));
799 else if (prgfunc
== 6 && IS_PREG (1, poprnd
))
801 OUTS (outf
, "CALL (");
802 OUTS (outf
, pregs (poprnd
));
805 else if (prgfunc
== 7 && IS_PREG (1, poprnd
))
807 OUTS (outf
, "CALL (PC + ");
808 OUTS (outf
, pregs (poprnd
));
811 else if (prgfunc
== 8 && IS_PREG (1, poprnd
))
813 OUTS (outf
, "JUMP (PC + ");
814 OUTS (outf
, pregs (poprnd
));
817 else if (prgfunc
== 9)
819 OUTS (outf
, "RAISE ");
820 OUTS (outf
, uimm4 (poprnd
));
822 else if (prgfunc
== 10)
824 OUTS (outf
, "EXCPT ");
825 OUTS (outf
, uimm4 (poprnd
));
827 else if (prgfunc
== 11 && IS_PREG (1, poprnd
) && poprnd
<= 5)
829 OUTS (outf
, "TESTSET (");
830 OUTS (outf
, pregs (poprnd
));
839 decode_CaCTRL_0 (TIword iw0
, disassemble_info
*outf
)
842 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
843 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
844 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
845 int a
= ((iw0
>> CaCTRL_a_bits
) & CaCTRL_a_mask
);
846 int op
= ((iw0
>> CaCTRL_op_bits
) & CaCTRL_op_mask
);
847 int reg
= ((iw0
>> CaCTRL_reg_bits
) & CaCTRL_reg_mask
);
852 if (a
== 0 && op
== 0)
854 OUTS (outf
, "PREFETCH[");
855 OUTS (outf
, pregs (reg
));
858 else if (a
== 0 && op
== 1)
860 OUTS (outf
, "FLUSHINV[");
861 OUTS (outf
, pregs (reg
));
864 else if (a
== 0 && op
== 2)
866 OUTS (outf
, "FLUSH[");
867 OUTS (outf
, pregs (reg
));
870 else if (a
== 0 && op
== 3)
872 OUTS (outf
, "IFLUSH[");
873 OUTS (outf
, pregs (reg
));
876 else if (a
== 1 && op
== 0)
878 OUTS (outf
, "PREFETCH[");
879 OUTS (outf
, pregs (reg
));
882 else if (a
== 1 && op
== 1)
884 OUTS (outf
, "FLUSHINV[");
885 OUTS (outf
, pregs (reg
));
888 else if (a
== 1 && op
== 2)
890 OUTS (outf
, "FLUSH[");
891 OUTS (outf
, pregs (reg
));
894 else if (a
== 1 && op
== 3)
896 OUTS (outf
, "IFLUSH[");
897 OUTS (outf
, pregs (reg
));
906 decode_PushPopReg_0 (TIword iw0
, disassemble_info
*outf
)
909 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
910 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
911 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
912 int W
= ((iw0
>> PushPopReg_W_bits
) & PushPopReg_W_mask
);
913 int grp
= ((iw0
>> PushPopReg_grp_bits
) & PushPopReg_grp_mask
);
914 int reg
= ((iw0
>> PushPopReg_reg_bits
) & PushPopReg_reg_mask
);
919 if (W
== 0 && mostreg (reg
, grp
))
921 OUTS (outf
, allregs (reg
, grp
));
922 OUTS (outf
, " = [SP++]");
924 else if (W
== 1 && allreg (reg
, grp
) && !(grp
== 1 && reg
== 6))
926 OUTS (outf
, "[--SP] = ");
927 OUTS (outf
, allregs (reg
, grp
));
935 decode_PushPopMultiple_0 (TIword iw0
, disassemble_info
*outf
)
938 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
939 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
940 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
941 int p
= ((iw0
>> PushPopMultiple_p_bits
) & PushPopMultiple_p_mask
);
942 int d
= ((iw0
>> PushPopMultiple_d_bits
) & PushPopMultiple_d_mask
);
943 int W
= ((iw0
>> PushPopMultiple_W_bits
) & PushPopMultiple_W_mask
);
944 int dr
= ((iw0
>> PushPopMultiple_dr_bits
) & PushPopMultiple_dr_mask
);
945 int pr
= ((iw0
>> PushPopMultiple_pr_bits
) & PushPopMultiple_pr_mask
);
953 if (W
== 1 && d
== 1 && p
== 1)
955 OUTS (outf
, "[--SP] = (R7:");
956 OUTS (outf
, imm5d (dr
));
957 OUTS (outf
, ", P5:");
958 OUTS (outf
, imm5d (pr
));
961 else if (W
== 1 && d
== 1 && p
== 0 && pr
== 0)
963 OUTS (outf
, "[--SP] = (R7:");
964 OUTS (outf
, imm5d (dr
));
967 else if (W
== 1 && d
== 0 && p
== 1 && dr
== 0)
969 OUTS (outf
, "[--SP] = (P5:");
970 OUTS (outf
, imm5d (pr
));
973 else if (W
== 0 && d
== 1 && p
== 1)
976 OUTS (outf
, imm5d (dr
));
977 OUTS (outf
, ", P5:");
978 OUTS (outf
, imm5d (pr
));
979 OUTS (outf
, ") = [SP++]");
981 else if (W
== 0 && d
== 1 && p
== 0 && pr
== 0)
984 OUTS (outf
, imm5d (dr
));
985 OUTS (outf
, ") = [SP++]");
987 else if (W
== 0 && d
== 0 && p
== 1 && dr
== 0)
990 OUTS (outf
, imm5d (pr
));
991 OUTS (outf
, ") = [SP++]");
999 decode_ccMV_0 (TIword iw0
, disassemble_info
*outf
)
1002 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1003 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
1004 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1005 int s
= ((iw0
>> CCmv_s_bits
) & CCmv_s_mask
);
1006 int d
= ((iw0
>> CCmv_d_bits
) & CCmv_d_mask
);
1007 int T
= ((iw0
>> CCmv_T_bits
) & CCmv_T_mask
);
1008 int src
= ((iw0
>> CCmv_src_bits
) & CCmv_src_mask
);
1009 int dst
= ((iw0
>> CCmv_dst_bits
) & CCmv_dst_mask
);
1016 OUTS (outf
, "IF CC ");
1017 OUTS (outf
, gregs (dst
, d
));
1019 OUTS (outf
, gregs (src
, s
));
1023 OUTS (outf
, "IF !CC ");
1024 OUTS (outf
, gregs (dst
, d
));
1026 OUTS (outf
, gregs (src
, s
));
1034 decode_CCflag_0 (TIword iw0
, disassemble_info
*outf
)
1037 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1038 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1039 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1040 int x
= ((iw0
>> CCflag_x_bits
) & CCflag_x_mask
);
1041 int y
= ((iw0
>> CCflag_y_bits
) & CCflag_y_mask
);
1042 int I
= ((iw0
>> CCflag_I_bits
) & CCflag_I_mask
);
1043 int G
= ((iw0
>> CCflag_G_bits
) & CCflag_G_mask
);
1044 int opc
= ((iw0
>> CCflag_opc_bits
) & CCflag_opc_mask
);
1049 if (opc
== 0 && I
== 0 && G
== 0)
1051 OUTS (outf
, "CC = ");
1052 OUTS (outf
, dregs (x
));
1053 OUTS (outf
, " == ");
1054 OUTS (outf
, dregs (y
));
1056 else if (opc
== 1 && I
== 0 && G
== 0)
1058 OUTS (outf
, "CC = ");
1059 OUTS (outf
, dregs (x
));
1061 OUTS (outf
, dregs (y
));
1063 else if (opc
== 2 && I
== 0 && G
== 0)
1065 OUTS (outf
, "CC = ");
1066 OUTS (outf
, dregs (x
));
1067 OUTS (outf
, " <= ");
1068 OUTS (outf
, dregs (y
));
1070 else if (opc
== 3 && I
== 0 && G
== 0)
1072 OUTS (outf
, "CC = ");
1073 OUTS (outf
, dregs (x
));
1075 OUTS (outf
, dregs (y
));
1076 OUTS (outf
, " (IU)");
1078 else if (opc
== 4 && I
== 0 && G
== 0)
1080 OUTS (outf
, "CC = ");
1081 OUTS (outf
, dregs (x
));
1082 OUTS (outf
, " <= ");
1083 OUTS (outf
, dregs (y
));
1084 OUTS (outf
, " (IU)");
1086 else if (opc
== 0 && I
== 1 && G
== 0)
1088 OUTS (outf
, "CC = ");
1089 OUTS (outf
, dregs (x
));
1090 OUTS (outf
, " == ");
1091 OUTS (outf
, imm3 (y
));
1093 else if (opc
== 1 && I
== 1 && G
== 0)
1095 OUTS (outf
, "CC = ");
1096 OUTS (outf
, dregs (x
));
1098 OUTS (outf
, imm3 (y
));
1100 else if (opc
== 2 && I
== 1 && G
== 0)
1102 OUTS (outf
, "CC = ");
1103 OUTS (outf
, dregs (x
));
1104 OUTS (outf
, " <= ");
1105 OUTS (outf
, imm3 (y
));
1107 else if (opc
== 3 && I
== 1 && G
== 0)
1109 OUTS (outf
, "CC = ");
1110 OUTS (outf
, dregs (x
));
1112 OUTS (outf
, uimm3 (y
));
1113 OUTS (outf
, " (IU)");
1115 else if (opc
== 4 && I
== 1 && G
== 0)
1117 OUTS (outf
, "CC = ");
1118 OUTS (outf
, dregs (x
));
1119 OUTS (outf
, " <= ");
1120 OUTS (outf
, uimm3 (y
));
1121 OUTS (outf
, " (IU)");
1123 else if (opc
== 0 && I
== 0 && G
== 1)
1125 OUTS (outf
, "CC = ");
1126 OUTS (outf
, pregs (x
));
1127 OUTS (outf
, " == ");
1128 OUTS (outf
, pregs (y
));
1130 else if (opc
== 1 && I
== 0 && G
== 1)
1132 OUTS (outf
, "CC = ");
1133 OUTS (outf
, pregs (x
));
1135 OUTS (outf
, pregs (y
));
1137 else if (opc
== 2 && I
== 0 && G
== 1)
1139 OUTS (outf
, "CC = ");
1140 OUTS (outf
, pregs (x
));
1141 OUTS (outf
, " <= ");
1142 OUTS (outf
, pregs (y
));
1144 else if (opc
== 3 && I
== 0 && G
== 1)
1146 OUTS (outf
, "CC = ");
1147 OUTS (outf
, pregs (x
));
1149 OUTS (outf
, pregs (y
));
1150 OUTS (outf
, " (IU)");
1152 else if (opc
== 4 && I
== 0 && G
== 1)
1154 OUTS (outf
, "CC = ");
1155 OUTS (outf
, pregs (x
));
1156 OUTS (outf
, " <= ");
1157 OUTS (outf
, pregs (y
));
1158 OUTS (outf
, " (IU)");
1160 else if (opc
== 0 && I
== 1 && G
== 1)
1162 OUTS (outf
, "CC = ");
1163 OUTS (outf
, pregs (x
));
1164 OUTS (outf
, " == ");
1165 OUTS (outf
, imm3 (y
));
1167 else if (opc
== 1 && I
== 1 && G
== 1)
1169 OUTS (outf
, "CC = ");
1170 OUTS (outf
, pregs (x
));
1172 OUTS (outf
, imm3 (y
));
1174 else if (opc
== 2 && I
== 1 && G
== 1)
1176 OUTS (outf
, "CC = ");
1177 OUTS (outf
, pregs (x
));
1178 OUTS (outf
, " <= ");
1179 OUTS (outf
, imm3 (y
));
1181 else if (opc
== 3 && I
== 1 && G
== 1)
1183 OUTS (outf
, "CC = ");
1184 OUTS (outf
, pregs (x
));
1186 OUTS (outf
, uimm3 (y
));
1187 OUTS (outf
, " (IU)");
1189 else if (opc
== 4 && I
== 1 && G
== 1)
1191 OUTS (outf
, "CC = ");
1192 OUTS (outf
, pregs (x
));
1193 OUTS (outf
, " <= ");
1194 OUTS (outf
, uimm3 (y
));
1195 OUTS (outf
, " (IU)");
1197 else if (opc
== 5 && I
== 0 && G
== 0 && x
== 0 && y
== 0)
1198 OUTS (outf
, "CC = A0 == A1");
1200 else if (opc
== 6 && I
== 0 && G
== 0 && x
== 0 && y
== 0)
1201 OUTS (outf
, "CC = A0 < A1");
1203 else if (opc
== 7 && I
== 0 && G
== 0 && x
== 0 && y
== 0)
1204 OUTS (outf
, "CC = A0 <= A1");
1212 decode_CC2dreg_0 (TIword iw0
, disassemble_info
*outf
)
1215 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1216 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1217 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1218 int op
= ((iw0
>> CC2dreg_op_bits
) & CC2dreg_op_mask
);
1219 int reg
= ((iw0
>> CC2dreg_reg_bits
) & CC2dreg_reg_mask
);
1226 OUTS (outf
, dregs (reg
));
1227 OUTS (outf
, " = CC");
1231 OUTS (outf
, "CC = ");
1232 OUTS (outf
, dregs (reg
));
1234 else if (op
== 3 && reg
== 0)
1235 OUTS (outf
, "CC = !CC");
1243 decode_CC2stat_0 (TIword iw0
, disassemble_info
*outf
)
1246 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1247 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1248 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1249 int D
= ((iw0
>> CC2stat_D_bits
) & CC2stat_D_mask
);
1250 int op
= ((iw0
>> CC2stat_op_bits
) & CC2stat_op_mask
);
1251 int cbit
= ((iw0
>> CC2stat_cbit_bits
) & CC2stat_cbit_mask
);
1253 const char *bitname
= statbits (cbit
);
1258 if (decode_statbits
[cbit
] == REG_LASTREG
)
1260 /* All ASTAT bits except CC may be operated on in hardware, but may
1261 not have a dedicated insn, so still decode "valid" insns. */
1262 static char bitnames
[64];
1264 sprintf (bitnames
, "ASTAT[%i /* unused bit */]", cbit
);
1271 if (op
== 0 && D
== 0)
1273 OUTS (outf
, "CC = ");
1274 OUTS (outf
, bitname
);
1276 else if (op
== 1 && D
== 0)
1278 OUTS (outf
, "CC |= ");
1279 OUTS (outf
, bitname
);
1281 else if (op
== 2 && D
== 0)
1283 OUTS (outf
, "CC &= ");
1284 OUTS (outf
, bitname
);
1286 else if (op
== 3 && D
== 0)
1288 OUTS (outf
, "CC ^= ");
1289 OUTS (outf
, bitname
);
1291 else if (op
== 0 && D
== 1)
1293 OUTS (outf
, bitname
);
1294 OUTS (outf
, " = CC");
1296 else if (op
== 1 && D
== 1)
1298 OUTS (outf
, bitname
);
1299 OUTS (outf
, " |= CC");
1301 else if (op
== 2 && D
== 1)
1303 OUTS (outf
, bitname
);
1304 OUTS (outf
, " &= CC");
1306 else if (op
== 3 && D
== 1)
1308 OUTS (outf
, bitname
);
1309 OUTS (outf
, " ^= CC");
1318 decode_BRCC_0 (TIword iw0
, bfd_vma pc
, disassemble_info
*outf
)
1321 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1322 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1323 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1324 int B
= ((iw0
>> BRCC_B_bits
) & BRCC_B_mask
);
1325 int T
= ((iw0
>> BRCC_T_bits
) & BRCC_T_mask
);
1326 int offset
= ((iw0
>> BRCC_offset_bits
) & BRCC_offset_mask
);
1331 if (T
== 1 && B
== 1)
1333 OUTS (outf
, "IF CC JUMP 0x");
1334 OUTS (outf
, pcrel10 (offset
));
1335 OUTS (outf
, " (BP)");
1337 else if (T
== 0 && B
== 1)
1339 OUTS (outf
, "IF !CC JUMP 0x");
1340 OUTS (outf
, pcrel10 (offset
));
1341 OUTS (outf
, " (BP)");
1345 OUTS (outf
, "IF CC JUMP 0x");
1346 OUTS (outf
, pcrel10 (offset
));
1350 OUTS (outf
, "IF !CC JUMP 0x");
1351 OUTS (outf
, pcrel10 (offset
));
1360 decode_UJUMP_0 (TIword iw0
, bfd_vma pc
, disassemble_info
*outf
)
1363 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1364 | 0 | 0 | 1 | 0 |.offset........................................|
1365 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1366 int offset
= ((iw0
>> UJump_offset_bits
) & UJump_offset_mask
);
1371 OUTS (outf
, "JUMP.S 0x");
1372 OUTS (outf
, pcrel12 (offset
));
1377 decode_REGMV_0 (TIword iw0
, disassemble_info
*outf
)
1380 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1381 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1382 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1383 int gs
= ((iw0
>> RegMv_gs_bits
) & RegMv_gs_mask
);
1384 int gd
= ((iw0
>> RegMv_gd_bits
) & RegMv_gd_mask
);
1385 int src
= ((iw0
>> RegMv_src_bits
) & RegMv_src_mask
);
1386 int dst
= ((iw0
>> RegMv_dst_bits
) & RegMv_dst_mask
);
1388 /* Reserved slots cannot be a src/dst. */
1389 if (IS_RESERVEDREG (gs
, src
) || IS_RESERVEDREG (gd
, dst
))
1392 /* Standard register moves */
1393 if ((gs
< 2) || /* Dregs/Pregs as source */
1394 (gd
< 2) || /* Dregs/Pregs as dest */
1395 (gs
== 4 && src
< 4) || /* Accumulators as source */
1396 (gd
== 4 && dst
< 4 && (gs
< 4)) || /* Accumulators as dest */
1397 (gs
== 7 && src
== 7 && !(gd
== 4 && dst
< 4)) || /* EMUDAT as src */
1398 (gd
== 7 && dst
== 7)) /* EMUDAT as dest */
1401 /* dareg = dareg (IMBL) */
1402 if (gs
< 4 && gd
< 4)
1405 /* USP can be src to sysregs, but not dagregs. */
1406 if ((gs
== 7 && src
== 0) && (gd
>= 4))
1409 /* USP can move between genregs (only check Accumulators). */
1410 if (((gs
== 7 && src
== 0) && (gd
== 4 && dst
< 4)) ||
1411 ((gd
== 7 && dst
== 0) && (gs
== 4 && src
< 4)))
1414 /* Still here ? Invalid reg pair. */
1419 OUTS (outf
, allregs (dst
, gd
));
1421 OUTS (outf
, allregs (src
, gs
));
1426 decode_ALU2op_0 (TIword iw0
, disassemble_info
*outf
)
1429 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1430 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1431 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1432 int src
= ((iw0
>> ALU2op_src_bits
) & ALU2op_src_mask
);
1433 int opc
= ((iw0
>> ALU2op_opc_bits
) & ALU2op_opc_mask
);
1434 int dst
= ((iw0
>> ALU2op_dst_bits
) & ALU2op_dst_mask
);
1438 OUTS (outf
, dregs (dst
));
1439 OUTS (outf
, " >>>= ");
1440 OUTS (outf
, dregs (src
));
1444 OUTS (outf
, dregs (dst
));
1445 OUTS (outf
, " >>= ");
1446 OUTS (outf
, dregs (src
));
1450 OUTS (outf
, dregs (dst
));
1451 OUTS (outf
, " <<= ");
1452 OUTS (outf
, dregs (src
));
1456 OUTS (outf
, dregs (dst
));
1457 OUTS (outf
, " *= ");
1458 OUTS (outf
, dregs (src
));
1462 OUTS (outf
, dregs (dst
));
1463 OUTS (outf
, " = (");
1464 OUTS (outf
, dregs (dst
));
1466 OUTS (outf
, dregs (src
));
1467 OUTS (outf
, ") << 0x1");
1471 OUTS (outf
, dregs (dst
));
1472 OUTS (outf
, " = (");
1473 OUTS (outf
, dregs (dst
));
1475 OUTS (outf
, dregs (src
));
1476 OUTS (outf
, ") << 0x2");
1480 OUTS (outf
, "DIVQ (");
1481 OUTS (outf
, dregs (dst
));
1483 OUTS (outf
, dregs (src
));
1488 OUTS (outf
, "DIVS (");
1489 OUTS (outf
, dregs (dst
));
1491 OUTS (outf
, dregs (src
));
1496 OUTS (outf
, dregs (dst
));
1498 OUTS (outf
, dregs_lo (src
));
1499 OUTS (outf
, " (X)");
1503 OUTS (outf
, dregs (dst
));
1505 OUTS (outf
, dregs_lo (src
));
1506 OUTS (outf
, " (Z)");
1510 OUTS (outf
, dregs (dst
));
1512 OUTS (outf
, dregs_byte (src
));
1513 OUTS (outf
, " (X)");
1517 OUTS (outf
, dregs (dst
));
1519 OUTS (outf
, dregs_byte (src
));
1520 OUTS (outf
, " (Z)");
1524 OUTS (outf
, dregs (dst
));
1525 OUTS (outf
, " = -");
1526 OUTS (outf
, dregs (src
));
1530 OUTS (outf
, dregs (dst
));
1531 OUTS (outf
, " =~ ");
1532 OUTS (outf
, dregs (src
));
1541 decode_PTR2op_0 (TIword iw0
, disassemble_info
*outf
)
1544 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1545 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1546 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1547 int src
= ((iw0
>> PTR2op_src_bits
) & PTR2op_dst_mask
);
1548 int opc
= ((iw0
>> PTR2op_opc_bits
) & PTR2op_opc_mask
);
1549 int dst
= ((iw0
>> PTR2op_dst_bits
) & PTR2op_dst_mask
);
1553 OUTS (outf
, pregs (dst
));
1554 OUTS (outf
, " -= ");
1555 OUTS (outf
, pregs (src
));
1559 OUTS (outf
, pregs (dst
));
1561 OUTS (outf
, pregs (src
));
1562 OUTS (outf
, " << 0x2");
1566 OUTS (outf
, pregs (dst
));
1568 OUTS (outf
, pregs (src
));
1569 OUTS (outf
, " >> 0x2");
1573 OUTS (outf
, pregs (dst
));
1575 OUTS (outf
, pregs (src
));
1576 OUTS (outf
, " >> 0x1");
1580 OUTS (outf
, pregs (dst
));
1581 OUTS (outf
, " += ");
1582 OUTS (outf
, pregs (src
));
1583 OUTS (outf
, " (BREV)");
1587 OUTS (outf
, pregs (dst
));
1588 OUTS (outf
, " = (");
1589 OUTS (outf
, pregs (dst
));
1591 OUTS (outf
, pregs (src
));
1592 OUTS (outf
, ") << 0x1");
1596 OUTS (outf
, pregs (dst
));
1597 OUTS (outf
, " = (");
1598 OUTS (outf
, pregs (dst
));
1600 OUTS (outf
, pregs (src
));
1601 OUTS (outf
, ") << 0x2");
1610 decode_LOGI2op_0 (TIword iw0
, disassemble_info
*outf
)
1613 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1614 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1615 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1616 int src
= ((iw0
>> LOGI2op_src_bits
) & LOGI2op_src_mask
);
1617 int opc
= ((iw0
>> LOGI2op_opc_bits
) & LOGI2op_opc_mask
);
1618 int dst
= ((iw0
>> LOGI2op_dst_bits
) & LOGI2op_dst_mask
);
1625 OUTS (outf
, "CC = !BITTST (");
1626 OUTS (outf
, dregs (dst
));
1628 OUTS (outf
, uimm5 (src
));
1629 OUTS (outf
, ");\t\t/* bit");
1630 OUTS (outf
, imm7d (src
));
1636 OUTS (outf
, "CC = BITTST (");
1637 OUTS (outf
, dregs (dst
));
1639 OUTS (outf
, uimm5 (src
));
1640 OUTS (outf
, ");\t\t/* bit");
1641 OUTS (outf
, imm7d (src
));
1647 OUTS (outf
, "BITSET (");
1648 OUTS (outf
, dregs (dst
));
1650 OUTS (outf
, uimm5 (src
));
1651 OUTS (outf
, ");\t\t/* bit");
1652 OUTS (outf
, imm7d (src
));
1658 OUTS (outf
, "BITTGL (");
1659 OUTS (outf
, dregs (dst
));
1661 OUTS (outf
, uimm5 (src
));
1662 OUTS (outf
, ");\t\t/* bit");
1663 OUTS (outf
, imm7d (src
));
1669 OUTS (outf
, "BITCLR (");
1670 OUTS (outf
, dregs (dst
));
1672 OUTS (outf
, uimm5 (src
));
1673 OUTS (outf
, ");\t\t/* bit");
1674 OUTS (outf
, imm7d (src
));
1680 OUTS (outf
, dregs (dst
));
1681 OUTS (outf
, " >>>= ");
1682 OUTS (outf
, uimm5 (src
));
1686 OUTS (outf
, dregs (dst
));
1687 OUTS (outf
, " >>= ");
1688 OUTS (outf
, uimm5 (src
));
1692 OUTS (outf
, dregs (dst
));
1693 OUTS (outf
, " <<= ");
1694 OUTS (outf
, uimm5 (src
));
1703 decode_COMP3op_0 (TIword iw0
, disassemble_info
*outf
)
1706 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1707 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1708 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1709 int opc
= ((iw0
>> COMP3op_opc_bits
) & COMP3op_opc_mask
);
1710 int dst
= ((iw0
>> COMP3op_dst_bits
) & COMP3op_dst_mask
);
1711 int src0
= ((iw0
>> COMP3op_src0_bits
) & COMP3op_src0_mask
);
1712 int src1
= ((iw0
>> COMP3op_src1_bits
) & COMP3op_src1_mask
);
1714 if (opc
== 5 && src1
== src0
)
1716 OUTS (outf
, pregs (dst
));
1718 OUTS (outf
, pregs (src0
));
1719 OUTS (outf
, " << 0x1");
1723 OUTS (outf
, dregs (dst
));
1725 OUTS (outf
, dregs (src0
));
1727 OUTS (outf
, dregs (src1
));
1731 OUTS (outf
, dregs (dst
));
1733 OUTS (outf
, dregs (src0
));
1735 OUTS (outf
, dregs (src1
));
1739 OUTS (outf
, dregs (dst
));
1741 OUTS (outf
, dregs (src0
));
1743 OUTS (outf
, dregs (src1
));
1747 OUTS (outf
, dregs (dst
));
1749 OUTS (outf
, dregs (src0
));
1751 OUTS (outf
, dregs (src1
));
1755 OUTS (outf
, pregs (dst
));
1757 OUTS (outf
, pregs (src0
));
1759 OUTS (outf
, pregs (src1
));
1763 OUTS (outf
, pregs (dst
));
1765 OUTS (outf
, pregs (src0
));
1766 OUTS (outf
, " + (");
1767 OUTS (outf
, pregs (src1
));
1768 OUTS (outf
, " << 0x1)");
1772 OUTS (outf
, pregs (dst
));
1774 OUTS (outf
, pregs (src0
));
1775 OUTS (outf
, " + (");
1776 OUTS (outf
, pregs (src1
));
1777 OUTS (outf
, " << 0x2)");
1781 OUTS (outf
, dregs (dst
));
1783 OUTS (outf
, dregs (src0
));
1785 OUTS (outf
, dregs (src1
));
1794 decode_COMPI2opD_0 (TIword iw0
, disassemble_info
*outf
)
1797 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1798 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1799 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1800 int op
= ((iw0
>> COMPI2opD_op_bits
) & COMPI2opD_op_mask
);
1801 int dst
= ((iw0
>> COMPI2opD_dst_bits
) & COMPI2opD_dst_mask
);
1802 int src
= ((iw0
>> COMPI2opD_src_bits
) & COMPI2opD_src_mask
);
1804 bu32
*pval
= get_allreg (0, dst
);
1809 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1810 to combine them, so it prints out the right values.
1811 Here we keep track of the registers. */
1814 *pval
= imm7_val (src
);
1816 *pval
|= 0xFFFFFF80;
1823 OUTS (outf
, dregs (dst
));
1825 OUTS (outf
, imm7 (src
));
1826 OUTS (outf
, " (X);\t\t/*\t\t");
1827 OUTS (outf
, dregs (dst
));
1829 OUTS (outf
, uimm32 (*pval
));
1831 OUTS (outf
, imm32 (*pval
));
1832 OUTS (outf
, ") */");
1837 OUTS (outf
, dregs (dst
));
1838 OUTS (outf
, " += ");
1839 OUTS (outf
, imm7 (src
));
1840 OUTS (outf
, ";\t\t/* (");
1841 OUTS (outf
, imm7d (src
));
1842 OUTS (outf
, ") */");
1852 decode_COMPI2opP_0 (TIword iw0
, disassemble_info
*outf
)
1855 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1856 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1857 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1858 int op
= ((iw0
>> COMPI2opP_op_bits
) & COMPI2opP_op_mask
);
1859 int src
= ((iw0
>> COMPI2opP_src_bits
) & COMPI2opP_src_mask
);
1860 int dst
= ((iw0
>> COMPI2opP_dst_bits
) & COMPI2opP_dst_mask
);
1862 bu32
*pval
= get_allreg (1, dst
);
1869 *pval
= imm7_val (src
);
1871 *pval
|= 0xFFFFFF80;
1878 OUTS (outf
, pregs (dst
));
1880 OUTS (outf
, imm7 (src
));
1881 OUTS (outf
, " (X);\t\t/*\t\t");
1882 OUTS (outf
, pregs (dst
));
1884 OUTS (outf
, uimm32 (*pval
));
1886 OUTS (outf
, imm32 (*pval
));
1887 OUTS (outf
, ") */");
1892 OUTS (outf
, pregs (dst
));
1893 OUTS (outf
, " += ");
1894 OUTS (outf
, imm7 (src
));
1895 OUTS (outf
, ";\t\t/* (");
1896 OUTS (outf
, imm7d (src
));
1897 OUTS (outf
, ") */");
1907 decode_LDSTpmod_0 (TIword iw0
, disassemble_info
*outf
)
1910 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1911 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1912 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1913 int W
= ((iw0
>> LDSTpmod_W_bits
) & LDSTpmod_W_mask
);
1914 int aop
= ((iw0
>> LDSTpmod_aop_bits
) & LDSTpmod_aop_mask
);
1915 int idx
= ((iw0
>> LDSTpmod_idx_bits
) & LDSTpmod_idx_mask
);
1916 int ptr
= ((iw0
>> LDSTpmod_ptr_bits
) & LDSTpmod_ptr_mask
);
1917 int reg
= ((iw0
>> LDSTpmod_reg_bits
) & LDSTpmod_reg_mask
);
1919 if (aop
== 1 && W
== 0 && idx
== ptr
)
1921 OUTS (outf
, dregs_lo (reg
));
1922 OUTS (outf
, " = W[");
1923 OUTS (outf
, pregs (ptr
));
1926 else if (aop
== 2 && W
== 0 && idx
== ptr
)
1928 OUTS (outf
, dregs_hi (reg
));
1929 OUTS (outf
, " = W[");
1930 OUTS (outf
, pregs (ptr
));
1933 else if (aop
== 1 && W
== 1 && idx
== ptr
)
1936 OUTS (outf
, pregs (ptr
));
1937 OUTS (outf
, "] = ");
1938 OUTS (outf
, dregs_lo (reg
));
1940 else if (aop
== 2 && W
== 1 && idx
== ptr
)
1943 OUTS (outf
, pregs (ptr
));
1944 OUTS (outf
, "] = ");
1945 OUTS (outf
, dregs_hi (reg
));
1947 else if (aop
== 0 && W
== 0)
1949 OUTS (outf
, dregs (reg
));
1950 OUTS (outf
, " = [");
1951 OUTS (outf
, pregs (ptr
));
1952 OUTS (outf
, " ++ ");
1953 OUTS (outf
, pregs (idx
));
1956 else if (aop
== 1 && W
== 0)
1958 OUTS (outf
, dregs_lo (reg
));
1959 OUTS (outf
, " = W[");
1960 OUTS (outf
, pregs (ptr
));
1961 OUTS (outf
, " ++ ");
1962 OUTS (outf
, pregs (idx
));
1965 else if (aop
== 2 && W
== 0)
1967 OUTS (outf
, dregs_hi (reg
));
1968 OUTS (outf
, " = W[");
1969 OUTS (outf
, pregs (ptr
));
1970 OUTS (outf
, " ++ ");
1971 OUTS (outf
, pregs (idx
));
1974 else if (aop
== 3 && W
== 0)
1976 OUTS (outf
, dregs (reg
));
1977 OUTS (outf
, " = W[");
1978 OUTS (outf
, pregs (ptr
));
1979 OUTS (outf
, " ++ ");
1980 OUTS (outf
, pregs (idx
));
1981 OUTS (outf
, "] (Z)");
1983 else if (aop
== 3 && W
== 1)
1985 OUTS (outf
, dregs (reg
));
1986 OUTS (outf
, " = W[");
1987 OUTS (outf
, pregs (ptr
));
1988 OUTS (outf
, " ++ ");
1989 OUTS (outf
, pregs (idx
));
1990 OUTS (outf
, "] (X)");
1992 else if (aop
== 0 && W
== 1)
1995 OUTS (outf
, pregs (ptr
));
1996 OUTS (outf
, " ++ ");
1997 OUTS (outf
, pregs (idx
));
1998 OUTS (outf
, "] = ");
1999 OUTS (outf
, dregs (reg
));
2001 else if (aop
== 1 && W
== 1)
2004 OUTS (outf
, pregs (ptr
));
2005 OUTS (outf
, " ++ ");
2006 OUTS (outf
, pregs (idx
));
2007 OUTS (outf
, "] = ");
2008 OUTS (outf
, dregs_lo (reg
));
2010 else if (aop
== 2 && W
== 1)
2013 OUTS (outf
, pregs (ptr
));
2014 OUTS (outf
, " ++ ");
2015 OUTS (outf
, pregs (idx
));
2016 OUTS (outf
, "] = ");
2017 OUTS (outf
, dregs_hi (reg
));
2026 decode_dagMODim_0 (TIword iw0
, disassemble_info
*outf
)
2029 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2030 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2031 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2032 int i
= ((iw0
>> DagMODim_i_bits
) & DagMODim_i_mask
);
2033 int m
= ((iw0
>> DagMODim_m_bits
) & DagMODim_m_mask
);
2034 int br
= ((iw0
>> DagMODim_br_bits
) & DagMODim_br_mask
);
2035 int op
= ((iw0
>> DagMODim_op_bits
) & DagMODim_op_mask
);
2037 if (op
== 0 && br
== 1)
2039 OUTS (outf
, iregs (i
));
2040 OUTS (outf
, " += ");
2041 OUTS (outf
, mregs (m
));
2042 OUTS (outf
, " (BREV)");
2046 OUTS (outf
, iregs (i
));
2047 OUTS (outf
, " += ");
2048 OUTS (outf
, mregs (m
));
2050 else if (op
== 1 && br
== 0)
2052 OUTS (outf
, iregs (i
));
2053 OUTS (outf
, " -= ");
2054 OUTS (outf
, mregs (m
));
2063 decode_dagMODik_0 (TIword iw0
, disassemble_info
*outf
)
2066 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2067 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2068 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2069 int i
= ((iw0
>> DagMODik_i_bits
) & DagMODik_i_mask
);
2070 int op
= ((iw0
>> DagMODik_op_bits
) & DagMODik_op_mask
);
2074 OUTS (outf
, iregs (i
));
2075 OUTS (outf
, " += 0x2");
2079 OUTS (outf
, iregs (i
));
2080 OUTS (outf
, " -= 0x2");
2084 OUTS (outf
, iregs (i
));
2085 OUTS (outf
, " += 0x4");
2089 OUTS (outf
, iregs (i
));
2090 OUTS (outf
, " -= 0x4");
2097 OUTS (outf
, ";\t\t/* ( ");
2098 if (op
== 0 || op
== 1)
2100 else if (op
== 2 || op
== 3)
2102 OUTS (outf
, ") */");
2110 decode_dspLDST_0 (TIword iw0
, disassemble_info
*outf
)
2113 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2114 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2115 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2116 int i
= ((iw0
>> DspLDST_i_bits
) & DspLDST_i_mask
);
2117 int m
= ((iw0
>> DspLDST_m_bits
) & DspLDST_m_mask
);
2118 int W
= ((iw0
>> DspLDST_W_bits
) & DspLDST_W_mask
);
2119 int aop
= ((iw0
>> DspLDST_aop_bits
) & DspLDST_aop_mask
);
2120 int reg
= ((iw0
>> DspLDST_reg_bits
) & DspLDST_reg_mask
);
2122 if (aop
== 0 && W
== 0 && m
== 0)
2124 OUTS (outf
, dregs (reg
));
2125 OUTS (outf
, " = [");
2126 OUTS (outf
, iregs (i
));
2129 else if (aop
== 0 && W
== 0 && m
== 1)
2131 OUTS (outf
, dregs_lo (reg
));
2132 OUTS (outf
, " = W[");
2133 OUTS (outf
, iregs (i
));
2136 else if (aop
== 0 && W
== 0 && m
== 2)
2138 OUTS (outf
, dregs_hi (reg
));
2139 OUTS (outf
, " = W[");
2140 OUTS (outf
, iregs (i
));
2143 else if (aop
== 1 && W
== 0 && m
== 0)
2145 OUTS (outf
, dregs (reg
));
2146 OUTS (outf
, " = [");
2147 OUTS (outf
, iregs (i
));
2150 else if (aop
== 1 && W
== 0 && m
== 1)
2152 OUTS (outf
, dregs_lo (reg
));
2153 OUTS (outf
, " = W[");
2154 OUTS (outf
, iregs (i
));
2157 else if (aop
== 1 && W
== 0 && m
== 2)
2159 OUTS (outf
, dregs_hi (reg
));
2160 OUTS (outf
, " = W[");
2161 OUTS (outf
, iregs (i
));
2164 else if (aop
== 2 && W
== 0 && m
== 0)
2166 OUTS (outf
, dregs (reg
));
2167 OUTS (outf
, " = [");
2168 OUTS (outf
, iregs (i
));
2171 else if (aop
== 2 && W
== 0 && m
== 1)
2173 OUTS (outf
, dregs_lo (reg
));
2174 OUTS (outf
, " = W[");
2175 OUTS (outf
, iregs (i
));
2178 else if (aop
== 2 && W
== 0 && m
== 2)
2180 OUTS (outf
, dregs_hi (reg
));
2181 OUTS (outf
, " = W[");
2182 OUTS (outf
, iregs (i
));
2185 else if (aop
== 0 && W
== 1 && m
== 0)
2188 OUTS (outf
, iregs (i
));
2189 OUTS (outf
, "++] = ");
2190 OUTS (outf
, dregs (reg
));
2192 else if (aop
== 0 && W
== 1 && m
== 1)
2195 OUTS (outf
, iregs (i
));
2196 OUTS (outf
, "++] = ");
2197 OUTS (outf
, dregs_lo (reg
));
2199 else if (aop
== 0 && W
== 1 && m
== 2)
2202 OUTS (outf
, iregs (i
));
2203 OUTS (outf
, "++] = ");
2204 OUTS (outf
, dregs_hi (reg
));
2206 else if (aop
== 1 && W
== 1 && m
== 0)
2209 OUTS (outf
, iregs (i
));
2210 OUTS (outf
, "--] = ");
2211 OUTS (outf
, dregs (reg
));
2213 else if (aop
== 1 && W
== 1 && m
== 1)
2216 OUTS (outf
, iregs (i
));
2217 OUTS (outf
, "--] = ");
2218 OUTS (outf
, dregs_lo (reg
));
2220 else if (aop
== 1 && W
== 1 && m
== 2)
2223 OUTS (outf
, iregs (i
));
2224 OUTS (outf
, "--] = ");
2225 OUTS (outf
, dregs_hi (reg
));
2227 else if (aop
== 2 && W
== 1 && m
== 0)
2230 OUTS (outf
, iregs (i
));
2231 OUTS (outf
, "] = ");
2232 OUTS (outf
, dregs (reg
));
2234 else if (aop
== 2 && W
== 1 && m
== 1)
2237 OUTS (outf
, iregs (i
));
2238 OUTS (outf
, "] = ");
2239 OUTS (outf
, dregs_lo (reg
));
2241 else if (aop
== 2 && W
== 1 && m
== 2)
2244 OUTS (outf
, iregs (i
));
2245 OUTS (outf
, "] = ");
2246 OUTS (outf
, dregs_hi (reg
));
2248 else if (aop
== 3 && W
== 0)
2250 OUTS (outf
, dregs (reg
));
2251 OUTS (outf
, " = [");
2252 OUTS (outf
, iregs (i
));
2253 OUTS (outf
, " ++ ");
2254 OUTS (outf
, mregs (m
));
2257 else if (aop
== 3 && W
== 1)
2260 OUTS (outf
, iregs (i
));
2261 OUTS (outf
, " ++ ");
2262 OUTS (outf
, mregs (m
));
2263 OUTS (outf
, "] = ");
2264 OUTS (outf
, dregs (reg
));
2273 decode_LDST_0 (TIword iw0
, disassemble_info
*outf
)
2276 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2277 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2278 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2279 int Z
= ((iw0
>> LDST_Z_bits
) & LDST_Z_mask
);
2280 int W
= ((iw0
>> LDST_W_bits
) & LDST_W_mask
);
2281 int sz
= ((iw0
>> LDST_sz_bits
) & LDST_sz_mask
);
2282 int aop
= ((iw0
>> LDST_aop_bits
) & LDST_aop_mask
);
2283 int reg
= ((iw0
>> LDST_reg_bits
) & LDST_reg_mask
);
2284 int ptr
= ((iw0
>> LDST_ptr_bits
) & LDST_ptr_mask
);
2286 if (aop
== 0 && sz
== 0 && Z
== 0 && W
== 0)
2288 OUTS (outf
, dregs (reg
));
2289 OUTS (outf
, " = [");
2290 OUTS (outf
, pregs (ptr
));
2293 else if (aop
== 0 && sz
== 0 && Z
== 1 && W
== 0 && reg
!= ptr
)
2295 OUTS (outf
, pregs (reg
));
2296 OUTS (outf
, " = [");
2297 OUTS (outf
, pregs (ptr
));
2300 else if (aop
== 0 && sz
== 1 && Z
== 0 && W
== 0)
2302 OUTS (outf
, dregs (reg
));
2303 OUTS (outf
, " = W[");
2304 OUTS (outf
, pregs (ptr
));
2305 OUTS (outf
, "++] (Z)");
2307 else if (aop
== 0 && sz
== 1 && Z
== 1 && W
== 0)
2309 OUTS (outf
, dregs (reg
));
2310 OUTS (outf
, " = W[");
2311 OUTS (outf
, pregs (ptr
));
2312 OUTS (outf
, "++] (X)");
2314 else if (aop
== 0 && sz
== 2 && Z
== 0 && W
== 0)
2316 OUTS (outf
, dregs (reg
));
2317 OUTS (outf
, " = B[");
2318 OUTS (outf
, pregs (ptr
));
2319 OUTS (outf
, "++] (Z)");
2321 else if (aop
== 0 && sz
== 2 && Z
== 1 && W
== 0)
2323 OUTS (outf
, dregs (reg
));
2324 OUTS (outf
, " = B[");
2325 OUTS (outf
, pregs (ptr
));
2326 OUTS (outf
, "++] (X)");
2328 else if (aop
== 1 && sz
== 0 && Z
== 0 && W
== 0)
2330 OUTS (outf
, dregs (reg
));
2331 OUTS (outf
, " = [");
2332 OUTS (outf
, pregs (ptr
));
2335 else if (aop
== 1 && sz
== 0 && Z
== 1 && W
== 0 && reg
!= ptr
)
2337 OUTS (outf
, pregs (reg
));
2338 OUTS (outf
, " = [");
2339 OUTS (outf
, pregs (ptr
));
2342 else if (aop
== 1 && sz
== 1 && Z
== 0 && W
== 0)
2344 OUTS (outf
, dregs (reg
));
2345 OUTS (outf
, " = W[");
2346 OUTS (outf
, pregs (ptr
));
2347 OUTS (outf
, "--] (Z)");
2349 else if (aop
== 1 && sz
== 1 && Z
== 1 && W
== 0)
2351 OUTS (outf
, dregs (reg
));
2352 OUTS (outf
, " = W[");
2353 OUTS (outf
, pregs (ptr
));
2354 OUTS (outf
, "--] (X)");
2356 else if (aop
== 1 && sz
== 2 && Z
== 0 && W
== 0)
2358 OUTS (outf
, dregs (reg
));
2359 OUTS (outf
, " = B[");
2360 OUTS (outf
, pregs (ptr
));
2361 OUTS (outf
, "--] (Z)");
2363 else if (aop
== 1 && sz
== 2 && Z
== 1 && W
== 0)
2365 OUTS (outf
, dregs (reg
));
2366 OUTS (outf
, " = B[");
2367 OUTS (outf
, pregs (ptr
));
2368 OUTS (outf
, "--] (X)");
2370 else if (aop
== 2 && sz
== 0 && Z
== 0 && W
== 0)
2372 OUTS (outf
, dregs (reg
));
2373 OUTS (outf
, " = [");
2374 OUTS (outf
, pregs (ptr
));
2377 else if (aop
== 2 && sz
== 0 && Z
== 1 && W
== 0)
2379 OUTS (outf
, pregs (reg
));
2380 OUTS (outf
, " = [");
2381 OUTS (outf
, pregs (ptr
));
2384 else if (aop
== 2 && sz
== 1 && Z
== 0 && W
== 0)
2386 OUTS (outf
, dregs (reg
));
2387 OUTS (outf
, " = W[");
2388 OUTS (outf
, pregs (ptr
));
2389 OUTS (outf
, "] (Z)");
2391 else if (aop
== 2 && sz
== 1 && Z
== 1 && W
== 0)
2393 OUTS (outf
, dregs (reg
));
2394 OUTS (outf
, " = W[");
2395 OUTS (outf
, pregs (ptr
));
2396 OUTS (outf
, "] (X)");
2398 else if (aop
== 2 && sz
== 2 && Z
== 0 && W
== 0)
2400 OUTS (outf
, dregs (reg
));
2401 OUTS (outf
, " = B[");
2402 OUTS (outf
, pregs (ptr
));
2403 OUTS (outf
, "] (Z)");
2405 else if (aop
== 2 && sz
== 2 && Z
== 1 && W
== 0)
2407 OUTS (outf
, dregs (reg
));
2408 OUTS (outf
, " = B[");
2409 OUTS (outf
, pregs (ptr
));
2410 OUTS (outf
, "] (X)");
2412 else if (aop
== 0 && sz
== 0 && Z
== 0 && W
== 1)
2415 OUTS (outf
, pregs (ptr
));
2416 OUTS (outf
, "++] = ");
2417 OUTS (outf
, dregs (reg
));
2419 else if (aop
== 0 && sz
== 0 && Z
== 1 && W
== 1)
2422 OUTS (outf
, pregs (ptr
));
2423 OUTS (outf
, "++] = ");
2424 OUTS (outf
, pregs (reg
));
2426 else if (aop
== 0 && sz
== 1 && Z
== 0 && W
== 1)
2429 OUTS (outf
, pregs (ptr
));
2430 OUTS (outf
, "++] = ");
2431 OUTS (outf
, dregs (reg
));
2433 else if (aop
== 0 && sz
== 2 && Z
== 0 && W
== 1)
2436 OUTS (outf
, pregs (ptr
));
2437 OUTS (outf
, "++] = ");
2438 OUTS (outf
, dregs (reg
));
2440 else if (aop
== 1 && sz
== 0 && Z
== 0 && W
== 1)
2443 OUTS (outf
, pregs (ptr
));
2444 OUTS (outf
, "--] = ");
2445 OUTS (outf
, dregs (reg
));
2447 else if (aop
== 1 && sz
== 0 && Z
== 1 && W
== 1)
2450 OUTS (outf
, pregs (ptr
));
2451 OUTS (outf
, "--] = ");
2452 OUTS (outf
, pregs (reg
));
2454 else if (aop
== 1 && sz
== 1 && Z
== 0 && W
== 1)
2457 OUTS (outf
, pregs (ptr
));
2458 OUTS (outf
, "--] = ");
2459 OUTS (outf
, dregs (reg
));
2461 else if (aop
== 1 && sz
== 2 && Z
== 0 && W
== 1)
2464 OUTS (outf
, pregs (ptr
));
2465 OUTS (outf
, "--] = ");
2466 OUTS (outf
, dregs (reg
));
2468 else if (aop
== 2 && sz
== 0 && Z
== 0 && W
== 1)
2471 OUTS (outf
, pregs (ptr
));
2472 OUTS (outf
, "] = ");
2473 OUTS (outf
, dregs (reg
));
2475 else if (aop
== 2 && sz
== 0 && Z
== 1 && W
== 1)
2478 OUTS (outf
, pregs (ptr
));
2479 OUTS (outf
, "] = ");
2480 OUTS (outf
, pregs (reg
));
2482 else if (aop
== 2 && sz
== 1 && Z
== 0 && W
== 1)
2485 OUTS (outf
, pregs (ptr
));
2486 OUTS (outf
, "] = ");
2487 OUTS (outf
, dregs (reg
));
2489 else if (aop
== 2 && sz
== 2 && Z
== 0 && W
== 1)
2492 OUTS (outf
, pregs (ptr
));
2493 OUTS (outf
, "] = ");
2494 OUTS (outf
, dregs (reg
));
2503 decode_LDSTiiFP_0 (TIword iw0
, disassemble_info
*outf
)
2506 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2507 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2508 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2509 int reg
= ((iw0
>> LDSTiiFP_reg_bits
) & LDSTiiFP_reg_mask
);
2510 int offset
= ((iw0
>> LDSTiiFP_offset_bits
) & LDSTiiFP_offset_mask
);
2511 int W
= ((iw0
>> LDSTiiFP_W_bits
) & LDSTiiFP_W_mask
);
2515 OUTS (outf
, dpregs (reg
));
2516 OUTS (outf
, " = [FP ");
2517 OUTS (outf
, negimm5s4 (offset
));
2522 OUTS (outf
, "[FP ");
2523 OUTS (outf
, negimm5s4 (offset
));
2524 OUTS (outf
, "] = ");
2525 OUTS (outf
, dpregs (reg
));
2534 decode_LDSTii_0 (TIword iw0
, disassemble_info
*outf
)
2537 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2538 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2539 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2540 int reg
= ((iw0
>> LDSTii_reg_bit
) & LDSTii_reg_mask
);
2541 int ptr
= ((iw0
>> LDSTii_ptr_bit
) & LDSTii_ptr_mask
);
2542 int offset
= ((iw0
>> LDSTii_offset_bit
) & LDSTii_offset_mask
);
2543 int op
= ((iw0
>> LDSTii_op_bit
) & LDSTii_op_mask
);
2544 int W
= ((iw0
>> LDSTii_W_bit
) & LDSTii_W_mask
);
2546 if (W
== 0 && op
== 0)
2548 OUTS (outf
, dregs (reg
));
2549 OUTS (outf
, " = [");
2550 OUTS (outf
, pregs (ptr
));
2552 OUTS (outf
, uimm4s4 (offset
));
2555 else if (W
== 0 && op
== 1)
2557 OUTS (outf
, dregs (reg
));
2558 OUTS (outf
, " = W[");
2559 OUTS (outf
, pregs (ptr
));
2561 OUTS (outf
, uimm4s2 (offset
));
2562 OUTS (outf
, "] (Z)");
2564 else if (W
== 0 && op
== 2)
2566 OUTS (outf
, dregs (reg
));
2567 OUTS (outf
, " = W[");
2568 OUTS (outf
, pregs (ptr
));
2570 OUTS (outf
, uimm4s2 (offset
));
2571 OUTS (outf
, "] (X)");
2573 else if (W
== 0 && op
== 3)
2575 OUTS (outf
, pregs (reg
));
2576 OUTS (outf
, " = [");
2577 OUTS (outf
, pregs (ptr
));
2579 OUTS (outf
, uimm4s4 (offset
));
2582 else if (W
== 1 && op
== 0)
2585 OUTS (outf
, pregs (ptr
));
2587 OUTS (outf
, uimm4s4 (offset
));
2588 OUTS (outf
, "] = ");
2589 OUTS (outf
, dregs (reg
));
2591 else if (W
== 1 && op
== 1)
2594 OUTS (outf
, pregs (ptr
));
2596 OUTS (outf
, uimm4s2 (offset
));
2597 OUTS (outf
, "] = ");
2598 OUTS (outf
, dregs (reg
));
2600 else if (W
== 1 && op
== 3)
2603 OUTS (outf
, pregs (ptr
));
2605 OUTS (outf
, uimm4s4 (offset
));
2606 OUTS (outf
, "] = ");
2607 OUTS (outf
, pregs (reg
));
2616 decode_LoopSetup_0 (TIword iw0
, TIword iw1
, bfd_vma pc
, disassemble_info
*outf
)
2619 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2620 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2621 |.reg...........| - | - |.eoffset...............................|
2622 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2623 int c
= ((iw0
>> (LoopSetup_c_bits
- 16)) & LoopSetup_c_mask
);
2624 int reg
= ((iw1
>> LoopSetup_reg_bits
) & LoopSetup_reg_mask
);
2625 int rop
= ((iw0
>> (LoopSetup_rop_bits
- 16)) & LoopSetup_rop_mask
);
2626 int soffset
= ((iw0
>> (LoopSetup_soffset_bits
- 16)) & LoopSetup_soffset_mask
);
2627 int eoffset
= ((iw1
>> LoopSetup_eoffset_bits
) & LoopSetup_eoffset_mask
);
2634 OUTS (outf
, "LSETUP");
2636 OUTS (outf
, pcrel4 (soffset
));
2637 OUTS (outf
, ", 0x");
2638 OUTS (outf
, lppcrel10 (eoffset
));
2640 OUTS (outf
, counters (c
));
2644 OUTS (outf
, "LSETUP");
2646 OUTS (outf
, pcrel4 (soffset
));
2647 OUTS (outf
, ", 0x");
2648 OUTS (outf
, lppcrel10 (eoffset
));
2650 OUTS (outf
, counters (c
));
2652 OUTS (outf
, pregs (reg
));
2656 OUTS (outf
, "LSETUP");
2658 OUTS (outf
, pcrel4 (soffset
));
2659 OUTS (outf
, ", 0x");
2660 OUTS (outf
, lppcrel10 (eoffset
));
2662 OUTS (outf
, counters (c
));
2664 OUTS (outf
, pregs (reg
));
2665 OUTS (outf
, " >> 0x1");
2674 decode_LDIMMhalf_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
2677 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2678 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2679 |.hword.........................................................|
2680 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2681 int H
= ((iw0
>> (LDIMMhalf_H_bits
- 16)) & LDIMMhalf_H_mask
);
2682 int Z
= ((iw0
>> (LDIMMhalf_Z_bits
- 16)) & LDIMMhalf_Z_mask
);
2683 int S
= ((iw0
>> (LDIMMhalf_S_bits
- 16)) & LDIMMhalf_S_mask
);
2684 int reg
= ((iw0
>> (LDIMMhalf_reg_bits
- 16)) & LDIMMhalf_reg_mask
);
2685 int grp
= ((iw0
>> (LDIMMhalf_grp_bits
- 16)) & LDIMMhalf_grp_mask
);
2686 int hword
= ((iw1
>> LDIMMhalf_hword_bits
) & LDIMMhalf_hword_mask
);
2688 bu32
*pval
= get_allreg (grp
, reg
);
2693 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2694 to combine them, so it prints out the right values.
2695 Here we keep track of the registers. */
2696 if (H
== 0 && S
== 1 && Z
== 0)
2698 /* regs = imm16 (x) */
2699 *pval
= imm16_val (hword
);
2701 *pval
|= 0xFFFF0000;
2705 else if (H
== 0 && S
== 0 && Z
== 1)
2707 /* regs = luimm16 (Z) */
2708 *pval
= luimm16_val (hword
);
2711 else if (H
== 0 && S
== 0 && Z
== 0)
2713 /* regs_lo = luimm16 */
2714 *pval
&= 0xFFFF0000;
2715 *pval
|= luimm16_val (hword
);
2717 else if (H
== 1 && S
== 0 && Z
== 0)
2719 /* regs_hi = huimm16 */
2721 *pval
|= luimm16_val (hword
) << 16;
2724 /* Here we do the disassembly */
2725 if (grp
== 0 && H
== 0 && S
== 0 && Z
== 0)
2727 OUTS (outf
, dregs_lo (reg
));
2729 OUTS (outf
, uimm16 (hword
));
2731 else if (grp
== 0 && H
== 1 && S
== 0 && Z
== 0)
2733 OUTS (outf
, dregs_hi (reg
));
2735 OUTS (outf
, uimm16 (hword
));
2737 else if (grp
== 0 && H
== 0 && S
== 1 && Z
== 0)
2739 OUTS (outf
, dregs (reg
));
2741 OUTS (outf
, imm16 (hword
));
2742 OUTS (outf
, " (X)");
2744 else if (H
== 0 && S
== 1 && Z
== 0)
2746 OUTS (outf
, regs (reg
, grp
));
2748 OUTS (outf
, imm16 (hword
));
2749 OUTS (outf
, " (X)");
2751 else if (H
== 0 && S
== 0 && Z
== 1)
2753 OUTS (outf
, regs (reg
, grp
));
2755 OUTS (outf
, uimm16 (hword
));
2756 OUTS (outf
, " (Z)");
2758 else if (H
== 0 && S
== 0 && Z
== 0)
2760 OUTS (outf
, regs_lo (reg
, grp
));
2762 OUTS (outf
, uimm16 (hword
));
2764 else if (H
== 1 && S
== 0 && Z
== 0)
2766 OUTS (outf
, regs_hi (reg
, grp
));
2768 OUTS (outf
, uimm16 (hword
));
2773 /* And we print out the 32-bit value if it is a pointer. */
2774 if (S
== 0 && Z
== 0)
2776 OUTS (outf
, ";\t\t/* (");
2777 OUTS (outf
, imm16d (hword
));
2780 /* If it is an MMR, don't print the symbol. */
2781 if (*pval
< 0xFFC00000 && grp
== 1)
2783 OUTS (outf
, regs (reg
, grp
));
2785 OUTS (outf
, huimm32e (*pval
));
2789 OUTS (outf
, regs (reg
, grp
));
2791 OUTS (outf
, huimm32e (*pval
));
2793 OUTS (outf
, imm32 (*pval
));
2800 if (S
== 1 || Z
== 1)
2802 OUTS (outf
, ";\t\t/*\t\t");
2803 OUTS (outf
, regs (reg
, grp
));
2805 OUTS (outf
, huimm32e (*pval
));
2807 OUTS (outf
, imm32 (*pval
));
2808 OUTS (outf
, ") */");
2815 decode_CALLa_0 (TIword iw0
, TIword iw1
, bfd_vma pc
, disassemble_info
*outf
)
2818 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2819 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2820 |.lsw...........................................................|
2821 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2822 int S
= ((iw0
>> (CALLa_S_bits
- 16)) & CALLa_S_mask
);
2823 int lsw
= ((iw1
>> 0) & 0xffff);
2824 int msw
= ((iw0
>> 0) & 0xff);
2830 OUTS (outf
, "CALL 0x");
2832 OUTS (outf
, "JUMP.L 0x");
2836 OUTS (outf
, pcrel24 (((msw
) << 16) | (lsw
)));
2841 decode_LDSTidxI_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
2844 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2845 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2846 |.offset........................................................|
2847 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2848 int Z
= ((iw0
>> (LDSTidxI_Z_bits
- 16)) & LDSTidxI_Z_mask
);
2849 int W
= ((iw0
>> (LDSTidxI_W_bits
- 16)) & LDSTidxI_W_mask
);
2850 int sz
= ((iw0
>> (LDSTidxI_sz_bits
- 16)) & LDSTidxI_sz_mask
);
2851 int reg
= ((iw0
>> (LDSTidxI_reg_bits
- 16)) & LDSTidxI_reg_mask
);
2852 int ptr
= ((iw0
>> (LDSTidxI_ptr_bits
- 16)) & LDSTidxI_ptr_mask
);
2853 int offset
= ((iw1
>> LDSTidxI_offset_bits
) & LDSTidxI_offset_mask
);
2855 if (W
== 0 && sz
== 0 && Z
== 0)
2857 OUTS (outf
, dregs (reg
));
2858 OUTS (outf
, " = [");
2859 OUTS (outf
, pregs (ptr
));
2861 OUTS (outf
, imm16s4 (offset
));
2864 else if (W
== 0 && sz
== 0 && Z
== 1)
2866 OUTS (outf
, pregs (reg
));
2867 OUTS (outf
, " = [");
2868 OUTS (outf
, pregs (ptr
));
2870 OUTS (outf
, imm16s4 (offset
));
2873 else if (W
== 0 && sz
== 1 && Z
== 0)
2875 OUTS (outf
, dregs (reg
));
2876 OUTS (outf
, " = W[");
2877 OUTS (outf
, pregs (ptr
));
2879 OUTS (outf
, imm16s2 (offset
));
2880 OUTS (outf
, "] (Z)");
2882 else if (W
== 0 && sz
== 1 && Z
== 1)
2884 OUTS (outf
, dregs (reg
));
2885 OUTS (outf
, " = W[");
2886 OUTS (outf
, pregs (ptr
));
2888 OUTS (outf
, imm16s2 (offset
));
2889 OUTS (outf
, "] (X)");
2891 else if (W
== 0 && sz
== 2 && Z
== 0)
2893 OUTS (outf
, dregs (reg
));
2894 OUTS (outf
, " = B[");
2895 OUTS (outf
, pregs (ptr
));
2897 OUTS (outf
, imm16 (offset
));
2898 OUTS (outf
, "] (Z)");
2900 else if (W
== 0 && sz
== 2 && Z
== 1)
2902 OUTS (outf
, dregs (reg
));
2903 OUTS (outf
, " = B[");
2904 OUTS (outf
, pregs (ptr
));
2906 OUTS (outf
, imm16 (offset
));
2907 OUTS (outf
, "] (X)");
2909 else if (W
== 1 && sz
== 0 && Z
== 0)
2912 OUTS (outf
, pregs (ptr
));
2914 OUTS (outf
, imm16s4 (offset
));
2915 OUTS (outf
, "] = ");
2916 OUTS (outf
, dregs (reg
));
2918 else if (W
== 1 && sz
== 0 && Z
== 1)
2921 OUTS (outf
, pregs (ptr
));
2923 OUTS (outf
, imm16s4 (offset
));
2924 OUTS (outf
, "] = ");
2925 OUTS (outf
, pregs (reg
));
2927 else if (W
== 1 && sz
== 1 && Z
== 0)
2930 OUTS (outf
, pregs (ptr
));
2932 OUTS (outf
, imm16s2 (offset
));
2933 OUTS (outf
, "] = ");
2934 OUTS (outf
, dregs (reg
));
2936 else if (W
== 1 && sz
== 2 && Z
== 0)
2939 OUTS (outf
, pregs (ptr
));
2941 OUTS (outf
, imm16 (offset
));
2942 OUTS (outf
, "] = ");
2943 OUTS (outf
, dregs (reg
));
2952 decode_linkage_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
2955 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2956 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2957 |.framesize.....................................................|
2958 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2959 int R
= ((iw0
>> (Linkage_R_bits
- 16)) & Linkage_R_mask
);
2960 int framesize
= ((iw1
>> Linkage_framesize_bits
) & Linkage_framesize_mask
);
2967 OUTS (outf
, "LINK ");
2968 OUTS (outf
, uimm16s4 (framesize
));
2969 OUTS (outf
, ";\t\t/* (");
2970 OUTS (outf
, uimm16s4d (framesize
));
2971 OUTS (outf
, ") */");
2975 OUTS (outf
, "UNLINK");
2983 decode_dsp32mac_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
2986 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2987 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2988 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2989 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2990 int op1
= ((iw0
>> (DSP32Mac_op1_bits
- 16)) & DSP32Mac_op1_mask
);
2991 int w1
= ((iw0
>> (DSP32Mac_w1_bits
- 16)) & DSP32Mac_w1_mask
);
2992 int P
= ((iw0
>> (DSP32Mac_p_bits
- 16)) & DSP32Mac_p_mask
);
2993 int MM
= ((iw0
>> (DSP32Mac_MM_bits
- 16)) & DSP32Mac_MM_mask
);
2994 int mmod
= ((iw0
>> (DSP32Mac_mmod_bits
- 16)) & DSP32Mac_mmod_mask
);
2995 int w0
= ((iw1
>> DSP32Mac_w0_bits
) & DSP32Mac_w0_mask
);
2996 int src0
= ((iw1
>> DSP32Mac_src0_bits
) & DSP32Mac_src0_mask
);
2997 int src1
= ((iw1
>> DSP32Mac_src1_bits
) & DSP32Mac_src1_mask
);
2998 int dst
= ((iw1
>> DSP32Mac_dst_bits
) & DSP32Mac_dst_mask
);
2999 int h10
= ((iw1
>> DSP32Mac_h10_bits
) & DSP32Mac_h10_mask
);
3000 int h00
= ((iw1
>> DSP32Mac_h00_bits
) & DSP32Mac_h00_mask
);
3001 int op0
= ((iw1
>> DSP32Mac_op0_bits
) & DSP32Mac_op0_mask
);
3002 int h11
= ((iw1
>> DSP32Mac_h11_bits
) & DSP32Mac_h11_mask
);
3003 int h01
= ((iw1
>> DSP32Mac_h01_bits
) & DSP32Mac_h01_mask
);
3005 if (w0
== 0 && w1
== 0 && op1
== 3 && op0
== 3)
3011 if ((w1
|| w0
) && mmod
== M_W32
)
3014 if (((1 << mmod
) & (P
? 0x131b : 0x1b5f)) == 0)
3017 if (w1
== 1 || op1
!= 3)
3020 OUTS (outf
, P
? dregs (dst
+ 1) : dregs_hi (dst
));
3023 OUTS (outf
, " = A1");
3027 OUTS (outf
, " = (");
3028 decode_macfunc (1, op1
, h01
, h11
, src0
, src1
, outf
);
3033 if (w0
== 1 || op0
!= 3)
3036 OUTS (outf
, " (M)");
3042 if (w0
== 1 || op0
!= 3)
3045 OUTS (outf
, P
? dregs (dst
) : dregs_lo (dst
));
3048 OUTS (outf
, " = A0");
3052 OUTS (outf
, " = (");
3053 decode_macfunc (0, op0
, h00
, h10
, src0
, src1
, outf
);
3059 decode_optmode (mmod
, MM
, outf
);
3065 decode_dsp32mult_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
3068 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3069 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3070 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3071 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3072 int w1
= ((iw0
>> (DSP32Mac_w1_bits
- 16)) & DSP32Mac_w1_mask
);
3073 int P
= ((iw0
>> (DSP32Mac_p_bits
- 16)) & DSP32Mac_p_mask
);
3074 int MM
= ((iw0
>> (DSP32Mac_MM_bits
- 16)) & DSP32Mac_MM_mask
);
3075 int mmod
= ((iw0
>> (DSP32Mac_mmod_bits
- 16)) & DSP32Mac_mmod_mask
);
3076 int w0
= ((iw1
>> DSP32Mac_w0_bits
) & DSP32Mac_w0_mask
);
3077 int src0
= ((iw1
>> DSP32Mac_src0_bits
) & DSP32Mac_src0_mask
);
3078 int src1
= ((iw1
>> DSP32Mac_src1_bits
) & DSP32Mac_src1_mask
);
3079 int dst
= ((iw1
>> DSP32Mac_dst_bits
) & DSP32Mac_dst_mask
);
3080 int h10
= ((iw1
>> DSP32Mac_h10_bits
) & DSP32Mac_h10_mask
);
3081 int h00
= ((iw1
>> DSP32Mac_h00_bits
) & DSP32Mac_h00_mask
);
3082 int h11
= ((iw1
>> DSP32Mac_h11_bits
) & DSP32Mac_h11_mask
);
3083 int h01
= ((iw1
>> DSP32Mac_h01_bits
) & DSP32Mac_h01_mask
);
3085 if (w1
== 0 && w0
== 0)
3088 if (((1 << mmod
) & (P
? 0x313 : 0x1b57)) == 0)
3093 OUTS (outf
, P
? dregs (dst
| 1) : dregs_hi (dst
));
3095 decode_multfunc (h01
, h11
, src0
, src1
, outf
);
3100 OUTS (outf
, " (M)");
3108 OUTS (outf
, dregs (dst
));
3110 decode_multfunc (h00
, h10
, src0
, src1
, outf
);
3113 decode_optmode (mmod
, MM
, outf
);
3118 decode_dsp32alu_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
3121 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3122 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3123 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3124 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3125 int s
= ((iw1
>> DSP32Alu_s_bits
) & DSP32Alu_s_mask
);
3126 int x
= ((iw1
>> DSP32Alu_x_bits
) & DSP32Alu_x_mask
);
3127 int aop
= ((iw1
>> DSP32Alu_aop_bits
) & DSP32Alu_aop_mask
);
3128 int src0
= ((iw1
>> DSP32Alu_src0_bits
) & DSP32Alu_src0_mask
);
3129 int src1
= ((iw1
>> DSP32Alu_src1_bits
) & DSP32Alu_src1_mask
);
3130 int dst0
= ((iw1
>> DSP32Alu_dst0_bits
) & DSP32Alu_dst0_mask
);
3131 int dst1
= ((iw1
>> DSP32Alu_dst1_bits
) & DSP32Alu_dst1_mask
);
3132 int HL
= ((iw0
>> (DSP32Alu_HL_bits
- 16)) & DSP32Alu_HL_mask
);
3133 int aopcde
= ((iw0
>> (DSP32Alu_aopcde_bits
- 16)) & DSP32Alu_aopcde_mask
);
3135 if (aop
== 0 && aopcde
== 9 && HL
== 0 && s
== 0)
3137 OUTS (outf
, "A0.L = ");
3138 OUTS (outf
, dregs_lo (src0
));
3140 else if (aop
== 2 && aopcde
== 9 && HL
== 1 && s
== 0)
3142 OUTS (outf
, "A1.H = ");
3143 OUTS (outf
, dregs_hi (src0
));
3145 else if (aop
== 2 && aopcde
== 9 && HL
== 0 && s
== 0)
3147 OUTS (outf
, "A1.L = ");
3148 OUTS (outf
, dregs_lo (src0
));
3150 else if (aop
== 0 && aopcde
== 9 && HL
== 1 && s
== 0)
3152 OUTS (outf
, "A0.H = ");
3153 OUTS (outf
, dregs_hi (src0
));
3155 else if (x
== 1 && HL
== 1 && aop
== 3 && aopcde
== 5)
3157 OUTS (outf
, dregs_hi (dst0
));
3159 OUTS (outf
, dregs (src0
));
3161 OUTS (outf
, dregs (src1
));
3162 OUTS (outf
, " (RND20)");
3164 else if (x
== 1 && HL
== 1 && aop
== 2 && aopcde
== 5)
3166 OUTS (outf
, dregs_hi (dst0
));
3168 OUTS (outf
, dregs (src0
));
3170 OUTS (outf
, dregs (src1
));
3171 OUTS (outf
, " (RND20)");
3173 else if (x
== 0 && HL
== 0 && aop
== 1 && aopcde
== 5)
3175 OUTS (outf
, dregs_lo (dst0
));
3177 OUTS (outf
, dregs (src0
));
3179 OUTS (outf
, dregs (src1
));
3180 OUTS (outf
, " (RND12)");
3182 else if (x
== 0 && HL
== 0 && aop
== 0 && aopcde
== 5)
3184 OUTS (outf
, dregs_lo (dst0
));
3186 OUTS (outf
, dregs (src0
));
3188 OUTS (outf
, dregs (src1
));
3189 OUTS (outf
, " (RND12)");
3191 else if (x
== 1 && HL
== 0 && aop
== 3 && aopcde
== 5)
3193 OUTS (outf
, dregs_lo (dst0
));
3195 OUTS (outf
, dregs (src0
));
3197 OUTS (outf
, dregs (src1
));
3198 OUTS (outf
, " (RND20)");
3200 else if (x
== 0 && HL
== 1 && aop
== 0 && aopcde
== 5)
3202 OUTS (outf
, dregs_hi (dst0
));
3204 OUTS (outf
, dregs (src0
));
3206 OUTS (outf
, dregs (src1
));
3207 OUTS (outf
, " (RND12)");
3209 else if (x
== 1 && HL
== 0 && aop
== 2 && aopcde
== 5)
3211 OUTS (outf
, dregs_lo (dst0
));
3213 OUTS (outf
, dregs (src0
));
3215 OUTS (outf
, dregs (src1
));
3216 OUTS (outf
, " (RND20)");
3218 else if (x
== 0 && HL
== 1 && aop
== 1 && aopcde
== 5)
3220 OUTS (outf
, dregs_hi (dst0
));
3222 OUTS (outf
, dregs (src0
));
3224 OUTS (outf
, dregs (src1
));
3225 OUTS (outf
, " (RND12)");
3227 else if (HL
== 1 && aop
== 0 && aopcde
== 2)
3229 OUTS (outf
, dregs_hi (dst0
));
3231 OUTS (outf
, dregs_lo (src0
));
3233 OUTS (outf
, dregs_lo (src1
));
3236 else if (HL
== 1 && aop
== 1 && aopcde
== 2)
3238 OUTS (outf
, dregs_hi (dst0
));
3240 OUTS (outf
, dregs_lo (src0
));
3242 OUTS (outf
, dregs_hi (src1
));
3245 else if (HL
== 1 && aop
== 2 && aopcde
== 2)
3247 OUTS (outf
, dregs_hi (dst0
));
3249 OUTS (outf
, dregs_hi (src0
));
3251 OUTS (outf
, dregs_lo (src1
));
3254 else if (HL
== 1 && aop
== 3 && aopcde
== 2)
3256 OUTS (outf
, dregs_hi (dst0
));
3258 OUTS (outf
, dregs_hi (src0
));
3260 OUTS (outf
, dregs_hi (src1
));
3263 else if (HL
== 0 && aop
== 0 && aopcde
== 3)
3265 OUTS (outf
, dregs_lo (dst0
));
3267 OUTS (outf
, dregs_lo (src0
));
3269 OUTS (outf
, dregs_lo (src1
));
3272 else if (HL
== 0 && aop
== 1 && aopcde
== 3)
3274 OUTS (outf
, dregs_lo (dst0
));
3276 OUTS (outf
, dregs_lo (src0
));
3278 OUTS (outf
, dregs_hi (src1
));
3281 else if (HL
== 0 && aop
== 3 && aopcde
== 2)
3283 OUTS (outf
, dregs_lo (dst0
));
3285 OUTS (outf
, dregs_hi (src0
));
3287 OUTS (outf
, dregs_hi (src1
));
3290 else if (HL
== 1 && aop
== 0 && aopcde
== 3)
3292 OUTS (outf
, dregs_hi (dst0
));
3294 OUTS (outf
, dregs_lo (src0
));
3296 OUTS (outf
, dregs_lo (src1
));
3299 else if (HL
== 1 && aop
== 1 && aopcde
== 3)
3301 OUTS (outf
, dregs_hi (dst0
));
3303 OUTS (outf
, dregs_lo (src0
));
3305 OUTS (outf
, dregs_hi (src1
));
3308 else if (HL
== 1 && aop
== 2 && aopcde
== 3)
3310 OUTS (outf
, dregs_hi (dst0
));
3312 OUTS (outf
, dregs_hi (src0
));
3314 OUTS (outf
, dregs_lo (src1
));
3317 else if (HL
== 1 && aop
== 3 && aopcde
== 3)
3319 OUTS (outf
, dregs_hi (dst0
));
3321 OUTS (outf
, dregs_hi (src0
));
3323 OUTS (outf
, dregs_hi (src1
));
3326 else if (HL
== 0 && aop
== 2 && aopcde
== 2)
3328 OUTS (outf
, dregs_lo (dst0
));
3330 OUTS (outf
, dregs_hi (src0
));
3332 OUTS (outf
, dregs_lo (src1
));
3335 else if (HL
== 0 && aop
== 1 && aopcde
== 2)
3337 OUTS (outf
, dregs_lo (dst0
));
3339 OUTS (outf
, dregs_lo (src0
));
3341 OUTS (outf
, dregs_hi (src1
));
3344 else if (HL
== 0 && aop
== 2 && aopcde
== 3)
3346 OUTS (outf
, dregs_lo (dst0
));
3348 OUTS (outf
, dregs_hi (src0
));
3350 OUTS (outf
, dregs_lo (src1
));
3353 else if (HL
== 0 && aop
== 3 && aopcde
== 3)
3355 OUTS (outf
, dregs_lo (dst0
));
3357 OUTS (outf
, dregs_hi (src0
));
3359 OUTS (outf
, dregs_hi (src1
));
3362 else if (HL
== 0 && aop
== 0 && aopcde
== 2)
3364 OUTS (outf
, dregs_lo (dst0
));
3366 OUTS (outf
, dregs_lo (src0
));
3368 OUTS (outf
, dregs_lo (src1
));
3371 else if (aop
== 0 && aopcde
== 9 && s
== 1)
3373 OUTS (outf
, "A0 = ");
3374 OUTS (outf
, dregs (src0
));
3376 else if (aop
== 3 && aopcde
== 11 && s
== 0)
3377 OUTS (outf
, "A0 -= A1");
3379 else if (aop
== 3 && aopcde
== 11 && s
== 1)
3380 OUTS (outf
, "A0 -= A1 (W32)");
3382 else if (aop
== 3 && aopcde
== 22 && HL
== 1)
3384 OUTS (outf
, dregs (dst0
));
3385 OUTS (outf
, " = BYTEOP2M (");
3386 OUTS (outf
, dregs (src0
+ 1));
3388 OUTS (outf
, imm5 (src0
));
3390 OUTS (outf
, dregs (src1
+ 1));
3392 OUTS (outf
, imm5 (src1
));
3393 OUTS (outf
, ") (TH");
3395 OUTS (outf
, ", R)");
3399 else if (aop
== 3 && aopcde
== 22 && HL
== 0)
3401 OUTS (outf
, dregs (dst0
));
3402 OUTS (outf
, " = BYTEOP2M (");
3403 OUTS (outf
, dregs (src0
+ 1));
3405 OUTS (outf
, imm5 (src0
));
3407 OUTS (outf
, dregs (src1
+ 1));
3409 OUTS (outf
, imm5 (src1
));
3410 OUTS (outf
, ") (TL");
3412 OUTS (outf
, ", R)");
3416 else if (aop
== 2 && aopcde
== 22 && HL
== 1)
3418 OUTS (outf
, dregs (dst0
));
3419 OUTS (outf
, " = BYTEOP2M (");
3420 OUTS (outf
, dregs (src0
+ 1));
3422 OUTS (outf
, imm5 (src0
));
3424 OUTS (outf
, dregs (src1
+ 1));
3426 OUTS (outf
, imm5 (src1
));
3427 OUTS (outf
, ") (RNDH");
3429 OUTS (outf
, ", R)");
3433 else if (aop
== 2 && aopcde
== 22 && HL
== 0)
3435 OUTS (outf
, dregs (dst0
));
3436 OUTS (outf
, " = BYTEOP2M (");
3437 OUTS (outf
, dregs (src0
+ 1));
3439 OUTS (outf
, imm5 (src0
));
3441 OUTS (outf
, dregs (src1
+ 1));
3443 OUTS (outf
, imm5 (src1
));
3444 OUTS (outf
, ") (RNDL");
3446 OUTS (outf
, ", R)");
3450 else if (aop
== 1 && aopcde
== 22 && HL
== 1)
3452 OUTS (outf
, dregs (dst0
));
3453 OUTS (outf
, " = BYTEOP2P (");
3454 OUTS (outf
, dregs (src0
+ 1));
3456 OUTS (outf
, imm5d (src0
));
3458 OUTS (outf
, dregs (src1
+ 1));
3460 OUTS (outf
, imm5d (src1
));
3461 OUTS (outf
, ") (TH");
3463 OUTS (outf
, ", R)");
3467 else if (aop
== 1 && aopcde
== 22 && HL
== 0)
3469 OUTS (outf
, dregs (dst0
));
3470 OUTS (outf
, " = BYTEOP2P (");
3471 OUTS (outf
, dregs (src0
+ 1));
3473 OUTS (outf
, imm5d (src0
));
3475 OUTS (outf
, dregs (src1
+ 1));
3477 OUTS (outf
, imm5d (src1
));
3478 OUTS (outf
, ") (TL");
3480 OUTS (outf
, ", R)");
3484 else if (aop
== 0 && aopcde
== 22 && HL
== 1)
3486 OUTS (outf
, dregs (dst0
));
3487 OUTS (outf
, " = BYTEOP2P (");
3488 OUTS (outf
, dregs (src0
+ 1));
3490 OUTS (outf
, imm5d (src0
));
3492 OUTS (outf
, dregs (src1
+ 1));
3494 OUTS (outf
, imm5d (src1
));
3495 OUTS (outf
, ") (RNDH");
3497 OUTS (outf
, ", R)");
3501 else if (aop
== 0 && aopcde
== 22 && HL
== 0)
3503 OUTS (outf
, dregs (dst0
));
3504 OUTS (outf
, " = BYTEOP2P (");
3505 OUTS (outf
, dregs (src0
+ 1));
3507 OUTS (outf
, imm5d (src0
));
3509 OUTS (outf
, dregs (src1
+ 1));
3511 OUTS (outf
, imm5d (src1
));
3512 OUTS (outf
, ") (RNDL");
3514 OUTS (outf
, ", R)");
3518 else if (aop
== 0 && s
== 0 && aopcde
== 8)
3519 OUTS (outf
, "A0 = 0");
3521 else if (aop
== 0 && s
== 1 && aopcde
== 8)
3522 OUTS (outf
, "A0 = A0 (S)");
3524 else if (aop
== 1 && s
== 0 && aopcde
== 8)
3525 OUTS (outf
, "A1 = 0");
3527 else if (aop
== 1 && s
== 1 && aopcde
== 8)
3528 OUTS (outf
, "A1 = A1 (S)");
3530 else if (aop
== 2 && s
== 0 && aopcde
== 8)
3531 OUTS (outf
, "A1 = A0 = 0");
3533 else if (aop
== 2 && s
== 1 && aopcde
== 8)
3534 OUTS (outf
, "A1 = A1 (S), A0 = A0 (S)");
3536 else if (aop
== 3 && s
== 0 && aopcde
== 8)
3537 OUTS (outf
, "A0 = A1");
3539 else if (aop
== 3 && s
== 1 && aopcde
== 8)
3540 OUTS (outf
, "A1 = A0");
3542 else if (aop
== 1 && aopcde
== 9 && s
== 0)
3544 OUTS (outf
, "A0.X = ");
3545 OUTS (outf
, dregs_lo (src0
));
3547 else if (aop
== 1 && HL
== 0 && aopcde
== 11)
3549 OUTS (outf
, dregs_lo (dst0
));
3550 OUTS (outf
, " = (A0 += A1)");
3552 else if (aop
== 3 && HL
== 0 && aopcde
== 16)
3553 OUTS (outf
, "A1 = ABS A0, A0 = ABS A0");
3555 else if (aop
== 0 && aopcde
== 23 && HL
== 1)
3557 OUTS (outf
, dregs (dst0
));
3558 OUTS (outf
, " = BYTEOP3P (");
3559 OUTS (outf
, dregs (src0
+ 1));
3561 OUTS (outf
, imm5d (src0
));
3563 OUTS (outf
, dregs (src1
+ 1));
3565 OUTS (outf
, imm5d (src1
));
3566 OUTS (outf
, ") (HI");
3568 OUTS (outf
, ", R)");
3572 else if (aop
== 3 && aopcde
== 9 && s
== 0)
3574 OUTS (outf
, "A1.X = ");
3575 OUTS (outf
, dregs_lo (src0
));
3577 else if (aop
== 1 && HL
== 1 && aopcde
== 16)
3578 OUTS (outf
, "A1 = ABS A1");
3580 else if (aop
== 0 && HL
== 1 && aopcde
== 16)
3581 OUTS (outf
, "A1 = ABS A0");
3583 else if (aop
== 2 && aopcde
== 9 && s
== 1)
3585 OUTS (outf
, "A1 = ");
3586 OUTS (outf
, dregs (src0
));
3588 else if (HL
== 0 && aop
== 3 && aopcde
== 12)
3590 OUTS (outf
, dregs_lo (dst0
));
3592 OUTS (outf
, dregs (src0
));
3593 OUTS (outf
, " (RND)");
3595 else if (aop
== 1 && HL
== 0 && aopcde
== 16)
3596 OUTS (outf
, "A0 = ABS A1");
3598 else if (aop
== 0 && HL
== 0 && aopcde
== 16)
3599 OUTS (outf
, "A0 = ABS A0");
3601 else if (aop
== 3 && HL
== 0 && aopcde
== 15)
3603 OUTS (outf
, dregs (dst0
));
3604 OUTS (outf
, " = -");
3605 OUTS (outf
, dregs (src0
));
3606 OUTS (outf
, " (V)");
3608 else if (aop
== 3 && s
== 1 && HL
== 0 && aopcde
== 7)
3610 OUTS (outf
, dregs (dst0
));
3611 OUTS (outf
, " = -");
3612 OUTS (outf
, dregs (src0
));
3613 OUTS (outf
, " (S)");
3615 else if (aop
== 3 && s
== 0 && HL
== 0 && aopcde
== 7)
3617 OUTS (outf
, dregs (dst0
));
3618 OUTS (outf
, " = -");
3619 OUTS (outf
, dregs (src0
));
3620 OUTS (outf
, " (NS)");
3622 else if (aop
== 1 && HL
== 1 && aopcde
== 11)
3624 OUTS (outf
, dregs_hi (dst0
));
3625 OUTS (outf
, " = (A0 += A1)");
3627 else if (aop
== 2 && aopcde
== 11 && s
== 0)
3628 OUTS (outf
, "A0 += A1");
3630 else if (aop
== 2 && aopcde
== 11 && s
== 1)
3631 OUTS (outf
, "A0 += A1 (W32)");
3633 else if (aop
== 3 && HL
== 0 && aopcde
== 14)
3634 OUTS (outf
, "A1 = -A1, A0 = -A0");
3636 else if (HL
== 1 && aop
== 3 && aopcde
== 12)
3638 OUTS (outf
, dregs_hi (dst0
));
3640 OUTS (outf
, dregs (src0
));
3641 OUTS (outf
, " (RND)");
3643 else if (aop
== 0 && aopcde
== 23 && HL
== 0)
3645 OUTS (outf
, dregs (dst0
));
3646 OUTS (outf
, " = BYTEOP3P (");
3647 OUTS (outf
, dregs (src0
+ 1));
3649 OUTS (outf
, imm5d (src0
));
3651 OUTS (outf
, dregs (src1
+ 1));
3653 OUTS (outf
, imm5d (src1
));
3654 OUTS (outf
, ") (LO");
3656 OUTS (outf
, ", R)");
3660 else if (aop
== 0 && HL
== 0 && aopcde
== 14)
3661 OUTS (outf
, "A0 = -A0");
3663 else if (aop
== 1 && HL
== 0 && aopcde
== 14)
3664 OUTS (outf
, "A0 = -A1");
3666 else if (aop
== 0 && HL
== 1 && aopcde
== 14)
3667 OUTS (outf
, "A1 = -A0");
3669 else if (aop
== 1 && HL
== 1 && aopcde
== 14)
3670 OUTS (outf
, "A1 = -A1");
3672 else if (aop
== 0 && aopcde
== 12)
3674 OUTS (outf
, dregs_hi (dst0
));
3676 OUTS (outf
, dregs_lo (dst0
));
3677 OUTS (outf
, " = SIGN (");
3678 OUTS (outf
, dregs_hi (src0
));
3679 OUTS (outf
, ") * ");
3680 OUTS (outf
, dregs_hi (src1
));
3681 OUTS (outf
, " + SIGN (");
3682 OUTS (outf
, dregs_lo (src0
));
3683 OUTS (outf
, ") * ");
3684 OUTS (outf
, dregs_lo (src1
));
3686 else if (aop
== 2 && aopcde
== 0)
3688 OUTS (outf
, dregs (dst0
));
3690 OUTS (outf
, dregs (src0
));
3691 OUTS (outf
, " -|+ ");
3692 OUTS (outf
, dregs (src1
));
3695 else if (aop
== 1 && aopcde
== 12)
3697 OUTS (outf
, dregs (dst1
));
3698 OUTS (outf
, " = A1.L + A1.H, ");
3699 OUTS (outf
, dregs (dst0
));
3700 OUTS (outf
, " = A0.L + A0.H");
3702 else if (aop
== 2 && aopcde
== 4)
3704 OUTS (outf
, dregs (dst1
));
3706 OUTS (outf
, dregs (src0
));
3708 OUTS (outf
, dregs (src1
));
3710 OUTS (outf
, dregs (dst0
));
3712 OUTS (outf
, dregs (src0
));
3714 OUTS (outf
, dregs (src1
));
3717 else if (HL
== 0 && aopcde
== 1)
3719 OUTS (outf
, dregs (dst1
));
3721 OUTS (outf
, dregs (src0
));
3722 OUTS (outf
, " +|+ ");
3723 OUTS (outf
, dregs (src1
));
3725 OUTS (outf
, dregs (dst0
));
3727 OUTS (outf
, dregs (src0
));
3728 OUTS (outf
, " -|- ");
3729 OUTS (outf
, dregs (src1
));
3730 amod0amod2 (s
, x
, aop
, outf
);
3732 else if (aop
== 0 && aopcde
== 11)
3734 OUTS (outf
, dregs (dst0
));
3735 OUTS (outf
, " = (A0 += A1)");
3737 else if (aop
== 0 && aopcde
== 10)
3739 OUTS (outf
, dregs_lo (dst0
));
3740 OUTS (outf
, " = A0.X");
3742 else if (aop
== 1 && aopcde
== 10)
3744 OUTS (outf
, dregs_lo (dst0
));
3745 OUTS (outf
, " = A1.X");
3747 else if (aop
== 1 && aopcde
== 0)
3749 OUTS (outf
, dregs (dst0
));
3751 OUTS (outf
, dregs (src0
));
3752 OUTS (outf
, " +|- ");
3753 OUTS (outf
, dregs (src1
));
3756 else if (aop
== 3 && aopcde
== 0)
3758 OUTS (outf
, dregs (dst0
));
3760 OUTS (outf
, dregs (src0
));
3761 OUTS (outf
, " -|- ");
3762 OUTS (outf
, dregs (src1
));
3765 else if (aop
== 1 && aopcde
== 4)
3767 OUTS (outf
, dregs (dst0
));
3769 OUTS (outf
, dregs (src0
));
3771 OUTS (outf
, dregs (src1
));
3774 else if (aop
== 0 && aopcde
== 17)
3776 OUTS (outf
, dregs (dst1
));
3777 OUTS (outf
, " = A1 + A0, ");
3778 OUTS (outf
, dregs (dst0
));
3779 OUTS (outf
, " = A1 - A0");
3782 else if (aop
== 1 && aopcde
== 17)
3784 OUTS (outf
, dregs (dst1
));
3785 OUTS (outf
, " = A0 + A1, ");
3786 OUTS (outf
, dregs (dst0
));
3787 OUTS (outf
, " = A0 - A1");
3790 else if (aop
== 0 && aopcde
== 18)
3792 OUTS (outf
, "SAA (");
3793 OUTS (outf
, dregs (src0
+ 1));
3795 OUTS (outf
, imm5d (src0
));
3797 OUTS (outf
, dregs (src1
+ 1));
3799 OUTS (outf
, imm5d (src1
));
3803 else if (aop
== 3 && aopcde
== 18)
3804 OUTS (outf
, "DISALGNEXCPT");
3806 else if (aop
== 0 && aopcde
== 20)
3808 OUTS (outf
, dregs (dst0
));
3809 OUTS (outf
, " = BYTEOP1P (");
3810 OUTS (outf
, dregs (src0
+ 1));
3812 OUTS (outf
, imm5d (src0
));
3814 OUTS (outf
, dregs (src1
+ 1));
3816 OUTS (outf
, imm5d (src1
));
3820 else if (aop
== 1 && aopcde
== 20)
3822 OUTS (outf
, dregs (dst0
));
3823 OUTS (outf
, " = BYTEOP1P (");
3824 OUTS (outf
, dregs (src0
+ 1));
3826 OUTS (outf
, imm5d (src0
));
3828 OUTS (outf
, dregs (src1
+ 1));
3830 OUTS (outf
, imm5d (src1
));
3831 OUTS (outf
, ") (T");
3833 OUTS (outf
, ", R)");
3837 else if (aop
== 0 && aopcde
== 21)
3840 OUTS (outf
, dregs (dst1
));
3842 OUTS (outf
, dregs (dst0
));
3843 OUTS (outf
, ") = BYTEOP16P (");
3844 OUTS (outf
, dregs (src0
+ 1));
3846 OUTS (outf
, imm5d (src0
));
3848 OUTS (outf
, dregs (src1
+ 1));
3850 OUTS (outf
, imm5d (src1
));
3854 else if (aop
== 1 && aopcde
== 21)
3857 OUTS (outf
, dregs (dst1
));
3859 OUTS (outf
, dregs (dst0
));
3860 OUTS (outf
, ") = BYTEOP16M (");
3861 OUTS (outf
, dregs (src0
+ 1));
3863 OUTS (outf
, imm5d (src0
));
3865 OUTS (outf
, dregs (src1
+ 1));
3867 OUTS (outf
, imm5d (src1
));
3871 else if (aop
== 2 && aopcde
== 7)
3873 OUTS (outf
, dregs (dst0
));
3874 OUTS (outf
, " = ABS ");
3875 OUTS (outf
, dregs (src0
));
3877 else if (aop
== 1 && aopcde
== 7)
3879 OUTS (outf
, dregs (dst0
));
3880 OUTS (outf
, " = MIN (");
3881 OUTS (outf
, dregs (src0
));
3883 OUTS (outf
, dregs (src1
));
3886 else if (aop
== 0 && aopcde
== 7)
3888 OUTS (outf
, dregs (dst0
));
3889 OUTS (outf
, " = MAX (");
3890 OUTS (outf
, dregs (src0
));
3892 OUTS (outf
, dregs (src1
));
3895 else if (aop
== 2 && aopcde
== 6)
3897 OUTS (outf
, dregs (dst0
));
3898 OUTS (outf
, " = ABS ");
3899 OUTS (outf
, dregs (src0
));
3900 OUTS (outf
, " (V)");
3902 else if (aop
== 1 && aopcde
== 6)
3904 OUTS (outf
, dregs (dst0
));
3905 OUTS (outf
, " = MIN (");
3906 OUTS (outf
, dregs (src0
));
3908 OUTS (outf
, dregs (src1
));
3909 OUTS (outf
, ") (V)");
3911 else if (aop
== 0 && aopcde
== 6)
3913 OUTS (outf
, dregs (dst0
));
3914 OUTS (outf
, " = MAX (");
3915 OUTS (outf
, dregs (src0
));
3917 OUTS (outf
, dregs (src1
));
3918 OUTS (outf
, ") (V)");
3920 else if (HL
== 1 && aopcde
== 1)
3922 OUTS (outf
, dregs (dst1
));
3924 OUTS (outf
, dregs (src0
));
3925 OUTS (outf
, " +|- ");
3926 OUTS (outf
, dregs (src1
));
3928 OUTS (outf
, dregs (dst0
));
3930 OUTS (outf
, dregs (src0
));
3931 OUTS (outf
, " -|+ ");
3932 OUTS (outf
, dregs (src1
));
3933 amod0amod2 (s
, x
, aop
, outf
);
3935 else if (aop
== 0 && aopcde
== 4)
3937 OUTS (outf
, dregs (dst0
));
3939 OUTS (outf
, dregs (src0
));
3941 OUTS (outf
, dregs (src1
));
3944 else if (aop
== 0 && aopcde
== 0)
3946 OUTS (outf
, dregs (dst0
));
3948 OUTS (outf
, dregs (src0
));
3949 OUTS (outf
, " +|+ ");
3950 OUTS (outf
, dregs (src1
));
3953 else if (aop
== 0 && aopcde
== 24)
3955 OUTS (outf
, dregs (dst0
));
3956 OUTS (outf
, " = BYTEPACK (");
3957 OUTS (outf
, dregs (src0
));
3959 OUTS (outf
, dregs (src1
));
3962 else if (aop
== 1 && aopcde
== 24)
3965 OUTS (outf
, dregs (dst1
));
3967 OUTS (outf
, dregs (dst0
));
3968 OUTS (outf
, ") = BYTEUNPACK ");
3969 OUTS (outf
, dregs (src0
+ 1));
3971 OUTS (outf
, imm5d (src0
));
3974 else if (aopcde
== 13)
3977 OUTS (outf
, dregs (dst1
));
3979 OUTS (outf
, dregs (dst0
));
3980 OUTS (outf
, ") = SEARCH ");
3981 OUTS (outf
, dregs (src0
));
3983 searchmod (aop
, outf
);
3993 decode_dsp32shift_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
3996 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3997 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3998 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3999 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4000 int HLs
= ((iw1
>> DSP32Shift_HLs_bits
) & DSP32Shift_HLs_mask
);
4001 int sop
= ((iw1
>> DSP32Shift_sop_bits
) & DSP32Shift_sop_mask
);
4002 int src0
= ((iw1
>> DSP32Shift_src0_bits
) & DSP32Shift_src0_mask
);
4003 int src1
= ((iw1
>> DSP32Shift_src1_bits
) & DSP32Shift_src1_mask
);
4004 int dst0
= ((iw1
>> DSP32Shift_dst0_bits
) & DSP32Shift_dst0_mask
);
4005 int sopcde
= ((iw0
>> (DSP32Shift_sopcde_bits
- 16)) & DSP32Shift_sopcde_mask
);
4006 const char *acc01
= (HLs
& 1) == 0 ? "A0" : "A1";
4008 if (HLs
== 0 && sop
== 0 && sopcde
== 0)
4010 OUTS (outf
, dregs_lo (dst0
));
4011 OUTS (outf
, " = ASHIFT ");
4012 OUTS (outf
, dregs_lo (src1
));
4013 OUTS (outf
, " BY ");
4014 OUTS (outf
, dregs_lo (src0
));
4016 else if (HLs
== 1 && sop
== 0 && sopcde
== 0)
4018 OUTS (outf
, dregs_lo (dst0
));
4019 OUTS (outf
, " = ASHIFT ");
4020 OUTS (outf
, dregs_hi (src1
));
4021 OUTS (outf
, " BY ");
4022 OUTS (outf
, dregs_lo (src0
));
4024 else if (HLs
== 2 && sop
== 0 && sopcde
== 0)
4026 OUTS (outf
, dregs_hi (dst0
));
4027 OUTS (outf
, " = ASHIFT ");
4028 OUTS (outf
, dregs_lo (src1
));
4029 OUTS (outf
, " BY ");
4030 OUTS (outf
, dregs_lo (src0
));
4032 else if (HLs
== 3 && sop
== 0 && sopcde
== 0)
4034 OUTS (outf
, dregs_hi (dst0
));
4035 OUTS (outf
, " = ASHIFT ");
4036 OUTS (outf
, dregs_hi (src1
));
4037 OUTS (outf
, " BY ");
4038 OUTS (outf
, dregs_lo (src0
));
4040 else if (HLs
== 0 && sop
== 1 && sopcde
== 0)
4042 OUTS (outf
, dregs_lo (dst0
));
4043 OUTS (outf
, " = ASHIFT ");
4044 OUTS (outf
, dregs_lo (src1
));
4045 OUTS (outf
, " BY ");
4046 OUTS (outf
, dregs_lo (src0
));
4047 OUTS (outf
, " (S)");
4049 else if (HLs
== 1 && sop
== 1 && sopcde
== 0)
4051 OUTS (outf
, dregs_lo (dst0
));
4052 OUTS (outf
, " = ASHIFT ");
4053 OUTS (outf
, dregs_hi (src1
));
4054 OUTS (outf
, " BY ");
4055 OUTS (outf
, dregs_lo (src0
));
4056 OUTS (outf
, " (S)");
4058 else if (HLs
== 2 && sop
== 1 && sopcde
== 0)
4060 OUTS (outf
, dregs_hi (dst0
));
4061 OUTS (outf
, " = ASHIFT ");
4062 OUTS (outf
, dregs_lo (src1
));
4063 OUTS (outf
, " BY ");
4064 OUTS (outf
, dregs_lo (src0
));
4065 OUTS (outf
, " (S)");
4067 else if (HLs
== 3 && sop
== 1 && sopcde
== 0)
4069 OUTS (outf
, dregs_hi (dst0
));
4070 OUTS (outf
, " = ASHIFT ");
4071 OUTS (outf
, dregs_hi (src1
));
4072 OUTS (outf
, " BY ");
4073 OUTS (outf
, dregs_lo (src0
));
4074 OUTS (outf
, " (S)");
4076 else if (sop
== 2 && sopcde
== 0)
4078 OUTS (outf
, (HLs
& 2) == 0 ? dregs_lo (dst0
) : dregs_hi (dst0
));
4079 OUTS (outf
, " = LSHIFT ");
4080 OUTS (outf
, (HLs
& 1) == 0 ? dregs_lo (src1
) : dregs_hi (src1
));
4081 OUTS (outf
, " BY ");
4082 OUTS (outf
, dregs_lo (src0
));
4084 else if (sop
== 0 && sopcde
== 3)
4087 OUTS (outf
, " = ASHIFT ");
4089 OUTS (outf
, " BY ");
4090 OUTS (outf
, dregs_lo (src0
));
4092 else if (sop
== 1 && sopcde
== 3)
4095 OUTS (outf
, " = LSHIFT ");
4097 OUTS (outf
, " BY ");
4098 OUTS (outf
, dregs_lo (src0
));
4100 else if (sop
== 2 && sopcde
== 3)
4103 OUTS (outf
, " = ROT ");
4105 OUTS (outf
, " BY ");
4106 OUTS (outf
, dregs_lo (src0
));
4108 else if (sop
== 3 && sopcde
== 3)
4110 OUTS (outf
, dregs (dst0
));
4111 OUTS (outf
, " = ROT ");
4112 OUTS (outf
, dregs (src1
));
4113 OUTS (outf
, " BY ");
4114 OUTS (outf
, dregs_lo (src0
));
4116 else if (sop
== 1 && sopcde
== 1)
4118 OUTS (outf
, dregs (dst0
));
4119 OUTS (outf
, " = ASHIFT ");
4120 OUTS (outf
, dregs (src1
));
4121 OUTS (outf
, " BY ");
4122 OUTS (outf
, dregs_lo (src0
));
4123 OUTS (outf
, " (V, S)");
4125 else if (sop
== 0 && sopcde
== 1)
4127 OUTS (outf
, dregs (dst0
));
4128 OUTS (outf
, " = ASHIFT ");
4129 OUTS (outf
, dregs (src1
));
4130 OUTS (outf
, " BY ");
4131 OUTS (outf
, dregs_lo (src0
));
4132 OUTS (outf
, " (V)");
4134 else if (sop
== 0 && sopcde
== 2)
4136 OUTS (outf
, dregs (dst0
));
4137 OUTS (outf
, " = ASHIFT ");
4138 OUTS (outf
, dregs (src1
));
4139 OUTS (outf
, " BY ");
4140 OUTS (outf
, dregs_lo (src0
));
4142 else if (sop
== 1 && sopcde
== 2)
4144 OUTS (outf
, dregs (dst0
));
4145 OUTS (outf
, " = ASHIFT ");
4146 OUTS (outf
, dregs (src1
));
4147 OUTS (outf
, " BY ");
4148 OUTS (outf
, dregs_lo (src0
));
4149 OUTS (outf
, " (S)");
4151 else if (sop
== 2 && sopcde
== 2)
4153 OUTS (outf
, dregs (dst0
));
4154 OUTS (outf
, " = LSHIFT ");
4155 OUTS (outf
, dregs (src1
));
4156 OUTS (outf
, " BY ");
4157 OUTS (outf
, dregs_lo (src0
));
4159 else if (sop
== 3 && sopcde
== 2)
4161 OUTS (outf
, dregs (dst0
));
4162 OUTS (outf
, " = ROT ");
4163 OUTS (outf
, dregs (src1
));
4164 OUTS (outf
, " BY ");
4165 OUTS (outf
, dregs_lo (src0
));
4167 else if (sop
== 2 && sopcde
== 1)
4169 OUTS (outf
, dregs (dst0
));
4170 OUTS (outf
, " = LSHIFT ");
4171 OUTS (outf
, dregs (src1
));
4172 OUTS (outf
, " BY ");
4173 OUTS (outf
, dregs_lo (src0
));
4174 OUTS (outf
, " (V)");
4176 else if (sop
== 0 && sopcde
== 4)
4178 OUTS (outf
, dregs (dst0
));
4179 OUTS (outf
, " = PACK (");
4180 OUTS (outf
, dregs_lo (src1
));
4182 OUTS (outf
, dregs_lo (src0
));
4185 else if (sop
== 1 && sopcde
== 4)
4187 OUTS (outf
, dregs (dst0
));
4188 OUTS (outf
, " = PACK (");
4189 OUTS (outf
, dregs_lo (src1
));
4191 OUTS (outf
, dregs_hi (src0
));
4194 else if (sop
== 2 && sopcde
== 4)
4196 OUTS (outf
, dregs (dst0
));
4197 OUTS (outf
, " = PACK (");
4198 OUTS (outf
, dregs_hi (src1
));
4200 OUTS (outf
, dregs_lo (src0
));
4203 else if (sop
== 3 && sopcde
== 4)
4205 OUTS (outf
, dregs (dst0
));
4206 OUTS (outf
, " = PACK (");
4207 OUTS (outf
, dregs_hi (src1
));
4209 OUTS (outf
, dregs_hi (src0
));
4212 else if (sop
== 0 && sopcde
== 5)
4214 OUTS (outf
, dregs_lo (dst0
));
4215 OUTS (outf
, " = SIGNBITS ");
4216 OUTS (outf
, dregs (src1
));
4218 else if (sop
== 1 && sopcde
== 5)
4220 OUTS (outf
, dregs_lo (dst0
));
4221 OUTS (outf
, " = SIGNBITS ");
4222 OUTS (outf
, dregs_lo (src1
));
4224 else if (sop
== 2 && sopcde
== 5)
4226 OUTS (outf
, dregs_lo (dst0
));
4227 OUTS (outf
, " = SIGNBITS ");
4228 OUTS (outf
, dregs_hi (src1
));
4230 else if (sop
== 0 && sopcde
== 6)
4232 OUTS (outf
, dregs_lo (dst0
));
4233 OUTS (outf
, " = SIGNBITS A0");
4235 else if (sop
== 1 && sopcde
== 6)
4237 OUTS (outf
, dregs_lo (dst0
));
4238 OUTS (outf
, " = SIGNBITS A1");
4240 else if (sop
== 3 && sopcde
== 6)
4242 OUTS (outf
, dregs_lo (dst0
));
4243 OUTS (outf
, " = ONES ");
4244 OUTS (outf
, dregs (src1
));
4246 else if (sop
== 0 && sopcde
== 7)
4248 OUTS (outf
, dregs_lo (dst0
));
4249 OUTS (outf
, " = EXPADJ (");
4250 OUTS (outf
, dregs (src1
));
4252 OUTS (outf
, dregs_lo (src0
));
4255 else if (sop
== 1 && sopcde
== 7)
4257 OUTS (outf
, dregs_lo (dst0
));
4258 OUTS (outf
, " = EXPADJ (");
4259 OUTS (outf
, dregs (src1
));
4261 OUTS (outf
, dregs_lo (src0
));
4262 OUTS (outf
, ") (V)");
4264 else if (sop
== 2 && sopcde
== 7)
4266 OUTS (outf
, dregs_lo (dst0
));
4267 OUTS (outf
, " = EXPADJ (");
4268 OUTS (outf
, dregs_lo (src1
));
4270 OUTS (outf
, dregs_lo (src0
));
4273 else if (sop
== 3 && sopcde
== 7)
4275 OUTS (outf
, dregs_lo (dst0
));
4276 OUTS (outf
, " = EXPADJ (");
4277 OUTS (outf
, dregs_hi (src1
));
4279 OUTS (outf
, dregs_lo (src0
));
4282 else if (sop
== 0 && sopcde
== 8)
4284 OUTS (outf
, "BITMUX (");
4285 OUTS (outf
, dregs (src0
));
4287 OUTS (outf
, dregs (src1
));
4288 OUTS (outf
, ", A0) (ASR)");
4290 else if (sop
== 1 && sopcde
== 8)
4292 OUTS (outf
, "BITMUX (");
4293 OUTS (outf
, dregs (src0
));
4295 OUTS (outf
, dregs (src1
));
4296 OUTS (outf
, ", A0) (ASL)");
4298 else if (sop
== 0 && sopcde
== 9)
4300 OUTS (outf
, dregs_lo (dst0
));
4301 OUTS (outf
, " = VIT_MAX (");
4302 OUTS (outf
, dregs (src1
));
4303 OUTS (outf
, ") (ASL)");
4305 else if (sop
== 1 && sopcde
== 9)
4307 OUTS (outf
, dregs_lo (dst0
));
4308 OUTS (outf
, " = VIT_MAX (");
4309 OUTS (outf
, dregs (src1
));
4310 OUTS (outf
, ") (ASR)");
4312 else if (sop
== 2 && sopcde
== 9)
4314 OUTS (outf
, dregs (dst0
));
4315 OUTS (outf
, " = VIT_MAX (");
4316 OUTS (outf
, dregs (src1
));
4318 OUTS (outf
, dregs (src0
));
4319 OUTS (outf
, ") (ASL)");
4321 else if (sop
== 3 && sopcde
== 9)
4323 OUTS (outf
, dregs (dst0
));
4324 OUTS (outf
, " = VIT_MAX (");
4325 OUTS (outf
, dregs (src1
));
4327 OUTS (outf
, dregs (src0
));
4328 OUTS (outf
, ") (ASR)");
4330 else if (sop
== 0 && sopcde
== 10)
4332 OUTS (outf
, dregs (dst0
));
4333 OUTS (outf
, " = EXTRACT (");
4334 OUTS (outf
, dregs (src1
));
4336 OUTS (outf
, dregs_lo (src0
));
4337 OUTS (outf
, ") (Z)");
4339 else if (sop
== 1 && sopcde
== 10)
4341 OUTS (outf
, dregs (dst0
));
4342 OUTS (outf
, " = EXTRACT (");
4343 OUTS (outf
, dregs (src1
));
4345 OUTS (outf
, dregs_lo (src0
));
4346 OUTS (outf
, ") (X)");
4348 else if (sop
== 2 && sopcde
== 10)
4350 OUTS (outf
, dregs (dst0
));
4351 OUTS (outf
, " = DEPOSIT (");
4352 OUTS (outf
, dregs (src1
));
4354 OUTS (outf
, dregs (src0
));
4357 else if (sop
== 3 && sopcde
== 10)
4359 OUTS (outf
, dregs (dst0
));
4360 OUTS (outf
, " = DEPOSIT (");
4361 OUTS (outf
, dregs (src1
));
4363 OUTS (outf
, dregs (src0
));
4364 OUTS (outf
, ") (X)");
4366 else if (sop
== 0 && sopcde
== 11)
4368 OUTS (outf
, dregs_lo (dst0
));
4369 OUTS (outf
, " = CC = BXORSHIFT (A0, ");
4370 OUTS (outf
, dregs (src0
));
4373 else if (sop
== 1 && sopcde
== 11)
4375 OUTS (outf
, dregs_lo (dst0
));
4376 OUTS (outf
, " = CC = BXOR (A0, ");
4377 OUTS (outf
, dregs (src0
));
4380 else if (sop
== 0 && sopcde
== 12)
4381 OUTS (outf
, "A0 = BXORSHIFT (A0, A1, CC)");
4383 else if (sop
== 1 && sopcde
== 12)
4385 OUTS (outf
, dregs_lo (dst0
));
4386 OUTS (outf
, " = CC = BXOR (A0, A1, CC)");
4388 else if (sop
== 0 && sopcde
== 13)
4390 OUTS (outf
, dregs (dst0
));
4391 OUTS (outf
, " = ALIGN8 (");
4392 OUTS (outf
, dregs (src1
));
4394 OUTS (outf
, dregs (src0
));
4397 else if (sop
== 1 && sopcde
== 13)
4399 OUTS (outf
, dregs (dst0
));
4400 OUTS (outf
, " = ALIGN16 (");
4401 OUTS (outf
, dregs (src1
));
4403 OUTS (outf
, dregs (src0
));
4406 else if (sop
== 2 && sopcde
== 13)
4408 OUTS (outf
, dregs (dst0
));
4409 OUTS (outf
, " = ALIGN24 (");
4410 OUTS (outf
, dregs (src1
));
4412 OUTS (outf
, dregs (src0
));
4422 decode_dsp32shiftimm_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
4425 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4426 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4427 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4428 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4429 int src1
= ((iw1
>> DSP32ShiftImm_src1_bits
) & DSP32ShiftImm_src1_mask
);
4430 int sop
= ((iw1
>> DSP32ShiftImm_sop_bits
) & DSP32ShiftImm_sop_mask
);
4431 int bit8
= ((iw1
>> 8) & 0x1);
4432 int immag
= ((iw1
>> DSP32ShiftImm_immag_bits
) & DSP32ShiftImm_immag_mask
);
4433 int newimmag
= (-(iw1
>> DSP32ShiftImm_immag_bits
) & DSP32ShiftImm_immag_mask
);
4434 int dst0
= ((iw1
>> DSP32ShiftImm_dst0_bits
) & DSP32ShiftImm_dst0_mask
);
4435 int sopcde
= ((iw0
>> (DSP32ShiftImm_sopcde_bits
- 16)) & DSP32ShiftImm_sopcde_mask
);
4436 int HLs
= ((iw1
>> DSP32ShiftImm_HLs_bits
) & DSP32ShiftImm_HLs_mask
);
4439 if (sop
== 0 && sopcde
== 0)
4441 OUTS (outf
, (HLs
& 2) ? dregs_hi (dst0
) : dregs_lo (dst0
));
4443 OUTS (outf
, (HLs
& 1) ? dregs_hi (src1
) : dregs_lo (src1
));
4444 OUTS (outf
, " >>> ");
4445 OUTS (outf
, uimm4 (newimmag
));
4447 else if (sop
== 1 && sopcde
== 0 && bit8
== 0)
4449 OUTS (outf
, (HLs
& 2) ? dregs_hi (dst0
) : dregs_lo (dst0
));
4451 OUTS (outf
, (HLs
& 1) ? dregs_hi (src1
) : dregs_lo (src1
));
4452 OUTS (outf
, " << ");
4453 OUTS (outf
, uimm4 (immag
));
4454 OUTS (outf
, " (S)");
4456 else if (sop
== 1 && sopcde
== 0 && bit8
== 1)
4458 OUTS (outf
, (HLs
& 2) ? dregs_hi (dst0
) : dregs_lo (dst0
));
4460 OUTS (outf
, (HLs
& 1) ? dregs_hi (src1
) : dregs_lo (src1
));
4461 OUTS (outf
, " >>> ");
4462 OUTS (outf
, uimm4 (newimmag
));
4463 OUTS (outf
, " (S)");
4465 else if (sop
== 2 && sopcde
== 0 && bit8
== 0)
4467 OUTS (outf
, (HLs
& 2) ? dregs_hi (dst0
) : dregs_lo (dst0
));
4469 OUTS (outf
, (HLs
& 1) ? dregs_hi (src1
) : dregs_lo (src1
));
4470 OUTS (outf
, " << ");
4471 OUTS (outf
, uimm4 (immag
));
4473 else if (sop
== 2 && sopcde
== 0 && bit8
== 1)
4475 OUTS (outf
, (HLs
& 2) ? dregs_hi (dst0
) : dregs_lo (dst0
));
4477 OUTS (outf
, (HLs
& 1) ? dregs_hi (src1
) : dregs_lo (src1
));
4478 OUTS (outf
, " >> ");
4479 OUTS (outf
, uimm4 (newimmag
));
4481 else if (sop
== 2 && sopcde
== 3 && HLs
== 1)
4483 OUTS (outf
, "A1 = ROT A1 BY ");
4484 OUTS (outf
, imm6 (immag
));
4486 else if (sop
== 0 && sopcde
== 3 && HLs
== 0 && bit8
== 0)
4488 OUTS (outf
, "A0 = A0 << ");
4489 OUTS (outf
, uimm5 (immag
));
4491 else if (sop
== 0 && sopcde
== 3 && HLs
== 0 && bit8
== 1)
4493 OUTS (outf
, "A0 = A0 >>> ");
4494 OUTS (outf
, uimm5 (newimmag
));
4496 else if (sop
== 0 && sopcde
== 3 && HLs
== 1 && bit8
== 0)
4498 OUTS (outf
, "A1 = A1 << ");
4499 OUTS (outf
, uimm5 (immag
));
4501 else if (sop
== 0 && sopcde
== 3 && HLs
== 1 && bit8
== 1)
4503 OUTS (outf
, "A1 = A1 >>> ");
4504 OUTS (outf
, uimm5 (newimmag
));
4506 else if (sop
== 1 && sopcde
== 3 && HLs
== 0)
4508 OUTS (outf
, "A0 = A0 >> ");
4509 OUTS (outf
, uimm5 (newimmag
));
4511 else if (sop
== 1 && sopcde
== 3 && HLs
== 1)
4513 OUTS (outf
, "A1 = A1 >> ");
4514 OUTS (outf
, uimm5 (newimmag
));
4516 else if (sop
== 2 && sopcde
== 3 && HLs
== 0)
4518 OUTS (outf
, "A0 = ROT A0 BY ");
4519 OUTS (outf
, imm6 (immag
));
4521 else if (sop
== 1 && sopcde
== 1 && bit8
== 0)
4523 OUTS (outf
, dregs (dst0
));
4525 OUTS (outf
, dregs (src1
));
4526 OUTS (outf
, " << ");
4527 OUTS (outf
, uimm5 (immag
));
4528 OUTS (outf
, " (V, S)");
4530 else if (sop
== 1 && sopcde
== 1 && bit8
== 1)
4532 OUTS (outf
, dregs (dst0
));
4534 OUTS (outf
, dregs (src1
));
4535 OUTS (outf
, " >>> ");
4536 OUTS (outf
, imm5 (-immag
));
4537 OUTS (outf
, " (V, S)");
4539 else if (sop
== 2 && sopcde
== 1 && bit8
== 1)
4541 OUTS (outf
, dregs (dst0
));
4543 OUTS (outf
, dregs (src1
));
4544 OUTS (outf
, " >> ");
4545 OUTS (outf
, uimm5 (newimmag
));
4546 OUTS (outf
, " (V)");
4548 else if (sop
== 2 && sopcde
== 1 && bit8
== 0)
4550 OUTS (outf
, dregs (dst0
));
4552 OUTS (outf
, dregs (src1
));
4553 OUTS (outf
, " << ");
4554 OUTS (outf
, imm5 (immag
));
4555 OUTS (outf
, " (V)");
4557 else if (sop
== 0 && sopcde
== 1)
4559 OUTS (outf
, dregs (dst0
));
4561 OUTS (outf
, dregs (src1
));
4562 OUTS (outf
, " >>> ");
4563 OUTS (outf
, uimm5 (newimmag
));
4564 OUTS (outf
, " (V)");
4566 else if (sop
== 1 && sopcde
== 2)
4568 OUTS (outf
, dregs (dst0
));
4570 OUTS (outf
, dregs (src1
));
4571 OUTS (outf
, " << ");
4572 OUTS (outf
, uimm5 (immag
));
4573 OUTS (outf
, " (S)");
4575 else if (sop
== 2 && sopcde
== 2 && bit8
== 1)
4577 OUTS (outf
, dregs (dst0
));
4579 OUTS (outf
, dregs (src1
));
4580 OUTS (outf
, " >> ");
4581 OUTS (outf
, uimm5 (newimmag
));
4583 else if (sop
== 2 && sopcde
== 2 && bit8
== 0)
4585 OUTS (outf
, dregs (dst0
));
4587 OUTS (outf
, dregs (src1
));
4588 OUTS (outf
, " << ");
4589 OUTS (outf
, uimm5 (immag
));
4591 else if (sop
== 3 && sopcde
== 2)
4593 OUTS (outf
, dregs (dst0
));
4594 OUTS (outf
, " = ROT ");
4595 OUTS (outf
, dregs (src1
));
4596 OUTS (outf
, " BY ");
4597 OUTS (outf
, imm6 (immag
));
4599 else if (sop
== 0 && sopcde
== 2)
4601 OUTS (outf
, dregs (dst0
));
4603 OUTS (outf
, dregs (src1
));
4604 OUTS (outf
, " >>> ");
4605 OUTS (outf
, uimm5 (newimmag
));
4614 decode_pseudoDEBUG_0 (TIword iw0
, disassemble_info
*outf
)
4617 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4618 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4619 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4620 int fn
= ((iw0
>> PseudoDbg_fn_bits
) & PseudoDbg_fn_mask
);
4621 int grp
= ((iw0
>> PseudoDbg_grp_bits
) & PseudoDbg_grp_mask
);
4622 int reg
= ((iw0
>> PseudoDbg_reg_bits
) & PseudoDbg_reg_mask
);
4627 if (reg
== 0 && fn
== 3)
4628 OUTS (outf
, "DBG A0");
4630 else if (reg
== 1 && fn
== 3)
4631 OUTS (outf
, "DBG A1");
4633 else if (reg
== 3 && fn
== 3)
4634 OUTS (outf
, "ABORT");
4636 else if (reg
== 4 && fn
== 3)
4639 else if (reg
== 5 && fn
== 3)
4640 OUTS (outf
, "DBGHALT");
4642 else if (reg
== 6 && fn
== 3)
4644 OUTS (outf
, "DBGCMPLX (");
4645 OUTS (outf
, dregs (grp
));
4648 else if (reg
== 7 && fn
== 3)
4651 else if (grp
== 0 && fn
== 2)
4653 OUTS (outf
, "OUTC ");
4654 OUTS (outf
, dregs (reg
));
4658 OUTS (outf
, "DBG ");
4659 OUTS (outf
, allregs (reg
, grp
));
4663 OUTS (outf
, "PRNT");
4664 OUTS (outf
, allregs (reg
, grp
));
4673 decode_pseudoOChar_0 (TIword iw0
, disassemble_info
*outf
)
4676 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4677 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4678 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4679 int ch
= ((iw0
>> PseudoChr_ch_bits
) & PseudoChr_ch_mask
);
4684 OUTS (outf
, "OUTC ");
4685 OUTS (outf
, uimm8 (ch
));
4691 decode_pseudodbg_assert_0 (TIword iw0
, TIword iw1
, disassemble_info
*outf
)
4694 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4695 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4696 |.expected......................................................|
4697 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4698 int expected
= ((iw1
>> PseudoDbg_Assert_expected_bits
) & PseudoDbg_Assert_expected_mask
);
4699 int dbgop
= ((iw0
>> (PseudoDbg_Assert_dbgop_bits
- 16)) & PseudoDbg_Assert_dbgop_mask
);
4700 int grp
= ((iw0
>> (PseudoDbg_Assert_grp_bits
- 16)) & PseudoDbg_Assert_grp_mask
);
4701 int regtest
= ((iw0
>> (PseudoDbg_Assert_regtest_bits
- 16)) & PseudoDbg_Assert_regtest_mask
);
4708 OUTS (outf
, "DBGA (");
4709 OUTS (outf
, regs_lo (regtest
, grp
));
4711 OUTS (outf
, uimm16 (expected
));
4714 else if (dbgop
== 1)
4716 OUTS (outf
, "DBGA (");
4717 OUTS (outf
, regs_hi (regtest
, grp
));
4719 OUTS (outf
, uimm16 (expected
));
4722 else if (dbgop
== 2)
4724 OUTS (outf
, "DBGAL (");
4725 OUTS (outf
, allregs (regtest
, grp
));
4727 OUTS (outf
, uimm16 (expected
));
4730 else if (dbgop
== 3)
4732 OUTS (outf
, "DBGAH (");
4733 OUTS (outf
, allregs (regtest
, grp
));
4735 OUTS (outf
, uimm16 (expected
));
4744 _print_insn_bfin (bfd_vma pc
, disassemble_info
*outf
)
4752 status
= (*outf
->read_memory_func
) (pc
& ~0x1, buf
, 2, outf
);
4755 status
= (*outf
->read_memory_func
) ((pc
+ 2) & ~0x1, buf
+ 2, 2, outf
);
4759 iw0
= bfd_getl16 (buf
);
4760 iw1
= bfd_getl16 (buf
+ 2);
4762 if ((iw0
& 0xf7ff) == 0xc003 && iw1
== 0x1800)
4766 OUTS (outf
, "ILLEGAL");
4769 OUTS (outf
, "MNOP");
4772 else if ((iw0
& 0xff00) == 0x0000)
4773 rv
= decode_ProgCtrl_0 (iw0
, outf
);
4774 else if ((iw0
& 0xffc0) == 0x0240)
4775 rv
= decode_CaCTRL_0 (iw0
, outf
);
4776 else if ((iw0
& 0xff80) == 0x0100)
4777 rv
= decode_PushPopReg_0 (iw0
, outf
);
4778 else if ((iw0
& 0xfe00) == 0x0400)
4779 rv
= decode_PushPopMultiple_0 (iw0
, outf
);
4780 else if ((iw0
& 0xfe00) == 0x0600)
4781 rv
= decode_ccMV_0 (iw0
, outf
);
4782 else if ((iw0
& 0xf800) == 0x0800)
4783 rv
= decode_CCflag_0 (iw0
, outf
);
4784 else if ((iw0
& 0xffe0) == 0x0200)
4785 rv
= decode_CC2dreg_0 (iw0
, outf
);
4786 else if ((iw0
& 0xff00) == 0x0300)
4787 rv
= decode_CC2stat_0 (iw0
, outf
);
4788 else if ((iw0
& 0xf000) == 0x1000)
4789 rv
= decode_BRCC_0 (iw0
, pc
, outf
);
4790 else if ((iw0
& 0xf000) == 0x2000)
4791 rv
= decode_UJUMP_0 (iw0
, pc
, outf
);
4792 else if ((iw0
& 0xf000) == 0x3000)
4793 rv
= decode_REGMV_0 (iw0
, outf
);
4794 else if ((iw0
& 0xfc00) == 0x4000)
4795 rv
= decode_ALU2op_0 (iw0
, outf
);
4796 else if ((iw0
& 0xfe00) == 0x4400)
4797 rv
= decode_PTR2op_0 (iw0
, outf
);
4798 else if ((iw0
& 0xf800) == 0x4800)
4799 rv
= decode_LOGI2op_0 (iw0
, outf
);
4800 else if ((iw0
& 0xf000) == 0x5000)
4801 rv
= decode_COMP3op_0 (iw0
, outf
);
4802 else if ((iw0
& 0xf800) == 0x6000)
4803 rv
= decode_COMPI2opD_0 (iw0
, outf
);
4804 else if ((iw0
& 0xf800) == 0x6800)
4805 rv
= decode_COMPI2opP_0 (iw0
, outf
);
4806 else if ((iw0
& 0xf000) == 0x8000)
4807 rv
= decode_LDSTpmod_0 (iw0
, outf
);
4808 else if ((iw0
& 0xff60) == 0x9e60)
4809 rv
= decode_dagMODim_0 (iw0
, outf
);
4810 else if ((iw0
& 0xfff0) == 0x9f60)
4811 rv
= decode_dagMODik_0 (iw0
, outf
);
4812 else if ((iw0
& 0xfc00) == 0x9c00)
4813 rv
= decode_dspLDST_0 (iw0
, outf
);
4814 else if ((iw0
& 0xf000) == 0x9000)
4815 rv
= decode_LDST_0 (iw0
, outf
);
4816 else if ((iw0
& 0xfc00) == 0xb800)
4817 rv
= decode_LDSTiiFP_0 (iw0
, outf
);
4818 else if ((iw0
& 0xe000) == 0xA000)
4819 rv
= decode_LDSTii_0 (iw0
, outf
);
4820 else if ((iw0
& 0xff80) == 0xe080 && (iw1
& 0x0C00) == 0x0000)
4821 rv
= decode_LoopSetup_0 (iw0
, iw1
, pc
, outf
);
4822 else if ((iw0
& 0xff00) == 0xe100 && (iw1
& 0x0000) == 0x0000)
4823 rv
= decode_LDIMMhalf_0 (iw0
, iw1
, outf
);
4824 else if ((iw0
& 0xfe00) == 0xe200 && (iw1
& 0x0000) == 0x0000)
4825 rv
= decode_CALLa_0 (iw0
, iw1
, pc
, outf
);
4826 else if ((iw0
& 0xfc00) == 0xe400 && (iw1
& 0x0000) == 0x0000)
4827 rv
= decode_LDSTidxI_0 (iw0
, iw1
, outf
);
4828 else if ((iw0
& 0xfffe) == 0xe800 && (iw1
& 0x0000) == 0x0000)
4829 rv
= decode_linkage_0 (iw0
, iw1
, outf
);
4830 else if ((iw0
& 0xf600) == 0xc000 && (iw1
& 0x0000) == 0x0000)
4831 rv
= decode_dsp32mac_0 (iw0
, iw1
, outf
);
4832 else if ((iw0
& 0xf600) == 0xc200 && (iw1
& 0x0000) == 0x0000)
4833 rv
= decode_dsp32mult_0 (iw0
, iw1
, outf
);
4834 else if ((iw0
& 0xf7c0) == 0xc400 && (iw1
& 0x0000) == 0x0000)
4835 rv
= decode_dsp32alu_0 (iw0
, iw1
, outf
);
4836 else if ((iw0
& 0xf780) == 0xc600 && (iw1
& 0x01c0) == 0x0000)
4837 rv
= decode_dsp32shift_0 (iw0
, iw1
, outf
);
4838 else if ((iw0
& 0xf780) == 0xc680 && (iw1
& 0x0000) == 0x0000)
4839 rv
= decode_dsp32shiftimm_0 (iw0
, iw1
, outf
);
4840 else if ((iw0
& 0xff00) == 0xf800)
4841 rv
= decode_pseudoDEBUG_0 (iw0
, outf
);
4842 else if ((iw0
& 0xFF00) == 0xF900)
4843 rv
= decode_pseudoOChar_0 (iw0
, outf
);
4844 else if ((iw0
& 0xFF00) == 0xf000 && (iw1
& 0x0000) == 0x0000)
4845 rv
= decode_pseudodbg_assert_0 (iw0
, iw1
, outf
);
4848 OUTS (outf
, "ILLEGAL");
4855 print_insn_bfin (bfd_vma pc
, disassemble_info
*outf
)
4862 status
= (*outf
->read_memory_func
) (pc
& ~0x01, buf
, 2, outf
);
4865 iw0
= bfd_getl16 (buf
);
4867 count
+= _print_insn_bfin (pc
, outf
);
4869 /* Proper display of multiple issue instructions. */
4871 if (count
== 4 && (iw0
& 0xc000) == 0xc000 && (iw0
& BIT_MULTI_INS
)
4872 && ((iw0
& 0xe800) != 0xe800 /* Not Linkage. */ ))
4878 outf
->fprintf_func (outf
->stream
, " || ");
4879 len
= _print_insn_bfin (pc
+ 4, outf
);
4880 outf
->fprintf_func (outf
->stream
, " || ");
4883 len
= _print_insn_bfin (pc
+ 6, outf
);
4891 outf
->fprintf_func (outf
->stream
, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
4899 outf
->fprintf_func (outf
->stream
, ";");