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* arc-dis.c: Include sysdep.h first, remove some redundant includes.
[deliverable/binutils-gdb.git] / opcodes / bfin-dis.c
1 /* Disassemble ADI Blackfin Instructions.
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
3 Free Software Foundation, Inc.
4
5 This file is part of libopcodes.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22 #include "sysdep.h"
23 #include <stdio.h>
24
25 #include "opcode/bfin.h"
26
27 #ifndef PRINTF
28 #define PRINTF printf
29 #endif
30
31 #ifndef EXIT
32 #define EXIT exit
33 #endif
34
35 typedef long TIword;
36
37 #define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
38 #define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
39 #define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
40 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
41
42 #include "dis-asm.h"
43
44 typedef unsigned int bu32;
45
46 static char comment = 0;
47 static char parallel = 0;
48
49 typedef enum
50 {
51 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
52 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
53 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
54 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
55 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
56 } const_forms_t;
57
58 static const struct
59 {
60 const char *name;
61 const int nbits;
62 const char reloc;
63 const char issigned;
64 const char pcrel;
65 const char scale;
66 const char offset;
67 const char negative;
68 const char positive;
69 const char decimal;
70 const char leading;
71 const char exact;
72 } constant_formats[] =
73 {
74 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
75 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
76 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
77 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
78 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
79 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
80 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
81 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
82 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
83 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
84 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
85 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
86 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
87 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
88 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
89 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
90 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
91 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
92 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
94 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
95 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
97 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
98 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
99 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
100 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
101 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
102 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
103 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
104 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
106 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
107 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
108 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
109 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
110 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
111 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
112 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
113 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
114 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
115 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
116 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
117 };
118
119 static const char *
120 fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
121 {
122 static char buf[60];
123
124 if (constant_formats[cf].reloc)
125 {
126 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
127 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
128 if (constant_formats[cf].pcrel)
129 ea += pc;
130
131 /* truncate to 32-bits for proper symbol lookup/matching */
132 ea = (bu32)ea;
133
134 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
135 {
136 outf->print_address_func (ea, outf);
137 return "";
138 }
139 else
140 {
141 sprintf (buf, "%lx", (unsigned long) x);
142 return buf;
143 }
144 }
145
146 /* Negative constants have an implied sign bit. */
147 if (constant_formats[cf].negative)
148 {
149 int nb = constant_formats[cf].nbits + 1;
150
151 x = x | (1 << constant_formats[cf].nbits);
152 x = SIGNEXTEND (x, nb);
153 }
154 else
155 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
156
157 if (constant_formats[cf].offset)
158 x += constant_formats[cf].offset;
159
160 if (constant_formats[cf].scale)
161 x <<= constant_formats[cf].scale;
162
163 if (constant_formats[cf].decimal)
164 sprintf (buf, "%*li", constant_formats[cf].leading, x);
165 else
166 {
167 if (constant_formats[cf].issigned && x < 0)
168 sprintf (buf, "-0x%x", abs (x));
169 else
170 sprintf (buf, "0x%lx", (unsigned long) x);
171 }
172
173 return buf;
174 }
175
176 static bu32
177 fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
178 {
179 if (0 && constant_formats[cf].reloc)
180 {
181 bu32 ea = (((constant_formats[cf].pcrel
182 ? SIGNEXTEND (x, constant_formats[cf].nbits)
183 : x) + constant_formats[cf].offset)
184 << constant_formats[cf].scale);
185 if (constant_formats[cf].pcrel)
186 ea += pc;
187
188 return ea;
189 }
190
191 /* Negative constants have an implied sign bit. */
192 if (constant_formats[cf].negative)
193 {
194 int nb = constant_formats[cf].nbits + 1;
195 x = x | (1 << constant_formats[cf].nbits);
196 x = SIGNEXTEND (x, nb);
197 }
198 else if (constant_formats[cf].issigned)
199 x = SIGNEXTEND (x, constant_formats[cf].nbits);
200
201 x += constant_formats[cf].offset;
202 x <<= constant_formats[cf].scale;
203
204 return x;
205 }
206
207 enum machine_registers
208 {
209 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
210 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
211 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
212 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
213 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
214 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
215 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
216 REG_L2, REG_L3,
217 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
218 REG_AQ, REG_V, REG_VS,
219 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
220 REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
221 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
222 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
223 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
224 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
225 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
226 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
227 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
228 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
229 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
230 REG_LASTREG,
231 };
232
233 enum reg_class
234 {
235 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
236 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
237 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
238 rc_sysregs3, rc_allregs,
239 LIM_REG_CLASSES
240 };
241
242 static const char * const reg_names[] =
243 {
244 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
245 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
246 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
247 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
248 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
249 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
250 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
251 "L2", "L3",
252 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
253 "AQ", "V", "VS",
254 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
255 "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
256 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
257 "RETE", "EMUDAT",
258 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
259 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
260 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
261 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
262 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
263 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
264 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
265 "AC0_COPY", "V_COPY", "RND_MOD",
266 "LASTREG",
267 0
268 };
269
270 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
271
272 /* RL(0..7). */
273 static const enum machine_registers decode_dregs_lo[] =
274 {
275 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
276 };
277
278 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
279
280 /* RH(0..7). */
281 static const enum machine_registers decode_dregs_hi[] =
282 {
283 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
284 };
285
286 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
287
288 /* R(0..7). */
289 static const enum machine_registers decode_dregs[] =
290 {
291 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
292 };
293
294 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
295
296 /* R BYTE(0..7). */
297 static const enum machine_registers decode_dregs_byte[] =
298 {
299 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
300 };
301
302 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
303
304 /* P(0..5) SP FP. */
305 static const enum machine_registers decode_pregs[] =
306 {
307 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
308 };
309
310 #define pregs(x) REGNAME (decode_pregs[(x) & 7])
311 #define spfp(x) REGNAME (decode_spfp[(x) & 1])
312 #define dregs_hilo(x, i) REGNAME (decode_dregs_hilo[((i) << 3) | (x)])
313 #define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
314 #define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
315 #define accum(x) REGNAME (decode_accum[(x) & 1])
316
317 /* I(0..3). */
318 static const enum machine_registers decode_iregs[] =
319 {
320 REG_I0, REG_I1, REG_I2, REG_I3,
321 };
322
323 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
324
325 /* M(0..3). */
326 static const enum machine_registers decode_mregs[] =
327 {
328 REG_M0, REG_M1, REG_M2, REG_M3,
329 };
330
331 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
332 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
333 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
334
335 /* dregs pregs. */
336 static const enum machine_registers decode_dpregs[] =
337 {
338 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
339 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
340 };
341
342 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
343
344 /* [dregs pregs]. */
345 static const enum machine_registers decode_gregs[] =
346 {
347 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
348 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
349 };
350
351 #define gregs(x, i) REGNAME (decode_gregs[((i) << 3) | (x)])
352
353 /* [dregs pregs (iregs mregs) (bregs lregs)]. */
354 static const enum machine_registers decode_regs[] =
355 {
356 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
357 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
358 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
359 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
360 };
361
362 #define regs(x, i) REGNAME (decode_regs[((i) << 3) | (x)])
363
364 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
365 static const enum machine_registers decode_regs_lo[] =
366 {
367 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
368 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
369 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
370 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
371 };
372
373 #define regs_lo(x, i) REGNAME (decode_regs_lo[((i) << 3) | (x)])
374
375 /* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
376 static const enum machine_registers decode_regs_hi[] =
377 {
378 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
379 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
380 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
381 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
382 };
383
384 #define regs_hi(x, i) REGNAME (decode_regs_hi[((i) << 3) | (x)])
385
386 static const enum machine_registers decode_statbits[] =
387 {
388 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
389 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
390 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
391 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
392 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
393 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
394 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
395 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
396 };
397
398 #define statbits(x) REGNAME (decode_statbits[(x) & 31])
399
400 /* LC0 LC1. */
401 static const enum machine_registers decode_counters[] =
402 {
403 REG_LC0, REG_LC1,
404 };
405
406 #define counters(x) REGNAME (decode_counters[(x) & 1])
407 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
408
409 /* [dregs pregs (iregs mregs) (bregs lregs)
410 dregs2_sysregs1 open sysregs2 sysregs3]. */
411 static const enum machine_registers decode_allregs[] =
412 {
413 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
414 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
415 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
416 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
417 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
418 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
419 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
420 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
421 REG_LASTREG,
422 };
423
424 #define IS_DREG(g,r) ((g) == 0 && (r) < 8)
425 #define IS_PREG(g,r) ((g) == 1 && (r) < 8)
426 #define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
427 #define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
428 #define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
429 #define IS_SYSREG(g,r) \
430 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
431 #define IS_RESERVEDREG(g,r) \
432 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
433
434 #define allreg(r,g) (!IS_RESERVEDREG (g, r))
435 #define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
436
437 #define allregs(x, i) REGNAME (decode_allregs[((i) << 3) | (x)])
438 #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
439 #define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
440 #define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
441 #define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
442 #define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
443 #define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
444 #define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
445 #define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
446 #define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
447 #define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
448 #define imm16(x) fmtconst (c_imm16, x, 0, outf)
449 #define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
450 #define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
451 #define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
452 #define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
453 #define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
454 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
455 #define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
456 #define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
457 #define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
458 #define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
459 #define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
460 #define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
461 #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
462 #define imm3(x) fmtconst (c_imm3, x, 0, outf)
463 #define imm4(x) fmtconst (c_imm4, x, 0, outf)
464 #define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
465 #define imm5(x) fmtconst (c_imm5, x, 0, outf)
466 #define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
467 #define imm6(x) fmtconst (c_imm6, x, 0, outf)
468 #define imm7(x) fmtconst (c_imm7, x, 0, outf)
469 #define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
470 #define imm8(x) fmtconst (c_imm8, x, 0, outf)
471 #define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
472 #define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
473 #define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
474 #define imm32(x) fmtconst (c_imm32, x, 0, outf)
475 #define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
476 #define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
477 #define imm7_val(x) fmtconst_val (c_imm7, x, 0)
478 #define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
479 #define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
480
481 /* (arch.pm)arch_disassembler_functions. */
482 #ifndef OUTS
483 #define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt)
484 #endif
485
486 static void
487 amod0 (int s0, int x0, disassemble_info *outf)
488 {
489 if (s0 == 1 && x0 == 0)
490 OUTS (outf, " (S)");
491 else if (s0 == 0 && x0 == 1)
492 OUTS (outf, " (CO)");
493 else if (s0 == 1 && x0 == 1)
494 OUTS (outf, " (SCO)");
495 }
496
497 static void
498 amod1 (int s0, int x0, disassemble_info *outf)
499 {
500 if (s0 == 0 && x0 == 0)
501 OUTS (outf, " (NS)");
502 else if (s0 == 1 && x0 == 0)
503 OUTS (outf, " (S)");
504 }
505
506 static void
507 amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
508 {
509 if (s0 == 1 && x0 == 0 && aop0 == 0)
510 OUTS (outf, " (S)");
511 else if (s0 == 0 && x0 == 1 && aop0 == 0)
512 OUTS (outf, " (CO)");
513 else if (s0 == 1 && x0 == 1 && aop0 == 0)
514 OUTS (outf, " (SCO)");
515 else if (s0 == 0 && x0 == 0 && aop0 == 2)
516 OUTS (outf, " (ASR)");
517 else if (s0 == 1 && x0 == 0 && aop0 == 2)
518 OUTS (outf, " (S, ASR)");
519 else if (s0 == 0 && x0 == 1 && aop0 == 2)
520 OUTS (outf, " (CO, ASR)");
521 else if (s0 == 1 && x0 == 1 && aop0 == 2)
522 OUTS (outf, " (SCO, ASR)");
523 else if (s0 == 0 && x0 == 0 && aop0 == 3)
524 OUTS (outf, " (ASL)");
525 else if (s0 == 1 && x0 == 0 && aop0 == 3)
526 OUTS (outf, " (S, ASL)");
527 else if (s0 == 0 && x0 == 1 && aop0 == 3)
528 OUTS (outf, " (CO, ASL)");
529 else if (s0 == 1 && x0 == 1 && aop0 == 3)
530 OUTS (outf, " (SCO, ASL)");
531 }
532
533 static void
534 searchmod (int r0, disassemble_info *outf)
535 {
536 if (r0 == 0)
537 OUTS (outf, "GT");
538 else if (r0 == 1)
539 OUTS (outf, "GE");
540 else if (r0 == 2)
541 OUTS (outf, "LT");
542 else if (r0 == 3)
543 OUTS (outf, "LE");
544 }
545
546 static void
547 aligndir (int r0, disassemble_info *outf)
548 {
549 if (r0 == 1)
550 OUTS (outf, " (R)");
551 }
552
553 static int
554 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
555 {
556 const char *s0, *s1;
557
558 if (h0)
559 s0 = dregs_hi (src0);
560 else
561 s0 = dregs_lo (src0);
562
563 if (h1)
564 s1 = dregs_hi (src1);
565 else
566 s1 = dregs_lo (src1);
567
568 OUTS (outf, s0);
569 OUTS (outf, " * ");
570 OUTS (outf, s1);
571 return 0;
572 }
573
574 static int
575 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
576 {
577 const char *a;
578 const char *sop = "<unknown op>";
579
580 if (which)
581 a = "A1";
582 else
583 a = "A0";
584
585 if (op == 3)
586 {
587 OUTS (outf, a);
588 return 0;
589 }
590
591 switch (op)
592 {
593 case 0: sop = " = "; break;
594 case 1: sop = " += "; break;
595 case 2: sop = " -= "; break;
596 default: break;
597 }
598
599 OUTS (outf, a);
600 OUTS (outf, sop);
601 decode_multfunc (h0, h1, src0, src1, outf);
602
603 return 0;
604 }
605
606 static void
607 decode_optmode (int mod, int MM, disassemble_info *outf)
608 {
609 if (mod == 0 && MM == 0)
610 return;
611
612 OUTS (outf, " (");
613
614 if (MM && !mod)
615 {
616 OUTS (outf, "M)");
617 return;
618 }
619
620 if (MM)
621 OUTS (outf, "M, ");
622
623 if (mod == M_S2RND)
624 OUTS (outf, "S2RND");
625 else if (mod == M_T)
626 OUTS (outf, "T");
627 else if (mod == M_W32)
628 OUTS (outf, "W32");
629 else if (mod == M_FU)
630 OUTS (outf, "FU");
631 else if (mod == M_TFU)
632 OUTS (outf, "TFU");
633 else if (mod == M_IS)
634 OUTS (outf, "IS");
635 else if (mod == M_ISS2)
636 OUTS (outf, "ISS2");
637 else if (mod == M_IH)
638 OUTS (outf, "IH");
639 else if (mod == M_IU)
640 OUTS (outf, "IU");
641 else
642 abort ();
643
644 OUTS (outf, ")");
645 }
646
647 static struct saved_state
648 {
649 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
650 bu32 ax[2], aw[2];
651 bu32 lt[2], lc[2], lb[2];
652 bu32 rets;
653 } saved_state;
654
655 #define DREG(x) (saved_state.dpregs[x])
656 #define GREG(x, i) DPREG ((x) | ((i) << 3))
657 #define DPREG(x) (saved_state.dpregs[x])
658 #define DREG(x) (saved_state.dpregs[x])
659 #define PREG(x) (saved_state.dpregs[(x) + 8])
660 #define SPREG PREG (6)
661 #define FPREG PREG (7)
662 #define IREG(x) (saved_state.iregs[x])
663 #define MREG(x) (saved_state.mregs[x])
664 #define BREG(x) (saved_state.bregs[x])
665 #define LREG(x) (saved_state.lregs[x])
666 #define AXREG(x) (saved_state.ax[x])
667 #define AWREG(x) (saved_state.aw[x])
668 #define LCREG(x) (saved_state.lc[x])
669 #define LTREG(x) (saved_state.lt[x])
670 #define LBREG(x) (saved_state.lb[x])
671 #define RETSREG (saved_state.rets)
672
673 static bu32 *
674 get_allreg (int grp, int reg)
675 {
676 int fullreg = (grp << 3) | reg;
677 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
678 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
679 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
680 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
681 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
682 , , , , , , , ,
683 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
684 REG_CYCLES2,
685 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
686 REG_LASTREG */
687 switch (fullreg >> 2)
688 {
689 case 0: case 1: return &DREG (reg);
690 case 2: case 3: return &PREG (reg);
691 case 4: return &IREG (reg & 3);
692 case 5: return &MREG (reg & 3);
693 case 6: return &BREG (reg & 3);
694 case 7: return &LREG (reg & 3);
695 default:
696 switch (fullreg)
697 {
698 case 32: return &AXREG (0);
699 case 33: return &AWREG (0);
700 case 34: return &AXREG (1);
701 case 35: return &AWREG (1);
702 case 39: return &RETSREG;
703 case 48: return &LCREG (0);
704 case 49: return &LTREG (0);
705 case 50: return &LBREG (0);
706 case 51: return &LCREG (1);
707 case 52: return &LTREG (1);
708 case 53: return &LBREG (1);
709 }
710 }
711 abort ();
712 }
713
714 static int
715 decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
716 {
717 /* ProgCtrl
718 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
719 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
720 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
721 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
722 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
723
724 if (prgfunc == 0 && poprnd == 0)
725 OUTS (outf, "NOP");
726 else if (parallel)
727 return 0;
728 else if (prgfunc == 1 && poprnd == 0)
729 OUTS (outf, "RTS");
730 else if (prgfunc == 1 && poprnd == 1)
731 OUTS (outf, "RTI");
732 else if (prgfunc == 1 && poprnd == 2)
733 OUTS (outf, "RTX");
734 else if (prgfunc == 1 && poprnd == 3)
735 OUTS (outf, "RTN");
736 else if (prgfunc == 1 && poprnd == 4)
737 OUTS (outf, "RTE");
738 else if (prgfunc == 2 && poprnd == 0)
739 OUTS (outf, "IDLE");
740 else if (prgfunc == 2 && poprnd == 3)
741 OUTS (outf, "CSYNC");
742 else if (prgfunc == 2 && poprnd == 4)
743 OUTS (outf, "SSYNC");
744 else if (prgfunc == 2 && poprnd == 5)
745 OUTS (outf, "EMUEXCPT");
746 else if (prgfunc == 3 && IS_DREG (0, poprnd))
747 {
748 OUTS (outf, "CLI ");
749 OUTS (outf, dregs (poprnd));
750 }
751 else if (prgfunc == 4 && IS_DREG (0, poprnd))
752 {
753 OUTS (outf, "STI ");
754 OUTS (outf, dregs (poprnd));
755 }
756 else if (prgfunc == 5 && IS_PREG (1, poprnd))
757 {
758 OUTS (outf, "JUMP (");
759 OUTS (outf, pregs (poprnd));
760 OUTS (outf, ")");
761 }
762 else if (prgfunc == 6 && IS_PREG (1, poprnd))
763 {
764 OUTS (outf, "CALL (");
765 OUTS (outf, pregs (poprnd));
766 OUTS (outf, ")");
767 }
768 else if (prgfunc == 7 && IS_PREG (1, poprnd))
769 {
770 OUTS (outf, "CALL (PC + ");
771 OUTS (outf, pregs (poprnd));
772 OUTS (outf, ")");
773 }
774 else if (prgfunc == 8 && IS_PREG (1, poprnd))
775 {
776 OUTS (outf, "JUMP (PC + ");
777 OUTS (outf, pregs (poprnd));
778 OUTS (outf, ")");
779 }
780 else if (prgfunc == 9)
781 {
782 OUTS (outf, "RAISE ");
783 OUTS (outf, uimm4 (poprnd));
784 }
785 else if (prgfunc == 10)
786 {
787 OUTS (outf, "EXCPT ");
788 OUTS (outf, uimm4 (poprnd));
789 }
790 else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
791 {
792 OUTS (outf, "TESTSET (");
793 OUTS (outf, pregs (poprnd));
794 OUTS (outf, ")");
795 }
796 else
797 return 0;
798 return 2;
799 }
800
801 static int
802 decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
803 {
804 /* CaCTRL
805 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
806 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
807 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
808 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
809 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
810 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
811
812 if (parallel)
813 return 0;
814
815 if (a == 0 && op == 0)
816 {
817 OUTS (outf, "PREFETCH[");
818 OUTS (outf, pregs (reg));
819 OUTS (outf, "]");
820 }
821 else if (a == 0 && op == 1)
822 {
823 OUTS (outf, "FLUSHINV[");
824 OUTS (outf, pregs (reg));
825 OUTS (outf, "]");
826 }
827 else if (a == 0 && op == 2)
828 {
829 OUTS (outf, "FLUSH[");
830 OUTS (outf, pregs (reg));
831 OUTS (outf, "]");
832 }
833 else if (a == 0 && op == 3)
834 {
835 OUTS (outf, "IFLUSH[");
836 OUTS (outf, pregs (reg));
837 OUTS (outf, "]");
838 }
839 else if (a == 1 && op == 0)
840 {
841 OUTS (outf, "PREFETCH[");
842 OUTS (outf, pregs (reg));
843 OUTS (outf, "++]");
844 }
845 else if (a == 1 && op == 1)
846 {
847 OUTS (outf, "FLUSHINV[");
848 OUTS (outf, pregs (reg));
849 OUTS (outf, "++]");
850 }
851 else if (a == 1 && op == 2)
852 {
853 OUTS (outf, "FLUSH[");
854 OUTS (outf, pregs (reg));
855 OUTS (outf, "++]");
856 }
857 else if (a == 1 && op == 3)
858 {
859 OUTS (outf, "IFLUSH[");
860 OUTS (outf, pregs (reg));
861 OUTS (outf, "++]");
862 }
863 else
864 return 0;
865 return 2;
866 }
867
868 static int
869 decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
870 {
871 /* PushPopReg
872 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
873 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
874 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
875 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
876 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
877 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
878
879 if (parallel)
880 return 0;
881
882 if (W == 0 && mostreg (reg, grp))
883 {
884 OUTS (outf, allregs (reg, grp));
885 OUTS (outf, " = [SP++]");
886 }
887 else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
888 {
889 OUTS (outf, "[--SP] = ");
890 OUTS (outf, allregs (reg, grp));
891 }
892 else
893 return 0;
894 return 2;
895 }
896
897 static int
898 decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
899 {
900 /* PushPopMultiple
901 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
902 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
903 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
904 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
905 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
906 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
907 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
908 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
909
910 if (parallel)
911 return 0;
912
913 if (pr > 5)
914 return 0;
915
916 if (W == 1 && d == 1 && p == 1)
917 {
918 OUTS (outf, "[--SP] = (R7:");
919 OUTS (outf, imm5d (dr));
920 OUTS (outf, ", P5:");
921 OUTS (outf, imm5d (pr));
922 OUTS (outf, ")");
923 }
924 else if (W == 1 && d == 1 && p == 0 && pr == 0)
925 {
926 OUTS (outf, "[--SP] = (R7:");
927 OUTS (outf, imm5d (dr));
928 OUTS (outf, ")");
929 }
930 else if (W == 1 && d == 0 && p == 1 && dr == 0)
931 {
932 OUTS (outf, "[--SP] = (P5:");
933 OUTS (outf, imm5d (pr));
934 OUTS (outf, ")");
935 }
936 else if (W == 0 && d == 1 && p == 1)
937 {
938 OUTS (outf, "(R7:");
939 OUTS (outf, imm5d (dr));
940 OUTS (outf, ", P5:");
941 OUTS (outf, imm5d (pr));
942 OUTS (outf, ") = [SP++]");
943 }
944 else if (W == 0 && d == 1 && p == 0 && pr == 0)
945 {
946 OUTS (outf, "(R7:");
947 OUTS (outf, imm5d (dr));
948 OUTS (outf, ") = [SP++]");
949 }
950 else if (W == 0 && d == 0 && p == 1 && dr == 0)
951 {
952 OUTS (outf, "(P5:");
953 OUTS (outf, imm5d (pr));
954 OUTS (outf, ") = [SP++]");
955 }
956 else
957 return 0;
958 return 2;
959 }
960
961 static int
962 decode_ccMV_0 (TIword iw0, disassemble_info *outf)
963 {
964 /* ccMV
965 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
966 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
967 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
968 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
969 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
970 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
971 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
972 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
973
974 if (parallel)
975 return 0;
976
977 if (T == 1)
978 {
979 OUTS (outf, "IF CC ");
980 OUTS (outf, gregs (dst, d));
981 OUTS (outf, " = ");
982 OUTS (outf, gregs (src, s));
983 }
984 else if (T == 0)
985 {
986 OUTS (outf, "IF !CC ");
987 OUTS (outf, gregs (dst, d));
988 OUTS (outf, " = ");
989 OUTS (outf, gregs (src, s));
990 }
991 else
992 return 0;
993 return 2;
994 }
995
996 static int
997 decode_CCflag_0 (TIword iw0, disassemble_info *outf)
998 {
999 /* CCflag
1000 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1001 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1002 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1003 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1004 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1005 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1006 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1007 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1008
1009 if (parallel)
1010 return 0;
1011
1012 if (opc == 0 && I == 0 && G == 0)
1013 {
1014 OUTS (outf, "CC = ");
1015 OUTS (outf, dregs (x));
1016 OUTS (outf, " == ");
1017 OUTS (outf, dregs (y));
1018 }
1019 else if (opc == 1 && I == 0 && G == 0)
1020 {
1021 OUTS (outf, "CC = ");
1022 OUTS (outf, dregs (x));
1023 OUTS (outf, " < ");
1024 OUTS (outf, dregs (y));
1025 }
1026 else if (opc == 2 && I == 0 && G == 0)
1027 {
1028 OUTS (outf, "CC = ");
1029 OUTS (outf, dregs (x));
1030 OUTS (outf, " <= ");
1031 OUTS (outf, dregs (y));
1032 }
1033 else if (opc == 3 && I == 0 && G == 0)
1034 {
1035 OUTS (outf, "CC = ");
1036 OUTS (outf, dregs (x));
1037 OUTS (outf, " < ");
1038 OUTS (outf, dregs (y));
1039 OUTS (outf, " (IU)");
1040 }
1041 else if (opc == 4 && I == 0 && G == 0)
1042 {
1043 OUTS (outf, "CC = ");
1044 OUTS (outf, dregs (x));
1045 OUTS (outf, " <= ");
1046 OUTS (outf, dregs (y));
1047 OUTS (outf, " (IU)");
1048 }
1049 else if (opc == 0 && I == 1 && G == 0)
1050 {
1051 OUTS (outf, "CC = ");
1052 OUTS (outf, dregs (x));
1053 OUTS (outf, " == ");
1054 OUTS (outf, imm3 (y));
1055 }
1056 else if (opc == 1 && I == 1 && G == 0)
1057 {
1058 OUTS (outf, "CC = ");
1059 OUTS (outf, dregs (x));
1060 OUTS (outf, " < ");
1061 OUTS (outf, imm3 (y));
1062 }
1063 else if (opc == 2 && I == 1 && G == 0)
1064 {
1065 OUTS (outf, "CC = ");
1066 OUTS (outf, dregs (x));
1067 OUTS (outf, " <= ");
1068 OUTS (outf, imm3 (y));
1069 }
1070 else if (opc == 3 && I == 1 && G == 0)
1071 {
1072 OUTS (outf, "CC = ");
1073 OUTS (outf, dregs (x));
1074 OUTS (outf, " < ");
1075 OUTS (outf, uimm3 (y));
1076 OUTS (outf, " (IU)");
1077 }
1078 else if (opc == 4 && I == 1 && G == 0)
1079 {
1080 OUTS (outf, "CC = ");
1081 OUTS (outf, dregs (x));
1082 OUTS (outf, " <= ");
1083 OUTS (outf, uimm3 (y));
1084 OUTS (outf, " (IU)");
1085 }
1086 else if (opc == 0 && I == 0 && G == 1)
1087 {
1088 OUTS (outf, "CC = ");
1089 OUTS (outf, pregs (x));
1090 OUTS (outf, " == ");
1091 OUTS (outf, pregs (y));
1092 }
1093 else if (opc == 1 && I == 0 && G == 1)
1094 {
1095 OUTS (outf, "CC = ");
1096 OUTS (outf, pregs (x));
1097 OUTS (outf, " < ");
1098 OUTS (outf, pregs (y));
1099 }
1100 else if (opc == 2 && I == 0 && G == 1)
1101 {
1102 OUTS (outf, "CC = ");
1103 OUTS (outf, pregs (x));
1104 OUTS (outf, " <= ");
1105 OUTS (outf, pregs (y));
1106 }
1107 else if (opc == 3 && I == 0 && G == 1)
1108 {
1109 OUTS (outf, "CC = ");
1110 OUTS (outf, pregs (x));
1111 OUTS (outf, " < ");
1112 OUTS (outf, pregs (y));
1113 OUTS (outf, " (IU)");
1114 }
1115 else if (opc == 4 && I == 0 && G == 1)
1116 {
1117 OUTS (outf, "CC = ");
1118 OUTS (outf, pregs (x));
1119 OUTS (outf, " <= ");
1120 OUTS (outf, pregs (y));
1121 OUTS (outf, " (IU)");
1122 }
1123 else if (opc == 0 && I == 1 && G == 1)
1124 {
1125 OUTS (outf, "CC = ");
1126 OUTS (outf, pregs (x));
1127 OUTS (outf, " == ");
1128 OUTS (outf, imm3 (y));
1129 }
1130 else if (opc == 1 && I == 1 && G == 1)
1131 {
1132 OUTS (outf, "CC = ");
1133 OUTS (outf, pregs (x));
1134 OUTS (outf, " < ");
1135 OUTS (outf, imm3 (y));
1136 }
1137 else if (opc == 2 && I == 1 && G == 1)
1138 {
1139 OUTS (outf, "CC = ");
1140 OUTS (outf, pregs (x));
1141 OUTS (outf, " <= ");
1142 OUTS (outf, imm3 (y));
1143 }
1144 else if (opc == 3 && I == 1 && G == 1)
1145 {
1146 OUTS (outf, "CC = ");
1147 OUTS (outf, pregs (x));
1148 OUTS (outf, " < ");
1149 OUTS (outf, uimm3 (y));
1150 OUTS (outf, " (IU)");
1151 }
1152 else if (opc == 4 && I == 1 && G == 1)
1153 {
1154 OUTS (outf, "CC = ");
1155 OUTS (outf, pregs (x));
1156 OUTS (outf, " <= ");
1157 OUTS (outf, uimm3 (y));
1158 OUTS (outf, " (IU)");
1159 }
1160 else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
1161 OUTS (outf, "CC = A0 == A1");
1162
1163 else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
1164 OUTS (outf, "CC = A0 < A1");
1165
1166 else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
1167 OUTS (outf, "CC = A0 <= A1");
1168
1169 else
1170 return 0;
1171 return 2;
1172 }
1173
1174 static int
1175 decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1176 {
1177 /* CC2dreg
1178 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1179 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1180 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1181 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1182 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1183
1184 if (parallel)
1185 return 0;
1186
1187 if (op == 0)
1188 {
1189 OUTS (outf, dregs (reg));
1190 OUTS (outf, " = CC");
1191 }
1192 else if (op == 1)
1193 {
1194 OUTS (outf, "CC = ");
1195 OUTS (outf, dregs (reg));
1196 }
1197 else if (op == 3 && reg == 0)
1198 OUTS (outf, "CC = !CC");
1199 else
1200 return 0;
1201
1202 return 2;
1203 }
1204
1205 static int
1206 decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1207 {
1208 /* CC2stat
1209 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1210 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1211 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1212 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1213 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1214 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1215
1216 const char *bitname = statbits (cbit);
1217
1218 if (parallel)
1219 return 0;
1220
1221 if (decode_statbits[cbit] == REG_LASTREG)
1222 {
1223 /* All ASTAT bits except CC may be operated on in hardware, but may
1224 not have a dedicated insn, so still decode "valid" insns. */
1225 static char bitnames[64];
1226 if (cbit != 5)
1227 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1228 else
1229 return 0;
1230
1231 bitname = bitnames;
1232 }
1233
1234 if (op == 0 && D == 0)
1235 {
1236 OUTS (outf, "CC = ");
1237 OUTS (outf, bitname);
1238 }
1239 else if (op == 1 && D == 0)
1240 {
1241 OUTS (outf, "CC |= ");
1242 OUTS (outf, bitname);
1243 }
1244 else if (op == 2 && D == 0)
1245 {
1246 OUTS (outf, "CC &= ");
1247 OUTS (outf, bitname);
1248 }
1249 else if (op == 3 && D == 0)
1250 {
1251 OUTS (outf, "CC ^= ");
1252 OUTS (outf, bitname);
1253 }
1254 else if (op == 0 && D == 1)
1255 {
1256 OUTS (outf, bitname);
1257 OUTS (outf, " = CC");
1258 }
1259 else if (op == 1 && D == 1)
1260 {
1261 OUTS (outf, bitname);
1262 OUTS (outf, " |= CC");
1263 }
1264 else if (op == 2 && D == 1)
1265 {
1266 OUTS (outf, bitname);
1267 OUTS (outf, " &= CC");
1268 }
1269 else if (op == 3 && D == 1)
1270 {
1271 OUTS (outf, bitname);
1272 OUTS (outf, " ^= CC");
1273 }
1274 else
1275 return 0;
1276
1277 return 2;
1278 }
1279
1280 static int
1281 decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1282 {
1283 /* BRCC
1284 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1285 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1286 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1287 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1288 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1289 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1290
1291 if (parallel)
1292 return 0;
1293
1294 if (T == 1 && B == 1)
1295 {
1296 OUTS (outf, "IF CC JUMP 0x");
1297 OUTS (outf, pcrel10 (offset));
1298 OUTS (outf, " (BP)");
1299 }
1300 else if (T == 0 && B == 1)
1301 {
1302 OUTS (outf, "IF !CC JUMP 0x");
1303 OUTS (outf, pcrel10 (offset));
1304 OUTS (outf, " (BP)");
1305 }
1306 else if (T == 1)
1307 {
1308 OUTS (outf, "IF CC JUMP 0x");
1309 OUTS (outf, pcrel10 (offset));
1310 }
1311 else if (T == 0)
1312 {
1313 OUTS (outf, "IF !CC JUMP 0x");
1314 OUTS (outf, pcrel10 (offset));
1315 }
1316 else
1317 return 0;
1318
1319 return 2;
1320 }
1321
1322 static int
1323 decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1324 {
1325 /* UJUMP
1326 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1327 | 0 | 0 | 1 | 0 |.offset........................................|
1328 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1329 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1330
1331 if (parallel)
1332 return 0;
1333
1334 OUTS (outf, "JUMP.S 0x");
1335 OUTS (outf, pcrel12 (offset));
1336 return 2;
1337 }
1338
1339 static int
1340 decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1341 {
1342 /* REGMV
1343 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1344 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1345 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1346 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1347 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1348 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1349 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1350
1351 /* Reserved slots cannot be a src/dst. */
1352 if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1353 goto invalid_move;
1354
1355 /* Standard register moves */
1356 if ((gs < 2) || /* Dregs/Pregs as source */
1357 (gd < 2) || /* Dregs/Pregs as dest */
1358 (gs == 4 && src < 4) || /* Accumulators as source */
1359 (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */
1360 (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */
1361 (gd == 7 && dst == 7)) /* EMUDAT as dest */
1362 goto valid_move;
1363
1364 /* dareg = dareg (IMBL) */
1365 if (gs < 4 && gd < 4)
1366 goto valid_move;
1367
1368 /* USP can be src to sysregs, but not dagregs. */
1369 if ((gs == 7 && src == 0) && (gd >= 4))
1370 goto valid_move;
1371
1372 /* USP can move between genregs (only check Accumulators). */
1373 if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1374 ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1375 goto valid_move;
1376
1377 /* Still here ? Invalid reg pair. */
1378 invalid_move:
1379 return 0;
1380
1381 valid_move:
1382 OUTS (outf, allregs (dst, gd));
1383 OUTS (outf, " = ");
1384 OUTS (outf, allregs (src, gs));
1385 return 2;
1386 }
1387
1388 static int
1389 decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1390 {
1391 /* ALU2op
1392 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1393 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1394 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1395 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1396 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1397 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1398
1399 if (opc == 0)
1400 {
1401 OUTS (outf, dregs (dst));
1402 OUTS (outf, " >>>= ");
1403 OUTS (outf, dregs (src));
1404 }
1405 else if (opc == 1)
1406 {
1407 OUTS (outf, dregs (dst));
1408 OUTS (outf, " >>= ");
1409 OUTS (outf, dregs (src));
1410 }
1411 else if (opc == 2)
1412 {
1413 OUTS (outf, dregs (dst));
1414 OUTS (outf, " <<= ");
1415 OUTS (outf, dregs (src));
1416 }
1417 else if (opc == 3)
1418 {
1419 OUTS (outf, dregs (dst));
1420 OUTS (outf, " *= ");
1421 OUTS (outf, dregs (src));
1422 }
1423 else if (opc == 4)
1424 {
1425 OUTS (outf, dregs (dst));
1426 OUTS (outf, " = (");
1427 OUTS (outf, dregs (dst));
1428 OUTS (outf, " + ");
1429 OUTS (outf, dregs (src));
1430 OUTS (outf, ") << 0x1");
1431 }
1432 else if (opc == 5)
1433 {
1434 OUTS (outf, dregs (dst));
1435 OUTS (outf, " = (");
1436 OUTS (outf, dregs (dst));
1437 OUTS (outf, " + ");
1438 OUTS (outf, dregs (src));
1439 OUTS (outf, ") << 0x2");
1440 }
1441 else if (opc == 8)
1442 {
1443 OUTS (outf, "DIVQ (");
1444 OUTS (outf, dregs (dst));
1445 OUTS (outf, ", ");
1446 OUTS (outf, dregs (src));
1447 OUTS (outf, ")");
1448 }
1449 else if (opc == 9)
1450 {
1451 OUTS (outf, "DIVS (");
1452 OUTS (outf, dregs (dst));
1453 OUTS (outf, ", ");
1454 OUTS (outf, dregs (src));
1455 OUTS (outf, ")");
1456 }
1457 else if (opc == 10)
1458 {
1459 OUTS (outf, dregs (dst));
1460 OUTS (outf, " = ");
1461 OUTS (outf, dregs_lo (src));
1462 OUTS (outf, " (X)");
1463 }
1464 else if (opc == 11)
1465 {
1466 OUTS (outf, dregs (dst));
1467 OUTS (outf, " = ");
1468 OUTS (outf, dregs_lo (src));
1469 OUTS (outf, " (Z)");
1470 }
1471 else if (opc == 12)
1472 {
1473 OUTS (outf, dregs (dst));
1474 OUTS (outf, " = ");
1475 OUTS (outf, dregs_byte (src));
1476 OUTS (outf, " (X)");
1477 }
1478 else if (opc == 13)
1479 {
1480 OUTS (outf, dregs (dst));
1481 OUTS (outf, " = ");
1482 OUTS (outf, dregs_byte (src));
1483 OUTS (outf, " (Z)");
1484 }
1485 else if (opc == 14)
1486 {
1487 OUTS (outf, dregs (dst));
1488 OUTS (outf, " = -");
1489 OUTS (outf, dregs (src));
1490 }
1491 else if (opc == 15)
1492 {
1493 OUTS (outf, dregs (dst));
1494 OUTS (outf, " =~ ");
1495 OUTS (outf, dregs (src));
1496 }
1497 else
1498 return 0;
1499
1500 return 2;
1501 }
1502
1503 static int
1504 decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1505 {
1506 /* PTR2op
1507 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1508 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1509 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1510 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1511 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1512 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1513
1514 if (opc == 0)
1515 {
1516 OUTS (outf, pregs (dst));
1517 OUTS (outf, " -= ");
1518 OUTS (outf, pregs (src));
1519 }
1520 else if (opc == 1)
1521 {
1522 OUTS (outf, pregs (dst));
1523 OUTS (outf, " = ");
1524 OUTS (outf, pregs (src));
1525 OUTS (outf, " << 0x2");
1526 }
1527 else if (opc == 3)
1528 {
1529 OUTS (outf, pregs (dst));
1530 OUTS (outf, " = ");
1531 OUTS (outf, pregs (src));
1532 OUTS (outf, " >> 0x2");
1533 }
1534 else if (opc == 4)
1535 {
1536 OUTS (outf, pregs (dst));
1537 OUTS (outf, " = ");
1538 OUTS (outf, pregs (src));
1539 OUTS (outf, " >> 0x1");
1540 }
1541 else if (opc == 5)
1542 {
1543 OUTS (outf, pregs (dst));
1544 OUTS (outf, " += ");
1545 OUTS (outf, pregs (src));
1546 OUTS (outf, " (BREV)");
1547 }
1548 else if (opc == 6)
1549 {
1550 OUTS (outf, pregs (dst));
1551 OUTS (outf, " = (");
1552 OUTS (outf, pregs (dst));
1553 OUTS (outf, " + ");
1554 OUTS (outf, pregs (src));
1555 OUTS (outf, ") << 0x1");
1556 }
1557 else if (opc == 7)
1558 {
1559 OUTS (outf, pregs (dst));
1560 OUTS (outf, " = (");
1561 OUTS (outf, pregs (dst));
1562 OUTS (outf, " + ");
1563 OUTS (outf, pregs (src));
1564 OUTS (outf, ") << 0x2");
1565 }
1566 else
1567 return 0;
1568
1569 return 2;
1570 }
1571
1572 static int
1573 decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1574 {
1575 /* LOGI2op
1576 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1577 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1578 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1579 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1580 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1581 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1582
1583 if (parallel)
1584 return 0;
1585
1586 if (opc == 0)
1587 {
1588 OUTS (outf, "CC = !BITTST (");
1589 OUTS (outf, dregs (dst));
1590 OUTS (outf, ", ");
1591 OUTS (outf, uimm5 (src));
1592 OUTS (outf, ");\t\t/* bit");
1593 OUTS (outf, imm7d (src));
1594 OUTS (outf, " */");
1595 comment = 1;
1596 }
1597 else if (opc == 1)
1598 {
1599 OUTS (outf, "CC = BITTST (");
1600 OUTS (outf, dregs (dst));
1601 OUTS (outf, ", ");
1602 OUTS (outf, uimm5 (src));
1603 OUTS (outf, ");\t\t/* bit");
1604 OUTS (outf, imm7d (src));
1605 OUTS (outf, " */");
1606 comment = 1;
1607 }
1608 else if (opc == 2)
1609 {
1610 OUTS (outf, "BITSET (");
1611 OUTS (outf, dregs (dst));
1612 OUTS (outf, ", ");
1613 OUTS (outf, uimm5 (src));
1614 OUTS (outf, ");\t\t/* bit");
1615 OUTS (outf, imm7d (src));
1616 OUTS (outf, " */");
1617 comment = 1;
1618 }
1619 else if (opc == 3)
1620 {
1621 OUTS (outf, "BITTGL (");
1622 OUTS (outf, dregs (dst));
1623 OUTS (outf, ", ");
1624 OUTS (outf, uimm5 (src));
1625 OUTS (outf, ");\t\t/* bit");
1626 OUTS (outf, imm7d (src));
1627 OUTS (outf, " */");
1628 comment = 1;
1629 }
1630 else if (opc == 4)
1631 {
1632 OUTS (outf, "BITCLR (");
1633 OUTS (outf, dregs (dst));
1634 OUTS (outf, ", ");
1635 OUTS (outf, uimm5 (src));
1636 OUTS (outf, ");\t\t/* bit");
1637 OUTS (outf, imm7d (src));
1638 OUTS (outf, " */");
1639 comment = 1;
1640 }
1641 else if (opc == 5)
1642 {
1643 OUTS (outf, dregs (dst));
1644 OUTS (outf, " >>>= ");
1645 OUTS (outf, uimm5 (src));
1646 }
1647 else if (opc == 6)
1648 {
1649 OUTS (outf, dregs (dst));
1650 OUTS (outf, " >>= ");
1651 OUTS (outf, uimm5 (src));
1652 }
1653 else if (opc == 7)
1654 {
1655 OUTS (outf, dregs (dst));
1656 OUTS (outf, " <<= ");
1657 OUTS (outf, uimm5 (src));
1658 }
1659 else
1660 return 0;
1661
1662 return 2;
1663 }
1664
1665 static int
1666 decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1667 {
1668 /* COMP3op
1669 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1670 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1671 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1672 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1673 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1674 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1675 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1676
1677 if (opc == 5 && src1 == src0)
1678 {
1679 OUTS (outf, pregs (dst));
1680 OUTS (outf, " = ");
1681 OUTS (outf, pregs (src0));
1682 OUTS (outf, " << 0x1");
1683 }
1684 else if (opc == 1)
1685 {
1686 OUTS (outf, dregs (dst));
1687 OUTS (outf, " = ");
1688 OUTS (outf, dregs (src0));
1689 OUTS (outf, " - ");
1690 OUTS (outf, dregs (src1));
1691 }
1692 else if (opc == 2)
1693 {
1694 OUTS (outf, dregs (dst));
1695 OUTS (outf, " = ");
1696 OUTS (outf, dregs (src0));
1697 OUTS (outf, " & ");
1698 OUTS (outf, dregs (src1));
1699 }
1700 else if (opc == 3)
1701 {
1702 OUTS (outf, dregs (dst));
1703 OUTS (outf, " = ");
1704 OUTS (outf, dregs (src0));
1705 OUTS (outf, " | ");
1706 OUTS (outf, dregs (src1));
1707 }
1708 else if (opc == 4)
1709 {
1710 OUTS (outf, dregs (dst));
1711 OUTS (outf, " = ");
1712 OUTS (outf, dregs (src0));
1713 OUTS (outf, " ^ ");
1714 OUTS (outf, dregs (src1));
1715 }
1716 else if (opc == 5)
1717 {
1718 OUTS (outf, pregs (dst));
1719 OUTS (outf, " = ");
1720 OUTS (outf, pregs (src0));
1721 OUTS (outf, " + ");
1722 OUTS (outf, pregs (src1));
1723 }
1724 else if (opc == 6)
1725 {
1726 OUTS (outf, pregs (dst));
1727 OUTS (outf, " = ");
1728 OUTS (outf, pregs (src0));
1729 OUTS (outf, " + (");
1730 OUTS (outf, pregs (src1));
1731 OUTS (outf, " << 0x1)");
1732 }
1733 else if (opc == 7)
1734 {
1735 OUTS (outf, pregs (dst));
1736 OUTS (outf, " = ");
1737 OUTS (outf, pregs (src0));
1738 OUTS (outf, " + (");
1739 OUTS (outf, pregs (src1));
1740 OUTS (outf, " << 0x2)");
1741 }
1742 else if (opc == 0)
1743 {
1744 OUTS (outf, dregs (dst));
1745 OUTS (outf, " = ");
1746 OUTS (outf, dregs (src0));
1747 OUTS (outf, " + ");
1748 OUTS (outf, dregs (src1));
1749 }
1750 else
1751 return 0;
1752
1753 return 2;
1754 }
1755
1756 static int
1757 decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1758 {
1759 /* COMPI2opD
1760 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1761 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1762 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1763 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1764 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1765 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1766
1767 bu32 *pval = get_allreg (0, dst);
1768
1769 if (parallel)
1770 return 0;
1771
1772 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1773 to combine them, so it prints out the right values.
1774 Here we keep track of the registers. */
1775 if (op == 0)
1776 {
1777 *pval = imm7_val (src);
1778 if (src & 0x40)
1779 *pval |= 0xFFFFFF80;
1780 else
1781 *pval &= 0x7F;
1782 }
1783
1784 if (op == 0)
1785 {
1786 OUTS (outf, dregs (dst));
1787 OUTS (outf, " = ");
1788 OUTS (outf, imm7 (src));
1789 OUTS (outf, " (X);\t\t/*\t\t");
1790 OUTS (outf, dregs (dst));
1791 OUTS (outf, "=");
1792 OUTS (outf, uimm32 (*pval));
1793 OUTS (outf, "(");
1794 OUTS (outf, imm32 (*pval));
1795 OUTS (outf, ") */");
1796 comment = 1;
1797 }
1798 else if (op == 1)
1799 {
1800 OUTS (outf, dregs (dst));
1801 OUTS (outf, " += ");
1802 OUTS (outf, imm7 (src));
1803 OUTS (outf, ";\t\t/* (");
1804 OUTS (outf, imm7d (src));
1805 OUTS (outf, ") */");
1806 comment = 1;
1807 }
1808 else
1809 return 0;
1810
1811 return 2;
1812 }
1813
1814 static int
1815 decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1816 {
1817 /* COMPI2opP
1818 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1819 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1820 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1821 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1822 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1823 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1824
1825 bu32 *pval = get_allreg (1, dst);
1826
1827 if (parallel)
1828 return 0;
1829
1830 if (op == 0)
1831 {
1832 *pval = imm7_val (src);
1833 if (src & 0x40)
1834 *pval |= 0xFFFFFF80;
1835 else
1836 *pval &= 0x7F;
1837 }
1838
1839 if (op == 0)
1840 {
1841 OUTS (outf, pregs (dst));
1842 OUTS (outf, " = ");
1843 OUTS (outf, imm7 (src));
1844 OUTS (outf, " (X);\t\t/*\t\t");
1845 OUTS (outf, pregs (dst));
1846 OUTS (outf, "=");
1847 OUTS (outf, uimm32 (*pval));
1848 OUTS (outf, "(");
1849 OUTS (outf, imm32 (*pval));
1850 OUTS (outf, ") */");
1851 comment = 1;
1852 }
1853 else if (op == 1)
1854 {
1855 OUTS (outf, pregs (dst));
1856 OUTS (outf, " += ");
1857 OUTS (outf, imm7 (src));
1858 OUTS (outf, ";\t\t/* (");
1859 OUTS (outf, imm7d (src));
1860 OUTS (outf, ") */");
1861 comment = 1;
1862 }
1863 else
1864 return 0;
1865
1866 return 2;
1867 }
1868
1869 static int
1870 decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1871 {
1872 /* LDSTpmod
1873 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1874 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1875 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1876 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1877 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1878 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1879 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1880 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1881
1882 if (aop == 1 && W == 0 && idx == ptr)
1883 {
1884 OUTS (outf, dregs_lo (reg));
1885 OUTS (outf, " = W[");
1886 OUTS (outf, pregs (ptr));
1887 OUTS (outf, "]");
1888 }
1889 else if (aop == 2 && W == 0 && idx == ptr)
1890 {
1891 OUTS (outf, dregs_hi (reg));
1892 OUTS (outf, " = W[");
1893 OUTS (outf, pregs (ptr));
1894 OUTS (outf, "]");
1895 }
1896 else if (aop == 1 && W == 1 && idx == ptr)
1897 {
1898 OUTS (outf, "W[");
1899 OUTS (outf, pregs (ptr));
1900 OUTS (outf, "] = ");
1901 OUTS (outf, dregs_lo (reg));
1902 }
1903 else if (aop == 2 && W == 1 && idx == ptr)
1904 {
1905 OUTS (outf, "W[");
1906 OUTS (outf, pregs (ptr));
1907 OUTS (outf, "] = ");
1908 OUTS (outf, dregs_hi (reg));
1909 }
1910 else if (aop == 0 && W == 0)
1911 {
1912 OUTS (outf, dregs (reg));
1913 OUTS (outf, " = [");
1914 OUTS (outf, pregs (ptr));
1915 OUTS (outf, " ++ ");
1916 OUTS (outf, pregs (idx));
1917 OUTS (outf, "]");
1918 }
1919 else if (aop == 1 && W == 0)
1920 {
1921 OUTS (outf, dregs_lo (reg));
1922 OUTS (outf, " = W[");
1923 OUTS (outf, pregs (ptr));
1924 OUTS (outf, " ++ ");
1925 OUTS (outf, pregs (idx));
1926 OUTS (outf, "]");
1927 }
1928 else if (aop == 2 && W == 0)
1929 {
1930 OUTS (outf, dregs_hi (reg));
1931 OUTS (outf, " = W[");
1932 OUTS (outf, pregs (ptr));
1933 OUTS (outf, " ++ ");
1934 OUTS (outf, pregs (idx));
1935 OUTS (outf, "]");
1936 }
1937 else if (aop == 3 && W == 0)
1938 {
1939 OUTS (outf, dregs (reg));
1940 OUTS (outf, " = W[");
1941 OUTS (outf, pregs (ptr));
1942 OUTS (outf, " ++ ");
1943 OUTS (outf, pregs (idx));
1944 OUTS (outf, "] (Z)");
1945 }
1946 else if (aop == 3 && W == 1)
1947 {
1948 OUTS (outf, dregs (reg));
1949 OUTS (outf, " = W[");
1950 OUTS (outf, pregs (ptr));
1951 OUTS (outf, " ++ ");
1952 OUTS (outf, pregs (idx));
1953 OUTS (outf, "] (X)");
1954 }
1955 else if (aop == 0 && W == 1)
1956 {
1957 OUTS (outf, "[");
1958 OUTS (outf, pregs (ptr));
1959 OUTS (outf, " ++ ");
1960 OUTS (outf, pregs (idx));
1961 OUTS (outf, "] = ");
1962 OUTS (outf, dregs (reg));
1963 }
1964 else if (aop == 1 && W == 1)
1965 {
1966 OUTS (outf, "W[");
1967 OUTS (outf, pregs (ptr));
1968 OUTS (outf, " ++ ");
1969 OUTS (outf, pregs (idx));
1970 OUTS (outf, "] = ");
1971 OUTS (outf, dregs_lo (reg));
1972 }
1973 else if (aop == 2 && W == 1)
1974 {
1975 OUTS (outf, "W[");
1976 OUTS (outf, pregs (ptr));
1977 OUTS (outf, " ++ ");
1978 OUTS (outf, pregs (idx));
1979 OUTS (outf, "] = ");
1980 OUTS (outf, dregs_hi (reg));
1981 }
1982 else
1983 return 0;
1984
1985 return 2;
1986 }
1987
1988 static int
1989 decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
1990 {
1991 /* dagMODim
1992 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1993 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1994 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1995 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
1996 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
1997 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
1998 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
1999
2000 if (op == 0 && br == 1)
2001 {
2002 OUTS (outf, iregs (i));
2003 OUTS (outf, " += ");
2004 OUTS (outf, mregs (m));
2005 OUTS (outf, " (BREV)");
2006 }
2007 else if (op == 0)
2008 {
2009 OUTS (outf, iregs (i));
2010 OUTS (outf, " += ");
2011 OUTS (outf, mregs (m));
2012 }
2013 else if (op == 1 && br == 0)
2014 {
2015 OUTS (outf, iregs (i));
2016 OUTS (outf, " -= ");
2017 OUTS (outf, mregs (m));
2018 }
2019 else
2020 return 0;
2021
2022 return 2;
2023 }
2024
2025 static int
2026 decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2027 {
2028 /* dagMODik
2029 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2030 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2031 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2032 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2033 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2034
2035 if (op == 0)
2036 {
2037 OUTS (outf, iregs (i));
2038 OUTS (outf, " += 0x2");
2039 }
2040 else if (op == 1)
2041 {
2042 OUTS (outf, iregs (i));
2043 OUTS (outf, " -= 0x2");
2044 }
2045 else if (op == 2)
2046 {
2047 OUTS (outf, iregs (i));
2048 OUTS (outf, " += 0x4");
2049 }
2050 else if (op == 3)
2051 {
2052 OUTS (outf, iregs (i));
2053 OUTS (outf, " -= 0x4");
2054 }
2055 else
2056 return 0;
2057
2058 if (! parallel)
2059 {
2060 OUTS (outf, ";\t\t/* ( ");
2061 if (op == 0 || op == 1)
2062 OUTS (outf, "2");
2063 else if (op == 2 || op == 3)
2064 OUTS (outf, "4");
2065 OUTS (outf, ") */");
2066 comment = 1;
2067 }
2068
2069 return 2;
2070 }
2071
2072 static int
2073 decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2074 {
2075 /* dspLDST
2076 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2077 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2078 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2079 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2080 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2081 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2082 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2083 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2084
2085 if (aop == 0 && W == 0 && m == 0)
2086 {
2087 OUTS (outf, dregs (reg));
2088 OUTS (outf, " = [");
2089 OUTS (outf, iregs (i));
2090 OUTS (outf, "++]");
2091 }
2092 else if (aop == 0 && W == 0 && m == 1)
2093 {
2094 OUTS (outf, dregs_lo (reg));
2095 OUTS (outf, " = W[");
2096 OUTS (outf, iregs (i));
2097 OUTS (outf, "++]");
2098 }
2099 else if (aop == 0 && W == 0 && m == 2)
2100 {
2101 OUTS (outf, dregs_hi (reg));
2102 OUTS (outf, " = W[");
2103 OUTS (outf, iregs (i));
2104 OUTS (outf, "++]");
2105 }
2106 else if (aop == 1 && W == 0 && m == 0)
2107 {
2108 OUTS (outf, dregs (reg));
2109 OUTS (outf, " = [");
2110 OUTS (outf, iregs (i));
2111 OUTS (outf, "--]");
2112 }
2113 else if (aop == 1 && W == 0 && m == 1)
2114 {
2115 OUTS (outf, dregs_lo (reg));
2116 OUTS (outf, " = W[");
2117 OUTS (outf, iregs (i));
2118 OUTS (outf, "--]");
2119 }
2120 else if (aop == 1 && W == 0 && m == 2)
2121 {
2122 OUTS (outf, dregs_hi (reg));
2123 OUTS (outf, " = W[");
2124 OUTS (outf, iregs (i));
2125 OUTS (outf, "--]");
2126 }
2127 else if (aop == 2 && W == 0 && m == 0)
2128 {
2129 OUTS (outf, dregs (reg));
2130 OUTS (outf, " = [");
2131 OUTS (outf, iregs (i));
2132 OUTS (outf, "]");
2133 }
2134 else if (aop == 2 && W == 0 && m == 1)
2135 {
2136 OUTS (outf, dregs_lo (reg));
2137 OUTS (outf, " = W[");
2138 OUTS (outf, iregs (i));
2139 OUTS (outf, "]");
2140 }
2141 else if (aop == 2 && W == 0 && m == 2)
2142 {
2143 OUTS (outf, dregs_hi (reg));
2144 OUTS (outf, " = W[");
2145 OUTS (outf, iregs (i));
2146 OUTS (outf, "]");
2147 }
2148 else if (aop == 0 && W == 1 && m == 0)
2149 {
2150 OUTS (outf, "[");
2151 OUTS (outf, iregs (i));
2152 OUTS (outf, "++] = ");
2153 OUTS (outf, dregs (reg));
2154 }
2155 else if (aop == 0 && W == 1 && m == 1)
2156 {
2157 OUTS (outf, "W[");
2158 OUTS (outf, iregs (i));
2159 OUTS (outf, "++] = ");
2160 OUTS (outf, dregs_lo (reg));
2161 }
2162 else if (aop == 0 && W == 1 && m == 2)
2163 {
2164 OUTS (outf, "W[");
2165 OUTS (outf, iregs (i));
2166 OUTS (outf, "++] = ");
2167 OUTS (outf, dregs_hi (reg));
2168 }
2169 else if (aop == 1 && W == 1 && m == 0)
2170 {
2171 OUTS (outf, "[");
2172 OUTS (outf, iregs (i));
2173 OUTS (outf, "--] = ");
2174 OUTS (outf, dregs (reg));
2175 }
2176 else if (aop == 1 && W == 1 && m == 1)
2177 {
2178 OUTS (outf, "W[");
2179 OUTS (outf, iregs (i));
2180 OUTS (outf, "--] = ");
2181 OUTS (outf, dregs_lo (reg));
2182 }
2183 else if (aop == 1 && W == 1 && m == 2)
2184 {
2185 OUTS (outf, "W[");
2186 OUTS (outf, iregs (i));
2187 OUTS (outf, "--] = ");
2188 OUTS (outf, dregs_hi (reg));
2189 }
2190 else if (aop == 2 && W == 1 && m == 0)
2191 {
2192 OUTS (outf, "[");
2193 OUTS (outf, iregs (i));
2194 OUTS (outf, "] = ");
2195 OUTS (outf, dregs (reg));
2196 }
2197 else if (aop == 2 && W == 1 && m == 1)
2198 {
2199 OUTS (outf, "W[");
2200 OUTS (outf, iregs (i));
2201 OUTS (outf, "] = ");
2202 OUTS (outf, dregs_lo (reg));
2203 }
2204 else if (aop == 2 && W == 1 && m == 2)
2205 {
2206 OUTS (outf, "W[");
2207 OUTS (outf, iregs (i));
2208 OUTS (outf, "] = ");
2209 OUTS (outf, dregs_hi (reg));
2210 }
2211 else if (aop == 3 && W == 0)
2212 {
2213 OUTS (outf, dregs (reg));
2214 OUTS (outf, " = [");
2215 OUTS (outf, iregs (i));
2216 OUTS (outf, " ++ ");
2217 OUTS (outf, mregs (m));
2218 OUTS (outf, "]");
2219 }
2220 else if (aop == 3 && W == 1)
2221 {
2222 OUTS (outf, "[");
2223 OUTS (outf, iregs (i));
2224 OUTS (outf, " ++ ");
2225 OUTS (outf, mregs (m));
2226 OUTS (outf, "] = ");
2227 OUTS (outf, dregs (reg));
2228 }
2229 else
2230 return 0;
2231
2232 return 2;
2233 }
2234
2235 static int
2236 decode_LDST_0 (TIword iw0, disassemble_info *outf)
2237 {
2238 /* LDST
2239 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2240 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2241 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2242 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2243 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2244 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2245 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2246 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2247 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2248
2249 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2250 {
2251 OUTS (outf, dregs (reg));
2252 OUTS (outf, " = [");
2253 OUTS (outf, pregs (ptr));
2254 OUTS (outf, "++]");
2255 }
2256 else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2257 {
2258 OUTS (outf, pregs (reg));
2259 OUTS (outf, " = [");
2260 OUTS (outf, pregs (ptr));
2261 OUTS (outf, "++]");
2262 }
2263 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2264 {
2265 OUTS (outf, dregs (reg));
2266 OUTS (outf, " = W[");
2267 OUTS (outf, pregs (ptr));
2268 OUTS (outf, "++] (Z)");
2269 }
2270 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2271 {
2272 OUTS (outf, dregs (reg));
2273 OUTS (outf, " = W[");
2274 OUTS (outf, pregs (ptr));
2275 OUTS (outf, "++] (X)");
2276 }
2277 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2278 {
2279 OUTS (outf, dregs (reg));
2280 OUTS (outf, " = B[");
2281 OUTS (outf, pregs (ptr));
2282 OUTS (outf, "++] (Z)");
2283 }
2284 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2285 {
2286 OUTS (outf, dregs (reg));
2287 OUTS (outf, " = B[");
2288 OUTS (outf, pregs (ptr));
2289 OUTS (outf, "++] (X)");
2290 }
2291 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2292 {
2293 OUTS (outf, dregs (reg));
2294 OUTS (outf, " = [");
2295 OUTS (outf, pregs (ptr));
2296 OUTS (outf, "--]");
2297 }
2298 else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2299 {
2300 OUTS (outf, pregs (reg));
2301 OUTS (outf, " = [");
2302 OUTS (outf, pregs (ptr));
2303 OUTS (outf, "--]");
2304 }
2305 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2306 {
2307 OUTS (outf, dregs (reg));
2308 OUTS (outf, " = W[");
2309 OUTS (outf, pregs (ptr));
2310 OUTS (outf, "--] (Z)");
2311 }
2312 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2313 {
2314 OUTS (outf, dregs (reg));
2315 OUTS (outf, " = W[");
2316 OUTS (outf, pregs (ptr));
2317 OUTS (outf, "--] (X)");
2318 }
2319 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2320 {
2321 OUTS (outf, dregs (reg));
2322 OUTS (outf, " = B[");
2323 OUTS (outf, pregs (ptr));
2324 OUTS (outf, "--] (Z)");
2325 }
2326 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2327 {
2328 OUTS (outf, dregs (reg));
2329 OUTS (outf, " = B[");
2330 OUTS (outf, pregs (ptr));
2331 OUTS (outf, "--] (X)");
2332 }
2333 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2334 {
2335 OUTS (outf, dregs (reg));
2336 OUTS (outf, " = [");
2337 OUTS (outf, pregs (ptr));
2338 OUTS (outf, "]");
2339 }
2340 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2341 {
2342 OUTS (outf, pregs (reg));
2343 OUTS (outf, " = [");
2344 OUTS (outf, pregs (ptr));
2345 OUTS (outf, "]");
2346 }
2347 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2348 {
2349 OUTS (outf, dregs (reg));
2350 OUTS (outf, " = W[");
2351 OUTS (outf, pregs (ptr));
2352 OUTS (outf, "] (Z)");
2353 }
2354 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2355 {
2356 OUTS (outf, dregs (reg));
2357 OUTS (outf, " = W[");
2358 OUTS (outf, pregs (ptr));
2359 OUTS (outf, "] (X)");
2360 }
2361 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2362 {
2363 OUTS (outf, dregs (reg));
2364 OUTS (outf, " = B[");
2365 OUTS (outf, pregs (ptr));
2366 OUTS (outf, "] (Z)");
2367 }
2368 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2369 {
2370 OUTS (outf, dregs (reg));
2371 OUTS (outf, " = B[");
2372 OUTS (outf, pregs (ptr));
2373 OUTS (outf, "] (X)");
2374 }
2375 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2376 {
2377 OUTS (outf, "[");
2378 OUTS (outf, pregs (ptr));
2379 OUTS (outf, "++] = ");
2380 OUTS (outf, dregs (reg));
2381 }
2382 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2383 {
2384 OUTS (outf, "[");
2385 OUTS (outf, pregs (ptr));
2386 OUTS (outf, "++] = ");
2387 OUTS (outf, pregs (reg));
2388 }
2389 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2390 {
2391 OUTS (outf, "W[");
2392 OUTS (outf, pregs (ptr));
2393 OUTS (outf, "++] = ");
2394 OUTS (outf, dregs (reg));
2395 }
2396 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2397 {
2398 OUTS (outf, "B[");
2399 OUTS (outf, pregs (ptr));
2400 OUTS (outf, "++] = ");
2401 OUTS (outf, dregs (reg));
2402 }
2403 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2404 {
2405 OUTS (outf, "[");
2406 OUTS (outf, pregs (ptr));
2407 OUTS (outf, "--] = ");
2408 OUTS (outf, dregs (reg));
2409 }
2410 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2411 {
2412 OUTS (outf, "[");
2413 OUTS (outf, pregs (ptr));
2414 OUTS (outf, "--] = ");
2415 OUTS (outf, pregs (reg));
2416 }
2417 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2418 {
2419 OUTS (outf, "W[");
2420 OUTS (outf, pregs (ptr));
2421 OUTS (outf, "--] = ");
2422 OUTS (outf, dregs (reg));
2423 }
2424 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2425 {
2426 OUTS (outf, "B[");
2427 OUTS (outf, pregs (ptr));
2428 OUTS (outf, "--] = ");
2429 OUTS (outf, dregs (reg));
2430 }
2431 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2432 {
2433 OUTS (outf, "[");
2434 OUTS (outf, pregs (ptr));
2435 OUTS (outf, "] = ");
2436 OUTS (outf, dregs (reg));
2437 }
2438 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2439 {
2440 OUTS (outf, "[");
2441 OUTS (outf, pregs (ptr));
2442 OUTS (outf, "] = ");
2443 OUTS (outf, pregs (reg));
2444 }
2445 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2446 {
2447 OUTS (outf, "W[");
2448 OUTS (outf, pregs (ptr));
2449 OUTS (outf, "] = ");
2450 OUTS (outf, dregs (reg));
2451 }
2452 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2453 {
2454 OUTS (outf, "B[");
2455 OUTS (outf, pregs (ptr));
2456 OUTS (outf, "] = ");
2457 OUTS (outf, dregs (reg));
2458 }
2459 else
2460 return 0;
2461
2462 return 2;
2463 }
2464
2465 static int
2466 decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2467 {
2468 /* LDSTiiFP
2469 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2470 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2471 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2472 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2473 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2474 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2475
2476 if (W == 0)
2477 {
2478 OUTS (outf, dpregs (reg));
2479 OUTS (outf, " = [FP ");
2480 OUTS (outf, negimm5s4 (offset));
2481 OUTS (outf, "]");
2482 }
2483 else if (W == 1)
2484 {
2485 OUTS (outf, "[FP ");
2486 OUTS (outf, negimm5s4 (offset));
2487 OUTS (outf, "] = ");
2488 OUTS (outf, dpregs (reg));
2489 }
2490 else
2491 return 0;
2492
2493 return 2;
2494 }
2495
2496 static int
2497 decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2498 {
2499 /* LDSTii
2500 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2501 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2502 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2503 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2504 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2505 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2506 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2507 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2508
2509 if (W == 0 && op == 0)
2510 {
2511 OUTS (outf, dregs (reg));
2512 OUTS (outf, " = [");
2513 OUTS (outf, pregs (ptr));
2514 OUTS (outf, " + ");
2515 OUTS (outf, uimm4s4 (offset));
2516 OUTS (outf, "]");
2517 }
2518 else if (W == 0 && op == 1)
2519 {
2520 OUTS (outf, dregs (reg));
2521 OUTS (outf, " = W[");
2522 OUTS (outf, pregs (ptr));
2523 OUTS (outf, " + ");
2524 OUTS (outf, uimm4s2 (offset));
2525 OUTS (outf, "] (Z)");
2526 }
2527 else if (W == 0 && op == 2)
2528 {
2529 OUTS (outf, dregs (reg));
2530 OUTS (outf, " = W[");
2531 OUTS (outf, pregs (ptr));
2532 OUTS (outf, " + ");
2533 OUTS (outf, uimm4s2 (offset));
2534 OUTS (outf, "] (X)");
2535 }
2536 else if (W == 0 && op == 3)
2537 {
2538 OUTS (outf, pregs (reg));
2539 OUTS (outf, " = [");
2540 OUTS (outf, pregs (ptr));
2541 OUTS (outf, " + ");
2542 OUTS (outf, uimm4s4 (offset));
2543 OUTS (outf, "]");
2544 }
2545 else if (W == 1 && op == 0)
2546 {
2547 OUTS (outf, "[");
2548 OUTS (outf, pregs (ptr));
2549 OUTS (outf, " + ");
2550 OUTS (outf, uimm4s4 (offset));
2551 OUTS (outf, "] = ");
2552 OUTS (outf, dregs (reg));
2553 }
2554 else if (W == 1 && op == 1)
2555 {
2556 OUTS (outf, "W[");
2557 OUTS (outf, pregs (ptr));
2558 OUTS (outf, " + ");
2559 OUTS (outf, uimm4s2 (offset));
2560 OUTS (outf, "] = ");
2561 OUTS (outf, dregs (reg));
2562 }
2563 else if (W == 1 && op == 3)
2564 {
2565 OUTS (outf, "[");
2566 OUTS (outf, pregs (ptr));
2567 OUTS (outf, " + ");
2568 OUTS (outf, uimm4s4 (offset));
2569 OUTS (outf, "] = ");
2570 OUTS (outf, pregs (reg));
2571 }
2572 else
2573 return 0;
2574
2575 return 2;
2576 }
2577
2578 static int
2579 decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2580 {
2581 /* LoopSetup
2582 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2583 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2584 |.reg...........| - | - |.eoffset...............................|
2585 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2586 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2587 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2588 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2589 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2590 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2591
2592 if (parallel)
2593 return 0;
2594
2595 if (reg > 7)
2596 return 0;
2597
2598 if (rop == 0)
2599 {
2600 OUTS (outf, "LSETUP");
2601 OUTS (outf, "(0x");
2602 OUTS (outf, pcrel4 (soffset));
2603 OUTS (outf, ", 0x");
2604 OUTS (outf, lppcrel10 (eoffset));
2605 OUTS (outf, ") ");
2606 OUTS (outf, counters (c));
2607 }
2608 else if (rop == 1)
2609 {
2610 OUTS (outf, "LSETUP");
2611 OUTS (outf, "(0x");
2612 OUTS (outf, pcrel4 (soffset));
2613 OUTS (outf, ", 0x");
2614 OUTS (outf, lppcrel10 (eoffset));
2615 OUTS (outf, ") ");
2616 OUTS (outf, counters (c));
2617 OUTS (outf, " = ");
2618 OUTS (outf, pregs (reg));
2619 }
2620 else if (rop == 3)
2621 {
2622 OUTS (outf, "LSETUP");
2623 OUTS (outf, "(0x");
2624 OUTS (outf, pcrel4 (soffset));
2625 OUTS (outf, ", 0x");
2626 OUTS (outf, lppcrel10 (eoffset));
2627 OUTS (outf, ") ");
2628 OUTS (outf, counters (c));
2629 OUTS (outf, " = ");
2630 OUTS (outf, pregs (reg));
2631 OUTS (outf, " >> 0x1");
2632 }
2633 else
2634 return 0;
2635
2636 return 4;
2637 }
2638
2639 static int
2640 decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2641 {
2642 /* LDIMMhalf
2643 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2644 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2645 |.hword.........................................................|
2646 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2647 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2648 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2649 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2650 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2651 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2652 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2653
2654 bu32 *pval = get_allreg (grp, reg);
2655
2656 if (parallel)
2657 return 0;
2658
2659 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2660 to combine them, so it prints out the right values.
2661 Here we keep track of the registers. */
2662 if (H == 0 && S == 1 && Z == 0)
2663 {
2664 /* regs = imm16 (x) */
2665 *pval = imm16_val (hword);
2666 if (hword & 0x8000)
2667 *pval |= 0xFFFF0000;
2668 else
2669 *pval &= 0xFFFF;
2670 }
2671 else if (H == 0 && S == 0 && Z == 1)
2672 {
2673 /* regs = luimm16 (Z) */
2674 *pval = luimm16_val (hword);
2675 *pval &= 0xFFFF;
2676 }
2677 else if (H == 0 && S == 0 && Z == 0)
2678 {
2679 /* regs_lo = luimm16 */
2680 *pval &= 0xFFFF0000;
2681 *pval |= luimm16_val (hword);
2682 }
2683 else if (H == 1 && S == 0 && Z == 0)
2684 {
2685 /* regs_hi = huimm16 */
2686 *pval &= 0xFFFF;
2687 *pval |= luimm16_val (hword) << 16;
2688 }
2689
2690 /* Here we do the disassembly */
2691 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2692 {
2693 OUTS (outf, dregs_lo (reg));
2694 OUTS (outf, " = ");
2695 OUTS (outf, uimm16 (hword));
2696 }
2697 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2698 {
2699 OUTS (outf, dregs_hi (reg));
2700 OUTS (outf, " = ");
2701 OUTS (outf, uimm16 (hword));
2702 }
2703 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2704 {
2705 OUTS (outf, dregs (reg));
2706 OUTS (outf, " = ");
2707 OUTS (outf, imm16 (hword));
2708 OUTS (outf, " (X)");
2709 }
2710 else if (H == 0 && S == 1 && Z == 0)
2711 {
2712 OUTS (outf, regs (reg, grp));
2713 OUTS (outf, " = ");
2714 OUTS (outf, imm16 (hword));
2715 OUTS (outf, " (X)");
2716 }
2717 else if (H == 0 && S == 0 && Z == 1)
2718 {
2719 OUTS (outf, regs (reg, grp));
2720 OUTS (outf, " = ");
2721 OUTS (outf, uimm16 (hword));
2722 OUTS (outf, " (Z)");
2723 }
2724 else if (H == 0 && S == 0 && Z == 0)
2725 {
2726 OUTS (outf, regs_lo (reg, grp));
2727 OUTS (outf, " = ");
2728 OUTS (outf, uimm16 (hword));
2729 }
2730 else if (H == 1 && S == 0 && Z == 0)
2731 {
2732 OUTS (outf, regs_hi (reg, grp));
2733 OUTS (outf, " = ");
2734 OUTS (outf, uimm16 (hword));
2735 }
2736 else
2737 return 0;
2738
2739 /* And we print out the 32-bit value if it is a pointer. */
2740 if (S == 0 && Z == 0)
2741 {
2742 OUTS (outf, ";\t\t/* (");
2743 OUTS (outf, imm16d (hword));
2744 OUTS (outf, ")\t");
2745
2746 /* If it is an MMR, don't print the symbol. */
2747 if (*pval < 0xFFC00000 && grp == 1)
2748 {
2749 OUTS (outf, regs (reg, grp));
2750 OUTS (outf, "=0x");
2751 OUTS (outf, huimm32e (*pval));
2752 }
2753 else
2754 {
2755 OUTS (outf, regs (reg, grp));
2756 OUTS (outf, "=0x");
2757 OUTS (outf, huimm32e (*pval));
2758 OUTS (outf, "(");
2759 OUTS (outf, imm32 (*pval));
2760 OUTS (outf, ")");
2761 }
2762
2763 OUTS (outf, " */");
2764 comment = 1;
2765 }
2766 if (S == 1 || Z == 1)
2767 {
2768 OUTS (outf, ";\t\t/*\t\t");
2769 OUTS (outf, regs (reg, grp));
2770 OUTS (outf, "=0x");
2771 OUTS (outf, huimm32e (*pval));
2772 OUTS (outf, "(");
2773 OUTS (outf, imm32 (*pval));
2774 OUTS (outf, ") */");
2775 comment = 1;
2776 }
2777 return 4;
2778 }
2779
2780 static int
2781 decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2782 {
2783 /* CALLa
2784 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2785 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2786 |.lsw...........................................................|
2787 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2788 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2789 int lsw = ((iw1 >> 0) & 0xffff);
2790 int msw = ((iw0 >> 0) & 0xff);
2791
2792 if (parallel)
2793 return 0;
2794
2795 if (S == 1)
2796 OUTS (outf, "CALL 0x");
2797 else if (S == 0)
2798 OUTS (outf, "JUMP.L 0x");
2799 else
2800 return 0;
2801
2802 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2803 return 4;
2804 }
2805
2806 static int
2807 decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2808 {
2809 /* LDSTidxI
2810 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2811 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2812 |.offset........................................................|
2813 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2814 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2815 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2816 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2817 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2818 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2819 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2820
2821 if (W == 0 && sz == 0 && Z == 0)
2822 {
2823 OUTS (outf, dregs (reg));
2824 OUTS (outf, " = [");
2825 OUTS (outf, pregs (ptr));
2826 OUTS (outf, " + ");
2827 OUTS (outf, imm16s4 (offset));
2828 OUTS (outf, "]");
2829 }
2830 else if (W == 0 && sz == 0 && Z == 1)
2831 {
2832 OUTS (outf, pregs (reg));
2833 OUTS (outf, " = [");
2834 OUTS (outf, pregs (ptr));
2835 OUTS (outf, " + ");
2836 OUTS (outf, imm16s4 (offset));
2837 OUTS (outf, "]");
2838 }
2839 else if (W == 0 && sz == 1 && Z == 0)
2840 {
2841 OUTS (outf, dregs (reg));
2842 OUTS (outf, " = W[");
2843 OUTS (outf, pregs (ptr));
2844 OUTS (outf, " + ");
2845 OUTS (outf, imm16s2 (offset));
2846 OUTS (outf, "] (Z)");
2847 }
2848 else if (W == 0 && sz == 1 && Z == 1)
2849 {
2850 OUTS (outf, dregs (reg));
2851 OUTS (outf, " = W[");
2852 OUTS (outf, pregs (ptr));
2853 OUTS (outf, " + ");
2854 OUTS (outf, imm16s2 (offset));
2855 OUTS (outf, "] (X)");
2856 }
2857 else if (W == 0 && sz == 2 && Z == 0)
2858 {
2859 OUTS (outf, dregs (reg));
2860 OUTS (outf, " = B[");
2861 OUTS (outf, pregs (ptr));
2862 OUTS (outf, " + ");
2863 OUTS (outf, imm16 (offset));
2864 OUTS (outf, "] (Z)");
2865 }
2866 else if (W == 0 && sz == 2 && Z == 1)
2867 {
2868 OUTS (outf, dregs (reg));
2869 OUTS (outf, " = B[");
2870 OUTS (outf, pregs (ptr));
2871 OUTS (outf, " + ");
2872 OUTS (outf, imm16 (offset));
2873 OUTS (outf, "] (X)");
2874 }
2875 else if (W == 1 && sz == 0 && Z == 0)
2876 {
2877 OUTS (outf, "[");
2878 OUTS (outf, pregs (ptr));
2879 OUTS (outf, " + ");
2880 OUTS (outf, imm16s4 (offset));
2881 OUTS (outf, "] = ");
2882 OUTS (outf, dregs (reg));
2883 }
2884 else if (W == 1 && sz == 0 && Z == 1)
2885 {
2886 OUTS (outf, "[");
2887 OUTS (outf, pregs (ptr));
2888 OUTS (outf, " + ");
2889 OUTS (outf, imm16s4 (offset));
2890 OUTS (outf, "] = ");
2891 OUTS (outf, pregs (reg));
2892 }
2893 else if (W == 1 && sz == 1 && Z == 0)
2894 {
2895 OUTS (outf, "W[");
2896 OUTS (outf, pregs (ptr));
2897 OUTS (outf, " + ");
2898 OUTS (outf, imm16s2 (offset));
2899 OUTS (outf, "] = ");
2900 OUTS (outf, dregs (reg));
2901 }
2902 else if (W == 1 && sz == 2 && Z == 0)
2903 {
2904 OUTS (outf, "B[");
2905 OUTS (outf, pregs (ptr));
2906 OUTS (outf, " + ");
2907 OUTS (outf, imm16 (offset));
2908 OUTS (outf, "] = ");
2909 OUTS (outf, dregs (reg));
2910 }
2911 else
2912 return 0;
2913
2914 return 4;
2915 }
2916
2917 static int
2918 decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2919 {
2920 /* linkage
2921 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2922 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2923 |.framesize.....................................................|
2924 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2925 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2926 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2927
2928 if (parallel)
2929 return 0;
2930
2931 if (R == 0)
2932 {
2933 OUTS (outf, "LINK ");
2934 OUTS (outf, uimm16s4 (framesize));
2935 OUTS (outf, ";\t\t/* (");
2936 OUTS (outf, uimm16s4d (framesize));
2937 OUTS (outf, ") */");
2938 comment = 1;
2939 }
2940 else if (R == 1)
2941 OUTS (outf, "UNLINK");
2942 else
2943 return 0;
2944
2945 return 4;
2946 }
2947
2948 static int
2949 decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2950 {
2951 /* dsp32mac
2952 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2953 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2954 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2955 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2956 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2957 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2958 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2959 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2960 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2961 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2962 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2963 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2964 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2965 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2966 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2967 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2968 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2969 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2970
2971 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2972 return 0;
2973
2974 if (op1 == 3 && MM)
2975 return 0;
2976
2977 if ((w1 || w0) && mmod == M_W32)
2978 return 0;
2979
2980 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
2981 return 0;
2982
2983 if (w1 == 1 || op1 != 3)
2984 {
2985 if (w1)
2986 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
2987
2988 if (op1 == 3)
2989 OUTS (outf, " = A1");
2990 else
2991 {
2992 if (w1)
2993 OUTS (outf, " = (");
2994 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
2995 if (w1)
2996 OUTS (outf, ")");
2997 }
2998
2999 if (w0 == 1 || op0 != 3)
3000 {
3001 if (MM)
3002 OUTS (outf, " (M)");
3003 OUTS (outf, ", ");
3004 }
3005 }
3006
3007 if (w0 == 1 || op0 != 3)
3008 {
3009 /* Clear MM option since it only matters for MAC1, and if we made
3010 it this far, we've already shown it or we want to ignore it. */
3011 MM = 0;
3012
3013 if (w0)
3014 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3015
3016 if (op0 == 3)
3017 OUTS (outf, " = A0");
3018 else
3019 {
3020 if (w0)
3021 OUTS (outf, " = (");
3022 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3023 if (w0)
3024 OUTS (outf, ")");
3025 }
3026 }
3027
3028 decode_optmode (mmod, MM, outf);
3029
3030 return 4;
3031 }
3032
3033 static int
3034 decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3035 {
3036 /* dsp32mult
3037 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3038 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3039 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3040 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3041 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3042 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3043 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
3044 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
3045 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
3046 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3047 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
3048 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3049 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3050 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3051 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3052 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3053
3054 if (w1 == 0 && w0 == 0)
3055 return 0;
3056
3057 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3058 return 0;
3059
3060 if (w1)
3061 {
3062 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3063 OUTS (outf, " = ");
3064 decode_multfunc (h01, h11, src0, src1, outf);
3065
3066 if (w0)
3067 {
3068 if (MM)
3069 OUTS (outf, " (M)");
3070 MM = 0;
3071 OUTS (outf, ", ");
3072 }
3073 }
3074
3075 if (w0)
3076 {
3077 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3078 OUTS (outf, " = ");
3079 decode_multfunc (h00, h10, src0, src1, outf);
3080 }
3081
3082 decode_optmode (mmod, MM, outf);
3083 return 4;
3084 }
3085
3086 static int
3087 decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3088 {
3089 /* dsp32alu
3090 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3091 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3092 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3093 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3094 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3095 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3096 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3097 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3098 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3099 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3100 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3101 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3102 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3103
3104 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3105 {
3106 OUTS (outf, "A0.L = ");
3107 OUTS (outf, dregs_lo (src0));
3108 }
3109 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3110 {
3111 OUTS (outf, "A1.H = ");
3112 OUTS (outf, dregs_hi (src0));
3113 }
3114 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3115 {
3116 OUTS (outf, "A1.L = ");
3117 OUTS (outf, dregs_lo (src0));
3118 }
3119 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3120 {
3121 OUTS (outf, "A0.H = ");
3122 OUTS (outf, dregs_hi (src0));
3123 }
3124 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3125 {
3126 OUTS (outf, dregs_hi (dst0));
3127 OUTS (outf, " = ");
3128 OUTS (outf, dregs (src0));
3129 OUTS (outf, " - ");
3130 OUTS (outf, dregs (src1));
3131 OUTS (outf, " (RND20)");
3132 }
3133 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3134 {
3135 OUTS (outf, dregs_hi (dst0));
3136 OUTS (outf, " = ");
3137 OUTS (outf, dregs (src0));
3138 OUTS (outf, " + ");
3139 OUTS (outf, dregs (src1));
3140 OUTS (outf, " (RND20)");
3141 }
3142 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3143 {
3144 OUTS (outf, dregs_lo (dst0));
3145 OUTS (outf, " = ");
3146 OUTS (outf, dregs (src0));
3147 OUTS (outf, " - ");
3148 OUTS (outf, dregs (src1));
3149 OUTS (outf, " (RND12)");
3150 }
3151 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3152 {
3153 OUTS (outf, dregs_lo (dst0));
3154 OUTS (outf, " = ");
3155 OUTS (outf, dregs (src0));
3156 OUTS (outf, " + ");
3157 OUTS (outf, dregs (src1));
3158 OUTS (outf, " (RND12)");
3159 }
3160 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3161 {
3162 OUTS (outf, dregs_lo (dst0));
3163 OUTS (outf, " = ");
3164 OUTS (outf, dregs (src0));
3165 OUTS (outf, " - ");
3166 OUTS (outf, dregs (src1));
3167 OUTS (outf, " (RND20)");
3168 }
3169 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3170 {
3171 OUTS (outf, dregs_hi (dst0));
3172 OUTS (outf, " = ");
3173 OUTS (outf, dregs (src0));
3174 OUTS (outf, " + ");
3175 OUTS (outf, dregs (src1));
3176 OUTS (outf, " (RND12)");
3177 }
3178 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3179 {
3180 OUTS (outf, dregs_lo (dst0));
3181 OUTS (outf, " = ");
3182 OUTS (outf, dregs (src0));
3183 OUTS (outf, " + ");
3184 OUTS (outf, dregs (src1));
3185 OUTS (outf, " (RND20)");
3186 }
3187 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3188 {
3189 OUTS (outf, dregs_hi (dst0));
3190 OUTS (outf, " = ");
3191 OUTS (outf, dregs (src0));
3192 OUTS (outf, " - ");
3193 OUTS (outf, dregs (src1));
3194 OUTS (outf, " (RND12)");
3195 }
3196 else if (HL == 1 && aop == 0 && aopcde == 2)
3197 {
3198 OUTS (outf, dregs_hi (dst0));
3199 OUTS (outf, " = ");
3200 OUTS (outf, dregs_lo (src0));
3201 OUTS (outf, " + ");
3202 OUTS (outf, dregs_lo (src1));
3203 amod1 (s, x, outf);
3204 }
3205 else if (HL == 1 && aop == 1 && aopcde == 2)
3206 {
3207 OUTS (outf, dregs_hi (dst0));
3208 OUTS (outf, " = ");
3209 OUTS (outf, dregs_lo (src0));
3210 OUTS (outf, " + ");
3211 OUTS (outf, dregs_hi (src1));
3212 amod1 (s, x, outf);
3213 }
3214 else if (HL == 1 && aop == 2 && aopcde == 2)
3215 {
3216 OUTS (outf, dregs_hi (dst0));
3217 OUTS (outf, " = ");
3218 OUTS (outf, dregs_hi (src0));
3219 OUTS (outf, " + ");
3220 OUTS (outf, dregs_lo (src1));
3221 amod1 (s, x, outf);
3222 }
3223 else if (HL == 1 && aop == 3 && aopcde == 2)
3224 {
3225 OUTS (outf, dregs_hi (dst0));
3226 OUTS (outf, " = ");
3227 OUTS (outf, dregs_hi (src0));
3228 OUTS (outf, " + ");
3229 OUTS (outf, dregs_hi (src1));
3230 amod1 (s, x, outf);
3231 }
3232 else if (HL == 0 && aop == 0 && aopcde == 3)
3233 {
3234 OUTS (outf, dregs_lo (dst0));
3235 OUTS (outf, " = ");
3236 OUTS (outf, dregs_lo (src0));
3237 OUTS (outf, " - ");
3238 OUTS (outf, dregs_lo (src1));
3239 amod1 (s, x, outf);
3240 }
3241 else if (HL == 0 && aop == 1 && aopcde == 3)
3242 {
3243 OUTS (outf, dregs_lo (dst0));
3244 OUTS (outf, " = ");
3245 OUTS (outf, dregs_lo (src0));
3246 OUTS (outf, " - ");
3247 OUTS (outf, dregs_hi (src1));
3248 amod1 (s, x, outf);
3249 }
3250 else if (HL == 0 && aop == 3 && aopcde == 2)
3251 {
3252 OUTS (outf, dregs_lo (dst0));
3253 OUTS (outf, " = ");
3254 OUTS (outf, dregs_hi (src0));
3255 OUTS (outf, " + ");
3256 OUTS (outf, dregs_hi (src1));
3257 amod1 (s, x, outf);
3258 }
3259 else if (HL == 1 && aop == 0 && aopcde == 3)
3260 {
3261 OUTS (outf, dregs_hi (dst0));
3262 OUTS (outf, " = ");
3263 OUTS (outf, dregs_lo (src0));
3264 OUTS (outf, " - ");
3265 OUTS (outf, dregs_lo (src1));
3266 amod1 (s, x, outf);
3267 }
3268 else if (HL == 1 && aop == 1 && aopcde == 3)
3269 {
3270 OUTS (outf, dregs_hi (dst0));
3271 OUTS (outf, " = ");
3272 OUTS (outf, dregs_lo (src0));
3273 OUTS (outf, " - ");
3274 OUTS (outf, dregs_hi (src1));
3275 amod1 (s, x, outf);
3276 }
3277 else if (HL == 1 && aop == 2 && aopcde == 3)
3278 {
3279 OUTS (outf, dregs_hi (dst0));
3280 OUTS (outf, " = ");
3281 OUTS (outf, dregs_hi (src0));
3282 OUTS (outf, " - ");
3283 OUTS (outf, dregs_lo (src1));
3284 amod1 (s, x, outf);
3285 }
3286 else if (HL == 1 && aop == 3 && aopcde == 3)
3287 {
3288 OUTS (outf, dregs_hi (dst0));
3289 OUTS (outf, " = ");
3290 OUTS (outf, dregs_hi (src0));
3291 OUTS (outf, " - ");
3292 OUTS (outf, dregs_hi (src1));
3293 amod1 (s, x, outf);
3294 }
3295 else if (HL == 0 && aop == 2 && aopcde == 2)
3296 {
3297 OUTS (outf, dregs_lo (dst0));
3298 OUTS (outf, " = ");
3299 OUTS (outf, dregs_hi (src0));
3300 OUTS (outf, " + ");
3301 OUTS (outf, dregs_lo (src1));
3302 amod1 (s, x, outf);
3303 }
3304 else if (HL == 0 && aop == 1 && aopcde == 2)
3305 {
3306 OUTS (outf, dregs_lo (dst0));
3307 OUTS (outf, " = ");
3308 OUTS (outf, dregs_lo (src0));
3309 OUTS (outf, " + ");
3310 OUTS (outf, dregs_hi (src1));
3311 amod1 (s, x, outf);
3312 }
3313 else if (HL == 0 && aop == 2 && aopcde == 3)
3314 {
3315 OUTS (outf, dregs_lo (dst0));
3316 OUTS (outf, " = ");
3317 OUTS (outf, dregs_hi (src0));
3318 OUTS (outf, " - ");
3319 OUTS (outf, dregs_lo (src1));
3320 amod1 (s, x, outf);
3321 }
3322 else if (HL == 0 && aop == 3 && aopcde == 3)
3323 {
3324 OUTS (outf, dregs_lo (dst0));
3325 OUTS (outf, " = ");
3326 OUTS (outf, dregs_hi (src0));
3327 OUTS (outf, " - ");
3328 OUTS (outf, dregs_hi (src1));
3329 amod1 (s, x, outf);
3330 }
3331 else if (HL == 0 && aop == 0 && aopcde == 2)
3332 {
3333 OUTS (outf, dregs_lo (dst0));
3334 OUTS (outf, " = ");
3335 OUTS (outf, dregs_lo (src0));
3336 OUTS (outf, " + ");
3337 OUTS (outf, dregs_lo (src1));
3338 amod1 (s, x, outf);
3339 }
3340 else if (aop == 0 && aopcde == 9 && s == 1)
3341 {
3342 OUTS (outf, "A0 = ");
3343 OUTS (outf, dregs (src0));
3344 }
3345 else if (aop == 3 && aopcde == 11 && s == 0)
3346 OUTS (outf, "A0 -= A1");
3347
3348 else if (aop == 3 && aopcde == 11 && s == 1)
3349 OUTS (outf, "A0 -= A1 (W32)");
3350
3351 else if (aop == 1 && aopcde == 22 && HL == 1)
3352 {
3353 OUTS (outf, dregs (dst0));
3354 OUTS (outf, " = BYTEOP2P (");
3355 OUTS (outf, dregs (src0 + 1));
3356 OUTS (outf, ":");
3357 OUTS (outf, imm5d (src0));
3358 OUTS (outf, ", ");
3359 OUTS (outf, dregs (src1 + 1));
3360 OUTS (outf, ":");
3361 OUTS (outf, imm5d (src1));
3362 OUTS (outf, ") (TH");
3363 if (s == 1)
3364 OUTS (outf, ", R)");
3365 else
3366 OUTS (outf, ")");
3367 }
3368 else if (aop == 1 && aopcde == 22 && HL == 0)
3369 {
3370 OUTS (outf, dregs (dst0));
3371 OUTS (outf, " = BYTEOP2P (");
3372 OUTS (outf, dregs (src0 + 1));
3373 OUTS (outf, ":");
3374 OUTS (outf, imm5d (src0));
3375 OUTS (outf, ", ");
3376 OUTS (outf, dregs (src1 + 1));
3377 OUTS (outf, ":");
3378 OUTS (outf, imm5d (src1));
3379 OUTS (outf, ") (TL");
3380 if (s == 1)
3381 OUTS (outf, ", R)");
3382 else
3383 OUTS (outf, ")");
3384 }
3385 else if (aop == 0 && aopcde == 22 && HL == 1)
3386 {
3387 OUTS (outf, dregs (dst0));
3388 OUTS (outf, " = BYTEOP2P (");
3389 OUTS (outf, dregs (src0 + 1));
3390 OUTS (outf, ":");
3391 OUTS (outf, imm5d (src0));
3392 OUTS (outf, ", ");
3393 OUTS (outf, dregs (src1 + 1));
3394 OUTS (outf, ":");
3395 OUTS (outf, imm5d (src1));
3396 OUTS (outf, ") (RNDH");
3397 if (s == 1)
3398 OUTS (outf, ", R)");
3399 else
3400 OUTS (outf, ")");
3401 }
3402 else if (aop == 0 && aopcde == 22 && HL == 0)
3403 {
3404 OUTS (outf, dregs (dst0));
3405 OUTS (outf, " = BYTEOP2P (");
3406 OUTS (outf, dregs (src0 + 1));
3407 OUTS (outf, ":");
3408 OUTS (outf, imm5d (src0));
3409 OUTS (outf, ", ");
3410 OUTS (outf, dregs (src1 + 1));
3411 OUTS (outf, ":");
3412 OUTS (outf, imm5d (src1));
3413 OUTS (outf, ") (RNDL");
3414 if (s == 1)
3415 OUTS (outf, ", R)");
3416 else
3417 OUTS (outf, ")");
3418 }
3419 else if (aop == 0 && s == 0 && aopcde == 8)
3420 OUTS (outf, "A0 = 0");
3421
3422 else if (aop == 0 && s == 1 && aopcde == 8)
3423 OUTS (outf, "A0 = A0 (S)");
3424
3425 else if (aop == 1 && s == 0 && aopcde == 8)
3426 OUTS (outf, "A1 = 0");
3427
3428 else if (aop == 1 && s == 1 && aopcde == 8)
3429 OUTS (outf, "A1 = A1 (S)");
3430
3431 else if (aop == 2 && s == 0 && aopcde == 8)
3432 OUTS (outf, "A1 = A0 = 0");
3433
3434 else if (aop == 2 && s == 1 && aopcde == 8)
3435 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3436
3437 else if (aop == 3 && s == 0 && aopcde == 8)
3438 OUTS (outf, "A0 = A1");
3439
3440 else if (aop == 3 && s == 1 && aopcde == 8)
3441 OUTS (outf, "A1 = A0");
3442
3443 else if (aop == 1 && aopcde == 9 && s == 0)
3444 {
3445 OUTS (outf, "A0.X = ");
3446 OUTS (outf, dregs_lo (src0));
3447 }
3448 else if (aop == 1 && HL == 0 && aopcde == 11)
3449 {
3450 OUTS (outf, dregs_lo (dst0));
3451 OUTS (outf, " = (A0 += A1)");
3452 }
3453 else if (aop == 3 && HL == 0 && aopcde == 16)
3454 OUTS (outf, "A1 = ABS A1, A0 = ABS A0");
3455
3456 else if (aop == 0 && aopcde == 23 && HL == 1)
3457 {
3458 OUTS (outf, dregs (dst0));
3459 OUTS (outf, " = BYTEOP3P (");
3460 OUTS (outf, dregs (src0 + 1));
3461 OUTS (outf, ":");
3462 OUTS (outf, imm5d (src0));
3463 OUTS (outf, ", ");
3464 OUTS (outf, dregs (src1 + 1));
3465 OUTS (outf, ":");
3466 OUTS (outf, imm5d (src1));
3467 OUTS (outf, ") (HI");
3468 if (s == 1)
3469 OUTS (outf, ", R)");
3470 else
3471 OUTS (outf, ")");
3472 }
3473 else if (aop == 3 && aopcde == 9 && s == 0)
3474 {
3475 OUTS (outf, "A1.X = ");
3476 OUTS (outf, dregs_lo (src0));
3477 }
3478 else if (aop == 1 && HL == 1 && aopcde == 16)
3479 OUTS (outf, "A1 = ABS A1");
3480
3481 else if (aop == 0 && HL == 1 && aopcde == 16)
3482 OUTS (outf, "A1 = ABS A0");
3483
3484 else if (aop == 2 && aopcde == 9 && s == 1)
3485 {
3486 OUTS (outf, "A1 = ");
3487 OUTS (outf, dregs (src0));
3488 }
3489 else if (HL == 0 && aop == 3 && aopcde == 12)
3490 {
3491 OUTS (outf, dregs_lo (dst0));
3492 OUTS (outf, " = ");
3493 OUTS (outf, dregs (src0));
3494 OUTS (outf, " (RND)");
3495 }
3496 else if (aop == 1 && HL == 0 && aopcde == 16)
3497 OUTS (outf, "A0 = ABS A1");
3498
3499 else if (aop == 0 && HL == 0 && aopcde == 16)
3500 OUTS (outf, "A0 = ABS A0");
3501
3502 else if (aop == 3 && HL == 0 && aopcde == 15)
3503 {
3504 OUTS (outf, dregs (dst0));
3505 OUTS (outf, " = -");
3506 OUTS (outf, dregs (src0));
3507 OUTS (outf, " (V)");
3508 }
3509 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3510 {
3511 OUTS (outf, dregs (dst0));
3512 OUTS (outf, " = -");
3513 OUTS (outf, dregs (src0));
3514 OUTS (outf, " (S)");
3515 }
3516 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3517 {
3518 OUTS (outf, dregs (dst0));
3519 OUTS (outf, " = -");
3520 OUTS (outf, dregs (src0));
3521 OUTS (outf, " (NS)");
3522 }
3523 else if (aop == 1 && HL == 1 && aopcde == 11)
3524 {
3525 OUTS (outf, dregs_hi (dst0));
3526 OUTS (outf, " = (A0 += A1)");
3527 }
3528 else if (aop == 2 && aopcde == 11 && s == 0)
3529 OUTS (outf, "A0 += A1");
3530
3531 else if (aop == 2 && aopcde == 11 && s == 1)
3532 OUTS (outf, "A0 += A1 (W32)");
3533
3534 else if (aop == 3 && HL == 0 && aopcde == 14)
3535 OUTS (outf, "A1 = -A1, A0 = -A0");
3536
3537 else if (HL == 1 && aop == 3 && aopcde == 12)
3538 {
3539 OUTS (outf, dregs_hi (dst0));
3540 OUTS (outf, " = ");
3541 OUTS (outf, dregs (src0));
3542 OUTS (outf, " (RND)");
3543 }
3544 else if (aop == 0 && aopcde == 23 && HL == 0)
3545 {
3546 OUTS (outf, dregs (dst0));
3547 OUTS (outf, " = BYTEOP3P (");
3548 OUTS (outf, dregs (src0 + 1));
3549 OUTS (outf, ":");
3550 OUTS (outf, imm5d (src0));
3551 OUTS (outf, ", ");
3552 OUTS (outf, dregs (src1 + 1));
3553 OUTS (outf, ":");
3554 OUTS (outf, imm5d (src1));
3555 OUTS (outf, ") (LO");
3556 if (s == 1)
3557 OUTS (outf, ", R)");
3558 else
3559 OUTS (outf, ")");
3560 }
3561 else if (aop == 0 && HL == 0 && aopcde == 14)
3562 OUTS (outf, "A0 = -A0");
3563
3564 else if (aop == 1 && HL == 0 && aopcde == 14)
3565 OUTS (outf, "A0 = -A1");
3566
3567 else if (aop == 0 && HL == 1 && aopcde == 14)
3568 OUTS (outf, "A1 = -A0");
3569
3570 else if (aop == 1 && HL == 1 && aopcde == 14)
3571 OUTS (outf, "A1 = -A1");
3572
3573 else if (aop == 0 && aopcde == 12)
3574 {
3575 OUTS (outf, dregs_hi (dst0));
3576 OUTS (outf, " = ");
3577 OUTS (outf, dregs_lo (dst0));
3578 OUTS (outf, " = SIGN (");
3579 OUTS (outf, dregs_hi (src0));
3580 OUTS (outf, ") * ");
3581 OUTS (outf, dregs_hi (src1));
3582 OUTS (outf, " + SIGN (");
3583 OUTS (outf, dregs_lo (src0));
3584 OUTS (outf, ") * ");
3585 OUTS (outf, dregs_lo (src1));
3586 }
3587 else if (aop == 2 && aopcde == 0)
3588 {
3589 OUTS (outf, dregs (dst0));
3590 OUTS (outf, " = ");
3591 OUTS (outf, dregs (src0));
3592 OUTS (outf, " -|+ ");
3593 OUTS (outf, dregs (src1));
3594 amod0 (s, x, outf);
3595 }
3596 else if (aop == 1 && aopcde == 12)
3597 {
3598 OUTS (outf, dregs (dst1));
3599 OUTS (outf, " = A1.L + A1.H, ");
3600 OUTS (outf, dregs (dst0));
3601 OUTS (outf, " = A0.L + A0.H");
3602 }
3603 else if (aop == 2 && aopcde == 4)
3604 {
3605 OUTS (outf, dregs (dst1));
3606 OUTS (outf, " = ");
3607 OUTS (outf, dregs (src0));
3608 OUTS (outf, " + ");
3609 OUTS (outf, dregs (src1));
3610 OUTS (outf, ", ");
3611 OUTS (outf, dregs (dst0));
3612 OUTS (outf, " = ");
3613 OUTS (outf, dregs (src0));
3614 OUTS (outf, " - ");
3615 OUTS (outf, dregs (src1));
3616 amod1 (s, x, outf);
3617 }
3618 else if (HL == 0 && aopcde == 1)
3619 {
3620 OUTS (outf, dregs (dst1));
3621 OUTS (outf, " = ");
3622 OUTS (outf, dregs (src0));
3623 OUTS (outf, " +|+ ");
3624 OUTS (outf, dregs (src1));
3625 OUTS (outf, ", ");
3626 OUTS (outf, dregs (dst0));
3627 OUTS (outf, " = ");
3628 OUTS (outf, dregs (src0));
3629 OUTS (outf, " -|- ");
3630 OUTS (outf, dregs (src1));
3631 amod0amod2 (s, x, aop, outf);
3632 }
3633 else if (aop == 0 && aopcde == 11)
3634 {
3635 OUTS (outf, dregs (dst0));
3636 OUTS (outf, " = (A0 += A1)");
3637 }
3638 else if (aop == 0 && aopcde == 10)
3639 {
3640 OUTS (outf, dregs_lo (dst0));
3641 OUTS (outf, " = A0.X");
3642 }
3643 else if (aop == 1 && aopcde == 10)
3644 {
3645 OUTS (outf, dregs_lo (dst0));
3646 OUTS (outf, " = A1.X");
3647 }
3648 else if (aop == 1 && aopcde == 0)
3649 {
3650 OUTS (outf, dregs (dst0));
3651 OUTS (outf, " = ");
3652 OUTS (outf, dregs (src0));
3653 OUTS (outf, " +|- ");
3654 OUTS (outf, dregs (src1));
3655 amod0 (s, x, outf);
3656 }
3657 else if (aop == 3 && aopcde == 0)
3658 {
3659 OUTS (outf, dregs (dst0));
3660 OUTS (outf, " = ");
3661 OUTS (outf, dregs (src0));
3662 OUTS (outf, " -|- ");
3663 OUTS (outf, dregs (src1));
3664 amod0 (s, x, outf);
3665 }
3666 else if (aop == 1 && aopcde == 4)
3667 {
3668 OUTS (outf, dregs (dst0));
3669 OUTS (outf, " = ");
3670 OUTS (outf, dregs (src0));
3671 OUTS (outf, " - ");
3672 OUTS (outf, dregs (src1));
3673 amod1 (s, x, outf);
3674 }
3675 else if (aop == 0 && aopcde == 17)
3676 {
3677 OUTS (outf, dregs (dst1));
3678 OUTS (outf, " = A1 + A0, ");
3679 OUTS (outf, dregs (dst0));
3680 OUTS (outf, " = A1 - A0");
3681 amod1 (s, x, outf);
3682 }
3683 else if (aop == 1 && aopcde == 17)
3684 {
3685 OUTS (outf, dregs (dst1));
3686 OUTS (outf, " = A0 + A1, ");
3687 OUTS (outf, dregs (dst0));
3688 OUTS (outf, " = A0 - A1");
3689 amod1 (s, x, outf);
3690 }
3691 else if (aop == 0 && aopcde == 18)
3692 {
3693 OUTS (outf, "SAA (");
3694 OUTS (outf, dregs (src0 + 1));
3695 OUTS (outf, ":");
3696 OUTS (outf, imm5d (src0));
3697 OUTS (outf, ", ");
3698 OUTS (outf, dregs (src1 + 1));
3699 OUTS (outf, ":");
3700 OUTS (outf, imm5d (src1));
3701 OUTS (outf, ")");
3702 aligndir (s, outf);
3703 }
3704 else if (aop == 3 && aopcde == 18)
3705 OUTS (outf, "DISALGNEXCPT");
3706
3707 else if (aop == 0 && aopcde == 20)
3708 {
3709 OUTS (outf, dregs (dst0));
3710 OUTS (outf, " = BYTEOP1P (");
3711 OUTS (outf, dregs (src0 + 1));
3712 OUTS (outf, ":");
3713 OUTS (outf, imm5d (src0));
3714 OUTS (outf, ", ");
3715 OUTS (outf, dregs (src1 + 1));
3716 OUTS (outf, ":");
3717 OUTS (outf, imm5d (src1));
3718 OUTS (outf, ")");
3719 aligndir (s, outf);
3720 }
3721 else if (aop == 1 && aopcde == 20)
3722 {
3723 OUTS (outf, dregs (dst0));
3724 OUTS (outf, " = BYTEOP1P (");
3725 OUTS (outf, dregs (src0 + 1));
3726 OUTS (outf, ":");
3727 OUTS (outf, imm5d (src0));
3728 OUTS (outf, ", ");
3729 OUTS (outf, dregs (src1 + 1));
3730 OUTS (outf, ":");
3731 OUTS (outf, imm5d (src1));
3732 OUTS (outf, ") (T");
3733 if (s == 1)
3734 OUTS (outf, ", R)");
3735 else
3736 OUTS (outf, ")");
3737 }
3738 else if (aop == 0 && aopcde == 21)
3739 {
3740 OUTS (outf, "(");
3741 OUTS (outf, dregs (dst1));
3742 OUTS (outf, ", ");
3743 OUTS (outf, dregs (dst0));
3744 OUTS (outf, ") = BYTEOP16P (");
3745 OUTS (outf, dregs (src0 + 1));
3746 OUTS (outf, ":");
3747 OUTS (outf, imm5d (src0));
3748 OUTS (outf, ", ");
3749 OUTS (outf, dregs (src1 + 1));
3750 OUTS (outf, ":");
3751 OUTS (outf, imm5d (src1));
3752 OUTS (outf, ")");
3753 aligndir (s, outf);
3754 }
3755 else if (aop == 1 && aopcde == 21)
3756 {
3757 OUTS (outf, "(");
3758 OUTS (outf, dregs (dst1));
3759 OUTS (outf, ", ");
3760 OUTS (outf, dregs (dst0));
3761 OUTS (outf, ") = BYTEOP16M (");
3762 OUTS (outf, dregs (src0 + 1));
3763 OUTS (outf, ":");
3764 OUTS (outf, imm5d (src0));
3765 OUTS (outf, ", ");
3766 OUTS (outf, dregs (src1 + 1));
3767 OUTS (outf, ":");
3768 OUTS (outf, imm5d (src1));
3769 OUTS (outf, ")");
3770 aligndir (s, outf);
3771 }
3772 else if (aop == 2 && aopcde == 7)
3773 {
3774 OUTS (outf, dregs (dst0));
3775 OUTS (outf, " = ABS ");
3776 OUTS (outf, dregs (src0));
3777 }
3778 else if (aop == 1 && aopcde == 7)
3779 {
3780 OUTS (outf, dregs (dst0));
3781 OUTS (outf, " = MIN (");
3782 OUTS (outf, dregs (src0));
3783 OUTS (outf, ", ");
3784 OUTS (outf, dregs (src1));
3785 OUTS (outf, ")");
3786 }
3787 else if (aop == 0 && aopcde == 7)
3788 {
3789 OUTS (outf, dregs (dst0));
3790 OUTS (outf, " = MAX (");
3791 OUTS (outf, dregs (src0));
3792 OUTS (outf, ", ");
3793 OUTS (outf, dregs (src1));
3794 OUTS (outf, ")");
3795 }
3796 else if (aop == 2 && aopcde == 6)
3797 {
3798 OUTS (outf, dregs (dst0));
3799 OUTS (outf, " = ABS ");
3800 OUTS (outf, dregs (src0));
3801 OUTS (outf, " (V)");
3802 }
3803 else if (aop == 1 && aopcde == 6)
3804 {
3805 OUTS (outf, dregs (dst0));
3806 OUTS (outf, " = MIN (");
3807 OUTS (outf, dregs (src0));
3808 OUTS (outf, ", ");
3809 OUTS (outf, dregs (src1));
3810 OUTS (outf, ") (V)");
3811 }
3812 else if (aop == 0 && aopcde == 6)
3813 {
3814 OUTS (outf, dregs (dst0));
3815 OUTS (outf, " = MAX (");
3816 OUTS (outf, dregs (src0));
3817 OUTS (outf, ", ");
3818 OUTS (outf, dregs (src1));
3819 OUTS (outf, ") (V)");
3820 }
3821 else if (HL == 1 && aopcde == 1)
3822 {
3823 OUTS (outf, dregs (dst1));
3824 OUTS (outf, " = ");
3825 OUTS (outf, dregs (src0));
3826 OUTS (outf, " +|- ");
3827 OUTS (outf, dregs (src1));
3828 OUTS (outf, ", ");
3829 OUTS (outf, dregs (dst0));
3830 OUTS (outf, " = ");
3831 OUTS (outf, dregs (src0));
3832 OUTS (outf, " -|+ ");
3833 OUTS (outf, dregs (src1));
3834 amod0amod2 (s, x, aop, outf);
3835 }
3836 else if (aop == 0 && aopcde == 4)
3837 {
3838 OUTS (outf, dregs (dst0));
3839 OUTS (outf, " = ");
3840 OUTS (outf, dregs (src0));
3841 OUTS (outf, " + ");
3842 OUTS (outf, dregs (src1));
3843 amod1 (s, x, outf);
3844 }
3845 else if (aop == 0 && aopcde == 0)
3846 {
3847 OUTS (outf, dregs (dst0));
3848 OUTS (outf, " = ");
3849 OUTS (outf, dregs (src0));
3850 OUTS (outf, " +|+ ");
3851 OUTS (outf, dregs (src1));
3852 amod0 (s, x, outf);
3853 }
3854 else if (aop == 0 && aopcde == 24)
3855 {
3856 OUTS (outf, dregs (dst0));
3857 OUTS (outf, " = BYTEPACK (");
3858 OUTS (outf, dregs (src0));
3859 OUTS (outf, ", ");
3860 OUTS (outf, dregs (src1));
3861 OUTS (outf, ")");
3862 }
3863 else if (aop == 1 && aopcde == 24)
3864 {
3865 OUTS (outf, "(");
3866 OUTS (outf, dregs (dst1));
3867 OUTS (outf, ", ");
3868 OUTS (outf, dregs (dst0));
3869 OUTS (outf, ") = BYTEUNPACK ");
3870 OUTS (outf, dregs (src0 + 1));
3871 OUTS (outf, ":");
3872 OUTS (outf, imm5d (src0));
3873 aligndir (s, outf);
3874 }
3875 else if (aopcde == 13)
3876 {
3877 OUTS (outf, "(");
3878 OUTS (outf, dregs (dst1));
3879 OUTS (outf, ", ");
3880 OUTS (outf, dregs (dst0));
3881 OUTS (outf, ") = SEARCH ");
3882 OUTS (outf, dregs (src0));
3883 OUTS (outf, " (");
3884 searchmod (aop, outf);
3885 OUTS (outf, ")");
3886 }
3887 else
3888 return 0;
3889
3890 return 4;
3891 }
3892
3893 static int
3894 decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3895 {
3896 /* dsp32shift
3897 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3898 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3899 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3900 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3901 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3902 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3903 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3904 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3905 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3906 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3907 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3908
3909 if (HLs == 0 && sop == 0 && sopcde == 0)
3910 {
3911 OUTS (outf, dregs_lo (dst0));
3912 OUTS (outf, " = ASHIFT ");
3913 OUTS (outf, dregs_lo (src1));
3914 OUTS (outf, " BY ");
3915 OUTS (outf, dregs_lo (src0));
3916 }
3917 else if (HLs == 1 && sop == 0 && sopcde == 0)
3918 {
3919 OUTS (outf, dregs_lo (dst0));
3920 OUTS (outf, " = ASHIFT ");
3921 OUTS (outf, dregs_hi (src1));
3922 OUTS (outf, " BY ");
3923 OUTS (outf, dregs_lo (src0));
3924 }
3925 else if (HLs == 2 && sop == 0 && sopcde == 0)
3926 {
3927 OUTS (outf, dregs_hi (dst0));
3928 OUTS (outf, " = ASHIFT ");
3929 OUTS (outf, dregs_lo (src1));
3930 OUTS (outf, " BY ");
3931 OUTS (outf, dregs_lo (src0));
3932 }
3933 else if (HLs == 3 && sop == 0 && sopcde == 0)
3934 {
3935 OUTS (outf, dregs_hi (dst0));
3936 OUTS (outf, " = ASHIFT ");
3937 OUTS (outf, dregs_hi (src1));
3938 OUTS (outf, " BY ");
3939 OUTS (outf, dregs_lo (src0));
3940 }
3941 else if (HLs == 0 && sop == 1 && sopcde == 0)
3942 {
3943 OUTS (outf, dregs_lo (dst0));
3944 OUTS (outf, " = ASHIFT ");
3945 OUTS (outf, dregs_lo (src1));
3946 OUTS (outf, " BY ");
3947 OUTS (outf, dregs_lo (src0));
3948 OUTS (outf, " (S)");
3949 }
3950 else if (HLs == 1 && sop == 1 && sopcde == 0)
3951 {
3952 OUTS (outf, dregs_lo (dst0));
3953 OUTS (outf, " = ASHIFT ");
3954 OUTS (outf, dregs_hi (src1));
3955 OUTS (outf, " BY ");
3956 OUTS (outf, dregs_lo (src0));
3957 OUTS (outf, " (S)");
3958 }
3959 else if (HLs == 2 && sop == 1 && sopcde == 0)
3960 {
3961 OUTS (outf, dregs_hi (dst0));
3962 OUTS (outf, " = ASHIFT ");
3963 OUTS (outf, dregs_lo (src1));
3964 OUTS (outf, " BY ");
3965 OUTS (outf, dregs_lo (src0));
3966 OUTS (outf, " (S)");
3967 }
3968 else if (HLs == 3 && sop == 1 && sopcde == 0)
3969 {
3970 OUTS (outf, dregs_hi (dst0));
3971 OUTS (outf, " = ASHIFT ");
3972 OUTS (outf, dregs_hi (src1));
3973 OUTS (outf, " BY ");
3974 OUTS (outf, dregs_lo (src0));
3975 OUTS (outf, " (S)");
3976 }
3977 else if (sop == 2 && sopcde == 0)
3978 {
3979 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
3980 OUTS (outf, " = LSHIFT ");
3981 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
3982 OUTS (outf, " BY ");
3983 OUTS (outf, dregs_lo (src0));
3984 }
3985 else if (sop == 0 && sopcde == 3)
3986 {
3987 OUTS (outf, acc01);
3988 OUTS (outf, " = ASHIFT ");
3989 OUTS (outf, acc01);
3990 OUTS (outf, " BY ");
3991 OUTS (outf, dregs_lo (src0));
3992 }
3993 else if (sop == 1 && sopcde == 3)
3994 {
3995 OUTS (outf, acc01);
3996 OUTS (outf, " = LSHIFT ");
3997 OUTS (outf, acc01);
3998 OUTS (outf, " BY ");
3999 OUTS (outf, dregs_lo (src0));
4000 }
4001 else if (sop == 2 && sopcde == 3)
4002 {
4003 OUTS (outf, acc01);
4004 OUTS (outf, " = ROT ");
4005 OUTS (outf, acc01);
4006 OUTS (outf, " BY ");
4007 OUTS (outf, dregs_lo (src0));
4008 }
4009 else if (sop == 3 && sopcde == 3)
4010 {
4011 OUTS (outf, dregs (dst0));
4012 OUTS (outf, " = ROT ");
4013 OUTS (outf, dregs (src1));
4014 OUTS (outf, " BY ");
4015 OUTS (outf, dregs_lo (src0));
4016 }
4017 else if (sop == 1 && sopcde == 1)
4018 {
4019 OUTS (outf, dregs (dst0));
4020 OUTS (outf, " = ASHIFT ");
4021 OUTS (outf, dregs (src1));
4022 OUTS (outf, " BY ");
4023 OUTS (outf, dregs_lo (src0));
4024 OUTS (outf, " (V, S)");
4025 }
4026 else if (sop == 0 && sopcde == 1)
4027 {
4028 OUTS (outf, dregs (dst0));
4029 OUTS (outf, " = ASHIFT ");
4030 OUTS (outf, dregs (src1));
4031 OUTS (outf, " BY ");
4032 OUTS (outf, dregs_lo (src0));
4033 OUTS (outf, " (V)");
4034 }
4035 else if (sop == 0 && sopcde == 2)
4036 {
4037 OUTS (outf, dregs (dst0));
4038 OUTS (outf, " = ASHIFT ");
4039 OUTS (outf, dregs (src1));
4040 OUTS (outf, " BY ");
4041 OUTS (outf, dregs_lo (src0));
4042 }
4043 else if (sop == 1 && sopcde == 2)
4044 {
4045 OUTS (outf, dregs (dst0));
4046 OUTS (outf, " = ASHIFT ");
4047 OUTS (outf, dregs (src1));
4048 OUTS (outf, " BY ");
4049 OUTS (outf, dregs_lo (src0));
4050 OUTS (outf, " (S)");
4051 }
4052 else if (sop == 2 && sopcde == 2)
4053 {
4054 OUTS (outf, dregs (dst0));
4055 OUTS (outf, " = LSHIFT ");
4056 OUTS (outf, dregs (src1));
4057 OUTS (outf, " BY ");
4058 OUTS (outf, dregs_lo (src0));
4059 }
4060 else if (sop == 3 && sopcde == 2)
4061 {
4062 OUTS (outf, dregs (dst0));
4063 OUTS (outf, " = ROT ");
4064 OUTS (outf, dregs (src1));
4065 OUTS (outf, " BY ");
4066 OUTS (outf, dregs_lo (src0));
4067 }
4068 else if (sop == 2 && sopcde == 1)
4069 {
4070 OUTS (outf, dregs (dst0));
4071 OUTS (outf, " = LSHIFT ");
4072 OUTS (outf, dregs (src1));
4073 OUTS (outf, " BY ");
4074 OUTS (outf, dregs_lo (src0));
4075 OUTS (outf, " (V)");
4076 }
4077 else if (sop == 0 && sopcde == 4)
4078 {
4079 OUTS (outf, dregs (dst0));
4080 OUTS (outf, " = PACK (");
4081 OUTS (outf, dregs_lo (src1));
4082 OUTS (outf, ", ");
4083 OUTS (outf, dregs_lo (src0));
4084 OUTS (outf, ")");
4085 }
4086 else if (sop == 1 && sopcde == 4)
4087 {
4088 OUTS (outf, dregs (dst0));
4089 OUTS (outf, " = PACK (");
4090 OUTS (outf, dregs_lo (src1));
4091 OUTS (outf, ", ");
4092 OUTS (outf, dregs_hi (src0));
4093 OUTS (outf, ")");
4094 }
4095 else if (sop == 2 && sopcde == 4)
4096 {
4097 OUTS (outf, dregs (dst0));
4098 OUTS (outf, " = PACK (");
4099 OUTS (outf, dregs_hi (src1));
4100 OUTS (outf, ", ");
4101 OUTS (outf, dregs_lo (src0));
4102 OUTS (outf, ")");
4103 }
4104 else if (sop == 3 && sopcde == 4)
4105 {
4106 OUTS (outf, dregs (dst0));
4107 OUTS (outf, " = PACK (");
4108 OUTS (outf, dregs_hi (src1));
4109 OUTS (outf, ", ");
4110 OUTS (outf, dregs_hi (src0));
4111 OUTS (outf, ")");
4112 }
4113 else if (sop == 0 && sopcde == 5)
4114 {
4115 OUTS (outf, dregs_lo (dst0));
4116 OUTS (outf, " = SIGNBITS ");
4117 OUTS (outf, dregs (src1));
4118 }
4119 else if (sop == 1 && sopcde == 5)
4120 {
4121 OUTS (outf, dregs_lo (dst0));
4122 OUTS (outf, " = SIGNBITS ");
4123 OUTS (outf, dregs_lo (src1));
4124 }
4125 else if (sop == 2 && sopcde == 5)
4126 {
4127 OUTS (outf, dregs_lo (dst0));
4128 OUTS (outf, " = SIGNBITS ");
4129 OUTS (outf, dregs_hi (src1));
4130 }
4131 else if (sop == 0 && sopcde == 6)
4132 {
4133 OUTS (outf, dregs_lo (dst0));
4134 OUTS (outf, " = SIGNBITS A0");
4135 }
4136 else if (sop == 1 && sopcde == 6)
4137 {
4138 OUTS (outf, dregs_lo (dst0));
4139 OUTS (outf, " = SIGNBITS A1");
4140 }
4141 else if (sop == 3 && sopcde == 6)
4142 {
4143 OUTS (outf, dregs_lo (dst0));
4144 OUTS (outf, " = ONES ");
4145 OUTS (outf, dregs (src1));
4146 }
4147 else if (sop == 0 && sopcde == 7)
4148 {
4149 OUTS (outf, dregs_lo (dst0));
4150 OUTS (outf, " = EXPADJ (");
4151 OUTS (outf, dregs (src1));
4152 OUTS (outf, ", ");
4153 OUTS (outf, dregs_lo (src0));
4154 OUTS (outf, ")");
4155 }
4156 else if (sop == 1 && sopcde == 7)
4157 {
4158 OUTS (outf, dregs_lo (dst0));
4159 OUTS (outf, " = EXPADJ (");
4160 OUTS (outf, dregs (src1));
4161 OUTS (outf, ", ");
4162 OUTS (outf, dregs_lo (src0));
4163 OUTS (outf, ") (V)");
4164 }
4165 else if (sop == 2 && sopcde == 7)
4166 {
4167 OUTS (outf, dregs_lo (dst0));
4168 OUTS (outf, " = EXPADJ (");
4169 OUTS (outf, dregs_lo (src1));
4170 OUTS (outf, ", ");
4171 OUTS (outf, dregs_lo (src0));
4172 OUTS (outf, ")");
4173 }
4174 else if (sop == 3 && sopcde == 7)
4175 {
4176 OUTS (outf, dregs_lo (dst0));
4177 OUTS (outf, " = EXPADJ (");
4178 OUTS (outf, dregs_hi (src1));
4179 OUTS (outf, ", ");
4180 OUTS (outf, dregs_lo (src0));
4181 OUTS (outf, ")");
4182 }
4183 else if (sop == 0 && sopcde == 8)
4184 {
4185 OUTS (outf, "BITMUX (");
4186 OUTS (outf, dregs (src0));
4187 OUTS (outf, ", ");
4188 OUTS (outf, dregs (src1));
4189 OUTS (outf, ", A0) (ASR)");
4190 }
4191 else if (sop == 1 && sopcde == 8)
4192 {
4193 OUTS (outf, "BITMUX (");
4194 OUTS (outf, dregs (src0));
4195 OUTS (outf, ", ");
4196 OUTS (outf, dregs (src1));
4197 OUTS (outf, ", A0) (ASL)");
4198 }
4199 else if (sop == 0 && sopcde == 9)
4200 {
4201 OUTS (outf, dregs_lo (dst0));
4202 OUTS (outf, " = VIT_MAX (");
4203 OUTS (outf, dregs (src1));
4204 OUTS (outf, ") (ASL)");
4205 }
4206 else if (sop == 1 && sopcde == 9)
4207 {
4208 OUTS (outf, dregs_lo (dst0));
4209 OUTS (outf, " = VIT_MAX (");
4210 OUTS (outf, dregs (src1));
4211 OUTS (outf, ") (ASR)");
4212 }
4213 else if (sop == 2 && sopcde == 9)
4214 {
4215 OUTS (outf, dregs (dst0));
4216 OUTS (outf, " = VIT_MAX (");
4217 OUTS (outf, dregs (src1));
4218 OUTS (outf, ", ");
4219 OUTS (outf, dregs (src0));
4220 OUTS (outf, ") (ASL)");
4221 }
4222 else if (sop == 3 && sopcde == 9)
4223 {
4224 OUTS (outf, dregs (dst0));
4225 OUTS (outf, " = VIT_MAX (");
4226 OUTS (outf, dregs (src1));
4227 OUTS (outf, ", ");
4228 OUTS (outf, dregs (src0));
4229 OUTS (outf, ") (ASR)");
4230 }
4231 else if (sop == 0 && sopcde == 10)
4232 {
4233 OUTS (outf, dregs (dst0));
4234 OUTS (outf, " = EXTRACT (");
4235 OUTS (outf, dregs (src1));
4236 OUTS (outf, ", ");
4237 OUTS (outf, dregs_lo (src0));
4238 OUTS (outf, ") (Z)");
4239 }
4240 else if (sop == 1 && sopcde == 10)
4241 {
4242 OUTS (outf, dregs (dst0));
4243 OUTS (outf, " = EXTRACT (");
4244 OUTS (outf, dregs (src1));
4245 OUTS (outf, ", ");
4246 OUTS (outf, dregs_lo (src0));
4247 OUTS (outf, ") (X)");
4248 }
4249 else if (sop == 2 && sopcde == 10)
4250 {
4251 OUTS (outf, dregs (dst0));
4252 OUTS (outf, " = DEPOSIT (");
4253 OUTS (outf, dregs (src1));
4254 OUTS (outf, ", ");
4255 OUTS (outf, dregs (src0));
4256 OUTS (outf, ")");
4257 }
4258 else if (sop == 3 && sopcde == 10)
4259 {
4260 OUTS (outf, dregs (dst0));
4261 OUTS (outf, " = DEPOSIT (");
4262 OUTS (outf, dregs (src1));
4263 OUTS (outf, ", ");
4264 OUTS (outf, dregs (src0));
4265 OUTS (outf, ") (X)");
4266 }
4267 else if (sop == 0 && sopcde == 11)
4268 {
4269 OUTS (outf, dregs_lo (dst0));
4270 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4271 OUTS (outf, dregs (src0));
4272 OUTS (outf, ")");
4273 }
4274 else if (sop == 1 && sopcde == 11)
4275 {
4276 OUTS (outf, dregs_lo (dst0));
4277 OUTS (outf, " = CC = BXOR (A0, ");
4278 OUTS (outf, dregs (src0));
4279 OUTS (outf, ")");
4280 }
4281 else if (sop == 0 && sopcde == 12)
4282 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4283
4284 else if (sop == 1 && sopcde == 12)
4285 {
4286 OUTS (outf, dregs_lo (dst0));
4287 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4288 }
4289 else if (sop == 0 && sopcde == 13)
4290 {
4291 OUTS (outf, dregs (dst0));
4292 OUTS (outf, " = ALIGN8 (");
4293 OUTS (outf, dregs (src1));
4294 OUTS (outf, ", ");
4295 OUTS (outf, dregs (src0));
4296 OUTS (outf, ")");
4297 }
4298 else if (sop == 1 && sopcde == 13)
4299 {
4300 OUTS (outf, dregs (dst0));
4301 OUTS (outf, " = ALIGN16 (");
4302 OUTS (outf, dregs (src1));
4303 OUTS (outf, ", ");
4304 OUTS (outf, dregs (src0));
4305 OUTS (outf, ")");
4306 }
4307 else if (sop == 2 && sopcde == 13)
4308 {
4309 OUTS (outf, dregs (dst0));
4310 OUTS (outf, " = ALIGN24 (");
4311 OUTS (outf, dregs (src1));
4312 OUTS (outf, ", ");
4313 OUTS (outf, dregs (src0));
4314 OUTS (outf, ")");
4315 }
4316 else
4317 return 0;
4318
4319 return 4;
4320 }
4321
4322 static int
4323 decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4324 {
4325 /* dsp32shiftimm
4326 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4327 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4328 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4329 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4330 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4331 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4332 int bit8 = ((iw1 >> 8) & 0x1);
4333 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4334 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4335 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4336 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4337 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4338
4339 if (sop == 0 && sopcde == 0)
4340 {
4341 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4342 OUTS (outf, " = ");
4343 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4344 OUTS (outf, " >>> ");
4345 OUTS (outf, uimm4 (newimmag));
4346 }
4347 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4348 {
4349 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4350 OUTS (outf, " = ");
4351 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4352 OUTS (outf, " << ");
4353 OUTS (outf, uimm4 (immag));
4354 OUTS (outf, " (S)");
4355 }
4356 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4357 {
4358 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4359 OUTS (outf, " = ");
4360 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4361 OUTS (outf, " >>> ");
4362 OUTS (outf, uimm4 (newimmag));
4363 OUTS (outf, " (S)");
4364 }
4365 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4366 {
4367 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4368 OUTS (outf, " = ");
4369 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4370 OUTS (outf, " << ");
4371 OUTS (outf, uimm4 (immag));
4372 }
4373 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4374 {
4375 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4376 OUTS (outf, " = ");
4377 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4378 OUTS (outf, " >> ");
4379 OUTS (outf, uimm4 (newimmag));
4380 }
4381 else if (sop == 2 && sopcde == 3 && HLs == 1)
4382 {
4383 OUTS (outf, "A1 = ROT A1 BY ");
4384 OUTS (outf, imm6 (immag));
4385 }
4386 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4387 {
4388 OUTS (outf, "A0 = A0 << ");
4389 OUTS (outf, uimm5 (immag));
4390 }
4391 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4392 {
4393 OUTS (outf, "A0 = A0 >>> ");
4394 OUTS (outf, uimm5 (newimmag));
4395 }
4396 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4397 {
4398 OUTS (outf, "A1 = A1 << ");
4399 OUTS (outf, uimm5 (immag));
4400 }
4401 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4402 {
4403 OUTS (outf, "A1 = A1 >>> ");
4404 OUTS (outf, uimm5 (newimmag));
4405 }
4406 else if (sop == 1 && sopcde == 3 && HLs == 0)
4407 {
4408 OUTS (outf, "A0 = A0 >> ");
4409 OUTS (outf, uimm5 (newimmag));
4410 }
4411 else if (sop == 1 && sopcde == 3 && HLs == 1)
4412 {
4413 OUTS (outf, "A1 = A1 >> ");
4414 OUTS (outf, uimm5 (newimmag));
4415 }
4416 else if (sop == 2 && sopcde == 3 && HLs == 0)
4417 {
4418 OUTS (outf, "A0 = ROT A0 BY ");
4419 OUTS (outf, imm6 (immag));
4420 }
4421 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4422 {
4423 OUTS (outf, dregs (dst0));
4424 OUTS (outf, " = ");
4425 OUTS (outf, dregs (src1));
4426 OUTS (outf, " << ");
4427 OUTS (outf, uimm5 (immag));
4428 OUTS (outf, " (V, S)");
4429 }
4430 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4431 {
4432 OUTS (outf, dregs (dst0));
4433 OUTS (outf, " = ");
4434 OUTS (outf, dregs (src1));
4435 OUTS (outf, " >>> ");
4436 OUTS (outf, imm5 (-immag));
4437 OUTS (outf, " (V, S)");
4438 }
4439 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4440 {
4441 OUTS (outf, dregs (dst0));
4442 OUTS (outf, " = ");
4443 OUTS (outf, dregs (src1));
4444 OUTS (outf, " >> ");
4445 OUTS (outf, uimm5 (newimmag));
4446 OUTS (outf, " (V)");
4447 }
4448 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4449 {
4450 OUTS (outf, dregs (dst0));
4451 OUTS (outf, " = ");
4452 OUTS (outf, dregs (src1));
4453 OUTS (outf, " << ");
4454 OUTS (outf, imm5 (immag));
4455 OUTS (outf, " (V)");
4456 }
4457 else if (sop == 0 && sopcde == 1)
4458 {
4459 OUTS (outf, dregs (dst0));
4460 OUTS (outf, " = ");
4461 OUTS (outf, dregs (src1));
4462 OUTS (outf, " >>> ");
4463 OUTS (outf, uimm5 (newimmag));
4464 OUTS (outf, " (V)");
4465 }
4466 else if (sop == 1 && sopcde == 2)
4467 {
4468 OUTS (outf, dregs (dst0));
4469 OUTS (outf, " = ");
4470 OUTS (outf, dregs (src1));
4471 OUTS (outf, " << ");
4472 OUTS (outf, uimm5 (immag));
4473 OUTS (outf, " (S)");
4474 }
4475 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4476 {
4477 OUTS (outf, dregs (dst0));
4478 OUTS (outf, " = ");
4479 OUTS (outf, dregs (src1));
4480 OUTS (outf, " >> ");
4481 OUTS (outf, uimm5 (newimmag));
4482 }
4483 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4484 {
4485 OUTS (outf, dregs (dst0));
4486 OUTS (outf, " = ");
4487 OUTS (outf, dregs (src1));
4488 OUTS (outf, " << ");
4489 OUTS (outf, uimm5 (immag));
4490 }
4491 else if (sop == 3 && sopcde == 2)
4492 {
4493 OUTS (outf, dregs (dst0));
4494 OUTS (outf, " = ROT ");
4495 OUTS (outf, dregs (src1));
4496 OUTS (outf, " BY ");
4497 OUTS (outf, imm6 (immag));
4498 }
4499 else if (sop == 0 && sopcde == 2)
4500 {
4501 OUTS (outf, dregs (dst0));
4502 OUTS (outf, " = ");
4503 OUTS (outf, dregs (src1));
4504 OUTS (outf, " >>> ");
4505 OUTS (outf, uimm5 (newimmag));
4506 }
4507 else
4508 return 0;
4509
4510 return 4;
4511 }
4512
4513 static int
4514 decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4515 {
4516 /* pseudoDEBUG
4517 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4518 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4519 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4520 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4521 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4522 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4523
4524 if (parallel)
4525 return 0;
4526
4527 if (reg == 0 && fn == 3)
4528 OUTS (outf, "DBG A0");
4529
4530 else if (reg == 1 && fn == 3)
4531 OUTS (outf, "DBG A1");
4532
4533 else if (reg == 3 && fn == 3)
4534 OUTS (outf, "ABORT");
4535
4536 else if (reg == 4 && fn == 3)
4537 OUTS (outf, "HLT");
4538
4539 else if (reg == 5 && fn == 3)
4540 OUTS (outf, "DBGHALT");
4541
4542 else if (reg == 6 && fn == 3)
4543 {
4544 OUTS (outf, "DBGCMPLX (");
4545 OUTS (outf, dregs (grp));
4546 OUTS (outf, ")");
4547 }
4548 else if (reg == 7 && fn == 3)
4549 OUTS (outf, "DBG");
4550
4551 else if (grp == 0 && fn == 2)
4552 {
4553 OUTS (outf, "OUTC ");
4554 OUTS (outf, dregs (reg));
4555 }
4556 else if (fn == 0)
4557 {
4558 OUTS (outf, "DBG ");
4559 OUTS (outf, allregs (reg, grp));
4560 }
4561 else if (fn == 1)
4562 {
4563 OUTS (outf, "PRNT ");
4564 OUTS (outf, allregs (reg, grp));
4565 }
4566 else
4567 return 0;
4568
4569 return 2;
4570 }
4571
4572 static int
4573 decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4574 {
4575 /* psedoOChar
4576 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4577 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4578 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4579 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4580
4581 if (parallel)
4582 return 0;
4583
4584 OUTS (outf, "OUTC ");
4585 OUTS (outf, uimm8 (ch));
4586
4587 return 2;
4588 }
4589
4590 static int
4591 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4592 {
4593 /* pseudodbg_assert
4594 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4595 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4596 |.expected......................................................|
4597 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4598 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4599 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4600 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
4601 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4602
4603 if (parallel)
4604 return 0;
4605
4606 if (dbgop == 0)
4607 {
4608 OUTS (outf, "DBGA (");
4609 OUTS (outf, regs_lo (regtest, grp));
4610 OUTS (outf, ", ");
4611 OUTS (outf, uimm16 (expected));
4612 OUTS (outf, ")");
4613 }
4614 else if (dbgop == 1)
4615 {
4616 OUTS (outf, "DBGA (");
4617 OUTS (outf, regs_hi (regtest, grp));
4618 OUTS (outf, ", ");
4619 OUTS (outf, uimm16 (expected));
4620 OUTS (outf, ")");
4621 }
4622 else if (dbgop == 2)
4623 {
4624 OUTS (outf, "DBGAL (");
4625 OUTS (outf, allregs (regtest, grp));
4626 OUTS (outf, ", ");
4627 OUTS (outf, uimm16 (expected));
4628 OUTS (outf, ")");
4629 }
4630 else if (dbgop == 3)
4631 {
4632 OUTS (outf, "DBGAH (");
4633 OUTS (outf, allregs (regtest, grp));
4634 OUTS (outf, ", ");
4635 OUTS (outf, uimm16 (expected));
4636 OUTS (outf, ")");
4637 }
4638 else
4639 return 0;
4640 return 4;
4641 }
4642
4643 static int
4644 _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4645 {
4646 bfd_byte buf[4];
4647 TIword iw0;
4648 TIword iw1;
4649 int status;
4650 int rv = 0;
4651
4652 status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
4653 /* FIXME */
4654 (void) status;
4655 status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
4656 /* FIXME */
4657 (void) status;
4658
4659 iw0 = bfd_getl16 (buf);
4660 iw1 = bfd_getl16 (buf + 2);
4661
4662 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4663 {
4664 if (parallel)
4665 {
4666 OUTS (outf, "ILLEGAL");
4667 return 0;
4668 }
4669 OUTS (outf, "MNOP");
4670 return 4;
4671 }
4672 else if ((iw0 & 0xff00) == 0x0000)
4673 rv = decode_ProgCtrl_0 (iw0, outf);
4674 else if ((iw0 & 0xffc0) == 0x0240)
4675 rv = decode_CaCTRL_0 (iw0, outf);
4676 else if ((iw0 & 0xff80) == 0x0100)
4677 rv = decode_PushPopReg_0 (iw0, outf);
4678 else if ((iw0 & 0xfe00) == 0x0400)
4679 rv = decode_PushPopMultiple_0 (iw0, outf);
4680 else if ((iw0 & 0xfe00) == 0x0600)
4681 rv = decode_ccMV_0 (iw0, outf);
4682 else if ((iw0 & 0xf800) == 0x0800)
4683 rv = decode_CCflag_0 (iw0, outf);
4684 else if ((iw0 & 0xffe0) == 0x0200)
4685 rv = decode_CC2dreg_0 (iw0, outf);
4686 else if ((iw0 & 0xff00) == 0x0300)
4687 rv = decode_CC2stat_0 (iw0, outf);
4688 else if ((iw0 & 0xf000) == 0x1000)
4689 rv = decode_BRCC_0 (iw0, pc, outf);
4690 else if ((iw0 & 0xf000) == 0x2000)
4691 rv = decode_UJUMP_0 (iw0, pc, outf);
4692 else if ((iw0 & 0xf000) == 0x3000)
4693 rv = decode_REGMV_0 (iw0, outf);
4694 else if ((iw0 & 0xfc00) == 0x4000)
4695 rv = decode_ALU2op_0 (iw0, outf);
4696 else if ((iw0 & 0xfe00) == 0x4400)
4697 rv = decode_PTR2op_0 (iw0, outf);
4698 else if ((iw0 & 0xf800) == 0x4800)
4699 rv = decode_LOGI2op_0 (iw0, outf);
4700 else if ((iw0 & 0xf000) == 0x5000)
4701 rv = decode_COMP3op_0 (iw0, outf);
4702 else if ((iw0 & 0xf800) == 0x6000)
4703 rv = decode_COMPI2opD_0 (iw0, outf);
4704 else if ((iw0 & 0xf800) == 0x6800)
4705 rv = decode_COMPI2opP_0 (iw0, outf);
4706 else if ((iw0 & 0xf000) == 0x8000)
4707 rv = decode_LDSTpmod_0 (iw0, outf);
4708 else if ((iw0 & 0xff60) == 0x9e60)
4709 rv = decode_dagMODim_0 (iw0, outf);
4710 else if ((iw0 & 0xfff0) == 0x9f60)
4711 rv = decode_dagMODik_0 (iw0, outf);
4712 else if ((iw0 & 0xfc00) == 0x9c00)
4713 rv = decode_dspLDST_0 (iw0, outf);
4714 else if ((iw0 & 0xf000) == 0x9000)
4715 rv = decode_LDST_0 (iw0, outf);
4716 else if ((iw0 & 0xfc00) == 0xb800)
4717 rv = decode_LDSTiiFP_0 (iw0, outf);
4718 else if ((iw0 & 0xe000) == 0xA000)
4719 rv = decode_LDSTii_0 (iw0, outf);
4720 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4721 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4722 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4723 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4724 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4725 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4726 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4727 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4728 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4729 rv = decode_linkage_0 (iw0, iw1, outf);
4730 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4731 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4732 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4733 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4734 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4735 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4736 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4737 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4738 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4739 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4740 else if ((iw0 & 0xff00) == 0xf800)
4741 rv = decode_pseudoDEBUG_0 (iw0, outf);
4742 else if ((iw0 & 0xFF00) == 0xF900)
4743 rv = decode_pseudoOChar_0 (iw0, outf);
4744 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4745 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4746
4747 if (rv == 0)
4748 OUTS (outf, "ILLEGAL");
4749
4750 return rv;
4751 }
4752
4753 int
4754 print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4755 {
4756 bfd_byte buf[2];
4757 unsigned short iw0;
4758 int status;
4759 int count = 0;
4760
4761 status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
4762 /* FIXME */
4763 (void) status;
4764 iw0 = bfd_getl16 (buf);
4765
4766 count += _print_insn_bfin (pc, outf);
4767
4768 /* Proper display of multiple issue instructions. */
4769
4770 if (count == 4 && (iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
4771 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4772 {
4773 int legal = 1;
4774 int len;
4775
4776 parallel = 1;
4777 OUTS (outf, " || ");
4778 len = _print_insn_bfin (pc + 4, outf);
4779 OUTS (outf, " || ");
4780 if (len != 2)
4781 legal = 0;
4782 len = _print_insn_bfin (pc + 6, outf);
4783 if (len != 2)
4784 legal = 0;
4785
4786 if (legal)
4787 count = 8;
4788 else
4789 {
4790 OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
4791 comment = 1;
4792 count = 0;
4793 }
4794 parallel = 0;
4795 }
4796
4797 if (!comment)
4798 OUTS (outf, ";");
4799
4800 if (count == 0)
4801 return 2;
4802
4803 comment = 0;
4804
4805 return count;
4806 }
GDB Binutils - Deliverables
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