1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
2 /* Instruction opcode table for bpf.
4 THIS FILE IS MACHINE GENERATED WITH CGEN.
6 Copyright (C) 1996-2019 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
10 This file is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 It is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License along
21 with this program; if not, write to the Free Software Foundation, Inc.,
22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
32 #include "libiberty.h"
37 /* The hash functions are recorded here to help keep assembler code out of
38 the disassembler and vice versa. */
40 static int asm_hash_insn_p (const CGEN_INSN
*);
41 static unsigned int asm_hash_insn (const char *);
42 static int dis_hash_insn_p (const CGEN_INSN
*);
43 static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT
);
45 /* Instruction formats. */
47 #define F(f) & bpf_cgen_ifld_table[BPF_##f]
48 static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED
= {
52 static const CGEN_IFMT ifmt_addile ATTRIBUTE_UNUSED
= {
53 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_CODE
) }, { F (F_DSTLE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
56 static const CGEN_IFMT ifmt_addrle ATTRIBUTE_UNUSED
= {
57 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_CODE
) }, { F (F_DSTLE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
60 static const CGEN_IFMT ifmt_negle ATTRIBUTE_UNUSED
= {
61 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_CODE
) }, { F (F_DSTLE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
64 static const CGEN_IFMT ifmt_addibe ATTRIBUTE_UNUSED
= {
65 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_CODE
) }, { F (F_SRCBE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
68 static const CGEN_IFMT ifmt_addrbe ATTRIBUTE_UNUSED
= {
69 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_CODE
) }, { F (F_SRCBE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
72 static const CGEN_IFMT ifmt_negbe ATTRIBUTE_UNUSED
= {
73 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_CODE
) }, { F (F_SRCBE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
76 static const CGEN_IFMT ifmt_endlele ATTRIBUTE_UNUSED
= {
77 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_CODE
) }, { F (F_DSTLE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
80 static const CGEN_IFMT ifmt_endlebe ATTRIBUTE_UNUSED
= {
81 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_CODE
) }, { F (F_SRCBE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
84 static const CGEN_IFMT ifmt_lddwle ATTRIBUTE_UNUSED
= {
85 8, 128, 0xff, { { F (F_IMM64
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_MODE
) }, { F (F_OP_SIZE
) }, { F (F_DSTLE
) }, { F (F_OP_CLASS
) }, { 0 } }
88 static const CGEN_IFMT ifmt_lddwbe ATTRIBUTE_UNUSED
= {
89 8, 128, 0xff, { { F (F_IMM64
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_MODE
) }, { F (F_OP_SIZE
) }, { F (F_SRCBE
) }, { F (F_OP_CLASS
) }, { 0 } }
92 static const CGEN_IFMT ifmt_ldabswle ATTRIBUTE_UNUSED
= {
93 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_MODE
) }, { F (F_OP_SIZE
) }, { F (F_DSTLE
) }, { F (F_OP_CLASS
) }, { 0 } }
96 static const CGEN_IFMT ifmt_ldabswbe ATTRIBUTE_UNUSED
= {
97 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_MODE
) }, { F (F_OP_SIZE
) }, { F (F_SRCBE
) }, { F (F_OP_CLASS
) }, { 0 } }
100 static const CGEN_IFMT ifmt_ldxwle ATTRIBUTE_UNUSED
= {
101 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_MODE
) }, { F (F_OP_SIZE
) }, { F (F_DSTLE
) }, { F (F_OP_CLASS
) }, { 0 } }
104 static const CGEN_IFMT ifmt_ldxwbe ATTRIBUTE_UNUSED
= {
105 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_MODE
) }, { F (F_OP_SIZE
) }, { F (F_SRCBE
) }, { F (F_OP_CLASS
) }, { 0 } }
108 static const CGEN_IFMT ifmt_stble ATTRIBUTE_UNUSED
= {
109 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_MODE
) }, { F (F_OP_SIZE
) }, { F (F_DSTLE
) }, { F (F_OP_CLASS
) }, { 0 } }
112 static const CGEN_IFMT ifmt_stbbe ATTRIBUTE_UNUSED
= {
113 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_MODE
) }, { F (F_OP_SIZE
) }, { F (F_SRCBE
) }, { F (F_OP_CLASS
) }, { 0 } }
116 static const CGEN_IFMT ifmt_jeqile ATTRIBUTE_UNUSED
= {
117 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_CODE
) }, { F (F_DSTLE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
120 static const CGEN_IFMT ifmt_jeqrle ATTRIBUTE_UNUSED
= {
121 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_SRCLE
) }, { F (F_OP_CODE
) }, { F (F_DSTLE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
124 static const CGEN_IFMT ifmt_jeqibe ATTRIBUTE_UNUSED
= {
125 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_CODE
) }, { F (F_SRCBE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
128 static const CGEN_IFMT ifmt_jeqrbe ATTRIBUTE_UNUSED
= {
129 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_DSTBE
) }, { F (F_OP_CODE
) }, { F (F_SRCBE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
132 static const CGEN_IFMT ifmt_ja ATTRIBUTE_UNUSED
= {
133 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_REGS
) }, { F (F_OP_CODE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
136 static const CGEN_IFMT ifmt_call ATTRIBUTE_UNUSED
= {
137 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_REGS
) }, { F (F_OP_CODE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
140 static const CGEN_IFMT ifmt_exit ATTRIBUTE_UNUSED
= {
141 8, 64, 0xff, { { F (F_IMM32
) }, { F (F_OFFSET16
) }, { F (F_REGS
) }, { F (F_OP_CODE
) }, { F (F_OP_SRC
) }, { F (F_OP_CLASS
) }, { 0 } }
146 #define A(a) (1 << CGEN_INSN_##a)
147 #define OPERAND(op) BPF_OPERAND_##op
148 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
149 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
151 /* The instruction table. */
153 static const CGEN_OPCODE bpf_cgen_insn_opcode_table
[MAX_INSNS
] =
155 /* Special null first entry.
156 A `num' value of zero is thus invalid.
157 Also, the special `invalid' insn resides here. */
158 { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
159 /* add $dstle,$imm32 */
162 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
163 & ifmt_addile
, { 0x7 }
165 /* add $dstle,$srcle */
168 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
169 & ifmt_addrle
, { 0xf }
171 /* add32 $dstle,$imm32 */
174 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
175 & ifmt_addile
, { 0x4 }
177 /* add32 $dstle,$srcle */
180 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
181 & ifmt_addrle
, { 0xc }
183 /* sub $dstle,$imm32 */
186 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
187 & ifmt_addile
, { 0x17 }
189 /* sub $dstle,$srcle */
192 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
193 & ifmt_addrle
, { 0x1f }
195 /* sub32 $dstle,$imm32 */
198 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
199 & ifmt_addile
, { 0x14 }
201 /* sub32 $dstle,$srcle */
204 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
205 & ifmt_addrle
, { 0x1c }
207 /* mul $dstle,$imm32 */
210 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
211 & ifmt_addile
, { 0x27 }
213 /* mul $dstle,$srcle */
216 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
217 & ifmt_addrle
, { 0x2f }
219 /* mul32 $dstle,$imm32 */
222 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
223 & ifmt_addile
, { 0x24 }
225 /* mul32 $dstle,$srcle */
228 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
229 & ifmt_addrle
, { 0x2c }
231 /* div $dstle,$imm32 */
234 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
235 & ifmt_addile
, { 0x37 }
237 /* div $dstle,$srcle */
240 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
241 & ifmt_addrle
, { 0x3f }
243 /* div32 $dstle,$imm32 */
246 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
247 & ifmt_addile
, { 0x34 }
249 /* div32 $dstle,$srcle */
252 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
253 & ifmt_addrle
, { 0x3c }
255 /* or $dstle,$imm32 */
258 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
259 & ifmt_addile
, { 0x47 }
261 /* or $dstle,$srcle */
264 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
265 & ifmt_addrle
, { 0x4f }
267 /* or32 $dstle,$imm32 */
270 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
271 & ifmt_addile
, { 0x44 }
273 /* or32 $dstle,$srcle */
276 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
277 & ifmt_addrle
, { 0x4c }
279 /* and $dstle,$imm32 */
282 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
283 & ifmt_addile
, { 0x57 }
285 /* and $dstle,$srcle */
288 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
289 & ifmt_addrle
, { 0x5f }
291 /* and32 $dstle,$imm32 */
294 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
295 & ifmt_addile
, { 0x54 }
297 /* and32 $dstle,$srcle */
300 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
301 & ifmt_addrle
, { 0x5c }
303 /* lsh $dstle,$imm32 */
306 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
307 & ifmt_addile
, { 0x67 }
309 /* lsh $dstle,$srcle */
312 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
313 & ifmt_addrle
, { 0x6f }
315 /* lsh32 $dstle,$imm32 */
318 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
319 & ifmt_addile
, { 0x64 }
321 /* lsh32 $dstle,$srcle */
324 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
325 & ifmt_addrle
, { 0x6c }
327 /* rsh $dstle,$imm32 */
330 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
331 & ifmt_addile
, { 0x77 }
333 /* rsh $dstle,$srcle */
336 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
337 & ifmt_addrle
, { 0x7f }
339 /* rsh32 $dstle,$imm32 */
342 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
343 & ifmt_addile
, { 0x74 }
345 /* rsh32 $dstle,$srcle */
348 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
349 & ifmt_addrle
, { 0x7c }
351 /* mod $dstle,$imm32 */
354 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
355 & ifmt_addile
, { 0x97 }
357 /* mod $dstle,$srcle */
360 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
361 & ifmt_addrle
, { 0x9f }
363 /* mod32 $dstle,$imm32 */
366 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
367 & ifmt_addile
, { 0x94 }
369 /* mod32 $dstle,$srcle */
372 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
373 & ifmt_addrle
, { 0x9c }
375 /* xor $dstle,$imm32 */
378 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
379 & ifmt_addile
, { 0xa7 }
381 /* xor $dstle,$srcle */
384 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
385 & ifmt_addrle
, { 0xaf }
387 /* xor32 $dstle,$imm32 */
390 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
391 & ifmt_addile
, { 0xa4 }
393 /* xor32 $dstle,$srcle */
396 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
397 & ifmt_addrle
, { 0xac }
399 /* mov $dstle,$imm32 */
402 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
403 & ifmt_addile
, { 0xb7 }
405 /* mov $dstle,$srcle */
408 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
409 & ifmt_addrle
, { 0xbf }
411 /* mov32 $dstle,$imm32 */
414 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
415 & ifmt_addile
, { 0xb4 }
417 /* mov32 $dstle,$srcle */
420 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
421 & ifmt_addrle
, { 0xbc }
423 /* arsh $dstle,$imm32 */
426 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
427 & ifmt_addile
, { 0xc7 }
429 /* arsh $dstle,$srcle */
432 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
433 & ifmt_addrle
, { 0xcf }
435 /* arsh32 $dstle,$imm32 */
438 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), 0 } },
439 & ifmt_addile
, { 0xc4 }
441 /* arsh32 $dstle,$srcle */
444 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), 0 } },
445 & ifmt_addrle
, { 0xcc }
450 { { MNEM
, ' ', OP (DSTLE
), 0 } },
451 & ifmt_negle
, { 0x8f }
456 { { MNEM
, ' ', OP (DSTLE
), 0 } },
457 & ifmt_negle
, { 0x8c }
459 /* add $dstbe,$imm32 */
462 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
463 & ifmt_addibe
, { 0x7 }
465 /* add $dstbe,$srcbe */
468 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
469 & ifmt_addrbe
, { 0xf }
471 /* add32 $dstbe,$imm32 */
474 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
475 & ifmt_addibe
, { 0x4 }
477 /* add32 $dstbe,$srcbe */
480 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
481 & ifmt_addrbe
, { 0xc }
483 /* sub $dstbe,$imm32 */
486 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
487 & ifmt_addibe
, { 0x17 }
489 /* sub $dstbe,$srcbe */
492 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
493 & ifmt_addrbe
, { 0x1f }
495 /* sub32 $dstbe,$imm32 */
498 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
499 & ifmt_addibe
, { 0x14 }
501 /* sub32 $dstbe,$srcbe */
504 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
505 & ifmt_addrbe
, { 0x1c }
507 /* mul $dstbe,$imm32 */
510 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
511 & ifmt_addibe
, { 0x27 }
513 /* mul $dstbe,$srcbe */
516 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
517 & ifmt_addrbe
, { 0x2f }
519 /* mul32 $dstbe,$imm32 */
522 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
523 & ifmt_addibe
, { 0x24 }
525 /* mul32 $dstbe,$srcbe */
528 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
529 & ifmt_addrbe
, { 0x2c }
531 /* div $dstbe,$imm32 */
534 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
535 & ifmt_addibe
, { 0x37 }
537 /* div $dstbe,$srcbe */
540 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
541 & ifmt_addrbe
, { 0x3f }
543 /* div32 $dstbe,$imm32 */
546 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
547 & ifmt_addibe
, { 0x34 }
549 /* div32 $dstbe,$srcbe */
552 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
553 & ifmt_addrbe
, { 0x3c }
555 /* or $dstbe,$imm32 */
558 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
559 & ifmt_addibe
, { 0x47 }
561 /* or $dstbe,$srcbe */
564 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
565 & ifmt_addrbe
, { 0x4f }
567 /* or32 $dstbe,$imm32 */
570 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
571 & ifmt_addibe
, { 0x44 }
573 /* or32 $dstbe,$srcbe */
576 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
577 & ifmt_addrbe
, { 0x4c }
579 /* and $dstbe,$imm32 */
582 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
583 & ifmt_addibe
, { 0x57 }
585 /* and $dstbe,$srcbe */
588 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
589 & ifmt_addrbe
, { 0x5f }
591 /* and32 $dstbe,$imm32 */
594 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
595 & ifmt_addibe
, { 0x54 }
597 /* and32 $dstbe,$srcbe */
600 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
601 & ifmt_addrbe
, { 0x5c }
603 /* lsh $dstbe,$imm32 */
606 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
607 & ifmt_addibe
, { 0x67 }
609 /* lsh $dstbe,$srcbe */
612 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
613 & ifmt_addrbe
, { 0x6f }
615 /* lsh32 $dstbe,$imm32 */
618 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
619 & ifmt_addibe
, { 0x64 }
621 /* lsh32 $dstbe,$srcbe */
624 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
625 & ifmt_addrbe
, { 0x6c }
627 /* rsh $dstbe,$imm32 */
630 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
631 & ifmt_addibe
, { 0x77 }
633 /* rsh $dstbe,$srcbe */
636 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
637 & ifmt_addrbe
, { 0x7f }
639 /* rsh32 $dstbe,$imm32 */
642 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
643 & ifmt_addibe
, { 0x74 }
645 /* rsh32 $dstbe,$srcbe */
648 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
649 & ifmt_addrbe
, { 0x7c }
651 /* mod $dstbe,$imm32 */
654 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
655 & ifmt_addibe
, { 0x97 }
657 /* mod $dstbe,$srcbe */
660 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
661 & ifmt_addrbe
, { 0x9f }
663 /* mod32 $dstbe,$imm32 */
666 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
667 & ifmt_addibe
, { 0x94 }
669 /* mod32 $dstbe,$srcbe */
672 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
673 & ifmt_addrbe
, { 0x9c }
675 /* xor $dstbe,$imm32 */
678 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
679 & ifmt_addibe
, { 0xa7 }
681 /* xor $dstbe,$srcbe */
684 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
685 & ifmt_addrbe
, { 0xaf }
687 /* xor32 $dstbe,$imm32 */
690 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
691 & ifmt_addibe
, { 0xa4 }
693 /* xor32 $dstbe,$srcbe */
696 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
697 & ifmt_addrbe
, { 0xac }
699 /* mov $dstbe,$imm32 */
702 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
703 & ifmt_addibe
, { 0xb7 }
705 /* mov $dstbe,$srcbe */
708 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
709 & ifmt_addrbe
, { 0xbf }
711 /* mov32 $dstbe,$imm32 */
714 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
715 & ifmt_addibe
, { 0xb4 }
717 /* mov32 $dstbe,$srcbe */
720 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
721 & ifmt_addrbe
, { 0xbc }
723 /* arsh $dstbe,$imm32 */
726 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
727 & ifmt_addibe
, { 0xc7 }
729 /* arsh $dstbe,$srcbe */
732 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
733 & ifmt_addrbe
, { 0xcf }
735 /* arsh32 $dstbe,$imm32 */
738 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), 0 } },
739 & ifmt_addibe
, { 0xc4 }
741 /* arsh32 $dstbe,$srcbe */
744 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), 0 } },
745 & ifmt_addrbe
, { 0xcc }
750 { { MNEM
, ' ', OP (DSTBE
), 0 } },
751 & ifmt_negbe
, { 0x8f }
756 { { MNEM
, ' ', OP (DSTBE
), 0 } },
757 & ifmt_negbe
, { 0x8c }
759 /* endle $dstle,$endsize */
762 { { MNEM
, ' ', OP (DSTLE
), ',', OP (ENDSIZE
), 0 } },
763 & ifmt_endlele
, { 0xd4 }
765 /* endbe $dstle,$endsize */
768 { { MNEM
, ' ', OP (DSTLE
), ',', OP (ENDSIZE
), 0 } },
769 & ifmt_endlele
, { 0xdc }
771 /* endle $dstbe,$endsize */
774 { { MNEM
, ' ', OP (DSTBE
), ',', OP (ENDSIZE
), 0 } },
775 & ifmt_endlebe
, { 0xd4 }
777 /* endbe $dstbe,$endsize */
780 { { MNEM
, ' ', OP (DSTBE
), ',', OP (ENDSIZE
), 0 } },
781 & ifmt_endlebe
, { 0xdc }
783 /* lddw $dstle,$imm64 */
786 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM64
), 0 } },
787 & ifmt_lddwle
, { 0x18 }
789 /* lddw $dstbe,$imm64 */
792 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM64
), 0 } },
793 & ifmt_lddwbe
, { 0x18 }
795 /* ldabsw $dstle,$srcle,$imm32 */
798 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (IMM32
), 0 } },
799 & ifmt_ldabswle
, { 0x20 }
801 /* ldabsh $dstle,$srcle,$imm32 */
804 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (IMM32
), 0 } },
805 & ifmt_ldabswle
, { 0x28 }
807 /* ldabsb $dstle,$srcle,$imm32 */
810 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (IMM32
), 0 } },
811 & ifmt_ldabswle
, { 0x30 }
813 /* ldabsdw $dstle,$srcle,$imm32 */
816 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (IMM32
), 0 } },
817 & ifmt_ldabswle
, { 0x38 }
819 /* ldindw $dstle,$srcle,$imm32 */
822 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (IMM32
), 0 } },
823 & ifmt_ldabswle
, { 0x40 }
825 /* ldindh $dstle,$srcle,$imm32 */
828 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (IMM32
), 0 } },
829 & ifmt_ldabswle
, { 0x48 }
831 /* ldindb $dstle,$srcle,$imm32 */
834 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (IMM32
), 0 } },
835 & ifmt_ldabswle
, { 0x50 }
837 /* ldinddw $dstle,$srcle,$imm32 */
840 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (IMM32
), 0 } },
841 & ifmt_ldabswle
, { 0x58 }
843 /* ldabsw $dstbe,$srcbe,$imm32 */
846 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (IMM32
), 0 } },
847 & ifmt_ldabswbe
, { 0x20 }
849 /* ldabsh $dstbe,$srcbe,$imm32 */
852 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (IMM32
), 0 } },
853 & ifmt_ldabswbe
, { 0x28 }
855 /* ldabsb $dstbe,$srcbe,$imm32 */
858 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (IMM32
), 0 } },
859 & ifmt_ldabswbe
, { 0x30 }
861 /* ldabsdw $dstbe,$srcbe,$imm32 */
864 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (IMM32
), 0 } },
865 & ifmt_ldabswbe
, { 0x38 }
867 /* ldindw $dstbe,$srcbe,$imm32 */
870 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (IMM32
), 0 } },
871 & ifmt_ldabswbe
, { 0x40 }
873 /* ldindh $dstbe,$srcbe,$imm32 */
876 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (IMM32
), 0 } },
877 & ifmt_ldabswbe
, { 0x48 }
879 /* ldindb $dstbe,$srcbe,$imm32 */
882 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (IMM32
), 0 } },
883 & ifmt_ldabswbe
, { 0x50 }
885 /* ldinddw $dstbe,$srcbe,$imm32 */
888 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (IMM32
), 0 } },
889 & ifmt_ldabswbe
, { 0x58 }
891 /* ldxw $dstle,[$srcle+$offset16] */
894 { { MNEM
, ' ', OP (DSTLE
), ',', '[', OP (SRCLE
), '+', OP (OFFSET16
), ']', 0 } },
895 & ifmt_ldxwle
, { 0x61 }
897 /* ldxh $dstle,[$srcle+$offset16] */
900 { { MNEM
, ' ', OP (DSTLE
), ',', '[', OP (SRCLE
), '+', OP (OFFSET16
), ']', 0 } },
901 & ifmt_ldxwle
, { 0x69 }
903 /* ldxb $dstle,[$srcle+$offset16] */
906 { { MNEM
, ' ', OP (DSTLE
), ',', '[', OP (SRCLE
), '+', OP (OFFSET16
), ']', 0 } },
907 & ifmt_ldxwle
, { 0x71 }
909 /* ldxdw $dstle,[$srcle+$offset16] */
912 { { MNEM
, ' ', OP (DSTLE
), ',', '[', OP (SRCLE
), '+', OP (OFFSET16
), ']', 0 } },
913 & ifmt_ldxwle
, { 0x79 }
915 /* stxw [$dstle+$offset16],$srcle */
918 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (SRCLE
), 0 } },
919 & ifmt_ldxwle
, { 0x63 }
921 /* stxh [$dstle+$offset16],$srcle */
924 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (SRCLE
), 0 } },
925 & ifmt_ldxwle
, { 0x6b }
927 /* stxb [$dstle+$offset16],$srcle */
930 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (SRCLE
), 0 } },
931 & ifmt_ldxwle
, { 0x73 }
933 /* stxdw [$dstle+$offset16],$srcle */
936 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (SRCLE
), 0 } },
937 & ifmt_ldxwle
, { 0x7b }
939 /* ldxw $dstbe,[$srcbe+$offset16] */
942 { { MNEM
, ' ', OP (DSTBE
), ',', '[', OP (SRCBE
), '+', OP (OFFSET16
), ']', 0 } },
943 & ifmt_ldxwbe
, { 0x61 }
945 /* ldxh $dstbe,[$srcbe+$offset16] */
948 { { MNEM
, ' ', OP (DSTBE
), ',', '[', OP (SRCBE
), '+', OP (OFFSET16
), ']', 0 } },
949 & ifmt_ldxwbe
, { 0x69 }
951 /* ldxb $dstbe,[$srcbe+$offset16] */
954 { { MNEM
, ' ', OP (DSTBE
), ',', '[', OP (SRCBE
), '+', OP (OFFSET16
), ']', 0 } },
955 & ifmt_ldxwbe
, { 0x71 }
957 /* ldxdw $dstbe,[$srcbe+$offset16] */
960 { { MNEM
, ' ', OP (DSTBE
), ',', '[', OP (SRCBE
), '+', OP (OFFSET16
), ']', 0 } },
961 & ifmt_ldxwbe
, { 0x79 }
963 /* stxw [$dstbe+$offset16],$srcbe */
966 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (SRCBE
), 0 } },
967 & ifmt_ldxwbe
, { 0x63 }
969 /* stxh [$dstbe+$offset16],$srcbe */
972 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (SRCBE
), 0 } },
973 & ifmt_ldxwbe
, { 0x6b }
975 /* stxb [$dstbe+$offset16],$srcbe */
978 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (SRCBE
), 0 } },
979 & ifmt_ldxwbe
, { 0x73 }
981 /* stxdw [$dstbe+$offset16],$srcbe */
984 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (SRCBE
), 0 } },
985 & ifmt_ldxwbe
, { 0x7b }
987 /* stb [$dstle+$offset16],$imm32 */
990 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (IMM32
), 0 } },
991 & ifmt_stble
, { 0x72 }
993 /* sth [$dstle+$offset16],$imm32 */
996 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (IMM32
), 0 } },
997 & ifmt_stble
, { 0x6a }
999 /* stw [$dstle+$offset16],$imm32 */
1002 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (IMM32
), 0 } },
1003 & ifmt_stble
, { 0x62 }
1005 /* stdw [$dstle+$offset16],$imm32 */
1008 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (IMM32
), 0 } },
1009 & ifmt_stble
, { 0x7a }
1011 /* stb [$dstbe+$offset16],$imm32 */
1014 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (IMM32
), 0 } },
1015 & ifmt_stbbe
, { 0x72 }
1017 /* sth [$dstbe+$offset16],$imm32 */
1020 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (IMM32
), 0 } },
1021 & ifmt_stbbe
, { 0x6a }
1023 /* stw [$dstbe+$offset16],$imm32 */
1026 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (IMM32
), 0 } },
1027 & ifmt_stbbe
, { 0x62 }
1029 /* stdw [$dstbe+$offset16],$imm32 */
1032 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (IMM32
), 0 } },
1033 & ifmt_stbbe
, { 0x7a }
1035 /* jeq $dstle,$imm32,$disp16 */
1038 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1039 & ifmt_jeqile
, { 0x15 }
1041 /* jeq $dstle,$srcle,$disp16 */
1044 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1045 & ifmt_jeqrle
, { 0x1d }
1047 /* jgt $dstle,$imm32,$disp16 */
1050 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1051 & ifmt_jeqile
, { 0x25 }
1053 /* jgt $dstle,$srcle,$disp16 */
1056 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1057 & ifmt_jeqrle
, { 0x2d }
1059 /* jge $dstle,$imm32,$disp16 */
1062 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1063 & ifmt_jeqile
, { 0x35 }
1065 /* jge $dstle,$srcle,$disp16 */
1068 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1069 & ifmt_jeqrle
, { 0x3d }
1071 /* jlt $dstle,$imm32,$disp16 */
1074 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1075 & ifmt_jeqile
, { 0xa5 }
1077 /* jlt $dstle,$srcle,$disp16 */
1080 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1081 & ifmt_jeqrle
, { 0xad }
1083 /* jle $dstle,$imm32,$disp16 */
1086 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1087 & ifmt_jeqile
, { 0xb5 }
1089 /* jle $dstle,$srcle,$disp16 */
1092 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1093 & ifmt_jeqrle
, { 0xbd }
1095 /* jset $dstle,$imm32,$disp16 */
1098 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1099 & ifmt_jeqile
, { 0x45 }
1101 /* jset $dstle,$srcle,$disp16 */
1104 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1105 & ifmt_jeqrle
, { 0x4d }
1107 /* jne $dstle,$imm32,$disp16 */
1110 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1111 & ifmt_jeqile
, { 0x55 }
1113 /* jne $dstle,$srcle,$disp16 */
1116 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1117 & ifmt_jeqrle
, { 0x5d }
1119 /* jsgt $dstle,$imm32,$disp16 */
1122 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1123 & ifmt_jeqile
, { 0x65 }
1125 /* jsgt $dstle,$srcle,$disp16 */
1128 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1129 & ifmt_jeqrle
, { 0x6d }
1131 /* jsge $dstle,$imm32,$disp16 */
1134 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1135 & ifmt_jeqile
, { 0x75 }
1137 /* jsge $dstle,$srcle,$disp16 */
1140 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1141 & ifmt_jeqrle
, { 0x7d }
1143 /* jslt $dstle,$imm32,$disp16 */
1146 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1147 & ifmt_jeqile
, { 0xc5 }
1149 /* jslt $dstle,$srcle,$disp16 */
1152 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1153 & ifmt_jeqrle
, { 0xcd }
1155 /* jsle $dstle,$imm32,$disp16 */
1158 { { MNEM
, ' ', OP (DSTLE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1159 & ifmt_jeqile
, { 0xd5 }
1161 /* jsle $dstle,$srcle,$disp16 */
1164 { { MNEM
, ' ', OP (DSTLE
), ',', OP (SRCLE
), ',', OP (DISP16
), 0 } },
1165 & ifmt_jeqrle
, { 0xdd }
1167 /* jeq $dstbe,$imm32,$disp16 */
1170 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1171 & ifmt_jeqibe
, { 0x15 }
1173 /* jeq $dstbe,$srcbe,$disp16 */
1176 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1177 & ifmt_jeqrbe
, { 0x1d }
1179 /* jgt $dstbe,$imm32,$disp16 */
1182 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1183 & ifmt_jeqibe
, { 0x25 }
1185 /* jgt $dstbe,$srcbe,$disp16 */
1188 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1189 & ifmt_jeqrbe
, { 0x2d }
1191 /* jge $dstbe,$imm32,$disp16 */
1194 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1195 & ifmt_jeqibe
, { 0x35 }
1197 /* jge $dstbe,$srcbe,$disp16 */
1200 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1201 & ifmt_jeqrbe
, { 0x3d }
1203 /* jlt $dstbe,$imm32,$disp16 */
1206 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1207 & ifmt_jeqibe
, { 0xa5 }
1209 /* jlt $dstbe,$srcbe,$disp16 */
1212 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1213 & ifmt_jeqrbe
, { 0xad }
1215 /* jle $dstbe,$imm32,$disp16 */
1218 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1219 & ifmt_jeqibe
, { 0xb5 }
1221 /* jle $dstbe,$srcbe,$disp16 */
1224 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1225 & ifmt_jeqrbe
, { 0xbd }
1227 /* jset $dstbe,$imm32,$disp16 */
1230 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1231 & ifmt_jeqibe
, { 0x45 }
1233 /* jset $dstbe,$srcbe,$disp16 */
1236 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1237 & ifmt_jeqrbe
, { 0x4d }
1239 /* jne $dstbe,$imm32,$disp16 */
1242 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1243 & ifmt_jeqibe
, { 0x55 }
1245 /* jne $dstbe,$srcbe,$disp16 */
1248 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1249 & ifmt_jeqrbe
, { 0x5d }
1251 /* jsgt $dstbe,$imm32,$disp16 */
1254 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1255 & ifmt_jeqibe
, { 0x65 }
1257 /* jsgt $dstbe,$srcbe,$disp16 */
1260 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1261 & ifmt_jeqrbe
, { 0x6d }
1263 /* jsge $dstbe,$imm32,$disp16 */
1266 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1267 & ifmt_jeqibe
, { 0x75 }
1269 /* jsge $dstbe,$srcbe,$disp16 */
1272 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1273 & ifmt_jeqrbe
, { 0x7d }
1275 /* jslt $dstbe,$imm32,$disp16 */
1278 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1279 & ifmt_jeqibe
, { 0xc5 }
1281 /* jslt $dstbe,$srcbe,$disp16 */
1284 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1285 & ifmt_jeqrbe
, { 0xcd }
1287 /* jsle $dstbe,$imm32,$disp16 */
1290 { { MNEM
, ' ', OP (DSTBE
), ',', OP (IMM32
), ',', OP (DISP16
), 0 } },
1291 & ifmt_jeqibe
, { 0xd5 }
1293 /* jsle $dstbe,$srcbe,$disp16 */
1296 { { MNEM
, ' ', OP (DSTBE
), ',', OP (SRCBE
), ',', OP (DISP16
), 0 } },
1297 & ifmt_jeqrbe
, { 0xdd }
1302 { { MNEM
, ' ', OP (DISP16
), 0 } },
1308 { { MNEM
, ' ', OP (DISP32
), 0 } },
1309 & ifmt_call
, { 0x85 }
1315 & ifmt_exit
, { 0x95 }
1317 /* xadddw [$dstle+$offset16],$srcle */
1320 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (SRCLE
), 0 } },
1321 & ifmt_ldxwle
, { 0xdb }
1323 /* xaddw [$dstle+$offset16],$srcle */
1326 { { MNEM
, ' ', '[', OP (DSTLE
), '+', OP (OFFSET16
), ']', ',', OP (SRCLE
), 0 } },
1327 & ifmt_ldxwle
, { 0xc3 }
1329 /* xadddw [$dstbe+$offset16],$srcbe */
1332 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (SRCBE
), 0 } },
1333 & ifmt_ldxwbe
, { 0xdb }
1335 /* xaddw [$dstbe+$offset16],$srcbe */
1338 { { MNEM
, ' ', '[', OP (DSTBE
), '+', OP (OFFSET16
), ']', ',', OP (SRCBE
), 0 } },
1339 & ifmt_ldxwbe
, { 0xc3 }
1348 /* Formats for ALIAS macro-insns. */
1350 #define F(f) & bpf_cgen_ifld_table[BPF_##f]
1353 /* Each non-simple macro entry points to an array of expansion possibilities. */
1355 #define A(a) (1 << CGEN_INSN_##a)
1356 #define OPERAND(op) BPF_OPERAND_##op
1357 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1358 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1360 /* The macro instruction table. */
1362 static const CGEN_IBASE bpf_cgen_macro_insn_table
[] =
1366 /* The macro instruction opcode table. */
1368 static const CGEN_OPCODE bpf_cgen_macro_insn_opcode_table
[] =
1377 #ifndef CGEN_ASM_HASH_P
1378 #define CGEN_ASM_HASH_P(insn) 1
1381 #ifndef CGEN_DIS_HASH_P
1382 #define CGEN_DIS_HASH_P(insn) 1
1385 /* Return non-zero if INSN is to be added to the hash table.
1386 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
1389 asm_hash_insn_p (const CGEN_INSN
*insn ATTRIBUTE_UNUSED
)
1391 return CGEN_ASM_HASH_P (insn
);
1395 dis_hash_insn_p (const CGEN_INSN
*insn
)
1397 /* If building the hash table and the NO-DIS attribute is present,
1399 if (CGEN_INSN_ATTR_VALUE (insn
, CGEN_INSN_NO_DIS
))
1401 return CGEN_DIS_HASH_P (insn
);
1404 #ifndef CGEN_ASM_HASH
1405 #define CGEN_ASM_HASH_SIZE 127
1406 #ifdef CGEN_MNEMONIC_OPERANDS
1407 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
1409 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
1413 /* It doesn't make much sense to provide a default here,
1414 but while this is under development we do.
1415 BUFFER is a pointer to the bytes of the insn, target order.
1416 VALUE is the first base_insn_bitsize bits as an int in host order. */
1418 #ifndef CGEN_DIS_HASH
1419 #define CGEN_DIS_HASH_SIZE 256
1420 #define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
1423 /* The result is the hash value of the insn.
1424 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
1427 asm_hash_insn (const char *mnem
)
1429 return CGEN_ASM_HASH (mnem
);
1432 /* BUF is a pointer to the bytes of the insn, target order.
1433 VALUE is the first base_insn_bitsize bits as an int in host order. */
1436 dis_hash_insn (const char *buf ATTRIBUTE_UNUSED
,
1437 CGEN_INSN_INT value ATTRIBUTE_UNUSED
)
1439 return CGEN_DIS_HASH (buf
, value
);
1442 /* Set the recorded length of the insn in the CGEN_FIELDS struct. */
1445 set_fields_bitsize (CGEN_FIELDS
*fields
, int size
)
1447 CGEN_FIELDS_BITSIZE (fields
) = size
;
1450 /* Function to call before using the operand instance table.
1451 This plugs the opcode entries and macro instructions into the cpu table. */
1454 bpf_cgen_init_opcode_table (CGEN_CPU_DESC cd
)
1457 int num_macros
= (sizeof (bpf_cgen_macro_insn_table
) /
1458 sizeof (bpf_cgen_macro_insn_table
[0]));
1459 const CGEN_IBASE
*ib
= & bpf_cgen_macro_insn_table
[0];
1460 const CGEN_OPCODE
*oc
= & bpf_cgen_macro_insn_opcode_table
[0];
1461 CGEN_INSN
*insns
= xmalloc (num_macros
* sizeof (CGEN_INSN
));
1463 /* This test has been added to avoid a warning generated
1464 if memset is called with a third argument of value zero. */
1465 if (num_macros
>= 1)
1466 memset (insns
, 0, num_macros
* sizeof (CGEN_INSN
));
1467 for (i
= 0; i
< num_macros
; ++i
)
1469 insns
[i
].base
= &ib
[i
];
1470 insns
[i
].opcode
= &oc
[i
];
1471 bpf_cgen_build_insn_regex (& insns
[i
]);
1473 cd
->macro_insn_table
.init_entries
= insns
;
1474 cd
->macro_insn_table
.entry_size
= sizeof (CGEN_IBASE
);
1475 cd
->macro_insn_table
.num_init_entries
= num_macros
;
1477 oc
= & bpf_cgen_insn_opcode_table
[0];
1478 insns
= (CGEN_INSN
*) cd
->insn_table
.init_entries
;
1479 for (i
= 0; i
< MAX_INSNS
; ++i
)
1481 insns
[i
].opcode
= &oc
[i
];
1482 bpf_cgen_build_insn_regex (& insns
[i
]);
1485 cd
->sizeof_fields
= sizeof (CGEN_FIELDS
);
1486 cd
->set_fields_bitsize
= set_fields_bitsize
;
1488 cd
->asm_hash_p
= asm_hash_insn_p
;
1489 cd
->asm_hash
= asm_hash_insn
;
1490 cd
->asm_hash_size
= CGEN_ASM_HASH_SIZE
;
1492 cd
->dis_hash_p
= dis_hash_insn_p
;
1493 cd
->dis_hash
= dis_hash_insn
;
1494 cd
->dis_hash_size
= CGEN_DIS_HASH_SIZE
;